1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver
4 //
5 // Copyright(c) 2021 Realtek Semiconductor Corp.
6 //
7 //
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <sound/core.h>
15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/sdw.h>
18 #include <sound/soc-dapm.h>
19 #include <sound/initval.h>
20 #include "rt1316-sdw.h"
21
22 static const struct reg_default rt1316_reg_defaults[] = {
23 { 0x3004, 0x00 },
24 { 0x3005, 0x00 },
25 { 0x3206, 0x00 },
26 { 0xc001, 0x00 },
27 { 0xc002, 0x00 },
28 { 0xc003, 0x00 },
29 { 0xc004, 0x00 },
30 { 0xc005, 0x00 },
31 { 0xc006, 0x00 },
32 { 0xc007, 0x00 },
33 { 0xc008, 0x00 },
34 { 0xc009, 0x00 },
35 { 0xc00a, 0x00 },
36 { 0xc00b, 0x00 },
37 { 0xc00c, 0x00 },
38 { 0xc00d, 0x00 },
39 { 0xc00e, 0x00 },
40 { 0xc00f, 0x00 },
41 { 0xc010, 0xa5 },
42 { 0xc011, 0x00 },
43 { 0xc012, 0xff },
44 { 0xc013, 0xff },
45 { 0xc014, 0x40 },
46 { 0xc015, 0x00 },
47 { 0xc016, 0x00 },
48 { 0xc017, 0x00 },
49 { 0xc605, 0x30 },
50 { 0xc700, 0x0a },
51 { 0xc701, 0xaa },
52 { 0xc702, 0x1a },
53 { 0xc703, 0x0a },
54 { 0xc710, 0x80 },
55 { 0xc711, 0x00 },
56 { 0xc712, 0x3e },
57 { 0xc713, 0x80 },
58 { 0xc714, 0x80 },
59 { 0xc715, 0x06 },
60 { 0xd101, 0x00 },
61 { 0xd102, 0x30 },
62 { 0xd103, 0x00 },
63 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
64 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
65 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
66 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 },
67 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
68 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
69 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
70 };
71
72 static const struct reg_sequence rt1316_blind_write[] = {
73 { 0xc710, 0x17 },
74 { 0xc711, 0x80 },
75 { 0xc712, 0x26 },
76 { 0xc713, 0x06 },
77 { 0xc714, 0x80 },
78 { 0xc715, 0x06 },
79 { 0xc702, 0x0a },
80 { 0xc703, 0x0a },
81 { 0xc001, 0x45 },
82 { 0xc003, 0x00 },
83 { 0xc004, 0x11 },
84 { 0xc005, 0x00 },
85 { 0xc006, 0x00 },
86 { 0xc106, 0x00 },
87 { 0xc007, 0x11 },
88 { 0xc008, 0x11 },
89 { 0xc009, 0x00 },
90
91 { 0x2f0a, 0x00 },
92 { 0xd101, 0xf0 },
93 { 0xd103, 0x9b },
94 { 0x2f36, 0x8e },
95 { 0x3206, 0x80 },
96 { 0x3211, 0x0b },
97 { 0x3216, 0x06 },
98 { 0xc614, 0x20 },
99 { 0xc615, 0x0a },
100 { 0xc616, 0x02 },
101 { 0xc617, 0x00 },
102 { 0xc60b, 0x10 },
103 { 0xc60e, 0x05 },
104 { 0xc102, 0x00 },
105 { 0xc090, 0xb0 },
106 { 0xc00f, 0x01 },
107 { 0xc09c, 0x7b },
108
109 { 0xc602, 0x07 },
110 { 0xc603, 0x07 },
111 { 0xc0a3, 0x71 },
112 { 0xc00b, 0x30 },
113 { 0xc093, 0x80 },
114 { 0xc09d, 0x80 },
115 { 0xc0b0, 0x77 },
116 { 0xc010, 0xa5 },
117 { 0xc050, 0x83 },
118 { 0x2f55, 0x03 },
119 { 0x3217, 0xb5 },
120 { 0x3202, 0x02 },
121
122 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 },
123
124 /* for IV sense */
125 { 0x2232, 0x80 },
126 { 0xc0b0, 0x77 },
127 { 0xc011, 0x00 },
128 { 0xc020, 0x00 },
129 { 0xc023, 0x00 },
130 { 0x3101, 0x00 },
131 { 0x3004, 0xa0 },
132 { 0x3005, 0xb1 },
133 { 0xc007, 0x11 },
134 { 0xc008, 0x11 },
135 { 0xc009, 0x00 },
136 { 0xc022, 0xd6 },
137 { 0xc025, 0xd6 },
138
139 { 0xd001, 0x03 },
140 { 0xd002, 0xbf },
141 { 0xd003, 0x03 },
142 { 0xd004, 0xbf },
143 };
144
rt1316_readable_register(struct device * dev,unsigned int reg)145 static bool rt1316_readable_register(struct device *dev, unsigned int reg)
146 {
147 switch (reg) {
148 case 0x2f0a:
149 case 0x2f36:
150 case 0x3203 ... 0x320e:
151 case 0xc000 ... 0xc7b4:
152 case 0xcf00 ... 0xcf03:
153 case 0xd101 ... 0xd103:
154 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0):
155 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L):
156 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R):
157 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
158 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
159 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
160 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
161 return true;
162 default:
163 return false;
164 }
165 }
166
rt1316_volatile_register(struct device * dev,unsigned int reg)167 static bool rt1316_volatile_register(struct device *dev, unsigned int reg)
168 {
169 switch (reg) {
170 case 0xc000:
171 case 0xc093:
172 case 0xc09d:
173 case 0xc0a3:
174 case 0xc201:
175 case 0xc427 ... 0xc428:
176 case 0xd102:
177 return true;
178 default:
179 return false;
180 }
181 }
182
183 static const struct regmap_config rt1316_sdw_regmap = {
184 .reg_bits = 32,
185 .val_bits = 8,
186 .readable_reg = rt1316_readable_register,
187 .volatile_reg = rt1316_volatile_register,
188 .max_register = 0x4108ffff,
189 .reg_defaults = rt1316_reg_defaults,
190 .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults),
191 .cache_type = REGCACHE_MAPLE,
192 .use_single_read = true,
193 .use_single_write = true,
194 };
195
rt1316_read_prop(struct sdw_slave * slave)196 static int rt1316_read_prop(struct sdw_slave *slave)
197 {
198 struct sdw_slave_prop *prop = &slave->prop;
199 int nval;
200 int i, j;
201 u32 bit;
202 unsigned long addr;
203 struct sdw_dpn_prop *dpn;
204
205 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
206 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
207
208 prop->paging_support = true;
209
210 /* first we need to allocate memory for set bits in port lists */
211 prop->source_ports = 0x04; /* BITMAP: 00000100 */
212 prop->sink_ports = 0x2; /* BITMAP: 00000010 */
213
214 nval = hweight32(prop->source_ports);
215 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
216 sizeof(*prop->src_dpn_prop), GFP_KERNEL);
217 if (!prop->src_dpn_prop)
218 return -ENOMEM;
219
220 i = 0;
221 dpn = prop->src_dpn_prop;
222 addr = prop->source_ports;
223 for_each_set_bit(bit, &addr, 32) {
224 dpn[i].num = bit;
225 dpn[i].type = SDW_DPN_FULL;
226 dpn[i].simple_ch_prep_sm = true;
227 dpn[i].ch_prep_timeout = 10;
228 i++;
229 }
230
231 /* do this again for sink now */
232 nval = hweight32(prop->sink_ports);
233 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
234 sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
235 if (!prop->sink_dpn_prop)
236 return -ENOMEM;
237
238 j = 0;
239 dpn = prop->sink_dpn_prop;
240 addr = prop->sink_ports;
241 for_each_set_bit(bit, &addr, 32) {
242 dpn[j].num = bit;
243 dpn[j].type = SDW_DPN_FULL;
244 dpn[j].simple_ch_prep_sm = true;
245 dpn[j].ch_prep_timeout = 10;
246 j++;
247 }
248
249 /* set the timeout values */
250 prop->clk_stop_timeout = 20;
251
252 dev_dbg(&slave->dev, "%s\n", __func__);
253
254 return 0;
255 }
256
rt1316_apply_bq_params(struct rt1316_sdw_priv * rt1316)257 static void rt1316_apply_bq_params(struct rt1316_sdw_priv *rt1316)
258 {
259 unsigned int i, reg, data;
260
261 for (i = 0; i < rt1316->bq_params_cnt; i += 3) {
262 reg = rt1316->bq_params[i] | (rt1316->bq_params[i + 1] << 8);
263 data = rt1316->bq_params[i + 2];
264 regmap_write(rt1316->regmap, reg, data);
265 }
266 }
267
rt1316_io_init(struct device * dev,struct sdw_slave * slave)268 static int rt1316_io_init(struct device *dev, struct sdw_slave *slave)
269 {
270 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
271
272 if (rt1316->hw_init)
273 return 0;
274
275 regcache_cache_only(rt1316->regmap, false);
276 if (rt1316->first_hw_init) {
277 regcache_cache_bypass(rt1316->regmap, true);
278 } else {
279 /*
280 * PM runtime status is marked as 'active' only when a Slave reports as Attached
281 */
282
283 /* update count of parent 'active' children */
284 pm_runtime_set_active(&slave->dev);
285 }
286
287 pm_runtime_get_noresume(&slave->dev);
288
289 /* sw reset */
290 regmap_write(rt1316->regmap, 0xc000, 0x02);
291
292 /* initial settings - blind write */
293 regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write,
294 ARRAY_SIZE(rt1316_blind_write));
295
296 if (rt1316->first_hw_init) {
297 regcache_cache_bypass(rt1316->regmap, false);
298 regcache_mark_dirty(rt1316->regmap);
299 } else
300 rt1316->first_hw_init = true;
301
302 /* Mark Slave initialization complete */
303 rt1316->hw_init = true;
304
305 pm_runtime_put_autosuspend(&slave->dev);
306
307 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
308 return 0;
309 }
310
rt1316_update_status(struct sdw_slave * slave,enum sdw_slave_status status)311 static int rt1316_update_status(struct sdw_slave *slave,
312 enum sdw_slave_status status)
313 {
314 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev);
315
316 if (status == SDW_SLAVE_UNATTACHED)
317 rt1316->hw_init = false;
318
319 /*
320 * Perform initialization only if slave status is present and
321 * hw_init flag is false
322 */
323 if (rt1316->hw_init || status != SDW_SLAVE_ATTACHED)
324 return 0;
325
326 /* perform I/O transfers required for Slave initialization */
327 return rt1316_io_init(&slave->dev, slave);
328 }
329
rt1316_classd_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)330 static int rt1316_classd_event(struct snd_soc_dapm_widget *w,
331 struct snd_kcontrol *kcontrol, int event)
332 {
333 struct snd_soc_component *component =
334 snd_soc_dapm_to_component(w->dapm);
335 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
336 unsigned char ps0 = 0x0, ps3 = 0x3;
337
338 switch (event) {
339 case SND_SOC_DAPM_POST_PMU:
340 regmap_write(rt1316->regmap,
341 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
342 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
343 ps0);
344 regmap_write(rt1316->regmap,
345 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
346 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
347 ps0);
348 regmap_write(rt1316->regmap,
349 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
350 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
351 ps0);
352 break;
353 case SND_SOC_DAPM_PRE_PMD:
354 regmap_write(rt1316->regmap,
355 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
356 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
357 ps3);
358 regmap_write(rt1316->regmap,
359 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
360 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
361 ps3);
362 regmap_write(rt1316->regmap,
363 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
364 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
365 ps3);
366 break;
367
368 default:
369 break;
370 }
371
372 return 0;
373 }
374
rt1316_pde24_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)375 static int rt1316_pde24_event(struct snd_soc_dapm_widget *w,
376 struct snd_kcontrol *kcontrol, int event)
377 {
378 struct snd_soc_component *component =
379 snd_soc_dapm_to_component(w->dapm);
380 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
381 unsigned char ps0 = 0x0, ps3 = 0x3;
382
383 switch (event) {
384 case SND_SOC_DAPM_POST_PMU:
385 regmap_write(rt1316->regmap,
386 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
387 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
388 ps0);
389 break;
390 case SND_SOC_DAPM_PRE_PMD:
391 regmap_write(rt1316->regmap,
392 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
393 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
394 ps3);
395 break;
396 }
397 return 0;
398 }
399
400 static const char * const rt1316_rx_data_ch_select[] = {
401 "L,R",
402 "L,L",
403 "L,R",
404 "L,L+R",
405 "R,L",
406 "R,R",
407 "R,L+R",
408 "L+R,L",
409 "L+R,R",
410 "L+R,L+R",
411 };
412
413 static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum,
414 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
415 rt1316_rx_data_ch_select);
416
417 static const char * const rt1316_dac_output_vol_select[] = {
418 "immediately",
419 "zero crossing",
420 "zero crossing with soft ramp",
421 };
422
423 static SOC_ENUM_SINGLE_DECL(rt1316_dac_vol_ctl_enum,
424 0xc010, 6, rt1316_dac_output_vol_select);
425
426 static const struct snd_kcontrol_new rt1316_snd_controls[] = {
427
428 /* I2S Data Channel Selection */
429 SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum),
430
431 /* XU24 Bypass Control */
432 SOC_SINGLE("XU24 Bypass Switch",
433 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0),
434
435 /* Left/Right IV tag */
436 SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0),
437 SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0),
438 SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0),
439 SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0),
440
441 /* IV mixer Control */
442 SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1),
443 SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1),
444
445 /* DAC Output Volume Control */
446 SOC_ENUM("DAC Output Vol Control", rt1316_dac_vol_ctl_enum),
447 };
448
449 static const struct snd_kcontrol_new rt1316_sto_dac =
450 SOC_DAPM_DOUBLE_R("Switch",
451 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L),
452 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R),
453 0, 1, 1);
454
455 static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = {
456 /* Audio Interface */
457 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
458 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
459
460 /* Digital Interface */
461 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac),
462
463 /* Output Lines */
464 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
465 rt1316_classd_event,
466 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
467 SND_SOC_DAPM_OUTPUT("SPOL"),
468 SND_SOC_DAPM_OUTPUT("SPOR"),
469
470 SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0,
471 rt1316_pde24_event,
472 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
473 SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
474 SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
475 SND_SOC_DAPM_SIGGEN("I Gen"),
476 SND_SOC_DAPM_SIGGEN("V Gen"),
477 };
478
479 static const struct snd_soc_dapm_route rt1316_dapm_routes[] = {
480 { "DAC", "Switch", "DP1RX" },
481 { "CLASS D", NULL, "DAC" },
482 { "SPOL", NULL, "CLASS D" },
483 { "SPOR", NULL, "CLASS D" },
484
485 { "I Sense", NULL, "I Gen" },
486 { "V Sense", NULL, "V Gen" },
487 { "I Sense", NULL, "PDE 24" },
488 { "V Sense", NULL, "PDE 24" },
489 { "DP2TX", NULL, "I Sense" },
490 { "DP2TX", NULL, "V Sense" },
491 };
492
rt1316_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)493 static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
494 int direction)
495 {
496 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
497
498 return 0;
499 }
500
rt1316_sdw_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)501 static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream,
502 struct snd_soc_dai *dai)
503 {
504 snd_soc_dai_set_dma_data(dai, substream, NULL);
505 }
506
rt1316_sdw_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)507 static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream,
508 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
509 {
510 struct snd_soc_component *component = dai->component;
511 struct rt1316_sdw_priv *rt1316 =
512 snd_soc_component_get_drvdata(component);
513 struct sdw_stream_config stream_config = {0};
514 struct sdw_port_config port_config = {0};
515 struct sdw_stream_runtime *sdw_stream;
516 int retval;
517
518 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
519 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
520
521 if (!sdw_stream)
522 return -EINVAL;
523
524 if (!rt1316->sdw_slave)
525 return -EINVAL;
526
527 /* SoundWire specific configuration */
528 snd_sdw_params_to_config(substream, params, &stream_config, &port_config);
529
530 /* port 1 for playback */
531 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
532 port_config.num = 1;
533 else
534 port_config.num = 2;
535
536 retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config,
537 &port_config, 1, sdw_stream);
538 if (retval) {
539 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
540 return retval;
541 }
542
543 return 0;
544 }
545
rt1316_sdw_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)546 static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
547 struct snd_soc_dai *dai)
548 {
549 struct snd_soc_component *component = dai->component;
550 struct rt1316_sdw_priv *rt1316 =
551 snd_soc_component_get_drvdata(component);
552 struct sdw_stream_runtime *sdw_stream =
553 snd_soc_dai_get_dma_data(dai, substream);
554
555 if (!rt1316->sdw_slave)
556 return -EINVAL;
557
558 sdw_stream_remove_slave(rt1316->sdw_slave, sdw_stream);
559 return 0;
560 }
561
562 /*
563 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
564 * port_prep are not defined for now
565 */
566 static const struct sdw_slave_ops rt1316_slave_ops = {
567 .read_prop = rt1316_read_prop,
568 .update_status = rt1316_update_status,
569 };
570
rt1316_sdw_parse_dt(struct rt1316_sdw_priv * rt1316,struct device * dev)571 static int rt1316_sdw_parse_dt(struct rt1316_sdw_priv *rt1316, struct device *dev)
572 {
573 int ret = 0;
574
575 device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1316->bq_params_cnt);
576 if (rt1316->bq_params_cnt) {
577 rt1316->bq_params = devm_kzalloc(dev, rt1316->bq_params_cnt, GFP_KERNEL);
578 if (!rt1316->bq_params) {
579 dev_err(dev, "%s: Could not allocate bq_params memory\n", __func__);
580 ret = -ENOMEM;
581 } else {
582 ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1316->bq_params, rt1316->bq_params_cnt);
583 if (ret < 0)
584 dev_err(dev, "%s: Could not read list of realtek,bq-params\n", __func__);
585 }
586 }
587
588 dev_dbg(dev, "bq_params_cnt=%d\n", rt1316->bq_params_cnt);
589 return ret;
590 }
591
rt1316_sdw_component_probe(struct snd_soc_component * component)592 static int rt1316_sdw_component_probe(struct snd_soc_component *component)
593 {
594 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
595 int ret;
596
597 rt1316->component = component;
598 rt1316_sdw_parse_dt(rt1316, &rt1316->sdw_slave->dev);
599
600 if (!rt1316->first_hw_init)
601 return 0;
602
603 ret = pm_runtime_resume(component->dev);
604 if (ret < 0 && ret != -EACCES)
605 return ret;
606
607 /* apply BQ params */
608 rt1316_apply_bq_params(rt1316);
609
610 return 0;
611 }
612
613 static const struct snd_soc_component_driver soc_component_sdw_rt1316 = {
614 .probe = rt1316_sdw_component_probe,
615 .controls = rt1316_snd_controls,
616 .num_controls = ARRAY_SIZE(rt1316_snd_controls),
617 .dapm_widgets = rt1316_dapm_widgets,
618 .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets),
619 .dapm_routes = rt1316_dapm_routes,
620 .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes),
621 .endianness = 1,
622 };
623
624 static const struct snd_soc_dai_ops rt1316_aif_dai_ops = {
625 .hw_params = rt1316_sdw_hw_params,
626 .hw_free = rt1316_sdw_pcm_hw_free,
627 .set_stream = rt1316_set_sdw_stream,
628 .shutdown = rt1316_sdw_shutdown,
629 };
630
631 #define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000
632 #define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
633 SNDRV_PCM_FMTBIT_S24_LE)
634
635 static struct snd_soc_dai_driver rt1316_sdw_dai[] = {
636 {
637 .name = "rt1316-aif",
638 .playback = {
639 .stream_name = "DP1 Playback",
640 .channels_min = 1,
641 .channels_max = 2,
642 .rates = RT1316_STEREO_RATES,
643 .formats = RT1316_FORMATS,
644 },
645 .capture = {
646 .stream_name = "DP2 Capture",
647 .channels_min = 1,
648 .channels_max = 2,
649 .rates = RT1316_STEREO_RATES,
650 .formats = RT1316_FORMATS,
651 },
652 .ops = &rt1316_aif_dai_ops,
653 },
654 };
655
rt1316_sdw_init(struct device * dev,struct regmap * regmap,struct sdw_slave * slave)656 static int rt1316_sdw_init(struct device *dev, struct regmap *regmap,
657 struct sdw_slave *slave)
658 {
659 struct rt1316_sdw_priv *rt1316;
660 int ret;
661
662 rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL);
663 if (!rt1316)
664 return -ENOMEM;
665
666 dev_set_drvdata(dev, rt1316);
667 rt1316->sdw_slave = slave;
668 rt1316->regmap = regmap;
669
670 regcache_cache_only(rt1316->regmap, true);
671
672 /*
673 * Mark hw_init to false
674 * HW init will be performed when device reports present
675 */
676 rt1316->hw_init = false;
677 rt1316->first_hw_init = false;
678
679 ret = devm_snd_soc_register_component(dev,
680 &soc_component_sdw_rt1316,
681 rt1316_sdw_dai,
682 ARRAY_SIZE(rt1316_sdw_dai));
683 if (ret < 0)
684 return ret;
685
686 /* set autosuspend parameters */
687 pm_runtime_set_autosuspend_delay(dev, 3000);
688 pm_runtime_use_autosuspend(dev);
689
690 /* make sure the device does not suspend immediately */
691 pm_runtime_mark_last_busy(dev);
692
693 pm_runtime_enable(dev);
694
695 /* important note: the device is NOT tagged as 'active' and will remain
696 * 'suspended' until the hardware is enumerated/initialized. This is required
697 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently
698 * fail with -EACCESS because of race conditions between card creation and enumeration
699 */
700
701 dev_dbg(dev, "%s\n", __func__);
702
703 return 0;
704 }
705
rt1316_sdw_probe(struct sdw_slave * slave,const struct sdw_device_id * id)706 static int rt1316_sdw_probe(struct sdw_slave *slave,
707 const struct sdw_device_id *id)
708 {
709 struct regmap *regmap;
710
711 /* Regmap Initialization */
712 regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap);
713 if (IS_ERR(regmap))
714 return PTR_ERR(regmap);
715
716 return rt1316_sdw_init(&slave->dev, regmap, slave);
717 }
718
rt1316_sdw_remove(struct sdw_slave * slave)719 static int rt1316_sdw_remove(struct sdw_slave *slave)
720 {
721 pm_runtime_disable(&slave->dev);
722
723 return 0;
724 }
725
726 static const struct sdw_device_id rt1316_id[] = {
727 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0),
728 {},
729 };
730 MODULE_DEVICE_TABLE(sdw, rt1316_id);
731
rt1316_dev_suspend(struct device * dev)732 static int rt1316_dev_suspend(struct device *dev)
733 {
734 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
735
736 if (!rt1316->hw_init)
737 return 0;
738
739 regcache_cache_only(rt1316->regmap, true);
740
741 return 0;
742 }
743
744 #define RT1316_PROBE_TIMEOUT 5000
745
rt1316_dev_resume(struct device * dev)746 static int rt1316_dev_resume(struct device *dev)
747 {
748 struct sdw_slave *slave = dev_to_sdw_dev(dev);
749 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
750 unsigned long time;
751
752 if (!rt1316->first_hw_init)
753 return 0;
754
755 if (!slave->unattach_request)
756 goto regmap_sync;
757
758 time = wait_for_completion_timeout(&slave->initialization_complete,
759 msecs_to_jiffies(RT1316_PROBE_TIMEOUT));
760 if (!time) {
761 dev_err(&slave->dev, "%s: Initialization not complete, timed out\n", __func__);
762 sdw_show_ping_status(slave->bus, true);
763
764 return -ETIMEDOUT;
765 }
766
767 regmap_sync:
768 slave->unattach_request = 0;
769 regcache_cache_only(rt1316->regmap, false);
770 regcache_sync(rt1316->regmap);
771
772 return 0;
773 }
774
775 static const struct dev_pm_ops rt1316_pm = {
776 SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume)
777 RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL)
778 };
779
780 static struct sdw_driver rt1316_sdw_driver = {
781 .driver = {
782 .name = "rt1316-sdca",
783 .pm = pm_ptr(&rt1316_pm),
784 },
785 .probe = rt1316_sdw_probe,
786 .remove = rt1316_sdw_remove,
787 .ops = &rt1316_slave_ops,
788 .id_table = rt1316_id,
789 };
790 module_sdw_driver(rt1316_sdw_driver);
791
792 MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW");
793 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
794 MODULE_LICENSE("GPL");
795