1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2026 Marvell. 5 * 6 */ 7 8 #ifndef NPC_CN20K_H 9 #define NPC_CN20K_H 10 11 #define MKEX_CN20K_SIGN 0x19bbfdbd160 12 13 /* MAX_NUM_BANKS, MAX_SUBBANK_DEPTH and MAX_NUM_SUB_BANKS represent 14 * hard limit on all silicon variants, preventing any possibility of 15 * out-of-bounds access on matrix defined using these values. 16 */ 17 #define MAX_NUM_BANKS 2 18 #define MAX_NUM_SUB_BANKS 32 19 #define MAX_SUBBANK_DEPTH 256 20 21 /* strtoull of "mkexprof" with base:36 */ 22 #define MKEX_END_SIGN 0xdeadbeef 23 24 #define NPC_CN20K_BYTESM GENMASK_ULL(18, 16) 25 #define NPC_CN20K_PARSE_NIBBLE GENMASK_ULL(22, 0) 26 #define NPC_CN20K_TOTAL_NIBBLE 23 27 28 #define CN20K_SET_EXTR_LT(intf, extr, ltype, cfg) \ 29 rvu_write64(rvu, BLKADDR_NPC, \ 30 NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype), cfg) 31 32 #define CN20K_GET_KEX_CFG(intf) \ 33 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf)) 34 35 #define CN20K_GET_EXTR_LID(intf, extr) \ 36 rvu_read64(rvu, BLKADDR_NPC, \ 37 NPC_AF_INTFX_EXTRACTORX_CFG(intf, extr)) 38 39 #define CN20K_SET_EXTR_LT(intf, extr, ltype, cfg) \ 40 rvu_write64(rvu, BLKADDR_NPC, \ 41 NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype), cfg) 42 43 #define CN20K_GET_EXTR_LT(intf, extr, ltype) \ 44 rvu_read64(rvu, BLKADDR_NPC, \ 45 NPC_AF_INTFX_EXTRACTORX_LTX_CFG(intf, extr, ltype)) 46 47 /* NPC_PARSE_KEX_S nibble definitions for each field */ 48 #define NPC_CN20K_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0) 49 #define NPC_CN20K_PARSE_NIBBLE_ERRLEV BIT_ULL(3) 50 #define NPC_CN20K_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4) 51 #define NPC_CN20K_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6) 52 #define NPC_CN20K_PARSE_NIBBLE_LA_FLAGS BIT_ULL(7) 53 #define NPC_CN20K_PARSE_NIBBLE_LA_LTYPE BIT_ULL(8) 54 #define NPC_CN20K_PARSE_NIBBLE_LB_FLAGS BIT_ULL(9) 55 #define NPC_CN20K_PARSE_NIBBLE_LB_LTYPE BIT_ULL(10) 56 #define NPC_CN20K_PARSE_NIBBLE_LC_FLAGS BIT_ULL(11) 57 #define NPC_CN20K_PARSE_NIBBLE_LC_LTYPE BIT_ULL(12) 58 #define NPC_CN20K_PARSE_NIBBLE_LD_FLAGS BIT_ULL(13) 59 #define NPC_CN20K_PARSE_NIBBLE_LD_LTYPE BIT_ULL(14) 60 #define NPC_CN20K_PARSE_NIBBLE_LE_FLAGS BIT_ULL(15) 61 #define NPC_CN20K_PARSE_NIBBLE_LE_LTYPE BIT_ULL(16) 62 #define NPC_CN20K_PARSE_NIBBLE_LF_FLAGS BIT_ULL(17) 63 #define NPC_CN20K_PARSE_NIBBLE_LF_LTYPE BIT_ULL(18) 64 #define NPC_CN20K_PARSE_NIBBLE_LG_FLAGS BIT_ULL(19) 65 #define NPC_CN20K_PARSE_NIBBLE_LG_LTYPE BIT_ULL(20) 66 #define NPC_CN20K_PARSE_NIBBLE_LH_FLAGS BIT_ULL(21) 67 #define NPC_CN20K_PARSE_NIBBLE_LH_LTYPE BIT_ULL(22) 68 69 /* Rx parse key extract nibble enable */ 70 #define NPC_CN20K_PARSE_NIBBLE_INTF_RX (NPC_CN20K_PARSE_NIBBLE_CHAN | \ 71 NPC_CN20K_PARSE_NIBBLE_L2L3_BCAST | \ 72 NPC_CN20K_PARSE_NIBBLE_LA_LTYPE | \ 73 NPC_CN20K_PARSE_NIBBLE_LB_LTYPE | \ 74 NPC_CN20K_PARSE_NIBBLE_LC_FLAGS | \ 75 NPC_CN20K_PARSE_NIBBLE_LC_LTYPE | \ 76 NPC_CN20K_PARSE_NIBBLE_LD_LTYPE | \ 77 NPC_CN20K_PARSE_NIBBLE_LE_LTYPE) 78 79 /* Tx parse key extract nibble enable */ 80 #define NPC_CN20K_PARSE_NIBBLE_INTF_TX (NPC_CN20K_PARSE_NIBBLE_LA_LTYPE | \ 81 NPC_CN20K_PARSE_NIBBLE_LB_LTYPE | \ 82 NPC_CN20K_PARSE_NIBBLE_LC_LTYPE | \ 83 NPC_CN20K_PARSE_NIBBLE_LD_LTYPE | \ 84 NPC_CN20K_PARSE_NIBBLE_LE_LTYPE) 85 86 /** 87 * enum npc_subbank_flag - NPC subbank status 88 * 89 * subbank flag indicates whether the subbank is free 90 * or used. 91 * 92 * @NPC_SUBBANK_FLAG_UNINIT: Subbank is not initialized. 93 * @NPC_SUBBANK_FLAG_FREE: Subbank is free. 94 * @NPC_SUBBANK_FLAG_USED: Subbank is used. 95 */ 96 enum npc_subbank_flag { 97 NPC_SUBBANK_FLAG_UNINIT, 98 NPC_SUBBANK_FLAG_FREE = BIT(0), 99 NPC_SUBBANK_FLAG_USED = BIT(1), 100 }; 101 102 /** 103 * enum npc_dft_rule_id - Default rule type 104 * 105 * Mcam default rule type. 106 * 107 * @NPC_DFT_RULE_START_ID: Not used 108 * @NPC_DFT_RULE_PROMISC_ID: promiscuous rule 109 * @NPC_DFT_RULE_MCAST_ID: multicast rule 110 * @NPC_DFT_RULE_BCAST_ID: broadcast rule 111 * @NPC_DFT_RULE_UCAST_ID: unicast rule 112 * @NPC_DFT_RULE_MAX_ID: Maximum index. 113 */ 114 enum npc_dft_rule_id { 115 NPC_DFT_RULE_START_ID = 1, 116 NPC_DFT_RULE_PROMISC_ID = NPC_DFT_RULE_START_ID, 117 NPC_DFT_RULE_MCAST_ID, 118 NPC_DFT_RULE_BCAST_ID, 119 NPC_DFT_RULE_UCAST_ID, 120 NPC_DFT_RULE_MAX_ID, 121 }; 122 123 /** 124 * struct npc_subbank - Subbank fields. 125 * @b0b: Subbanks bottom index for bank0 126 * @b1b: Subbanks bottom index for bank1 127 * @b0t: Subbanks top index for bank0 128 * @b1t: Subbanks top index for bank1 129 * @flags: Subbank flags 130 * @lock: Mutex lock for flags and rsrc mofiication 131 * @b0map: Bitmap map for bank0 indexes 132 * @b1map: Bitmap map for bank1 indexes 133 * @idx: Subbank index 134 * @arr_idx: Index to the free array or used array 135 * @free_cnt: Number of free slots in the subbank. 136 * @key_type: X4 or X2 subbank. 137 * 138 * MCAM resource is divided horizontally into multiple subbanks and 139 * Resource allocation from each subbank is managed by this data 140 * structure. 141 */ 142 struct npc_subbank { 143 u16 b0t, b0b, b1t, b1b; 144 enum npc_subbank_flag flags; 145 struct mutex lock; /* Protect subbank resources */ 146 DECLARE_BITMAP(b0map, MAX_SUBBANK_DEPTH); 147 DECLARE_BITMAP(b1map, MAX_SUBBANK_DEPTH); 148 u16 idx; 149 u16 arr_idx; 150 u16 free_cnt; 151 u8 key_type; 152 }; 153 154 /** 155 * struct npc_defrag_show_node - Defragmentation show node 156 * @old_midx: Old mcam index. 157 * @new_midx: New mcam index. 158 * @vidx: Virtual index 159 * @list: Linked list of these nodes 160 * 161 * This structure holds information on last defragmentation 162 * executed on mcam resource. 163 */ 164 struct npc_defrag_show_node { 165 u16 old_midx; 166 u16 new_midx; 167 u16 vidx; 168 struct list_head list; 169 }; 170 171 /** 172 * struct npc_priv_t - NPC private structure. 173 * @bank_depth: Total entries in each bank. 174 * @num_banks: Number of banks. 175 * @num_subbanks: Number of subbanks. 176 * @subbank_depth: Depth of subbank. 177 * @en_map: Enable/disable status. 178 * @kw: Kex configured key type. 179 * @sb: Subbank array. 180 * @xa_sb_used: Array of used subbanks. 181 * @xa_sb_free: Array of free subbanks. 182 * @xa_pf2idx_map: PF to mcam index map. 183 * @xa_idx2pf_map: Mcam index to PF map. 184 * @xa_pf_map: Pcifunc to index map. 185 * @pf_cnt: Number of PFs. 186 * @xa_pf2dfl_rmap: PF to default rule index map. 187 * @xa_idx2vidx_map: Mcam index to virtual index map. 188 * @xa_vidx2idx_map: virtual index to mcam index map. 189 * @defrag_lh: Defrag list head. 190 * @lock: Lock for defrag list 191 * 192 * This structure is populated during probing time by reading 193 * HW csr registers. 194 */ 195 struct npc_priv_t { 196 int bank_depth; 197 int num_banks; 198 int num_subbanks; 199 int subbank_depth; 200 DECLARE_BITMAP(en_map, MAX_NUM_BANKS * 201 MAX_NUM_SUB_BANKS * 202 MAX_SUBBANK_DEPTH); 203 u8 kw; 204 struct npc_subbank *sb; 205 struct xarray xa_sb_used; 206 struct xarray xa_sb_free; 207 struct xarray *xa_pf2idx_map; 208 struct xarray xa_idx2pf_map; 209 struct xarray xa_pf_map; 210 struct xarray xa_pf2dfl_rmap; 211 struct xarray xa_idx2vidx_map; 212 struct xarray xa_vidx2idx_map; 213 struct list_head defrag_lh; 214 struct mutex lock; /* protect defrag nodes */ 215 int pf_cnt; 216 }; 217 218 struct npc_kpm_action0 { 219 #if defined(__BIG_ENDIAN_BITFIELD) 220 u64 rsvd_63_57 : 7; 221 u64 byp_count : 3; 222 u64 capture_ena : 1; 223 u64 parse_done : 1; 224 u64 next_state : 8; 225 u64 rsvd_43 : 1; 226 u64 capture_lid : 3; 227 u64 capture_ltype : 4; 228 u64 rsvd_32_35 : 4; 229 u64 capture_flags : 4; 230 u64 ptr_advance : 8; 231 u64 var_len_offset : 8; 232 u64 var_len_mask : 8; 233 u64 var_len_right : 1; 234 u64 var_len_shift : 3; 235 #else 236 u64 var_len_shift : 3; 237 u64 var_len_right : 1; 238 u64 var_len_mask : 8; 239 u64 var_len_offset : 8; 240 u64 ptr_advance : 8; 241 u64 capture_flags : 4; 242 u64 rsvd_32_35 : 4; 243 u64 capture_ltype : 4; 244 u64 capture_lid : 3; 245 u64 rsvd_43 : 1; 246 u64 next_state : 8; 247 u64 parse_done : 1; 248 u64 capture_ena : 1; 249 u64 byp_count : 3; 250 u64 rsvd_63_57 : 7; 251 #endif 252 }; 253 254 struct npc_mcam_kex_extr { 255 /* MKEX Profle Header */ 256 u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */ 257 u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */ 258 u64 cpu_model; /* Format as profiled by CPU hardware */ 259 u64 kpu_version; /* KPU firmware/profile version */ 260 u64 reserved; /* Reserved for extension */ 261 262 /* MKEX Profle Data */ 263 u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */ 264 #define NPC_MAX_EXTRACTOR 24 265 /* MKEX Extractor data */ 266 u64 intf_extr_lid[NPC_MAX_INTF][NPC_MAX_EXTRACTOR]; 267 /* KEX configuration per extractor */ 268 u64 intf_extr_lt[NPC_MAX_INTF][NPC_MAX_EXTRACTOR][NPC_MAX_LT]; 269 } __packed; 270 271 struct npc_cn20k_kpu_profile_fwdata { 272 #define KPU_SIGN 0x00666f727075706b 273 #define KPU_NAME_LEN 32 274 /* Maximum number of custom KPU entries supported by 275 * the built-in profile. 276 */ 277 #define KPU_CN20K_MAX_CST_ENT 6 278 /* KPU Profle Header */ 279 __le64 signature; /* "kpuprof\0" (8 bytes/ASCII characters) */ 280 u8 name[KPU_NAME_LEN]; /* KPU Profile name */ 281 __le64 version; /* KPU profile version */ 282 u8 kpus; 283 u8 reserved[7]; 284 285 /* Default MKEX profile to be used with this KPU profile. May be 286 * overridden with mkex_profile module parameter. 287 * Format is same as for the MKEX profile to streamline processing. 288 */ 289 struct npc_mcam_kex_extr mkex; 290 /* LTYPE values for specific HW offloaded protocols. */ 291 struct npc_lt_def_cfg lt_def; 292 /* Dynamically sized data: 293 * Custom KPU CAM and ACTION configuration entries. 294 * struct npc_kpu_fwdata kpu[kpus]; 295 */ 296 u8 data[]; 297 } __packed; 298 299 struct rvu; 300 301 struct npc_priv_t *npc_priv_get(void); 302 int npc_cn20k_init(struct rvu *rvu); 303 void npc_cn20k_deinit(struct rvu *rvu); 304 305 void npc_cn20k_subbank_calc_free(struct rvu *rvu, int *x2_free, 306 int *x4_free, int *sb_free); 307 308 int npc_cn20k_ref_idx_alloc(struct rvu *rvu, int pcifunc, int key_type, 309 int prio, u16 *mcam_idx, int ref, int limit, 310 bool contig, int count, bool virt); 311 int npc_cn20k_idx_free(struct rvu *rvu, u16 *mcam_idx, int count); 312 void npc_cn20k_parser_profile_init(struct rvu *rvu, int blkaddr); 313 struct npc_mcam_kex_extr *npc_mkex_extr_default_get(void); 314 void npc_cn20k_load_mkex_profile(struct rvu *rvu, int blkaddr, 315 const char *mkex_profile); 316 int npc_cn20k_apply_custom_kpu(struct rvu *rvu, 317 struct npc_kpu_profile_adapter *profile); 318 319 void 320 npc_cn20k_update_action_entries_n_flags(struct rvu *rvu, 321 struct npc_kpu_profile_adapter *pfl); 322 323 int npc_cn20k_dft_rules_alloc(struct rvu *rvu, u16 pcifunc); 324 void npc_cn20k_dft_rules_free(struct rvu *rvu, u16 pcifunc); 325 326 int npc_cn20k_dft_rules_idx_get(struct rvu *rvu, u16 pcifunc, u16 *bcast, 327 u16 *mcast, u16 *promisc, u16 *ucast); 328 329 int npc_cn20k_config_mcam_entry(struct rvu *rvu, int blkaddr, int index, 330 u8 intf, struct cn20k_mcam_entry *entry, 331 bool enable, u8 hw_prio, u8 req_kw_type); 332 int npc_cn20k_enable_mcam_entry(struct rvu *rvu, int blkaddr, 333 int index, bool enable); 334 int npc_cn20k_copy_mcam_entry(struct rvu *rvu, int blkaddr, 335 u16 src, u16 dest); 336 int npc_cn20k_read_mcam_entry(struct rvu *rvu, int blkaddr, u16 index, 337 struct cn20k_mcam_entry *entry, u8 *intf, 338 u8 *ena, u8 *hw_prio); 339 int npc_cn20k_clear_mcam_entry(struct rvu *rvu, int blkaddr, int index); 340 int npc_mcam_idx_2_key_type(struct rvu *rvu, u16 mcam_idx, u8 *key_type); 341 u16 npc_cn20k_vidx2idx(u16 index); 342 u16 npc_cn20k_idx2vidx(u16 idx); 343 int npc_cn20k_defrag(struct rvu *rvu); 344 bool npc_is_cgx_or_lbk(struct rvu *rvu, u16 pcifunc); 345 int npc_mcam_idx_2_subbank_idx(struct rvu *rvu, u16 mcam_idx, 346 struct npc_subbank **sb, 347 int *sb_off); 348 const u32 *npc_cn20k_search_order_get(bool *restricted_order, u32 *sz); 349 int npc_cn20k_search_order_set(struct rvu *rvu, u64 narr[MAX_NUM_SUB_BANKS], 350 int cnt); 351 352 #endif /* NPC_CN20K_H */ 353