1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/dim.h> 34 #include <linux/ethtool_netlink.h> 35 #include <net/netdev_queues.h> 36 37 #include "en.h" 38 #include "en/channels.h" 39 #include "en/dim.h" 40 #include "en/port.h" 41 #include "en/params.h" 42 #include "en/ptp.h" 43 #include "lib/clock.h" 44 #include "en/fs_ethtool.h" 45 46 #define LANES_UNKNOWN 0 47 48 #define MLX5E_MAX_INDIR_RQT_SIZE \ 49 roundup_pow_of_two(MLX5E_MAX_NUM_CHANNELS * \ 50 MLX5E_UNIFORM_SPREAD_RQT_FACTOR) 51 52 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 53 struct ethtool_drvinfo *drvinfo) 54 { 55 struct mlx5_core_dev *mdev = priv->mdev; 56 int count; 57 58 strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver)); 59 count = snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 60 "%d.%d.%04d (%.16s)", fw_rev_maj(mdev), 61 fw_rev_min(mdev), fw_rev_sub(mdev), mdev->board_id); 62 if (count >= sizeof(drvinfo->fw_version)) 63 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 64 "%d.%d.%04d", fw_rev_maj(mdev), 65 fw_rev_min(mdev), fw_rev_sub(mdev)); 66 67 strscpy(drvinfo->bus_info, dev_name(mdev->device), 68 sizeof(drvinfo->bus_info)); 69 } 70 71 static void mlx5e_get_drvinfo(struct net_device *dev, 72 struct ethtool_drvinfo *drvinfo) 73 { 74 struct mlx5e_priv *priv = netdev_priv(dev); 75 76 mlx5e_ethtool_get_drvinfo(priv, drvinfo); 77 } 78 79 struct ptys2ethtool_config { 80 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 81 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); 82 }; 83 84 static 85 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER]; 86 static 87 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER]; 88 89 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \ 90 ({ \ 91 struct ptys2ethtool_config *cfg; \ 92 const unsigned int modes[] = { __VA_ARGS__ }; \ 93 unsigned int i; \ 94 cfg = &ptys2##table##_ethtool_table[reg_]; \ 95 bitmap_zero(cfg->supported, \ 96 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 97 bitmap_zero(cfg->advertised, \ 98 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 99 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ 100 bitmap_set(cfg->supported, modes[i], 1); \ 101 bitmap_set(cfg->advertised, modes[i], 1); \ 102 } \ 103 }) 104 105 void mlx5e_build_ptys2ethtool_map(void) 106 { 107 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table)); 108 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table)); 109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy, 110 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy, 112 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy, 114 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy, 116 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy, 118 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy, 120 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); 121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy, 122 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); 123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy, 124 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); 125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy, 126 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); 127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy, 128 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy, 130 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy, 132 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy, 134 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); 135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy, 136 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy, 138 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy, 140 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT); 141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy, 142 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT); 143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy, 144 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT); 145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy, 146 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 147 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100BASE_TX, legacy, 148 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_T, legacy, 150 ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy, 152 ETHTOOL_LINK_MODE_10000baseT_Full_BIT); 153 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy, 154 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT); 155 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy, 156 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT); 157 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy, 158 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy, 160 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT); 161 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy, 162 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT); 163 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext, 164 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext, 166 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 167 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 168 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext, 170 ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 171 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext, 172 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 173 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 174 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 175 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 176 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 177 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 178 ETHTOOL_LINK_MODE_10000baseER_Full_BIT); 179 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext, 180 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 181 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 182 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 183 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 184 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext, 185 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 186 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 187 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 188 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, 189 ext, 190 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 191 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 192 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 193 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext, 194 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 195 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 196 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 197 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 198 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT); 199 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext, 200 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 201 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 202 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 203 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 204 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext, 205 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 206 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 207 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 208 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 209 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT); 210 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext, 211 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 212 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 213 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 214 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT, 215 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT); 216 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_8_400GBASE_CR8, ext, 217 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT, 218 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT, 219 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT, 220 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT, 221 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT); 222 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext, 223 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 224 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 225 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 226 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT, 227 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT); 228 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext, 229 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 230 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 231 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 232 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT, 233 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT); 234 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext, 235 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 236 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 237 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 238 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT, 239 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT); 240 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_8_800GBASE_CR8_KR8, ext, 241 ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT, 242 ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT, 243 ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT, 244 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT, 245 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT, 246 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT); 247 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext, 248 ETHTOOL_LINK_MODE_200000baseCR_Full_BIT, 249 ETHTOOL_LINK_MODE_200000baseKR_Full_BIT, 250 ETHTOOL_LINK_MODE_200000baseDR_Full_BIT, 251 ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT, 252 ETHTOOL_LINK_MODE_200000baseSR_Full_BIT, 253 ETHTOOL_LINK_MODE_200000baseVR_Full_BIT); 254 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext, 255 ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT, 256 ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT, 257 ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT, 258 ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT, 259 ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT, 260 ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT); 261 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext, 262 ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT, 263 ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT, 264 ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT, 265 ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT, 266 ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT, 267 ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT); 268 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8, ext, 269 ETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT, 270 ETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT, 271 ETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT, 272 ETHTOOL_LINK_MODE_1600000baseDR8_2_Full_BIT); 273 } 274 275 static void mlx5e_ethtool_get_speed_arr(bool ext, 276 struct ptys2ethtool_config **arr, 277 u32 *size) 278 { 279 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; 280 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : 281 ARRAY_SIZE(ptys2legacy_ethtool_table); 282 } 283 284 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable); 285 286 struct pflag_desc { 287 char name[ETH_GSTRING_LEN]; 288 mlx5e_pflag_handler handler; 289 }; 290 291 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS]; 292 293 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset) 294 { 295 switch (sset) { 296 case ETH_SS_STATS: 297 return mlx5e_stats_total_num(priv); 298 case ETH_SS_PRIV_FLAGS: 299 return MLX5E_NUM_PFLAGS; 300 case ETH_SS_TEST: 301 return mlx5e_self_test_num(priv); 302 default: 303 return -EOPNOTSUPP; 304 } 305 } 306 307 static int mlx5e_get_sset_count(struct net_device *dev, int sset) 308 { 309 struct mlx5e_priv *priv = netdev_priv(dev); 310 311 return mlx5e_ethtool_get_sset_count(priv, sset); 312 } 313 314 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data) 315 { 316 int i; 317 318 switch (stringset) { 319 case ETH_SS_PRIV_FLAGS: 320 for (i = 0; i < MLX5E_NUM_PFLAGS; i++) 321 ethtool_puts(&data, mlx5e_priv_flags[i].name); 322 break; 323 324 case ETH_SS_TEST: 325 mlx5e_self_test_fill_strings(priv, data); 326 break; 327 328 case ETH_SS_STATS: 329 mlx5e_stats_fill_strings(priv, data); 330 break; 331 } 332 } 333 334 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data) 335 { 336 struct mlx5e_priv *priv = netdev_priv(dev); 337 338 mlx5e_ethtool_get_strings(priv, stringset, data); 339 } 340 341 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 342 struct ethtool_stats *stats, u64 *data) 343 { 344 int idx = 0; 345 346 mutex_lock(&priv->state_lock); 347 mlx5e_stats_update(priv); 348 mutex_unlock(&priv->state_lock); 349 350 mlx5e_stats_fill(priv, data, idx); 351 } 352 353 static void mlx5e_get_ethtool_stats(struct net_device *dev, 354 struct ethtool_stats *stats, 355 u64 *data) 356 { 357 struct mlx5e_priv *priv = netdev_priv(dev); 358 359 mlx5e_ethtool_get_ethtool_stats(priv, stats, data); 360 } 361 362 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 363 struct ethtool_ringparam *param, 364 struct kernel_ethtool_ringparam *kernel_param) 365 { 366 /* Limitation for regular RQ. XSK RQ may clamp the queue length in 367 * mlx5e_mpwqe_get_log_rq_size. 368 */ 369 u8 max_log_mpwrq_pkts = mlx5e_mpwrq_max_log_rq_pkts(priv->mdev, 370 PAGE_SHIFT, 371 MLX5E_MPWRQ_UMR_MODE_ALIGNED); 372 373 param->rx_max_pending = 1 << min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE, 374 max_log_mpwrq_pkts); 375 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; 376 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames; 377 param->tx_pending = 1 << priv->channels.params.log_sq_size; 378 379 kernel_param->hds_thresh = 0; 380 kernel_param->hds_thresh_max = 0; 381 } 382 383 static void mlx5e_get_ringparam(struct net_device *dev, 384 struct ethtool_ringparam *param, 385 struct kernel_ethtool_ringparam *kernel_param, 386 struct netlink_ext_ack *extack) 387 { 388 struct mlx5e_priv *priv = netdev_priv(dev); 389 390 mlx5e_ethtool_get_ringparam(priv, param, kernel_param); 391 } 392 393 static bool mlx5e_ethtool_set_tcp_data_split(struct mlx5e_priv *priv, 394 u8 tcp_data_split, 395 struct netlink_ext_ack *extack) 396 { 397 struct net_device *dev = priv->netdev; 398 399 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED && 400 !(dev->features & NETIF_F_GRO_HW)) { 401 NL_SET_ERR_MSG_MOD(extack, 402 "TCP-data-split is not supported when GRO HW is disabled"); 403 return false; 404 } 405 406 /* Might need to disable HW-GRO if it was kept on due to hds. */ 407 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && 408 dev->cfg->hds_config == ETHTOOL_TCP_DATA_SPLIT_ENABLED) 409 netdev_update_features(priv->netdev); 410 411 return true; 412 } 413 414 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 415 struct ethtool_ringparam *param, 416 struct netlink_ext_ack *extack) 417 { 418 struct mlx5e_params new_params; 419 u8 log_rq_size; 420 u8 log_sq_size; 421 int err = 0; 422 423 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) { 424 NL_SET_ERR_MSG_FMT_MOD(extack, "rx (%d) < min (%d)", 425 param->rx_pending, 426 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); 427 return -EINVAL; 428 } 429 430 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { 431 NL_SET_ERR_MSG_FMT_MOD(extack, "tx (%d) < min (%d)", 432 param->tx_pending, 433 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); 434 return -EINVAL; 435 } 436 437 log_rq_size = order_base_2(param->rx_pending); 438 log_sq_size = order_base_2(param->tx_pending); 439 440 if (log_rq_size == priv->channels.params.log_rq_mtu_frames && 441 log_sq_size == priv->channels.params.log_sq_size) 442 return 0; 443 444 mutex_lock(&priv->state_lock); 445 446 new_params = priv->channels.params; 447 new_params.log_rq_mtu_frames = log_rq_size; 448 new_params.log_sq_size = log_sq_size; 449 450 err = mlx5e_validate_params(priv->mdev, &new_params); 451 if (err) 452 goto unlock; 453 454 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 455 456 unlock: 457 mutex_unlock(&priv->state_lock); 458 459 if (!err) 460 netdev_update_features(priv->netdev); 461 462 return err; 463 } 464 465 static int mlx5e_set_ringparam(struct net_device *dev, 466 struct ethtool_ringparam *param, 467 struct kernel_ethtool_ringparam *kernel_param, 468 struct netlink_ext_ack *extack) 469 { 470 struct mlx5e_priv *priv = netdev_priv(dev); 471 472 if (!mlx5e_ethtool_set_tcp_data_split(priv, 473 kernel_param->tcp_data_split, 474 extack)) 475 return -EINVAL; 476 477 return mlx5e_ethtool_set_ringparam(priv, param, extack); 478 } 479 480 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 481 struct ethtool_channels *ch) 482 { 483 mutex_lock(&priv->state_lock); 484 ch->max_combined = priv->max_nch; 485 ch->combined_count = priv->channels.params.num_channels; 486 mutex_unlock(&priv->state_lock); 487 } 488 489 static void mlx5e_get_channels(struct net_device *dev, 490 struct ethtool_channels *ch) 491 { 492 struct mlx5e_priv *priv = netdev_priv(dev); 493 494 mlx5e_ethtool_get_channels(priv, ch); 495 } 496 497 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 498 struct ethtool_channels *ch) 499 { 500 struct mlx5e_params *cur_params = &priv->channels.params; 501 unsigned int count = ch->combined_count; 502 int new_rqt_size, cur_rqt_size; 503 struct mlx5e_params new_params; 504 struct mlx5e_rss *rss0; 505 bool arfs_enabled; 506 bool has_rss_ctxs; 507 bool opened; 508 int err = 0; 509 510 ASSERT_RTNL(); 511 512 if (!count) { 513 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n", 514 __func__); 515 return -EINVAL; 516 } 517 518 if (cur_params->num_channels == count) 519 return 0; 520 521 new_rqt_size = mlx5e_rqt_size(priv->mdev, count); 522 /* Validate that all non-default RSS contexts can be resized before 523 * committing to the channel count change. 524 * ethtool_rxfh_ctxs_can_resize() acquires rss_lock internally and 525 * cannot be called under state_lock (rss_lock -> state_lock ordering). 526 */ 527 has_rss_ctxs = priv->rx_res && mlx5e_rx_res_rss_cnt(priv->rx_res) > 1; 528 if (has_rss_ctxs) { 529 err = ethtool_rxfh_ctxs_can_resize(priv->netdev, new_rqt_size); 530 if (err) 531 return err; 532 } 533 534 mutex_lock(&priv->state_lock); 535 536 if (!priv->rx_res) { 537 err = -EINVAL; 538 goto out; 539 } 540 541 cur_rqt_size = mlx5e_rqt_size(priv->mdev, cur_params->num_channels); 542 rss0 = mlx5e_rx_res_rss_get(priv->rx_res, 0); 543 544 if (!ethtool_rxfh_indir_can_resize(priv->netdev, 545 mlx5e_rss_get_indir_table(rss0), 546 cur_rqt_size, new_rqt_size)) { 547 netdev_err(priv->netdev, 548 "%s: cannot resize RSS table (%u -> %u); reset indirection table to allow this change\n", 549 __func__, cur_rqt_size, new_rqt_size); 550 err = -EINVAL; 551 goto out; 552 } 553 554 /* Don't allow changing the number of channels if HTB offload is active, 555 * because the numeration of the QoS SQs will change, while per-queue 556 * qdiscs are attached. 557 */ 558 if (mlx5e_selq_is_htb_enabled(&priv->selq)) { 559 err = -EINVAL; 560 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n", 561 __func__); 562 goto out; 563 } 564 565 /* Don't allow changing the number of channels if MQPRIO mode channel offload is active, 566 * because it defines a partition over the channels queues. 567 */ 568 if (cur_params->mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { 569 err = -EINVAL; 570 netdev_err(priv->netdev, "%s: MQPRIO mode channel offload is active, cannot change the number of channels\n", 571 __func__); 572 goto out; 573 } 574 575 new_params = *cur_params; 576 new_params.num_channels = count; 577 578 opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 579 580 arfs_enabled = opened && mlx5e_fs_want_arfs(priv->netdev); 581 if (arfs_enabled) 582 mlx5e_arfs_disable(priv->fs); 583 584 /* Switch to new channels, set new parameters and close old ones */ 585 err = mlx5e_safe_switch_params(priv, &new_params, 586 mlx5e_num_channels_changed_ctx, NULL, true); 587 588 if (arfs_enabled) { 589 int err2 = mlx5e_arfs_enable(priv->fs); 590 591 if (err2) 592 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n", 593 __func__, err2); 594 } 595 596 out: 597 mutex_unlock(&priv->state_lock); 598 599 /* After a successful channel count change that altered the RQT size, 600 * fold or unfold the indirection tables of all non-default RSS 601 * contexts. Must run after state_lock is released because 602 * ethtool_rxfh_ctxs_resize() acquires rss_lock internally. 603 */ 604 if (!err && cur_rqt_size != new_rqt_size && has_rss_ctxs) 605 ethtool_rxfh_ctxs_resize(priv->netdev, new_rqt_size); 606 607 return err; 608 } 609 610 static int mlx5e_set_channels(struct net_device *dev, 611 struct ethtool_channels *ch) 612 { 613 struct mlx5e_priv *priv = netdev_priv(dev); 614 615 return mlx5e_ethtool_set_channels(priv, ch); 616 } 617 618 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 619 struct ethtool_coalesce *coal, 620 struct kernel_ethtool_coalesce *kernel_coal, 621 struct netlink_ext_ack *extack) 622 { 623 struct dim_cq_moder *rx_moder, *tx_moder; 624 625 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) { 626 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported"); 627 return -EOPNOTSUPP; 628 } 629 630 rx_moder = &priv->channels.params.rx_cq_moderation; 631 coal->rx_coalesce_usecs = rx_moder->usec; 632 coal->rx_max_coalesced_frames = rx_moder->pkts; 633 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled; 634 kernel_coal->use_cqe_mode_rx = priv->channels.params.rx_moder_use_cqe_mode; 635 636 tx_moder = &priv->channels.params.tx_cq_moderation; 637 coal->tx_coalesce_usecs = tx_moder->usec; 638 coal->tx_max_coalesced_frames = tx_moder->pkts; 639 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled; 640 kernel_coal->use_cqe_mode_tx = priv->channels.params.tx_moder_use_cqe_mode; 641 642 return 0; 643 } 644 645 static int mlx5e_get_coalesce(struct net_device *netdev, 646 struct ethtool_coalesce *coal, 647 struct kernel_ethtool_coalesce *kernel_coal, 648 struct netlink_ext_ack *extack) 649 { 650 struct mlx5e_priv *priv = netdev_priv(netdev); 651 652 return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal, extack); 653 } 654 655 static int mlx5e_ethtool_get_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue, 656 struct ethtool_coalesce *coal) 657 { 658 struct dim_cq_moder cur_moder; 659 struct mlx5e_channels *chs; 660 struct mlx5e_channel *c; 661 662 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) 663 return -EOPNOTSUPP; 664 665 mutex_lock(&priv->state_lock); 666 667 chs = &priv->channels; 668 if (chs->num <= queue) { 669 mutex_unlock(&priv->state_lock); 670 return -EINVAL; 671 } 672 673 c = chs->c[queue]; 674 675 coal->use_adaptive_rx_coalesce = !!c->rq.dim; 676 if (coal->use_adaptive_rx_coalesce) { 677 cur_moder = net_dim_get_rx_moderation(c->rq.dim->mode, 678 c->rq.dim->profile_ix); 679 680 coal->rx_coalesce_usecs = cur_moder.usec; 681 coal->rx_max_coalesced_frames = cur_moder.pkts; 682 } else { 683 coal->rx_coalesce_usecs = c->rx_cq_moder.usec; 684 coal->rx_max_coalesced_frames = c->rx_cq_moder.pkts; 685 } 686 687 coal->use_adaptive_tx_coalesce = !!c->sq[0].dim; 688 if (coal->use_adaptive_tx_coalesce) { 689 /* NOTE: Will only display DIM coalesce profile information of 690 * first channel. The current interface cannot display this 691 * information for all tc. 692 */ 693 cur_moder = net_dim_get_tx_moderation(c->sq[0].dim->mode, 694 c->sq[0].dim->profile_ix); 695 696 coal->tx_coalesce_usecs = cur_moder.usec; 697 coal->tx_max_coalesced_frames = cur_moder.pkts; 698 699 } else { 700 coal->tx_coalesce_usecs = c->tx_cq_moder.usec; 701 coal->tx_max_coalesced_frames = c->tx_cq_moder.pkts; 702 } 703 704 mutex_unlock(&priv->state_lock); 705 706 return 0; 707 } 708 709 int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue, 710 struct ethtool_coalesce *coal) 711 { 712 struct mlx5e_priv *priv = netdev_priv(dev); 713 714 return mlx5e_ethtool_get_per_queue_coalesce(priv, queue, coal); 715 } 716 717 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD 718 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT 719 720 static void 721 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder) 722 { 723 int tc; 724 int i; 725 726 for (i = 0; i < priv->channels.num; ++i) { 727 struct mlx5e_channel *c = priv->channels.c[i]; 728 struct mlx5_core_dev *mdev = c->mdev; 729 enum mlx5_cq_period_mode mode; 730 731 mode = mlx5e_cq_period_mode(moder->cq_period_mode); 732 c->tx_cq_moder = *moder; 733 734 for (tc = 0; tc < c->num_tc; tc++) { 735 mlx5e_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq, 736 moder->usec, moder->pkts, 737 mode); 738 } 739 } 740 } 741 742 static void 743 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct dim_cq_moder *moder) 744 { 745 int i; 746 747 for (i = 0; i < priv->channels.num; ++i) { 748 struct mlx5e_channel *c = priv->channels.c[i]; 749 struct mlx5_core_dev *mdev = c->mdev; 750 enum mlx5_cq_period_mode mode; 751 752 mode = mlx5e_cq_period_mode(moder->cq_period_mode); 753 c->rx_cq_moder = *moder; 754 755 mlx5e_modify_cq_moderation(mdev, &c->rq.cq.mcq, moder->usec, moder->pkts, 756 mode); 757 } 758 } 759 760 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 761 struct ethtool_coalesce *coal, 762 struct kernel_ethtool_coalesce *kernel_coal, 763 struct netlink_ext_ack *extack) 764 { 765 struct dim_cq_moder *rx_moder, *tx_moder; 766 struct mlx5_core_dev *mdev = priv->mdev; 767 bool rx_dim_enabled, tx_dim_enabled; 768 struct mlx5e_params new_params; 769 bool reset_rx, reset_tx; 770 u8 cq_period_mode; 771 int err = 0; 772 773 if (!MLX5_CAP_GEN(mdev, cq_moderation) || 774 !MLX5_CAP_GEN(mdev, cq_period_mode_modify)) { 775 NL_SET_ERR_MSG_MOD(extack, "CQ moderation not supported"); 776 return -EOPNOTSUPP; 777 } 778 779 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || 780 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { 781 NL_SET_ERR_MSG_FMT_MOD( 782 extack, 783 "Max coalesce time %lu usecs, tx-usecs (%u) rx-usecs (%u)", 784 MLX5E_MAX_COAL_TIME, coal->tx_coalesce_usecs, 785 coal->rx_coalesce_usecs); 786 return -ERANGE; 787 } 788 789 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || 790 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { 791 NL_SET_ERR_MSG_FMT_MOD( 792 extack, 793 "Max coalesce frames %lu, tx-frames (%u) rx-frames (%u)", 794 MLX5E_MAX_COAL_FRAMES, coal->tx_max_coalesced_frames, 795 coal->rx_max_coalesced_frames); 796 return -ERANGE; 797 } 798 799 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 800 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) { 801 NL_SET_ERR_MSG_MOD(extack, "cqe-mode-rx/tx is not supported on this device"); 802 return -EOPNOTSUPP; 803 } 804 805 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; 806 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; 807 808 mutex_lock(&priv->state_lock); 809 new_params = priv->channels.params; 810 811 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_rx); 812 reset_rx = mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode, 813 rx_dim_enabled, false); 814 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER, cq_period_mode); 815 816 cq_period_mode = mlx5e_dim_cq_period_mode(kernel_coal->use_cqe_mode_tx); 817 reset_tx = mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode, 818 tx_dim_enabled, false); 819 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER, cq_period_mode); 820 821 reset_rx |= rx_dim_enabled != new_params.rx_dim_enabled; 822 reset_tx |= tx_dim_enabled != new_params.tx_dim_enabled; 823 824 /* Solely used for global ethtool get coalesce */ 825 rx_moder = &new_params.rx_cq_moderation; 826 new_params.rx_dim_enabled = rx_dim_enabled; 827 new_params.rx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_rx; 828 829 tx_moder = &new_params.tx_cq_moderation; 830 new_params.tx_dim_enabled = tx_dim_enabled; 831 new_params.tx_moder_use_cqe_mode = kernel_coal->use_cqe_mode_tx; 832 833 if (reset_rx) { 834 mlx5e_channels_rx_change_dim(&priv->channels, false); 835 mlx5e_reset_rx_moderation(rx_moder, new_params.rx_moder_use_cqe_mode, 836 rx_dim_enabled); 837 838 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder); 839 } else if (!rx_dim_enabled) { 840 rx_moder->usec = coal->rx_coalesce_usecs; 841 rx_moder->pkts = coal->rx_max_coalesced_frames; 842 843 mlx5e_set_priv_channels_rx_coalesce(priv, rx_moder); 844 } 845 846 if (reset_tx) { 847 mlx5e_channels_tx_change_dim(&priv->channels, false); 848 mlx5e_reset_tx_moderation(tx_moder, new_params.tx_moder_use_cqe_mode, 849 tx_dim_enabled); 850 851 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder); 852 } else if (!tx_dim_enabled) { 853 tx_moder->usec = coal->tx_coalesce_usecs; 854 tx_moder->pkts = coal->tx_max_coalesced_frames; 855 856 mlx5e_set_priv_channels_tx_coalesce(priv, tx_moder); 857 } 858 859 /* DIM enable/disable Rx and Tx channels */ 860 err = mlx5e_channels_rx_change_dim(&priv->channels, rx_dim_enabled); 861 if (err) 862 goto state_unlock; 863 err = mlx5e_channels_tx_change_dim(&priv->channels, tx_dim_enabled); 864 if (err) 865 goto state_unlock; 866 867 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false); 868 state_unlock: 869 mutex_unlock(&priv->state_lock); 870 return err; 871 } 872 873 static int mlx5e_set_coalesce(struct net_device *netdev, 874 struct ethtool_coalesce *coal, 875 struct kernel_ethtool_coalesce *kernel_coal, 876 struct netlink_ext_ack *extack) 877 { 878 struct mlx5e_priv *priv = netdev_priv(netdev); 879 880 return mlx5e_ethtool_set_coalesce(priv, coal, kernel_coal, extack); 881 } 882 883 static int mlx5e_ethtool_set_per_queue_coalesce(struct mlx5e_priv *priv, u32 queue, 884 struct ethtool_coalesce *coal) 885 { 886 struct mlx5_core_dev *mdev = priv->mdev; 887 bool rx_dim_enabled, tx_dim_enabled; 888 struct mlx5e_channels *chs; 889 struct mlx5e_channel *c; 890 int err = 0; 891 int tc; 892 893 if (!MLX5_CAP_GEN(mdev, cq_moderation)) 894 return -EOPNOTSUPP; 895 896 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || 897 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { 898 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n", 899 __func__, MLX5E_MAX_COAL_TIME); 900 return -ERANGE; 901 } 902 903 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || 904 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { 905 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n", 906 __func__, MLX5E_MAX_COAL_FRAMES); 907 return -ERANGE; 908 } 909 910 rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; 911 tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; 912 913 mutex_lock(&priv->state_lock); 914 915 chs = &priv->channels; 916 if (chs->num <= queue) { 917 mutex_unlock(&priv->state_lock); 918 return -EINVAL; 919 } 920 921 c = chs->c[queue]; 922 923 err = mlx5e_dim_rx_change(&c->rq, rx_dim_enabled); 924 if (err) 925 goto state_unlock; 926 927 for (tc = 0; tc < c->num_tc; tc++) { 928 err = mlx5e_dim_tx_change(&c->sq[tc], tx_dim_enabled); 929 if (err) 930 goto state_unlock; 931 } 932 933 if (!rx_dim_enabled) { 934 c->rx_cq_moder.usec = coal->rx_coalesce_usecs; 935 c->rx_cq_moder.pkts = coal->rx_max_coalesced_frames; 936 937 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, 938 coal->rx_coalesce_usecs, 939 coal->rx_max_coalesced_frames); 940 } 941 942 if (!tx_dim_enabled) { 943 c->tx_cq_moder.usec = coal->tx_coalesce_usecs; 944 c->tx_cq_moder.pkts = coal->tx_max_coalesced_frames; 945 946 for (tc = 0; tc < c->num_tc; tc++) 947 mlx5_core_modify_cq_moderation(mdev, &c->sq[tc].cq.mcq, 948 coal->tx_coalesce_usecs, 949 coal->tx_max_coalesced_frames); 950 } 951 952 state_unlock: 953 mutex_unlock(&priv->state_lock); 954 return err; 955 } 956 957 int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue, 958 struct ethtool_coalesce *coal) 959 { 960 struct mlx5e_priv *priv = netdev_priv(dev); 961 962 return mlx5e_ethtool_set_per_queue_coalesce(priv, queue, coal); 963 } 964 965 static void ptys2ethtool_process_link(u32 eth_eproto, bool ext, bool advertised, 966 unsigned long *modes) 967 { 968 unsigned long eproto = eth_eproto; 969 struct ptys2ethtool_config *table; 970 u32 max_size; 971 int proto; 972 973 mlx5e_ethtool_get_speed_arr(ext, &table, &max_size); 974 for_each_set_bit(proto, &eproto, max_size) 975 bitmap_or(modes, modes, 976 advertised ? 977 table[proto].advertised : table[proto].supported, 978 __ETHTOOL_LINK_MODE_MASK_NBITS); 979 } 980 981 static const u32 pplm_fec_2_ethtool[] = { 982 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF, 983 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER, 984 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS, 985 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS, 986 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS, 987 [MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_FEC_RS, 988 }; 989 990 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size) 991 { 992 int mode = 0; 993 994 if (!fec_mode) 995 return ETHTOOL_FEC_AUTO; 996 997 mode = find_first_bit(&fec_mode, size); 998 999 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool)) 1000 return pplm_fec_2_ethtool[mode]; 1001 1002 return 0; 1003 } 1004 1005 #define MLX5E_ADVERTISE_SUPPORTED_FEC(fec_mask, ethtool_fec) \ 1006 do { \ 1007 if (mlx5e_fec_in_caps(dev, fec_mask)) \ 1008 __set_bit(ethtool_fec, \ 1009 link_ksettings->link_modes.supported);\ 1010 } while (0) 1011 1012 static const u32 pplm_fec_2_ethtool_linkmodes[] = { 1013 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1014 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1015 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 1016 [MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 1017 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 1018 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 1019 }; 1020 1021 static int get_fec_supported_advertised(struct mlx5_core_dev *dev, 1022 struct ethtool_link_ksettings *link_ksettings) 1023 { 1024 unsigned long active_fec_long; 1025 u32 active_fec; 1026 u32 bitn; 1027 int err; 1028 1029 err = mlx5e_get_fec_mode(dev, &active_fec, NULL); 1030 if (err) 1031 return (err == -EOPNOTSUPP) ? 0 : err; 1032 1033 MLX5E_ADVERTISE_SUPPORTED_FEC(BIT(MLX5E_FEC_NOFEC), 1034 ETHTOOL_LINK_MODE_FEC_NONE_BIT); 1035 MLX5E_ADVERTISE_SUPPORTED_FEC(BIT(MLX5E_FEC_FIRECODE), 1036 ETHTOOL_LINK_MODE_FEC_BASER_BIT); 1037 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_MASK, 1038 ETHTOOL_LINK_MODE_FEC_RS_BIT); 1039 MLX5E_ADVERTISE_SUPPORTED_FEC(BIT(MLX5E_FEC_LLRS_272_257_1), 1040 ETHTOOL_LINK_MODE_FEC_LLRS_BIT); 1041 1042 active_fec_long = active_fec; 1043 /* active fec is a bit set, find out which bit is set and 1044 * advertise the corresponding ethtool bit 1045 */ 1046 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE); 1047 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes)) 1048 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn], 1049 link_ksettings->link_modes.advertising); 1050 1051 return 0; 1052 } 1053 1054 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev, 1055 struct ethtool_link_ksettings *link_ksettings, 1056 u32 eth_proto_cap, u8 connector_type) 1057 { 1058 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) { 1059 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR) 1060 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR) 1061 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) 1062 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) 1063 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) 1064 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 1065 ethtool_link_ksettings_add_link_mode(link_ksettings, 1066 supported, 1067 FIBRE); 1068 ethtool_link_ksettings_add_link_mode(link_ksettings, 1069 advertising, 1070 FIBRE); 1071 } 1072 1073 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4) 1074 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) 1075 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) 1076 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) 1077 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) { 1078 ethtool_link_ksettings_add_link_mode(link_ksettings, 1079 supported, 1080 Backplane); 1081 ethtool_link_ksettings_add_link_mode(link_ksettings, 1082 advertising, 1083 Backplane); 1084 } 1085 return; 1086 } 1087 1088 switch (connector_type) { 1089 case MLX5E_PORT_TP: 1090 ethtool_link_ksettings_add_link_mode(link_ksettings, 1091 supported, TP); 1092 ethtool_link_ksettings_add_link_mode(link_ksettings, 1093 advertising, TP); 1094 break; 1095 case MLX5E_PORT_AUI: 1096 ethtool_link_ksettings_add_link_mode(link_ksettings, 1097 supported, AUI); 1098 ethtool_link_ksettings_add_link_mode(link_ksettings, 1099 advertising, AUI); 1100 break; 1101 case MLX5E_PORT_BNC: 1102 ethtool_link_ksettings_add_link_mode(link_ksettings, 1103 supported, BNC); 1104 ethtool_link_ksettings_add_link_mode(link_ksettings, 1105 advertising, BNC); 1106 break; 1107 case MLX5E_PORT_MII: 1108 ethtool_link_ksettings_add_link_mode(link_ksettings, 1109 supported, MII); 1110 ethtool_link_ksettings_add_link_mode(link_ksettings, 1111 advertising, MII); 1112 break; 1113 case MLX5E_PORT_FIBRE: 1114 ethtool_link_ksettings_add_link_mode(link_ksettings, 1115 supported, FIBRE); 1116 ethtool_link_ksettings_add_link_mode(link_ksettings, 1117 advertising, FIBRE); 1118 break; 1119 case MLX5E_PORT_DA: 1120 ethtool_link_ksettings_add_link_mode(link_ksettings, 1121 supported, Backplane); 1122 ethtool_link_ksettings_add_link_mode(link_ksettings, 1123 advertising, Backplane); 1124 break; 1125 case MLX5E_PORT_NONE: 1126 case MLX5E_PORT_OTHER: 1127 default: 1128 break; 1129 } 1130 } 1131 1132 static void get_link_properties(struct net_device *netdev, 1133 u32 eth_proto_oper, bool force_legacy, 1134 u16 data_rate_oper, 1135 struct ethtool_link_ksettings *link_ksettings) 1136 { 1137 struct mlx5e_priv *priv = netdev_priv(netdev); 1138 const struct mlx5_link_info *info; 1139 u8 duplex = DUPLEX_UNKNOWN; 1140 u32 speed = SPEED_UNKNOWN; 1141 u32 lanes = LANES_UNKNOWN; 1142 1143 if (!netif_carrier_ok(netdev)) 1144 goto out; 1145 1146 info = mlx5_port_ptys2info(priv->mdev, eth_proto_oper, force_legacy); 1147 if (info) { 1148 speed = info->speed; 1149 lanes = info->lanes; 1150 duplex = DUPLEX_FULL; 1151 } else if (data_rate_oper) 1152 speed = 100 * data_rate_oper; 1153 1154 out: 1155 link_ksettings->base.duplex = duplex; 1156 link_ksettings->base.speed = speed; 1157 link_ksettings->lanes = lanes; 1158 } 1159 1160 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap, 1161 struct ethtool_link_ksettings *link_ksettings) 1162 { 1163 unsigned long *supported = link_ksettings->link_modes.supported; 1164 bool ext = mlx5_ptys_ext_supported(mdev); 1165 1166 ptys2ethtool_process_link(eth_proto_cap, ext, false, supported); 1167 1168 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause); 1169 } 1170 1171 static void get_advertising(u32 eth_proto_admin, u8 tx_pause, u8 rx_pause, 1172 struct ethtool_link_ksettings *link_ksettings, 1173 bool ext) 1174 { 1175 unsigned long *advertising = link_ksettings->link_modes.advertising; 1176 ptys2ethtool_process_link(eth_proto_admin, ext, true, advertising); 1177 if (rx_pause) 1178 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause); 1179 if (tx_pause ^ rx_pause) 1180 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause); 1181 } 1182 1183 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = { 1184 [MLX5E_PORT_UNKNOWN] = PORT_OTHER, 1185 [MLX5E_PORT_NONE] = PORT_NONE, 1186 [MLX5E_PORT_TP] = PORT_TP, 1187 [MLX5E_PORT_AUI] = PORT_AUI, 1188 [MLX5E_PORT_BNC] = PORT_BNC, 1189 [MLX5E_PORT_MII] = PORT_MII, 1190 [MLX5E_PORT_FIBRE] = PORT_FIBRE, 1191 [MLX5E_PORT_DA] = PORT_DA, 1192 [MLX5E_PORT_OTHER] = PORT_OTHER, 1193 }; 1194 1195 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type) 1196 { 1197 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) 1198 return ptys2connector_type[connector_type]; 1199 1200 if (eth_proto & 1201 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | 1202 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | 1203 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | 1204 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 1205 return PORT_FIBRE; 1206 } 1207 1208 if (eth_proto & 1209 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | 1210 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | 1211 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) { 1212 return PORT_DA; 1213 } 1214 1215 if (eth_proto & 1216 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | 1217 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | 1218 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | 1219 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) { 1220 return PORT_NONE; 1221 } 1222 1223 return PORT_OTHER; 1224 } 1225 1226 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp, 1227 struct ethtool_link_ksettings *link_ksettings) 1228 { 1229 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising; 1230 bool ext = mlx5_ptys_ext_supported(mdev); 1231 1232 ptys2ethtool_process_link(eth_proto_lp, ext, true, lp_advertising); 1233 } 1234 1235 static int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 1236 struct ethtool_link_ksettings *link_ksettings) 1237 { 1238 struct mlx5_core_dev *mdev = priv->mdev; 1239 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 1240 u32 eth_proto_admin; 1241 u8 an_disable_admin; 1242 u16 data_rate_oper; 1243 u32 eth_proto_oper; 1244 u32 eth_proto_cap; 1245 u8 connector_type; 1246 u32 rx_pause = 0; 1247 u32 tx_pause = 0; 1248 u32 eth_proto_lp; 1249 bool admin_ext; 1250 u8 an_status; 1251 bool ext; 1252 int err; 1253 1254 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1, 0); 1255 if (err) { 1256 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n", 1257 __func__, err); 1258 goto err_query_regs; 1259 } 1260 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 1261 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 1262 eth_proto_capability); 1263 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 1264 eth_proto_admin); 1265 /* Fields: eth_proto_admin and ext_eth_proto_admin are 1266 * mutually exclusive. Hence try reading legacy advertising 1267 * when extended advertising is zero. 1268 * admin_ext indicates which proto_admin (ext vs. legacy) 1269 * should be read and interpreted 1270 */ 1271 admin_ext = ext; 1272 if (ext && !eth_proto_admin) { 1273 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false, 1274 eth_proto_admin); 1275 admin_ext = false; 1276 } 1277 1278 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext, 1279 eth_proto_oper); 1280 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise); 1281 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin); 1282 an_status = MLX5_GET(ptys_reg, out, an_status); 1283 connector_type = MLX5_GET(ptys_reg, out, connector_type); 1284 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper); 1285 1286 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 1287 1288 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 1289 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 1290 1291 get_supported(mdev, eth_proto_cap, link_ksettings); 1292 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings, 1293 admin_ext); 1294 get_link_properties(priv->netdev, eth_proto_oper, !admin_ext, 1295 data_rate_oper, link_ksettings); 1296 1297 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; 1298 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ? 1299 connector_type : MLX5E_PORT_UNKNOWN; 1300 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type); 1301 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin, 1302 connector_type); 1303 get_lp_advertising(mdev, eth_proto_lp, link_ksettings); 1304 1305 if (an_status == MLX5_AN_COMPLETE) 1306 ethtool_link_ksettings_add_link_mode(link_ksettings, 1307 lp_advertising, Autoneg); 1308 1309 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : 1310 AUTONEG_ENABLE; 1311 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 1312 Autoneg); 1313 1314 err = get_fec_supported_advertised(mdev, link_ksettings); 1315 if (err) { 1316 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n", 1317 __func__, err); 1318 err = 0; /* don't fail caps query because of FEC error */ 1319 } 1320 1321 if (!an_disable_admin) 1322 ethtool_link_ksettings_add_link_mode(link_ksettings, 1323 advertising, Autoneg); 1324 1325 err_query_regs: 1326 return err; 1327 } 1328 1329 static int mlx5e_get_link_ksettings(struct net_device *netdev, 1330 struct ethtool_link_ksettings *link_ksettings) 1331 { 1332 struct mlx5e_priv *priv = netdev_priv(netdev); 1333 1334 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings); 1335 } 1336 1337 static int mlx5e_speed_validate(struct net_device *netdev, bool ext, 1338 const unsigned long link_modes, u8 autoneg) 1339 { 1340 /* Extended link-mode has no speed limitations. */ 1341 if (ext) 1342 return 0; 1343 1344 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) && 1345 autoneg != AUTONEG_ENABLE) { 1346 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n", 1347 __func__); 1348 return -EINVAL; 1349 } 1350 return 0; 1351 } 1352 1353 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) 1354 { 1355 u32 i, ptys_modes = 0; 1356 1357 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 1358 if (bitmap_empty(ptys2legacy_ethtool_table[i].advertised, 1359 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1360 continue; 1361 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised, 1362 link_modes, 1363 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1364 ptys_modes |= MLX5E_PROT_MASK(i); 1365 } 1366 1367 return ptys_modes; 1368 } 1369 1370 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes) 1371 { 1372 u32 i, ptys_modes = 0; 1373 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes); 1374 1375 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) { 1376 if (bitmap_empty(ptys2ext_ethtool_table[i].advertised, 1377 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1378 continue; 1379 bitmap_zero(modes, __ETHTOOL_LINK_MODE_MASK_NBITS); 1380 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised, 1381 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS); 1382 1383 if (bitmap_equal(modes, ptys2ext_ethtool_table[i].advertised, 1384 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1385 ptys_modes |= MLX5E_PROT_MASK(i); 1386 } 1387 return ptys_modes; 1388 } 1389 1390 static bool ext_link_mode_requested(const unsigned long *adver) 1391 { 1392 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT 1393 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT; 1394 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,}; 1395 1396 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size); 1397 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS); 1398 } 1399 1400 static int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1401 const struct ethtool_link_ksettings *link_ksettings) 1402 { 1403 struct mlx5_core_dev *mdev = priv->mdev; 1404 struct mlx5_port_eth_proto eproto; 1405 struct mlx5_link_info info = {}; 1406 const unsigned long *adver; 1407 bool an_changes = false; 1408 u8 an_disable_admin; 1409 bool ext_supported; 1410 bool ext_requested; 1411 u8 an_disable_cap; 1412 bool an_disable; 1413 u32 link_modes; 1414 u8 an_status; 1415 u8 autoneg; 1416 bool ext; 1417 int err; 1418 1419 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver); 1420 1421 adver = link_ksettings->link_modes.advertising; 1422 autoneg = link_ksettings->base.autoneg; 1423 info.speed = link_ksettings->base.speed; 1424 info.lanes = link_ksettings->lanes; 1425 1426 ext_supported = mlx5_ptys_ext_supported(mdev); 1427 ext_requested = ext_link_mode_requested(adver); 1428 if (!ext_supported && ext_requested) 1429 return -EOPNOTSUPP; 1430 1431 ext = autoneg == AUTONEG_ENABLE ? ext_requested : ext_supported; 1432 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link : 1433 mlx5e_ethtool2ptys_adver_link; 1434 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto); 1435 if (err) { 1436 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n", 1437 __func__, err); 1438 goto out; 1439 } 1440 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) : 1441 mlx5_port_info2linkmodes(mdev, &info, !ext); 1442 1443 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg); 1444 if (err) 1445 goto out; 1446 1447 link_modes = link_modes & eproto.cap; 1448 if (!link_modes) { 1449 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested", 1450 __func__); 1451 err = -EINVAL; 1452 goto out; 1453 } 1454 1455 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap, 1456 &an_disable_admin); 1457 1458 an_disable = autoneg == AUTONEG_DISABLE; 1459 an_changes = ((!an_disable && an_disable_admin) || 1460 (an_disable && !an_disable_admin)); 1461 1462 if (!an_changes && link_modes == eproto.admin) 1463 goto out; 1464 1465 err = mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext); 1466 if (err) { 1467 netdev_err(priv->netdev, "%s: failed to set ptys reg: %d\n", __func__, err); 1468 goto out; 1469 } 1470 1471 mlx5_toggle_port_link(mdev); 1472 1473 out: 1474 return err; 1475 } 1476 1477 static int mlx5e_set_link_ksettings(struct net_device *netdev, 1478 const struct ethtool_link_ksettings *link_ksettings) 1479 { 1480 struct mlx5e_priv *priv = netdev_priv(netdev); 1481 1482 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings); 1483 } 1484 1485 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) 1486 { 1487 return sizeof_field(struct mlx5e_rss_params_hash, toeplitz_hash_key); 1488 } 1489 1490 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) 1491 { 1492 struct mlx5e_priv *priv = netdev_priv(netdev); 1493 1494 return mlx5e_ethtool_get_rxfh_key_size(priv); 1495 } 1496 1497 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv) 1498 { 1499 return mlx5e_rqt_size(priv->mdev, priv->channels.params.num_channels); 1500 } 1501 1502 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev) 1503 { 1504 struct mlx5e_priv *priv = netdev_priv(netdev); 1505 1506 return mlx5e_ethtool_get_rxfh_indir_size(priv); 1507 } 1508 1509 static int mlx5e_get_rxfh(struct net_device *netdev, struct ethtool_rxfh_param *rxfh) 1510 { 1511 struct mlx5e_priv *priv = netdev_priv(netdev); 1512 bool symmetric; 1513 1514 mutex_lock(&priv->state_lock); 1515 mlx5e_rx_res_rss_get_rxfh(priv->rx_res, 0, rxfh->indir, rxfh->key, 1516 &rxfh->hfunc, &symmetric); 1517 mutex_unlock(&priv->state_lock); 1518 1519 if (symmetric) 1520 rxfh->input_xfrm = RXH_XFRM_SYM_OR_XOR; 1521 1522 return 0; 1523 } 1524 1525 static int mlx5e_set_rxfh(struct net_device *dev, 1526 struct ethtool_rxfh_param *rxfh, 1527 struct netlink_ext_ack *extack) 1528 { 1529 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR; 1530 struct mlx5e_priv *priv = netdev_priv(dev); 1531 u8 hfunc = rxfh->hfunc; 1532 int err; 1533 1534 mutex_lock(&priv->state_lock); 1535 1536 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context, 1537 rxfh->indir, rxfh->key, 1538 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc, 1539 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric); 1540 1541 mutex_unlock(&priv->state_lock); 1542 return err; 1543 } 1544 1545 static int mlx5e_create_rxfh_context(struct net_device *dev, 1546 struct ethtool_rxfh_context *ctx, 1547 const struct ethtool_rxfh_param *rxfh, 1548 struct netlink_ext_ack *extack) 1549 { 1550 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR; 1551 struct mlx5e_priv *priv = netdev_priv(dev); 1552 u8 hfunc = rxfh->hfunc; 1553 int err; 1554 1555 mutex_lock(&priv->state_lock); 1556 1557 err = mlx5e_rx_res_rss_init(priv->rx_res, rxfh->rss_context, 1558 priv->channels.params.num_channels); 1559 if (err) 1560 goto unlock; 1561 1562 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context, 1563 rxfh->indir, rxfh->key, 1564 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc, 1565 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric); 1566 if (err) { 1567 WARN_ON(mlx5e_rx_res_rss_destroy(priv->rx_res, 1568 rxfh->rss_context)); 1569 goto unlock; 1570 } 1571 1572 mlx5e_rx_res_rss_get_rxfh(priv->rx_res, rxfh->rss_context, 1573 ethtool_rxfh_context_indir(ctx), 1574 ethtool_rxfh_context_key(ctx), 1575 &ctx->hfunc, &symmetric); 1576 if (symmetric) 1577 ctx->input_xfrm = RXH_XFRM_SYM_OR_XOR; 1578 1579 unlock: 1580 mutex_unlock(&priv->state_lock); 1581 return err; 1582 } 1583 1584 static int mlx5e_modify_rxfh_context(struct net_device *dev, 1585 struct ethtool_rxfh_context *ctx, 1586 const struct ethtool_rxfh_param *rxfh, 1587 struct netlink_ext_ack *extack) 1588 { 1589 bool symmetric = rxfh->input_xfrm == RXH_XFRM_SYM_OR_XOR; 1590 struct mlx5e_priv *priv = netdev_priv(dev); 1591 u8 hfunc = rxfh->hfunc; 1592 int err; 1593 1594 mutex_lock(&priv->state_lock); 1595 1596 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, rxfh->rss_context, 1597 rxfh->indir, rxfh->key, 1598 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc, 1599 rxfh->input_xfrm == RXH_XFRM_NO_CHANGE ? NULL : &symmetric); 1600 1601 mutex_unlock(&priv->state_lock); 1602 return err; 1603 } 1604 1605 static int mlx5e_remove_rxfh_context(struct net_device *dev, 1606 struct ethtool_rxfh_context *ctx, 1607 u32 rss_context, 1608 struct netlink_ext_ack *extack) 1609 { 1610 struct mlx5e_priv *priv = netdev_priv(dev); 1611 int err; 1612 1613 mutex_lock(&priv->state_lock); 1614 err = mlx5e_rx_res_rss_destroy(priv->rx_res, rss_context); 1615 mutex_unlock(&priv->state_lock); 1616 return err; 1617 } 1618 1619 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100 1620 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000 1621 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85 1622 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80 1623 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \ 1624 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \ 1625 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100) 1626 1627 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev, 1628 u16 *pfc_prevention_tout) 1629 { 1630 struct mlx5e_priv *priv = netdev_priv(netdev); 1631 struct mlx5_core_dev *mdev = priv->mdev; 1632 1633 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1634 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1635 return -EOPNOTSUPP; 1636 1637 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL); 1638 } 1639 1640 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev, 1641 u16 pfc_preven) 1642 { 1643 struct mlx5e_priv *priv = netdev_priv(netdev); 1644 struct mlx5_core_dev *mdev = priv->mdev; 1645 u16 critical_tout; 1646 u16 minor; 1647 1648 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1649 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1650 return -EOPNOTSUPP; 1651 1652 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ? 1653 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC : 1654 pfc_preven; 1655 1656 if (critical_tout != PFC_STORM_PREVENTION_DISABLE && 1657 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC || 1658 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) { 1659 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n", 1660 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, 1661 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC); 1662 return -EINVAL; 1663 } 1664 1665 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout); 1666 return mlx5_set_port_stall_watermark(mdev, critical_tout, 1667 minor); 1668 } 1669 1670 static int mlx5e_get_tunable(struct net_device *dev, 1671 const struct ethtool_tunable *tuna, 1672 void *data) 1673 { 1674 int err; 1675 1676 switch (tuna->id) { 1677 case ETHTOOL_PFC_PREVENTION_TOUT: 1678 err = mlx5e_get_pfc_prevention_tout(dev, data); 1679 break; 1680 default: 1681 err = -EINVAL; 1682 break; 1683 } 1684 1685 return err; 1686 } 1687 1688 static int mlx5e_set_tunable(struct net_device *dev, 1689 const struct ethtool_tunable *tuna, 1690 const void *data) 1691 { 1692 struct mlx5e_priv *priv = netdev_priv(dev); 1693 int err; 1694 1695 mutex_lock(&priv->state_lock); 1696 1697 switch (tuna->id) { 1698 case ETHTOOL_PFC_PREVENTION_TOUT: 1699 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data); 1700 break; 1701 default: 1702 err = -EINVAL; 1703 break; 1704 } 1705 1706 mutex_unlock(&priv->state_lock); 1707 return err; 1708 } 1709 1710 static void mlx5e_get_pause_stats(struct net_device *netdev, 1711 struct ethtool_pause_stats *pause_stats) 1712 { 1713 struct mlx5e_priv *priv = netdev_priv(netdev); 1714 1715 mlx5e_stats_pause_get(priv, pause_stats); 1716 } 1717 1718 static void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1719 struct ethtool_pauseparam *pauseparam) 1720 { 1721 struct mlx5_core_dev *mdev = priv->mdev; 1722 int err; 1723 1724 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause, 1725 &pauseparam->tx_pause); 1726 if (err) { 1727 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n", 1728 __func__, err); 1729 } 1730 } 1731 1732 static void mlx5e_get_pauseparam(struct net_device *netdev, 1733 struct ethtool_pauseparam *pauseparam) 1734 { 1735 struct mlx5e_priv *priv = netdev_priv(netdev); 1736 1737 mlx5e_ethtool_get_pauseparam(priv, pauseparam); 1738 } 1739 1740 static int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1741 struct ethtool_pauseparam *pauseparam) 1742 { 1743 struct mlx5_core_dev *mdev = priv->mdev; 1744 int err; 1745 1746 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) 1747 return -EOPNOTSUPP; 1748 1749 if (pauseparam->autoneg) 1750 return -EINVAL; 1751 1752 err = mlx5_set_port_pause(mdev, 1753 pauseparam->rx_pause ? 1 : 0, 1754 pauseparam->tx_pause ? 1 : 0); 1755 if (err) { 1756 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n", 1757 __func__, err); 1758 } 1759 1760 return err; 1761 } 1762 1763 static int mlx5e_set_pauseparam(struct net_device *netdev, 1764 struct ethtool_pauseparam *pauseparam) 1765 { 1766 struct mlx5e_priv *priv = netdev_priv(netdev); 1767 1768 return mlx5e_ethtool_set_pauseparam(priv, pauseparam); 1769 } 1770 1771 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1772 struct kernel_ethtool_ts_info *info) 1773 { 1774 struct mlx5_core_dev *mdev = priv->mdev; 1775 1776 info->phc_index = mlx5_clock_get_ptp_index(mdev); 1777 1778 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 1779 info->phc_index == -1) 1780 return 0; 1781 1782 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | 1783 SOF_TIMESTAMPING_TX_SOFTWARE | 1784 SOF_TIMESTAMPING_RX_HARDWARE | 1785 SOF_TIMESTAMPING_RAW_HARDWARE; 1786 1787 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 1788 BIT(HWTSTAMP_TX_ON); 1789 1790 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1791 BIT(HWTSTAMP_FILTER_ALL); 1792 1793 return 0; 1794 } 1795 1796 static int mlx5e_get_ts_info(struct net_device *dev, 1797 struct kernel_ethtool_ts_info *info) 1798 { 1799 struct mlx5e_priv *priv = netdev_priv(dev); 1800 1801 return mlx5e_ethtool_get_ts_info(priv, info); 1802 } 1803 1804 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev) 1805 { 1806 __u32 ret = 0; 1807 1808 if (MLX5_CAP_GEN(mdev, wol_g)) 1809 ret |= WAKE_MAGIC; 1810 1811 if (MLX5_CAP_GEN(mdev, wol_s)) 1812 ret |= WAKE_MAGICSECURE; 1813 1814 if (MLX5_CAP_GEN(mdev, wol_a)) 1815 ret |= WAKE_ARP; 1816 1817 if (MLX5_CAP_GEN(mdev, wol_b)) 1818 ret |= WAKE_BCAST; 1819 1820 if (MLX5_CAP_GEN(mdev, wol_m)) 1821 ret |= WAKE_MCAST; 1822 1823 if (MLX5_CAP_GEN(mdev, wol_u)) 1824 ret |= WAKE_UCAST; 1825 1826 if (MLX5_CAP_GEN(mdev, wol_p)) 1827 ret |= WAKE_PHY; 1828 1829 return ret; 1830 } 1831 1832 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode) 1833 { 1834 __u32 ret = 0; 1835 1836 if (mode & MLX5_WOL_MAGIC) 1837 ret |= WAKE_MAGIC; 1838 1839 if (mode & MLX5_WOL_SECURED_MAGIC) 1840 ret |= WAKE_MAGICSECURE; 1841 1842 if (mode & MLX5_WOL_ARP) 1843 ret |= WAKE_ARP; 1844 1845 if (mode & MLX5_WOL_BROADCAST) 1846 ret |= WAKE_BCAST; 1847 1848 if (mode & MLX5_WOL_MULTICAST) 1849 ret |= WAKE_MCAST; 1850 1851 if (mode & MLX5_WOL_UNICAST) 1852 ret |= WAKE_UCAST; 1853 1854 if (mode & MLX5_WOL_PHY_ACTIVITY) 1855 ret |= WAKE_PHY; 1856 1857 return ret; 1858 } 1859 1860 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode) 1861 { 1862 u8 ret = 0; 1863 1864 if (mode & WAKE_MAGIC) 1865 ret |= MLX5_WOL_MAGIC; 1866 1867 if (mode & WAKE_MAGICSECURE) 1868 ret |= MLX5_WOL_SECURED_MAGIC; 1869 1870 if (mode & WAKE_ARP) 1871 ret |= MLX5_WOL_ARP; 1872 1873 if (mode & WAKE_BCAST) 1874 ret |= MLX5_WOL_BROADCAST; 1875 1876 if (mode & WAKE_MCAST) 1877 ret |= MLX5_WOL_MULTICAST; 1878 1879 if (mode & WAKE_UCAST) 1880 ret |= MLX5_WOL_UNICAST; 1881 1882 if (mode & WAKE_PHY) 1883 ret |= MLX5_WOL_PHY_ACTIVITY; 1884 1885 return ret; 1886 } 1887 1888 static void mlx5e_get_wol(struct net_device *netdev, 1889 struct ethtool_wolinfo *wol) 1890 { 1891 struct mlx5e_priv *priv = netdev_priv(netdev); 1892 struct mlx5_core_dev *mdev = priv->mdev; 1893 u8 mlx5_wol_mode; 1894 int err; 1895 1896 memset(wol, 0, sizeof(*wol)); 1897 1898 wol->supported = mlx5e_get_wol_supported(mdev); 1899 if (!wol->supported) 1900 return; 1901 1902 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode); 1903 if (err) 1904 return; 1905 1906 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode); 1907 } 1908 1909 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1910 { 1911 struct mlx5e_priv *priv = netdev_priv(netdev); 1912 struct mlx5_core_dev *mdev = priv->mdev; 1913 __u32 wol_supported = mlx5e_get_wol_supported(mdev); 1914 u32 mlx5_wol_mode; 1915 1916 if (!wol_supported) 1917 return -EOPNOTSUPP; 1918 1919 if (wol->wolopts & ~wol_supported) 1920 return -EINVAL; 1921 1922 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts); 1923 1924 return mlx5_set_port_wol(mdev, mlx5_wol_mode); 1925 } 1926 1927 static void mlx5e_get_fec_stats(struct net_device *netdev, 1928 struct ethtool_fec_stats *fec_stats, 1929 struct ethtool_fec_hist *hist) 1930 { 1931 struct mlx5e_priv *priv = netdev_priv(netdev); 1932 1933 mlx5e_stats_fec_get(priv, fec_stats, hist); 1934 } 1935 1936 static int mlx5e_get_fecparam(struct net_device *netdev, 1937 struct ethtool_fecparam *fecparam) 1938 { 1939 struct mlx5e_priv *priv = netdev_priv(netdev); 1940 struct mlx5_core_dev *mdev = priv->mdev; 1941 u16 fec_configured; 1942 u32 fec_active; 1943 int err; 1944 1945 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); 1946 1947 if (err) 1948 return err; 1949 1950 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active, 1951 sizeof(unsigned long) * BITS_PER_BYTE); 1952 1953 if (!fecparam->active_fec) 1954 return -EOPNOTSUPP; 1955 1956 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured, 1957 sizeof(unsigned long) * BITS_PER_BYTE); 1958 1959 return 0; 1960 } 1961 1962 static int mlx5e_set_fecparam(struct net_device *netdev, 1963 struct ethtool_fecparam *fecparam) 1964 { 1965 struct mlx5e_priv *priv = netdev_priv(netdev); 1966 struct mlx5_core_dev *mdev = priv->mdev; 1967 unsigned long fec_bitmap; 1968 u16 fec_policy = 0; 1969 int mode; 1970 int err; 1971 1972 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE); 1973 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1) 1974 return -EOPNOTSUPP; 1975 1976 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) { 1977 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec)) 1978 continue; 1979 fec_policy |= (1 << mode); 1980 break; 1981 } 1982 1983 err = mlx5e_set_fec_mode(mdev, fec_policy); 1984 1985 if (err) 1986 return err; 1987 1988 mlx5_toggle_port_link(mdev); 1989 1990 return 0; 1991 } 1992 1993 static int mlx5e_set_phys_id(struct net_device *dev, 1994 enum ethtool_phys_id_state state) 1995 { 1996 struct mlx5e_priv *priv = netdev_priv(dev); 1997 struct mlx5_core_dev *mdev = priv->mdev; 1998 u16 beacon_duration; 1999 2000 if (!MLX5_CAP_GEN(mdev, beacon_led)) 2001 return -EOPNOTSUPP; 2002 2003 switch (state) { 2004 case ETHTOOL_ID_ACTIVE: 2005 beacon_duration = MLX5_BEACON_DURATION_INF; 2006 break; 2007 case ETHTOOL_ID_INACTIVE: 2008 beacon_duration = MLX5_BEACON_DURATION_OFF; 2009 break; 2010 default: 2011 return -EOPNOTSUPP; 2012 } 2013 2014 return mlx5_set_port_beacon(mdev, beacon_duration); 2015 } 2016 2017 static int mlx5e_get_module_info(struct net_device *netdev, 2018 struct ethtool_modinfo *modinfo) 2019 { 2020 struct mlx5e_priv *priv = netdev_priv(netdev); 2021 struct mlx5_core_dev *dev = priv->mdev; 2022 int size_read = 0; 2023 u8 data[4] = {0}; 2024 2025 size_read = mlx5_query_module_eeprom(dev, 0, 2, data, NULL); 2026 if (size_read < 2) 2027 return -EIO; 2028 2029 /* data[0] = identifier byte */ 2030 switch (data[0]) { 2031 case MLX5_MODULE_ID_QSFP: 2032 modinfo->type = ETH_MODULE_SFF_8436; 2033 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 2034 break; 2035 case MLX5_MODULE_ID_QSFP_PLUS: 2036 case MLX5_MODULE_ID_QSFP28: 2037 /* data[1] = revision id */ 2038 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) { 2039 modinfo->type = ETH_MODULE_SFF_8636; 2040 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN; 2041 } else { 2042 modinfo->type = ETH_MODULE_SFF_8436; 2043 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 2044 } 2045 break; 2046 case MLX5_MODULE_ID_SFP: 2047 modinfo->type = ETH_MODULE_SFF_8472; 2048 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2049 break; 2050 default: 2051 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n", 2052 __func__, data[0]); 2053 return -EINVAL; 2054 } 2055 2056 return 0; 2057 } 2058 2059 static int mlx5e_get_module_eeprom(struct net_device *netdev, 2060 struct ethtool_eeprom *ee, 2061 u8 *data) 2062 { 2063 struct mlx5e_priv *priv = netdev_priv(netdev); 2064 struct mlx5_core_dev *mdev = priv->mdev; 2065 int offset = ee->offset; 2066 int size_read; 2067 u8 status = 0; 2068 int i = 0; 2069 2070 if (!ee->len) 2071 return -EINVAL; 2072 2073 memset(data, 0, ee->len); 2074 2075 while (i < ee->len) { 2076 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i, 2077 data + i, &status); 2078 if (!size_read) 2079 /* Done reading */ 2080 return 0; 2081 2082 if (size_read < 0) { 2083 netdev_err(netdev, 2084 "%s: mlx5_query_eeprom failed:0x%x, status %u\n", 2085 __func__, size_read, status); 2086 return size_read; 2087 } 2088 2089 i += size_read; 2090 offset += size_read; 2091 } 2092 2093 return 0; 2094 } 2095 2096 static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev, 2097 const struct ethtool_module_eeprom *page_data, 2098 struct netlink_ext_ack *extack) 2099 { 2100 struct mlx5e_priv *priv = netdev_priv(netdev); 2101 struct mlx5_module_eeprom_query_params query; 2102 struct mlx5_core_dev *mdev = priv->mdev; 2103 u8 *data = page_data->data; 2104 int size_read; 2105 u8 status = 0; 2106 int i = 0; 2107 2108 if (!page_data->length) 2109 return -EINVAL; 2110 2111 memset(data, 0, page_data->length); 2112 2113 query.offset = page_data->offset; 2114 query.i2c_address = page_data->i2c_address; 2115 query.bank = page_data->bank; 2116 query.page = page_data->page; 2117 while (i < page_data->length) { 2118 query.size = page_data->length - i; 2119 size_read = mlx5_query_module_eeprom_by_page(mdev, &query, 2120 data + i, &status); 2121 2122 /* Done reading, return how many bytes was read */ 2123 if (!size_read) 2124 return i; 2125 2126 if (size_read < 0) { 2127 NL_SET_ERR_MSG_FMT_MOD( 2128 extack, 2129 "Query module eeprom by page failed, read %u bytes, err %d, status %u", 2130 i, size_read, status); 2131 return size_read; 2132 } 2133 2134 i += size_read; 2135 query.offset += size_read; 2136 } 2137 2138 return i; 2139 } 2140 2141 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 2142 struct ethtool_flash *flash) 2143 { 2144 struct mlx5_core_dev *mdev = priv->mdev; 2145 struct net_device *dev = priv->netdev; 2146 const struct firmware *fw; 2147 int err; 2148 2149 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 2150 return -EOPNOTSUPP; 2151 2152 err = request_firmware_direct(&fw, flash->data, &dev->dev); 2153 if (err) 2154 return err; 2155 2156 err = mlx5_firmware_flash(mdev, fw, NULL); 2157 release_firmware(fw); 2158 2159 return err; 2160 } 2161 2162 static int mlx5e_flash_device(struct net_device *dev, 2163 struct ethtool_flash *flash) 2164 { 2165 struct mlx5e_priv *priv = netdev_priv(dev); 2166 2167 return mlx5e_ethtool_flash_device(priv, flash); 2168 } 2169 2170 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable, 2171 bool is_rx_cq) 2172 { 2173 struct mlx5e_priv *priv = netdev_priv(netdev); 2174 u8 cq_period_mode, current_cq_period_mode; 2175 struct mlx5e_params new_params; 2176 2177 if (enable && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 2178 return -EOPNOTSUPP; 2179 2180 cq_period_mode = mlx5e_dim_cq_period_mode(enable); 2181 2182 current_cq_period_mode = is_rx_cq ? 2183 priv->channels.params.rx_cq_moderation.cq_period_mode : 2184 priv->channels.params.tx_cq_moderation.cq_period_mode; 2185 2186 if (cq_period_mode == current_cq_period_mode) 2187 return 0; 2188 2189 new_params = priv->channels.params; 2190 if (is_rx_cq) { 2191 mlx5e_reset_rx_channels_moderation(&priv->channels, cq_period_mode, 2192 false, true); 2193 mlx5e_channels_rx_toggle_dim(&priv->channels); 2194 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_BASED_MODER, 2195 cq_period_mode); 2196 } else { 2197 mlx5e_reset_tx_channels_moderation(&priv->channels, cq_period_mode, 2198 false, true); 2199 mlx5e_channels_tx_toggle_dim(&priv->channels); 2200 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_CQE_BASED_MODER, 2201 cq_period_mode); 2202 } 2203 2204 /* Update pflags of existing channels without resetting them */ 2205 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, false); 2206 } 2207 2208 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable) 2209 { 2210 return set_pflag_cqe_based_moder(netdev, enable, false); 2211 } 2212 2213 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) 2214 { 2215 return set_pflag_cqe_based_moder(netdev, enable, true); 2216 } 2217 2218 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter) 2219 { 2220 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS); 2221 struct mlx5e_params new_params; 2222 int err = 0; 2223 2224 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 2225 return new_val ? -EOPNOTSUPP : 0; 2226 2227 if (curr_val == new_val) 2228 return 0; 2229 2230 if (new_val && !mlx5e_profile_feature_cap(priv->profile, PTP_RX) && rx_filter) { 2231 netdev_err(priv->netdev, 2232 "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n"); 2233 return -EINVAL; 2234 } 2235 2236 if (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 2237 netdev_warn(priv->netdev, "Can't set CQE compression with HW-GRO, disable it first.\n"); 2238 return -EINVAL; 2239 } 2240 2241 new_params = priv->channels.params; 2242 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); 2243 if (rx_filter) 2244 new_params.ptp_rx = new_val; 2245 2246 if (new_params.ptp_rx == priv->channels.params.ptp_rx) 2247 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 2248 else 2249 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx, 2250 &new_params.ptp_rx, true); 2251 if (err) 2252 return err; 2253 2254 netdev_dbg(priv->netdev, "MLX5E: RxCqeCmprss was turned %s\n", 2255 MLX5E_GET_PFLAG(&priv->channels.params, 2256 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF"); 2257 2258 return 0; 2259 } 2260 2261 static int set_pflag_rx_cqe_compress(struct net_device *netdev, 2262 bool enable) 2263 { 2264 struct mlx5e_priv *priv = netdev_priv(netdev); 2265 struct mlx5_core_dev *mdev = priv->mdev; 2266 bool rx_filter; 2267 int err; 2268 2269 if (!MLX5_CAP_GEN(mdev, cqe_compression)) 2270 return -EOPNOTSUPP; 2271 2272 rx_filter = priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE; 2273 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter); 2274 if (err) 2275 return err; 2276 2277 priv->channels.params.rx_cqe_compress_def = enable; 2278 2279 return 0; 2280 } 2281 2282 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable) 2283 { 2284 struct mlx5e_priv *priv = netdev_priv(netdev); 2285 struct mlx5_core_dev *mdev = priv->mdev; 2286 struct mlx5e_params new_params; 2287 2288 if (enable) { 2289 /* Checking the regular RQ here; mlx5e_validate_xsk_param called 2290 * from mlx5e_open_xsk will check for each XSK queue, and 2291 * mlx5e_safe_switch_params will be reverted if any check fails. 2292 */ 2293 int err = mlx5e_mpwrq_validate_regular(mdev, &priv->channels.params); 2294 2295 if (err) 2296 return err; 2297 } else if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) { 2298 netdev_warn(netdev, "Can't set legacy RQ with HW-GRO/LRO, disable them first\n"); 2299 return -EINVAL; 2300 } 2301 2302 new_params = priv->channels.params; 2303 2304 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ, enable); 2305 mlx5e_set_rq_type(mdev, &new_params); 2306 2307 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 2308 } 2309 2310 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable) 2311 { 2312 struct mlx5e_priv *priv = netdev_priv(netdev); 2313 struct mlx5e_channels *channels = &priv->channels; 2314 struct mlx5e_channel *c; 2315 int i; 2316 2317 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || 2318 priv->channels.params.xdp_prog) 2319 return 0; 2320 2321 for (i = 0; i < channels->num; i++) { 2322 c = channels->c[i]; 2323 if (enable) 2324 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 2325 else 2326 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 2327 } 2328 2329 return 0; 2330 } 2331 2332 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable) 2333 { 2334 struct mlx5e_priv *priv = netdev_priv(netdev); 2335 struct mlx5_core_dev *mdev = priv->mdev; 2336 struct mlx5e_params new_params; 2337 2338 if (enable && !mlx5e_tx_mpwqe_supported(mdev)) 2339 return -EOPNOTSUPP; 2340 2341 new_params = priv->channels.params; 2342 2343 MLX5E_SET_PFLAG(&new_params, flag, enable); 2344 2345 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 2346 } 2347 2348 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable) 2349 { 2350 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable); 2351 } 2352 2353 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable) 2354 { 2355 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable); 2356 } 2357 2358 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable) 2359 { 2360 struct mlx5e_priv *priv = netdev_priv(netdev); 2361 struct mlx5_core_dev *mdev = priv->mdev; 2362 struct mlx5e_params new_params; 2363 int err; 2364 2365 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) || 2366 !MLX5_CAP_GEN_2(mdev, ts_cqe_metadata_size2wqe_counter)) 2367 return -EOPNOTSUPP; 2368 2369 /* Don't allow changing the PTP state if HTB offload is active, because 2370 * the numeration of the QoS SQs will change, while per-queue qdiscs are 2371 * attached. 2372 */ 2373 if (mlx5e_selq_is_htb_enabled(&priv->selq)) { 2374 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n", 2375 __func__); 2376 return -EINVAL; 2377 } 2378 2379 new_params = priv->channels.params; 2380 /* Don't allow enabling TX-port-TS if MQPRIO mode channel offload is 2381 * active, since it defines explicitly which TC accepts the packet. 2382 * This conflicts with TX-port-TS hijacking the PTP traffic to a specific 2383 * HW TX-queue. 2384 */ 2385 if (enable && new_params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { 2386 netdev_err(priv->netdev, 2387 "%s: MQPRIO mode channel offload is active, cannot set the TX-port-TS\n", 2388 __func__); 2389 return -EINVAL; 2390 } 2391 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable); 2392 /* No need to verify SQ stop room as 2393 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both 2394 * has the same log_sq_size. 2395 */ 2396 2397 err = mlx5e_safe_switch_params(priv, &new_params, 2398 mlx5e_update_tc_and_tx_queues_ctx, NULL, true); 2399 if (!err) 2400 priv->tx_ptp_opened = true; 2401 2402 return err; 2403 } 2404 2405 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = { 2406 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder }, 2407 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder }, 2408 { "rx_cqe_compress", set_pflag_rx_cqe_compress }, 2409 { "rx_striding_rq", set_pflag_rx_striding_rq }, 2410 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete }, 2411 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe }, 2412 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe }, 2413 { "tx_port_ts", set_pflag_tx_port_ts }, 2414 }; 2415 2416 static int mlx5e_handle_pflag(struct net_device *netdev, 2417 u32 wanted_flags, 2418 enum mlx5e_priv_flag flag) 2419 { 2420 struct mlx5e_priv *priv = netdev_priv(netdev); 2421 bool enable = !!(wanted_flags & BIT(flag)); 2422 u32 changes = wanted_flags ^ priv->channels.params.pflags; 2423 int err; 2424 2425 if (!(changes & BIT(flag))) 2426 return 0; 2427 2428 err = mlx5e_priv_flags[flag].handler(netdev, enable); 2429 if (err) { 2430 netdev_err(netdev, "%s private flag '%s' failed err %d\n", 2431 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err); 2432 return err; 2433 } 2434 2435 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable); 2436 return 0; 2437 } 2438 2439 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) 2440 { 2441 struct mlx5e_priv *priv = netdev_priv(netdev); 2442 enum mlx5e_priv_flag pflag; 2443 int err; 2444 2445 mutex_lock(&priv->state_lock); 2446 2447 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) { 2448 err = mlx5e_handle_pflag(netdev, pflags, pflag); 2449 if (err) 2450 break; 2451 } 2452 2453 mutex_unlock(&priv->state_lock); 2454 2455 /* Need to fix some features.. */ 2456 netdev_update_features(netdev); 2457 2458 return err; 2459 } 2460 2461 static u32 mlx5e_get_priv_flags(struct net_device *netdev) 2462 { 2463 struct mlx5e_priv *priv = netdev_priv(netdev); 2464 2465 return priv->channels.params.pflags; 2466 } 2467 2468 static int mlx5e_get_rxfh_fields(struct net_device *dev, 2469 struct ethtool_rxfh_fields *info) 2470 { 2471 struct mlx5e_priv *priv = netdev_priv(dev); 2472 2473 return mlx5e_ethtool_get_rxfh_fields(priv, info); 2474 } 2475 2476 static int mlx5e_set_rxfh_fields(struct net_device *dev, 2477 const struct ethtool_rxfh_fields *cmd, 2478 struct netlink_ext_ack *extack) 2479 { 2480 struct mlx5e_priv *priv = netdev_priv(dev); 2481 2482 return mlx5e_ethtool_set_rxfh_fields(priv, cmd, extack); 2483 } 2484 2485 static u32 mlx5e_get_rx_ring_count(struct net_device *dev) 2486 { 2487 struct mlx5e_priv *priv = netdev_priv(dev); 2488 2489 return priv->channels.params.num_channels; 2490 } 2491 2492 static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2493 u32 *rule_locs) 2494 { 2495 struct mlx5e_priv *priv = netdev_priv(dev); 2496 2497 return mlx5e_ethtool_get_rxnfc(priv, info, rule_locs); 2498 } 2499 2500 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2501 { 2502 struct mlx5e_priv *priv = netdev_priv(dev); 2503 2504 return mlx5e_ethtool_set_rxnfc(priv, cmd); 2505 } 2506 2507 static int query_port_status_opcode(struct mlx5_core_dev *mdev, u32 *status_opcode) 2508 { 2509 struct mlx5_ifc_pddr_troubleshooting_page_bits *pddr_troubleshooting_page; 2510 u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {}; 2511 u32 out[MLX5_ST_SZ_DW(pddr_reg)]; 2512 int err; 2513 2514 MLX5_SET(pddr_reg, in, local_port, 1); 2515 MLX5_SET(pddr_reg, in, page_select, 2516 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE); 2517 2518 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, in, page_data); 2519 MLX5_SET(pddr_troubleshooting_page, pddr_troubleshooting_page, 2520 group_opcode, MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR); 2521 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 2522 sizeof(out), MLX5_REG_PDDR, 0, 0); 2523 if (err) 2524 return err; 2525 2526 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, out, page_data); 2527 *status_opcode = MLX5_GET(pddr_troubleshooting_page, pddr_troubleshooting_page, 2528 status_opcode); 2529 return 0; 2530 } 2531 2532 struct mlx5e_ethtool_link_ext_state_opcode_mapping { 2533 u32 status_opcode; 2534 enum ethtool_link_ext_state link_ext_state; 2535 u8 link_ext_substate; 2536 }; 2537 2538 static const struct mlx5e_ethtool_link_ext_state_opcode_mapping 2539 mlx5e_link_ext_state_opcode_map[] = { 2540 /* States relating to the autonegotiation or issues therein */ 2541 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2542 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED}, 2543 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2544 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED}, 2545 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2546 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED}, 2547 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2548 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE}, 2549 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2550 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE}, 2551 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2552 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD}, 2553 2554 /* Failure during link training */ 2555 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2556 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED}, 2557 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2558 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT}, 2559 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2560 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY}, 2561 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0}, 2562 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2563 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT}, 2564 2565 /* Logical mismatch in physical coding sublayer or forward error correction sublayer */ 2566 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2567 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK}, 2568 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2569 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK}, 2570 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2571 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS}, 2572 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2573 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED}, 2574 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2575 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED}, 2576 2577 /* Signal integrity issues */ 2578 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0}, 2579 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 2580 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS}, 2581 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 2582 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE}, 2583 2584 /* No cable connected */ 2585 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0}, 2586 2587 /* Failure is related to cable, e.g., unsupported cable */ 2588 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2589 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2590 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2591 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2592 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2593 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2594 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2595 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2596 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2597 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2598 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0}, 2599 2600 /* Failure is related to EEPROM, e.g., failure during reading or parsing the data */ 2601 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0}, 2602 2603 /* Failure during calibration algorithm */ 2604 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0}, 2605 2606 /* The hardware is not able to provide the power required from cable or module */ 2607 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0}, 2608 2609 /* The module is overheated */ 2610 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0}, 2611 }; 2612 2613 static void 2614 mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping 2615 link_ext_state_mapping, 2616 struct ethtool_link_ext_state_info *link_ext_state_info) 2617 { 2618 switch (link_ext_state_mapping.link_ext_state) { 2619 case ETHTOOL_LINK_EXT_STATE_AUTONEG: 2620 link_ext_state_info->autoneg = 2621 link_ext_state_mapping.link_ext_substate; 2622 break; 2623 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE: 2624 link_ext_state_info->link_training = 2625 link_ext_state_mapping.link_ext_substate; 2626 break; 2627 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH: 2628 link_ext_state_info->link_logical_mismatch = 2629 link_ext_state_mapping.link_ext_substate; 2630 break; 2631 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY: 2632 link_ext_state_info->bad_signal_integrity = 2633 link_ext_state_mapping.link_ext_substate; 2634 break; 2635 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE: 2636 link_ext_state_info->cable_issue = 2637 link_ext_state_mapping.link_ext_substate; 2638 break; 2639 default: 2640 break; 2641 } 2642 2643 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state; 2644 } 2645 2646 static int 2647 mlx5e_get_link_ext_state(struct net_device *dev, 2648 struct ethtool_link_ext_state_info *link_ext_state_info) 2649 { 2650 struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping; 2651 struct mlx5e_priv *priv = netdev_priv(dev); 2652 u32 status_opcode = 0; 2653 int i; 2654 2655 /* Exit without data if the interface state is OK, since no extended data is 2656 * available in such case 2657 */ 2658 if (netif_carrier_ok(dev)) 2659 return -ENODATA; 2660 2661 if (query_port_status_opcode(priv->mdev, &status_opcode) || 2662 !status_opcode) 2663 return -ENODATA; 2664 2665 for (i = 0; i < ARRAY_SIZE(mlx5e_link_ext_state_opcode_map); i++) { 2666 link_ext_state_mapping = mlx5e_link_ext_state_opcode_map[i]; 2667 if (link_ext_state_mapping.status_opcode == status_opcode) { 2668 mlx5e_set_link_ext_state(link_ext_state_mapping, 2669 link_ext_state_info); 2670 return 0; 2671 } 2672 } 2673 2674 return -ENODATA; 2675 } 2676 2677 static void mlx5e_get_eth_phy_stats(struct net_device *netdev, 2678 struct ethtool_eth_phy_stats *phy_stats) 2679 { 2680 struct mlx5e_priv *priv = netdev_priv(netdev); 2681 2682 mlx5e_stats_eth_phy_get(priv, phy_stats); 2683 } 2684 2685 static void mlx5e_get_eth_mac_stats(struct net_device *netdev, 2686 struct ethtool_eth_mac_stats *mac_stats) 2687 { 2688 struct mlx5e_priv *priv = netdev_priv(netdev); 2689 2690 mlx5e_stats_eth_mac_get(priv, mac_stats); 2691 } 2692 2693 static void mlx5e_get_eth_ctrl_stats(struct net_device *netdev, 2694 struct ethtool_eth_ctrl_stats *ctrl_stats) 2695 { 2696 struct mlx5e_priv *priv = netdev_priv(netdev); 2697 2698 mlx5e_stats_eth_ctrl_get(priv, ctrl_stats); 2699 } 2700 2701 static void mlx5e_get_rmon_stats(struct net_device *netdev, 2702 struct ethtool_rmon_stats *rmon_stats, 2703 const struct ethtool_rmon_hist_range **ranges) 2704 { 2705 struct mlx5e_priv *priv = netdev_priv(netdev); 2706 2707 mlx5e_stats_rmon_get(priv, rmon_stats, ranges); 2708 } 2709 2710 static void mlx5e_get_ts_stats(struct net_device *netdev, 2711 struct ethtool_ts_stats *ts_stats) 2712 { 2713 struct mlx5e_priv *priv = netdev_priv(netdev); 2714 2715 mlx5e_stats_ts_get(priv, ts_stats); 2716 } 2717 2718 const struct ethtool_ops mlx5e_ethtool_ops = { 2719 .cap_link_lanes_supported = true, 2720 .rxfh_per_ctx_fields = true, 2721 .rxfh_per_ctx_key = true, 2722 .rxfh_max_num_contexts = MLX5E_MAX_NUM_RSS, 2723 .op_needs_rtnl = ETHTOOL_OP_NEEDS_RTNL_SCHANNELS | 2724 ETHTOOL_OP_NEEDS_RTNL_SRINGPARAM | 2725 ETHTOOL_OP_NEEDS_RTNL_SPFLAGS | 2726 ETHTOOL_OP_NEEDS_RTNL_GLINK, 2727 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2728 ETHTOOL_COALESCE_MAX_FRAMES | 2729 ETHTOOL_COALESCE_USE_ADAPTIVE | 2730 ETHTOOL_COALESCE_USE_CQE, 2731 .supported_input_xfrm = RXH_XFRM_SYM_OR_XOR, 2732 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT | 2733 ETHTOOL_RING_USE_HDS_THRS, 2734 .rxfh_indir_space = MLX5E_MAX_INDIR_RQT_SIZE, 2735 .get_drvinfo = mlx5e_get_drvinfo, 2736 .get_link = ethtool_op_get_link, 2737 .get_link_ext_state = mlx5e_get_link_ext_state, 2738 .get_strings = mlx5e_get_strings, 2739 .get_sset_count = mlx5e_get_sset_count, 2740 .get_ethtool_stats = mlx5e_get_ethtool_stats, 2741 .get_ringparam = mlx5e_get_ringparam, 2742 .set_ringparam = mlx5e_set_ringparam, 2743 .get_channels = mlx5e_get_channels, 2744 .set_channels = mlx5e_set_channels, 2745 .get_coalesce = mlx5e_get_coalesce, 2746 .set_coalesce = mlx5e_set_coalesce, 2747 .get_per_queue_coalesce = mlx5e_get_per_queue_coalesce, 2748 .set_per_queue_coalesce = mlx5e_set_per_queue_coalesce, 2749 .get_link_ksettings = mlx5e_get_link_ksettings, 2750 .set_link_ksettings = mlx5e_set_link_ksettings, 2751 .get_rxfh_key_size = mlx5e_get_rxfh_key_size, 2752 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size, 2753 .get_rxfh = mlx5e_get_rxfh, 2754 .set_rxfh = mlx5e_set_rxfh, 2755 .get_rxfh_fields = mlx5e_get_rxfh_fields, 2756 .set_rxfh_fields = mlx5e_set_rxfh_fields, 2757 .create_rxfh_context = mlx5e_create_rxfh_context, 2758 .modify_rxfh_context = mlx5e_modify_rxfh_context, 2759 .remove_rxfh_context = mlx5e_remove_rxfh_context, 2760 .get_rxnfc = mlx5e_get_rxnfc, 2761 .set_rxnfc = mlx5e_set_rxnfc, 2762 .get_rx_ring_count = mlx5e_get_rx_ring_count, 2763 .get_tunable = mlx5e_get_tunable, 2764 .set_tunable = mlx5e_set_tunable, 2765 .get_pause_stats = mlx5e_get_pause_stats, 2766 .get_pauseparam = mlx5e_get_pauseparam, 2767 .set_pauseparam = mlx5e_set_pauseparam, 2768 .get_ts_info = mlx5e_get_ts_info, 2769 .set_phys_id = mlx5e_set_phys_id, 2770 .get_wol = mlx5e_get_wol, 2771 .set_wol = mlx5e_set_wol, 2772 .get_module_info = mlx5e_get_module_info, 2773 .get_module_eeprom = mlx5e_get_module_eeprom, 2774 .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page, 2775 .flash_device = mlx5e_flash_device, 2776 .get_priv_flags = mlx5e_get_priv_flags, 2777 .set_priv_flags = mlx5e_set_priv_flags, 2778 .self_test = mlx5e_self_test, 2779 .get_fec_stats = mlx5e_get_fec_stats, 2780 .get_fecparam = mlx5e_get_fecparam, 2781 .set_fecparam = mlx5e_set_fecparam, 2782 .get_eth_phy_stats = mlx5e_get_eth_phy_stats, 2783 .get_eth_mac_stats = mlx5e_get_eth_mac_stats, 2784 .get_eth_ctrl_stats = mlx5e_get_eth_ctrl_stats, 2785 .get_rmon_stats = mlx5e_get_rmon_stats, 2786 .get_ts_stats = mlx5e_get_ts_stats, 2787 .get_link_ext_stats = mlx5e_get_link_ext_stats 2788 }; 2789