xref: /linux/drivers/gpu/drm/radeon/rs400.c (revision 28f587adb69957125241a8df359b68b134f3c4a1)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/slab.h>
32 
33 #include <drm/drm_device.h>
34 #include <drm/drm_file.h>
35 
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "rs400d.h"
39 
40 /* This files gather functions specifics to : rs400,rs480 */
41 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
42 
rs400_gart_adjust_size(struct radeon_device * rdev)43 void rs400_gart_adjust_size(struct radeon_device *rdev)
44 {
45 	/* Check gart size */
46 	switch (rdev->mc.gtt_size/(1024*1024)) {
47 	case 32:
48 	case 64:
49 	case 128:
50 	case 256:
51 	case 512:
52 	case 1024:
53 	case 2048:
54 		break;
55 	default:
56 		DRM_ERROR("Unable to use IGP GART size %uM\n",
57 			  (unsigned)(rdev->mc.gtt_size >> 20));
58 		DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
59 		DRM_ERROR("Forcing to 32M GART size\n");
60 		rdev->mc.gtt_size = 32 * 1024 * 1024;
61 		return;
62 	}
63 }
64 
rs400_gart_tlb_flush(struct radeon_device * rdev)65 void rs400_gart_tlb_flush(struct radeon_device *rdev)
66 {
67 	uint32_t tmp;
68 	unsigned int timeout = rdev->usec_timeout;
69 
70 	WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
71 	do {
72 		tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
73 		if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
74 			break;
75 		udelay(1);
76 		timeout--;
77 	} while (timeout > 0);
78 	WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
79 }
80 
rs400_gart_init(struct radeon_device * rdev)81 int rs400_gart_init(struct radeon_device *rdev)
82 {
83 	int r;
84 
85 	if (rdev->gart.ptr) {
86 		WARN(1, "RS400 GART already initialized\n");
87 		return 0;
88 	}
89 	/* Check gart size */
90 	switch (rdev->mc.gtt_size / (1024 * 1024)) {
91 	case 32:
92 	case 64:
93 	case 128:
94 	case 256:
95 	case 512:
96 	case 1024:
97 	case 2048:
98 		break;
99 	default:
100 		return -EINVAL;
101 	}
102 	/* Initialize common gart structure */
103 	r = radeon_gart_init(rdev);
104 	if (r)
105 		return r;
106 	rs400_debugfs_pcie_gart_info_init(rdev);
107 	rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
108 	return radeon_gart_table_ram_alloc(rdev);
109 }
110 
rs400_gart_enable(struct radeon_device * rdev)111 int rs400_gart_enable(struct radeon_device *rdev)
112 {
113 	uint32_t size_reg;
114 	uint32_t tmp;
115 
116 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
117 	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
118 	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
119 	/* Check gart size */
120 	switch (rdev->mc.gtt_size / (1024 * 1024)) {
121 	case 32:
122 		size_reg = RS480_VA_SIZE_32MB;
123 		break;
124 	case 64:
125 		size_reg = RS480_VA_SIZE_64MB;
126 		break;
127 	case 128:
128 		size_reg = RS480_VA_SIZE_128MB;
129 		break;
130 	case 256:
131 		size_reg = RS480_VA_SIZE_256MB;
132 		break;
133 	case 512:
134 		size_reg = RS480_VA_SIZE_512MB;
135 		break;
136 	case 1024:
137 		size_reg = RS480_VA_SIZE_1GB;
138 		break;
139 	case 2048:
140 		size_reg = RS480_VA_SIZE_2GB;
141 		break;
142 	default:
143 		return -EINVAL;
144 	}
145 	/* It should be fine to program it to max value */
146 	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
147 		WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
148 		WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
149 	} else {
150 		WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
151 		WREG32(RS480_AGP_BASE_2, 0);
152 	}
153 	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
154 	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
155 	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
156 		WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
157 		tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
158 		WREG32(RADEON_BUS_CNTL, tmp);
159 	} else {
160 		WREG32(RADEON_MC_AGP_LOCATION, tmp);
161 		tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
162 		WREG32(RADEON_BUS_CNTL, tmp);
163 	}
164 	/* Table should be in 32bits address space so ignore bits above. */
165 	tmp = (u32)rdev->gart.table_addr & 0xfffff000;
166 	tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
167 
168 	WREG32_MC(RS480_GART_BASE, tmp);
169 	/* TODO: more tweaking here */
170 	WREG32_MC(RS480_GART_FEATURE_ID,
171 		  (RS480_TLB_ENABLE |
172 		   RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
173 	/* Disable snooping */
174 	WREG32_MC(RS480_AGP_MODE_CNTL,
175 		  (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
176 	/* Disable AGP mode */
177 	/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
178 	 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
179 	if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
180 		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
181 		tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
182 		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
183 	} else {
184 		tmp = RREG32_MC(RS480_MC_MISC_CNTL);
185 		tmp |= RS480_GART_INDEX_REG_EN;
186 		WREG32_MC(RS480_MC_MISC_CNTL, tmp);
187 	}
188 	/* Enable gart */
189 	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
190 	rs400_gart_tlb_flush(rdev);
191 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
192 		 (unsigned)(rdev->mc.gtt_size >> 20),
193 		 (unsigned long long)rdev->gart.table_addr);
194 	rdev->gart.ready = true;
195 	return 0;
196 }
197 
rs400_gart_disable(struct radeon_device * rdev)198 void rs400_gart_disable(struct radeon_device *rdev)
199 {
200 	uint32_t tmp;
201 
202 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
203 	tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
204 	WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
205 	WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
206 }
207 
rs400_gart_fini(struct radeon_device * rdev)208 void rs400_gart_fini(struct radeon_device *rdev)
209 {
210 	radeon_gart_fini(rdev);
211 	rs400_gart_disable(rdev);
212 	radeon_gart_table_ram_free(rdev);
213 }
214 
215 #define RS400_PTE_UNSNOOPED (1 << 0)
216 #define RS400_PTE_WRITEABLE (1 << 2)
217 #define RS400_PTE_READABLE  (1 << 3)
218 
rs400_gart_get_page_entry(uint64_t addr,uint32_t flags)219 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
220 {
221 	uint32_t entry;
222 
223 	entry = (lower_32_bits(addr) & PAGE_MASK) |
224 		((upper_32_bits(addr) & 0xff) << 4);
225 	if (flags & RADEON_GART_PAGE_READ)
226 		entry |= RS400_PTE_READABLE;
227 	if (flags & RADEON_GART_PAGE_WRITE)
228 		entry |= RS400_PTE_WRITEABLE;
229 	if (!(flags & RADEON_GART_PAGE_SNOOP))
230 		entry |= RS400_PTE_UNSNOOPED;
231 	return entry;
232 }
233 
rs400_gart_set_page(struct radeon_device * rdev,unsigned i,uint64_t entry)234 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
235 			 uint64_t entry)
236 {
237 	u32 *gtt = rdev->gart.ptr;
238 	gtt[i] = cpu_to_le32(lower_32_bits(entry));
239 }
240 
rs400_mc_wait_for_idle(struct radeon_device * rdev)241 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
242 {
243 	unsigned i;
244 	uint32_t tmp;
245 
246 	for (i = 0; i < rdev->usec_timeout; i++) {
247 		/* read MC_STATUS */
248 		tmp = RREG32(RADEON_MC_STATUS);
249 		if (tmp & RADEON_MC_IDLE) {
250 			return 0;
251 		}
252 		udelay(1);
253 	}
254 	return -1;
255 }
256 
rs400_gpu_init(struct radeon_device * rdev)257 static void rs400_gpu_init(struct radeon_device *rdev)
258 {
259 	/* Earlier code was calling r420_pipes_init and then
260 	 * rs400_mc_wait_for_idle(rdev). The problem is that
261 	 * at least on my Mobility Radeon Xpress 200M RC410 card
262 	 * that ends up in this code path ends up num_gb_pipes == 3
263 	 * while the card seems to have only one pipe. With the
264 	 * r420 pipe initialization method.
265 	 *
266 	 * Problems shown up as HyperZ glitches, see:
267 	 * https://bugs.freedesktop.org/show_bug.cgi?id=110897
268 	 *
269 	 * Delegating initialization to r300 code seems to work
270 	 * and results in proper pipe numbers. The rs400 cards
271 	 * are said to be not r400, but r300 kind of cards.
272 	 */
273 	r300_gpu_init(rdev);
274 
275 	if (rs400_mc_wait_for_idle(rdev)) {
276 		pr_warn("rs400: Failed to wait MC idle while programming pipes. Bad things might happen. %08x\n",
277 			RREG32(RADEON_MC_STATUS));
278 	}
279 }
280 
rs400_mc_init(struct radeon_device * rdev)281 static void rs400_mc_init(struct radeon_device *rdev)
282 {
283 	u64 base;
284 
285 	rs400_gart_adjust_size(rdev);
286 	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
287 	/* DDR for all card after R300 & IGP */
288 	rdev->mc.vram_is_ddr = true;
289 	rdev->mc.vram_width = 128;
290 	r100_vram_init_sizes(rdev);
291 	base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
292 	radeon_vram_location(rdev, &rdev->mc, base);
293 	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
294 	radeon_gtt_location(rdev, &rdev->mc);
295 	radeon_update_bandwidth_info(rdev);
296 }
297 
rs400_mc_rreg(struct radeon_device * rdev,uint32_t reg)298 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
299 {
300 	unsigned long flags;
301 	uint32_t r;
302 
303 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
304 	WREG32(RS480_NB_MC_INDEX, reg & 0xff);
305 	r = RREG32(RS480_NB_MC_DATA);
306 	WREG32(RS480_NB_MC_INDEX, 0xff);
307 	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
308 	return r;
309 }
310 
rs400_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)311 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
312 {
313 	unsigned long flags;
314 
315 	spin_lock_irqsave(&rdev->mc_idx_lock, flags);
316 	WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
317 	WREG32(RS480_NB_MC_DATA, (v));
318 	WREG32(RS480_NB_MC_INDEX, 0xff);
319 	spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
320 }
321 
322 #if defined(CONFIG_DEBUG_FS)
rs400_debugfs_gart_info_show(struct seq_file * m,void * unused)323 static int rs400_debugfs_gart_info_show(struct seq_file *m, void *unused)
324 {
325 	struct radeon_device *rdev = m->private;
326 	uint32_t tmp;
327 
328 	tmp = RREG32(RADEON_HOST_PATH_CNTL);
329 	seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
330 	tmp = RREG32(RADEON_BUS_CNTL);
331 	seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
332 	tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
333 	seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
334 	if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
335 		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
336 		seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
337 		tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
338 		seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
339 		tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
340 		seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
341 		tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
342 		seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
343 		tmp = RREG32(RS690_HDP_FB_LOCATION);
344 		seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
345 	} else {
346 		tmp = RREG32(RADEON_AGP_BASE);
347 		seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
348 		tmp = RREG32(RS480_AGP_BASE_2);
349 		seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
350 		tmp = RREG32(RADEON_MC_AGP_LOCATION);
351 		seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
352 	}
353 	tmp = RREG32_MC(RS480_GART_BASE);
354 	seq_printf(m, "GART_BASE 0x%08x\n", tmp);
355 	tmp = RREG32_MC(RS480_GART_FEATURE_ID);
356 	seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
357 	tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
358 	seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
359 	tmp = RREG32_MC(RS480_MC_MISC_CNTL);
360 	seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
361 	tmp = RREG32_MC(0x5F);
362 	seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
363 	tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
364 	seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
365 	tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
366 	seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
367 	tmp = RREG32_MC(0x3B);
368 	seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
369 	tmp = RREG32_MC(0x3C);
370 	seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
371 	tmp = RREG32_MC(0x30);
372 	seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
373 	tmp = RREG32_MC(0x31);
374 	seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
375 	tmp = RREG32_MC(0x32);
376 	seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
377 	tmp = RREG32_MC(0x33);
378 	seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
379 	tmp = RREG32_MC(0x34);
380 	seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
381 	tmp = RREG32_MC(0x35);
382 	seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
383 	tmp = RREG32_MC(0x36);
384 	seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
385 	tmp = RREG32_MC(0x37);
386 	seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
387 	return 0;
388 }
389 
390 DEFINE_SHOW_ATTRIBUTE(rs400_debugfs_gart_info);
391 #endif
392 
rs400_debugfs_pcie_gart_info_init(struct radeon_device * rdev)393 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
394 {
395 #if defined(CONFIG_DEBUG_FS)
396 	struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
397 
398 	debugfs_create_file("rs400_gart_info", 0444, root, rdev,
399 			    &rs400_debugfs_gart_info_fops);
400 #endif
401 }
402 
rs400_mc_program(struct radeon_device * rdev)403 static void rs400_mc_program(struct radeon_device *rdev)
404 {
405 	struct r100_mc_save save;
406 
407 	/* Stops all mc clients */
408 	r100_mc_stop(rdev, &save);
409 
410 	/* Wait for mc idle */
411 	if (rs400_mc_wait_for_idle(rdev))
412 		dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
413 	WREG32(R_000148_MC_FB_LOCATION,
414 		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
415 		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
416 
417 	r100_mc_resume(rdev, &save);
418 }
419 
rs400_startup(struct radeon_device * rdev)420 static int rs400_startup(struct radeon_device *rdev)
421 {
422 	int r;
423 
424 	r100_set_common_regs(rdev);
425 
426 	rs400_mc_program(rdev);
427 	/* Resume clock */
428 	r300_clock_startup(rdev);
429 	/* Initialize GPU configuration (# pipes, ...) */
430 	rs400_gpu_init(rdev);
431 	r100_enable_bm(rdev);
432 	/* Initialize GART (initialize after TTM so we can allocate
433 	 * memory through TTM but finalize after TTM) */
434 	r = rs400_gart_enable(rdev);
435 	if (r)
436 		return r;
437 
438 	/* allocate wb buffer */
439 	r = radeon_wb_init(rdev);
440 	if (r)
441 		return r;
442 
443 	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
444 	if (r) {
445 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
446 		return r;
447 	}
448 
449 	/* Enable IRQ */
450 	if (!rdev->irq.installed) {
451 		r = radeon_irq_kms_init(rdev);
452 		if (r)
453 			return r;
454 	}
455 
456 	r100_irq_set(rdev);
457 	rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
458 	/* 1M ring buffer */
459 	r = r100_cp_init(rdev, 1024 * 1024);
460 	if (r) {
461 		dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
462 		return r;
463 	}
464 
465 	r = radeon_ib_pool_init(rdev);
466 	if (r) {
467 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
468 		return r;
469 	}
470 
471 	return 0;
472 }
473 
rs400_resume(struct radeon_device * rdev)474 int rs400_resume(struct radeon_device *rdev)
475 {
476 	int r;
477 
478 	/* Make sur GART are not working */
479 	rs400_gart_disable(rdev);
480 	/* Resume clock before doing reset */
481 	r300_clock_startup(rdev);
482 	/* setup MC before calling post tables */
483 	rs400_mc_program(rdev);
484 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
485 	if (radeon_asic_reset(rdev)) {
486 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
487 			RREG32(R_000E40_RBBM_STATUS),
488 			RREG32(R_0007C0_CP_STAT));
489 	}
490 	/* post */
491 	radeon_combios_asic_init(rdev_to_drm(rdev));
492 	/* Resume clock after posting */
493 	r300_clock_startup(rdev);
494 	/* Initialize surface registers */
495 	radeon_surface_init(rdev);
496 
497 	rdev->accel_working = true;
498 	r = rs400_startup(rdev);
499 	if (r) {
500 		rdev->accel_working = false;
501 	}
502 	return r;
503 }
504 
rs400_suspend(struct radeon_device * rdev)505 int rs400_suspend(struct radeon_device *rdev)
506 {
507 	radeon_pm_suspend(rdev);
508 	r100_cp_disable(rdev);
509 	radeon_wb_disable(rdev);
510 	r100_irq_disable(rdev);
511 	rs400_gart_disable(rdev);
512 	return 0;
513 }
514 
rs400_fini(struct radeon_device * rdev)515 void rs400_fini(struct radeon_device *rdev)
516 {
517 	radeon_pm_fini(rdev);
518 	r100_cp_fini(rdev);
519 	radeon_wb_fini(rdev);
520 	radeon_ib_pool_fini(rdev);
521 	radeon_gem_fini(rdev);
522 	rs400_gart_fini(rdev);
523 	radeon_irq_kms_fini(rdev);
524 	radeon_fence_driver_fini(rdev);
525 	radeon_bo_fini(rdev);
526 	radeon_atombios_fini(rdev);
527 	kfree(rdev->bios);
528 	rdev->bios = NULL;
529 }
530 
rs400_init(struct radeon_device * rdev)531 int rs400_init(struct radeon_device *rdev)
532 {
533 	int r;
534 
535 	/* Disable VGA */
536 	r100_vga_render_disable(rdev);
537 	/* Initialize scratch registers */
538 	radeon_scratch_init(rdev);
539 	/* Initialize surface registers */
540 	radeon_surface_init(rdev);
541 	/* TODO: disable VGA need to use VGA request */
542 	/* restore some register to sane defaults */
543 	r100_restore_sanity(rdev);
544 	/* BIOS*/
545 	if (!radeon_get_bios(rdev)) {
546 		if (ASIC_IS_AVIVO(rdev))
547 			return -EINVAL;
548 	}
549 	if (rdev->is_atom_bios) {
550 		dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
551 		return -EINVAL;
552 	} else {
553 		r = radeon_combios_init(rdev);
554 		if (r)
555 			return r;
556 	}
557 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
558 	if (radeon_asic_reset(rdev)) {
559 		dev_warn(rdev->dev,
560 			"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
561 			RREG32(R_000E40_RBBM_STATUS),
562 			RREG32(R_0007C0_CP_STAT));
563 	}
564 	/* check if cards are posted or not */
565 	if (radeon_boot_test_post_card(rdev) == false)
566 		return -EINVAL;
567 
568 	/* Initialize clocks */
569 	radeon_get_clock_info(rdev_to_drm(rdev));
570 	/* initialize memory controller */
571 	rs400_mc_init(rdev);
572 	/* Fence driver */
573 	radeon_fence_driver_init(rdev);
574 	/* Memory manager */
575 	r = radeon_bo_init(rdev);
576 	if (r)
577 		return r;
578 	r = rs400_gart_init(rdev);
579 	if (r)
580 		return r;
581 	r300_set_reg_safe(rdev);
582 
583 	/* Initialize power management */
584 	radeon_pm_init(rdev);
585 
586 	rdev->accel_working = true;
587 	r = rs400_startup(rdev);
588 	if (r) {
589 		/* Somethings want wront with the accel init stop accel */
590 		dev_err(rdev->dev, "Disabling GPU acceleration\n");
591 		r100_cp_fini(rdev);
592 		radeon_wb_fini(rdev);
593 		radeon_ib_pool_fini(rdev);
594 		rs400_gart_fini(rdev);
595 		radeon_irq_kms_fini(rdev);
596 		rdev->accel_working = false;
597 	}
598 	return 0;
599 }
600