1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28
29 #include <asm/byteorder.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33
34 #include "atomfirmware.h"
35
36 //<DMUB_TYPES>==================================================================
37 /* Basic type definitions. */
38
39 #define __forceinline inline
40
41 /**
42 * Flag from driver to indicate that ABM should be disabled gradually
43 * by slowly reversing all backlight programming and pixel compensation.
44 */
45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
46
47 /**
48 * Flag from driver to indicate that ABM should be disabled immediately
49 * and undo all backlight programming and pixel compensation.
50 */
51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
52
53 /**
54 * Flag from driver to indicate that ABM should be disabled immediately
55 * and keep the current backlight programming and pixel compensation.
56 */
57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
58
59 /**
60 * Flag from driver to set the current ABM pipe index or ABM operating level.
61 */
62 #define SET_ABM_PIPE_NORMAL 1
63
64 /**
65 * Number of ambient light levels in ABM algorithm.
66 */
67 #define NUM_AMBI_LEVEL 5
68
69 /**
70 * Number of operating/aggression levels in ABM algorithm.
71 */
72 #define NUM_AGGR_LEVEL 4
73
74 /**
75 * Number of segments in the gamma curve.
76 */
77 #define NUM_POWER_FN_SEGS 8
78
79 /**
80 * Number of segments in the backlight curve.
81 */
82 #define NUM_BL_CURVE_SEGS 16
83
84 /**
85 * Maximum number of segments in ABM ACE curve.
86 */
87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64
88
89 /**
90 * Maximum number of bins in ABM histogram.
91 */
92 #define ABM_MAX_NUM_OF_HG_BINS 64
93
94 /* Maximum number of SubVP streams */
95 #define DMUB_MAX_SUBVP_STREAMS 2
96
97 /* Define max FPO streams as 4 for now. Current implementation today
98 * only supports 1, but could be more in the future. Reduce array
99 * size to ensure the command size remains less than 64 bytes if
100 * adding new fields.
101 */
102 #define DMUB_MAX_FPO_STREAMS 4
103
104 /* Maximum number of streams on any ASIC. */
105 #define DMUB_MAX_STREAMS 6
106
107 /* Maximum number of planes on any ASIC. */
108 #define DMUB_MAX_PLANES 6
109
110 /* Maximum number of phantom planes on any ASIC */
111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2)
112
113 /* Trace buffer offset for entry */
114 #define TRACE_BUFFER_ENTRY_OFFSET 16
115
116 /**
117 * Maximum number of dirty rects supported by FW.
118 */
119 #define DMUB_MAX_DIRTY_RECTS 3
120
121 /**
122 *
123 * PSR control version legacy
124 */
125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
126 /**
127 * PSR control version with multi edp support
128 */
129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
130
131
132 /**
133 * ABM control version legacy
134 */
135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
136
137 /**
138 * ABM control version with multi edp support
139 */
140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
141
142 /**
143 * Physical framebuffer address location, 64-bit.
144 */
145 #ifndef PHYSICAL_ADDRESS_LOC
146 #define PHYSICAL_ADDRESS_LOC union large_integer
147 #endif
148
149 /**
150 * OS/FW agnostic memcpy
151 */
152 #ifndef dmub_memcpy
153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
154 #endif
155
156 /**
157 * OS/FW agnostic memset
158 */
159 #ifndef dmub_memset
160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
161 #endif
162
163 /**
164 * OS/FW agnostic udelay
165 */
166 #ifndef dmub_udelay
167 #define dmub_udelay(microseconds) udelay(microseconds)
168 #endif
169
170 #pragma pack(push, 1)
171 #define ABM_NUM_OF_ACE_SEGMENTS 5
172
173 /**
174 * Debug FW state offset
175 */
176 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300
177
178 union abm_flags {
179 struct {
180 /**
181 * @abm_enabled: Indicates if ABM is enabled.
182 */
183 unsigned int abm_enabled : 1;
184
185 /**
186 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
187 */
188 unsigned int disable_abm_requested : 1;
189
190 /**
191 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.
192 */
193 unsigned int disable_abm_immediately : 1;
194
195 /**
196 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
197 * to be disabled immediately and keep gain.
198 */
199 unsigned int disable_abm_immediate_keep_gain : 1;
200
201 /**
202 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
203 */
204 unsigned int fractional_pwm : 1;
205
206 /**
207 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
208 * of user backlight level.
209 */
210 unsigned int abm_gradual_bl_change : 1;
211
212 /**
213 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady
214 */
215 unsigned int abm_new_frame : 1;
216
217 /**
218 * @vb_scaling_enabled: Indicates variBright Scaling Enable
219 */
220 unsigned int vb_scaling_enabled : 1;
221 } bitfields;
222
223 unsigned int u32All;
224 };
225
226 struct abm_save_restore {
227 /**
228 * @flags: Misc. ABM flags.
229 */
230 union abm_flags flags;
231
232 /**
233 * @pause: true: pause ABM and get state
234 * false: unpause ABM after setting state
235 */
236 uint32_t pause;
237
238 /**
239 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
240 */
241 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
242
243 /**
244 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
245 */
246 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
247
248 /**
249 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
250 */
251 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
252
253
254 /**
255 * @knee_threshold: Current x-position of ACE knee (u0.16).
256 */
257 uint32_t knee_threshold;
258 /**
259 * @current_gain: Current backlight reduction (u16.16).
260 */
261 uint32_t current_gain;
262 /**
263 * @curr_bl_level: Current actual backlight level converging to target backlight level.
264 */
265 uint16_t curr_bl_level;
266
267 /**
268 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
269 */
270 uint16_t curr_user_bl_level;
271
272 };
273
274 /**
275 * union dmub_addr - DMUB physical/virtual 64-bit address.
276 */
277 union dmub_addr {
278 struct {
279 uint32_t low_part; /**< Lower 32 bits */
280 uint32_t high_part; /**< Upper 32 bits */
281 } u; /*<< Low/high bit access */
282 uint64_t quad_part; /*<< 64 bit address */
283 };
284 #pragma pack(pop)
285
286 /**
287 * Dirty rect definition.
288 */
289 struct dmub_rect {
290 /**
291 * Dirty rect x offset.
292 */
293 uint32_t x;
294
295 /**
296 * Dirty rect y offset.
297 */
298 uint32_t y;
299
300 /**
301 * Dirty rect width.
302 */
303 uint32_t width;
304
305 /**
306 * Dirty rect height.
307 */
308 uint32_t height;
309 };
310
311 /**
312 * Flags that can be set by driver to change some PSR behaviour.
313 */
314 union dmub_psr_debug_flags {
315 /**
316 * Debug flags.
317 */
318 struct {
319 /**
320 * Enable visual confirm in FW.
321 */
322 uint32_t visual_confirm : 1;
323
324 /**
325 * Force all selective updates to bw full frame updates.
326 */
327 uint32_t force_full_frame_update : 1;
328
329 /**
330 * Use HW Lock Mgr object to do HW locking in FW.
331 */
332 uint32_t use_hw_lock_mgr : 1;
333
334 /**
335 * Use TPS3 signal when restore main link.
336 */
337 uint32_t force_wakeup_by_tps3 : 1;
338
339 /**
340 * Back to back flip, therefore cannot power down PHY
341 */
342 uint32_t back_to_back_flip : 1;
343
344 /**
345 * Enable visual confirm for IPS
346 */
347 uint32_t enable_ips_visual_confirm : 1;
348 } bitfields;
349
350 /**
351 * Union for debug flags.
352 */
353 uint32_t u32All;
354 };
355
356 /**
357 * Flags that can be set by driver to change some Replay behaviour.
358 */
359 union replay_debug_flags {
360 struct {
361 /**
362 * 0x1 (bit 0)
363 * Enable visual confirm in FW.
364 */
365 uint32_t visual_confirm : 1;
366
367 /**
368 * 0x2 (bit 1)
369 * @skip_crc: Set if need to skip CRC.
370 */
371 uint32_t skip_crc : 1;
372
373 /**
374 * 0x4 (bit 2)
375 * @force_link_power_on: Force disable ALPM control
376 */
377 uint32_t force_link_power_on : 1;
378
379 /**
380 * 0x8 (bit 3)
381 * @force_phy_power_on: Force phy power on
382 */
383 uint32_t force_phy_power_on : 1;
384
385 /**
386 * 0x10 (bit 4)
387 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
388 */
389 uint32_t timing_resync_disabled : 1;
390
391 /**
392 * 0x20 (bit 5)
393 * @skip_crtc_disabled: CRTC disable skipped
394 */
395 uint32_t skip_crtc_disabled : 1;
396
397 /**
398 * 0x40 (bit 6)
399 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
400 */
401 uint32_t force_defer_one_frame_update : 1;
402
403 /**
404 * 0x80 (bit 7)
405 * @disable_delay_alpm_on: Force disable delay alpm on
406 */
407 uint32_t disable_delay_alpm_on : 1;
408
409 /**
410 * 0x100 (bit 8)
411 * @disable_desync_error_check: Force disable desync error check
412 */
413 uint32_t disable_desync_error_check : 1;
414
415 /**
416 * 0x200 (bit 9)
417 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady
418 */
419 uint32_t force_self_update_when_abm_non_steady : 1;
420
421 /**
422 * 0x400 (bit 10)
423 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS
424 * If we enter IPS2, the Visual confirm bar will change to yellow
425 */
426 uint32_t enable_ips_visual_confirm : 1;
427
428 /**
429 * 0x800 (bit 11)
430 * @enable_ips_residency_profiling: Enable IPS residency profiling
431 */
432 uint32_t enable_ips_residency_profiling : 1;
433
434 /**
435 * 0x1000 (bit 12)
436 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check
437 */
438 uint32_t enable_coasting_vtotal_check : 1;
439 /**
440 * 0x2000 (bit 13)
441 * @enable_visual_confirm_debug: Enable Visual Confirm Debug
442 */
443 uint32_t enable_visual_confirm_debug : 1;
444
445 uint32_t reserved : 18;
446 } bitfields;
447
448 uint32_t u32All;
449 };
450
451 /**
452 * Flags record error state.
453 */
454 union replay_visual_confirm_error_state_flags {
455 struct {
456 /**
457 * 0x1 (bit 0) - Desync Error flag.
458 */
459 uint32_t desync_error : 1;
460
461 /**
462 * 0x2 (bit 1) - State Transition Error flag.
463 */
464 uint32_t state_transition_error : 1;
465
466 /**
467 * 0x4 (bit 2) - Crc Error flag
468 */
469 uint32_t crc_error : 1;
470
471 /**
472 * 0x8 (bit 3) - Reserved
473 */
474 uint32_t reserved_3 : 1;
475
476 /**
477 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write.
478 * Added new debug flag to control DPCD.
479 */
480 uint32_t incorrect_vtotal_in_static_screen : 1;
481
482 /**
483 * 0x20 (bit 5) - No doubled Refresh Rate.
484 */
485 uint32_t no_double_rr : 1;
486
487 /**
488 * Reserved bit 6-7
489 */
490 uint32_t reserved_6_7 : 2;
491
492 /**
493 * Reserved bit 9-31
494 */
495 uint32_t reserved_9_31 : 24;
496 } bitfields;
497
498 uint32_t u32All;
499 };
500
501 union replay_hw_flags {
502 struct {
503 /**
504 * @allow_alpm_fw_standby_mode: To indicate whether the
505 * ALPM FW standby mode is allowed
506 */
507 uint32_t allow_alpm_fw_standby_mode : 1;
508
509 /*
510 * @dsc_enable_status: DSC enable status in driver
511 */
512 uint32_t dsc_enable_status : 1;
513
514 /**
515 * @fec_enable_status: receive fec enable/disable status from driver
516 */
517 uint32_t fec_enable_status : 1;
518
519 /*
520 * @smu_optimizations_en: SMU power optimization.
521 * Only when active display is Replay capable and display enters Replay.
522 * Trigger interrupt to SMU to powerup/down.
523 */
524 uint32_t smu_optimizations_en : 1;
525
526 /**
527 * @phy_power_state: Indicates current phy power state
528 */
529 uint32_t phy_power_state : 1;
530
531 /**
532 * @link_power_state: Indicates current link power state
533 */
534 uint32_t link_power_state : 1;
535 /**
536 * Use TPS3 signal when restore main link.
537 */
538 uint32_t force_wakeup_by_tps3 : 1;
539 /**
540 * @is_alpm_initialized: Indicates whether ALPM is initialized
541 */
542 uint32_t is_alpm_initialized : 1;
543 } bitfields;
544
545 uint32_t u32All;
546 };
547
548 union fw_assisted_mclk_switch_version {
549 struct {
550 uint8_t minor : 5;
551 uint8_t major : 3;
552 };
553 uint8_t ver;
554 };
555
556 /**
557 * DMUB feature capabilities.
558 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
559 */
560 struct dmub_feature_caps {
561 /**
562 * Max PSR version supported by FW.
563 */
564 uint8_t psr;
565 uint8_t fw_assisted_mclk_switch_ver;
566 uint8_t reserved[4];
567 uint8_t subvp_psr_support;
568 uint8_t gecc_enable;
569 uint8_t replay_supported;
570 uint8_t replay_reserved[3];
571 uint8_t abm_aux_backlight_support;
572 };
573
574 struct dmub_visual_confirm_color {
575 /**
576 * Maximum 10 bits color value
577 */
578 uint16_t color_r_cr;
579 uint16_t color_g_y;
580 uint16_t color_b_cb;
581 uint16_t panel_inst;
582 };
583
584 //==============================================================================
585 //</DMUB_TYPES>=================================================================
586 //==============================================================================
587 //< DMUB_META>==================================================================
588 //==============================================================================
589 #pragma pack(push, 1)
590
591 /* Magic value for identifying dmub_fw_meta_info */
592 #define DMUB_FW_META_MAGIC 0x444D5542
593
594 /* Offset from the end of the file to the dmub_fw_meta_info */
595 #define DMUB_FW_META_OFFSET 0x24
596
597 /**
598 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization
599 */
600 union dmub_fw_meta_feature_bits {
601 struct {
602 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */
603 uint32_t reserved : 31;
604 } bits; /**< status bits */
605 uint32_t all; /**< 32-bit access to status bits */
606 };
607
608 /**
609 * struct dmub_fw_meta_info - metadata associated with fw binary
610 *
611 * NOTE: This should be considered a stable API. Fields should
612 * not be repurposed or reordered. New fields should be
613 * added instead to extend the structure.
614 *
615 * @magic_value: magic value identifying DMUB firmware meta info
616 * @fw_region_size: size of the firmware state region
617 * @trace_buffer_size: size of the tracebuffer region
618 * @fw_version: the firmware version information
619 * @dal_fw: 1 if the firmware is DAL
620 * @shared_state_size: size of the shared state region in bytes
621 * @shared_state_features: number of shared state features
622 */
623 struct dmub_fw_meta_info {
624 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
625 uint32_t fw_region_size; /**< size of the firmware state region */
626 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
627 uint32_t fw_version; /**< the firmware version information */
628 uint8_t dal_fw; /**< 1 if the firmware is DAL */
629 uint8_t reserved[3]; /**< padding bits */
630 uint32_t shared_state_size; /**< size of the shared state region in bytes */
631 uint16_t shared_state_features; /**< number of shared state features */
632 uint16_t reserved2; /**< padding bytes */
633 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */
634 };
635
636 /**
637 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
638 */
639 union dmub_fw_meta {
640 struct dmub_fw_meta_info info; /**< metadata info */
641 uint8_t reserved[64]; /**< padding bits */
642 };
643
644 #pragma pack(pop)
645
646 //==============================================================================
647 //< DMUB Trace Buffer>================================================================
648 //==============================================================================
649 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED)
650 /**
651 * dmub_trace_code_t - firmware trace code, 32-bits
652 */
653 typedef uint32_t dmub_trace_code_t;
654
655 /**
656 * struct dmcub_trace_buf_entry - Firmware trace entry
657 */
658 struct dmcub_trace_buf_entry {
659 dmub_trace_code_t trace_code; /**< trace code for the event */
660 uint32_t tick_count; /**< the tick count at time of trace */
661 uint32_t param0; /**< trace defined parameter 0 */
662 uint32_t param1; /**< trace defined parameter 1 */
663 };
664 #endif
665
666 //==============================================================================
667 //< DMUB_STATUS>================================================================
668 //==============================================================================
669
670 /**
671 * DMCUB scratch registers can be used to determine firmware status.
672 * Current scratch register usage is as follows:
673 *
674 * SCRATCH0: FW Boot Status register
675 * SCRATCH5: LVTMA Status Register
676 * SCRATCH15: FW Boot Options register
677 */
678
679 /**
680 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
681 */
682 union dmub_fw_boot_status {
683 struct {
684 uint32_t dal_fw : 1; /**< 1 if DAL FW */
685 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
686 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
687 uint32_t restore_required : 1; /**< 1 if driver should call restore */
688 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
689 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
690 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
691 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
692 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
693 } bits; /**< status bits */
694 uint32_t all; /**< 32-bit access to status bits */
695 };
696
697 /**
698 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
699 */
700 enum dmub_fw_boot_status_bit {
701 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
702 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
703 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
704 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
705 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
706 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
707 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
708 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
709 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
710 };
711
712 /* Register bit definition for SCRATCH5 */
713 union dmub_lvtma_status {
714 struct {
715 uint32_t psp_ok : 1;
716 uint32_t edp_on : 1;
717 uint32_t reserved : 30;
718 } bits;
719 uint32_t all;
720 };
721
722 enum dmub_lvtma_status_bit {
723 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
724 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
725 };
726
727 enum dmub_ips_disable_type {
728 DMUB_IPS_ENABLE = 0,
729 DMUB_IPS_DISABLE_ALL = 1,
730 DMUB_IPS_DISABLE_IPS1 = 2,
731 DMUB_IPS_DISABLE_IPS2 = 3,
732 DMUB_IPS_DISABLE_IPS2_Z10 = 4,
733 DMUB_IPS_DISABLE_DYNAMIC = 5,
734 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6,
735 };
736
737 #define DMUB_IPS1_ALLOW_MASK 0x00000001
738 #define DMUB_IPS2_ALLOW_MASK 0x00000002
739 #define DMUB_IPS1_COMMIT_MASK 0x00000004
740 #define DMUB_IPS2_COMMIT_MASK 0x00000008
741
742 /**
743 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
744 */
745 union dmub_fw_boot_options {
746 struct {
747 uint32_t pemu_env : 1; /**< 1 if PEMU */
748 uint32_t fpga_env : 1; /**< 1 if FPGA */
749 uint32_t optimized_init : 1; /**< 1 if optimized init */
750 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
751 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
752 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
753 uint32_t z10_disable: 1; /**< 1 to disable z10 */
754 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
755 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
756 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
757 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */
758 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
759 uint32_t power_optimization: 1;
760 uint32_t diag_env: 1; /* 1 if diagnostic environment */
761 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
762 uint32_t usb4_cm_version: 1; /**< 1 CM support */
763 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
764 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/
765 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
766 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
767 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
768 uint32_t ips_disable: 3; /* options to disable ips support*/
769 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
770 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */
771 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */
772 uint32_t reserved : 6; /**< reserved */
773 } bits; /**< boot bits */
774 uint32_t all; /**< 32-bit access to bits */
775 };
776
777 enum dmub_fw_boot_options_bit {
778 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
779 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
780 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
781 };
782
783 //==============================================================================
784 //< DMUB_SHARED_STATE>==========================================================
785 //==============================================================================
786
787 /**
788 * Shared firmware state between driver and firmware for lockless communication
789 * in situations where the inbox/outbox may be unavailable.
790 *
791 * Each structure *must* be at most 256-bytes in size. The layout allocation is
792 * described below:
793 *
794 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]...
795 */
796
797 /**
798 * enum dmub_shared_state_feature_id - List of shared state features.
799 */
800 enum dmub_shared_state_feature_id {
801 DMUB_SHARED_SHARE_FEATURE__INVALID = 0,
802 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1,
803 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2,
804 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3,
805 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */
806 };
807
808 /**
809 * struct dmub_shared_state_ips_fw - Firmware signals for IPS.
810 */
811 union dmub_shared_state_ips_fw_signals {
812 struct {
813 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */
814 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */
815 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */
816 uint32_t detection_required : 1; /**< 1 if detection is required */
817 uint32_t reserved_bits : 28; /**< Reversed */
818 } bits;
819 uint32_t all;
820 };
821
822 /**
823 * struct dmub_shared_state_ips_signals - Firmware signals for IPS.
824 */
825 union dmub_shared_state_ips_driver_signals {
826 struct {
827 uint32_t allow_pg : 1; /**< 1 if PG is allowed */
828 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */
829 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */
830 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */
831 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */
832 uint32_t reserved_bits : 27; /**< Reversed bits */
833 } bits;
834 uint32_t all;
835 };
836
837 /**
838 * IPS FW Version
839 */
840 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1
841
842 struct dmub_shared_state_debug_setup {
843 union {
844 struct {
845 uint32_t exclude_points[62];
846 } profile_mode;
847 };
848 };
849
850 /**
851 * struct dmub_shared_state_ips_fw - Firmware state for IPS.
852 */
853 struct dmub_shared_state_ips_fw {
854 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */
855 uint32_t rcg_entry_count; /**< Entry counter for RCG */
856 uint32_t rcg_exit_count; /**< Exit counter for RCG */
857 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */
858 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */
859 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */
860 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */
861 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */
862 }; /* 248-bytes, fixed */
863
864 /**
865 * IPS Driver Version
866 */
867 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1
868
869 /**
870 * struct dmub_shared_state_ips_driver - Driver state for IPS.
871 */
872 struct dmub_shared_state_ips_driver {
873 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */
874 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */
875 }; /* 248-bytes, fixed */
876
877 /**
878 * enum dmub_shared_state_feature_common - Generic payload.
879 */
880 struct dmub_shared_state_feature_common {
881 uint32_t padding[62];
882 }; /* 248-bytes, fixed */
883
884 /**
885 * enum dmub_shared_state_feature_header - Feature description.
886 */
887 struct dmub_shared_state_feature_header {
888 uint16_t id; /**< Feature ID */
889 uint16_t version; /**< Feature version */
890 uint32_t reserved; /**< Reserved bytes. */
891 }; /* 8 bytes, fixed */
892
893 /**
894 * struct dmub_shared_state_feature_block - Feature block.
895 */
896 struct dmub_shared_state_feature_block {
897 struct dmub_shared_state_feature_header header; /**< Shared state header. */
898 union dmub_shared_feature_state_union {
899 struct dmub_shared_state_feature_common common; /**< Generic data */
900 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */
901 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */
902 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */
903 } data; /**< Shared state data. */
904 }; /* 256-bytes, fixed */
905
906 /**
907 * Shared state size in bytes.
908 */
909 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \
910 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block))
911
912 //==============================================================================
913 //</DMUB_STATUS>================================================================
914 //==============================================================================
915 //< DMUB_VBIOS>=================================================================
916 //==============================================================================
917
918 /*
919 * enum dmub_cmd_vbios_type - VBIOS commands.
920 *
921 * Command IDs should be treated as stable ABI.
922 * Do not reuse or modify IDs.
923 */
924 enum dmub_cmd_vbios_type {
925 /**
926 * Configures the DIG encoder.
927 */
928 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
929 /**
930 * Controls the PHY.
931 */
932 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
933 /**
934 * Sets the pixel clock/symbol clock.
935 */
936 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
937 /**
938 * Enables or disables power gating.
939 */
940 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
941 /**
942 * Controls embedded panels.
943 */
944 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
945 /**
946 * Query DP alt status on a transmitter.
947 */
948 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
949 /**
950 * Control PHY FSM
951 */
952 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29,
953 /**
954 * Controls domain power gating
955 */
956 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
957 };
958
959 //==============================================================================
960 //</DMUB_VBIOS>=================================================================
961 //==============================================================================
962 //< DMUB_GPINT>=================================================================
963 //==============================================================================
964
965 /**
966 * The shifts and masks below may alternatively be used to format and read
967 * the command register bits.
968 */
969
970 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
971 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
972
973 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
974 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
975
976 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
977 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
978
979 /**
980 * Command responses.
981 */
982
983 /**
984 * Return response for DMUB_GPINT__STOP_FW command.
985 */
986 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
987
988 /**
989 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
990 */
991 union dmub_gpint_data_register {
992 struct {
993 uint32_t param : 16; /**< 16-bit parameter */
994 uint32_t command_code : 12; /**< GPINT command */
995 uint32_t status : 4; /**< Command status bit */
996 } bits; /**< GPINT bit access */
997 uint32_t all; /**< GPINT 32-bit access */
998 };
999
1000 /*
1001 * enum dmub_gpint_command - GPINT command to DMCUB FW
1002 *
1003 * Command IDs should be treated as stable ABI.
1004 * Do not reuse or modify IDs.
1005 */
1006 enum dmub_gpint_command {
1007 /**
1008 * Invalid command, ignored.
1009 */
1010 DMUB_GPINT__INVALID_COMMAND = 0,
1011 /**
1012 * DESC: Queries the firmware version.
1013 * RETURN: Firmware version.
1014 */
1015 DMUB_GPINT__GET_FW_VERSION = 1,
1016 /**
1017 * DESC: Halts the firmware.
1018 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
1019 */
1020 DMUB_GPINT__STOP_FW = 2,
1021 /**
1022 * DESC: Get PSR state from FW.
1023 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
1024 */
1025 DMUB_GPINT__GET_PSR_STATE = 7,
1026 /**
1027 * DESC: Notifies DMCUB of the currently active streams.
1028 * ARGS: Stream mask, 1 bit per active stream index.
1029 */
1030 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
1031 /**
1032 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
1033 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
1034 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
1035 * RETURN: PSR residency in milli-percent.
1036 */
1037 DMUB_GPINT__PSR_RESIDENCY = 9,
1038
1039 /**
1040 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
1041 */
1042 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
1043
1044 /**
1045 * DESC: Get REPLAY state from FW.
1046 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
1047 */
1048 DMUB_GPINT__GET_REPLAY_STATE = 13,
1049
1050 /**
1051 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
1052 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
1053 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
1054 * RETURN: REPLAY residency in milli-percent.
1055 */
1056 DMUB_GPINT__REPLAY_RESIDENCY = 14,
1057
1058 /**
1059 * DESC: Copy bounding box to the host.
1060 * ARGS: Version of bounding box to copy
1061 * RETURN: Result of copying bounding box
1062 */
1063 DMUB_GPINT__BB_COPY = 96,
1064
1065 /**
1066 * DESC: Updates the host addresses bit48~bit63 for bounding box.
1067 * ARGS: The word3 for the 64 bit address
1068 */
1069 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,
1070
1071 /**
1072 * DESC: Updates the host addresses bit32~bit47 for bounding box.
1073 * ARGS: The word2 for the 64 bit address
1074 */
1075 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,
1076
1077 /**
1078 * DESC: Updates the host addresses bit16~bit31 for bounding box.
1079 * ARGS: The word1 for the 64 bit address
1080 */
1081 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,
1082
1083 /**
1084 * DESC: Updates the host addresses bit0~bit15 for bounding box.
1085 * ARGS: The word0 for the 64 bit address
1086 */
1087 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,
1088
1089 /**
1090 * DESC: Updates the trace buffer lower 32-bit mask.
1091 * ARGS: The new mask
1092 * RETURN: Lower 32-bit mask.
1093 */
1094 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
1095
1096 /**
1097 * DESC: Updates the trace buffer mask bit0~bit15.
1098 * ARGS: The new mask
1099 * RETURN: Lower 32-bit mask.
1100 */
1101 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
1102
1103 /**
1104 * DESC: Updates the trace buffer mask bit16~bit31.
1105 * ARGS: The new mask
1106 * RETURN: Lower 32-bit mask.
1107 */
1108 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
1109
1110 /**
1111 * DESC: Updates the trace buffer mask bit32~bit47.
1112 * ARGS: The new mask
1113 * RETURN: Lower 32-bit mask.
1114 */
1115 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,
1116
1117 /**
1118 * DESC: Updates the trace buffer mask bit48~bit63.
1119 * ARGS: The new mask
1120 * RETURN: Lower 32-bit mask.
1121 */
1122 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,
1123
1124 /**
1125 * DESC: Read the trace buffer mask bi0~bit15.
1126 */
1127 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116,
1128
1129 /**
1130 * DESC: Read the trace buffer mask bit16~bit31.
1131 */
1132 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117,
1133
1134 /**
1135 * DESC: Read the trace buffer mask bi32~bit47.
1136 */
1137 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118,
1138
1139 /**
1140 * DESC: Updates the trace buffer mask bit32~bit63.
1141 */
1142 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,
1143
1144 /**
1145 * DESC: Set IPS residency measurement
1146 * ARGS: 0 - Disable ips measurement
1147 * 1 - Enable ips measurement
1148 */
1149 DMUB_GPINT__IPS_RESIDENCY = 121,
1150
1151 /**
1152 * DESC: Enable measurements for various task duration
1153 * ARGS: 0 - Disable measurement
1154 * 1 - Enable measurement
1155 */
1156 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,
1157
1158 /**
1159 * DESC: Gets IPS residency in microseconds
1160 * ARGS: 0 - Return IPS1 residency
1161 * 1 - Return IPS2 residency
1162 * 2 - Return IPS1_RCG residency
1163 * 3 - Return IPS1_ONO2_ON residency
1164 * RETURN: Total residency in microseconds - lower 32 bits
1165 */
1166 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124,
1167
1168 /**
1169 * DESC: Gets IPS1 histogram counts
1170 * ARGS: Bucket index
1171 * RETURN: Total count for the bucket
1172 */
1173 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125,
1174
1175 /**
1176 * DESC: Gets IPS2 histogram counts
1177 * ARGS: Bucket index
1178 * RETURN: Total count for the bucket
1179 */
1180 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126,
1181
1182 /**
1183 * DESC: Gets IPS residency
1184 * ARGS: 0 - Return IPS1 residency
1185 * 1 - Return IPS2 residency
1186 * 2 - Return IPS1_RCG residency
1187 * 3 - Return IPS1_ONO2_ON residency
1188 * RETURN: Total residency in milli-percent.
1189 */
1190 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127,
1191
1192 /**
1193 * DESC: Gets IPS1_RCG histogram counts
1194 * ARGS: Bucket index
1195 * RETURN: Total count for the bucket
1196 */
1197 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128,
1198
1199 /**
1200 * DESC: Gets IPS1_ONO2_ON histogram counts
1201 * ARGS: Bucket index
1202 * RETURN: Total count for the bucket
1203 */
1204 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129,
1205
1206 /**
1207 * DESC: Gets IPS entry counter during residency measurement
1208 * ARGS: 0 - Return IPS1 entry counts
1209 * 1 - Return IPS2 entry counts
1210 * 2 - Return IPS1_RCG entry counts
1211 * 3 - Return IPS2_ONO2_ON entry counts
1212 * RETURN: Entry counter for selected IPS mode
1213 */
1214 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130,
1215
1216 /**
1217 * DESC: Gets IPS inactive residency in microseconds
1218 * ARGS: 0 - Return IPS1_MAX residency
1219 * 1 - Return IPS2 residency
1220 * 2 - Return IPS1_RCG residency
1221 * 3 - Return IPS1_ONO2_ON residency
1222 * RETURN: Total inactive residency in microseconds - lower 32 bits
1223 */
1224 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131,
1225
1226 /**
1227 * DESC: Gets IPS inactive residency in microseconds
1228 * ARGS: 0 - Return IPS1_MAX residency
1229 * 1 - Return IPS2 residency
1230 * 2 - Return IPS1_RCG residency
1231 * 3 - Return IPS1_ONO2_ON residency
1232 * RETURN: Total inactive residency in microseconds - upper 32 bits
1233 */
1234 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132,
1235
1236 /**
1237 * DESC: Gets IPS residency in microseconds
1238 * ARGS: 0 - Return IPS1 residency
1239 * 1 - Return IPS2 residency
1240 * 2 - Return IPS1_RCG residency
1241 * 3 - Return IPS1_ONO2_ON residency
1242 * RETURN: Total residency in microseconds - upper 32 bits
1243 */
1244 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133,
1245 /**
1246 * DESC: Setup debug configs.
1247 */
1248 DMUB_GPINT__SETUP_DEBUG_MODE = 136,
1249 };
1250
1251 /**
1252 * INBOX0 generic command definition
1253 */
1254 union dmub_inbox0_cmd_common {
1255 struct {
1256 uint32_t command_code: 8; /**< INBOX0 command code */
1257 uint32_t param: 24; /**< 24-bit parameter */
1258 } bits;
1259 uint32_t all;
1260 };
1261
1262 /**
1263 * INBOX0 hw_lock command definition
1264 */
1265 union dmub_inbox0_cmd_lock_hw {
1266 struct {
1267 uint32_t command_code: 8;
1268
1269 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
1270 uint32_t hw_lock_client: 2;
1271
1272 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
1273 uint32_t otg_inst: 3;
1274 uint32_t opp_inst: 3;
1275 uint32_t dig_inst: 3;
1276
1277 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
1278 uint32_t lock_pipe: 1;
1279 uint32_t lock_cursor: 1;
1280 uint32_t lock_dig: 1;
1281 uint32_t triple_buffer_lock: 1;
1282
1283 uint32_t lock: 1; /**< Lock */
1284 uint32_t should_release: 1; /**< Release */
1285 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
1286 } bits;
1287 uint32_t all;
1288 };
1289
1290 union dmub_inbox0_data_register {
1291 union dmub_inbox0_cmd_common inbox0_cmd_common;
1292 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
1293 };
1294
1295 enum dmub_inbox0_command {
1296 /**
1297 * DESC: Invalid command, ignored.
1298 */
1299 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
1300 /**
1301 * DESC: Notification to acquire/release HW lock
1302 * ARGS:
1303 */
1304 DMUB_INBOX0_CMD__HW_LOCK = 1,
1305 };
1306 //==============================================================================
1307 //</DMUB_GPINT>=================================================================
1308 //==============================================================================
1309 //< DMUB_CMD>===================================================================
1310 //==============================================================================
1311
1312 /**
1313 * Size in bytes of each DMUB command.
1314 */
1315 #define DMUB_RB_CMD_SIZE 64
1316
1317 /**
1318 * Maximum number of items in the DMUB ringbuffer.
1319 */
1320 #define DMUB_RB_MAX_ENTRY 128
1321
1322 /**
1323 * Ringbuffer size in bytes.
1324 */
1325 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
1326
1327 /**
1328 * REG_SET mask for reg offload.
1329 */
1330 #define REG_SET_MASK 0xFFFF
1331
1332 /*
1333 * enum dmub_cmd_type - DMUB inbox command.
1334 *
1335 * Command IDs should be treated as stable ABI.
1336 * Do not reuse or modify IDs.
1337 */
1338 enum dmub_cmd_type {
1339 /**
1340 * Invalid command.
1341 */
1342 DMUB_CMD__NULL = 0,
1343 /**
1344 * Read modify write register sequence offload.
1345 */
1346 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
1347 /**
1348 * Field update register sequence offload.
1349 */
1350 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
1351 /**
1352 * Burst write sequence offload.
1353 */
1354 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
1355 /**
1356 * Reg wait sequence offload.
1357 */
1358 DMUB_CMD__REG_REG_WAIT = 4,
1359 /**
1360 * Workaround to avoid HUBP underflow during NV12 playback.
1361 */
1362 DMUB_CMD__PLAT_54186_WA = 5,
1363 /**
1364 * Command type used to query FW feature caps.
1365 */
1366 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
1367 /**
1368 * Command type used to get visual confirm color.
1369 */
1370 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
1371 /**
1372 * Command type used for all PSR commands.
1373 */
1374 DMUB_CMD__PSR = 64,
1375 /**
1376 * Command type used for all MALL commands.
1377 */
1378 DMUB_CMD__MALL = 65,
1379 /**
1380 * Command type used for all ABM commands.
1381 */
1382 DMUB_CMD__ABM = 66,
1383 /**
1384 * Command type used to update dirty rects in FW.
1385 */
1386 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
1387 /**
1388 * Command type used to update cursor info in FW.
1389 */
1390 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
1391 /**
1392 * Command type used for HW locking in FW.
1393 */
1394 DMUB_CMD__HW_LOCK = 69,
1395 /**
1396 * Command type used to access DP AUX.
1397 */
1398 DMUB_CMD__DP_AUX_ACCESS = 70,
1399 /**
1400 * Command type used for OUTBOX1 notification enable
1401 */
1402 DMUB_CMD__OUTBOX1_ENABLE = 71,
1403
1404 /**
1405 * Command type used for all idle optimization commands.
1406 */
1407 DMUB_CMD__IDLE_OPT = 72,
1408 /**
1409 * Command type used for all clock manager commands.
1410 */
1411 DMUB_CMD__CLK_MGR = 73,
1412 /**
1413 * Command type used for all panel control commands.
1414 */
1415 DMUB_CMD__PANEL_CNTL = 74,
1416
1417 /**
1418 * Command type used for all CAB commands.
1419 */
1420 DMUB_CMD__CAB_FOR_SS = 75,
1421
1422 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
1423
1424 /**
1425 * Command type used for interfacing with DPIA.
1426 */
1427 DMUB_CMD__DPIA = 77,
1428 /**
1429 * Command type used for EDID CEA parsing
1430 */
1431 DMUB_CMD__EDID_CEA = 79,
1432 /**
1433 * Command type used for getting usbc cable ID
1434 */
1435 DMUB_CMD_GET_USBC_CABLE_ID = 81,
1436 /**
1437 * Command type used to query HPD state.
1438 */
1439 DMUB_CMD__QUERY_HPD_STATE = 82,
1440 /**
1441 * Command type used for all VBIOS interface commands.
1442 */
1443 /**
1444 * Command type used for all REPLAY commands.
1445 */
1446 DMUB_CMD__REPLAY = 83,
1447
1448 /**
1449 * Command type used for all SECURE_DISPLAY commands.
1450 */
1451 DMUB_CMD__SECURE_DISPLAY = 85,
1452
1453 /**
1454 * Command type used to set DPIA HPD interrupt state
1455 */
1456 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1457
1458 /**
1459 * Command type used for all PSP commands.
1460 */
1461 DMUB_CMD__PSP = 88,
1462
1463 DMUB_CMD__VBIOS = 128,
1464 };
1465
1466 /**
1467 * enum dmub_out_cmd_type - DMUB outbox commands.
1468 */
1469 enum dmub_out_cmd_type {
1470 /**
1471 * Invalid outbox command, ignored.
1472 */
1473 DMUB_OUT_CMD__NULL = 0,
1474 /**
1475 * Command type used for DP AUX Reply data notification
1476 */
1477 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1478 /**
1479 * Command type used for DP HPD event notification
1480 */
1481 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1482 /**
1483 * Command type used for SET_CONFIG Reply notification
1484 */
1485 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1486 /**
1487 * Command type used for USB4 DPIA notification
1488 */
1489 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1490 /**
1491 * Command type used for HPD redetect notification
1492 */
1493 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6,
1494 };
1495
1496 /* DMUB_CMD__DPIA command sub-types. */
1497 enum dmub_cmd_dpia_type {
1498 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1499 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST
1500 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1501 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3,
1502 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4,
1503 };
1504
1505 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1506 enum dmub_cmd_dpia_notification_type {
1507 DPIA_NOTIFY__BW_ALLOCATION = 0,
1508 };
1509
1510 #pragma pack(push, 1)
1511
1512 /**
1513 * struct dmub_cmd_header - Common command header fields.
1514 */
1515 struct dmub_cmd_header {
1516 unsigned int type : 8; /**< command type */
1517 unsigned int sub_type : 8; /**< command sub type */
1518 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1519 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1520 unsigned int reserved0 : 6; /**< reserved bits */
1521 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1522 unsigned int reserved1 : 2; /**< reserved bits */
1523 };
1524
1525 /*
1526 * struct dmub_cmd_read_modify_write_sequence - Read modify write
1527 *
1528 * 60 payload bytes can hold up to 5 sets of read modify writes,
1529 * each take 3 dwords.
1530 *
1531 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1532 *
1533 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
1534 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1535 */
1536 struct dmub_cmd_read_modify_write_sequence {
1537 uint32_t addr; /**< register address */
1538 uint32_t modify_mask; /**< modify mask */
1539 uint32_t modify_value; /**< modify value */
1540 };
1541
1542 /**
1543 * Maximum number of ops in read modify write sequence.
1544 */
1545 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1546
1547 /**
1548 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1549 */
1550 struct dmub_rb_cmd_read_modify_write {
1551 struct dmub_cmd_header header; /**< command header */
1552 /**
1553 * Read modify write sequence.
1554 */
1555 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
1556 };
1557
1558 /*
1559 * Update a register with specified masks and values sequeunce
1560 *
1561 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
1562 *
1563 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
1564 *
1565 *
1566 * USE CASE:
1567 * 1. auto-increment register where additional read would update pointer and produce wrong result
1568 * 2. toggle a bit without read in the middle
1569 */
1570
1571 struct dmub_cmd_reg_field_update_sequence {
1572 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
1573 uint32_t modify_value; /**< value to update with */
1574 };
1575
1576 /**
1577 * Maximum number of ops in field update sequence.
1578 */
1579 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
1580
1581 /**
1582 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
1583 */
1584 struct dmub_rb_cmd_reg_field_update_sequence {
1585 struct dmub_cmd_header header; /**< command header */
1586 uint32_t addr; /**< register address */
1587 /**
1588 * Field update sequence.
1589 */
1590 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
1591 };
1592
1593
1594 /**
1595 * Maximum number of burst write values.
1596 */
1597 #define DMUB_BURST_WRITE_VALUES__MAX 14
1598
1599 /*
1600 * struct dmub_rb_cmd_burst_write - Burst write
1601 *
1602 * support use case such as writing out LUTs.
1603 *
1604 * 60 payload bytes can hold up to 14 values to write to given address
1605 *
1606 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
1607 */
1608 struct dmub_rb_cmd_burst_write {
1609 struct dmub_cmd_header header; /**< command header */
1610 uint32_t addr; /**< register start address */
1611 /**
1612 * Burst write register values.
1613 */
1614 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
1615 };
1616
1617 /**
1618 * struct dmub_rb_cmd_common - Common command header
1619 */
1620 struct dmub_rb_cmd_common {
1621 struct dmub_cmd_header header; /**< command header */
1622 /**
1623 * Padding to RB_CMD_SIZE
1624 */
1625 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
1626 };
1627
1628 /**
1629 * struct dmub_cmd_reg_wait_data - Register wait data
1630 */
1631 struct dmub_cmd_reg_wait_data {
1632 uint32_t addr; /**< Register address */
1633 uint32_t mask; /**< Mask for register bits */
1634 uint32_t condition_field_value; /**< Value to wait for */
1635 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
1636 };
1637
1638 /**
1639 * struct dmub_rb_cmd_reg_wait - Register wait command
1640 */
1641 struct dmub_rb_cmd_reg_wait {
1642 struct dmub_cmd_header header; /**< Command header */
1643 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
1644 };
1645
1646 /**
1647 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
1648 *
1649 * Reprograms surface parameters to avoid underflow.
1650 */
1651 struct dmub_cmd_PLAT_54186_wa {
1652 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
1653 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
1654 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
1655 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
1656 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
1657 struct {
1658 uint32_t hubp_inst : 4; /**< HUBP instance */
1659 uint32_t tmz_surface : 1; /**< TMZ enable or disable */
1660 uint32_t immediate :1; /**< Immediate flip */
1661 uint32_t vmid : 4; /**< VMID */
1662 uint32_t grph_stereo : 1; /**< 1 if stereo */
1663 uint32_t reserved : 21; /**< Reserved */
1664 } flip_params; /**< Pageflip parameters */
1665 uint32_t reserved[9]; /**< Reserved bits */
1666 };
1667
1668 /**
1669 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
1670 */
1671 struct dmub_rb_cmd_PLAT_54186_wa {
1672 struct dmub_cmd_header header; /**< Command header */
1673 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
1674 };
1675
1676 /**
1677 * enum dmub_cmd_mall_type - MALL commands
1678 */
1679 enum dmub_cmd_mall_type {
1680 /**
1681 * Allows display refresh from MALL.
1682 */
1683 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1684 /**
1685 * Disallows display refresh from MALL.
1686 */
1687 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1688 /**
1689 * Cursor copy for MALL.
1690 */
1691 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1692 /**
1693 * Controls DF requests.
1694 */
1695 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1696 };
1697
1698 /**
1699 * struct dmub_rb_cmd_mall - MALL command data.
1700 */
1701 struct dmub_rb_cmd_mall {
1702 struct dmub_cmd_header header; /**< Common command header */
1703 union dmub_addr cursor_copy_src; /**< Cursor copy address */
1704 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
1705 uint32_t tmr_delay; /**< Timer delay */
1706 uint32_t tmr_scale; /**< Timer scale */
1707 uint16_t cursor_width; /**< Cursor width in pixels */
1708 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
1709 uint16_t cursor_height; /**< Cursor height in pixels */
1710 uint8_t cursor_bpp; /**< Cursor bits per pixel */
1711 uint8_t debug_bits; /**< Debug bits */
1712
1713 uint8_t reserved1; /**< Reserved bits */
1714 uint8_t reserved2; /**< Reserved bits */
1715 };
1716
1717 /**
1718 * enum dmub_cmd_cab_type - CAB command data.
1719 */
1720 enum dmub_cmd_cab_type {
1721 /**
1722 * No idle optimizations (i.e. no CAB)
1723 */
1724 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
1725 /**
1726 * No DCN requests for memory
1727 */
1728 DMUB_CMD__CAB_NO_DCN_REQ = 1,
1729 /**
1730 * Fit surfaces in CAB (i.e. CAB enable)
1731 */
1732 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
1733 /**
1734 * Do not fit surfaces in CAB (i.e. no CAB)
1735 */
1736 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,
1737 };
1738
1739 /**
1740 * struct dmub_rb_cmd_cab - CAB command data.
1741 */
1742 struct dmub_rb_cmd_cab_for_ss {
1743 struct dmub_cmd_header header;
1744 uint8_t cab_alloc_ways; /* total number of ways */
1745 uint8_t debug_bits; /* debug bits */
1746 };
1747
1748 /**
1749 * Enum for indicating which MCLK switch mode per pipe
1750 */
1751 enum mclk_switch_mode {
1752 NONE = 0,
1753 FPO = 1,
1754 SUBVP = 2,
1755 VBLANK = 3,
1756 };
1757
1758 /* Per pipe struct which stores the MCLK switch mode
1759 * data to be sent to DMUB.
1760 * Named "v2" for now -- once FPO and SUBVP are fully merged
1761 * the type name can be updated
1762 */
1763 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
1764 union {
1765 struct {
1766 uint32_t pix_clk_100hz;
1767 uint16_t main_vblank_start;
1768 uint16_t main_vblank_end;
1769 uint16_t mall_region_lines;
1770 uint16_t prefetch_lines;
1771 uint16_t prefetch_to_mall_start_lines;
1772 uint16_t processing_delay_lines;
1773 uint16_t htotal; // required to calculate line time for multi-display cases
1774 uint16_t vtotal;
1775 uint8_t main_pipe_index;
1776 uint8_t phantom_pipe_index;
1777 /* Since the microschedule is calculated in terms of OTG lines,
1778 * include any scaling factors to make sure when we get accurate
1779 * conversion when programming MALL_START_LINE (which is in terms
1780 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1781 * is 1/2 (numerator = 1, denominator = 2).
1782 */
1783 uint8_t scale_factor_numerator;
1784 uint8_t scale_factor_denominator;
1785 uint8_t is_drr;
1786 uint8_t main_split_pipe_index;
1787 uint8_t phantom_split_pipe_index;
1788 } subvp_data;
1789
1790 struct {
1791 uint32_t pix_clk_100hz;
1792 uint16_t vblank_start;
1793 uint16_t vblank_end;
1794 uint16_t vstartup_start;
1795 uint16_t vtotal;
1796 uint16_t htotal;
1797 uint8_t vblank_pipe_index;
1798 uint8_t padding[1];
1799 struct {
1800 uint8_t drr_in_use;
1801 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
1802 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
1803 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
1804 uint8_t use_ramping; // Use ramping or not
1805 uint8_t drr_vblank_start_margin;
1806 } drr_info; // DRR considered as part of SubVP + VBLANK case
1807 } vblank_data;
1808 } pipe_config;
1809
1810 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
1811 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1812 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1813 */
1814 uint8_t mode; // enum mclk_switch_mode
1815 };
1816
1817 /**
1818 * Config data for Sub-VP and FPO
1819 * Named "v2" for now -- once FPO and SUBVP are fully merged
1820 * the type name can be updated
1821 */
1822 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1823 uint16_t watermark_a_cache;
1824 uint8_t vertical_int_margin_us;
1825 uint8_t pstate_allow_width_us;
1826 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1827 };
1828
1829 /**
1830 * DMUB rb command definition for Sub-VP and FPO
1831 * Named "v2" for now -- once FPO and SUBVP are fully merged
1832 * the type name can be updated
1833 */
1834 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1835 struct dmub_cmd_header header;
1836 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1837 };
1838
1839 struct dmub_flip_addr_info {
1840 uint32_t surf_addr_lo;
1841 uint32_t surf_addr_c_lo;
1842 uint32_t meta_addr_lo;
1843 uint32_t meta_addr_c_lo;
1844 uint16_t surf_addr_hi;
1845 uint16_t surf_addr_c_hi;
1846 uint16_t meta_addr_hi;
1847 uint16_t meta_addr_c_hi;
1848 };
1849
1850 struct dmub_fams2_flip_info {
1851 union {
1852 struct {
1853 uint8_t is_immediate: 1;
1854 } bits;
1855 uint8_t all;
1856 } config;
1857 uint8_t otg_inst;
1858 uint8_t pipe_mask;
1859 uint8_t pad;
1860 struct dmub_flip_addr_info addr_info;
1861 };
1862
1863 struct dmub_rb_cmd_fams2_flip {
1864 struct dmub_cmd_header header;
1865 struct dmub_fams2_flip_info flip_info;
1866 };
1867
1868 struct dmub_optc_state_v2 {
1869 uint32_t v_total_min;
1870 uint32_t v_total_max;
1871 uint32_t v_total_mid;
1872 uint32_t v_total_mid_frame_num;
1873 uint8_t program_manual_trigger;
1874 uint8_t tg_inst;
1875 uint8_t pad[2];
1876 };
1877
1878 struct dmub_optc_position {
1879 uint32_t vpos;
1880 uint32_t hpos;
1881 uint32_t frame;
1882 };
1883
1884 struct dmub_rb_cmd_fams2_drr_update {
1885 struct dmub_cmd_header header;
1886 struct dmub_optc_state_v2 dmub_optc_state_req;
1887 };
1888
1889 /* HW and FW global configuration data for FAMS2 */
1890 /* FAMS2 types and structs */
1891 enum fams2_stream_type {
1892 FAMS2_STREAM_TYPE_NONE = 0,
1893 FAMS2_STREAM_TYPE_VBLANK = 1,
1894 FAMS2_STREAM_TYPE_VACTIVE = 2,
1895 FAMS2_STREAM_TYPE_DRR = 3,
1896 FAMS2_STREAM_TYPE_SUBVP = 4,
1897 };
1898
1899 /* static stream state */
1900 struct dmub_fams2_legacy_stream_static_state {
1901 uint8_t vactive_det_fill_delay_otg_vlines;
1902 uint8_t programming_delay_otg_vlines;
1903 }; //v0
1904
1905 struct dmub_fams2_subvp_stream_static_state {
1906 uint16_t vratio_numerator;
1907 uint16_t vratio_denominator;
1908 uint16_t phantom_vtotal;
1909 uint16_t phantom_vactive;
1910 union {
1911 struct {
1912 uint8_t is_multi_planar : 1;
1913 uint8_t is_yuv420 : 1;
1914 } bits;
1915 uint8_t all;
1916 } config;
1917 uint8_t programming_delay_otg_vlines;
1918 uint8_t prefetch_to_mall_otg_vlines;
1919 uint8_t phantom_otg_inst;
1920 uint8_t phantom_pipe_mask;
1921 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
1922 }; //v0
1923
1924 struct dmub_fams2_drr_stream_static_state {
1925 uint16_t nom_stretched_vtotal;
1926 uint8_t programming_delay_otg_vlines;
1927 uint8_t only_stretch_if_required;
1928 uint8_t pad[2];
1929 }; //v0
1930
1931 struct dmub_fams2_cmd_legacy_stream_static_state {
1932 uint16_t vactive_det_fill_delay_otg_vlines;
1933 uint16_t programming_delay_otg_vlines;
1934 }; //v1
1935
1936 struct dmub_fams2_cmd_subvp_stream_static_state {
1937 uint16_t vratio_numerator;
1938 uint16_t vratio_denominator;
1939 uint16_t phantom_vtotal;
1940 uint16_t phantom_vactive;
1941 uint16_t programming_delay_otg_vlines;
1942 uint16_t prefetch_to_mall_otg_vlines;
1943 union {
1944 struct {
1945 uint8_t is_multi_planar : 1;
1946 uint8_t is_yuv420 : 1;
1947 } bits;
1948 uint8_t all;
1949 } config;
1950 uint8_t phantom_otg_inst;
1951 uint8_t phantom_pipe_mask;
1952 uint8_t pad0;
1953 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
1954 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)];
1955 }; //v1
1956
1957 struct dmub_fams2_cmd_drr_stream_static_state {
1958 uint16_t nom_stretched_vtotal;
1959 uint16_t programming_delay_otg_vlines;
1960 uint8_t only_stretch_if_required;
1961 uint8_t pad[3];
1962 }; //v1
1963
1964 union dmub_fams2_stream_static_sub_state {
1965 struct dmub_fams2_legacy_stream_static_state legacy;
1966 struct dmub_fams2_subvp_stream_static_state subvp;
1967 struct dmub_fams2_drr_stream_static_state drr;
1968 }; //v0
1969
1970 union dmub_fams2_cmd_stream_static_sub_state {
1971 struct dmub_fams2_cmd_legacy_stream_static_state legacy;
1972 struct dmub_fams2_cmd_subvp_stream_static_state subvp;
1973 struct dmub_fams2_cmd_drr_stream_static_state drr;
1974 }; //v1
1975
1976 struct dmub_fams2_stream_static_state {
1977 enum fams2_stream_type type;
1978 uint32_t otg_vline_time_ns;
1979 uint32_t otg_vline_time_ticks;
1980 uint16_t htotal;
1981 uint16_t vtotal; // nominal vtotal
1982 uint16_t vblank_start;
1983 uint16_t vblank_end;
1984 uint16_t max_vtotal;
1985 uint16_t allow_start_otg_vline;
1986 uint16_t allow_end_otg_vline;
1987 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
1988 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
1989 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution
1990 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
1991 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
1992 union {
1993 struct {
1994 uint8_t is_drr: 1; // stream is DRR enabled
1995 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal
1996 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank
1997 } bits;
1998 uint8_t all;
1999 } config;
2000 uint8_t otg_inst;
2001 uint8_t pipe_mask; // pipe mask for the whole config
2002 uint8_t num_planes;
2003 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
2004 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];
2005 union dmub_fams2_stream_static_sub_state sub_state;
2006 }; //v0
2007
2008 struct dmub_fams2_cmd_stream_static_base_state {
2009 enum fams2_stream_type type;
2010 uint32_t otg_vline_time_ns;
2011 uint32_t otg_vline_time_ticks;
2012 uint16_t htotal;
2013 uint16_t vtotal; // nominal vtotal
2014 uint16_t vblank_start;
2015 uint16_t vblank_end;
2016 uint16_t max_vtotal;
2017 uint16_t allow_start_otg_vline;
2018 uint16_t allow_end_otg_vline;
2019 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
2020 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
2021 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution
2022 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
2023 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
2024 union {
2025 struct {
2026 uint8_t is_drr : 1; // stream is DRR enabled
2027 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal
2028 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank
2029 } bits;
2030 uint8_t all;
2031 } config;
2032 uint8_t otg_inst;
2033 uint8_t pipe_mask; // pipe mask for the whole config
2034 uint8_t num_planes;
2035 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
2036 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];
2037 }; //v1
2038
2039 struct dmub_fams2_stream_static_state_v1 {
2040 struct dmub_fams2_cmd_stream_static_base_state base;
2041 union dmub_fams2_cmd_stream_static_sub_state sub_state;
2042 }; //v1
2043
2044 /**
2045 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive
2046 * p-state request to allow latency
2047 */
2048 enum dmub_fams2_allow_delay_check_mode {
2049 /* No check for request to allow delay */
2050 FAMS2_ALLOW_DELAY_CHECK_NONE = 0,
2051 /* Check for request to allow delay */
2052 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1,
2053 /* Check for prepare to allow delay */
2054 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2,
2055 };
2056
2057 union dmub_fams2_global_feature_config {
2058 struct {
2059 uint32_t enable: 1;
2060 uint32_t enable_ppt_check: 1;
2061 uint32_t enable_stall_recovery: 1;
2062 uint32_t enable_debug: 1;
2063 uint32_t enable_offload_flip: 1;
2064 uint32_t enable_visual_confirm: 1;
2065 uint32_t allow_delay_check_mode: 2;
2066 uint32_t reserved: 24;
2067 } bits;
2068 uint32_t all;
2069 };
2070
2071 struct dmub_cmd_fams2_global_config {
2072 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin
2073 uint32_t lock_wait_time_us; // time to forecast acquisition of lock
2074 uint32_t num_streams;
2075 union dmub_fams2_global_feature_config features;
2076 uint32_t recovery_timeout_us;
2077 uint32_t hwfq_flip_programming_delay_us;
2078 };
2079
2080 union dmub_cmd_fams2_config {
2081 struct dmub_cmd_fams2_global_config global;
2082 struct dmub_fams2_stream_static_state stream; //v0
2083 union {
2084 struct dmub_fams2_cmd_stream_static_base_state base;
2085 union dmub_fams2_cmd_stream_static_sub_state sub_state;
2086 } stream_v1; //v1
2087 };
2088
2089 /**
2090 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy)
2091 */
2092 struct dmub_rb_cmd_fams2 {
2093 struct dmub_cmd_header header;
2094 union dmub_cmd_fams2_config config;
2095 };
2096
2097 /**
2098 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
2099 */
2100 enum dmub_cmd_idle_opt_type {
2101 /**
2102 * DCN hardware restore.
2103 */
2104 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
2105
2106 /**
2107 * DCN hardware save.
2108 */
2109 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
2110
2111 /**
2112 * DCN hardware notify idle.
2113 */
2114 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2,
2115
2116 /**
2117 * DCN hardware notify power state.
2118 */
2119 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3,
2120 };
2121
2122 /**
2123 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
2124 */
2125 struct dmub_rb_cmd_idle_opt_dcn_restore {
2126 struct dmub_cmd_header header; /**< header */
2127 };
2128
2129 /**
2130 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
2131 */
2132 struct dmub_dcn_notify_idle_cntl_data {
2133 uint8_t driver_idle;
2134 uint8_t skip_otg_disable;
2135 uint8_t reserved[58];
2136 };
2137
2138 /**
2139 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
2140 */
2141 struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
2142 struct dmub_cmd_header header; /**< header */
2143 struct dmub_dcn_notify_idle_cntl_data cntl_data;
2144 };
2145
2146 /**
2147 * enum dmub_idle_opt_dc_power_state - DC power states.
2148 */
2149 enum dmub_idle_opt_dc_power_state {
2150 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0,
2151 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1,
2152 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2,
2153 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4,
2154 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8,
2155 };
2156
2157 /**
2158 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
2159 */
2160 struct dmub_idle_opt_set_dc_power_state_data {
2161 uint8_t power_state; /**< power state */
2162 uint8_t pad[3]; /**< padding */
2163 };
2164
2165 /**
2166 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
2167 */
2168 struct dmub_rb_cmd_idle_opt_set_dc_power_state {
2169 struct dmub_cmd_header header; /**< header */
2170 struct dmub_idle_opt_set_dc_power_state_data data;
2171 };
2172
2173 /**
2174 * struct dmub_clocks - Clock update notification.
2175 */
2176 struct dmub_clocks {
2177 uint32_t dispclk_khz; /**< dispclk kHz */
2178 uint32_t dppclk_khz; /**< dppclk kHz */
2179 uint32_t dcfclk_khz; /**< dcfclk kHz */
2180 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
2181 };
2182
2183 /**
2184 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
2185 */
2186 enum dmub_cmd_clk_mgr_type {
2187 /**
2188 * Notify DMCUB of clock update.
2189 */
2190 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
2191 };
2192
2193 /**
2194 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
2195 */
2196 struct dmub_rb_cmd_clk_mgr_notify_clocks {
2197 struct dmub_cmd_header header; /**< header */
2198 struct dmub_clocks clocks; /**< clock data */
2199 };
2200
2201 /**
2202 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
2203 */
2204 struct dmub_cmd_digx_encoder_control_data {
2205 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
2206 };
2207
2208 /**
2209 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
2210 */
2211 struct dmub_rb_cmd_digx_encoder_control {
2212 struct dmub_cmd_header header; /**< header */
2213 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
2214 };
2215
2216 /**
2217 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
2218 */
2219 struct dmub_cmd_set_pixel_clock_data {
2220 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
2221 };
2222
2223 /**
2224 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
2225 */
2226 struct dmub_rb_cmd_set_pixel_clock {
2227 struct dmub_cmd_header header; /**< header */
2228 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
2229 };
2230
2231 /**
2232 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
2233 */
2234 struct dmub_cmd_enable_disp_power_gating_data {
2235 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
2236 };
2237
2238 /**
2239 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
2240 */
2241 struct dmub_rb_cmd_enable_disp_power_gating {
2242 struct dmub_cmd_header header; /**< header */
2243 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
2244 };
2245
2246 /**
2247 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
2248 */
2249 struct dmub_dig_transmitter_control_data_v1_7 {
2250 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
2251 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
2252 union {
2253 uint8_t digmode; /**< enum atom_encode_mode_def */
2254 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
2255 } mode_laneset;
2256 uint8_t lanenum; /**< Number of lanes */
2257 union {
2258 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
2259 } symclk_units;
2260 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
2261 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
2262 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
2263 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
2264 uint8_t reserved1; /**< For future use */
2265 uint8_t reserved2[3]; /**< For future use */
2266 uint32_t reserved3[11]; /**< For future use */
2267 };
2268
2269 /**
2270 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
2271 */
2272 union dmub_cmd_dig1_transmitter_control_data {
2273 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
2274 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
2275 };
2276
2277 /**
2278 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
2279 */
2280 struct dmub_rb_cmd_dig1_transmitter_control {
2281 struct dmub_cmd_header header; /**< header */
2282 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
2283 };
2284
2285 /**
2286 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
2287 */
2288 struct dmub_rb_cmd_domain_control_data {
2289 uint8_t inst : 6; /**< DOMAIN instance to control */
2290 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
2291 uint8_t reserved[3]; /**< Reserved for future use */
2292 };
2293
2294 /**
2295 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
2296 */
2297 struct dmub_rb_cmd_domain_control {
2298 struct dmub_cmd_header header; /**< header */
2299 struct dmub_rb_cmd_domain_control_data data; /**< payload */
2300 };
2301
2302 /**
2303 * DPIA tunnel command parameters.
2304 */
2305 struct dmub_cmd_dig_dpia_control_data {
2306 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
2307 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
2308 union {
2309 uint8_t digmode; /** enum atom_encode_mode_def */
2310 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
2311 } mode_laneset;
2312 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
2313 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
2314 uint8_t hpdsel; /** =0: HPD is not assigned */
2315 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
2316 uint8_t dpia_id; /** Index of DPIA */
2317 uint8_t fec_rdy : 1;
2318 uint8_t reserved : 7;
2319 uint32_t reserved1;
2320 };
2321
2322 /**
2323 * DMUB command for DPIA tunnel control.
2324 */
2325 struct dmub_rb_cmd_dig1_dpia_control {
2326 struct dmub_cmd_header header;
2327 struct dmub_cmd_dig_dpia_control_data dpia_control;
2328 };
2329
2330 /**
2331 * SET_CONFIG Command Payload (deprecated)
2332 */
2333 struct set_config_cmd_payload {
2334 uint8_t msg_type; /* set config message type */
2335 uint8_t msg_data; /* set config message data */
2336 };
2337
2338 /**
2339 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated)
2340 */
2341 struct dmub_cmd_set_config_control_data {
2342 struct set_config_cmd_payload cmd_pkt;
2343 uint8_t instance; /* DPIA instance */
2344 uint8_t immed_status; /* Immediate status returned in case of error */
2345 };
2346
2347 /**
2348 * SET_CONFIG Request Command Payload
2349 */
2350 struct set_config_request_cmd_payload {
2351 uint8_t instance; /* DPIA instance */
2352 uint8_t immed_status; /* Immediate status returned in case of error */
2353 uint8_t msg_type; /* set config message type */
2354 uint8_t reserved;
2355 uint32_t msg_data; /* set config message data */
2356 };
2357
2358 /**
2359 * DMUB command structure for SET_CONFIG command.
2360 */
2361 struct dmub_rb_cmd_set_config_access {
2362 struct dmub_cmd_header header; /* header */
2363 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
2364 };
2365
2366 /**
2367 * DMUB command structure for SET_CONFIG request command.
2368 */
2369 struct dmub_rb_cmd_set_config_request {
2370 struct dmub_cmd_header header; /* header */
2371 struct set_config_request_cmd_payload payload; /* set config request payload */
2372 };
2373
2374 /**
2375 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
2376 */
2377 struct dmub_cmd_mst_alloc_slots_control_data {
2378 uint8_t mst_alloc_slots; /* mst slots to be allotted */
2379 uint8_t instance; /* DPIA instance */
2380 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
2381 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
2382 };
2383
2384 /**
2385 * DMUB command structure for SET_ command.
2386 */
2387 struct dmub_rb_cmd_set_mst_alloc_slots {
2388 struct dmub_cmd_header header; /* header */
2389 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
2390 };
2391
2392 /**
2393 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command.
2394 */
2395 struct dmub_cmd_tps_notification_data {
2396 uint8_t instance; /* DPIA instance */
2397 uint8_t tps; /* requested training pattern */
2398 uint8_t reserved1;
2399 uint8_t reserved2;
2400 };
2401
2402 /**
2403 * DMUB command structure for SET_TPS_NOTIFICATION command.
2404 */
2405 struct dmub_rb_cmd_set_tps_notification {
2406 struct dmub_cmd_header header; /* header */
2407 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */
2408 };
2409
2410 /**
2411 * DMUB command structure for DPIA HPD int enable control.
2412 */
2413 struct dmub_rb_cmd_dpia_hpd_int_enable {
2414 struct dmub_cmd_header header; /* header */
2415 uint32_t enable; /* dpia hpd interrupt enable */
2416 };
2417
2418 /**
2419 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
2420 */
2421 struct dmub_rb_cmd_dpphy_init {
2422 struct dmub_cmd_header header; /**< header */
2423 uint8_t reserved[60]; /**< reserved bits */
2424 };
2425
2426 /**
2427 * enum dp_aux_request_action - DP AUX request command listing.
2428 *
2429 * 4 AUX request command bits are shifted to high nibble.
2430 */
2431 enum dp_aux_request_action {
2432 /** I2C-over-AUX write request */
2433 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
2434 /** I2C-over-AUX read request */
2435 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
2436 /** I2C-over-AUX write status request */
2437 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
2438 /** I2C-over-AUX write request with MOT=1 */
2439 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
2440 /** I2C-over-AUX read request with MOT=1 */
2441 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
2442 /** I2C-over-AUX write status request with MOT=1 */
2443 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
2444 /** Native AUX write request */
2445 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
2446 /** Native AUX read request */
2447 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
2448 };
2449
2450 /**
2451 * enum aux_return_code_type - DP AUX process return code listing.
2452 */
2453 enum aux_return_code_type {
2454 /** AUX process succeeded */
2455 AUX_RET_SUCCESS = 0,
2456 /** AUX process failed with unknown reason */
2457 AUX_RET_ERROR_UNKNOWN,
2458 /** AUX process completed with invalid reply */
2459 AUX_RET_ERROR_INVALID_REPLY,
2460 /** AUX process timed out */
2461 AUX_RET_ERROR_TIMEOUT,
2462 /** HPD was low during AUX process */
2463 AUX_RET_ERROR_HPD_DISCON,
2464 /** Failed to acquire AUX engine */
2465 AUX_RET_ERROR_ENGINE_ACQUIRE,
2466 /** AUX request not supported */
2467 AUX_RET_ERROR_INVALID_OPERATION,
2468 /** AUX process not available */
2469 AUX_RET_ERROR_PROTOCOL_ERROR,
2470 };
2471
2472 /**
2473 * enum aux_channel_type - DP AUX channel type listing.
2474 */
2475 enum aux_channel_type {
2476 /** AUX thru Legacy DP AUX */
2477 AUX_CHANNEL_LEGACY_DDC,
2478 /** AUX thru DPIA DP tunneling */
2479 AUX_CHANNEL_DPIA
2480 };
2481
2482 /**
2483 * struct aux_transaction_parameters - DP AUX request transaction data
2484 */
2485 struct aux_transaction_parameters {
2486 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
2487 uint8_t action; /**< enum dp_aux_request_action */
2488 uint8_t length; /**< DP AUX request data length */
2489 uint8_t reserved; /**< For future use */
2490 uint32_t address; /**< DP AUX address */
2491 uint8_t data[16]; /**< DP AUX write data */
2492 };
2493
2494 /**
2495 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
2496 */
2497 struct dmub_cmd_dp_aux_control_data {
2498 uint8_t instance; /**< AUX instance or DPIA instance */
2499 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
2500 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
2501 uint8_t reserved0; /**< For future use */
2502 uint16_t timeout; /**< timeout time in us */
2503 uint16_t reserved1; /**< For future use */
2504 enum aux_channel_type type; /**< enum aux_channel_type */
2505 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
2506 };
2507
2508 /**
2509 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
2510 */
2511 struct dmub_rb_cmd_dp_aux_access {
2512 /**
2513 * Command header.
2514 */
2515 struct dmub_cmd_header header;
2516 /**
2517 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
2518 */
2519 struct dmub_cmd_dp_aux_control_data aux_control;
2520 };
2521
2522 /**
2523 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
2524 */
2525 struct dmub_rb_cmd_outbox1_enable {
2526 /**
2527 * Command header.
2528 */
2529 struct dmub_cmd_header header;
2530 /**
2531 * enable: 0x0 -> disable outbox1 notification (default value)
2532 * 0x1 -> enable outbox1 notification
2533 */
2534 uint32_t enable;
2535 };
2536
2537 /* DP AUX Reply command - OutBox Cmd */
2538 /**
2539 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2540 */
2541 struct aux_reply_data {
2542 /**
2543 * Aux cmd
2544 */
2545 uint8_t command;
2546 /**
2547 * Aux reply data length (max: 16 bytes)
2548 */
2549 uint8_t length;
2550 /**
2551 * Alignment only
2552 */
2553 uint8_t pad[2];
2554 /**
2555 * Aux reply data
2556 */
2557 uint8_t data[16];
2558 };
2559
2560 /**
2561 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2562 */
2563 struct aux_reply_control_data {
2564 /**
2565 * Reserved for future use
2566 */
2567 uint32_t handle;
2568 /**
2569 * Aux Instance
2570 */
2571 uint8_t instance;
2572 /**
2573 * Aux transaction result: definition in enum aux_return_code_type
2574 */
2575 uint8_t result;
2576 /**
2577 * Alignment only
2578 */
2579 uint16_t pad;
2580 };
2581
2582 /**
2583 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
2584 */
2585 struct dmub_rb_cmd_dp_aux_reply {
2586 /**
2587 * Command header.
2588 */
2589 struct dmub_cmd_header header;
2590 /**
2591 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2592 */
2593 struct aux_reply_control_data control;
2594 /**
2595 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2596 */
2597 struct aux_reply_data reply_data;
2598 };
2599
2600 /* DP HPD Notify command - OutBox Cmd */
2601 /**
2602 * DP HPD Type
2603 */
2604 enum dp_hpd_type {
2605 /**
2606 * Normal DP HPD
2607 */
2608 DP_HPD = 0,
2609 /**
2610 * DP HPD short pulse
2611 */
2612 DP_IRQ
2613 };
2614
2615 /**
2616 * DP HPD Status
2617 */
2618 enum dp_hpd_status {
2619 /**
2620 * DP_HPD status low
2621 */
2622 DP_HPD_UNPLUG = 0,
2623 /**
2624 * DP_HPD status high
2625 */
2626 DP_HPD_PLUG
2627 };
2628
2629 /**
2630 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2631 */
2632 struct dp_hpd_data {
2633 /**
2634 * DP HPD instance
2635 */
2636 uint8_t instance;
2637 /**
2638 * HPD type
2639 */
2640 uint8_t hpd_type;
2641 /**
2642 * HPD status: only for type: DP_HPD to indicate status
2643 */
2644 uint8_t hpd_status;
2645 /**
2646 * Alignment only
2647 */
2648 uint8_t pad;
2649 };
2650
2651 /**
2652 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2653 */
2654 struct dmub_rb_cmd_dp_hpd_notify {
2655 /**
2656 * Command header.
2657 */
2658 struct dmub_cmd_header header;
2659 /**
2660 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2661 */
2662 struct dp_hpd_data hpd_data;
2663 };
2664
2665 /**
2666 * Definition of a SET_CONFIG reply from DPOA.
2667 */
2668 enum set_config_status {
2669 SET_CONFIG_PENDING = 0,
2670 SET_CONFIG_ACK_RECEIVED,
2671 SET_CONFIG_RX_TIMEOUT,
2672 SET_CONFIG_UNKNOWN_ERROR,
2673 };
2674
2675 /**
2676 * Definition of a set_config reply
2677 */
2678 struct set_config_reply_control_data {
2679 uint8_t instance; /* DPIA Instance */
2680 uint8_t status; /* Set Config reply */
2681 uint16_t pad; /* Alignment */
2682 };
2683
2684 /**
2685 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
2686 */
2687 struct dmub_rb_cmd_dp_set_config_reply {
2688 struct dmub_cmd_header header;
2689 struct set_config_reply_control_data set_config_reply_control;
2690 };
2691
2692 /**
2693 * Definition of a DPIA notification header
2694 */
2695 struct dpia_notification_header {
2696 uint8_t instance; /**< DPIA Instance */
2697 uint8_t reserved[3];
2698 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
2699 };
2700
2701 /**
2702 * Definition of the common data struct of DPIA notification
2703 */
2704 struct dpia_notification_common {
2705 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
2706 - sizeof(struct dpia_notification_header)];
2707 };
2708
2709 /**
2710 * Definition of a DPIA notification data
2711 */
2712 struct dpia_bw_allocation_notify_data {
2713 union {
2714 struct {
2715 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
2716 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
2717 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
2718 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
2719 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
2720 uint16_t reserved: 11; /**< Reserved */
2721 } bits;
2722
2723 uint16_t flags;
2724 };
2725
2726 uint8_t cm_id; /**< CM ID */
2727 uint8_t group_id; /**< Group ID */
2728 uint8_t granularity; /**< BW Allocation Granularity */
2729 uint8_t estimated_bw; /**< Estimated_BW */
2730 uint8_t allocated_bw; /**< Allocated_BW */
2731 uint8_t reserved;
2732 };
2733
2734 /**
2735 * union dpia_notify_data_type - DPIA Notification in Outbox command
2736 */
2737 union dpia_notification_data {
2738 /**
2739 * DPIA Notification for common data struct
2740 */
2741 struct dpia_notification_common common_data;
2742
2743 /**
2744 * DPIA Notification for DP BW Allocation support
2745 */
2746 struct dpia_bw_allocation_notify_data dpia_bw_alloc;
2747 };
2748
2749 /**
2750 * Definition of a DPIA notification payload
2751 */
2752 struct dpia_notification_payload {
2753 struct dpia_notification_header header;
2754 union dpia_notification_data data; /**< DPIA notification payload data */
2755 };
2756
2757 /**
2758 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
2759 */
2760 struct dmub_rb_cmd_dpia_notification {
2761 struct dmub_cmd_header header; /**< DPIA notification header */
2762 struct dpia_notification_payload payload; /**< DPIA notification payload */
2763 };
2764
2765 /**
2766 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
2767 */
2768 struct dmub_cmd_hpd_state_query_data {
2769 uint8_t instance; /**< HPD instance or DPIA instance */
2770 uint8_t result; /**< For returning HPD state */
2771 uint16_t pad; /** < Alignment */
2772 enum aux_channel_type ch_type; /**< enum aux_channel_type */
2773 enum aux_return_code_type status; /**< for returning the status of command */
2774 };
2775
2776 /**
2777 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
2778 */
2779 struct dmub_rb_cmd_query_hpd_state {
2780 /**
2781 * Command header.
2782 */
2783 struct dmub_cmd_header header;
2784 /**
2785 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
2786 */
2787 struct dmub_cmd_hpd_state_query_data data;
2788 };
2789
2790 /**
2791 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data.
2792 */
2793 struct dmub_rb_cmd_hpd_sense_notify_data {
2794 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */
2795 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */
2796 };
2797
2798 /**
2799 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command.
2800 */
2801 struct dmub_rb_cmd_hpd_sense_notify {
2802 struct dmub_cmd_header header; /**< header */
2803 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */
2804 };
2805
2806 /*
2807 * Command IDs should be treated as stable ABI.
2808 * Do not reuse or modify IDs.
2809 */
2810
2811 /**
2812 * PSR command sub-types.
2813 */
2814 enum dmub_cmd_psr_type {
2815 /**
2816 * Set PSR version support.
2817 */
2818 DMUB_CMD__PSR_SET_VERSION = 0,
2819 /**
2820 * Copy driver-calculated parameters to PSR state.
2821 */
2822 DMUB_CMD__PSR_COPY_SETTINGS = 1,
2823 /**
2824 * Enable PSR.
2825 */
2826 DMUB_CMD__PSR_ENABLE = 2,
2827
2828 /**
2829 * Disable PSR.
2830 */
2831 DMUB_CMD__PSR_DISABLE = 3,
2832
2833 /**
2834 * Set PSR level.
2835 * PSR level is a 16-bit value dicated by driver that
2836 * will enable/disable different functionality.
2837 */
2838 DMUB_CMD__PSR_SET_LEVEL = 4,
2839
2840 /**
2841 * Forces PSR enabled until an explicit PSR disable call.
2842 */
2843 DMUB_CMD__PSR_FORCE_STATIC = 5,
2844 /**
2845 * Set vtotal in psr active for FreeSync PSR.
2846 */
2847 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
2848 /**
2849 * Set PSR power option
2850 */
2851 DMUB_CMD__SET_PSR_POWER_OPT = 7,
2852 };
2853
2854 /**
2855 * Different PSR residency modes.
2856 * Different modes change the definition of PSR residency.
2857 */
2858 enum psr_residency_mode {
2859 PSR_RESIDENCY_MODE_PHY = 0,
2860 PSR_RESIDENCY_MODE_ALPM,
2861 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
2862 /* Do not add below. */
2863 PSR_RESIDENCY_MODE_LAST_ELEMENT,
2864 };
2865
2866 enum dmub_cmd_fams_type {
2867 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
2868 DMUB_CMD__FAMS_DRR_UPDATE = 1,
2869 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
2870 /**
2871 * For SubVP set manual trigger in FW because it
2872 * triggers DRR_UPDATE_PENDING which SubVP relies
2873 * on (for any SubVP cases that use a DRR display)
2874 */
2875 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
2876 DMUB_CMD__FAMS2_CONFIG = 4,
2877 DMUB_CMD__FAMS2_DRR_UPDATE = 5,
2878 DMUB_CMD__FAMS2_FLIP = 6,
2879 };
2880
2881 /**
2882 * PSR versions.
2883 */
2884 enum psr_version {
2885 /**
2886 * PSR version 1.
2887 */
2888 PSR_VERSION_1 = 0,
2889 /**
2890 * Freesync PSR SU.
2891 */
2892 PSR_VERSION_SU_1 = 1,
2893 /**
2894 * PSR not supported.
2895 */
2896 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide
2897 };
2898
2899 /**
2900 * PHY Link rate for DP.
2901 */
2902 enum phy_link_rate {
2903 /**
2904 * not supported.
2905 */
2906 PHY_RATE_UNKNOWN = 0,
2907 /**
2908 * Rate_1 (RBR) - 1.62 Gbps/Lane
2909 */
2910 PHY_RATE_162 = 1,
2911 /**
2912 * Rate_2 - 2.16 Gbps/Lane
2913 */
2914 PHY_RATE_216 = 2,
2915 /**
2916 * Rate_3 - 2.43 Gbps/Lane
2917 */
2918 PHY_RATE_243 = 3,
2919 /**
2920 * Rate_4 (HBR) - 2.70 Gbps/Lane
2921 */
2922 PHY_RATE_270 = 4,
2923 /**
2924 * Rate_5 (RBR2)- 3.24 Gbps/Lane
2925 */
2926 PHY_RATE_324 = 5,
2927 /**
2928 * Rate_6 - 4.32 Gbps/Lane
2929 */
2930 PHY_RATE_432 = 6,
2931 /**
2932 * Rate_7 (HBR2)- 5.40 Gbps/Lane
2933 */
2934 PHY_RATE_540 = 7,
2935 /**
2936 * Rate_8 (HBR3)- 8.10 Gbps/Lane
2937 */
2938 PHY_RATE_810 = 8,
2939 /**
2940 * UHBR10 - 10.0 Gbps/Lane
2941 */
2942 PHY_RATE_1000 = 9,
2943 /**
2944 * UHBR13.5 - 13.5 Gbps/Lane
2945 */
2946 PHY_RATE_1350 = 10,
2947 /**
2948 * UHBR10 - 20.0 Gbps/Lane
2949 */
2950 PHY_RATE_2000 = 11,
2951
2952 PHY_RATE_675 = 12,
2953 /**
2954 * Rate 12 - 6.75 Gbps/Lane
2955 */
2956 };
2957
2958 /**
2959 * enum dmub_phy_fsm_state - PHY FSM states.
2960 * PHY FSM state to transit to during PSR enable/disable.
2961 */
2962 enum dmub_phy_fsm_state {
2963 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
2964 DMUB_PHY_FSM_RESET,
2965 DMUB_PHY_FSM_RESET_RELEASED,
2966 DMUB_PHY_FSM_SRAM_LOAD_DONE,
2967 DMUB_PHY_FSM_INITIALIZED,
2968 DMUB_PHY_FSM_CALIBRATED,
2969 DMUB_PHY_FSM_CALIBRATED_LP,
2970 DMUB_PHY_FSM_CALIBRATED_PG,
2971 DMUB_PHY_FSM_POWER_DOWN,
2972 DMUB_PHY_FSM_PLL_EN,
2973 DMUB_PHY_FSM_TX_EN,
2974 DMUB_PHY_FSM_TX_EN_TEST_MODE,
2975 DMUB_PHY_FSM_FAST_LP,
2976 DMUB_PHY_FSM_P2_PLL_OFF_CPM,
2977 DMUB_PHY_FSM_P2_PLL_OFF_PG,
2978 DMUB_PHY_FSM_P2_PLL_OFF,
2979 DMUB_PHY_FSM_P2_PLL_ON,
2980 };
2981
2982 /**
2983 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2984 */
2985 struct dmub_cmd_psr_copy_settings_data {
2986 /**
2987 * Flags that can be set by driver to change some PSR behaviour.
2988 */
2989 union dmub_psr_debug_flags debug;
2990 /**
2991 * 16-bit value dicated by driver that will enable/disable different functionality.
2992 */
2993 uint16_t psr_level;
2994 /**
2995 * DPP HW instance.
2996 */
2997 uint8_t dpp_inst;
2998 /**
2999 * MPCC HW instance.
3000 * Not used in dmub fw,
3001 * dmub fw will get active opp by reading odm registers.
3002 */
3003 uint8_t mpcc_inst;
3004 /**
3005 * OPP HW instance.
3006 * Not used in dmub fw,
3007 * dmub fw will get active opp by reading odm registers.
3008 */
3009 uint8_t opp_inst;
3010 /**
3011 * OTG HW instance.
3012 */
3013 uint8_t otg_inst;
3014 /**
3015 * DIG FE HW instance.
3016 */
3017 uint8_t digfe_inst;
3018 /**
3019 * DIG BE HW instance.
3020 */
3021 uint8_t digbe_inst;
3022 /**
3023 * DP PHY HW instance.
3024 */
3025 uint8_t dpphy_inst;
3026 /**
3027 * AUX HW instance.
3028 */
3029 uint8_t aux_inst;
3030 /**
3031 * Determines if SMU optimzations are enabled/disabled.
3032 */
3033 uint8_t smu_optimizations_en;
3034 /**
3035 * Unused.
3036 * TODO: Remove.
3037 */
3038 uint8_t frame_delay;
3039 /**
3040 * If RFB setup time is greater than the total VBLANK time,
3041 * it is not possible for the sink to capture the video frame
3042 * in the same frame the SDP is sent. In this case,
3043 * the frame capture indication bit should be set and an extra
3044 * static frame should be transmitted to the sink.
3045 */
3046 uint8_t frame_cap_ind;
3047 /**
3048 * Granularity of Y offset supported by sink.
3049 */
3050 uint8_t su_y_granularity;
3051 /**
3052 * Indicates whether sink should start capturing
3053 * immediately following active scan line,
3054 * or starting with the 2nd active scan line.
3055 */
3056 uint8_t line_capture_indication;
3057 /**
3058 * Multi-display optimizations are implemented on certain ASICs.
3059 */
3060 uint8_t multi_disp_optimizations_en;
3061 /**
3062 * The last possible line SDP may be transmitted without violating
3063 * the RFB setup time or entering the active video frame.
3064 */
3065 uint16_t init_sdp_deadline;
3066 /**
3067 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
3068 */
3069 uint8_t rate_control_caps ;
3070 /*
3071 * Force PSRSU always doing full frame update
3072 */
3073 uint8_t force_ffu_mode;
3074 /**
3075 * Length of each horizontal line in us.
3076 */
3077 uint32_t line_time_in_us;
3078 /**
3079 * FEC enable status in driver
3080 */
3081 uint8_t fec_enable_status;
3082 /**
3083 * FEC re-enable delay when PSR exit.
3084 * unit is 100us, range form 0~255(0xFF).
3085 */
3086 uint8_t fec_enable_delay_in100us;
3087 /**
3088 * PSR control version.
3089 */
3090 uint8_t cmd_version;
3091 /**
3092 * Panel Instance.
3093 * Panel instance to identify which psr_state to use
3094 * Currently the support is only for 0 or 1
3095 */
3096 uint8_t panel_inst;
3097 /*
3098 * DSC enable status in driver
3099 */
3100 uint8_t dsc_enable_status;
3101 /*
3102 * Use FSM state for PSR power up/down
3103 */
3104 uint8_t use_phy_fsm;
3105 /**
3106 * frame delay for frame re-lock
3107 */
3108 uint8_t relock_delay_frame_cnt;
3109 /**
3110 * esd recovery indicate.
3111 */
3112 uint8_t esd_recovery;
3113 /**
3114 * DSC Slice height.
3115 */
3116 uint16_t dsc_slice_height;
3117 /**
3118 * Some panels request main link off before xth vertical line
3119 */
3120 uint16_t poweroff_before_vertical_line;
3121 };
3122
3123 /**
3124 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
3125 */
3126 struct dmub_rb_cmd_psr_copy_settings {
3127 /**
3128 * Command header.
3129 */
3130 struct dmub_cmd_header header;
3131 /**
3132 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
3133 */
3134 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
3135 };
3136
3137 /**
3138 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
3139 */
3140 struct dmub_cmd_psr_set_level_data {
3141 /**
3142 * 16-bit value dicated by driver that will enable/disable different functionality.
3143 */
3144 uint16_t psr_level;
3145 /**
3146 * PSR control version.
3147 */
3148 uint8_t cmd_version;
3149 /**
3150 * Panel Instance.
3151 * Panel instance to identify which psr_state to use
3152 * Currently the support is only for 0 or 1
3153 */
3154 uint8_t panel_inst;
3155 };
3156
3157 /**
3158 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3159 */
3160 struct dmub_rb_cmd_psr_set_level {
3161 /**
3162 * Command header.
3163 */
3164 struct dmub_cmd_header header;
3165 /**
3166 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3167 */
3168 struct dmub_cmd_psr_set_level_data psr_set_level_data;
3169 };
3170
3171 struct dmub_rb_cmd_psr_enable_data {
3172 /**
3173 * PSR control version.
3174 */
3175 uint8_t cmd_version;
3176 /**
3177 * Panel Instance.
3178 * Panel instance to identify which psr_state to use
3179 * Currently the support is only for 0 or 1
3180 */
3181 uint8_t panel_inst;
3182 /**
3183 * Phy state to enter.
3184 * Values to use are defined in dmub_phy_fsm_state
3185 */
3186 uint8_t phy_fsm_state;
3187 /**
3188 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
3189 * Set this using enum phy_link_rate.
3190 * This does not support HDMI/DP2 for now.
3191 */
3192 uint8_t phy_rate;
3193 };
3194
3195 /**
3196 * Definition of a DMUB_CMD__PSR_ENABLE command.
3197 * PSR enable/disable is controlled using the sub_type.
3198 */
3199 struct dmub_rb_cmd_psr_enable {
3200 /**
3201 * Command header.
3202 */
3203 struct dmub_cmd_header header;
3204
3205 struct dmub_rb_cmd_psr_enable_data data;
3206 };
3207
3208 /**
3209 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
3210 */
3211 struct dmub_cmd_psr_set_version_data {
3212 /**
3213 * PSR version that FW should implement.
3214 */
3215 enum psr_version version;
3216 /**
3217 * PSR control version.
3218 */
3219 uint8_t cmd_version;
3220 /**
3221 * Panel Instance.
3222 * Panel instance to identify which psr_state to use
3223 * Currently the support is only for 0 or 1
3224 */
3225 uint8_t panel_inst;
3226 /**
3227 * Explicit padding to 4 byte boundary.
3228 */
3229 uint8_t pad[2];
3230 };
3231
3232 /**
3233 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
3234 */
3235 struct dmub_rb_cmd_psr_set_version {
3236 /**
3237 * Command header.
3238 */
3239 struct dmub_cmd_header header;
3240 /**
3241 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
3242 */
3243 struct dmub_cmd_psr_set_version_data psr_set_version_data;
3244 };
3245
3246 struct dmub_cmd_psr_force_static_data {
3247 /**
3248 * PSR control version.
3249 */
3250 uint8_t cmd_version;
3251 /**
3252 * Panel Instance.
3253 * Panel instance to identify which psr_state to use
3254 * Currently the support is only for 0 or 1
3255 */
3256 uint8_t panel_inst;
3257 /**
3258 * Explicit padding to 4 byte boundary.
3259 */
3260 uint8_t pad[2];
3261 };
3262
3263 /**
3264 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3265 */
3266 struct dmub_rb_cmd_psr_force_static {
3267 /**
3268 * Command header.
3269 */
3270 struct dmub_cmd_header header;
3271 /**
3272 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
3273 */
3274 struct dmub_cmd_psr_force_static_data psr_force_static_data;
3275 };
3276
3277 /**
3278 * PSR SU debug flags.
3279 */
3280 union dmub_psr_su_debug_flags {
3281 /**
3282 * PSR SU debug flags.
3283 */
3284 struct {
3285 /**
3286 * Update dirty rect in SW only.
3287 */
3288 uint8_t update_dirty_rect_only : 1;
3289 /**
3290 * Reset the cursor/plane state before processing the call.
3291 */
3292 uint8_t reset_state : 1;
3293 } bitfields;
3294
3295 /**
3296 * Union for debug flags.
3297 */
3298 uint32_t u32All;
3299 };
3300
3301 /**
3302 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
3303 * This triggers a selective update for PSR SU.
3304 */
3305 struct dmub_cmd_update_dirty_rect_data {
3306 /**
3307 * Dirty rects from OS.
3308 */
3309 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
3310 /**
3311 * PSR SU debug flags.
3312 */
3313 union dmub_psr_su_debug_flags debug_flags;
3314 /**
3315 * OTG HW instance.
3316 */
3317 uint8_t pipe_idx;
3318 /**
3319 * Number of dirty rects.
3320 */
3321 uint8_t dirty_rect_count;
3322 /**
3323 * PSR control version.
3324 */
3325 uint8_t cmd_version;
3326 /**
3327 * Panel Instance.
3328 * Panel instance to identify which psr_state to use
3329 * Currently the support is only for 0 or 1
3330 */
3331 uint8_t panel_inst;
3332 };
3333
3334 /**
3335 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
3336 */
3337 struct dmub_rb_cmd_update_dirty_rect {
3338 /**
3339 * Command header.
3340 */
3341 struct dmub_cmd_header header;
3342 /**
3343 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
3344 */
3345 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
3346 };
3347
3348 /**
3349 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
3350 */
3351 union dmub_reg_cursor_control_cfg {
3352 struct {
3353 uint32_t cur_enable: 1;
3354 uint32_t reser0: 3;
3355 uint32_t cur_2x_magnify: 1;
3356 uint32_t reser1: 3;
3357 uint32_t mode: 3;
3358 uint32_t reser2: 5;
3359 uint32_t pitch: 2;
3360 uint32_t reser3: 6;
3361 uint32_t line_per_chunk: 5;
3362 uint32_t reser4: 3;
3363 } bits;
3364 uint32_t raw;
3365 };
3366 struct dmub_cursor_position_cache_hubp {
3367 union dmub_reg_cursor_control_cfg cur_ctl;
3368 union dmub_reg_position_cfg {
3369 struct {
3370 uint32_t cur_x_pos: 16;
3371 uint32_t cur_y_pos: 16;
3372 } bits;
3373 uint32_t raw;
3374 } position;
3375 union dmub_reg_hot_spot_cfg {
3376 struct {
3377 uint32_t hot_x: 16;
3378 uint32_t hot_y: 16;
3379 } bits;
3380 uint32_t raw;
3381 } hot_spot;
3382 union dmub_reg_dst_offset_cfg {
3383 struct {
3384 uint32_t dst_x_offset: 13;
3385 uint32_t reserved: 19;
3386 } bits;
3387 uint32_t raw;
3388 } dst_offset;
3389 };
3390
3391 union dmub_reg_cur0_control_cfg {
3392 struct {
3393 uint32_t cur0_enable: 1;
3394 uint32_t expansion_mode: 1;
3395 uint32_t reser0: 1;
3396 uint32_t cur0_rom_en: 1;
3397 uint32_t mode: 3;
3398 uint32_t reserved: 25;
3399 } bits;
3400 uint32_t raw;
3401 };
3402 struct dmub_cursor_position_cache_dpp {
3403 union dmub_reg_cur0_control_cfg cur0_ctl;
3404 };
3405 struct dmub_cursor_position_cfg {
3406 struct dmub_cursor_position_cache_hubp pHubp;
3407 struct dmub_cursor_position_cache_dpp pDpp;
3408 uint8_t pipe_idx;
3409 /*
3410 * Padding is required. To be 4 Bytes Aligned.
3411 */
3412 uint8_t padding[3];
3413 };
3414
3415 struct dmub_cursor_attribute_cache_hubp {
3416 uint32_t SURFACE_ADDR_HIGH;
3417 uint32_t SURFACE_ADDR;
3418 union dmub_reg_cursor_control_cfg cur_ctl;
3419 union dmub_reg_cursor_size_cfg {
3420 struct {
3421 uint32_t width: 16;
3422 uint32_t height: 16;
3423 } bits;
3424 uint32_t raw;
3425 } size;
3426 union dmub_reg_cursor_settings_cfg {
3427 struct {
3428 uint32_t dst_y_offset: 8;
3429 uint32_t chunk_hdl_adjust: 2;
3430 uint32_t reserved: 22;
3431 } bits;
3432 uint32_t raw;
3433 } settings;
3434 };
3435 struct dmub_cursor_attribute_cache_dpp {
3436 union dmub_reg_cur0_control_cfg cur0_ctl;
3437 };
3438 struct dmub_cursor_attributes_cfg {
3439 struct dmub_cursor_attribute_cache_hubp aHubp;
3440 struct dmub_cursor_attribute_cache_dpp aDpp;
3441 };
3442
3443 struct dmub_cmd_update_cursor_payload0 {
3444 /**
3445 * Cursor dirty rects.
3446 */
3447 struct dmub_rect cursor_rect;
3448 /**
3449 * PSR SU debug flags.
3450 */
3451 union dmub_psr_su_debug_flags debug_flags;
3452 /**
3453 * Cursor enable/disable.
3454 */
3455 uint8_t enable;
3456 /**
3457 * OTG HW instance.
3458 */
3459 uint8_t pipe_idx;
3460 /**
3461 * PSR control version.
3462 */
3463 uint8_t cmd_version;
3464 /**
3465 * Panel Instance.
3466 * Panel instance to identify which psr_state to use
3467 * Currently the support is only for 0 or 1
3468 */
3469 uint8_t panel_inst;
3470 /**
3471 * Cursor Position Register.
3472 * Registers contains Hubp & Dpp modules
3473 */
3474 struct dmub_cursor_position_cfg position_cfg;
3475 };
3476
3477 struct dmub_cmd_update_cursor_payload1 {
3478 struct dmub_cursor_attributes_cfg attribute_cfg;
3479 };
3480
3481 union dmub_cmd_update_cursor_info_data {
3482 struct dmub_cmd_update_cursor_payload0 payload0;
3483 struct dmub_cmd_update_cursor_payload1 payload1;
3484 };
3485 /**
3486 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
3487 */
3488 struct dmub_rb_cmd_update_cursor_info {
3489 /**
3490 * Command header.
3491 */
3492 struct dmub_cmd_header header;
3493 /**
3494 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
3495 */
3496 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
3497 };
3498
3499 /**
3500 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3501 */
3502 struct dmub_cmd_psr_set_vtotal_data {
3503 /**
3504 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
3505 */
3506 uint16_t psr_vtotal_idle;
3507 /**
3508 * PSR control version.
3509 */
3510 uint8_t cmd_version;
3511 /**
3512 * Panel Instance.
3513 * Panel instance to identify which psr_state to use
3514 * Currently the support is only for 0 or 1
3515 */
3516 uint8_t panel_inst;
3517 /*
3518 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
3519 */
3520 uint16_t psr_vtotal_su;
3521 /**
3522 * Explicit padding to 4 byte boundary.
3523 */
3524 uint8_t pad2[2];
3525 };
3526
3527 /**
3528 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3529 */
3530 struct dmub_rb_cmd_psr_set_vtotal {
3531 /**
3532 * Command header.
3533 */
3534 struct dmub_cmd_header header;
3535 /**
3536 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3537 */
3538 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
3539 };
3540
3541 /**
3542 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
3543 */
3544 struct dmub_cmd_psr_set_power_opt_data {
3545 /**
3546 * PSR control version.
3547 */
3548 uint8_t cmd_version;
3549 /**
3550 * Panel Instance.
3551 * Panel instance to identify which psr_state to use
3552 * Currently the support is only for 0 or 1
3553 */
3554 uint8_t panel_inst;
3555 /**
3556 * Explicit padding to 4 byte boundary.
3557 */
3558 uint8_t pad[2];
3559 /**
3560 * PSR power option
3561 */
3562 uint32_t power_opt;
3563 };
3564
3565 /**
3566 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3567 */
3568 struct dmub_rb_cmd_psr_set_power_opt {
3569 /**
3570 * Command header.
3571 */
3572 struct dmub_cmd_header header;
3573 /**
3574 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3575 */
3576 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
3577 };
3578
3579 /**
3580 * Definition of Replay Residency GPINT command.
3581 * Bit[0] - Residency mode for Revision 0
3582 * Bit[1] - Enable/Disable state
3583 * Bit[2-3] - Revision number
3584 * Bit[4-7] - Residency mode for Revision 1
3585 * Bit[8] - Panel instance
3586 * Bit[9-15] - Reserved
3587 */
3588
3589 enum pr_residency_mode {
3590 PR_RESIDENCY_MODE_PHY = 0x0,
3591 PR_RESIDENCY_MODE_ALPM,
3592 PR_RESIDENCY_MODE_IPS2,
3593 PR_RESIDENCY_MODE_FRAME_CNT,
3594 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
3595 };
3596
3597 #define REPLAY_RESIDENCY_MODE_SHIFT (0)
3598 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
3599 #define REPLAY_RESIDENCY_REVISION_SHIFT (2)
3600 #define REPLAY_RESIDENCY_MODE2_SHIFT (4)
3601
3602 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
3603 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
3604 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
3605
3606 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT)
3607 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT)
3608 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT)
3609 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT)
3610
3611 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3612 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3613 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3614
3615 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT)
3616 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT)
3617 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT)
3618
3619 /**
3620 * Definition of a replay_state.
3621 */
3622 enum replay_state {
3623 REPLAY_STATE_0 = 0x0,
3624 REPLAY_STATE_1 = 0x10,
3625 REPLAY_STATE_1A = 0x11,
3626 REPLAY_STATE_2 = 0x20,
3627 REPLAY_STATE_2A = 0x21,
3628 REPLAY_STATE_3 = 0x30,
3629 REPLAY_STATE_3INIT = 0x31,
3630 REPLAY_STATE_4 = 0x40,
3631 REPLAY_STATE_4A = 0x41,
3632 REPLAY_STATE_4B = 0x42,
3633 REPLAY_STATE_4C = 0x43,
3634 REPLAY_STATE_4D = 0x44,
3635 REPLAY_STATE_4E = 0x45,
3636 REPLAY_STATE_4B_LOCKED = 0x4A,
3637 REPLAY_STATE_4C_UNLOCKED = 0x4B,
3638 REPLAY_STATE_5 = 0x50,
3639 REPLAY_STATE_5A = 0x51,
3640 REPLAY_STATE_5B = 0x52,
3641 REPLAY_STATE_5A_LOCKED = 0x5A,
3642 REPLAY_STATE_5B_UNLOCKED = 0x5B,
3643 REPLAY_STATE_6 = 0x60,
3644 REPLAY_STATE_6A = 0x61,
3645 REPLAY_STATE_6B = 0x62,
3646 REPLAY_STATE_INVALID = 0xFF,
3647 };
3648
3649 /**
3650 * Replay command sub-types.
3651 */
3652 enum dmub_cmd_replay_type {
3653 /**
3654 * Copy driver-calculated parameters to REPLAY state.
3655 */
3656 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
3657 /**
3658 * Enable REPLAY.
3659 */
3660 DMUB_CMD__REPLAY_ENABLE = 1,
3661 /**
3662 * Set Replay power option.
3663 */
3664 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
3665 /**
3666 * Set coasting vtotal.
3667 */
3668 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
3669 /**
3670 * Set power opt and coasting vtotal.
3671 */
3672 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4,
3673 /**
3674 * Set disabled iiming sync.
3675 */
3676 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5,
3677 /**
3678 * Set Residency Frameupdate Timer.
3679 */
3680 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,
3681 /**
3682 * Set pseudo vtotal
3683 */
3684 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
3685 /**
3686 * Set adaptive sync sdp enabled
3687 */
3688 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,
3689 /**
3690 * Set Replay General command.
3691 */
3692 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,
3693 };
3694
3695 /**
3696 * Replay general command sub-types.
3697 */
3698 enum dmub_cmd_replay_general_subtype {
3699 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1,
3700 /**
3701 * TODO: For backward compatible, allow new command only.
3702 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED,
3703 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER,
3704 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL,
3705 */
3706 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,
3707 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,
3708 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS,
3709 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE,
3710 };
3711
3712 /**
3713 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3714 */
3715 struct dmub_cmd_replay_copy_settings_data {
3716 /**
3717 * Flags that can be set by driver to change some replay behaviour.
3718 */
3719 union replay_debug_flags debug;
3720
3721 /**
3722 * @flags: Flags used to determine feature functionality.
3723 */
3724 union replay_hw_flags flags;
3725
3726 /**
3727 * DPP HW instance.
3728 */
3729 uint8_t dpp_inst;
3730 /**
3731 * OTG HW instance.
3732 */
3733 uint8_t otg_inst;
3734 /**
3735 * DIG FE HW instance.
3736 */
3737 uint8_t digfe_inst;
3738 /**
3739 * DIG BE HW instance.
3740 */
3741 uint8_t digbe_inst;
3742 /**
3743 * AUX HW instance.
3744 */
3745 uint8_t aux_inst;
3746 /**
3747 * Panel Instance.
3748 * Panel isntance to identify which psr_state to use
3749 * Currently the support is only for 0 or 1
3750 */
3751 uint8_t panel_inst;
3752 /**
3753 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
3754 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
3755 */
3756 uint8_t pixel_deviation_per_line;
3757 /**
3758 * @max_deviation_line: The max number of deviation line that can keep the timing
3759 * synchronized between the Source and Sink during Replay normal sleep mode.
3760 */
3761 uint8_t max_deviation_line;
3762 /**
3763 * Length of each horizontal line in ns.
3764 */
3765 uint32_t line_time_in_ns;
3766 /**
3767 * PHY instance.
3768 */
3769 uint8_t dpphy_inst;
3770 /**
3771 * Determines if SMU optimzations are enabled/disabled.
3772 */
3773 uint8_t smu_optimizations_en;
3774 /**
3775 * Determines if timing sync are enabled/disabled.
3776 */
3777 uint8_t replay_timing_sync_supported;
3778 /*
3779 * Use FSM state for Replay power up/down
3780 */
3781 uint8_t use_phy_fsm;
3782 };
3783
3784 /**
3785 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3786 */
3787 struct dmub_rb_cmd_replay_copy_settings {
3788 /**
3789 * Command header.
3790 */
3791 struct dmub_cmd_header header;
3792 /**
3793 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3794 */
3795 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
3796 };
3797
3798 /**
3799 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
3800 */
3801 enum replay_enable {
3802 /**
3803 * Disable REPLAY.
3804 */
3805 REPLAY_DISABLE = 0,
3806 /**
3807 * Enable REPLAY.
3808 */
3809 REPLAY_ENABLE = 1,
3810 };
3811
3812 /**
3813 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
3814 */
3815 struct dmub_rb_cmd_replay_enable_data {
3816 /**
3817 * Replay enable or disable.
3818 */
3819 uint8_t enable;
3820 /**
3821 * Panel Instance.
3822 * Panel isntance to identify which replay_state to use
3823 * Currently the support is only for 0 or 1
3824 */
3825 uint8_t panel_inst;
3826 /**
3827 * Phy state to enter.
3828 * Values to use are defined in dmub_phy_fsm_state
3829 */
3830 uint8_t phy_fsm_state;
3831 /**
3832 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
3833 * Set this using enum phy_link_rate.
3834 * This does not support HDMI/DP2 for now.
3835 */
3836 uint8_t phy_rate;
3837 };
3838
3839 /**
3840 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
3841 * Replay enable/disable is controlled using action in data.
3842 */
3843 struct dmub_rb_cmd_replay_enable {
3844 /**
3845 * Command header.
3846 */
3847 struct dmub_cmd_header header;
3848
3849 struct dmub_rb_cmd_replay_enable_data data;
3850 };
3851
3852 /**
3853 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3854 */
3855 struct dmub_cmd_replay_set_power_opt_data {
3856 /**
3857 * Panel Instance.
3858 * Panel isntance to identify which replay_state to use
3859 * Currently the support is only for 0 or 1
3860 */
3861 uint8_t panel_inst;
3862 /**
3863 * Explicit padding to 4 byte boundary.
3864 */
3865 uint8_t pad[3];
3866 /**
3867 * REPLAY power option
3868 */
3869 uint32_t power_opt;
3870 };
3871
3872 /**
3873 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3874 */
3875 struct dmub_cmd_replay_set_timing_sync_data {
3876 /**
3877 * Panel Instance.
3878 * Panel isntance to identify which replay_state to use
3879 * Currently the support is only for 0 or 1
3880 */
3881 uint8_t panel_inst;
3882 /**
3883 * REPLAY set_timing_sync
3884 */
3885 uint8_t timing_sync_supported;
3886 /**
3887 * Explicit padding to 4 byte boundary.
3888 */
3889 uint8_t pad[2];
3890 };
3891
3892 /**
3893 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3894 */
3895 struct dmub_cmd_replay_set_pseudo_vtotal {
3896 /**
3897 * Panel Instance.
3898 * Panel isntance to identify which replay_state to use
3899 * Currently the support is only for 0 or 1
3900 */
3901 uint8_t panel_inst;
3902 /**
3903 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal
3904 */
3905 uint16_t vtotal;
3906 /**
3907 * Explicit padding to 4 byte boundary.
3908 */
3909 uint8_t pad;
3910 };
3911 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {
3912 /**
3913 * Panel Instance.
3914 * Panel isntance to identify which replay_state to use
3915 * Currently the support is only for 0 or 1
3916 */
3917 uint8_t panel_inst;
3918 /**
3919 * enabled: set adaptive sync sdp enabled
3920 */
3921 uint8_t force_disabled;
3922
3923 uint8_t pad[2];
3924 };
3925 struct dmub_cmd_replay_set_general_cmd_data {
3926 /**
3927 * Panel Instance.
3928 * Panel isntance to identify which replay_state to use
3929 * Currently the support is only for 0 or 1
3930 */
3931 uint8_t panel_inst;
3932 /**
3933 * subtype: replay general cmd sub type
3934 */
3935 uint8_t subtype;
3936
3937 uint8_t pad[2];
3938 /**
3939 * config data with param1 and param2
3940 */
3941 uint32_t param1;
3942
3943 uint32_t param2;
3944 };
3945
3946 /**
3947 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3948 */
3949 struct dmub_rb_cmd_replay_set_power_opt {
3950 /**
3951 * Command header.
3952 */
3953 struct dmub_cmd_header header;
3954 /**
3955 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3956 */
3957 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
3958 };
3959
3960 /**
3961 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3962 */
3963 struct dmub_cmd_replay_set_coasting_vtotal_data {
3964 /**
3965 * 16-bit value dicated by driver that indicates the coasting vtotal.
3966 */
3967 uint16_t coasting_vtotal;
3968 /**
3969 * REPLAY control version.
3970 */
3971 uint8_t cmd_version;
3972 /**
3973 * Panel Instance.
3974 * Panel isntance to identify which replay_state to use
3975 * Currently the support is only for 0 or 1
3976 */
3977 uint8_t panel_inst;
3978 /**
3979 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part.
3980 */
3981 uint16_t coasting_vtotal_high;
3982 /**
3983 * Explicit padding to 4 byte boundary.
3984 */
3985 uint8_t pad[2];
3986 };
3987
3988 /**
3989 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3990 */
3991 struct dmub_rb_cmd_replay_set_coasting_vtotal {
3992 /**
3993 * Command header.
3994 */
3995 struct dmub_cmd_header header;
3996 /**
3997 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3998 */
3999 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
4000 };
4001
4002 /**
4003 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
4004 */
4005 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {
4006 /**
4007 * Command header.
4008 */
4009 struct dmub_cmd_header header;
4010 /**
4011 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4012 */
4013 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
4014 /**
4015 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4016 */
4017 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
4018 };
4019
4020 /**
4021 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
4022 */
4023 struct dmub_rb_cmd_replay_set_timing_sync {
4024 /**
4025 * Command header.
4026 */
4027 struct dmub_cmd_header header;
4028 /**
4029 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
4030 */
4031 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;
4032 };
4033
4034 /**
4035 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4036 */
4037 struct dmub_rb_cmd_replay_set_pseudo_vtotal {
4038 /**
4039 * Command header.
4040 */
4041 struct dmub_cmd_header header;
4042 /**
4043 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4044 */
4045 struct dmub_cmd_replay_set_pseudo_vtotal data;
4046 };
4047
4048 /**
4049 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
4050 */
4051 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {
4052 /**
4053 * Command header.
4054 */
4055 struct dmub_cmd_header header;
4056 /**
4057 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
4058 */
4059 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;
4060 };
4061
4062 /**
4063 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
4064 */
4065 struct dmub_rb_cmd_replay_set_general_cmd {
4066 /**
4067 * Command header.
4068 */
4069 struct dmub_cmd_header header;
4070 /**
4071 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
4072 */
4073 struct dmub_cmd_replay_set_general_cmd_data data;
4074 };
4075
4076 /**
4077 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
4078 */
4079 struct dmub_cmd_replay_frameupdate_timer_data {
4080 /**
4081 * Panel Instance.
4082 * Panel isntance to identify which replay_state to use
4083 * Currently the support is only for 0 or 1
4084 */
4085 uint8_t panel_inst;
4086 /**
4087 * Replay Frameupdate Timer Enable or not
4088 */
4089 uint8_t enable;
4090 /**
4091 * REPLAY force reflash frame update number
4092 */
4093 uint16_t frameupdate_count;
4094 };
4095 /**
4096 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER
4097 */
4098 struct dmub_rb_cmd_replay_set_frameupdate_timer {
4099 /**
4100 * Command header.
4101 */
4102 struct dmub_cmd_header header;
4103 /**
4104 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4105 */
4106 struct dmub_cmd_replay_frameupdate_timer_data data;
4107 };
4108
4109 /**
4110 * Definition union of replay command set
4111 */
4112 union dmub_replay_cmd_set {
4113 /**
4114 * Panel Instance.
4115 * Panel isntance to identify which replay_state to use
4116 * Currently the support is only for 0 or 1
4117 */
4118 uint8_t panel_inst;
4119 /**
4120 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data.
4121 */
4122 struct dmub_cmd_replay_set_timing_sync_data sync_data;
4123 /**
4124 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data.
4125 */
4126 struct dmub_cmd_replay_frameupdate_timer_data timer_data;
4127 /**
4128 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
4129 */
4130 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
4131 /**
4132 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.
4133 */
4134 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;
4135 /**
4136 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data.
4137 */
4138 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;
4139 };
4140
4141 /**
4142 * Set of HW components that can be locked.
4143 *
4144 * Note: If updating with more HW components, fields
4145 * in dmub_inbox0_cmd_lock_hw must be updated to match.
4146 */
4147 union dmub_hw_lock_flags {
4148 /**
4149 * Set of HW components that can be locked.
4150 */
4151 struct {
4152 /**
4153 * Lock/unlock OTG master update lock.
4154 */
4155 uint8_t lock_pipe : 1;
4156 /**
4157 * Lock/unlock cursor.
4158 */
4159 uint8_t lock_cursor : 1;
4160 /**
4161 * Lock/unlock global update lock.
4162 */
4163 uint8_t lock_dig : 1;
4164 /**
4165 * Triple buffer lock requires additional hw programming to usual OTG master lock.
4166 */
4167 uint8_t triple_buffer_lock : 1;
4168 } bits;
4169
4170 /**
4171 * Union for HW Lock flags.
4172 */
4173 uint8_t u8All;
4174 };
4175
4176 /**
4177 * Instances of HW to be locked.
4178 *
4179 * Note: If updating with more HW components, fields
4180 * in dmub_inbox0_cmd_lock_hw must be updated to match.
4181 */
4182 struct dmub_hw_lock_inst_flags {
4183 /**
4184 * OTG HW instance for OTG master update lock.
4185 */
4186 uint8_t otg_inst;
4187 /**
4188 * OPP instance for cursor lock.
4189 */
4190 uint8_t opp_inst;
4191 /**
4192 * OTG HW instance for global update lock.
4193 * TODO: Remove, and re-use otg_inst.
4194 */
4195 uint8_t dig_inst;
4196 /**
4197 * Explicit pad to 4 byte boundary.
4198 */
4199 uint8_t pad;
4200 };
4201
4202 /**
4203 * Clients that can acquire the HW Lock Manager.
4204 *
4205 * Note: If updating with more clients, fields in
4206 * dmub_inbox0_cmd_lock_hw must be updated to match.
4207 */
4208 enum hw_lock_client {
4209 /**
4210 * Driver is the client of HW Lock Manager.
4211 */
4212 HW_LOCK_CLIENT_DRIVER = 0,
4213 /**
4214 * PSR SU is the client of HW Lock Manager.
4215 */
4216 HW_LOCK_CLIENT_PSR_SU = 1,
4217 HW_LOCK_CLIENT_SUBVP = 3,
4218 /**
4219 * Replay is the client of HW Lock Manager.
4220 */
4221 HW_LOCK_CLIENT_REPLAY = 4,
4222 HW_LOCK_CLIENT_FAMS2 = 5,
4223 /**
4224 * Invalid client.
4225 */
4226 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
4227 };
4228
4229 /**
4230 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
4231 */
4232 struct dmub_cmd_lock_hw_data {
4233 /**
4234 * Specifies the client accessing HW Lock Manager.
4235 */
4236 enum hw_lock_client client;
4237 /**
4238 * HW instances to be locked.
4239 */
4240 struct dmub_hw_lock_inst_flags inst_flags;
4241 /**
4242 * Which components to be locked.
4243 */
4244 union dmub_hw_lock_flags hw_locks;
4245 /**
4246 * Specifies lock/unlock.
4247 */
4248 uint8_t lock;
4249 /**
4250 * HW can be unlocked separately from releasing the HW Lock Mgr.
4251 * This flag is set if the client wishes to release the object.
4252 */
4253 uint8_t should_release;
4254 /**
4255 * Explicit padding to 4 byte boundary.
4256 */
4257 uint8_t pad;
4258 };
4259
4260 /**
4261 * Definition of a DMUB_CMD__HW_LOCK command.
4262 * Command is used by driver and FW.
4263 */
4264 struct dmub_rb_cmd_lock_hw {
4265 /**
4266 * Command header.
4267 */
4268 struct dmub_cmd_header header;
4269 /**
4270 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
4271 */
4272 struct dmub_cmd_lock_hw_data lock_hw_data;
4273 };
4274
4275 /**
4276 * ABM command sub-types.
4277 */
4278 enum dmub_cmd_abm_type {
4279 /**
4280 * Initialize parameters for ABM algorithm.
4281 * Data is passed through an indirect buffer.
4282 */
4283 DMUB_CMD__ABM_INIT_CONFIG = 0,
4284 /**
4285 * Set OTG and panel HW instance.
4286 */
4287 DMUB_CMD__ABM_SET_PIPE = 1,
4288 /**
4289 * Set user requested backklight level.
4290 */
4291 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
4292 /**
4293 * Set ABM operating/aggression level.
4294 */
4295 DMUB_CMD__ABM_SET_LEVEL = 3,
4296 /**
4297 * Set ambient light level.
4298 */
4299 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
4300 /**
4301 * Enable/disable fractional duty cycle for backlight PWM.
4302 */
4303 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
4304
4305 /**
4306 * unregister vertical interrupt after steady state is reached
4307 */
4308 DMUB_CMD__ABM_PAUSE = 6,
4309
4310 /**
4311 * Save and Restore ABM state. On save we save parameters, and
4312 * on restore we update state with passed in data.
4313 */
4314 DMUB_CMD__ABM_SAVE_RESTORE = 7,
4315
4316 /**
4317 * Query ABM caps.
4318 */
4319 DMUB_CMD__ABM_QUERY_CAPS = 8,
4320
4321 /**
4322 * Set ABM Events
4323 */
4324 DMUB_CMD__ABM_SET_EVENT = 9,
4325
4326 /**
4327 * Get the current ACE curve.
4328 */
4329 DMUB_CMD__ABM_GET_ACE_CURVE = 10,
4330 };
4331
4332 struct abm_ace_curve {
4333 /**
4334 * @offsets: ACE curve offsets.
4335 */
4336 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4337
4338 /**
4339 * @thresholds: ACE curve thresholds.
4340 */
4341 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4342
4343 /**
4344 * @slopes: ACE curve slopes.
4345 */
4346 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4347 };
4348
4349 struct fixed_pt_format {
4350 /**
4351 * @sign_bit: Indicates whether one bit is reserved for the sign.
4352 */
4353 bool sign_bit;
4354
4355 /**
4356 * @num_int_bits: Number of bits used for integer part.
4357 */
4358 uint8_t num_int_bits;
4359
4360 /**
4361 * @num_frac_bits: Number of bits used for fractional part.
4362 */
4363 uint8_t num_frac_bits;
4364
4365 /**
4366 * @pad: Explicit padding to 4 byte boundary.
4367 */
4368 uint8_t pad;
4369 };
4370
4371 struct abm_caps {
4372 /**
4373 * @num_hg_bins: Number of histogram bins.
4374 */
4375 uint8_t num_hg_bins;
4376
4377 /**
4378 * @num_ace_segments: Number of ACE curve segments.
4379 */
4380 uint8_t num_ace_segments;
4381
4382 /**
4383 * @pad: Explicit padding to 4 byte boundary.
4384 */
4385 uint8_t pad[2];
4386
4387 /**
4388 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0.
4389 */
4390 struct fixed_pt_format ace_thresholds_format;
4391
4392 /**
4393 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0.
4394 */
4395 struct fixed_pt_format ace_offsets_format;
4396
4397 /**
4398 * @ace_slopes_format: Format of the ACE slopes.
4399 */
4400 struct fixed_pt_format ace_slopes_format;
4401 };
4402
4403 /**
4404 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
4405 * Requirements:
4406 * - Padded explicitly to 32-bit boundary.
4407 * - Must ensure this structure matches the one on driver-side,
4408 * otherwise it won't be aligned.
4409 */
4410 struct abm_config_table {
4411 /**
4412 * Gamma curve thresholds, used for crgb conversion.
4413 */
4414 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
4415 /**
4416 * Gamma curve offsets, used for crgb conversion.
4417 */
4418 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
4419 /**
4420 * Gamma curve slopes, used for crgb conversion.
4421 */
4422 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
4423 /**
4424 * Custom backlight curve thresholds.
4425 */
4426 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
4427 /**
4428 * Custom backlight curve offsets.
4429 */
4430 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
4431 /**
4432 * Ambient light thresholds.
4433 */
4434 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
4435 /**
4436 * Minimum programmable backlight.
4437 */
4438 uint16_t min_abm_backlight; // 122B
4439 /**
4440 * Minimum reduction values.
4441 */
4442 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
4443 /**
4444 * Maximum reduction values.
4445 */
4446 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
4447 /**
4448 * Bright positive gain.
4449 */
4450 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
4451 /**
4452 * Dark negative gain.
4453 */
4454 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
4455 /**
4456 * Hybrid factor.
4457 */
4458 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
4459 /**
4460 * Contrast factor.
4461 */
4462 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
4463 /**
4464 * Deviation gain.
4465 */
4466 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
4467 /**
4468 * Minimum knee.
4469 */
4470 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
4471 /**
4472 * Maximum knee.
4473 */
4474 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
4475 /**
4476 * Unused.
4477 */
4478 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
4479 /**
4480 * Explicit padding to 4 byte boundary.
4481 */
4482 uint8_t pad3[3]; // 229B
4483 /**
4484 * Backlight ramp reduction.
4485 */
4486 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
4487 /**
4488 * Backlight ramp start.
4489 */
4490 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
4491 };
4492
4493 /**
4494 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
4495 */
4496 struct dmub_cmd_abm_set_pipe_data {
4497 /**
4498 * OTG HW instance.
4499 */
4500 uint8_t otg_inst;
4501
4502 /**
4503 * Panel Control HW instance.
4504 */
4505 uint8_t panel_inst;
4506
4507 /**
4508 * Controls how ABM will interpret a set pipe or set level command.
4509 */
4510 uint8_t set_pipe_option;
4511
4512 /**
4513 * Unused.
4514 * TODO: Remove.
4515 */
4516 uint8_t ramping_boundary;
4517
4518 /**
4519 * PwrSeq HW Instance.
4520 */
4521 uint8_t pwrseq_inst;
4522
4523 /**
4524 * Explicit padding to 4 byte boundary.
4525 */
4526 uint8_t pad[3];
4527 };
4528
4529 /**
4530 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
4531 */
4532 struct dmub_rb_cmd_abm_set_pipe {
4533 /**
4534 * Command header.
4535 */
4536 struct dmub_cmd_header header;
4537
4538 /**
4539 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
4540 */
4541 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
4542 };
4543
4544 /**
4545 * Type of backlight control method to be used by ABM module
4546 */
4547 enum dmub_backlight_control_type {
4548 /**
4549 * PWM Backlight control
4550 */
4551 DMU_BACKLIGHT_CONTROL_PWM = 0,
4552 /**
4553 * VESA Aux-based backlight control
4554 */
4555 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1,
4556 /**
4557 * AMD DPCD Aux-based backlight control
4558 */
4559 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2,
4560 };
4561
4562 /**
4563 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
4564 */
4565 struct dmub_cmd_abm_set_backlight_data {
4566 /**
4567 * Number of frames to ramp to backlight user level.
4568 */
4569 uint32_t frame_ramp;
4570
4571 /**
4572 * Requested backlight level from user.
4573 */
4574 uint32_t backlight_user_level;
4575
4576 /**
4577 * ABM control version.
4578 */
4579 uint8_t version;
4580
4581 /**
4582 * Panel Control HW instance mask.
4583 * Bit 0 is Panel Control HW instance 0.
4584 * Bit 1 is Panel Control HW instance 1.
4585 */
4586 uint8_t panel_mask;
4587
4588 /**
4589 * AUX HW Instance.
4590 */
4591 uint8_t aux_inst;
4592
4593 /**
4594 * Explicit padding to 4 byte boundary.
4595 */
4596 uint8_t pad[1];
4597
4598 /**
4599 * Backlight control type.
4600 * Value 0 is PWM backlight control.
4601 * Value 1 is VAUX backlight control.
4602 * Value 2 is AMD DPCD AUX backlight control.
4603 */
4604 enum dmub_backlight_control_type backlight_control_type;
4605
4606 /**
4607 * Minimum luminance in nits.
4608 */
4609 uint32_t min_luminance;
4610
4611 /**
4612 * Maximum luminance in nits.
4613 */
4614 uint32_t max_luminance;
4615
4616 /**
4617 * Minimum backlight in pwm.
4618 */
4619 uint32_t min_backlight_pwm;
4620
4621 /**
4622 * Maximum backlight in pwm.
4623 */
4624 uint32_t max_backlight_pwm;
4625 };
4626
4627 /**
4628 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
4629 */
4630 struct dmub_rb_cmd_abm_set_backlight {
4631 /**
4632 * Command header.
4633 */
4634 struct dmub_cmd_header header;
4635
4636 /**
4637 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
4638 */
4639 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
4640 };
4641
4642 /**
4643 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
4644 */
4645 struct dmub_cmd_abm_set_level_data {
4646 /**
4647 * Set current ABM operating/aggression level.
4648 */
4649 uint32_t level;
4650
4651 /**
4652 * ABM control version.
4653 */
4654 uint8_t version;
4655
4656 /**
4657 * Panel Control HW instance mask.
4658 * Bit 0 is Panel Control HW instance 0.
4659 * Bit 1 is Panel Control HW instance 1.
4660 */
4661 uint8_t panel_mask;
4662
4663 /**
4664 * Explicit padding to 4 byte boundary.
4665 */
4666 uint8_t pad[2];
4667 };
4668
4669 /**
4670 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
4671 */
4672 struct dmub_rb_cmd_abm_set_level {
4673 /**
4674 * Command header.
4675 */
4676 struct dmub_cmd_header header;
4677
4678 /**
4679 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
4680 */
4681 struct dmub_cmd_abm_set_level_data abm_set_level_data;
4682 };
4683
4684 /**
4685 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4686 */
4687 struct dmub_cmd_abm_set_ambient_level_data {
4688 /**
4689 * Ambient light sensor reading from OS.
4690 */
4691 uint32_t ambient_lux;
4692
4693 /**
4694 * ABM control version.
4695 */
4696 uint8_t version;
4697
4698 /**
4699 * Panel Control HW instance mask.
4700 * Bit 0 is Panel Control HW instance 0.
4701 * Bit 1 is Panel Control HW instance 1.
4702 */
4703 uint8_t panel_mask;
4704
4705 /**
4706 * Explicit padding to 4 byte boundary.
4707 */
4708 uint8_t pad[2];
4709 };
4710
4711 /**
4712 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4713 */
4714 struct dmub_rb_cmd_abm_set_ambient_level {
4715 /**
4716 * Command header.
4717 */
4718 struct dmub_cmd_header header;
4719
4720 /**
4721 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4722 */
4723 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
4724 };
4725
4726 /**
4727 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
4728 */
4729 struct dmub_cmd_abm_set_pwm_frac_data {
4730 /**
4731 * Enable/disable fractional duty cycle for backlight PWM.
4732 * TODO: Convert to uint8_t.
4733 */
4734 uint32_t fractional_pwm;
4735
4736 /**
4737 * ABM control version.
4738 */
4739 uint8_t version;
4740
4741 /**
4742 * Panel Control HW instance mask.
4743 * Bit 0 is Panel Control HW instance 0.
4744 * Bit 1 is Panel Control HW instance 1.
4745 */
4746 uint8_t panel_mask;
4747
4748 /**
4749 * Explicit padding to 4 byte boundary.
4750 */
4751 uint8_t pad[2];
4752 };
4753
4754 /**
4755 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
4756 */
4757 struct dmub_rb_cmd_abm_set_pwm_frac {
4758 /**
4759 * Command header.
4760 */
4761 struct dmub_cmd_header header;
4762
4763 /**
4764 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
4765 */
4766 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
4767 };
4768
4769 /**
4770 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4771 */
4772 struct dmub_cmd_abm_init_config_data {
4773 /**
4774 * Location of indirect buffer used to pass init data to ABM.
4775 */
4776 union dmub_addr src;
4777
4778 /**
4779 * Indirect buffer length.
4780 */
4781 uint16_t bytes;
4782
4783
4784 /**
4785 * ABM control version.
4786 */
4787 uint8_t version;
4788
4789 /**
4790 * Panel Control HW instance mask.
4791 * Bit 0 is Panel Control HW instance 0.
4792 * Bit 1 is Panel Control HW instance 1.
4793 */
4794 uint8_t panel_mask;
4795
4796 /**
4797 * Explicit padding to 4 byte boundary.
4798 */
4799 uint8_t pad[2];
4800 };
4801
4802 /**
4803 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
4804 */
4805 struct dmub_rb_cmd_abm_init_config {
4806 /**
4807 * Command header.
4808 */
4809 struct dmub_cmd_header header;
4810
4811 /**
4812 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4813 */
4814 struct dmub_cmd_abm_init_config_data abm_init_config_data;
4815 };
4816
4817 /**
4818 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
4819 */
4820
4821 struct dmub_cmd_abm_pause_data {
4822
4823 /**
4824 * Panel Control HW instance mask.
4825 * Bit 0 is Panel Control HW instance 0.
4826 * Bit 1 is Panel Control HW instance 1.
4827 */
4828 uint8_t panel_mask;
4829
4830 /**
4831 * OTG hw instance
4832 */
4833 uint8_t otg_inst;
4834
4835 /**
4836 * Enable or disable ABM pause
4837 */
4838 uint8_t enable;
4839
4840 /**
4841 * Explicit padding to 4 byte boundary.
4842 */
4843 uint8_t pad[1];
4844 };
4845
4846 /**
4847 * Definition of a DMUB_CMD__ABM_PAUSE command.
4848 */
4849 struct dmub_rb_cmd_abm_pause {
4850 /**
4851 * Command header.
4852 */
4853 struct dmub_cmd_header header;
4854
4855 /**
4856 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
4857 */
4858 struct dmub_cmd_abm_pause_data abm_pause_data;
4859 };
4860
4861 /**
4862 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command.
4863 */
4864 struct dmub_cmd_abm_query_caps_in {
4865 /**
4866 * Panel instance.
4867 */
4868 uint8_t panel_inst;
4869
4870 /**
4871 * Explicit padding to 4 byte boundary.
4872 */
4873 uint8_t pad[3];
4874 };
4875
4876 /**
4877 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command.
4878 */
4879 struct dmub_cmd_abm_query_caps_out {
4880 /**
4881 * SW Algorithm caps.
4882 */
4883 struct abm_caps sw_caps;
4884
4885 /**
4886 * ABM HW caps.
4887 */
4888 struct abm_caps hw_caps;
4889 };
4890
4891 /**
4892 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
4893 */
4894 struct dmub_rb_cmd_abm_query_caps {
4895 /**
4896 * Command header.
4897 */
4898 struct dmub_cmd_header header;
4899
4900 /**
4901 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command.
4902 */
4903 union {
4904 struct dmub_cmd_abm_query_caps_in abm_query_caps_in;
4905 struct dmub_cmd_abm_query_caps_out abm_query_caps_out;
4906 } data;
4907 };
4908
4909 /**
4910 * enum dmub_abm_ace_curve_type - ACE curve type.
4911 */
4912 enum dmub_abm_ace_curve_type {
4913 /**
4914 * ACE curve as defined by the SW layer.
4915 */
4916 ABM_ACE_CURVE_TYPE__SW = 0,
4917 /**
4918 * ACE curve as defined by the SW to HW translation interface layer.
4919 */
4920 ABM_ACE_CURVE_TYPE__SW_IF = 1,
4921 };
4922
4923 /**
4924 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
4925 */
4926 struct dmub_rb_cmd_abm_get_ace_curve {
4927 /**
4928 * Command header.
4929 */
4930 struct dmub_cmd_header header;
4931
4932 /**
4933 * Address where ACE curve should be copied.
4934 */
4935 union dmub_addr dest;
4936
4937 /**
4938 * Type of ACE curve being queried.
4939 */
4940 enum dmub_abm_ace_curve_type ace_type;
4941
4942 /**
4943 * Indirect buffer length.
4944 */
4945 uint16_t bytes;
4946
4947 /**
4948 * eDP panel instance.
4949 */
4950 uint8_t panel_inst;
4951
4952 /**
4953 * Explicit padding to 4 byte boundary.
4954 */
4955 uint8_t pad;
4956 };
4957
4958 /**
4959 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
4960 */
4961 struct dmub_rb_cmd_abm_save_restore {
4962 /**
4963 * Command header.
4964 */
4965 struct dmub_cmd_header header;
4966
4967 /**
4968 * OTG hw instance
4969 */
4970 uint8_t otg_inst;
4971
4972 /**
4973 * Enable or disable ABM pause
4974 */
4975 uint8_t freeze;
4976
4977 /**
4978 * Explicit padding to 4 byte boundary.
4979 */
4980 uint8_t debug;
4981
4982 /**
4983 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4984 */
4985 struct dmub_cmd_abm_init_config_data abm_init_config_data;
4986 };
4987
4988 /**
4989 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
4990 */
4991
4992 struct dmub_cmd_abm_set_event_data {
4993
4994 /**
4995 * VB Scaling Init. Strength Mapping
4996 * Byte 0: 0~255 for VB level 0
4997 * Byte 1: 0~255 for VB level 1
4998 * Byte 2: 0~255 for VB level 2
4999 * Byte 3: 0~255 for VB level 3
5000 */
5001 uint32_t vb_scaling_strength_mapping;
5002 /**
5003 * VariBright Scaling Enable
5004 */
5005 uint8_t vb_scaling_enable;
5006 /**
5007 * Panel Control HW instance mask.
5008 * Bit 0 is Panel Control HW instance 0.
5009 * Bit 1 is Panel Control HW instance 1.
5010 */
5011 uint8_t panel_mask;
5012
5013 /**
5014 * Explicit padding to 4 byte boundary.
5015 */
5016 uint8_t pad[2];
5017 };
5018
5019 /**
5020 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
5021 */
5022 struct dmub_rb_cmd_abm_set_event {
5023 /**
5024 * Command header.
5025 */
5026 struct dmub_cmd_header header;
5027
5028 /**
5029 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
5030 */
5031 struct dmub_cmd_abm_set_event_data abm_set_event_data;
5032 };
5033
5034 /**
5035 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
5036 */
5037 struct dmub_cmd_query_feature_caps_data {
5038 /**
5039 * DMUB feature capabilities.
5040 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
5041 */
5042 struct dmub_feature_caps feature_caps;
5043 };
5044
5045 /**
5046 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
5047 */
5048 struct dmub_rb_cmd_query_feature_caps {
5049 /**
5050 * Command header.
5051 */
5052 struct dmub_cmd_header header;
5053 /**
5054 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
5055 */
5056 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
5057 };
5058
5059 /**
5060 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
5061 */
5062 struct dmub_cmd_visual_confirm_color_data {
5063 /**
5064 * DMUB visual confirm color
5065 */
5066 struct dmub_visual_confirm_color visual_confirm_color;
5067 };
5068
5069 /**
5070 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
5071 */
5072 struct dmub_rb_cmd_get_visual_confirm_color {
5073 /**
5074 * Command header.
5075 */
5076 struct dmub_cmd_header header;
5077 /**
5078 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
5079 */
5080 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
5081 };
5082
5083 /**
5084 * enum dmub_cmd_panel_cntl_type - Panel control command.
5085 */
5086 enum dmub_cmd_panel_cntl_type {
5087 /**
5088 * Initializes embedded panel hardware blocks.
5089 */
5090 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
5091 /**
5092 * Queries backlight info for the embedded panel.
5093 */
5094 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
5095 /**
5096 * Sets the PWM Freq as per user's requirement.
5097 */
5098 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,
5099 };
5100
5101 /**
5102 * struct dmub_cmd_panel_cntl_data - Panel control data.
5103 */
5104 struct dmub_cmd_panel_cntl_data {
5105 uint32_t pwrseq_inst; /**< pwrseq instance */
5106 uint32_t current_backlight; /* in/out */
5107 uint32_t bl_pwm_cntl; /* in/out */
5108 uint32_t bl_pwm_period_cntl; /* in/out */
5109 uint32_t bl_pwm_ref_div1; /* in/out */
5110 uint8_t is_backlight_on : 1; /* in/out */
5111 uint8_t is_powered_on : 1; /* in/out */
5112 uint8_t padding[3];
5113 uint32_t bl_pwm_ref_div2; /* in/out */
5114 uint8_t reserved[4];
5115 };
5116
5117 /**
5118 * struct dmub_rb_cmd_panel_cntl - Panel control command.
5119 */
5120 struct dmub_rb_cmd_panel_cntl {
5121 struct dmub_cmd_header header; /**< header */
5122 struct dmub_cmd_panel_cntl_data data; /**< payload */
5123 };
5124
5125 struct dmub_optc_state {
5126 uint32_t v_total_max;
5127 uint32_t v_total_min;
5128 uint32_t tg_inst;
5129 };
5130
5131 struct dmub_rb_cmd_drr_update {
5132 struct dmub_cmd_header header;
5133 struct dmub_optc_state dmub_optc_state_req;
5134 };
5135
5136 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
5137 uint32_t pix_clk_100hz;
5138 uint8_t max_ramp_step;
5139 uint8_t pipes;
5140 uint8_t min_refresh_in_hz;
5141 uint8_t pipe_count;
5142 uint8_t pipe_index[4];
5143 };
5144
5145 struct dmub_cmd_fw_assisted_mclk_switch_config {
5146 uint8_t fams_enabled;
5147 uint8_t visual_confirm_enabled;
5148 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
5149 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
5150 };
5151
5152 struct dmub_rb_cmd_fw_assisted_mclk_switch {
5153 struct dmub_cmd_header header;
5154 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
5155 };
5156
5157 /**
5158 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
5159 */
5160 struct dmub_cmd_lvtma_control_data {
5161 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
5162 uint8_t bypass_panel_control_wait;
5163 uint8_t reserved_0[2]; /**< For future use */
5164 uint8_t pwrseq_inst; /**< LVTMA control instance */
5165 uint8_t reserved_1[3]; /**< For future use */
5166 };
5167
5168 /**
5169 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
5170 */
5171 struct dmub_rb_cmd_lvtma_control {
5172 /**
5173 * Command header.
5174 */
5175 struct dmub_cmd_header header;
5176 /**
5177 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
5178 */
5179 struct dmub_cmd_lvtma_control_data data;
5180 };
5181
5182 /**
5183 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
5184 */
5185 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
5186 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
5187 uint8_t is_usb; /**< is phy is usb */
5188 uint8_t is_dp_alt_disable; /**< is dp alt disable */
5189 uint8_t is_dp4; /**< is dp in 4 lane */
5190 };
5191
5192 /**
5193 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
5194 */
5195 struct dmub_rb_cmd_transmitter_query_dp_alt {
5196 struct dmub_cmd_header header; /**< header */
5197 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
5198 };
5199
5200 struct phy_test_mode {
5201 uint8_t mode;
5202 uint8_t pat0;
5203 uint8_t pad[2];
5204 };
5205
5206 /**
5207 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
5208 */
5209 struct dmub_rb_cmd_transmitter_set_phy_fsm_data {
5210 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
5211 uint8_t mode; /**< HDMI/DP/DP2 etc */
5212 uint8_t lane_num; /**< Number of lanes */
5213 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */
5214 struct phy_test_mode test_mode;
5215 enum dmub_phy_fsm_state state;
5216 uint32_t status;
5217 uint8_t pad;
5218 };
5219
5220 /**
5221 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
5222 */
5223 struct dmub_rb_cmd_transmitter_set_phy_fsm {
5224 struct dmub_cmd_header header; /**< header */
5225 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */
5226 };
5227
5228 /**
5229 * Maximum number of bytes a chunk sent to DMUB for parsing
5230 */
5231 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
5232
5233 /**
5234 * Represent a chunk of CEA blocks sent to DMUB for parsing
5235 */
5236 struct dmub_cmd_send_edid_cea {
5237 uint16_t offset; /**< offset into the CEA block */
5238 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
5239 uint16_t cea_total_length; /**< total length of the CEA block */
5240 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
5241 uint8_t pad[3]; /**< padding and for future expansion */
5242 };
5243
5244 /**
5245 * Result of VSDB parsing from CEA block
5246 */
5247 struct dmub_cmd_edid_cea_amd_vsdb {
5248 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
5249 uint8_t freesync_supported; /**< 1 if Freesync is supported */
5250 uint16_t amd_vsdb_version; /**< AMD VSDB version */
5251 uint16_t min_frame_rate; /**< Maximum frame rate */
5252 uint16_t max_frame_rate; /**< Minimum frame rate */
5253 };
5254
5255 /**
5256 * Result of sending a CEA chunk
5257 */
5258 struct dmub_cmd_edid_cea_ack {
5259 uint16_t offset; /**< offset of the chunk into the CEA block */
5260 uint8_t success; /**< 1 if this sending of chunk succeeded */
5261 uint8_t pad; /**< padding and for future expansion */
5262 };
5263
5264 /**
5265 * Specify whether the result is an ACK/NACK or the parsing has finished
5266 */
5267 enum dmub_cmd_edid_cea_reply_type {
5268 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
5269 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
5270 };
5271
5272 /**
5273 * Definition of a DMUB_CMD__EDID_CEA command.
5274 */
5275 struct dmub_rb_cmd_edid_cea {
5276 struct dmub_cmd_header header; /**< Command header */
5277 union dmub_cmd_edid_cea_data {
5278 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
5279 struct dmub_cmd_edid_cea_output { /**< output with results */
5280 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
5281 union {
5282 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
5283 struct dmub_cmd_edid_cea_ack ack;
5284 };
5285 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
5286 } data; /**< Command data */
5287
5288 };
5289
5290 /**
5291 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
5292 */
5293 struct dmub_cmd_cable_id_input {
5294 uint8_t phy_inst; /**< phy inst for cable id data */
5295 };
5296
5297 /**
5298 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
5299 */
5300 struct dmub_cmd_cable_id_output {
5301 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
5302 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
5303 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
5304 uint8_t RESERVED :2; /**< reserved means not defined */
5305 };
5306
5307 /**
5308 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
5309 */
5310 struct dmub_rb_cmd_get_usbc_cable_id {
5311 struct dmub_cmd_header header; /**< Command header */
5312 /**
5313 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
5314 */
5315 union dmub_cmd_cable_id_data {
5316 struct dmub_cmd_cable_id_input input; /**< Input */
5317 struct dmub_cmd_cable_id_output output; /**< Output */
5318 uint8_t output_raw; /**< Raw data output */
5319 } data;
5320 };
5321
5322 /**
5323 * Command type of a DMUB_CMD__SECURE_DISPLAY command
5324 */
5325 enum dmub_cmd_secure_display_type {
5326 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
5327 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
5328 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY,
5329 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE,
5330 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY
5331 };
5332
5333 #define MAX_ROI_NUM 2
5334
5335 struct dmub_cmd_roi_info {
5336 uint16_t x_start;
5337 uint16_t x_end;
5338 uint16_t y_start;
5339 uint16_t y_end;
5340 uint8_t otg_id;
5341 uint8_t phy_id;
5342 };
5343
5344 struct dmub_cmd_roi_window_ctl {
5345 uint16_t x_start;
5346 uint16_t x_end;
5347 uint16_t y_start;
5348 uint16_t y_end;
5349 bool enable;
5350 };
5351
5352 struct dmub_cmd_roi_ctl_info {
5353 uint8_t otg_id;
5354 uint8_t phy_id;
5355 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM];
5356 };
5357
5358 /**
5359 * Definition of a DMUB_CMD__SECURE_DISPLAY command
5360 */
5361 struct dmub_rb_cmd_secure_display {
5362 struct dmub_cmd_header header;
5363 /**
5364 * Data passed from driver to dmub firmware.
5365 */
5366 struct dmub_cmd_roi_info roi_info;
5367 struct dmub_cmd_roi_ctl_info mul_roi_ctl;
5368 };
5369
5370 /**
5371 * Command type of a DMUB_CMD__PSP command
5372 */
5373 enum dmub_cmd_psp_type {
5374 DMUB_CMD__PSP_ASSR_ENABLE = 0
5375 };
5376
5377 /**
5378 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command.
5379 */
5380 struct dmub_cmd_assr_enable_data {
5381 /**
5382 * ASSR enable or disable.
5383 */
5384 uint8_t enable;
5385 /**
5386 * PHY port type.
5387 * Indicates eDP / non-eDP port type
5388 */
5389 uint8_t phy_port_type;
5390 /**
5391 * PHY port ID.
5392 */
5393 uint8_t phy_port_id;
5394 /**
5395 * Link encoder index.
5396 */
5397 uint8_t link_enc_index;
5398 /**
5399 * HPO mode.
5400 */
5401 uint8_t hpo_mode;
5402
5403 /**
5404 * Reserved field.
5405 */
5406 uint8_t reserved[7];
5407 };
5408
5409 /**
5410 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
5411 */
5412 struct dmub_rb_cmd_assr_enable {
5413 /**
5414 * Command header.
5415 */
5416 struct dmub_cmd_header header;
5417
5418 /**
5419 * Assr data.
5420 */
5421 struct dmub_cmd_assr_enable_data assr_data;
5422
5423 /**
5424 * Reserved field.
5425 */
5426 uint32_t reserved[3];
5427 };
5428
5429 /**
5430 * union dmub_rb_cmd - DMUB inbox command.
5431 */
5432 union dmub_rb_cmd {
5433 /**
5434 * Elements shared with all commands.
5435 */
5436 struct dmub_rb_cmd_common cmd_common;
5437 /**
5438 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
5439 */
5440 struct dmub_rb_cmd_read_modify_write read_modify_write;
5441 /**
5442 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
5443 */
5444 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
5445 /**
5446 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
5447 */
5448 struct dmub_rb_cmd_burst_write burst_write;
5449 /**
5450 * Definition of a DMUB_CMD__REG_REG_WAIT command.
5451 */
5452 struct dmub_rb_cmd_reg_wait reg_wait;
5453 /**
5454 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
5455 */
5456 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
5457 /**
5458 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
5459 */
5460 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
5461 /**
5462 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
5463 */
5464 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
5465 /**
5466 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
5467 */
5468 struct dmub_rb_cmd_dpphy_init dpphy_init;
5469 /**
5470 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
5471 */
5472 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
5473 /**
5474 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
5475 */
5476 struct dmub_rb_cmd_domain_control domain_control;
5477 /**
5478 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
5479 */
5480 struct dmub_rb_cmd_psr_set_version psr_set_version;
5481 /**
5482 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
5483 */
5484 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
5485 /**
5486 * Definition of a DMUB_CMD__PSR_ENABLE command.
5487 */
5488 struct dmub_rb_cmd_psr_enable psr_enable;
5489 /**
5490 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
5491 */
5492 struct dmub_rb_cmd_psr_set_level psr_set_level;
5493 /**
5494 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
5495 */
5496 struct dmub_rb_cmd_psr_force_static psr_force_static;
5497 /**
5498 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
5499 */
5500 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
5501 /**
5502 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
5503 */
5504 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
5505 /**
5506 * Definition of a DMUB_CMD__HW_LOCK command.
5507 * Command is used by driver and FW.
5508 */
5509 struct dmub_rb_cmd_lock_hw lock_hw;
5510 /**
5511 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
5512 */
5513 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
5514 /**
5515 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
5516 */
5517 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
5518 /**
5519 * Definition of a DMUB_CMD__PLAT_54186_WA command.
5520 */
5521 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
5522 /**
5523 * Definition of a DMUB_CMD__MALL command.
5524 */
5525 struct dmub_rb_cmd_mall mall;
5526
5527 /**
5528 * Definition of a DMUB_CMD__CAB command.
5529 */
5530 struct dmub_rb_cmd_cab_for_ss cab;
5531
5532 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
5533
5534 /**
5535 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
5536 */
5537 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
5538
5539 /**
5540 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
5541 */
5542 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
5543
5544 /**
5545 * Definition of DMUB_CMD__PANEL_CNTL commands.
5546 */
5547 struct dmub_rb_cmd_panel_cntl panel_cntl;
5548
5549 /**
5550 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
5551 */
5552 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
5553
5554 /**
5555 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
5556 */
5557 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
5558
5559 /**
5560 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
5561 */
5562 struct dmub_rb_cmd_abm_set_level abm_set_level;
5563
5564 /**
5565 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5566 */
5567 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
5568
5569 /**
5570 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
5571 */
5572 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
5573
5574 /**
5575 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
5576 */
5577 struct dmub_rb_cmd_abm_init_config abm_init_config;
5578
5579 /**
5580 * Definition of a DMUB_CMD__ABM_PAUSE command.
5581 */
5582 struct dmub_rb_cmd_abm_pause abm_pause;
5583
5584 /**
5585 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
5586 */
5587 struct dmub_rb_cmd_abm_save_restore abm_save_restore;
5588
5589 /**
5590 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
5591 */
5592 struct dmub_rb_cmd_abm_query_caps abm_query_caps;
5593
5594 /**
5595 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
5596 */
5597 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve;
5598
5599 /**
5600 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
5601 */
5602 struct dmub_rb_cmd_abm_set_event abm_set_event;
5603
5604 /**
5605 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
5606 */
5607 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
5608
5609 /**
5610 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
5611 */
5612 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
5613
5614 /**
5615 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
5616 */
5617 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
5618
5619 /**
5620 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
5621 */
5622 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
5623 struct dmub_rb_cmd_drr_update drr_update;
5624 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
5625
5626 /**
5627 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
5628 */
5629 struct dmub_rb_cmd_lvtma_control lvtma_control;
5630 /**
5631 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
5632 */
5633 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
5634 /**
5635 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
5636 */
5637 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm;
5638 /**
5639 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
5640 */
5641 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
5642 /**
5643 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
5644 */
5645 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated)
5646 /**
5647 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
5648 */
5649 struct dmub_rb_cmd_set_config_request set_config_request;
5650 /**
5651 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
5652 */
5653 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
5654 /**
5655 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command.
5656 */
5657 struct dmub_rb_cmd_set_tps_notification set_tps_notification;
5658 /**
5659 * Definition of a DMUB_CMD__EDID_CEA command.
5660 */
5661 struct dmub_rb_cmd_edid_cea edid_cea;
5662 /**
5663 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
5664 */
5665 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
5666
5667 /**
5668 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
5669 */
5670 struct dmub_rb_cmd_query_hpd_state query_hpd;
5671 /**
5672 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
5673 */
5674 struct dmub_rb_cmd_secure_display secure_display;
5675
5676 /**
5677 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
5678 */
5679 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
5680 /**
5681 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
5682 */
5683 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
5684 /**
5685 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
5686 */
5687 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state;
5688 /*
5689 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
5690 */
5691 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
5692 /**
5693 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
5694 */
5695 struct dmub_rb_cmd_replay_enable replay_enable;
5696 /**
5697 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
5698 */
5699 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
5700 /**
5701 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
5702 */
5703 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
5704 /**
5705 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
5706 */
5707 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal;
5708
5709 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync;
5710 /**
5711 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
5712 */
5713 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer;
5714 /**
5715 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
5716 */
5717 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
5718 /**
5719 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
5720 */
5721 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;
5722 /**
5723 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
5724 */
5725 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd;
5726 /**
5727 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
5728 */
5729 struct dmub_rb_cmd_assr_enable assr_enable;
5730 struct dmub_rb_cmd_fams2 fams2_config;
5731
5732 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update;
5733
5734 struct dmub_rb_cmd_fams2_flip fams2_flip;
5735 };
5736
5737 /**
5738 * union dmub_rb_out_cmd - Outbox command
5739 */
5740 union dmub_rb_out_cmd {
5741 /**
5742 * Parameters common to every command.
5743 */
5744 struct dmub_rb_cmd_common cmd_common;
5745 /**
5746 * AUX reply command.
5747 */
5748 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
5749 /**
5750 * HPD notify command.
5751 */
5752 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
5753 /**
5754 * SET_CONFIG reply command.
5755 */
5756 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
5757 /**
5758 * DPIA notification command.
5759 */
5760 struct dmub_rb_cmd_dpia_notification dpia_notification;
5761 /**
5762 * HPD sense notification command.
5763 */
5764 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify;
5765 };
5766 #pragma pack(pop)
5767
5768
5769 //==============================================================================
5770 //</DMUB_CMD>===================================================================
5771 //==============================================================================
5772 //< DMUB_RB>====================================================================
5773 //==============================================================================
5774
5775 /**
5776 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
5777 */
5778 struct dmub_rb_init_params {
5779 void *ctx; /**< Caller provided context pointer */
5780 void *base_address; /**< CPU base address for ring's data */
5781 uint32_t capacity; /**< Ringbuffer capacity in bytes */
5782 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
5783 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
5784 };
5785
5786 /**
5787 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
5788 */
5789 struct dmub_rb {
5790 void *base_address; /**< CPU address for the ring's data */
5791 uint32_t rptr; /**< Read pointer for consumer in bytes */
5792 uint32_t wrpt; /**< Write pointer for producer in bytes */
5793 uint32_t capacity; /**< Ringbuffer capacity in bytes */
5794
5795 void *ctx; /**< Caller provided context pointer */
5796 void *dmub; /**< Pointer to the DMUB interface */
5797 };
5798
5799 /**
5800 * @brief Checks if the ringbuffer is empty.
5801 *
5802 * @param rb DMUB Ringbuffer
5803 * @return true if empty
5804 * @return false otherwise
5805 */
dmub_rb_empty(struct dmub_rb * rb)5806 static inline bool dmub_rb_empty(struct dmub_rb *rb)
5807 {
5808 return (rb->wrpt == rb->rptr);
5809 }
5810
5811 /**
5812 * @brief Checks if the ringbuffer is full
5813 *
5814 * @param rb DMUB Ringbuffer
5815 * @return true if full
5816 * @return false otherwise
5817 */
dmub_rb_full(struct dmub_rb * rb)5818 static inline bool dmub_rb_full(struct dmub_rb *rb)
5819 {
5820 uint32_t data_count;
5821
5822 if (rb->wrpt >= rb->rptr)
5823 data_count = rb->wrpt - rb->rptr;
5824 else
5825 data_count = rb->capacity - (rb->rptr - rb->wrpt);
5826
5827 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
5828 }
5829
5830 /**
5831 * @brief Pushes a command into the ringbuffer
5832 *
5833 * @param rb DMUB ringbuffer
5834 * @param cmd The command to push
5835 * @return true if the ringbuffer was not full
5836 * @return false otherwise
5837 */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)5838 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
5839 const union dmub_rb_cmd *cmd)
5840 {
5841 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
5842 const uint64_t *src = (const uint64_t *)cmd;
5843 uint8_t i;
5844
5845 if (dmub_rb_full(rb))
5846 return false;
5847
5848 // copying data
5849 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
5850 *dst++ = *src++;
5851
5852 rb->wrpt += DMUB_RB_CMD_SIZE;
5853
5854 if (rb->wrpt >= rb->capacity)
5855 rb->wrpt %= rb->capacity;
5856
5857 return true;
5858 }
5859
5860 /**
5861 * @brief Pushes a command into the DMUB outbox ringbuffer
5862 *
5863 * @param rb DMUB outbox ringbuffer
5864 * @param cmd Outbox command
5865 * @return true if not full
5866 * @return false otherwise
5867 */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)5868 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
5869 const union dmub_rb_out_cmd *cmd)
5870 {
5871 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
5872 const uint8_t *src = (const uint8_t *)cmd;
5873
5874 if (dmub_rb_full(rb))
5875 return false;
5876
5877 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
5878
5879 rb->wrpt += DMUB_RB_CMD_SIZE;
5880
5881 if (rb->wrpt >= rb->capacity)
5882 rb->wrpt %= rb->capacity;
5883
5884 return true;
5885 }
5886
5887 /**
5888 * @brief Returns the next unprocessed command in the ringbuffer.
5889 *
5890 * @param rb DMUB ringbuffer
5891 * @param cmd The command to return
5892 * @return true if not empty
5893 * @return false otherwise
5894 */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)5895 static inline bool dmub_rb_front(struct dmub_rb *rb,
5896 union dmub_rb_cmd **cmd)
5897 {
5898 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
5899
5900 if (dmub_rb_empty(rb))
5901 return false;
5902
5903 *cmd = (union dmub_rb_cmd *)rb_cmd;
5904
5905 return true;
5906 }
5907
5908 /**
5909 * @brief Determines the next ringbuffer offset.
5910 *
5911 * @param rb DMUB inbox ringbuffer
5912 * @param num_cmds Number of commands
5913 * @param next_rptr The next offset in the ringbuffer
5914 */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)5915 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
5916 uint32_t num_cmds,
5917 uint32_t *next_rptr)
5918 {
5919 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
5920
5921 if (*next_rptr >= rb->capacity)
5922 *next_rptr %= rb->capacity;
5923 }
5924
5925 /**
5926 * @brief Returns a pointer to a command in the inbox.
5927 *
5928 * @param rb DMUB inbox ringbuffer
5929 * @param cmd The inbox command to return
5930 * @param rptr The ringbuffer offset
5931 * @return true if not empty
5932 * @return false otherwise
5933 */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)5934 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
5935 union dmub_rb_cmd **cmd,
5936 uint32_t rptr)
5937 {
5938 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
5939
5940 if (dmub_rb_empty(rb))
5941 return false;
5942
5943 *cmd = (union dmub_rb_cmd *)rb_cmd;
5944
5945 return true;
5946 }
5947
5948 /**
5949 * @brief Returns the next unprocessed command in the outbox.
5950 *
5951 * @param rb DMUB outbox ringbuffer
5952 * @param cmd The outbox command to return
5953 * @return true if not empty
5954 * @return false otherwise
5955 */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)5956 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
5957 union dmub_rb_out_cmd *cmd)
5958 {
5959 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
5960 uint64_t *dst = (uint64_t *)cmd;
5961 uint8_t i;
5962
5963 if (dmub_rb_empty(rb))
5964 return false;
5965
5966 // copying data
5967 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
5968 *dst++ = *src++;
5969
5970 return true;
5971 }
5972
5973 /**
5974 * @brief Removes the front entry in the ringbuffer.
5975 *
5976 * @param rb DMUB ringbuffer
5977 * @return true if the command was removed
5978 * @return false if there were no commands
5979 */
dmub_rb_pop_front(struct dmub_rb * rb)5980 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
5981 {
5982 if (dmub_rb_empty(rb))
5983 return false;
5984
5985 rb->rptr += DMUB_RB_CMD_SIZE;
5986
5987 if (rb->rptr >= rb->capacity)
5988 rb->rptr %= rb->capacity;
5989
5990 return true;
5991 }
5992
5993 /**
5994 * @brief Flushes commands in the ringbuffer to framebuffer memory.
5995 *
5996 * Avoids a race condition where DMCUB accesses memory while
5997 * there are still writes in flight to framebuffer.
5998 *
5999 * @param rb DMUB ringbuffer
6000 */
dmub_rb_flush_pending(const struct dmub_rb * rb)6001 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
6002 {
6003 uint32_t rptr = rb->rptr;
6004 uint32_t wptr = rb->wrpt;
6005
6006 while (rptr != wptr) {
6007 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
6008 uint8_t i;
6009
6010 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
6011 (void)READ_ONCE(*data++);
6012
6013 rptr += DMUB_RB_CMD_SIZE;
6014 if (rptr >= rb->capacity)
6015 rptr %= rb->capacity;
6016 }
6017 }
6018
6019 /**
6020 * @brief Initializes a DMCUB ringbuffer
6021 *
6022 * @param rb DMUB ringbuffer
6023 * @param init_params initial configuration for the ringbuffer
6024 */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)6025 static inline void dmub_rb_init(struct dmub_rb *rb,
6026 struct dmub_rb_init_params *init_params)
6027 {
6028 rb->base_address = init_params->base_address;
6029 rb->capacity = init_params->capacity;
6030 rb->rptr = init_params->read_ptr;
6031 rb->wrpt = init_params->write_ptr;
6032 }
6033
6034 /**
6035 * @brief Copies output data from in/out commands into the given command.
6036 *
6037 * @param rb DMUB ringbuffer
6038 * @param cmd Command to copy data into
6039 */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)6040 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
6041 union dmub_rb_cmd *cmd)
6042 {
6043 // Copy rb entry back into command
6044 uint8_t *rd_ptr = (rb->rptr == 0) ?
6045 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
6046 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
6047
6048 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
6049 }
6050
6051 //==============================================================================
6052 //</DMUB_RB>====================================================================
6053 //==============================================================================
6054 #endif /* _DMUB_CMD_H_ */
6055