1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Rockchip SoCs.
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 * http://www.rock-chips.com
7 *
8 * Author: Simon Xue <xxm@rock-chips.com>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24
25 #include "../../pci.h"
26 #include "pcie-designware.h"
27
28 /*
29 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write
30 * mask for the lower 16 bits.
31 */
32 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
33 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
34 #define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
35
36 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
37
38 /* General Control Register */
39 #define PCIE_CLIENT_GENERAL_CON 0x0
40 #define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)
41 #define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)
42 #define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)
43 #define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)
44
45 /* Interrupt Status Register Related to Legacy Interrupt */
46 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
47
48 /* Interrupt Status Register Related to Miscellaneous Operation */
49 #define PCIE_CLIENT_INTR_STATUS_MISC 0x10
50 #define PCIE_RDLH_LINK_UP_CHGED BIT(1)
51 #define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
52
53 /* Interrupt Mask Register Related to Legacy Interrupt */
54 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
55
56 /* Interrupt Mask Register Related to Miscellaneous Operation */
57 #define PCIE_CLIENT_INTR_MASK_MISC 0x24
58
59 /* Hot Reset Control Register */
60 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
61 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
62
63 /* LTSSM Status Register */
64 #define PCIE_CLIENT_LTSSM_STATUS 0x300
65 #define PCIE_LINKUP 0x3
66 #define PCIE_LINKUP_MASK GENMASK(17, 16)
67 #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
68
69 struct rockchip_pcie {
70 struct dw_pcie pci;
71 void __iomem *apb_base;
72 struct phy *phy;
73 struct clk_bulk_data *clks;
74 unsigned int clk_cnt;
75 struct reset_control *rst;
76 struct gpio_desc *rst_gpio;
77 struct regulator *vpcie3v3;
78 struct irq_domain *irq_domain;
79 const struct rockchip_pcie_of_data *data;
80 };
81
82 struct rockchip_pcie_of_data {
83 enum dw_pcie_device_mode mode;
84 const struct pci_epc_features *epc_features;
85 };
86
rockchip_pcie_readl_apb(struct rockchip_pcie * rockchip,u32 reg)87 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)
88 {
89 return readl_relaxed(rockchip->apb_base + reg);
90 }
91
rockchip_pcie_writel_apb(struct rockchip_pcie * rockchip,u32 val,u32 reg)92 static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val,
93 u32 reg)
94 {
95 writel_relaxed(val, rockchip->apb_base + reg);
96 }
97
rockchip_pcie_intx_handler(struct irq_desc * desc)98 static void rockchip_pcie_intx_handler(struct irq_desc *desc)
99 {
100 struct irq_chip *chip = irq_desc_get_chip(desc);
101 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
102 unsigned long reg, hwirq;
103
104 chained_irq_enter(chip, desc);
105
106 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
107
108 for_each_set_bit(hwirq, ®, 4)
109 generic_handle_domain_irq(rockchip->irq_domain, hwirq);
110
111 chained_irq_exit(chip, desc);
112 }
113
rockchip_intx_mask(struct irq_data * data)114 static void rockchip_intx_mask(struct irq_data *data)
115 {
116 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
117 HIWORD_UPDATE_BIT(BIT(data->hwirq)),
118 PCIE_CLIENT_INTR_MASK_LEGACY);
119 };
120
rockchip_intx_unmask(struct irq_data * data)121 static void rockchip_intx_unmask(struct irq_data *data)
122 {
123 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
124 HIWORD_DISABLE_BIT(BIT(data->hwirq)),
125 PCIE_CLIENT_INTR_MASK_LEGACY);
126 };
127
128 static struct irq_chip rockchip_intx_irq_chip = {
129 .name = "INTx",
130 .irq_mask = rockchip_intx_mask,
131 .irq_unmask = rockchip_intx_unmask,
132 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
133 };
134
rockchip_pcie_intx_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)135 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
136 irq_hw_number_t hwirq)
137 {
138 irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
139 irq_set_chip_data(irq, domain->host_data);
140
141 return 0;
142 }
143
144 static const struct irq_domain_ops intx_domain_ops = {
145 .map = rockchip_pcie_intx_map,
146 };
147
rockchip_pcie_init_irq_domain(struct rockchip_pcie * rockchip)148 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
149 {
150 struct device *dev = rockchip->pci.dev;
151 struct device_node *intc;
152
153 intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
154 if (!intc) {
155 dev_err(dev, "missing child interrupt-controller node\n");
156 return -EINVAL;
157 }
158
159 rockchip->irq_domain = irq_domain_create_linear(of_fwnode_handle(intc), PCI_NUM_INTX,
160 &intx_domain_ops, rockchip);
161 of_node_put(intc);
162 if (!rockchip->irq_domain) {
163 dev_err(dev, "failed to get a INTx IRQ domain\n");
164 return -EINVAL;
165 }
166
167 return 0;
168 }
169
rockchip_pcie_get_ltssm(struct rockchip_pcie * rockchip)170 static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)
171 {
172 return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);
173 }
174
rockchip_pcie_enable_ltssm(struct rockchip_pcie * rockchip)175 static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
176 {
177 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
178 PCIE_CLIENT_GENERAL_CON);
179 }
180
rockchip_pcie_disable_ltssm(struct rockchip_pcie * rockchip)181 static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
182 {
183 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,
184 PCIE_CLIENT_GENERAL_CON);
185 }
186
rockchip_pcie_link_up(struct dw_pcie * pci)187 static bool rockchip_pcie_link_up(struct dw_pcie *pci)
188 {
189 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
190 u32 val = rockchip_pcie_get_ltssm(rockchip);
191
192 return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP;
193 }
194
rockchip_pcie_enable_l0s(struct dw_pcie * pci)195 static void rockchip_pcie_enable_l0s(struct dw_pcie *pci)
196 {
197 u32 cap, lnkcap;
198
199 /* Enable L0S capability for all SoCs */
200 cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
201 if (cap) {
202 lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
203 lnkcap |= PCI_EXP_LNKCAP_ASPM_L0S;
204 dw_pcie_dbi_ro_wr_en(pci);
205 dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
206 dw_pcie_dbi_ro_wr_dis(pci);
207 }
208 }
209
rockchip_pcie_start_link(struct dw_pcie * pci)210 static int rockchip_pcie_start_link(struct dw_pcie *pci)
211 {
212 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
213
214 /* Reset device */
215 gpiod_set_value_cansleep(rockchip->rst_gpio, 0);
216
217 rockchip_pcie_enable_ltssm(rockchip);
218
219 /*
220 * PCIe requires the refclk to be stable for 100µs prior to releasing
221 * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
222 * Express Card Electromechanical Specification, 1.1. However, we don't
223 * know if the refclk is coming from RC's PHY or external OSC. If it's
224 * from RC, so enabling LTSSM is the just right place to release #PERST.
225 * We need more extra time as before, rather than setting just
226 * 100us as we don't know how long should the device need to reset.
227 */
228 msleep(PCIE_T_PVPERL_MS);
229 gpiod_set_value_cansleep(rockchip->rst_gpio, 1);
230
231 return 0;
232 }
233
rockchip_pcie_stop_link(struct dw_pcie * pci)234 static void rockchip_pcie_stop_link(struct dw_pcie *pci)
235 {
236 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
237
238 rockchip_pcie_disable_ltssm(rockchip);
239 }
240
rockchip_pcie_host_init(struct dw_pcie_rp * pp)241 static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
242 {
243 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
244 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
245 struct device *dev = rockchip->pci.dev;
246 int irq, ret;
247
248 irq = of_irq_get_byname(dev->of_node, "legacy");
249 if (irq < 0)
250 return irq;
251
252 ret = rockchip_pcie_init_irq_domain(rockchip);
253 if (ret < 0)
254 dev_err(dev, "failed to init irq domain\n");
255
256 irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,
257 rockchip);
258
259 rockchip_pcie_enable_l0s(pci);
260
261 return 0;
262 }
263
264 static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
265 .init = rockchip_pcie_host_init,
266 };
267
268 /*
269 * ATS does not work on RK3588 when running in EP mode.
270 *
271 * After the host has enabled ATS on the EP side, it will send an IOTLB
272 * invalidation request to the EP side. However, the RK3588 will never send
273 * a completion back and eventually the host will print an IOTLB_INV_TIMEOUT
274 * error, and the EP will not be operational. If we hide the ATS capability,
275 * things work as expected.
276 */
rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep * ep)277 static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep)
278 {
279 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
280 struct device *dev = pci->dev;
281
282 /* Only hide the ATS capability for RK3588 running in EP mode. */
283 if (!of_device_is_compatible(dev->of_node, "rockchip,rk3588-pcie-ep"))
284 return;
285
286 if (dw_pcie_ep_hide_ext_capability(pci, PCI_EXT_CAP_ID_SECPCI,
287 PCI_EXT_CAP_ID_ATS))
288 dev_err(dev, "failed to hide ATS capability\n");
289 }
290
rockchip_pcie_ep_init(struct dw_pcie_ep * ep)291 static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
292 {
293 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
294 enum pci_barno bar;
295
296 rockchip_pcie_enable_l0s(pci);
297 rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
298
299 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
300 dw_pcie_ep_reset_bar(pci, bar);
301 };
302
rockchip_pcie_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)303 static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
304 unsigned int type, u16 interrupt_num)
305 {
306 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
307
308 switch (type) {
309 case PCI_IRQ_INTX:
310 return dw_pcie_ep_raise_intx_irq(ep, func_no);
311 case PCI_IRQ_MSI:
312 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
313 case PCI_IRQ_MSIX:
314 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
315 default:
316 dev_err(pci->dev, "UNKNOWN IRQ type\n");
317 }
318
319 return 0;
320 }
321
322 static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
323 .linkup_notifier = true,
324 .msi_capable = true,
325 .msix_capable = true,
326 .intx_capable = false,
327 .align = SZ_64K,
328 .bar[BAR_0] = { .type = BAR_RESIZABLE, },
329 .bar[BAR_1] = { .type = BAR_RESIZABLE, },
330 .bar[BAR_2] = { .type = BAR_RESIZABLE, },
331 .bar[BAR_3] = { .type = BAR_RESIZABLE, },
332 .bar[BAR_4] = { .type = BAR_RESIZABLE, },
333 .bar[BAR_5] = { .type = BAR_RESIZABLE, },
334 };
335
336 /*
337 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of
338 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
339 * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by
340 * default.) If the host could write to BAR4, the iATU settings (for all other
341 * BARs) would be overwritten, resulting in (all other BARs) no longer working.
342 */
343 static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
344 .linkup_notifier = true,
345 .msi_capable = true,
346 .msix_capable = true,
347 .intx_capable = false,
348 .align = SZ_64K,
349 .bar[BAR_0] = { .type = BAR_RESIZABLE, },
350 .bar[BAR_1] = { .type = BAR_RESIZABLE, },
351 .bar[BAR_2] = { .type = BAR_RESIZABLE, },
352 .bar[BAR_3] = { .type = BAR_RESIZABLE, },
353 .bar[BAR_4] = { .type = BAR_RESERVED, },
354 .bar[BAR_5] = { .type = BAR_RESIZABLE, },
355 };
356
357 static const struct pci_epc_features *
rockchip_pcie_get_features(struct dw_pcie_ep * ep)358 rockchip_pcie_get_features(struct dw_pcie_ep *ep)
359 {
360 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
361 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
362
363 return rockchip->data->epc_features;
364 }
365
366 static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {
367 .init = rockchip_pcie_ep_init,
368 .raise_irq = rockchip_pcie_raise_irq,
369 .get_features = rockchip_pcie_get_features,
370 };
371
rockchip_pcie_clk_init(struct rockchip_pcie * rockchip)372 static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)
373 {
374 struct device *dev = rockchip->pci.dev;
375 int ret;
376
377 ret = devm_clk_bulk_get_all(dev, &rockchip->clks);
378 if (ret < 0)
379 return dev_err_probe(dev, ret, "failed to get clocks\n");
380
381 rockchip->clk_cnt = ret;
382
383 ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);
384 if (ret)
385 return dev_err_probe(dev, ret, "failed to enable clocks\n");
386
387 return 0;
388 }
389
rockchip_pcie_resource_get(struct platform_device * pdev,struct rockchip_pcie * rockchip)390 static int rockchip_pcie_resource_get(struct platform_device *pdev,
391 struct rockchip_pcie *rockchip)
392 {
393 rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
394 if (IS_ERR(rockchip->apb_base))
395 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base),
396 "failed to map apb registers\n");
397
398 rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
399 GPIOD_OUT_LOW);
400 if (IS_ERR(rockchip->rst_gpio))
401 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst_gpio),
402 "failed to get reset gpio\n");
403
404 rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
405 if (IS_ERR(rockchip->rst))
406 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
407 "failed to get reset lines\n");
408
409 return 0;
410 }
411
rockchip_pcie_phy_init(struct rockchip_pcie * rockchip)412 static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)
413 {
414 struct device *dev = rockchip->pci.dev;
415 int ret;
416
417 rockchip->phy = devm_phy_get(dev, "pcie-phy");
418 if (IS_ERR(rockchip->phy))
419 return dev_err_probe(dev, PTR_ERR(rockchip->phy),
420 "missing PHY\n");
421
422 ret = phy_init(rockchip->phy);
423 if (ret < 0)
424 return ret;
425
426 ret = phy_power_on(rockchip->phy);
427 if (ret)
428 phy_exit(rockchip->phy);
429
430 return ret;
431 }
432
rockchip_pcie_phy_deinit(struct rockchip_pcie * rockchip)433 static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
434 {
435 phy_power_off(rockchip->phy);
436 phy_exit(rockchip->phy);
437 }
438
439 static const struct dw_pcie_ops dw_pcie_ops = {
440 .link_up = rockchip_pcie_link_up,
441 .start_link = rockchip_pcie_start_link,
442 .stop_link = rockchip_pcie_stop_link,
443 };
444
rockchip_pcie_rc_sys_irq_thread(int irq,void * arg)445 static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg)
446 {
447 struct rockchip_pcie *rockchip = arg;
448 struct dw_pcie *pci = &rockchip->pci;
449 struct dw_pcie_rp *pp = &pci->pp;
450 struct device *dev = pci->dev;
451 u32 reg;
452
453 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
454 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
455
456 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
457 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
458
459 if (reg & PCIE_RDLH_LINK_UP_CHGED) {
460 if (rockchip_pcie_link_up(pci)) {
461 dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
462 /* Rescan the bus to enumerate endpoint devices */
463 pci_lock_rescan_remove();
464 pci_rescan_bus(pp->bridge->bus);
465 pci_unlock_rescan_remove();
466 }
467 }
468
469 return IRQ_HANDLED;
470 }
471
rockchip_pcie_ep_sys_irq_thread(int irq,void * arg)472 static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
473 {
474 struct rockchip_pcie *rockchip = arg;
475 struct dw_pcie *pci = &rockchip->pci;
476 struct device *dev = pci->dev;
477 u32 reg;
478
479 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);
480 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
481
482 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
483 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
484
485 if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
486 dev_dbg(dev, "hot reset or link-down reset\n");
487 dw_pcie_ep_linkdown(&pci->ep);
488 }
489
490 if (reg & PCIE_RDLH_LINK_UP_CHGED) {
491 if (rockchip_pcie_link_up(pci)) {
492 dev_dbg(dev, "link up\n");
493 dw_pcie_ep_linkup(&pci->ep);
494 }
495 }
496
497 return IRQ_HANDLED;
498 }
499
rockchip_pcie_configure_rc(struct platform_device * pdev,struct rockchip_pcie * rockchip)500 static int rockchip_pcie_configure_rc(struct platform_device *pdev,
501 struct rockchip_pcie *rockchip)
502 {
503 struct device *dev = &pdev->dev;
504 struct dw_pcie_rp *pp;
505 int irq, ret;
506 u32 val;
507
508 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST))
509 return -ENODEV;
510
511 irq = platform_get_irq_byname(pdev, "sys");
512 if (irq < 0)
513 return irq;
514
515 ret = devm_request_threaded_irq(dev, irq, NULL,
516 rockchip_pcie_rc_sys_irq_thread,
517 IRQF_ONESHOT, "pcie-sys-rc", rockchip);
518 if (ret) {
519 dev_err(dev, "failed to request PCIe sys IRQ\n");
520 return ret;
521 }
522
523 /* LTSSM enable control mode */
524 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
525 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
526
527 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,
528 PCIE_CLIENT_GENERAL_CON);
529
530 pp = &rockchip->pci.pp;
531 pp->ops = &rockchip_pcie_host_ops;
532 pp->use_linkup_irq = true;
533
534 ret = dw_pcie_host_init(pp);
535 if (ret) {
536 dev_err(dev, "failed to initialize host\n");
537 return ret;
538 }
539
540 /* unmask DLL up/down indicator */
541 val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED, 0);
542 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
543
544 return ret;
545 }
546
rockchip_pcie_configure_ep(struct platform_device * pdev,struct rockchip_pcie * rockchip)547 static int rockchip_pcie_configure_ep(struct platform_device *pdev,
548 struct rockchip_pcie *rockchip)
549 {
550 struct device *dev = &pdev->dev;
551 int irq, ret;
552 u32 val;
553
554 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))
555 return -ENODEV;
556
557 irq = platform_get_irq_byname(pdev, "sys");
558 if (irq < 0)
559 return irq;
560
561 ret = devm_request_threaded_irq(dev, irq, NULL,
562 rockchip_pcie_ep_sys_irq_thread,
563 IRQF_ONESHOT, "pcie-sys-ep", rockchip);
564 if (ret) {
565 dev_err(dev, "failed to request PCIe sys IRQ\n");
566 return ret;
567 }
568
569 /* LTSSM enable control mode */
570 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
571 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
572
573 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,
574 PCIE_CLIENT_GENERAL_CON);
575
576 rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;
577 rockchip->pci.ep.page_size = SZ_64K;
578
579 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
580
581 ret = dw_pcie_ep_init(&rockchip->pci.ep);
582 if (ret) {
583 dev_err(dev, "failed to initialize endpoint\n");
584 return ret;
585 }
586
587 ret = dw_pcie_ep_init_registers(&rockchip->pci.ep);
588 if (ret) {
589 dev_err(dev, "failed to initialize DWC endpoint registers\n");
590 dw_pcie_ep_deinit(&rockchip->pci.ep);
591 return ret;
592 }
593
594 pci_epc_init_notify(rockchip->pci.ep.epc);
595
596 /* unmask DLL up/down indicator and hot reset/link-down reset */
597 val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED | PCIE_LINK_REQ_RST_NOT_INT, 0);
598 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
599
600 return ret;
601 }
602
rockchip_pcie_probe(struct platform_device * pdev)603 static int rockchip_pcie_probe(struct platform_device *pdev)
604 {
605 struct device *dev = &pdev->dev;
606 struct rockchip_pcie *rockchip;
607 const struct rockchip_pcie_of_data *data;
608 int ret;
609
610 data = of_device_get_match_data(dev);
611 if (!data)
612 return -EINVAL;
613
614 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
615 if (!rockchip)
616 return -ENOMEM;
617
618 platform_set_drvdata(pdev, rockchip);
619
620 rockchip->pci.dev = dev;
621 rockchip->pci.ops = &dw_pcie_ops;
622 rockchip->data = data;
623
624 /* Default N_FTS value (210) is broken, override it to 255 */
625 rockchip->pci.n_fts[0] = 255; /* Gen1 */
626 rockchip->pci.n_fts[1] = 255; /* Gen2+ */
627
628 ret = rockchip_pcie_resource_get(pdev, rockchip);
629 if (ret)
630 return ret;
631
632 ret = reset_control_assert(rockchip->rst);
633 if (ret)
634 return ret;
635
636 /* DON'T MOVE ME: must be enable before PHY init */
637 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
638 if (IS_ERR(rockchip->vpcie3v3)) {
639 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)
640 return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3),
641 "failed to get vpcie3v3 regulator\n");
642 rockchip->vpcie3v3 = NULL;
643 } else {
644 ret = regulator_enable(rockchip->vpcie3v3);
645 if (ret)
646 return dev_err_probe(dev, ret,
647 "failed to enable vpcie3v3 regulator\n");
648 }
649
650 ret = rockchip_pcie_phy_init(rockchip);
651 if (ret)
652 goto disable_regulator;
653
654 ret = reset_control_deassert(rockchip->rst);
655 if (ret)
656 goto deinit_phy;
657
658 ret = rockchip_pcie_clk_init(rockchip);
659 if (ret)
660 goto deinit_phy;
661
662 switch (data->mode) {
663 case DW_PCIE_RC_TYPE:
664 ret = rockchip_pcie_configure_rc(pdev, rockchip);
665 if (ret)
666 goto deinit_clk;
667 break;
668 case DW_PCIE_EP_TYPE:
669 ret = rockchip_pcie_configure_ep(pdev, rockchip);
670 if (ret)
671 goto deinit_clk;
672 break;
673 default:
674 dev_err(dev, "INVALID device type %d\n", data->mode);
675 ret = -EINVAL;
676 goto deinit_clk;
677 }
678
679 return 0;
680
681 deinit_clk:
682 clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
683 deinit_phy:
684 rockchip_pcie_phy_deinit(rockchip);
685 disable_regulator:
686 if (rockchip->vpcie3v3)
687 regulator_disable(rockchip->vpcie3v3);
688
689 return ret;
690 }
691
692 static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {
693 .mode = DW_PCIE_RC_TYPE,
694 };
695
696 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = {
697 .mode = DW_PCIE_EP_TYPE,
698 .epc_features = &rockchip_pcie_epc_features_rk3568,
699 };
700
701 static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = {
702 .mode = DW_PCIE_EP_TYPE,
703 .epc_features = &rockchip_pcie_epc_features_rk3588,
704 };
705
706 static const struct of_device_id rockchip_pcie_of_match[] = {
707 {
708 .compatible = "rockchip,rk3568-pcie",
709 .data = &rockchip_pcie_rc_of_data_rk3568,
710 },
711 {
712 .compatible = "rockchip,rk3568-pcie-ep",
713 .data = &rockchip_pcie_ep_of_data_rk3568,
714 },
715 {
716 .compatible = "rockchip,rk3588-pcie-ep",
717 .data = &rockchip_pcie_ep_of_data_rk3588,
718 },
719 {},
720 };
721
722 static struct platform_driver rockchip_pcie_driver = {
723 .driver = {
724 .name = "rockchip-dw-pcie",
725 .of_match_table = rockchip_pcie_of_match,
726 .suppress_bind_attrs = true,
727 },
728 .probe = rockchip_pcie_probe,
729 };
730 builtin_platform_driver(rockchip_pcie_driver);
731