1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip SoC DP (Display Port) interface driver.
4 *
5 * Copyright (C) Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
9 */
10
11 #include <linux/component.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/clk.h>
20
21 #include <video/of_videomode.h>
22 #include <video/videomode.h>
23
24 #include <drm/display/drm_dp_aux_bus.h>
25 #include <drm/display/drm_dp_helper.h>
26 #include <drm/drm_atomic.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/bridge/analogix_dp.h>
29 #include <drm/drm_of.h>
30 #include <drm/drm_panel.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
33 #include <drm/drm_simple_kms_helper.h>
34
35 #include "rockchip_drm_drv.h"
36
37 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
38
39 #define GRF_REG_FIELD(_reg, _lsb, _msb) { \
40 .reg = _reg, \
41 .lsb = _lsb, \
42 .msb = _msb, \
43 .valid = true, \
44 }
45
46 struct rockchip_grf_reg_field {
47 u32 reg;
48 u32 lsb;
49 u32 msb;
50 bool valid;
51 };
52
53 /**
54 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
55 * @lcdc_sel: grf register field of lcdc_sel
56 * @edp_mode: grf register field of edp_mode
57 * @chip_type: specific chip type
58 * @reg: register base address
59 */
60 struct rockchip_dp_chip_data {
61 const struct rockchip_grf_reg_field lcdc_sel;
62 const struct rockchip_grf_reg_field edp_mode;
63 u32 chip_type;
64 u32 reg;
65 };
66
67 struct rockchip_dp_device {
68 struct drm_device *drm_dev;
69 struct device *dev;
70 struct rockchip_encoder encoder;
71 struct drm_display_mode mode;
72
73 struct clk *pclk;
74 struct clk *grfclk;
75 struct regmap *grf;
76 struct reset_control *rst;
77 struct reset_control *apbrst;
78
79 const struct rockchip_dp_chip_data *data;
80
81 struct analogix_dp_device *adp;
82 struct analogix_dp_plat_data plat_data;
83 };
84
encoder_to_dp(struct drm_encoder * encoder)85 static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
86 {
87 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
88
89 return container_of(rkencoder, struct rockchip_dp_device, encoder);
90 }
91
pdata_encoder_to_dp(struct analogix_dp_plat_data * plat_data)92 static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
93 {
94 return container_of(plat_data, struct rockchip_dp_device, plat_data);
95 }
96
rockchip_grf_write(struct regmap * grf,u32 reg,u32 mask,u32 val)97 static int rockchip_grf_write(struct regmap *grf, u32 reg, u32 mask, u32 val)
98 {
99 return regmap_write(grf, reg, (mask << 16) | (val & mask));
100 }
101
rockchip_grf_field_write(struct regmap * grf,const struct rockchip_grf_reg_field * field,u32 val)102 static int rockchip_grf_field_write(struct regmap *grf,
103 const struct rockchip_grf_reg_field *field,
104 u32 val)
105 {
106 u32 mask;
107
108 if (!field->valid)
109 return 0;
110
111 mask = GENMASK(field->msb, field->lsb);
112 val <<= field->lsb;
113
114 return rockchip_grf_write(grf, field->reg, mask, val);
115 }
116
rockchip_dp_pre_init(struct rockchip_dp_device * dp)117 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
118 {
119 reset_control_assert(dp->rst);
120 usleep_range(10, 20);
121 reset_control_deassert(dp->rst);
122
123 reset_control_assert(dp->apbrst);
124 usleep_range(10, 20);
125 reset_control_deassert(dp->apbrst);
126
127 return 0;
128 }
129
rockchip_dp_poweron(struct analogix_dp_plat_data * plat_data)130 static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
131 {
132 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
133 int ret;
134
135 ret = clk_prepare_enable(dp->pclk);
136 if (ret < 0) {
137 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
138 return ret;
139 }
140
141 ret = rockchip_dp_pre_init(dp);
142 if (ret < 0) {
143 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
144 clk_disable_unprepare(dp->pclk);
145 return ret;
146 }
147
148 ret = rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 1);
149 if (ret != 0)
150 DRM_DEV_ERROR(dp->dev, "failed to set edp mode %d\n", ret);
151
152 return ret;
153 }
154
rockchip_dp_powerdown(struct analogix_dp_plat_data * plat_data)155 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
156 {
157 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
158 int ret;
159
160 ret = rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 0);
161 if (ret != 0)
162 DRM_DEV_ERROR(dp->dev, "failed to set edp mode %d\n", ret);
163
164 clk_disable_unprepare(dp->pclk);
165
166 return 0;
167 }
168
rockchip_dp_get_modes(struct analogix_dp_plat_data * plat_data,struct drm_connector * connector)169 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
170 struct drm_connector *connector)
171 {
172 struct drm_display_info *di = &connector->display_info;
173 /* VOP couldn't output YUV video format for eDP rightly */
174 u32 mask = DRM_COLOR_FORMAT_YCBCR444 | DRM_COLOR_FORMAT_YCBCR422;
175
176 if ((di->color_formats & mask)) {
177 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
178 di->color_formats &= ~mask;
179 di->color_formats |= DRM_COLOR_FORMAT_RGB444;
180 di->bpc = 8;
181 }
182
183 return 0;
184 }
185
186 static bool
rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)187 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
188 const struct drm_display_mode *mode,
189 struct drm_display_mode *adjusted_mode)
190 {
191 /* do nothing */
192 return true;
193 }
194
rockchip_dp_drm_encoder_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted)195 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
196 struct drm_display_mode *mode,
197 struct drm_display_mode *adjusted)
198 {
199 /* do nothing */
200 }
201
202 static
rockchip_dp_drm_get_new_crtc(struct drm_encoder * encoder,struct drm_atomic_state * state)203 struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
204 struct drm_atomic_state *state)
205 {
206 struct drm_connector *connector;
207 struct drm_connector_state *conn_state;
208
209 connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
210 if (!connector)
211 return NULL;
212
213 conn_state = drm_atomic_get_new_connector_state(state, connector);
214 if (!conn_state)
215 return NULL;
216
217 return conn_state->crtc;
218 }
219
rockchip_dp_drm_encoder_enable(struct drm_encoder * encoder,struct drm_atomic_state * state)220 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
221 struct drm_atomic_state *state)
222 {
223 struct rockchip_dp_device *dp = encoder_to_dp(encoder);
224 struct drm_crtc *crtc;
225 struct drm_crtc_state *old_crtc_state;
226 struct of_endpoint endpoint;
227 struct device_node *remote_port, *remote_port_parent;
228 char name[32];
229 u32 port_id;
230 int ret;
231
232 crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
233 if (!crtc)
234 return;
235
236 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
237 /* Coming back from self refresh, nothing to do */
238 if (old_crtc_state && old_crtc_state->self_refresh_active)
239 return;
240
241 ret = clk_prepare_enable(dp->grfclk);
242 if (ret < 0) {
243 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
244 return;
245 }
246
247 ret = drm_of_encoder_active_endpoint(dp->dev->of_node, encoder, &endpoint);
248 if (ret < 0)
249 return;
250
251 remote_port_parent = of_graph_get_remote_port_parent(endpoint.local_node);
252 if (remote_port_parent) {
253 if (of_get_child_by_name(remote_port_parent, "ports")) {
254 remote_port = of_graph_get_remote_port(endpoint.local_node);
255 of_property_read_u32(remote_port, "reg", &port_id);
256 of_node_put(remote_port);
257 sprintf(name, "%s vp%d", remote_port_parent->full_name, port_id);
258 } else {
259 sprintf(name, "%s %s",
260 remote_port_parent->full_name, endpoint.id ? "vopl" : "vopb");
261 }
262 of_node_put(remote_port_parent);
263
264 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
265 }
266
267 ret = rockchip_grf_field_write(dp->grf, &dp->data->lcdc_sel, endpoint.id);
268 if (ret != 0)
269 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
270
271 clk_disable_unprepare(dp->grfclk);
272 }
273
rockchip_dp_drm_encoder_disable(struct drm_encoder * encoder,struct drm_atomic_state * state)274 static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
275 struct drm_atomic_state *state)
276 {
277 struct rockchip_dp_device *dp = encoder_to_dp(encoder);
278 struct drm_crtc *crtc;
279 struct drm_crtc_state *new_crtc_state = NULL;
280 int ret;
281
282 crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
283 /* No crtc means we're doing a full shutdown */
284 if (!crtc)
285 return;
286
287 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
288 /* If we're not entering self-refresh, no need to wait for vact */
289 if (!new_crtc_state || !new_crtc_state->self_refresh_active)
290 return;
291
292 ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
293 if (ret)
294 DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
295 }
296
297 static int
rockchip_dp_drm_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)298 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
299 struct drm_crtc_state *crtc_state,
300 struct drm_connector_state *conn_state)
301 {
302 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
303 struct drm_display_info *di = &conn_state->connector->display_info;
304
305 /*
306 * The hardware IC designed that VOP must output the RGB10 video
307 * format to eDP controller, and if eDP panel only support RGB8,
308 * then eDP controller should cut down the video data, not via VOP
309 * controller, that's why we need to hardcode the VOP output mode
310 * to RGA10 here.
311 */
312
313 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
314 s->output_type = DRM_MODE_CONNECTOR_eDP;
315 s->output_bpc = di->bpc;
316
317 return 0;
318 }
319
320 static const struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
321 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
322 .mode_set = rockchip_dp_drm_encoder_mode_set,
323 .atomic_enable = rockchip_dp_drm_encoder_enable,
324 .atomic_disable = rockchip_dp_drm_encoder_disable,
325 .atomic_check = rockchip_dp_drm_encoder_atomic_check,
326 };
327
rockchip_dp_of_probe(struct rockchip_dp_device * dp)328 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
329 {
330 struct device *dev = dp->dev;
331 struct device_node *np = dev->of_node;
332
333 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
334 if (IS_ERR(dp->grf))
335 return dev_err_probe(dev, PTR_ERR(dp->grf),
336 "failed to get rockchip,grf property\n");
337
338 dp->grfclk = devm_clk_get_optional(dev, "grf");
339 if (IS_ERR(dp->grfclk))
340 return dev_err_probe(dev, PTR_ERR(dp->grfclk),
341 "failed to get grf clock\n");
342
343 dp->pclk = devm_clk_get(dev, "pclk");
344 if (IS_ERR(dp->pclk))
345 return dev_err_probe(dev, PTR_ERR(dp->pclk),
346 "failed to get pclk property\n");
347
348 dp->rst = devm_reset_control_get(dev, "dp");
349 if (IS_ERR(dp->rst))
350 return dev_err_probe(dev, PTR_ERR(dp->rst),
351 "failed to get dp reset control\n");
352
353 dp->apbrst = devm_reset_control_get_optional(dev, "apb");
354 if (IS_ERR(dp->apbrst))
355 return dev_err_probe(dev, PTR_ERR(dp->apbrst),
356 "failed to get apb reset control\n");
357
358 return 0;
359 }
360
rockchip_dp_drm_create_encoder(struct rockchip_dp_device * dp)361 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
362 {
363 struct drm_encoder *encoder = &dp->encoder.encoder;
364 struct drm_device *drm_dev = dp->drm_dev;
365 struct device *dev = dp->dev;
366 int ret;
367
368 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
369 dev->of_node);
370 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
371
372 ret = drm_simple_encoder_init(drm_dev, encoder,
373 DRM_MODE_ENCODER_TMDS);
374 if (ret) {
375 DRM_ERROR("failed to initialize encoder with drm\n");
376 return ret;
377 }
378
379 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
380
381 return 0;
382 }
383
rockchip_dp_bind(struct device * dev,struct device * master,void * data)384 static int rockchip_dp_bind(struct device *dev, struct device *master,
385 void *data)
386 {
387 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
388 struct drm_device *drm_dev = data;
389 int ret;
390
391 dp->drm_dev = drm_dev;
392
393 ret = rockchip_dp_drm_create_encoder(dp);
394 if (ret) {
395 DRM_ERROR("failed to create drm encoder\n");
396 return ret;
397 }
398
399 rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder,
400 dev->of_node, 0, 0);
401
402 dp->plat_data.encoder = &dp->encoder.encoder;
403
404 ret = analogix_dp_bind(dp->adp, drm_dev);
405 if (ret)
406 goto err_cleanup_encoder;
407
408 return 0;
409 err_cleanup_encoder:
410 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
411 return ret;
412 }
413
rockchip_dp_unbind(struct device * dev,struct device * master,void * data)414 static void rockchip_dp_unbind(struct device *dev, struct device *master,
415 void *data)
416 {
417 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
418
419 analogix_dp_unbind(dp->adp);
420 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
421 }
422
423 static const struct component_ops rockchip_dp_component_ops = {
424 .bind = rockchip_dp_bind,
425 .unbind = rockchip_dp_unbind,
426 };
427
rockchip_dp_link_panel(struct drm_dp_aux * aux)428 static int rockchip_dp_link_panel(struct drm_dp_aux *aux)
429 {
430 struct analogix_dp_plat_data *plat_data = analogix_dp_aux_to_plat_data(aux);
431 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
432 int ret;
433
434 /*
435 * If drm_of_find_panel_or_bridge() returns -ENODEV, there may be no valid panel
436 * or bridge nodes. The driver should go on for the driver-free bridge or the DP
437 * mode applications.
438 */
439 ret = drm_of_find_panel_or_bridge(dp->dev->of_node, 1, 0, &plat_data->panel, NULL);
440 if (ret && ret != -ENODEV)
441 return ret;
442
443 return component_add(dp->dev, &rockchip_dp_component_ops);
444 }
445
rockchip_dp_probe(struct platform_device * pdev)446 static int rockchip_dp_probe(struct platform_device *pdev)
447 {
448 struct device *dev = &pdev->dev;
449 const struct rockchip_dp_chip_data *dp_data;
450 struct rockchip_dp_device *dp;
451 struct resource *res;
452 int i;
453 int ret;
454
455 dp_data = of_device_get_match_data(dev);
456 if (!dp_data)
457 return -ENODEV;
458
459 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
460 if (!dp)
461 return -ENOMEM;
462
463 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
464
465 i = 0;
466 while (dp_data[i].reg) {
467 if (dp_data[i].reg == res->start) {
468 dp->data = &dp_data[i];
469 break;
470 }
471
472 i++;
473 }
474
475 if (!dp->data)
476 return dev_err_probe(dev, -EINVAL, "no chip-data for %s node\n",
477 dev->of_node->name);
478
479 dp->dev = dev;
480 dp->adp = ERR_PTR(-ENODEV);
481 dp->plat_data.dev_type = dp->data->chip_type;
482 dp->plat_data.power_on = rockchip_dp_poweron;
483 dp->plat_data.power_off = rockchip_dp_powerdown;
484 dp->plat_data.get_modes = rockchip_dp_get_modes;
485
486 ret = rockchip_dp_of_probe(dp);
487 if (ret < 0)
488 return ret;
489
490 platform_set_drvdata(pdev, dp);
491
492 dp->adp = analogix_dp_probe(dev, &dp->plat_data);
493 if (IS_ERR(dp->adp))
494 return PTR_ERR(dp->adp);
495
496 ret = devm_of_dp_aux_populate_bus(analogix_dp_get_aux(dp->adp), rockchip_dp_link_panel);
497 if (ret) {
498 /*
499 * If devm_of_dp_aux_populate_bus() returns -ENODEV, the done_probing() will not
500 * be called because there are no EP devices. Then the rockchip_dp_link_panel()
501 * will be called directly in order to support the other valid DT configurations.
502 *
503 * NOTE: The devm_of_dp_aux_populate_bus() is allowed to return -EPROBE_DEFER.
504 */
505 if (ret != -ENODEV)
506 return dev_err_probe(dp->dev, ret, "failed to populate aux bus\n");
507
508 return rockchip_dp_link_panel(analogix_dp_get_aux(dp->adp));
509 }
510
511 return 0;
512 }
513
rockchip_dp_remove(struct platform_device * pdev)514 static void rockchip_dp_remove(struct platform_device *pdev)
515 {
516 component_del(&pdev->dev, &rockchip_dp_component_ops);
517 }
518
rockchip_dp_suspend(struct device * dev)519 static int rockchip_dp_suspend(struct device *dev)
520 {
521 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
522
523 if (IS_ERR(dp->adp))
524 return 0;
525
526 return analogix_dp_suspend(dp->adp);
527 }
528
rockchip_dp_resume(struct device * dev)529 static int rockchip_dp_resume(struct device *dev)
530 {
531 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
532
533 if (IS_ERR(dp->adp))
534 return 0;
535
536 return analogix_dp_resume(dp->adp);
537 }
538
539 static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, rockchip_dp_suspend,
540 rockchip_dp_resume, NULL);
541
542 static const struct rockchip_dp_chip_data rk3399_edp[] = {
543 {
544 .lcdc_sel = GRF_REG_FIELD(0x6250, 5, 5),
545 .chip_type = RK3399_EDP,
546 .reg = 0xff970000,
547 },
548 { /* sentinel */ }
549 };
550
551 static const struct rockchip_dp_chip_data rk3288_dp[] = {
552 {
553 .lcdc_sel = GRF_REG_FIELD(0x025c, 5, 5),
554 .chip_type = RK3288_DP,
555 .reg = 0xff970000,
556 },
557 { /* sentinel */ }
558 };
559
560 static const struct rockchip_dp_chip_data rk3588_edp[] = {
561 {
562 .edp_mode = GRF_REG_FIELD(0x0000, 0, 0),
563 .chip_type = RK3588_EDP,
564 .reg = 0xfdec0000,
565 },
566 {
567 .edp_mode = GRF_REG_FIELD(0x0004, 0, 0),
568 .chip_type = RK3588_EDP,
569 .reg = 0xfded0000,
570 },
571 { /* sentinel */ }
572 };
573
574 static const struct of_device_id rockchip_dp_dt_ids[] = {
575 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
576 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
577 {.compatible = "rockchip,rk3588-edp", .data = &rk3588_edp },
578 {}
579 };
580 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
581
582 struct platform_driver rockchip_dp_driver = {
583 .probe = rockchip_dp_probe,
584 .remove = rockchip_dp_remove,
585 .driver = {
586 .name = "rockchip-dp",
587 .pm = pm_ptr(&rockchip_dp_pm_ops),
588 .of_match_table = rockchip_dp_dt_ids,
589 },
590 };
591