1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
4 * Author: Lin Huang <hl@rock-chips.com>
5 */
6
7 #include <linux/arm-smccc.h>
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/slab.h>
12 #include <soc/rockchip/rockchip_sip.h>
13 #include "clk.h"
14
15 struct rockchip_ddrclk {
16 struct clk_hw hw;
17 void __iomem *reg_base;
18 int mux_offset;
19 int mux_shift;
20 int mux_width;
21 int div_shift;
22 int div_width;
23 int ddr_flag;
24 spinlock_t *lock;
25 };
26
27 #define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw)
28
rockchip_ddrclk_sip_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)29 static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate,
30 unsigned long prate)
31 {
32 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
33 unsigned long flags;
34 struct arm_smccc_res res;
35
36 spin_lock_irqsave(ddrclk->lock, flags);
37 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0,
38 ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
39 0, 0, 0, 0, &res);
40 spin_unlock_irqrestore(ddrclk->lock, flags);
41
42 return res.a0;
43 }
44
45 static unsigned long
rockchip_ddrclk_sip_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)46 rockchip_ddrclk_sip_recalc_rate(struct clk_hw *hw,
47 unsigned long parent_rate)
48 {
49 struct arm_smccc_res res;
50
51 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
52 ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
53 0, 0, 0, 0, &res);
54
55 return res.a0;
56 }
57
rockchip_ddrclk_sip_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)58 static int rockchip_ddrclk_sip_determine_rate(struct clk_hw *hw,
59 struct clk_rate_request *req)
60 {
61 struct arm_smccc_res res;
62
63 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, req->rate, 0,
64 ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
65 0, 0, 0, 0, &res);
66
67 req->rate = res.a0;
68
69 return 0;
70 }
71
rockchip_ddrclk_get_parent(struct clk_hw * hw)72 static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
73 {
74 struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
75 u32 val;
76
77 val = readl(ddrclk->reg_base +
78 ddrclk->mux_offset) >> ddrclk->mux_shift;
79 val &= GENMASK(ddrclk->mux_width - 1, 0);
80
81 return val;
82 }
83
84 static const struct clk_ops rockchip_ddrclk_sip_ops = {
85 .recalc_rate = rockchip_ddrclk_sip_recalc_rate,
86 .set_rate = rockchip_ddrclk_sip_set_rate,
87 .determine_rate = rockchip_ddrclk_sip_determine_rate,
88 .get_parent = rockchip_ddrclk_get_parent,
89 };
90
rockchip_clk_register_ddrclk(const char * name,int flags,const char * const * parent_names,u8 num_parents,int mux_offset,int mux_shift,int mux_width,int div_shift,int div_width,int ddr_flag,void __iomem * reg_base,spinlock_t * lock)91 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
92 const char *const *parent_names,
93 u8 num_parents, int mux_offset,
94 int mux_shift, int mux_width,
95 int div_shift, int div_width,
96 int ddr_flag, void __iomem *reg_base,
97 spinlock_t *lock)
98 {
99 struct rockchip_ddrclk *ddrclk;
100 struct clk_init_data init;
101 struct clk *clk;
102
103 ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL);
104 if (!ddrclk)
105 return ERR_PTR(-ENOMEM);
106
107 init.name = name;
108 init.parent_names = parent_names;
109 init.num_parents = num_parents;
110
111 init.flags = flags;
112 init.flags |= CLK_SET_RATE_NO_REPARENT;
113
114 switch (ddr_flag) {
115 case ROCKCHIP_DDRCLK_SIP:
116 init.ops = &rockchip_ddrclk_sip_ops;
117 break;
118 default:
119 pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
120 kfree(ddrclk);
121 return ERR_PTR(-EINVAL);
122 }
123
124 ddrclk->reg_base = reg_base;
125 ddrclk->lock = lock;
126 ddrclk->hw.init = &init;
127 ddrclk->mux_offset = mux_offset;
128 ddrclk->mux_shift = mux_shift;
129 ddrclk->mux_width = mux_width;
130 ddrclk->div_shift = div_shift;
131 ddrclk->div_width = div_width;
132 ddrclk->ddr_flag = ddr_flag;
133
134 clk = clk_register(NULL, &ddrclk->hw);
135 if (IS_ERR(clk))
136 kfree(ddrclk);
137
138 return clk;
139 }
140 EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);
141