1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/dma-mapping.h>
5 #include <linux/etherdevice.h>
6 #include <linux/interrupt.h>
7 #ifdef CONFIG_RFS_ACCEL
8 #include <linux/cpu_rmap.h>
9 #endif
10 #include <linux/if_vlan.h>
11 #include <linux/irq.h>
12 #include <linux/ip.h>
13 #include <linux/ipv6.h>
14 #include <linux/iommu.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/skbuff.h>
18 #include <linux/sctp.h>
19 #include <net/gre.h>
20 #include <net/gro.h>
21 #include <net/ip6_checksum.h>
22 #include <net/page_pool/helpers.h>
23 #include <net/pkt_cls.h>
24 #include <net/pkt_sched.h>
25 #include <net/tcp.h>
26 #include <net/vxlan.h>
27 #include <net/geneve.h>
28 #include <net/netdev_queues.h>
29
30 #include "hnae3.h"
31 #include "hns3_enet.h"
32 /* All hns3 tracepoints are defined by the include below, which
33 * must be included exactly once across the whole kernel with
34 * CREATE_TRACE_POINTS defined
35 */
36 #define CREATE_TRACE_POINTS
37 #include "hns3_trace.h"
38
39 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift))
40 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
41
42 #define hns3_rl_err(fmt, ...) \
43 do { \
44 if (net_ratelimit()) \
45 netdev_err(fmt, ##__VA_ARGS__); \
46 } while (0)
47
48 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
49
50 static const char hns3_driver_name[] = "hns3";
51 static const char hns3_driver_string[] =
52 "Hisilicon Ethernet Network Driver for Hip08 Family";
53 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
54 static struct hnae3_client client;
55
56 static int debug = -1;
57 module_param(debug, int, 0);
58 MODULE_PARM_DESC(debug, " Network interface message level setting");
59
60 static unsigned int tx_sgl = 1;
61 module_param(tx_sgl, uint, 0600);
62 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
63
64 static bool page_pool_enabled = true;
65 module_param(page_pool_enabled, bool, 0400);
66
67 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \
68 sizeof(struct sg_table))
69 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
70 dma_get_cache_alignment())
71
72 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
73 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
74
75 #define HNS3_INNER_VLAN_TAG 1
76 #define HNS3_OUTER_VLAN_TAG 2
77
78 #define HNS3_MIN_TX_LEN 33U
79 #define HNS3_MIN_TUN_PKT_LEN 65U
80
81 /* hns3_pci_tbl - PCI Device ID Table
82 *
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88 static const struct pci_device_id hns3_pci_tbl[] = {
89 {
90 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE),
91 .driver_data = 0,
92 }, {
93 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE),
94 .driver_data = 0,
95 }, {
96 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA),
97 .driver_data = HNAE3_DEV_SUPPORT_ROCE_DCB_BITS,
98 }, {
99 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC),
100 .driver_data = HNAE3_DEV_SUPPORT_ROCE_DCB_BITS,
101 }, {
102 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA),
103 .driver_data = HNAE3_DEV_SUPPORT_ROCE_DCB_BITS,
104 }, {
105 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC),
106 .driver_data = HNAE3_DEV_SUPPORT_ROCE_DCB_BITS,
107 }, {
108 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
109 .driver_data = HNAE3_DEV_SUPPORT_ROCE_DCB_BITS,
110 }, {
111 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
112 .driver_data = HNAE3_DEV_SUPPORT_ROCE_DCB_BITS,
113 }, {
114 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF),
115 .driver_data = 0,
116 }, {
117 PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
118 .driver_data = HNAE3_DEV_SUPPORT_ROCE_DCB_BITS,
119 },
120 /* required last entry */
121 { }
122 };
123 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
124
125 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \
126 { ptype, \
127 l, \
128 CHECKSUM_##s, \
129 HNS3_L3_TYPE_##t, \
130 1, \
131 h}
132
133 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \
134 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \
135 PKT_HASH_TYPE_NONE }
136
137 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = {
138 HNS3_RX_PTYPE_UNUSED_ENTRY(0),
139 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE),
140 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE),
141 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE),
142 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
143 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
144 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
145 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE),
146 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
147 HNS3_RX_PTYPE_UNUSED_ENTRY(9),
148 HNS3_RX_PTYPE_UNUSED_ENTRY(10),
149 HNS3_RX_PTYPE_UNUSED_ENTRY(11),
150 HNS3_RX_PTYPE_UNUSED_ENTRY(12),
151 HNS3_RX_PTYPE_UNUSED_ENTRY(13),
152 HNS3_RX_PTYPE_UNUSED_ENTRY(14),
153 HNS3_RX_PTYPE_UNUSED_ENTRY(15),
154 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
155 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
156 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE),
157 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
158 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
159 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE),
160 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
161 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
162 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3),
163 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
164 HNS3_RX_PTYPE_UNUSED_ENTRY(26),
165 HNS3_RX_PTYPE_UNUSED_ENTRY(27),
166 HNS3_RX_PTYPE_UNUSED_ENTRY(28),
167 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
168 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
169 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
170 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
171 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
172 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
173 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
174 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
175 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
176 HNS3_RX_PTYPE_UNUSED_ENTRY(38),
177 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
178 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
179 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
180 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
181 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
182 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
183 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
184 HNS3_RX_PTYPE_UNUSED_ENTRY(46),
185 HNS3_RX_PTYPE_UNUSED_ENTRY(47),
186 HNS3_RX_PTYPE_UNUSED_ENTRY(48),
187 HNS3_RX_PTYPE_UNUSED_ENTRY(49),
188 HNS3_RX_PTYPE_UNUSED_ENTRY(50),
189 HNS3_RX_PTYPE_UNUSED_ENTRY(51),
190 HNS3_RX_PTYPE_UNUSED_ENTRY(52),
191 HNS3_RX_PTYPE_UNUSED_ENTRY(53),
192 HNS3_RX_PTYPE_UNUSED_ENTRY(54),
193 HNS3_RX_PTYPE_UNUSED_ENTRY(55),
194 HNS3_RX_PTYPE_UNUSED_ENTRY(56),
195 HNS3_RX_PTYPE_UNUSED_ENTRY(57),
196 HNS3_RX_PTYPE_UNUSED_ENTRY(58),
197 HNS3_RX_PTYPE_UNUSED_ENTRY(59),
198 HNS3_RX_PTYPE_UNUSED_ENTRY(60),
199 HNS3_RX_PTYPE_UNUSED_ENTRY(61),
200 HNS3_RX_PTYPE_UNUSED_ENTRY(62),
201 HNS3_RX_PTYPE_UNUSED_ENTRY(63),
202 HNS3_RX_PTYPE_UNUSED_ENTRY(64),
203 HNS3_RX_PTYPE_UNUSED_ENTRY(65),
204 HNS3_RX_PTYPE_UNUSED_ENTRY(66),
205 HNS3_RX_PTYPE_UNUSED_ENTRY(67),
206 HNS3_RX_PTYPE_UNUSED_ENTRY(68),
207 HNS3_RX_PTYPE_UNUSED_ENTRY(69),
208 HNS3_RX_PTYPE_UNUSED_ENTRY(70),
209 HNS3_RX_PTYPE_UNUSED_ENTRY(71),
210 HNS3_RX_PTYPE_UNUSED_ENTRY(72),
211 HNS3_RX_PTYPE_UNUSED_ENTRY(73),
212 HNS3_RX_PTYPE_UNUSED_ENTRY(74),
213 HNS3_RX_PTYPE_UNUSED_ENTRY(75),
214 HNS3_RX_PTYPE_UNUSED_ENTRY(76),
215 HNS3_RX_PTYPE_UNUSED_ENTRY(77),
216 HNS3_RX_PTYPE_UNUSED_ENTRY(78),
217 HNS3_RX_PTYPE_UNUSED_ENTRY(79),
218 HNS3_RX_PTYPE_UNUSED_ENTRY(80),
219 HNS3_RX_PTYPE_UNUSED_ENTRY(81),
220 HNS3_RX_PTYPE_UNUSED_ENTRY(82),
221 HNS3_RX_PTYPE_UNUSED_ENTRY(83),
222 HNS3_RX_PTYPE_UNUSED_ENTRY(84),
223 HNS3_RX_PTYPE_UNUSED_ENTRY(85),
224 HNS3_RX_PTYPE_UNUSED_ENTRY(86),
225 HNS3_RX_PTYPE_UNUSED_ENTRY(87),
226 HNS3_RX_PTYPE_UNUSED_ENTRY(88),
227 HNS3_RX_PTYPE_UNUSED_ENTRY(89),
228 HNS3_RX_PTYPE_UNUSED_ENTRY(90),
229 HNS3_RX_PTYPE_UNUSED_ENTRY(91),
230 HNS3_RX_PTYPE_UNUSED_ENTRY(92),
231 HNS3_RX_PTYPE_UNUSED_ENTRY(93),
232 HNS3_RX_PTYPE_UNUSED_ENTRY(94),
233 HNS3_RX_PTYPE_UNUSED_ENTRY(95),
234 HNS3_RX_PTYPE_UNUSED_ENTRY(96),
235 HNS3_RX_PTYPE_UNUSED_ENTRY(97),
236 HNS3_RX_PTYPE_UNUSED_ENTRY(98),
237 HNS3_RX_PTYPE_UNUSED_ENTRY(99),
238 HNS3_RX_PTYPE_UNUSED_ENTRY(100),
239 HNS3_RX_PTYPE_UNUSED_ENTRY(101),
240 HNS3_RX_PTYPE_UNUSED_ENTRY(102),
241 HNS3_RX_PTYPE_UNUSED_ENTRY(103),
242 HNS3_RX_PTYPE_UNUSED_ENTRY(104),
243 HNS3_RX_PTYPE_UNUSED_ENTRY(105),
244 HNS3_RX_PTYPE_UNUSED_ENTRY(106),
245 HNS3_RX_PTYPE_UNUSED_ENTRY(107),
246 HNS3_RX_PTYPE_UNUSED_ENTRY(108),
247 HNS3_RX_PTYPE_UNUSED_ENTRY(109),
248 HNS3_RX_PTYPE_UNUSED_ENTRY(110),
249 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
250 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
251 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
252 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
253 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
254 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
255 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
256 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3),
257 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
258 HNS3_RX_PTYPE_UNUSED_ENTRY(120),
259 HNS3_RX_PTYPE_UNUSED_ENTRY(121),
260 HNS3_RX_PTYPE_UNUSED_ENTRY(122),
261 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
262 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE),
263 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
264 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
265 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
266 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
267 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4),
268 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
269 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3),
270 HNS3_RX_PTYPE_UNUSED_ENTRY(132),
271 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
272 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
273 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
274 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
275 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4),
276 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
277 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3),
278 HNS3_RX_PTYPE_UNUSED_ENTRY(140),
279 HNS3_RX_PTYPE_UNUSED_ENTRY(141),
280 HNS3_RX_PTYPE_UNUSED_ENTRY(142),
281 HNS3_RX_PTYPE_UNUSED_ENTRY(143),
282 HNS3_RX_PTYPE_UNUSED_ENTRY(144),
283 HNS3_RX_PTYPE_UNUSED_ENTRY(145),
284 HNS3_RX_PTYPE_UNUSED_ENTRY(146),
285 HNS3_RX_PTYPE_UNUSED_ENTRY(147),
286 HNS3_RX_PTYPE_UNUSED_ENTRY(148),
287 HNS3_RX_PTYPE_UNUSED_ENTRY(149),
288 HNS3_RX_PTYPE_UNUSED_ENTRY(150),
289 HNS3_RX_PTYPE_UNUSED_ENTRY(151),
290 HNS3_RX_PTYPE_UNUSED_ENTRY(152),
291 HNS3_RX_PTYPE_UNUSED_ENTRY(153),
292 HNS3_RX_PTYPE_UNUSED_ENTRY(154),
293 HNS3_RX_PTYPE_UNUSED_ENTRY(155),
294 HNS3_RX_PTYPE_UNUSED_ENTRY(156),
295 HNS3_RX_PTYPE_UNUSED_ENTRY(157),
296 HNS3_RX_PTYPE_UNUSED_ENTRY(158),
297 HNS3_RX_PTYPE_UNUSED_ENTRY(159),
298 HNS3_RX_PTYPE_UNUSED_ENTRY(160),
299 HNS3_RX_PTYPE_UNUSED_ENTRY(161),
300 HNS3_RX_PTYPE_UNUSED_ENTRY(162),
301 HNS3_RX_PTYPE_UNUSED_ENTRY(163),
302 HNS3_RX_PTYPE_UNUSED_ENTRY(164),
303 HNS3_RX_PTYPE_UNUSED_ENTRY(165),
304 HNS3_RX_PTYPE_UNUSED_ENTRY(166),
305 HNS3_RX_PTYPE_UNUSED_ENTRY(167),
306 HNS3_RX_PTYPE_UNUSED_ENTRY(168),
307 HNS3_RX_PTYPE_UNUSED_ENTRY(169),
308 HNS3_RX_PTYPE_UNUSED_ENTRY(170),
309 HNS3_RX_PTYPE_UNUSED_ENTRY(171),
310 HNS3_RX_PTYPE_UNUSED_ENTRY(172),
311 HNS3_RX_PTYPE_UNUSED_ENTRY(173),
312 HNS3_RX_PTYPE_UNUSED_ENTRY(174),
313 HNS3_RX_PTYPE_UNUSED_ENTRY(175),
314 HNS3_RX_PTYPE_UNUSED_ENTRY(176),
315 HNS3_RX_PTYPE_UNUSED_ENTRY(177),
316 HNS3_RX_PTYPE_UNUSED_ENTRY(178),
317 HNS3_RX_PTYPE_UNUSED_ENTRY(179),
318 HNS3_RX_PTYPE_UNUSED_ENTRY(180),
319 HNS3_RX_PTYPE_UNUSED_ENTRY(181),
320 HNS3_RX_PTYPE_UNUSED_ENTRY(182),
321 HNS3_RX_PTYPE_UNUSED_ENTRY(183),
322 HNS3_RX_PTYPE_UNUSED_ENTRY(184),
323 HNS3_RX_PTYPE_UNUSED_ENTRY(185),
324 HNS3_RX_PTYPE_UNUSED_ENTRY(186),
325 HNS3_RX_PTYPE_UNUSED_ENTRY(187),
326 HNS3_RX_PTYPE_UNUSED_ENTRY(188),
327 HNS3_RX_PTYPE_UNUSED_ENTRY(189),
328 HNS3_RX_PTYPE_UNUSED_ENTRY(190),
329 HNS3_RX_PTYPE_UNUSED_ENTRY(191),
330 HNS3_RX_PTYPE_UNUSED_ENTRY(192),
331 HNS3_RX_PTYPE_UNUSED_ENTRY(193),
332 HNS3_RX_PTYPE_UNUSED_ENTRY(194),
333 HNS3_RX_PTYPE_UNUSED_ENTRY(195),
334 HNS3_RX_PTYPE_UNUSED_ENTRY(196),
335 HNS3_RX_PTYPE_UNUSED_ENTRY(197),
336 HNS3_RX_PTYPE_UNUSED_ENTRY(198),
337 HNS3_RX_PTYPE_UNUSED_ENTRY(199),
338 HNS3_RX_PTYPE_UNUSED_ENTRY(200),
339 HNS3_RX_PTYPE_UNUSED_ENTRY(201),
340 HNS3_RX_PTYPE_UNUSED_ENTRY(202),
341 HNS3_RX_PTYPE_UNUSED_ENTRY(203),
342 HNS3_RX_PTYPE_UNUSED_ENTRY(204),
343 HNS3_RX_PTYPE_UNUSED_ENTRY(205),
344 HNS3_RX_PTYPE_UNUSED_ENTRY(206),
345 HNS3_RX_PTYPE_UNUSED_ENTRY(207),
346 HNS3_RX_PTYPE_UNUSED_ENTRY(208),
347 HNS3_RX_PTYPE_UNUSED_ENTRY(209),
348 HNS3_RX_PTYPE_UNUSED_ENTRY(210),
349 HNS3_RX_PTYPE_UNUSED_ENTRY(211),
350 HNS3_RX_PTYPE_UNUSED_ENTRY(212),
351 HNS3_RX_PTYPE_UNUSED_ENTRY(213),
352 HNS3_RX_PTYPE_UNUSED_ENTRY(214),
353 HNS3_RX_PTYPE_UNUSED_ENTRY(215),
354 HNS3_RX_PTYPE_UNUSED_ENTRY(216),
355 HNS3_RX_PTYPE_UNUSED_ENTRY(217),
356 HNS3_RX_PTYPE_UNUSED_ENTRY(218),
357 HNS3_RX_PTYPE_UNUSED_ENTRY(219),
358 HNS3_RX_PTYPE_UNUSED_ENTRY(220),
359 HNS3_RX_PTYPE_UNUSED_ENTRY(221),
360 HNS3_RX_PTYPE_UNUSED_ENTRY(222),
361 HNS3_RX_PTYPE_UNUSED_ENTRY(223),
362 HNS3_RX_PTYPE_UNUSED_ENTRY(224),
363 HNS3_RX_PTYPE_UNUSED_ENTRY(225),
364 HNS3_RX_PTYPE_UNUSED_ENTRY(226),
365 HNS3_RX_PTYPE_UNUSED_ENTRY(227),
366 HNS3_RX_PTYPE_UNUSED_ENTRY(228),
367 HNS3_RX_PTYPE_UNUSED_ENTRY(229),
368 HNS3_RX_PTYPE_UNUSED_ENTRY(230),
369 HNS3_RX_PTYPE_UNUSED_ENTRY(231),
370 HNS3_RX_PTYPE_UNUSED_ENTRY(232),
371 HNS3_RX_PTYPE_UNUSED_ENTRY(233),
372 HNS3_RX_PTYPE_UNUSED_ENTRY(234),
373 HNS3_RX_PTYPE_UNUSED_ENTRY(235),
374 HNS3_RX_PTYPE_UNUSED_ENTRY(236),
375 HNS3_RX_PTYPE_UNUSED_ENTRY(237),
376 HNS3_RX_PTYPE_UNUSED_ENTRY(238),
377 HNS3_RX_PTYPE_UNUSED_ENTRY(239),
378 HNS3_RX_PTYPE_UNUSED_ENTRY(240),
379 HNS3_RX_PTYPE_UNUSED_ENTRY(241),
380 HNS3_RX_PTYPE_UNUSED_ENTRY(242),
381 HNS3_RX_PTYPE_UNUSED_ENTRY(243),
382 HNS3_RX_PTYPE_UNUSED_ENTRY(244),
383 HNS3_RX_PTYPE_UNUSED_ENTRY(245),
384 HNS3_RX_PTYPE_UNUSED_ENTRY(246),
385 HNS3_RX_PTYPE_UNUSED_ENTRY(247),
386 HNS3_RX_PTYPE_UNUSED_ENTRY(248),
387 HNS3_RX_PTYPE_UNUSED_ENTRY(249),
388 HNS3_RX_PTYPE_UNUSED_ENTRY(250),
389 HNS3_RX_PTYPE_UNUSED_ENTRY(251),
390 HNS3_RX_PTYPE_UNUSED_ENTRY(252),
391 HNS3_RX_PTYPE_UNUSED_ENTRY(253),
392 HNS3_RX_PTYPE_UNUSED_ENTRY(254),
393 HNS3_RX_PTYPE_UNUSED_ENTRY(255),
394 };
395
396 #define HNS3_INVALID_PTYPE \
397 ARRAY_SIZE(hns3_rx_ptype_tbl)
398
hns3_irq_handle(int irq,void * vector)399 static irqreturn_t hns3_irq_handle(int irq, void *vector)
400 {
401 struct hns3_enet_tqp_vector *tqp_vector = vector;
402
403 napi_schedule_irqoff(&tqp_vector->napi);
404 tqp_vector->event_cnt++;
405
406 return IRQ_HANDLED;
407 }
408
hns3_nic_uninit_irq(struct hns3_nic_priv * priv)409 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
410 {
411 struct hns3_enet_tqp_vector *tqp_vectors;
412 unsigned int i;
413
414 for (i = 0; i < priv->vector_num; i++) {
415 tqp_vectors = &priv->tqp_vector[i];
416
417 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED)
418 continue;
419
420 /* clear the affinity mask */
421 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL);
422
423 /* release the irq resource */
424 free_irq(tqp_vectors->vector_irq, tqp_vectors);
425 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED;
426 }
427 }
428
hns3_nic_init_irq(struct hns3_nic_priv * priv)429 static int hns3_nic_init_irq(struct hns3_nic_priv *priv)
430 {
431 struct hns3_enet_tqp_vector *tqp_vectors;
432 int txrx_int_idx = 0;
433 int rx_int_idx = 0;
434 int tx_int_idx = 0;
435 unsigned int i;
436 int ret;
437
438 for (i = 0; i < priv->vector_num; i++) {
439 tqp_vectors = &priv->tqp_vector[i];
440
441 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED)
442 continue;
443
444 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) {
445 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
446 "%s-%s-%s-%d", hns3_driver_name,
447 pci_name(priv->ae_handle->pdev),
448 "TxRx", txrx_int_idx++);
449 txrx_int_idx++;
450 } else if (tqp_vectors->rx_group.ring) {
451 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
452 "%s-%s-%s-%d", hns3_driver_name,
453 pci_name(priv->ae_handle->pdev),
454 "Rx", rx_int_idx++);
455 } else if (tqp_vectors->tx_group.ring) {
456 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN,
457 "%s-%s-%s-%d", hns3_driver_name,
458 pci_name(priv->ae_handle->pdev),
459 "Tx", tx_int_idx++);
460 } else {
461 /* Skip this unused q_vector */
462 continue;
463 }
464
465 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0';
466
467 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN);
468 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0,
469 tqp_vectors->name, tqp_vectors);
470 if (ret) {
471 netdev_err(priv->netdev, "request irq(%d) fail\n",
472 tqp_vectors->vector_irq);
473 hns3_nic_uninit_irq(priv);
474 return ret;
475 }
476
477 irq_set_affinity_hint(tqp_vectors->vector_irq,
478 &tqp_vectors->affinity_mask);
479
480 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED;
481 }
482
483 return 0;
484 }
485
hns3_mask_vector_irq(struct hns3_enet_tqp_vector * tqp_vector,u32 mask_en)486 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector,
487 u32 mask_en)
488 {
489 writel(mask_en, tqp_vector->mask_addr);
490 }
491
hns3_irq_enable(struct hns3_enet_tqp_vector * tqp_vector)492 static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector)
493 {
494 napi_enable(&tqp_vector->napi);
495 enable_irq(tqp_vector->vector_irq);
496 }
497
hns3_irq_disable(struct hns3_enet_tqp_vector * tqp_vector)498 static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector)
499 {
500 disable_irq(tqp_vector->vector_irq);
501 napi_disable(&tqp_vector->napi);
502 cancel_work_sync(&tqp_vector->rx_group.dim.work);
503 cancel_work_sync(&tqp_vector->tx_group.dim.work);
504 }
505
hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector * tqp_vector,u32 rl_value)506 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
507 u32 rl_value)
508 {
509 u32 rl_reg = hns3_rl_usec_to_reg(rl_value);
510
511 /* this defines the configuration for RL (Interrupt Rate Limiter).
512 * Rl defines rate of interrupts i.e. number of interrupts-per-second
513 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
514 */
515 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
516 !tqp_vector->rx_group.coal.adapt_enable)
517 /* According to the hardware, the range of rl_reg is
518 * 0-59 and the unit is 4.
519 */
520 rl_reg |= HNS3_INT_RL_ENABLE_MASK;
521
522 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET);
523 }
524
hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)525 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
526 u32 gl_value)
527 {
528 u32 new_val;
529
530 if (tqp_vector->rx_group.coal.unit_1us)
531 new_val = gl_value | HNS3_INT_GL_1US;
532 else
533 new_val = hns3_gl_usec_to_reg(gl_value);
534
535 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET);
536 }
537
hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector * tqp_vector,u32 gl_value)538 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
539 u32 gl_value)
540 {
541 u32 new_val;
542
543 if (tqp_vector->tx_group.coal.unit_1us)
544 new_val = gl_value | HNS3_INT_GL_1US;
545 else
546 new_val = hns3_gl_usec_to_reg(gl_value);
547
548 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
549 }
550
hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)551 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
552 u32 ql_value)
553 {
554 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
555 }
556
hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector * tqp_vector,u32 ql_value)557 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
558 u32 ql_value)
559 {
560 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
561 }
562
hns3_vector_coalesce_init(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)563 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
564 struct hns3_nic_priv *priv)
565 {
566 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
567 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
568 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
569 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
570 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
571
572 tx_coal->adapt_enable = ptx_coal->adapt_enable;
573 rx_coal->adapt_enable = prx_coal->adapt_enable;
574
575 tx_coal->int_gl = ptx_coal->int_gl;
576 rx_coal->int_gl = prx_coal->int_gl;
577
578 rx_coal->flow_level = prx_coal->flow_level;
579 tx_coal->flow_level = ptx_coal->flow_level;
580
581 /* device version above V3(include V3), GL can configure 1us
582 * unit, so uses 1us unit.
583 */
584 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
585 tx_coal->unit_1us = 1;
586 rx_coal->unit_1us = 1;
587 }
588
589 if (ae_dev->dev_specs.int_ql_max) {
590 tx_coal->ql_enable = 1;
591 rx_coal->ql_enable = 1;
592 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
593 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
594 tx_coal->int_ql = ptx_coal->int_ql;
595 rx_coal->int_ql = prx_coal->int_ql;
596 }
597 }
598
599 static void
hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector * tqp_vector,struct hns3_nic_priv * priv)600 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
601 struct hns3_nic_priv *priv)
602 {
603 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
604 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
605 struct hnae3_handle *h = priv->ae_handle;
606
607 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
608 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
609 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
610
611 if (tx_coal->ql_enable)
612 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
613
614 if (rx_coal->ql_enable)
615 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
616 }
617
hns3_nic_set_real_num_queue(struct net_device * netdev)618 static int hns3_nic_set_real_num_queue(struct net_device *netdev)
619 {
620 struct hnae3_handle *h = hns3_get_handle(netdev);
621 struct hnae3_knic_private_info *kinfo = &h->kinfo;
622 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
623 unsigned int queue_size = kinfo->num_tqps;
624 int i, ret;
625
626 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) {
627 netdev_reset_tc(netdev);
628 } else {
629 ret = netdev_set_num_tc(netdev, tc_info->num_tc);
630 if (ret) {
631 netdev_err(netdev,
632 "netdev_set_num_tc fail, ret=%d!\n", ret);
633 return ret;
634 }
635
636 for (i = 0; i < tc_info->num_tc; i++)
637 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i],
638 tc_info->tqp_offset[i]);
639 }
640
641 ret = netif_set_real_num_tx_queues(netdev, queue_size);
642 if (ret) {
643 netdev_err(netdev,
644 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret);
645 return ret;
646 }
647
648 ret = netif_set_real_num_rx_queues(netdev, queue_size);
649 if (ret) {
650 netdev_err(netdev,
651 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret);
652 return ret;
653 }
654
655 return 0;
656 }
657
hns3_get_max_available_channels(struct hnae3_handle * h)658 u16 hns3_get_max_available_channels(struct hnae3_handle *h)
659 {
660 u16 alloc_tqps, max_rss_size, rss_size;
661
662 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size);
663 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc;
664
665 return min_t(u16, rss_size, max_rss_size);
666 }
667
hns3_tqp_enable(struct hnae3_queue * tqp)668 static void hns3_tqp_enable(struct hnae3_queue *tqp)
669 {
670 u32 rcb_reg;
671
672 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
673 rcb_reg |= BIT(HNS3_RING_EN_B);
674 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
675 }
676
hns3_tqp_disable(struct hnae3_queue * tqp)677 static void hns3_tqp_disable(struct hnae3_queue *tqp)
678 {
679 u32 rcb_reg;
680
681 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG);
682 rcb_reg &= ~BIT(HNS3_RING_EN_B);
683 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg);
684 }
685
hns3_free_rx_cpu_rmap(struct net_device * netdev)686 static void hns3_free_rx_cpu_rmap(struct net_device *netdev)
687 {
688 #ifdef CONFIG_RFS_ACCEL
689 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
690 netdev->rx_cpu_rmap = NULL;
691 #endif
692 }
693
hns3_set_rx_cpu_rmap(struct net_device * netdev)694 static int hns3_set_rx_cpu_rmap(struct net_device *netdev)
695 {
696 #ifdef CONFIG_RFS_ACCEL
697 struct hns3_nic_priv *priv = netdev_priv(netdev);
698 struct hns3_enet_tqp_vector *tqp_vector;
699 int i, ret;
700
701 if (!netdev->rx_cpu_rmap) {
702 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num);
703 if (!netdev->rx_cpu_rmap)
704 return -ENOMEM;
705 }
706
707 for (i = 0; i < priv->vector_num; i++) {
708 tqp_vector = &priv->tqp_vector[i];
709 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap,
710 tqp_vector->vector_irq);
711 if (ret) {
712 hns3_free_rx_cpu_rmap(netdev);
713 return ret;
714 }
715 }
716 #endif
717 return 0;
718 }
719
hns3_enable_irqs_and_tqps(struct net_device * netdev)720 static void hns3_enable_irqs_and_tqps(struct net_device *netdev)
721 {
722 struct hns3_nic_priv *priv = netdev_priv(netdev);
723 struct hnae3_handle *h = priv->ae_handle;
724 u16 i;
725
726 for (i = 0; i < priv->vector_num; i++)
727 hns3_irq_enable(&priv->tqp_vector[i]);
728
729 for (i = 0; i < priv->vector_num; i++)
730 hns3_mask_vector_irq(&priv->tqp_vector[i], 1);
731
732 for (i = 0; i < h->kinfo.num_tqps; i++)
733 hns3_tqp_enable(h->kinfo.tqp[i]);
734 }
735
hns3_disable_irqs_and_tqps(struct net_device * netdev)736 static void hns3_disable_irqs_and_tqps(struct net_device *netdev)
737 {
738 struct hns3_nic_priv *priv = netdev_priv(netdev);
739 struct hnae3_handle *h = priv->ae_handle;
740 u16 i;
741
742 for (i = 0; i < h->kinfo.num_tqps; i++)
743 hns3_tqp_disable(h->kinfo.tqp[i]);
744
745 for (i = 0; i < priv->vector_num; i++)
746 hns3_mask_vector_irq(&priv->tqp_vector[i], 0);
747
748 for (i = 0; i < priv->vector_num; i++)
749 hns3_irq_disable(&priv->tqp_vector[i]);
750 }
751
hns3_nic_net_up(struct net_device * netdev)752 static int hns3_nic_net_up(struct net_device *netdev)
753 {
754 struct hns3_nic_priv *priv = netdev_priv(netdev);
755 struct hnae3_handle *h = priv->ae_handle;
756 int ret;
757
758 ret = hns3_nic_reset_all_ring(h);
759 if (ret)
760 return ret;
761
762 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
763
764 hns3_enable_irqs_and_tqps(netdev);
765
766 /* start the ae_dev */
767 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0;
768 if (ret) {
769 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
770 hns3_disable_irqs_and_tqps(netdev);
771 }
772
773 return ret;
774 }
775
hns3_config_xps(struct hns3_nic_priv * priv)776 static void hns3_config_xps(struct hns3_nic_priv *priv)
777 {
778 int i;
779
780 for (i = 0; i < priv->vector_num; i++) {
781 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i];
782 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring;
783
784 while (ring) {
785 int ret;
786
787 ret = netif_set_xps_queue(priv->netdev,
788 &tqp_vector->affinity_mask,
789 ring->tqp->tqp_index);
790 if (ret)
791 netdev_warn(priv->netdev,
792 "set xps queue failed: %d", ret);
793
794 ring = ring->next;
795 }
796 }
797 }
798
hns3_nic_net_open(struct net_device * netdev)799 static int hns3_nic_net_open(struct net_device *netdev)
800 {
801 struct hns3_nic_priv *priv = netdev_priv(netdev);
802 struct hnae3_handle *h = hns3_get_handle(netdev);
803 struct hnae3_knic_private_info *kinfo;
804 int i, ret;
805
806 if (hns3_nic_resetting(netdev))
807 return -EBUSY;
808
809 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
810 netdev_warn(netdev, "net open repeatedly!\n");
811 return 0;
812 }
813
814 netif_carrier_off(netdev);
815
816 ret = hns3_nic_set_real_num_queue(netdev);
817 if (ret)
818 return ret;
819
820 ret = hns3_nic_net_up(netdev);
821 if (ret) {
822 netdev_err(netdev, "net up fail, ret=%d!\n", ret);
823 return ret;
824 }
825
826 kinfo = &h->kinfo;
827 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
828 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]);
829
830 if (h->ae_algo->ops->set_timer_task)
831 h->ae_algo->ops->set_timer_task(priv->ae_handle, true);
832
833 hns3_config_xps(priv);
834
835 netif_dbg(h, drv, netdev, "net open\n");
836
837 return 0;
838 }
839
hns3_reset_tx_queue(struct hnae3_handle * h)840 static void hns3_reset_tx_queue(struct hnae3_handle *h)
841 {
842 struct net_device *ndev = h->kinfo.netdev;
843 struct hns3_nic_priv *priv = netdev_priv(ndev);
844 struct netdev_queue *dev_queue;
845 u32 i;
846
847 for (i = 0; i < h->kinfo.num_tqps; i++) {
848 dev_queue = netdev_get_tx_queue(ndev,
849 priv->ring[i].queue_index);
850 netdev_tx_reset_queue(dev_queue);
851 }
852 }
853
hns3_nic_net_down(struct net_device * netdev)854 static void hns3_nic_net_down(struct net_device *netdev)
855 {
856 struct hns3_nic_priv *priv = netdev_priv(netdev);
857 const struct hnae3_ae_ops *ops;
858
859 hns3_disable_irqs_and_tqps(netdev);
860
861 /* stop ae_dev */
862 ops = priv->ae_handle->ae_algo->ops;
863 if (ops->stop)
864 ops->stop(priv->ae_handle);
865
866 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
867 * during reset process, because driver may not be able
868 * to disable the ring through firmware when downing the netdev.
869 */
870 if (!hns3_nic_resetting(netdev))
871 hns3_clear_all_ring(priv->ae_handle, false);
872
873 hns3_reset_tx_queue(priv->ae_handle);
874 }
875
hns3_nic_net_stop(struct net_device * netdev)876 static int hns3_nic_net_stop(struct net_device *netdev)
877 {
878 struct hns3_nic_priv *priv = netdev_priv(netdev);
879 struct hnae3_handle *h = hns3_get_handle(netdev);
880
881 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
882 return 0;
883
884 netif_dbg(h, drv, netdev, "net stop\n");
885
886 if (h->ae_algo->ops->set_timer_task)
887 h->ae_algo->ops->set_timer_task(priv->ae_handle, false);
888
889 netif_carrier_off(netdev);
890 netif_tx_disable(netdev);
891
892 hns3_nic_net_down(netdev);
893
894 return 0;
895 }
896
hns3_nic_uc_sync(struct net_device * netdev,const unsigned char * addr)897 static int hns3_nic_uc_sync(struct net_device *netdev,
898 const unsigned char *addr)
899 {
900 struct hnae3_handle *h = hns3_get_handle(netdev);
901
902 if (h->ae_algo->ops->add_uc_addr)
903 return h->ae_algo->ops->add_uc_addr(h, addr);
904
905 return 0;
906 }
907
hns3_nic_uc_unsync(struct net_device * netdev,const unsigned char * addr)908 static int hns3_nic_uc_unsync(struct net_device *netdev,
909 const unsigned char *addr)
910 {
911 struct hnae3_handle *h = hns3_get_handle(netdev);
912
913 /* need ignore the request of removing device address, because
914 * we store the device address and other addresses of uc list
915 * in the function's mac filter list.
916 */
917 if (ether_addr_equal(addr, netdev->dev_addr))
918 return 0;
919
920 if (h->ae_algo->ops->rm_uc_addr)
921 return h->ae_algo->ops->rm_uc_addr(h, addr);
922
923 return 0;
924 }
925
hns3_nic_mc_sync(struct net_device * netdev,const unsigned char * addr)926 static int hns3_nic_mc_sync(struct net_device *netdev,
927 const unsigned char *addr)
928 {
929 struct hnae3_handle *h = hns3_get_handle(netdev);
930
931 if (h->ae_algo->ops->add_mc_addr)
932 return h->ae_algo->ops->add_mc_addr(h, addr);
933
934 return 0;
935 }
936
hns3_nic_mc_unsync(struct net_device * netdev,const unsigned char * addr)937 static int hns3_nic_mc_unsync(struct net_device *netdev,
938 const unsigned char *addr)
939 {
940 struct hnae3_handle *h = hns3_get_handle(netdev);
941
942 if (h->ae_algo->ops->rm_mc_addr)
943 return h->ae_algo->ops->rm_mc_addr(h, addr);
944
945 return 0;
946 }
947
hns3_get_netdev_flags(struct net_device * netdev)948 static u8 hns3_get_netdev_flags(struct net_device *netdev)
949 {
950 u8 flags = 0;
951
952 if (netdev->flags & IFF_PROMISC)
953 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE;
954 else if (netdev->flags & IFF_ALLMULTI)
955 flags = HNAE3_USER_MPE;
956
957 return flags;
958 }
959
hns3_nic_set_rx_mode(struct net_device * netdev)960 static void hns3_nic_set_rx_mode(struct net_device *netdev)
961 {
962 struct hnae3_handle *h = hns3_get_handle(netdev);
963 u8 new_flags;
964
965 new_flags = hns3_get_netdev_flags(netdev);
966
967 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync);
968 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync);
969
970 /* User mode Promisc mode enable and vlan filtering is disabled to
971 * let all packets in.
972 */
973 h->netdev_flags = new_flags;
974 hns3_request_update_promisc_mode(h);
975 }
976
hns3_request_update_promisc_mode(struct hnae3_handle * handle)977 void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
978 {
979 const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
980
981 if (ops->request_update_promisc_mode)
982 ops->request_update_promisc_mode(handle);
983 }
984
hns3_tx_spare_space(struct hns3_enet_ring * ring)985 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
986 {
987 struct hns3_tx_spare *tx_spare = ring->tx_spare;
988 u32 ntc, ntu;
989
990 /* This smp_load_acquire() pairs with smp_store_release() in
991 * hns3_tx_spare_update() called in tx desc cleaning process.
992 */
993 ntc = smp_load_acquire(&tx_spare->last_to_clean);
994 ntu = tx_spare->next_to_use;
995
996 if (ntc > ntu)
997 return ntc - ntu - 1;
998
999 /* The free tx buffer is divided into two part, so pick the
1000 * larger one.
1001 */
1002 return max(ntc, tx_spare->len - ntu) - 1;
1003 }
1004
hns3_tx_spare_update(struct hns3_enet_ring * ring)1005 static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
1006 {
1007 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1008
1009 if (!tx_spare ||
1010 tx_spare->last_to_clean == tx_spare->next_to_clean)
1011 return;
1012
1013 /* This smp_store_release() pairs with smp_load_acquire() in
1014 * hns3_tx_spare_space() called in xmit process.
1015 */
1016 smp_store_release(&tx_spare->last_to_clean,
1017 tx_spare->next_to_clean);
1018 }
1019
hns3_can_use_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1020 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
1021 struct sk_buff *skb,
1022 u32 space)
1023 {
1024 u32 len = skb->len <= ring->tx_copybreak ? skb->len :
1025 skb_headlen(skb);
1026
1027 if (len > ring->tx_copybreak)
1028 return false;
1029
1030 if (ALIGN(len, dma_get_cache_alignment()) > space) {
1031 hns3_ring_stats_update(ring, tx_spare_full);
1032 return false;
1033 }
1034
1035 return true;
1036 }
1037
hns3_can_use_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 space)1038 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
1039 struct sk_buff *skb,
1040 u32 space)
1041 {
1042 if (skb->len <= ring->tx_copybreak || !tx_sgl ||
1043 (!skb_has_frag_list(skb) &&
1044 skb_shinfo(skb)->nr_frags < tx_sgl))
1045 return false;
1046
1047 if (space < HNS3_MAX_SGL_SIZE) {
1048 hns3_ring_stats_update(ring, tx_spare_full);
1049 return false;
1050 }
1051
1052 return true;
1053 }
1054
hns3_init_tx_spare_buffer(struct hns3_enet_ring * ring)1055 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
1056 {
1057 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
1058 struct net_device *netdev = ring_to_netdev(ring);
1059 struct hns3_nic_priv *priv = netdev_priv(netdev);
1060 struct hns3_tx_spare *tx_spare;
1061 struct page *page;
1062 dma_addr_t dma;
1063 int order;
1064
1065 if (!alloc_size)
1066 goto not_init;
1067
1068 order = get_order(alloc_size);
1069 if (order > MAX_PAGE_ORDER) {
1070 if (net_ratelimit())
1071 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
1072 goto not_init;
1073 }
1074
1075 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
1076 GFP_KERNEL);
1077 if (!tx_spare) {
1078 /* The driver still work without the tx spare buffer */
1079 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
1080 goto devm_kzalloc_error;
1081 }
1082
1083 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
1084 GFP_KERNEL, order);
1085 if (!page) {
1086 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
1087 goto alloc_pages_error;
1088 }
1089
1090 dma = dma_map_page(ring_to_dev(ring), page, 0,
1091 PAGE_SIZE << order, DMA_TO_DEVICE);
1092 if (dma_mapping_error(ring_to_dev(ring), dma)) {
1093 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
1094 goto dma_mapping_error;
1095 }
1096
1097 tx_spare->dma = dma;
1098 tx_spare->buf = page_address(page);
1099 tx_spare->len = PAGE_SIZE << order;
1100 ring->tx_spare = tx_spare;
1101 ring->tx_copybreak = priv->tx_copybreak;
1102 return;
1103
1104 dma_mapping_error:
1105 put_page(page);
1106 alloc_pages_error:
1107 devm_kfree(ring_to_dev(ring), tx_spare);
1108 devm_kzalloc_error:
1109 ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
1110 not_init:
1111 /* When driver init or reset_init, the ring->tx_spare is always NULL;
1112 * but when called from hns3_set_ringparam, it's usually not NULL, and
1113 * will be restored if hns3_init_all_ring() failed. So it's safe to set
1114 * ring->tx_spare to NULL here.
1115 */
1116 ring->tx_spare = NULL;
1117 }
1118
1119 /* Use hns3_tx_spare_space() to make sure there is enough buffer
1120 * before calling below function to allocate tx buffer.
1121 */
hns3_tx_spare_alloc(struct hns3_enet_ring * ring,unsigned int size,dma_addr_t * dma,u32 * cb_len)1122 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
1123 unsigned int size, dma_addr_t *dma,
1124 u32 *cb_len)
1125 {
1126 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1127 u32 ntu = tx_spare->next_to_use;
1128
1129 size = ALIGN(size, dma_get_cache_alignment());
1130 *cb_len = size;
1131
1132 /* Tx spare buffer wraps back here because the end of
1133 * freed tx buffer is not enough.
1134 */
1135 if (ntu + size > tx_spare->len) {
1136 *cb_len += (tx_spare->len - ntu);
1137 ntu = 0;
1138 }
1139
1140 tx_spare->next_to_use = ntu + size;
1141 if (tx_spare->next_to_use == tx_spare->len)
1142 tx_spare->next_to_use = 0;
1143
1144 *dma = tx_spare->dma + ntu;
1145
1146 return tx_spare->buf + ntu;
1147 }
1148
hns3_tx_spare_rollback(struct hns3_enet_ring * ring,u32 len)1149 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
1150 {
1151 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1152
1153 if (len > tx_spare->next_to_use) {
1154 len -= tx_spare->next_to_use;
1155 tx_spare->next_to_use = tx_spare->len - len;
1156 } else {
1157 tx_spare->next_to_use -= len;
1158 }
1159 }
1160
hns3_tx_spare_reclaim_cb(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)1161 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
1162 struct hns3_desc_cb *cb)
1163 {
1164 struct hns3_tx_spare *tx_spare = ring->tx_spare;
1165 u32 ntc = tx_spare->next_to_clean;
1166 u32 len = cb->length;
1167
1168 tx_spare->next_to_clean += len;
1169
1170 if (tx_spare->next_to_clean >= tx_spare->len) {
1171 tx_spare->next_to_clean -= tx_spare->len;
1172
1173 if (tx_spare->next_to_clean) {
1174 ntc = 0;
1175 len = tx_spare->next_to_clean;
1176 }
1177 }
1178
1179 /* This tx spare buffer is only really reclaimed after calling
1180 * hns3_tx_spare_update(), so it is still safe to use the info in
1181 * the tx buffer to do the dma sync or sg unmapping after
1182 * tx_spare->next_to_clean is moved forword.
1183 */
1184 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
1185 dma_addr_t dma = tx_spare->dma + ntc;
1186
1187 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
1188 DMA_TO_DEVICE);
1189 } else {
1190 struct sg_table *sgt = tx_spare->buf + ntc;
1191
1192 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
1193 DMA_TO_DEVICE);
1194 }
1195 }
1196
hns3_set_tso(struct sk_buff * skb,u32 * paylen_fdop_ol4cs,u16 * mss,u32 * type_cs_vlan_tso,u32 * send_bytes)1197 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
1198 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
1199 {
1200 u32 l4_offset, hdr_len;
1201 union l3_hdr_info l3;
1202 union l4_hdr_info l4;
1203 u32 l4_paylen;
1204 int ret;
1205
1206 if (!skb_is_gso(skb))
1207 return 0;
1208
1209 ret = skb_cow_head(skb, 0);
1210 if (unlikely(ret < 0))
1211 return ret;
1212
1213 l3.hdr = skb_network_header(skb);
1214 l4.hdr = skb_transport_header(skb);
1215
1216 /* Software should clear the IPv4's checksum field when tso is
1217 * needed.
1218 */
1219 if (l3.v4->version == 4)
1220 l3.v4->check = 0;
1221
1222 /* tunnel packet */
1223 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1224 SKB_GSO_GRE_CSUM |
1225 SKB_GSO_UDP_TUNNEL |
1226 SKB_GSO_UDP_TUNNEL_CSUM)) {
1227 /* reset l3&l4 pointers from outer to inner headers */
1228 l3.hdr = skb_inner_network_header(skb);
1229 l4.hdr = skb_inner_transport_header(skb);
1230
1231 /* Software should clear the IPv4's checksum field when
1232 * tso is needed.
1233 */
1234 if (l3.v4->version == 4)
1235 l3.v4->check = 0;
1236 }
1237
1238 /* normal or tunnel packet */
1239 l4_offset = l4.hdr - skb->data;
1240
1241 /* remove payload length from inner pseudo checksum when tso */
1242 l4_paylen = skb->len - l4_offset;
1243
1244 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
1245 hdr_len = sizeof(*l4.udp) + l4_offset;
1246 csum_replace_by_diff(&l4.udp->check,
1247 (__force __wsum)htonl(l4_paylen));
1248 } else {
1249 hdr_len = (l4.tcp->doff << 2) + l4_offset;
1250 csum_replace_by_diff(&l4.tcp->check,
1251 (__force __wsum)htonl(l4_paylen));
1252 }
1253
1254 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
1255
1256 /* find the txbd field values */
1257 *paylen_fdop_ol4cs = skb->len - hdr_len;
1258 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
1259
1260 /* offload outer UDP header checksum */
1261 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1262 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1);
1263
1264 /* get MSS for TSO */
1265 *mss = skb_shinfo(skb)->gso_size;
1266
1267 trace_hns3_tso(skb);
1268
1269 return 0;
1270 }
1271
hns3_get_l4_protocol(struct sk_buff * skb,u8 * ol4_proto,u8 * il4_proto)1272 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto,
1273 u8 *il4_proto)
1274 {
1275 union l3_hdr_info l3;
1276 unsigned char *l4_hdr;
1277 unsigned char *exthdr;
1278 u8 l4_proto_tmp;
1279 __be16 frag_off;
1280
1281 /* find outer header point */
1282 l3.hdr = skb_network_header(skb);
1283 l4_hdr = skb_transport_header(skb);
1284
1285 if (skb->protocol == htons(ETH_P_IPV6)) {
1286 exthdr = l3.hdr + sizeof(*l3.v6);
1287 l4_proto_tmp = l3.v6->nexthdr;
1288 if (l4_hdr != exthdr)
1289 ipv6_skip_exthdr(skb, exthdr - skb->data,
1290 &l4_proto_tmp, &frag_off);
1291 } else if (skb->protocol == htons(ETH_P_IP)) {
1292 l4_proto_tmp = l3.v4->protocol;
1293 } else {
1294 return -EINVAL;
1295 }
1296
1297 *ol4_proto = l4_proto_tmp;
1298
1299 /* tunnel packet */
1300 if (!skb->encapsulation) {
1301 *il4_proto = 0;
1302 return 0;
1303 }
1304
1305 /* find inner header point */
1306 l3.hdr = skb_inner_network_header(skb);
1307 l4_hdr = skb_inner_transport_header(skb);
1308
1309 if (l3.v6->version == 6) {
1310 exthdr = l3.hdr + sizeof(*l3.v6);
1311 l4_proto_tmp = l3.v6->nexthdr;
1312 if (l4_hdr != exthdr)
1313 ipv6_skip_exthdr(skb, exthdr - skb->data,
1314 &l4_proto_tmp, &frag_off);
1315 } else if (l3.v4->version == 4) {
1316 l4_proto_tmp = l3.v4->protocol;
1317 }
1318
1319 *il4_proto = l4_proto_tmp;
1320
1321 return 0;
1322 }
1323
1324 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL
1325 * and it is udp packet, which has a dest port as the IANA assigned.
1326 * the hardware is expected to do the checksum offload, but the
1327 * hardware will not do the checksum offload when udp dest port is
1328 * 4789, 4790 or 6081.
1329 */
hns3_tunnel_csum_bug(struct sk_buff * skb)1330 static bool hns3_tunnel_csum_bug(struct sk_buff *skb)
1331 {
1332 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1333 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
1334 union l4_hdr_info l4;
1335
1336 /* device version above V3(include V3), the hardware can
1337 * do this checksum offload.
1338 */
1339 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
1340 return false;
1341
1342 l4.hdr = skb_transport_header(skb);
1343
1344 if (!(!skb->encapsulation &&
1345 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) ||
1346 l4.udp->dest == htons(GENEVE_UDP_PORT) ||
1347 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT))))
1348 return false;
1349
1350 return true;
1351 }
1352
hns3_set_outer_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u32 * ol_type_vlan_len_msec)1353 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1354 u32 *ol_type_vlan_len_msec)
1355 {
1356 u32 l2_len, l3_len, l4_len;
1357 unsigned char *il2_hdr;
1358 union l3_hdr_info l3;
1359 union l4_hdr_info l4;
1360
1361 l3.hdr = skb_network_header(skb);
1362 l4.hdr = skb_transport_header(skb);
1363
1364 /* compute OL2 header size, defined in 2 Bytes */
1365 l2_len = l3.hdr - skb->data;
1366 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1);
1367
1368 /* compute OL3 header size, defined in 4 Bytes */
1369 l3_len = l4.hdr - l3.hdr;
1370 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2);
1371
1372 il2_hdr = skb_inner_mac_header(skb);
1373 /* compute OL4 header size, defined in 4 Bytes */
1374 l4_len = il2_hdr - l4.hdr;
1375 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2);
1376
1377 /* define outer network header type */
1378 if (skb->protocol == htons(ETH_P_IP)) {
1379 if (skb_is_gso(skb))
1380 hns3_set_field(*ol_type_vlan_len_msec,
1381 HNS3_TXD_OL3T_S,
1382 HNS3_OL3T_IPV4_CSUM);
1383 else
1384 hns3_set_field(*ol_type_vlan_len_msec,
1385 HNS3_TXD_OL3T_S,
1386 HNS3_OL3T_IPV4_NO_CSUM);
1387 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1388 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S,
1389 HNS3_OL3T_IPV6);
1390 }
1391
1392 if (ol4_proto == IPPROTO_UDP)
1393 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1394 HNS3_TUN_MAC_IN_UDP);
1395 else if (ol4_proto == IPPROTO_GRE)
1396 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S,
1397 HNS3_TUN_NVGRE);
1398 }
1399
hns3_set_l3_type(struct sk_buff * skb,union l3_hdr_info l3,u32 * type_cs_vlan_tso)1400 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3,
1401 u32 *type_cs_vlan_tso)
1402 {
1403 if (l3.v4->version == 4) {
1404 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1405 HNS3_L3T_IPV4);
1406
1407 /* the stack computes the IP header already, the only time we
1408 * need the hardware to recompute it is in the case of TSO.
1409 */
1410 if (skb_is_gso(skb))
1411 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1);
1412 } else if (l3.v6->version == 6) {
1413 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S,
1414 HNS3_L3T_IPV6);
1415 }
1416 }
1417
hns3_set_l4_csum_length(struct sk_buff * skb,union l4_hdr_info l4,u32 l4_proto,u32 * type_cs_vlan_tso)1418 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4,
1419 u32 l4_proto, u32 *type_cs_vlan_tso)
1420 {
1421 /* compute inner(/normal) L4 header size, defined in 4 Bytes */
1422 switch (l4_proto) {
1423 case IPPROTO_TCP:
1424 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1425 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1426 HNS3_L4T_TCP);
1427 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1428 l4.tcp->doff);
1429 break;
1430 case IPPROTO_UDP:
1431 if (hns3_tunnel_csum_bug(skb)) {
1432 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN);
1433
1434 return ret ? ret : skb_checksum_help(skb);
1435 }
1436
1437 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1438 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1439 HNS3_L4T_UDP);
1440 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1441 (sizeof(struct udphdr) >> 2));
1442 break;
1443 case IPPROTO_SCTP:
1444 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1);
1445 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S,
1446 HNS3_L4T_SCTP);
1447 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S,
1448 (sizeof(struct sctphdr) >> 2));
1449 break;
1450 default:
1451 /* drop the skb tunnel packet if hardware don't support,
1452 * because hardware can't calculate csum when TSO.
1453 */
1454 if (skb_is_gso(skb))
1455 return -EDOM;
1456
1457 /* the stack computes the IP header already,
1458 * driver calculate l4 checksum when not TSO.
1459 */
1460 return skb_checksum_help(skb);
1461 }
1462
1463 return 0;
1464 }
1465
hns3_set_l2l3l4(struct sk_buff * skb,u8 ol4_proto,u8 il4_proto,u32 * type_cs_vlan_tso,u32 * ol_type_vlan_len_msec)1466 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto,
1467 u8 il4_proto, u32 *type_cs_vlan_tso,
1468 u32 *ol_type_vlan_len_msec)
1469 {
1470 unsigned char *l2_hdr = skb->data;
1471 u32 l4_proto = ol4_proto;
1472 union l4_hdr_info l4;
1473 union l3_hdr_info l3;
1474 u32 l2_len, l3_len;
1475
1476 l4.hdr = skb_transport_header(skb);
1477 l3.hdr = skb_network_header(skb);
1478
1479 /* handle encapsulation skb */
1480 if (skb->encapsulation) {
1481 /* If this is a not UDP/GRE encapsulation skb */
1482 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) {
1483 /* drop the skb tunnel packet if hardware don't support,
1484 * because hardware can't calculate csum when TSO.
1485 */
1486 if (skb_is_gso(skb))
1487 return -EDOM;
1488
1489 /* the stack computes the IP header already,
1490 * driver calculate l4 checksum when not TSO.
1491 */
1492 return skb_checksum_help(skb);
1493 }
1494
1495 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec);
1496
1497 /* switch to inner header */
1498 l2_hdr = skb_inner_mac_header(skb);
1499 l3.hdr = skb_inner_network_header(skb);
1500 l4.hdr = skb_inner_transport_header(skb);
1501 l4_proto = il4_proto;
1502 }
1503
1504 hns3_set_l3_type(skb, l3, type_cs_vlan_tso);
1505
1506 /* compute inner(/normal) L2 header size, defined in 2 Bytes */
1507 l2_len = l3.hdr - l2_hdr;
1508 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1);
1509
1510 /* compute inner(/normal) L3 header size, defined in 4 Bytes */
1511 l3_len = l4.hdr - l3.hdr;
1512 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2);
1513
1514 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso);
1515 }
1516
hns3_handle_vtags(struct hns3_enet_ring * tx_ring,struct sk_buff * skb)1517 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
1518 struct sk_buff *skb)
1519 {
1520 struct hnae3_handle *handle = tx_ring->tqp->handle;
1521 struct hnae3_ae_dev *ae_dev;
1522 struct vlan_ethhdr *vhdr;
1523 int rc;
1524
1525 if (!(skb->protocol == htons(ETH_P_8021Q) ||
1526 skb_vlan_tag_present(skb)))
1527 return 0;
1528
1529 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert
1530 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it
1531 * will cause RAS error.
1532 */
1533 ae_dev = hns3_get_ae_dev(handle);
1534 if (unlikely(skb_vlan_tagged_multi(skb) &&
1535 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
1536 handle->port_base_vlan_state ==
1537 HNAE3_PORT_BASE_VLAN_ENABLE))
1538 return -EINVAL;
1539
1540 if (skb->protocol == htons(ETH_P_8021Q) &&
1541 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1542 /* When HW VLAN acceleration is turned off, and the stack
1543 * sets the protocol to 802.1q, the driver just need to
1544 * set the protocol to the encapsulated ethertype.
1545 */
1546 skb->protocol = vlan_get_protocol(skb);
1547 return 0;
1548 }
1549
1550 if (skb_vlan_tag_present(skb)) {
1551 /* Based on hw strategy, use out_vtag in two layer tag case,
1552 * and use inner_vtag in one tag case.
1553 */
1554 if (skb->protocol == htons(ETH_P_8021Q) &&
1555 handle->port_base_vlan_state ==
1556 HNAE3_PORT_BASE_VLAN_DISABLE)
1557 rc = HNS3_OUTER_VLAN_TAG;
1558 else
1559 rc = HNS3_INNER_VLAN_TAG;
1560
1561 skb->protocol = vlan_get_protocol(skb);
1562 return rc;
1563 }
1564
1565 rc = skb_cow_head(skb, 0);
1566 if (unlikely(rc < 0))
1567 return rc;
1568
1569 vhdr = skb_vlan_eth_hdr(skb);
1570 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
1571 & VLAN_PRIO_MASK);
1572
1573 skb->protocol = vlan_get_protocol(skb);
1574 return 0;
1575 }
1576
1577 /* check if the hardware is capable of checksum offloading */
hns3_check_hw_tx_csum(struct sk_buff * skb)1578 static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
1579 {
1580 struct hns3_nic_priv *priv = netdev_priv(skb->dev);
1581
1582 /* Kindly note, due to backward compatibility of the TX descriptor,
1583 * HW checksum of the non-IP packets and GSO packets is handled at
1584 * different place in the following code
1585 */
1586 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) ||
1587 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
1588 return false;
1589
1590 return true;
1591 }
1592
1593 struct hns3_desc_param {
1594 u32 paylen_ol4cs;
1595 u32 ol_type_vlan_len_msec;
1596 u32 type_cs_vlan_tso;
1597 u16 mss_hw_csum;
1598 u16 inner_vtag;
1599 u16 out_vtag;
1600 };
1601
hns3_init_desc_data(struct sk_buff * skb,struct hns3_desc_param * pa)1602 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
1603 {
1604 pa->paylen_ol4cs = skb->len;
1605 pa->ol_type_vlan_len_msec = 0;
1606 pa->type_cs_vlan_tso = 0;
1607 pa->mss_hw_csum = 0;
1608 pa->inner_vtag = 0;
1609 pa->out_vtag = 0;
1610 }
1611
hns3_handle_vlan_info(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_param * param)1612 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
1613 struct sk_buff *skb,
1614 struct hns3_desc_param *param)
1615 {
1616 int ret;
1617
1618 ret = hns3_handle_vtags(ring, skb);
1619 if (unlikely(ret < 0)) {
1620 hns3_ring_stats_update(ring, tx_vlan_err);
1621 return ret;
1622 } else if (ret == HNS3_INNER_VLAN_TAG) {
1623 param->inner_vtag = skb_vlan_tag_get(skb);
1624 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1625 VLAN_PRIO_MASK;
1626 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
1627 } else if (ret == HNS3_OUTER_VLAN_TAG) {
1628 param->out_vtag = skb_vlan_tag_get(skb);
1629 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
1630 VLAN_PRIO_MASK;
1631 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
1632 1);
1633 }
1634 return 0;
1635 }
1636
hns3_handle_csum_partial(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,struct hns3_desc_param * param)1637 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
1638 struct sk_buff *skb,
1639 struct hns3_desc_cb *desc_cb,
1640 struct hns3_desc_param *param)
1641 {
1642 u8 ol4_proto, il4_proto;
1643 int ret;
1644
1645 if (hns3_check_hw_tx_csum(skb)) {
1646 /* set checksum start and offset, defined in 2 Bytes */
1647 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
1648 skb_checksum_start_offset(skb) >> 1);
1649 hns3_set_field(param->ol_type_vlan_len_msec,
1650 HNS3_TXD_CSUM_OFFSET_S,
1651 skb->csum_offset >> 1);
1652 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
1653 return 0;
1654 }
1655
1656 skb_reset_mac_len(skb);
1657
1658 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
1659 if (unlikely(ret < 0)) {
1660 hns3_ring_stats_update(ring, tx_l4_proto_err);
1661 return ret;
1662 }
1663
1664 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
1665 ¶m->type_cs_vlan_tso,
1666 ¶m->ol_type_vlan_len_msec);
1667 if (unlikely(ret < 0)) {
1668 hns3_ring_stats_update(ring, tx_l2l3l4_err);
1669 return ret;
1670 }
1671
1672 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum,
1673 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes);
1674 if (unlikely(ret < 0)) {
1675 hns3_ring_stats_update(ring, tx_tso_err);
1676 return ret;
1677 }
1678 return 0;
1679 }
1680
hns3_fill_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc * desc,struct hns3_desc_cb * desc_cb)1681 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
1682 struct sk_buff *skb, struct hns3_desc *desc,
1683 struct hns3_desc_cb *desc_cb)
1684 {
1685 struct hns3_desc_param param;
1686 int ret;
1687
1688 hns3_init_desc_data(skb, ¶m);
1689 ret = hns3_handle_vlan_info(ring, skb, ¶m);
1690 if (unlikely(ret < 0))
1691 return ret;
1692
1693 desc_cb->send_bytes = skb->len;
1694
1695 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1696 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m);
1697 if (ret)
1698 return ret;
1699 }
1700
1701 /* Set txbd */
1702 desc->tx.ol_type_vlan_len_msec =
1703 cpu_to_le32(param.ol_type_vlan_len_msec);
1704 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
1705 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs);
1706 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
1707 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
1708 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
1709
1710 return 0;
1711 }
1712
hns3_fill_desc(struct hns3_enet_ring * ring,dma_addr_t dma,unsigned int size)1713 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
1714 unsigned int size)
1715 {
1716 #define HNS3_LIKELY_BD_NUM 1
1717
1718 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
1719 unsigned int frag_buf_num, k;
1720 int sizeoflast;
1721
1722 if (likely(size <= HNS3_MAX_BD_SIZE)) {
1723 desc->addr = cpu_to_le64(dma);
1724 desc->tx.send_size = cpu_to_le16(size);
1725 desc->tx.bdtp_fe_sc_vld_ra_ri =
1726 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1727
1728 trace_hns3_tx_desc(ring, ring->next_to_use);
1729 ring_ptr_move_fw(ring, next_to_use);
1730 return HNS3_LIKELY_BD_NUM;
1731 }
1732
1733 frag_buf_num = hns3_tx_bd_count(size);
1734 sizeoflast = size % HNS3_MAX_BD_SIZE;
1735 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
1736
1737 /* When frag size is bigger than hardware limit, split this frag */
1738 for (k = 0; k < frag_buf_num; k++) {
1739 /* now, fill the descriptor */
1740 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k);
1741 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ?
1742 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE);
1743 desc->tx.bdtp_fe_sc_vld_ra_ri =
1744 cpu_to_le16(BIT(HNS3_TXD_VLD_B));
1745
1746 trace_hns3_tx_desc(ring, ring->next_to_use);
1747 /* move ring pointer to next */
1748 ring_ptr_move_fw(ring, next_to_use);
1749
1750 desc = &ring->desc[ring->next_to_use];
1751 }
1752
1753 return frag_buf_num;
1754 }
1755
hns3_map_and_fill_desc(struct hns3_enet_ring * ring,void * priv,unsigned int type)1756 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
1757 unsigned int type)
1758 {
1759 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
1760 struct device *dev = ring_to_dev(ring);
1761 unsigned int size;
1762 dma_addr_t dma;
1763
1764 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
1765 struct sk_buff *skb = (struct sk_buff *)priv;
1766
1767 size = skb_headlen(skb);
1768 if (!size)
1769 return 0;
1770
1771 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
1772 } else if (type & DESC_TYPE_BOUNCE_HEAD) {
1773 /* Head data has been filled in hns3_handle_tx_bounce(),
1774 * just return 0 here.
1775 */
1776 return 0;
1777 } else {
1778 skb_frag_t *frag = (skb_frag_t *)priv;
1779
1780 size = skb_frag_size(frag);
1781 if (!size)
1782 return 0;
1783
1784 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
1785 }
1786
1787 if (unlikely(dma_mapping_error(dev, dma))) {
1788 hns3_ring_stats_update(ring, sw_err_cnt);
1789 return -ENOMEM;
1790 }
1791
1792 desc_cb->priv = priv;
1793 desc_cb->length = size;
1794 desc_cb->dma = dma;
1795 desc_cb->type = type;
1796
1797 return hns3_fill_desc(ring, dma, size);
1798 }
1799
hns3_skb_bd_num(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num)1800 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1801 unsigned int bd_num)
1802 {
1803 unsigned int size;
1804 int i;
1805
1806 size = skb_headlen(skb);
1807 while (size > HNS3_MAX_BD_SIZE) {
1808 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1809 size -= HNS3_MAX_BD_SIZE;
1810
1811 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1812 return bd_num;
1813 }
1814
1815 if (size) {
1816 bd_size[bd_num++] = size;
1817 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1818 return bd_num;
1819 }
1820
1821 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1822 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1823 size = skb_frag_size(frag);
1824 if (!size)
1825 continue;
1826
1827 while (size > HNS3_MAX_BD_SIZE) {
1828 bd_size[bd_num++] = HNS3_MAX_BD_SIZE;
1829 size -= HNS3_MAX_BD_SIZE;
1830
1831 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1832 return bd_num;
1833 }
1834
1835 bd_size[bd_num++] = size;
1836 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1837 return bd_num;
1838 }
1839
1840 return bd_num;
1841 }
1842
hns3_tx_bd_num(struct sk_buff * skb,unsigned int * bd_size,u8 max_non_tso_bd_num,unsigned int bd_num,unsigned int recursion_level)1843 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
1844 u8 max_non_tso_bd_num, unsigned int bd_num,
1845 unsigned int recursion_level)
1846 {
1847 #define HNS3_MAX_RECURSION_LEVEL 24
1848
1849 struct sk_buff *frag_skb;
1850
1851 /* If the total len is within the max bd limit */
1852 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level &&
1853 !skb_has_frag_list(skb) &&
1854 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num))
1855 return skb_shinfo(skb)->nr_frags + 1U;
1856
1857 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL))
1858 return UINT_MAX;
1859
1860 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
1861 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
1862 return bd_num;
1863
1864 skb_walk_frags(skb, frag_skb) {
1865 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num,
1866 bd_num, recursion_level + 1);
1867 if (bd_num > HNS3_MAX_TSO_BD_NUM)
1868 return bd_num;
1869 }
1870
1871 return bd_num;
1872 }
1873
hns3_gso_hdr_len(struct sk_buff * skb)1874 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
1875 {
1876 if (!skb->encapsulation)
1877 return skb_tcp_all_headers(skb);
1878
1879 return skb_inner_tcp_all_headers(skb);
1880 }
1881
1882 /* HW need every continuous max_non_tso_bd_num buffer data to be larger
1883 * than MSS, we simplify it by ensuring skb_headlen + the first continuous
1884 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss,
1885 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger
1886 * than MSS except the last max_non_tso_bd_num - 1 frags.
1887 */
hns3_skb_need_linearized(struct sk_buff * skb,unsigned int * bd_size,unsigned int bd_num,u8 max_non_tso_bd_num)1888 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size,
1889 unsigned int bd_num, u8 max_non_tso_bd_num)
1890 {
1891 unsigned int tot_len = 0;
1892 unsigned int i;
1893
1894 for (i = 0; i < max_non_tso_bd_num - 1U; i++)
1895 tot_len += bd_size[i];
1896
1897 /* ensure the first max_non_tso_bd_num frags is greater than
1898 * mss + header
1899 */
1900 if (tot_len + bd_size[max_non_tso_bd_num - 1U] <
1901 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb))
1902 return true;
1903
1904 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater
1905 * than mss except the last one.
1906 */
1907 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) {
1908 tot_len -= bd_size[i];
1909 tot_len += bd_size[i + max_non_tso_bd_num - 1U];
1910
1911 if (tot_len < skb_shinfo(skb)->gso_size)
1912 return true;
1913 }
1914
1915 return false;
1916 }
1917
hns3_shinfo_pack(struct skb_shared_info * shinfo,__u32 * size)1918 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
1919 {
1920 u32 i;
1921
1922 for (i = 0; i < MAX_SKB_FRAGS; i++)
1923 size[i] = skb_frag_size(&shinfo->frags[i]);
1924 }
1925
hns3_skb_linearize(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int bd_num)1926 static int hns3_skb_linearize(struct hns3_enet_ring *ring,
1927 struct sk_buff *skb,
1928 unsigned int bd_num)
1929 {
1930 /* 'bd_num == UINT_MAX' means the skb' fraglist has a
1931 * recursion level of over HNS3_MAX_RECURSION_LEVEL.
1932 */
1933 if (bd_num == UINT_MAX) {
1934 hns3_ring_stats_update(ring, over_max_recursion);
1935 return -ENOMEM;
1936 }
1937
1938 /* The skb->len has exceeded the hw limitation, linearization
1939 * will not help.
1940 */
1941 if (skb->len > HNS3_MAX_TSO_SIZE ||
1942 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
1943 hns3_ring_stats_update(ring, hw_limitation);
1944 return -ENOMEM;
1945 }
1946
1947 if (__skb_linearize(skb)) {
1948 hns3_ring_stats_update(ring, sw_err_cnt);
1949 return -ENOMEM;
1950 }
1951
1952 return 0;
1953 }
1954
hns3_nic_maybe_stop_tx(struct hns3_enet_ring * ring,struct net_device * netdev,struct sk_buff * skb)1955 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring,
1956 struct net_device *netdev,
1957 struct sk_buff *skb)
1958 {
1959 struct hns3_nic_priv *priv = netdev_priv(netdev);
1960 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num;
1961 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U];
1962 unsigned int bd_num;
1963
1964 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0);
1965 if (unlikely(bd_num > max_non_tso_bd_num)) {
1966 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) &&
1967 !hns3_skb_need_linearized(skb, bd_size, bd_num,
1968 max_non_tso_bd_num)) {
1969 trace_hns3_over_max_bd(skb);
1970 goto out;
1971 }
1972
1973 if (hns3_skb_linearize(ring, skb, bd_num))
1974 return -ENOMEM;
1975
1976 bd_num = hns3_tx_bd_count(skb->len);
1977
1978 hns3_ring_stats_update(ring, tx_copy);
1979 }
1980
1981 out:
1982 if (likely(ring_space(ring) >= bd_num))
1983 return bd_num;
1984
1985 netif_stop_subqueue(netdev, ring->queue_index);
1986 smp_mb(); /* Memory barrier before checking ring_space */
1987
1988 /* Start queue in case hns3_clean_tx_ring has just made room
1989 * available and has not seen the queue stopped state performed
1990 * by netif_stop_subqueue above.
1991 */
1992 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) &&
1993 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
1994 netif_start_subqueue(netdev, ring->queue_index);
1995 return bd_num;
1996 }
1997
1998 hns3_ring_stats_update(ring, tx_busy);
1999
2000 return -EBUSY;
2001 }
2002
hns3_clear_desc(struct hns3_enet_ring * ring,int next_to_use_orig)2003 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
2004 {
2005 struct device *dev = ring_to_dev(ring);
2006 unsigned int i;
2007
2008 for (i = 0; i < ring->desc_num; i++) {
2009 struct hns3_desc *desc = &ring->desc[ring->next_to_use];
2010 struct hns3_desc_cb *desc_cb;
2011
2012 memset(desc, 0, sizeof(*desc));
2013
2014 /* check if this is where we started */
2015 if (ring->next_to_use == next_to_use_orig)
2016 break;
2017
2018 /* rollback one */
2019 ring_ptr_move_bw(ring, next_to_use);
2020
2021 desc_cb = &ring->desc_cb[ring->next_to_use];
2022
2023 if (!desc_cb->dma)
2024 continue;
2025
2026 /* unmap the descriptor dma address */
2027 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
2028 dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
2029 DMA_TO_DEVICE);
2030 else if (desc_cb->type &
2031 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
2032 hns3_tx_spare_rollback(ring, desc_cb->length);
2033 else if (desc_cb->length)
2034 dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
2035 DMA_TO_DEVICE);
2036
2037 desc_cb->length = 0;
2038 desc_cb->dma = 0;
2039 desc_cb->type = DESC_TYPE_UNKNOWN;
2040 }
2041 }
2042
hns3_fill_skb_to_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,unsigned int type)2043 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
2044 struct sk_buff *skb, unsigned int type)
2045 {
2046 struct sk_buff *frag_skb;
2047 int i, ret, bd_num = 0;
2048
2049 ret = hns3_map_and_fill_desc(ring, skb, type);
2050 if (unlikely(ret < 0))
2051 return ret;
2052
2053 bd_num += ret;
2054
2055 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2056 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2057
2058 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
2059 if (unlikely(ret < 0))
2060 return ret;
2061
2062 bd_num += ret;
2063 }
2064
2065 skb_walk_frags(skb, frag_skb) {
2066 ret = hns3_fill_skb_to_desc(ring, frag_skb,
2067 DESC_TYPE_FRAGLIST_SKB);
2068 if (unlikely(ret < 0))
2069 return ret;
2070
2071 bd_num += ret;
2072 }
2073
2074 return bd_num;
2075 }
2076
hns3_tx_push_bd(struct hns3_enet_ring * ring,int num)2077 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
2078 {
2079 #define HNS3_BYTES_PER_64BIT 8
2080
2081 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
2082 int offset = 0;
2083
2084 /* make sure everything is visible to device before
2085 * excuting tx push or updating doorbell
2086 */
2087 dma_wmb();
2088
2089 do {
2090 int idx = (ring->next_to_use - num + ring->desc_num) %
2091 ring->desc_num;
2092
2093 u64_stats_update_begin(&ring->syncp);
2094 ring->stats.tx_push++;
2095 u64_stats_update_end(&ring->syncp);
2096 memcpy(&desc[offset], &ring->desc[idx],
2097 sizeof(struct hns3_desc));
2098 offset++;
2099 } while (--num);
2100
2101 __iowrite64_copy(ring->tqp->mem_base, desc,
2102 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
2103 HNS3_BYTES_PER_64BIT);
2104 }
2105
hns3_tx_mem_doorbell(struct hns3_enet_ring * ring)2106 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
2107 {
2108 #define HNS3_MEM_DOORBELL_OFFSET 64
2109
2110 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
2111
2112 /* make sure everything is visible to device before
2113 * excuting tx push or updating doorbell
2114 */
2115 dma_wmb();
2116
2117 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
2118 &bd_num, 1);
2119 u64_stats_update_begin(&ring->syncp);
2120 ring->stats.tx_mem_doorbell += ring->pending_buf;
2121 u64_stats_update_end(&ring->syncp);
2122 }
2123
hns3_tx_doorbell(struct hns3_enet_ring * ring,int num,bool doorbell)2124 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
2125 bool doorbell)
2126 {
2127 struct net_device *netdev = ring_to_netdev(ring);
2128 struct hns3_nic_priv *priv = netdev_priv(netdev);
2129
2130 /* when tx push is enabled, the packet whose number of BD below
2131 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
2132 */
2133 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
2134 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
2135 /* This smp_store_release() pairs with smp_load_acquire() in
2136 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit
2137 * is updated.
2138 */
2139 smp_store_release(&ring->last_to_use, ring->next_to_use);
2140 hns3_tx_push_bd(ring, num);
2141 return;
2142 }
2143
2144 ring->pending_buf += num;
2145
2146 if (!doorbell) {
2147 hns3_ring_stats_update(ring, tx_more);
2148 return;
2149 }
2150
2151 /* This smp_store_release() pairs with smp_load_acquire() in
2152 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
2153 */
2154 smp_store_release(&ring->last_to_use, ring->next_to_use);
2155
2156 if (ring->tqp->mem_base)
2157 hns3_tx_mem_doorbell(ring);
2158 else
2159 writel(ring->pending_buf,
2160 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
2161
2162 ring->pending_buf = 0;
2163 }
2164
hns3_tsyn(struct net_device * netdev,struct sk_buff * skb,struct hns3_desc * desc)2165 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
2166 struct hns3_desc *desc)
2167 {
2168 struct hnae3_handle *h = hns3_get_handle(netdev);
2169
2170 if (!(h->ae_algo->ops->set_tx_hwts_info &&
2171 h->ae_algo->ops->set_tx_hwts_info(h, skb)))
2172 return;
2173
2174 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
2175 }
2176
hns3_handle_tx_bounce(struct hns3_enet_ring * ring,struct sk_buff * skb)2177 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
2178 struct sk_buff *skb)
2179 {
2180 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2181 unsigned int type = DESC_TYPE_BOUNCE_HEAD;
2182 unsigned int size = skb_headlen(skb);
2183 dma_addr_t dma;
2184 int bd_num = 0;
2185 u32 cb_len;
2186 void *buf;
2187 int ret;
2188
2189 if (skb->len <= ring->tx_copybreak) {
2190 size = skb->len;
2191 type = DESC_TYPE_BOUNCE_ALL;
2192 }
2193
2194 /* hns3_can_use_tx_bounce() is called to ensure the below
2195 * function can always return the tx buffer.
2196 */
2197 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
2198
2199 ret = skb_copy_bits(skb, 0, buf, size);
2200 if (unlikely(ret < 0)) {
2201 hns3_tx_spare_rollback(ring, cb_len);
2202 hns3_ring_stats_update(ring, copy_bits_err);
2203 return ret;
2204 }
2205
2206 desc_cb->priv = skb;
2207 desc_cb->length = cb_len;
2208 desc_cb->dma = dma;
2209 desc_cb->type = type;
2210
2211 bd_num += hns3_fill_desc(ring, dma, size);
2212
2213 if (type == DESC_TYPE_BOUNCE_HEAD) {
2214 ret = hns3_fill_skb_to_desc(ring, skb,
2215 DESC_TYPE_BOUNCE_HEAD);
2216 if (unlikely(ret < 0))
2217 return ret;
2218
2219 bd_num += ret;
2220 }
2221
2222 dma_sync_single_for_device(ring_to_dev(ring), dma, size,
2223 DMA_TO_DEVICE);
2224
2225 hns3_ring_stats_update(ring, tx_bounce);
2226
2227 return bd_num;
2228 }
2229
hns3_handle_tx_sgl(struct hns3_enet_ring * ring,struct sk_buff * skb)2230 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
2231 struct sk_buff *skb)
2232 {
2233 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2234 u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
2235 struct sg_table *sgt;
2236 int bd_num = 0;
2237 dma_addr_t dma;
2238 u32 cb_len, i;
2239 int nents;
2240
2241 if (skb_has_frag_list(skb))
2242 nfrag = HNS3_MAX_TSO_BD_NUM;
2243
2244 /* hns3_can_use_tx_sgl() is called to ensure the below
2245 * function can always return the tx buffer.
2246 */
2247 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
2248 &dma, &cb_len);
2249
2250 /* scatterlist follows by the sg table */
2251 sgt->sgl = (struct scatterlist *)(sgt + 1);
2252 sg_init_table(sgt->sgl, nfrag);
2253 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
2254 if (unlikely(nents < 0)) {
2255 hns3_tx_spare_rollback(ring, cb_len);
2256 hns3_ring_stats_update(ring, skb2sgl_err);
2257 return -ENOMEM;
2258 }
2259
2260 sgt->orig_nents = nents;
2261 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
2262 DMA_TO_DEVICE);
2263 if (unlikely(!sgt->nents)) {
2264 hns3_tx_spare_rollback(ring, cb_len);
2265 hns3_ring_stats_update(ring, map_sg_err);
2266 return -ENOMEM;
2267 }
2268
2269 desc_cb->priv = skb;
2270 desc_cb->length = cb_len;
2271 desc_cb->dma = dma;
2272 desc_cb->type = DESC_TYPE_SGL_SKB;
2273
2274 for (i = 0; i < sgt->nents; i++)
2275 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
2276 sg_dma_len(sgt->sgl + i));
2277 hns3_ring_stats_update(ring, tx_sgl);
2278
2279 return bd_num;
2280 }
2281
hns3_handle_desc_filling(struct hns3_enet_ring * ring,struct sk_buff * skb)2282 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
2283 struct sk_buff *skb)
2284 {
2285 u32 space;
2286
2287 if (!ring->tx_spare)
2288 goto out;
2289
2290 space = hns3_tx_spare_space(ring);
2291
2292 if (hns3_can_use_tx_sgl(ring, skb, space))
2293 return hns3_handle_tx_sgl(ring, skb);
2294
2295 if (hns3_can_use_tx_bounce(ring, skb, space))
2296 return hns3_handle_tx_bounce(ring, skb);
2297
2298 out:
2299 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
2300 }
2301
hns3_handle_skb_desc(struct hns3_enet_ring * ring,struct sk_buff * skb,struct hns3_desc_cb * desc_cb,int next_to_use_head)2302 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring,
2303 struct sk_buff *skb,
2304 struct hns3_desc_cb *desc_cb,
2305 int next_to_use_head)
2306 {
2307 int ret;
2308
2309 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use],
2310 desc_cb);
2311 if (unlikely(ret < 0))
2312 goto fill_err;
2313
2314 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is
2315 * zero, which is unlikely, and 'ret > 0' means how many tx desc
2316 * need to be notified to the hw.
2317 */
2318 ret = hns3_handle_desc_filling(ring, skb);
2319 if (likely(ret > 0))
2320 return ret;
2321
2322 fill_err:
2323 hns3_clear_desc(ring, next_to_use_head);
2324 return ret;
2325 }
2326
hns3_nic_net_xmit(struct sk_buff * skb,struct net_device * netdev)2327 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
2328 {
2329 struct hns3_nic_priv *priv = netdev_priv(netdev);
2330 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
2331 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
2332 struct netdev_queue *dev_queue;
2333 int pre_ntu, ret;
2334 bool doorbell;
2335
2336 /* Hardware can only handle short frames above 32 bytes */
2337 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
2338 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2339
2340 hns3_ring_stats_update(ring, sw_err_cnt);
2341
2342 return NETDEV_TX_OK;
2343 }
2344
2345 /* Prefetch the data used later */
2346 prefetch(skb->data);
2347
2348 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb);
2349 if (unlikely(ret <= 0)) {
2350 if (ret == -EBUSY) {
2351 hns3_tx_doorbell(ring, 0, true);
2352 return NETDEV_TX_BUSY;
2353 }
2354
2355 hns3_rl_err(netdev, "xmit error: %d!\n", ret);
2356 goto out_err_tx_ok;
2357 }
2358
2359 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use);
2360 if (unlikely(ret <= 0))
2361 goto out_err_tx_ok;
2362
2363 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
2364 (ring->desc_num - 1);
2365
2366 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
2367 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
2368
2369 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
2370 cpu_to_le16(BIT(HNS3_TXD_FE_B));
2371 trace_hns3_tx_desc(ring, pre_ntu);
2372
2373 skb_tx_timestamp(skb);
2374
2375 /* Complete translate all packets */
2376 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
2377 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes,
2378 netdev_xmit_more());
2379 hns3_tx_doorbell(ring, ret, doorbell);
2380
2381 return NETDEV_TX_OK;
2382
2383 out_err_tx_ok:
2384 dev_kfree_skb_any(skb);
2385 hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
2386 return NETDEV_TX_OK;
2387 }
2388
hns3_nic_net_set_mac_address(struct net_device * netdev,void * p)2389 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p)
2390 {
2391 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN];
2392 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN];
2393 struct hnae3_handle *h = hns3_get_handle(netdev);
2394 struct sockaddr *mac_addr = p;
2395 int ret;
2396
2397 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data))
2398 return -EADDRNOTAVAIL;
2399
2400 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) {
2401 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2402 netdev_info(netdev, "already using mac address %s\n",
2403 format_mac_addr_sa);
2404 return 0;
2405 }
2406
2407 /* For VF device, if there is a perm_addr, then the user will not
2408 * be allowed to change the address.
2409 */
2410 if (!hns3_is_phys_func(h->pdev) &&
2411 !is_zero_ether_addr(netdev->perm_addr)) {
2412 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr);
2413 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data);
2414 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n",
2415 format_mac_addr_perm, format_mac_addr_sa);
2416 return -EPERM;
2417 }
2418
2419 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false);
2420 if (ret) {
2421 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret);
2422 return ret;
2423 }
2424
2425 eth_hw_addr_set(netdev, mac_addr->sa_data);
2426
2427 return 0;
2428 }
2429
hns3_nic_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)2430 static int hns3_nic_do_ioctl(struct net_device *netdev,
2431 struct ifreq *ifr, int cmd)
2432 {
2433 struct hnae3_handle *h = hns3_get_handle(netdev);
2434
2435 if (!netif_running(netdev))
2436 return -EINVAL;
2437
2438 if (!h->ae_algo->ops->do_ioctl)
2439 return -EOPNOTSUPP;
2440
2441 return h->ae_algo->ops->do_ioctl(h, ifr, cmd);
2442 }
2443
hns3_nic_hwtstamp_get(struct net_device * netdev,struct kernel_hwtstamp_config * config)2444 static int hns3_nic_hwtstamp_get(struct net_device *netdev,
2445 struct kernel_hwtstamp_config *config)
2446 {
2447 struct hnae3_handle *h = hns3_get_handle(netdev);
2448
2449 if (!netif_running(netdev))
2450 return -EINVAL;
2451
2452 if (!h->ae_algo->ops->hwtstamp_get)
2453 return -EOPNOTSUPP;
2454
2455 return h->ae_algo->ops->hwtstamp_get(h, config);
2456 }
2457
hns3_nic_hwtstamp_set(struct net_device * netdev,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)2458 static int hns3_nic_hwtstamp_set(struct net_device *netdev,
2459 struct kernel_hwtstamp_config *config,
2460 struct netlink_ext_ack *extack)
2461 {
2462 struct hnae3_handle *h = hns3_get_handle(netdev);
2463
2464 if (!netif_running(netdev))
2465 return -EINVAL;
2466
2467 if (!h->ae_algo->ops->hwtstamp_set)
2468 return -EOPNOTSUPP;
2469
2470 return h->ae_algo->ops->hwtstamp_set(h, config, extack);
2471 }
2472
hns3_nic_set_features(struct net_device * netdev,netdev_features_t features)2473 static int hns3_nic_set_features(struct net_device *netdev,
2474 netdev_features_t features)
2475 {
2476 netdev_features_t changed = netdev->features ^ features;
2477 struct hns3_nic_priv *priv = netdev_priv(netdev);
2478 struct hnae3_handle *h = priv->ae_handle;
2479 bool enable;
2480 int ret;
2481
2482 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) {
2483 enable = !!(features & NETIF_F_GRO_HW);
2484 ret = h->ae_algo->ops->set_gro_en(h, enable);
2485 if (ret)
2486 return ret;
2487 }
2488
2489 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
2490 h->ae_algo->ops->enable_hw_strip_rxvtag) {
2491 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
2492 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable);
2493 if (ret)
2494 return ret;
2495 }
2496
2497 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) {
2498 enable = !!(features & NETIF_F_NTUPLE);
2499 h->ae_algo->ops->enable_fd(h, enable);
2500 }
2501
2502 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) &&
2503 h->ae_algo->ops->cls_flower_active(h)) {
2504 netdev_err(netdev,
2505 "there are offloaded TC filters active, cannot disable HW TC offload\n");
2506 return -EINVAL;
2507 }
2508
2509 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
2510 h->ae_algo->ops->enable_vlan_filter) {
2511 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
2512 ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
2513 if (ret)
2514 return ret;
2515 }
2516
2517 return 0;
2518 }
2519
hns3_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2520 static netdev_features_t hns3_features_check(struct sk_buff *skb,
2521 struct net_device *dev,
2522 netdev_features_t features)
2523 {
2524 #define HNS3_MAX_HDR_LEN 480U
2525 #define HNS3_MAX_L4_HDR_LEN 60U
2526
2527 size_t len;
2528
2529 if (skb->ip_summed != CHECKSUM_PARTIAL)
2530 return features;
2531
2532 if (skb->encapsulation)
2533 len = skb_inner_transport_offset(skb);
2534 else
2535 len = skb_transport_offset(skb);
2536
2537 /* Assume L4 is 60 byte as TCP is the only protocol with a
2538 * a flexible value, and it's max len is 60 bytes.
2539 */
2540 len += HNS3_MAX_L4_HDR_LEN;
2541
2542 /* Hardware only supports checksum on the skb with a max header
2543 * len of 480 bytes.
2544 */
2545 if (len > HNS3_MAX_HDR_LEN)
2546 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2547
2548 return features;
2549 }
2550
hns3_fetch_stats(struct rtnl_link_stats64 * stats,struct hns3_enet_ring * ring,bool is_tx)2551 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats,
2552 struct hns3_enet_ring *ring, bool is_tx)
2553 {
2554 struct ring_stats ring_stats;
2555 unsigned int start;
2556
2557 do {
2558 start = u64_stats_fetch_begin(&ring->syncp);
2559 ring_stats = ring->stats;
2560 } while (u64_stats_fetch_retry(&ring->syncp, start));
2561
2562 if (is_tx) {
2563 stats->tx_bytes += ring_stats.tx_bytes;
2564 stats->tx_packets += ring_stats.tx_pkts;
2565 stats->tx_dropped += ring_stats.sw_err_cnt;
2566 stats->tx_dropped += ring_stats.tx_vlan_err;
2567 stats->tx_dropped += ring_stats.tx_l4_proto_err;
2568 stats->tx_dropped += ring_stats.tx_l2l3l4_err;
2569 stats->tx_dropped += ring_stats.tx_tso_err;
2570 stats->tx_dropped += ring_stats.over_max_recursion;
2571 stats->tx_dropped += ring_stats.hw_limitation;
2572 stats->tx_dropped += ring_stats.copy_bits_err;
2573 stats->tx_dropped += ring_stats.skb2sgl_err;
2574 stats->tx_dropped += ring_stats.map_sg_err;
2575 stats->tx_errors += ring_stats.sw_err_cnt;
2576 stats->tx_errors += ring_stats.tx_vlan_err;
2577 stats->tx_errors += ring_stats.tx_l4_proto_err;
2578 stats->tx_errors += ring_stats.tx_l2l3l4_err;
2579 stats->tx_errors += ring_stats.tx_tso_err;
2580 stats->tx_errors += ring_stats.over_max_recursion;
2581 stats->tx_errors += ring_stats.hw_limitation;
2582 stats->tx_errors += ring_stats.copy_bits_err;
2583 stats->tx_errors += ring_stats.skb2sgl_err;
2584 stats->tx_errors += ring_stats.map_sg_err;
2585 } else {
2586 stats->rx_bytes += ring_stats.rx_bytes;
2587 stats->rx_packets += ring_stats.rx_pkts;
2588 stats->rx_dropped += ring_stats.l2_err;
2589 stats->rx_errors += ring_stats.l2_err;
2590 stats->rx_errors += ring_stats.l3l4_csum_err;
2591 stats->rx_crc_errors += ring_stats.l2_err;
2592 stats->multicast += ring_stats.rx_multicast;
2593 stats->rx_length_errors += ring_stats.err_pkt_len;
2594 }
2595 }
2596
hns3_nic_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)2597 static void hns3_nic_get_stats64(struct net_device *netdev,
2598 struct rtnl_link_stats64 *stats)
2599 {
2600 struct hns3_nic_priv *priv = netdev_priv(netdev);
2601 int queue_num = priv->ae_handle->kinfo.num_tqps;
2602 struct hnae3_handle *handle = priv->ae_handle;
2603 struct rtnl_link_stats64 ring_total_stats;
2604 struct hns3_enet_ring *ring;
2605 int idx;
2606
2607 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
2608 return;
2609
2610 handle->ae_algo->ops->update_stats(handle);
2611
2612 memset(&ring_total_stats, 0, sizeof(ring_total_stats));
2613 for (idx = 0; idx < queue_num; idx++) {
2614 /* fetch the tx stats */
2615 ring = &priv->ring[idx];
2616 hns3_fetch_stats(&ring_total_stats, ring, true);
2617
2618 /* fetch the rx stats */
2619 ring = &priv->ring[idx + queue_num];
2620 hns3_fetch_stats(&ring_total_stats, ring, false);
2621 }
2622
2623 stats->tx_bytes = ring_total_stats.tx_bytes;
2624 stats->tx_packets = ring_total_stats.tx_packets;
2625 stats->rx_bytes = ring_total_stats.rx_bytes;
2626 stats->rx_packets = ring_total_stats.rx_packets;
2627
2628 stats->rx_errors = ring_total_stats.rx_errors;
2629 stats->multicast = ring_total_stats.multicast;
2630 stats->rx_length_errors = ring_total_stats.rx_length_errors;
2631 stats->rx_crc_errors = ring_total_stats.rx_crc_errors;
2632 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
2633
2634 stats->tx_errors = ring_total_stats.tx_errors;
2635 stats->rx_dropped = ring_total_stats.rx_dropped;
2636 stats->tx_dropped = ring_total_stats.tx_dropped;
2637 stats->collisions = netdev->stats.collisions;
2638 stats->rx_over_errors = netdev->stats.rx_over_errors;
2639 stats->rx_frame_errors = netdev->stats.rx_frame_errors;
2640 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors;
2641 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors;
2642 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors;
2643 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors;
2644 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors;
2645 stats->tx_window_errors = netdev->stats.tx_window_errors;
2646 stats->rx_compressed = netdev->stats.rx_compressed;
2647 stats->tx_compressed = netdev->stats.tx_compressed;
2648 }
2649
hns3_setup_tc(struct net_device * netdev,void * type_data)2650 static int hns3_setup_tc(struct net_device *netdev, void *type_data)
2651 {
2652 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
2653 struct hnae3_knic_private_info *kinfo;
2654 u8 tc = mqprio_qopt->qopt.num_tc;
2655 u16 mode = mqprio_qopt->mode;
2656 u8 hw = mqprio_qopt->qopt.hw;
2657 struct hnae3_handle *h;
2658
2659 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS &&
2660 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0)))
2661 return -EOPNOTSUPP;
2662
2663 if (tc > HNAE3_MAX_TC)
2664 return -EINVAL;
2665
2666 if (!netdev)
2667 return -EINVAL;
2668
2669 h = hns3_get_handle(netdev);
2670 kinfo = &h->kinfo;
2671
2672 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc);
2673
2674 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ?
2675 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP;
2676 }
2677
hns3_setup_tc_cls_flower(struct hns3_nic_priv * priv,struct flow_cls_offload * flow)2678 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv,
2679 struct flow_cls_offload *flow)
2680 {
2681 struct hnae3_handle *h = hns3_get_handle(priv->netdev);
2682
2683 switch (flow->command) {
2684 case FLOW_CLS_REPLACE:
2685 if (h->ae_algo->ops->add_cls_flower)
2686 return h->ae_algo->ops->add_cls_flower(h, flow);
2687 break;
2688 case FLOW_CLS_DESTROY:
2689 if (h->ae_algo->ops->del_cls_flower)
2690 return h->ae_algo->ops->del_cls_flower(h, flow);
2691 break;
2692 default:
2693 break;
2694 }
2695
2696 return -EOPNOTSUPP;
2697 }
2698
hns3_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)2699 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2700 void *cb_priv)
2701 {
2702 struct hns3_nic_priv *priv = cb_priv;
2703
2704 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
2705 return -EOPNOTSUPP;
2706
2707 switch (type) {
2708 case TC_SETUP_CLSFLOWER:
2709 return hns3_setup_tc_cls_flower(priv, type_data);
2710 default:
2711 return -EOPNOTSUPP;
2712 }
2713 }
2714
2715 static LIST_HEAD(hns3_block_cb_list);
2716
hns3_nic_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)2717 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type,
2718 void *type_data)
2719 {
2720 struct hns3_nic_priv *priv = netdev_priv(dev);
2721 int ret;
2722
2723 switch (type) {
2724 case TC_SETUP_QDISC_MQPRIO:
2725 ret = hns3_setup_tc(dev, type_data);
2726 break;
2727 case TC_SETUP_BLOCK:
2728 ret = flow_block_cb_setup_simple(type_data,
2729 &hns3_block_cb_list,
2730 hns3_setup_tc_block_cb,
2731 priv, priv, true);
2732 break;
2733 default:
2734 return -EOPNOTSUPP;
2735 }
2736
2737 return ret;
2738 }
2739
hns3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2740 static int hns3_vlan_rx_add_vid(struct net_device *netdev,
2741 __be16 proto, u16 vid)
2742 {
2743 struct hnae3_handle *h = hns3_get_handle(netdev);
2744 int ret = -EIO;
2745
2746 if (h->ae_algo->ops->set_vlan_filter)
2747 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
2748
2749 return ret;
2750 }
2751
hns3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2752 static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
2753 __be16 proto, u16 vid)
2754 {
2755 struct hnae3_handle *h = hns3_get_handle(netdev);
2756 int ret = -EIO;
2757
2758 if (h->ae_algo->ops->set_vlan_filter)
2759 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
2760
2761 return ret;
2762 }
2763
hns3_ndo_set_vf_vlan(struct net_device * netdev,int vf,u16 vlan,u8 qos,__be16 vlan_proto)2764 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
2765 u8 qos, __be16 vlan_proto)
2766 {
2767 struct hnae3_handle *h = hns3_get_handle(netdev);
2768 int ret = -EIO;
2769
2770 netif_dbg(h, drv, netdev,
2771 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
2772 vf, vlan, qos, ntohs(vlan_proto));
2773
2774 if (h->ae_algo->ops->set_vf_vlan_filter)
2775 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
2776 qos, vlan_proto);
2777
2778 return ret;
2779 }
2780
hns3_set_vf_spoofchk(struct net_device * netdev,int vf,bool enable)2781 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable)
2782 {
2783 struct hnae3_handle *handle = hns3_get_handle(netdev);
2784
2785 if (hns3_nic_resetting(netdev))
2786 return -EBUSY;
2787
2788 if (!handle->ae_algo->ops->set_vf_spoofchk)
2789 return -EOPNOTSUPP;
2790
2791 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable);
2792 }
2793
hns3_set_vf_trust(struct net_device * netdev,int vf,bool enable)2794 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable)
2795 {
2796 struct hnae3_handle *handle = hns3_get_handle(netdev);
2797
2798 if (!handle->ae_algo->ops->set_vf_trust)
2799 return -EOPNOTSUPP;
2800
2801 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable);
2802 }
2803
hns3_nic_change_mtu(struct net_device * netdev,int new_mtu)2804 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu)
2805 {
2806 struct hnae3_handle *h = hns3_get_handle(netdev);
2807 int ret;
2808
2809 if (hns3_nic_resetting(netdev))
2810 return -EBUSY;
2811
2812 if (!h->ae_algo->ops->set_mtu)
2813 return -EOPNOTSUPP;
2814
2815 netif_dbg(h, drv, netdev,
2816 "change mtu from %u to %d\n", netdev->mtu, new_mtu);
2817
2818 ret = h->ae_algo->ops->set_mtu(h, new_mtu);
2819 if (ret)
2820 netdev_err(netdev, "failed to change MTU in hardware %d\n",
2821 ret);
2822 else
2823 WRITE_ONCE(netdev->mtu, new_mtu);
2824
2825 return ret;
2826 }
2827
hns3_dump_timeout_queue(struct net_device * ndev,unsigned int txqueue)2828 static bool hns3_dump_timeout_queue(struct net_device *ndev,
2829 unsigned int txqueue)
2830 {
2831 unsigned int timedout_ms;
2832 struct netdev_queue *q;
2833
2834 q = netdev_get_tx_queue(ndev, txqueue);
2835 timedout_ms = netif_xmit_timeout_ms(q);
2836 if (timedout_ms) {
2837 #ifdef CONFIG_BQL
2838 struct dql *dql = &q->dql;
2839
2840 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
2841 dql->last_obj_cnt, dql->num_queued,
2842 dql->adj_limit, dql->num_completed);
2843 #endif
2844 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
2845 q->state, timedout_ms);
2846 return true;
2847 }
2848
2849 return false;
2850 }
2851
hns3_dump_queue_stats(struct net_device * ndev,struct hns3_enet_ring * tx_ring,int timeout_queue)2852 static void hns3_dump_queue_stats(struct net_device *ndev,
2853 struct hns3_enet_ring *tx_ring,
2854 int timeout_queue)
2855 {
2856 struct napi_struct *napi = &tx_ring->tqp_vector->napi;
2857 struct hns3_nic_priv *priv = netdev_priv(ndev);
2858
2859 netdev_info(ndev,
2860 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n",
2861 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use,
2862 tx_ring->next_to_clean, napi->state);
2863
2864 netdev_info(ndev,
2865 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n",
2866 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes,
2867 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf);
2868
2869 netdev_info(ndev,
2870 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n",
2871 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more,
2872 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy);
2873
2874 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n",
2875 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell);
2876 }
2877
hns3_dump_queue_reg(struct net_device * ndev,struct hns3_enet_ring * tx_ring)2878 static void hns3_dump_queue_reg(struct net_device *ndev,
2879 struct hns3_enet_ring *tx_ring)
2880 {
2881 netdev_info(ndev,
2882 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n",
2883 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG),
2884 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG),
2885 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG),
2886 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG),
2887 readl(tx_ring->tqp_vector->mask_addr));
2888 netdev_info(ndev,
2889 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n",
2890 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG),
2891 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG),
2892 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG),
2893 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG),
2894 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG),
2895 hns3_tqp_read_reg(tx_ring,
2896 HNS3_RING_TX_RING_EBD_OFFSET_REG));
2897 }
2898
hns3_get_tx_timeo_queue_info(struct net_device * ndev,unsigned int txqueue)2899 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev,
2900 unsigned int txqueue)
2901 {
2902 struct hns3_nic_priv *priv = netdev_priv(ndev);
2903 struct hnae3_handle *h = hns3_get_handle(ndev);
2904 struct hns3_enet_ring *tx_ring;
2905
2906 if (txqueue >= h->kinfo.num_tqps ||
2907 !hns3_dump_timeout_queue(ndev, txqueue)) {
2908 netdev_info(ndev,
2909 "no netdev TX timeout queue found, timeout count: %llu\n",
2910 priv->tx_timeout_count);
2911 return false;
2912 }
2913
2914 priv->tx_timeout_count++;
2915
2916 tx_ring = &priv->ring[txqueue];
2917 hns3_dump_queue_stats(ndev, tx_ring, txqueue);
2918
2919 /* When mac received many pause frames continuous, it's unable to send
2920 * packets, which may cause tx timeout
2921 */
2922 if (h->ae_algo->ops->get_mac_stats) {
2923 struct hns3_mac_stats mac_stats;
2924
2925 h->ae_algo->ops->get_mac_stats(h, &mac_stats);
2926 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
2927 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
2928 }
2929
2930 hns3_dump_queue_reg(ndev, tx_ring);
2931
2932 return true;
2933 }
2934
hns3_nic_net_timeout(struct net_device * ndev,unsigned int txqueue)2935 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue)
2936 {
2937 struct hns3_nic_priv *priv = netdev_priv(ndev);
2938 struct hnae3_handle *h = priv->ae_handle;
2939
2940 if (!hns3_get_tx_timeo_queue_info(ndev, txqueue))
2941 return;
2942
2943 /* request the reset, and let the hclge to determine
2944 * which reset level should be done
2945 */
2946 if (h->ae_algo->ops->reset_event)
2947 h->ae_algo->ops->reset_event(h->pdev, h);
2948 }
2949
2950 #ifdef CONFIG_RFS_ACCEL
hns3_rx_flow_steer(struct net_device * dev,const struct sk_buff * skb,u16 rxq_index,u32 flow_id)2951 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
2952 u16 rxq_index, u32 flow_id)
2953 {
2954 struct hnae3_handle *h = hns3_get_handle(dev);
2955 struct flow_keys fkeys;
2956
2957 if (!h->ae_algo->ops->add_arfs_entry)
2958 return -EOPNOTSUPP;
2959
2960 if (skb->encapsulation)
2961 return -EPROTONOSUPPORT;
2962
2963 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0))
2964 return -EPROTONOSUPPORT;
2965
2966 if ((fkeys.basic.n_proto != htons(ETH_P_IP) &&
2967 fkeys.basic.n_proto != htons(ETH_P_IPV6)) ||
2968 (fkeys.basic.ip_proto != IPPROTO_TCP &&
2969 fkeys.basic.ip_proto != IPPROTO_UDP))
2970 return -EPROTONOSUPPORT;
2971
2972 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys);
2973 }
2974 #endif
2975
hns3_nic_get_vf_config(struct net_device * ndev,int vf,struct ifla_vf_info * ivf)2976 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf,
2977 struct ifla_vf_info *ivf)
2978 {
2979 struct hnae3_handle *h = hns3_get_handle(ndev);
2980
2981 if (!h->ae_algo->ops->get_vf_config)
2982 return -EOPNOTSUPP;
2983
2984 return h->ae_algo->ops->get_vf_config(h, vf, ivf);
2985 }
2986
hns3_nic_set_vf_link_state(struct net_device * ndev,int vf,int link_state)2987 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf,
2988 int link_state)
2989 {
2990 struct hnae3_handle *h = hns3_get_handle(ndev);
2991
2992 if (!h->ae_algo->ops->set_vf_link_state)
2993 return -EOPNOTSUPP;
2994
2995 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state);
2996 }
2997
hns3_nic_set_vf_rate(struct net_device * ndev,int vf,int min_tx_rate,int max_tx_rate)2998 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf,
2999 int min_tx_rate, int max_tx_rate)
3000 {
3001 struct hnae3_handle *h = hns3_get_handle(ndev);
3002
3003 if (!h->ae_algo->ops->set_vf_rate)
3004 return -EOPNOTSUPP;
3005
3006 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate,
3007 false);
3008 }
3009
hns3_nic_set_vf_mac(struct net_device * netdev,int vf_id,u8 * mac)3010 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
3011 {
3012 struct hnae3_handle *h = hns3_get_handle(netdev);
3013 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
3014
3015 if (!h->ae_algo->ops->set_vf_mac)
3016 return -EOPNOTSUPP;
3017
3018 if (is_multicast_ether_addr(mac)) {
3019 hnae3_format_mac_addr(format_mac_addr, mac);
3020 netdev_err(netdev,
3021 "Invalid MAC:%s specified. Could not set MAC\n",
3022 format_mac_addr);
3023 return -EINVAL;
3024 }
3025
3026 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac);
3027 }
3028
3029 #define HNS3_INVALID_DSCP 0xff
3030 #define HNS3_DSCP_SHIFT 2
3031
hns3_get_skb_dscp(struct sk_buff * skb)3032 static u8 hns3_get_skb_dscp(struct sk_buff *skb)
3033 {
3034 __be16 protocol = skb->protocol;
3035 u8 dscp = HNS3_INVALID_DSCP;
3036
3037 if (protocol == htons(ETH_P_8021Q))
3038 protocol = vlan_get_protocol(skb);
3039
3040 if (protocol == htons(ETH_P_IP))
3041 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT;
3042 else if (protocol == htons(ETH_P_IPV6))
3043 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT;
3044
3045 return dscp;
3046 }
3047
hns3_nic_select_queue(struct net_device * netdev,struct sk_buff * skb,struct net_device * sb_dev)3048 static u16 hns3_nic_select_queue(struct net_device *netdev,
3049 struct sk_buff *skb,
3050 struct net_device *sb_dev)
3051 {
3052 struct hnae3_handle *h = hns3_get_handle(netdev);
3053 u8 dscp;
3054
3055 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP ||
3056 !h->ae_algo->ops->get_dscp_prio)
3057 goto out;
3058
3059 dscp = hns3_get_skb_dscp(skb);
3060 if (unlikely(dscp >= HNAE3_MAX_DSCP))
3061 goto out;
3062
3063 skb->priority = h->kinfo.dscp_prio[dscp];
3064 if (skb->priority == HNAE3_PRIO_ID_INVALID)
3065 skb->priority = 0;
3066
3067 out:
3068 return netdev_pick_tx(netdev, skb, sb_dev);
3069 }
3070
3071 static const struct net_device_ops hns3_nic_netdev_ops = {
3072 .ndo_open = hns3_nic_net_open,
3073 .ndo_stop = hns3_nic_net_stop,
3074 .ndo_start_xmit = hns3_nic_net_xmit,
3075 .ndo_tx_timeout = hns3_nic_net_timeout,
3076 .ndo_set_mac_address = hns3_nic_net_set_mac_address,
3077 .ndo_eth_ioctl = hns3_nic_do_ioctl,
3078 .ndo_change_mtu = hns3_nic_change_mtu,
3079 .ndo_set_features = hns3_nic_set_features,
3080 .ndo_features_check = hns3_features_check,
3081 .ndo_get_stats64 = hns3_nic_get_stats64,
3082 .ndo_setup_tc = hns3_nic_setup_tc,
3083 .ndo_set_rx_mode = hns3_nic_set_rx_mode,
3084 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid,
3085 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid,
3086 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan,
3087 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk,
3088 .ndo_set_vf_trust = hns3_set_vf_trust,
3089 #ifdef CONFIG_RFS_ACCEL
3090 .ndo_rx_flow_steer = hns3_rx_flow_steer,
3091 #endif
3092 .ndo_get_vf_config = hns3_nic_get_vf_config,
3093 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state,
3094 .ndo_set_vf_rate = hns3_nic_set_vf_rate,
3095 .ndo_set_vf_mac = hns3_nic_set_vf_mac,
3096 .ndo_select_queue = hns3_nic_select_queue,
3097 .ndo_hwtstamp_get = hns3_nic_hwtstamp_get,
3098 .ndo_hwtstamp_set = hns3_nic_hwtstamp_set,
3099 };
3100
hns3_is_phys_func(struct pci_dev * pdev)3101 bool hns3_is_phys_func(struct pci_dev *pdev)
3102 {
3103 u32 dev_id = pdev->device;
3104
3105 switch (dev_id) {
3106 case HNAE3_DEV_ID_GE:
3107 case HNAE3_DEV_ID_25GE:
3108 case HNAE3_DEV_ID_25GE_RDMA:
3109 case HNAE3_DEV_ID_25GE_RDMA_MACSEC:
3110 case HNAE3_DEV_ID_50GE_RDMA:
3111 case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
3112 case HNAE3_DEV_ID_100G_RDMA_MACSEC:
3113 case HNAE3_DEV_ID_200G_RDMA:
3114 return true;
3115 case HNAE3_DEV_ID_VF:
3116 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
3117 return false;
3118 default:
3119 dev_warn(&pdev->dev, "un-recognized pci device-id %u",
3120 dev_id);
3121 }
3122
3123 return false;
3124 }
3125
hns3_disable_sriov(struct pci_dev * pdev)3126 static void hns3_disable_sriov(struct pci_dev *pdev)
3127 {
3128 /* If our VFs are assigned we cannot shut down SR-IOV
3129 * without causing issues, so just leave the hardware
3130 * available but disabled
3131 */
3132 if (pci_vfs_assigned(pdev)) {
3133 dev_warn(&pdev->dev,
3134 "disabling driver while VFs are assigned\n");
3135 return;
3136 }
3137
3138 pci_disable_sriov(pdev);
3139 }
3140
3141 /* hns3_probe - Device initialization routine
3142 * @pdev: PCI device information struct
3143 * @ent: entry in hns3_pci_tbl
3144 *
3145 * hns3_probe initializes a PF identified by a pci_dev structure.
3146 * The OS initialization, configuring of the PF private structure,
3147 * and a hardware reset occur.
3148 *
3149 * Returns 0 on success, negative on failure
3150 */
hns3_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3151 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3152 {
3153 struct hnae3_ae_dev *ae_dev;
3154 int ret;
3155
3156 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL);
3157 if (!ae_dev)
3158 return -ENOMEM;
3159
3160 ae_dev->pdev = pdev;
3161 ae_dev->flag = ent->driver_data;
3162 pci_set_drvdata(pdev, ae_dev);
3163
3164 ret = hnae3_register_ae_dev(ae_dev);
3165 if (ret)
3166 pci_set_drvdata(pdev, NULL);
3167
3168 return ret;
3169 }
3170
3171 /**
3172 * hns3_clean_vf_config
3173 * @pdev: pointer to a pci_dev structure
3174 * @num_vfs: number of VFs allocated
3175 *
3176 * Clean residual vf config after disable sriov
3177 **/
hns3_clean_vf_config(struct pci_dev * pdev,int num_vfs)3178 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs)
3179 {
3180 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3181
3182 if (ae_dev->ops->clean_vf_config)
3183 ae_dev->ops->clean_vf_config(ae_dev, num_vfs);
3184 }
3185
3186 /* hns3_remove - Device removal routine
3187 * @pdev: PCI device information struct
3188 */
hns3_remove(struct pci_dev * pdev)3189 static void hns3_remove(struct pci_dev *pdev)
3190 {
3191 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3192
3193 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))
3194 hns3_disable_sriov(pdev);
3195
3196 hnae3_unregister_ae_dev(ae_dev);
3197 pci_set_drvdata(pdev, NULL);
3198 }
3199
3200 /**
3201 * hns3_pci_sriov_configure
3202 * @pdev: pointer to a pci_dev structure
3203 * @num_vfs: number of VFs to allocate
3204 *
3205 * Enable or change the number of VFs. Called when the user updates the number
3206 * of VFs in sysfs.
3207 **/
hns3_pci_sriov_configure(struct pci_dev * pdev,int num_vfs)3208 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
3209 {
3210 int ret;
3211
3212 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) {
3213 dev_warn(&pdev->dev, "Can not config SRIOV\n");
3214 return -EINVAL;
3215 }
3216
3217 if (num_vfs) {
3218 ret = pci_enable_sriov(pdev, num_vfs);
3219 if (ret)
3220 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret);
3221 else
3222 return num_vfs;
3223 } else if (!pci_vfs_assigned(pdev)) {
3224 int num_vfs_pre = pci_num_vf(pdev);
3225
3226 pci_disable_sriov(pdev);
3227 hns3_clean_vf_config(pdev, num_vfs_pre);
3228 } else {
3229 dev_warn(&pdev->dev,
3230 "Unable to free VFs because some are assigned to VMs.\n");
3231 }
3232
3233 return 0;
3234 }
3235
hns3_shutdown(struct pci_dev * pdev)3236 static void hns3_shutdown(struct pci_dev *pdev)
3237 {
3238 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3239
3240 hnae3_unregister_ae_dev(ae_dev);
3241 pci_set_drvdata(pdev, NULL);
3242
3243 if (system_state == SYSTEM_POWER_OFF)
3244 pci_set_power_state(pdev, PCI_D3hot);
3245 }
3246
hns3_suspend(struct device * dev)3247 static int __maybe_unused hns3_suspend(struct device *dev)
3248 {
3249 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3250
3251 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3252 dev_info(dev, "Begin to suspend.\n");
3253 if (ae_dev->ops && ae_dev->ops->reset_prepare)
3254 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET);
3255 }
3256
3257 return 0;
3258 }
3259
hns3_resume(struct device * dev)3260 static int __maybe_unused hns3_resume(struct device *dev)
3261 {
3262 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev);
3263
3264 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) {
3265 dev_info(dev, "Begin to resume.\n");
3266 if (ae_dev->ops && ae_dev->ops->reset_done)
3267 ae_dev->ops->reset_done(ae_dev);
3268 }
3269
3270 return 0;
3271 }
3272
hns3_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3273 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
3274 pci_channel_state_t state)
3275 {
3276 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3277 pci_ers_result_t ret;
3278
3279 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state);
3280
3281 if (state == pci_channel_io_perm_failure)
3282 return PCI_ERS_RESULT_DISCONNECT;
3283
3284 if (!ae_dev || !ae_dev->ops) {
3285 dev_err(&pdev->dev,
3286 "Can't recover - error happened before device initialized\n");
3287 return PCI_ERS_RESULT_NONE;
3288 }
3289
3290 if (ae_dev->ops->handle_hw_ras_error)
3291 ret = ae_dev->ops->handle_hw_ras_error(ae_dev);
3292 else
3293 return PCI_ERS_RESULT_NONE;
3294
3295 return ret;
3296 }
3297
hns3_slot_reset(struct pci_dev * pdev)3298 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
3299 {
3300 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3301 const struct hnae3_ae_ops *ops;
3302 enum hnae3_reset_type reset_type;
3303 struct device *dev = &pdev->dev;
3304
3305 if (!ae_dev || !ae_dev->ops)
3306 return PCI_ERS_RESULT_NONE;
3307
3308 ops = ae_dev->ops;
3309 /* request the reset */
3310 if (ops->reset_event && ops->get_reset_level &&
3311 ops->set_default_reset_request) {
3312 if (ae_dev->hw_err_reset_req) {
3313 reset_type = ops->get_reset_level(ae_dev,
3314 &ae_dev->hw_err_reset_req);
3315 ops->set_default_reset_request(ae_dev, reset_type);
3316 dev_info(dev, "requesting reset due to PCI error\n");
3317 ops->reset_event(pdev, NULL);
3318 }
3319
3320 return PCI_ERS_RESULT_RECOVERED;
3321 }
3322
3323 return PCI_ERS_RESULT_DISCONNECT;
3324 }
3325
hns3_reset_prepare(struct pci_dev * pdev)3326 static void hns3_reset_prepare(struct pci_dev *pdev)
3327 {
3328 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3329
3330 dev_info(&pdev->dev, "FLR prepare\n");
3331 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare)
3332 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET);
3333 }
3334
hns3_reset_done(struct pci_dev * pdev)3335 static void hns3_reset_done(struct pci_dev *pdev)
3336 {
3337 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3338
3339 dev_info(&pdev->dev, "FLR done\n");
3340 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done)
3341 ae_dev->ops->reset_done(ae_dev);
3342 }
3343
3344 static const struct pci_error_handlers hns3_err_handler = {
3345 .error_detected = hns3_error_detected,
3346 .slot_reset = hns3_slot_reset,
3347 .reset_prepare = hns3_reset_prepare,
3348 .reset_done = hns3_reset_done,
3349 };
3350
3351 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume);
3352
3353 static struct pci_driver hns3_driver = {
3354 .name = hns3_driver_name,
3355 .id_table = hns3_pci_tbl,
3356 .probe = hns3_probe,
3357 .remove = hns3_remove,
3358 .shutdown = hns3_shutdown,
3359 .driver.pm = &hns3_pm_ops,
3360 .sriov_configure = hns3_pci_sriov_configure,
3361 .err_handler = &hns3_err_handler,
3362 };
3363
3364 /* set default feature to hns3 */
hns3_set_default_feature(struct net_device * netdev)3365 static void hns3_set_default_feature(struct net_device *netdev)
3366 {
3367 struct hnae3_handle *h = hns3_get_handle(netdev);
3368 struct pci_dev *pdev = h->pdev;
3369 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
3370
3371 netdev->priv_flags |= IFF_UNICAST_FLT;
3372
3373 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3374 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3375 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
3376 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
3377 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
3378 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
3379
3380 if (hnae3_ae_dev_gro_supported(ae_dev))
3381 netdev->features |= NETIF_F_GRO_HW;
3382
3383 if (hnae3_ae_dev_fd_supported(ae_dev))
3384 netdev->features |= NETIF_F_NTUPLE;
3385
3386 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
3387 netdev->features |= NETIF_F_GSO_UDP_L4;
3388
3389 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
3390 netdev->features |= NETIF_F_HW_CSUM;
3391 else
3392 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3393
3394 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
3395 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
3396
3397 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
3398 netdev->features |= NETIF_F_HW_TC;
3399
3400 netdev->hw_features |= netdev->features;
3401 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
3402 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
3403
3404 netdev->vlan_features |= netdev->features &
3405 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
3406 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
3407 NETIF_F_HW_TC);
3408
3409 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
3410
3411 /* The device_version V3 hardware can't offload the checksum for IP in
3412 * GRE packets, but can do it for NvGRE. So default to disable the
3413 * checksum and GSO offload for GRE.
3414 */
3415 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) {
3416 netdev->features &= ~NETIF_F_GSO_GRE;
3417 netdev->features &= ~NETIF_F_GSO_GRE_CSUM;
3418 }
3419 }
3420
hns3_alloc_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3421 static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
3422 struct hns3_desc_cb *cb)
3423 {
3424 unsigned int order = hns3_page_order(ring);
3425 struct page *p;
3426
3427 if (ring->page_pool) {
3428 p = page_pool_dev_alloc_frag(ring->page_pool,
3429 &cb->page_offset,
3430 hns3_buf_size(ring));
3431 if (unlikely(!p))
3432 return -ENOMEM;
3433
3434 cb->priv = p;
3435 cb->buf = page_address(p);
3436 cb->dma = page_pool_get_dma_addr(p);
3437 cb->type = DESC_TYPE_PP_FRAG;
3438 cb->reuse_flag = 0;
3439 return 0;
3440 }
3441
3442 p = dev_alloc_pages(order);
3443 if (!p)
3444 return -ENOMEM;
3445
3446 cb->priv = p;
3447 cb->page_offset = 0;
3448 cb->reuse_flag = 0;
3449 cb->buf = page_address(p);
3450 cb->length = hns3_page_size(ring);
3451 cb->type = DESC_TYPE_PAGE;
3452 page_ref_add(p, USHRT_MAX - 1);
3453 cb->pagecnt_bias = USHRT_MAX;
3454
3455 return 0;
3456 }
3457
hns3_free_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb,int budget)3458 static void hns3_free_buffer(struct hns3_enet_ring *ring,
3459 struct hns3_desc_cb *cb, int budget)
3460 {
3461 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
3462 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
3463 napi_consume_skb(cb->priv, budget);
3464 else if (!HNAE3_IS_TX_RING(ring)) {
3465 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias)
3466 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
3467 else if (cb->type & DESC_TYPE_PP_FRAG)
3468 page_pool_put_full_page(ring->page_pool, cb->priv,
3469 false);
3470 }
3471 memset(cb, 0, sizeof(*cb));
3472 }
3473
hns3_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3474 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
3475 {
3476 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0,
3477 cb->length, ring_to_dma_dir(ring));
3478
3479 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma)))
3480 return -EIO;
3481
3482 return 0;
3483 }
3484
hns3_unmap_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3485 static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
3486 struct hns3_desc_cb *cb)
3487 {
3488 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
3489 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
3490 ring_to_dma_dir(ring));
3491 else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
3492 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
3493 ring_to_dma_dir(ring));
3494 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
3495 DESC_TYPE_SGL_SKB))
3496 hns3_tx_spare_reclaim_cb(ring, cb);
3497 }
3498
hns3_buffer_detach(struct hns3_enet_ring * ring,int i)3499 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
3500 {
3501 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3502 ring->desc[i].addr = 0;
3503 ring->desc_cb[i].refill = 0;
3504 }
3505
hns3_free_buffer_detach(struct hns3_enet_ring * ring,int i,int budget)3506 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
3507 int budget)
3508 {
3509 struct hns3_desc_cb *cb = &ring->desc_cb[i];
3510
3511 if (!ring->desc_cb[i].dma)
3512 return;
3513
3514 hns3_buffer_detach(ring, i);
3515 hns3_free_buffer(ring, cb, budget);
3516 }
3517
hns3_free_buffers(struct hns3_enet_ring * ring)3518 static void hns3_free_buffers(struct hns3_enet_ring *ring)
3519 {
3520 int i;
3521
3522 for (i = 0; i < ring->desc_num; i++)
3523 hns3_free_buffer_detach(ring, i, 0);
3524 }
3525
3526 /* free desc along with its attached buffer */
hns3_free_desc(struct hns3_enet_ring * ring)3527 static void hns3_free_desc(struct hns3_enet_ring *ring)
3528 {
3529 int size = ring->desc_num * sizeof(ring->desc[0]);
3530
3531 hns3_free_buffers(ring);
3532
3533 if (ring->desc) {
3534 dma_free_coherent(ring_to_dev(ring), size,
3535 ring->desc, ring->desc_dma_addr);
3536 ring->desc = NULL;
3537 }
3538 }
3539
hns3_alloc_desc(struct hns3_enet_ring * ring)3540 static int hns3_alloc_desc(struct hns3_enet_ring *ring)
3541 {
3542 int size = ring->desc_num * sizeof(ring->desc[0]);
3543
3544 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size,
3545 &ring->desc_dma_addr, GFP_KERNEL);
3546 if (!ring->desc)
3547 return -ENOMEM;
3548
3549 return 0;
3550 }
3551
hns3_alloc_and_map_buffer(struct hns3_enet_ring * ring,struct hns3_desc_cb * cb)3552 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring,
3553 struct hns3_desc_cb *cb)
3554 {
3555 int ret;
3556
3557 ret = hns3_alloc_buffer(ring, cb);
3558 if (ret || ring->page_pool)
3559 goto out;
3560
3561 ret = hns3_map_buffer(ring, cb);
3562 if (ret)
3563 goto out_with_buf;
3564
3565 return 0;
3566
3567 out_with_buf:
3568 hns3_free_buffer(ring, cb, 0);
3569 out:
3570 return ret;
3571 }
3572
hns3_alloc_and_attach_buffer(struct hns3_enet_ring * ring,int i)3573 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
3574 {
3575 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]);
3576
3577 if (ret)
3578 return ret;
3579
3580 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3581 ring->desc_cb[i].page_offset);
3582 ring->desc_cb[i].refill = 1;
3583
3584 return 0;
3585 }
3586
3587 /* Allocate memory for raw pkg, and map with dma */
hns3_alloc_ring_buffers(struct hns3_enet_ring * ring)3588 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring)
3589 {
3590 int i, j, ret;
3591
3592 for (i = 0; i < ring->desc_num; i++) {
3593 ret = hns3_alloc_and_attach_buffer(ring, i);
3594 if (ret)
3595 goto out_buffer_fail;
3596
3597 if (!(i % HNS3_RESCHED_BD_NUM))
3598 cond_resched();
3599 }
3600
3601 return 0;
3602
3603 out_buffer_fail:
3604 for (j = i - 1; j >= 0; j--)
3605 hns3_free_buffer_detach(ring, j, 0);
3606 return ret;
3607 }
3608
3609 /* detach a in-used buffer and replace with a reserved one */
hns3_replace_buffer(struct hns3_enet_ring * ring,int i,struct hns3_desc_cb * res_cb)3610 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
3611 struct hns3_desc_cb *res_cb)
3612 {
3613 hns3_unmap_buffer(ring, &ring->desc_cb[i]);
3614 ring->desc_cb[i] = *res_cb;
3615 ring->desc_cb[i].refill = 1;
3616 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3617 ring->desc_cb[i].page_offset);
3618 ring->desc[i].rx.bd_base_info = 0;
3619 }
3620
hns3_reuse_buffer(struct hns3_enet_ring * ring,int i)3621 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
3622 {
3623 ring->desc_cb[i].reuse_flag = 0;
3624 ring->desc_cb[i].refill = 1;
3625 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
3626 ring->desc_cb[i].page_offset);
3627 ring->desc[i].rx.bd_base_info = 0;
3628
3629 dma_sync_single_for_device(ring_to_dev(ring),
3630 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset,
3631 hns3_buf_size(ring),
3632 DMA_FROM_DEVICE);
3633 }
3634
hns3_nic_reclaim_desc(struct hns3_enet_ring * ring,int * bytes,int * pkts,int budget)3635 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
3636 int *bytes, int *pkts, int budget)
3637 {
3638 /* This smp_load_acquire() pairs with smp_store_release() in
3639 * hns3_tx_doorbell().
3640 */
3641 int ltu = smp_load_acquire(&ring->last_to_use);
3642 int ntc = ring->next_to_clean;
3643 struct hns3_desc_cb *desc_cb;
3644 bool reclaimed = false;
3645 struct hns3_desc *desc;
3646
3647 while (ltu != ntc) {
3648 desc = &ring->desc[ntc];
3649
3650 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) &
3651 BIT(HNS3_TXD_VLD_B))
3652 break;
3653
3654 desc_cb = &ring->desc_cb[ntc];
3655
3656 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
3657 DESC_TYPE_BOUNCE_HEAD |
3658 DESC_TYPE_SGL_SKB)) {
3659 (*pkts)++;
3660 (*bytes) += desc_cb->send_bytes;
3661 }
3662
3663 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */
3664 hns3_free_buffer_detach(ring, ntc, budget);
3665
3666 if (++ntc == ring->desc_num)
3667 ntc = 0;
3668
3669 /* Issue prefetch for next Tx descriptor */
3670 prefetch(&ring->desc_cb[ntc]);
3671 reclaimed = true;
3672 }
3673
3674 if (unlikely(!reclaimed))
3675 return false;
3676
3677 /* This smp_store_release() pairs with smp_load_acquire() in
3678 * ring_space called by hns3_nic_net_xmit.
3679 */
3680 smp_store_release(&ring->next_to_clean, ntc);
3681
3682 hns3_tx_spare_update(ring);
3683
3684 return true;
3685 }
3686
hns3_clean_tx_ring(struct hns3_enet_ring * ring,int budget)3687 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget)
3688 {
3689 struct net_device *netdev = ring_to_netdev(ring);
3690 struct hns3_nic_priv *priv = netdev_priv(netdev);
3691 struct netdev_queue *dev_queue;
3692 int bytes, pkts;
3693
3694 bytes = 0;
3695 pkts = 0;
3696
3697 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget)))
3698 return;
3699
3700 ring->tqp_vector->tx_group.total_bytes += bytes;
3701 ring->tqp_vector->tx_group.total_packets += pkts;
3702
3703 u64_stats_update_begin(&ring->syncp);
3704 ring->stats.tx_bytes += bytes;
3705 ring->stats.tx_pkts += pkts;
3706 u64_stats_update_end(&ring->syncp);
3707
3708 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index);
3709 netdev_tx_completed_queue(dev_queue, pkts, bytes);
3710
3711 if (unlikely(netif_carrier_ok(netdev) &&
3712 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) {
3713 /* Make sure that anybody stopping the queue after this
3714 * sees the new next_to_clean.
3715 */
3716 smp_mb();
3717 if (netif_tx_queue_stopped(dev_queue) &&
3718 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
3719 netif_tx_wake_queue(dev_queue);
3720 ring->stats.restart_queue++;
3721 }
3722 }
3723 }
3724
hns3_desc_unused(struct hns3_enet_ring * ring)3725 static int hns3_desc_unused(struct hns3_enet_ring *ring)
3726 {
3727 int ntc = ring->next_to_clean;
3728 int ntu = ring->next_to_use;
3729
3730 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
3731 return ring->desc_num;
3732
3733 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
3734 }
3735
3736 /* Return true if there is any allocation failure */
hns3_nic_alloc_rx_buffers(struct hns3_enet_ring * ring,int cleand_count)3737 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
3738 int cleand_count)
3739 {
3740 struct hns3_desc_cb *desc_cb;
3741 struct hns3_desc_cb res_cbs;
3742 int i, ret;
3743
3744 for (i = 0; i < cleand_count; i++) {
3745 desc_cb = &ring->desc_cb[ring->next_to_use];
3746 if (desc_cb->reuse_flag) {
3747 hns3_ring_stats_update(ring, reuse_pg_cnt);
3748
3749 hns3_reuse_buffer(ring, ring->next_to_use);
3750 } else {
3751 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
3752 if (ret) {
3753 hns3_ring_stats_update(ring, sw_err_cnt);
3754
3755 hns3_rl_err(ring_to_netdev(ring),
3756 "alloc rx buffer failed: %d\n",
3757 ret);
3758
3759 writel(i, ring->tqp->io_base +
3760 HNS3_RING_RX_RING_HEAD_REG);
3761 return true;
3762 }
3763 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
3764
3765 hns3_ring_stats_update(ring, non_reuse_pg);
3766 }
3767
3768 ring_ptr_move_fw(ring, next_to_use);
3769 }
3770
3771 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
3772 return false;
3773 }
3774
hns3_can_reuse_page(struct hns3_desc_cb * cb)3775 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
3776 {
3777 return page_count(cb->priv) == cb->pagecnt_bias;
3778 }
3779
hns3_handle_rx_copybreak(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3780 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
3781 struct hns3_enet_ring *ring,
3782 int pull_len,
3783 struct hns3_desc_cb *desc_cb)
3784 {
3785 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3786 u32 frag_offset = desc_cb->page_offset + pull_len;
3787 int size = le16_to_cpu(desc->rx.size);
3788 u32 frag_size = size - pull_len;
3789 void *frag = napi_alloc_frag(frag_size);
3790
3791 if (unlikely(!frag)) {
3792 hns3_ring_stats_update(ring, frag_alloc_err);
3793
3794 hns3_rl_err(ring_to_netdev(ring),
3795 "failed to allocate rx frag\n");
3796 return -ENOMEM;
3797 }
3798
3799 desc_cb->reuse_flag = 1;
3800 memcpy(frag, desc_cb->buf + frag_offset, frag_size);
3801 skb_add_rx_frag(skb, i, virt_to_page(frag),
3802 offset_in_page(frag), frag_size, frag_size);
3803
3804 hns3_ring_stats_update(ring, frag_alloc);
3805 return 0;
3806 }
3807
hns3_nic_reuse_page(struct sk_buff * skb,int i,struct hns3_enet_ring * ring,int pull_len,struct hns3_desc_cb * desc_cb)3808 static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
3809 struct hns3_enet_ring *ring, int pull_len,
3810 struct hns3_desc_cb *desc_cb)
3811 {
3812 struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
3813 u32 frag_offset = desc_cb->page_offset + pull_len;
3814 int size = le16_to_cpu(desc->rx.size);
3815 u32 truesize = hns3_buf_size(ring);
3816 u32 frag_size = size - pull_len;
3817 int ret = 0;
3818 bool reused;
3819
3820 if (ring->page_pool) {
3821 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3822 frag_size, truesize);
3823 return;
3824 }
3825
3826 /* Avoid re-using remote or pfmem page */
3827 if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
3828 goto out;
3829
3830 reused = hns3_can_reuse_page(desc_cb);
3831
3832 /* Rx page can be reused when:
3833 * 1. Rx page is only owned by the driver when page_offset
3834 * is zero, which means 0 @ truesize will be used by
3835 * stack after skb_add_rx_frag() is called, and the rest
3836 * of rx page can be reused by driver.
3837 * Or
3838 * 2. Rx page is only owned by the driver when page_offset
3839 * is non-zero, which means page_offset @ truesize will
3840 * be used by stack after skb_add_rx_frag() is called,
3841 * and 0 @ truesize can be reused by driver.
3842 */
3843 if ((!desc_cb->page_offset && reused) ||
3844 ((desc_cb->page_offset + truesize + truesize) <=
3845 hns3_page_size(ring) && desc_cb->page_offset)) {
3846 desc_cb->page_offset += truesize;
3847 desc_cb->reuse_flag = 1;
3848 } else if (desc_cb->page_offset && reused) {
3849 desc_cb->page_offset = 0;
3850 desc_cb->reuse_flag = 1;
3851 } else if (frag_size <= ring->rx_copybreak) {
3852 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
3853 if (!ret)
3854 return;
3855 }
3856
3857 out:
3858 desc_cb->pagecnt_bias--;
3859
3860 if (unlikely(!desc_cb->pagecnt_bias)) {
3861 page_ref_add(desc_cb->priv, USHRT_MAX);
3862 desc_cb->pagecnt_bias = USHRT_MAX;
3863 }
3864
3865 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
3866 frag_size, truesize);
3867
3868 if (unlikely(!desc_cb->reuse_flag))
3869 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
3870 }
3871
hns3_gro_complete(struct sk_buff * skb,u32 l234info)3872 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
3873 {
3874 __be16 type = skb->protocol;
3875 struct tcphdr *th;
3876 u32 depth = 0;
3877
3878 while (eth_type_vlan(type)) {
3879 struct vlan_hdr *vh;
3880
3881 if ((depth + VLAN_HLEN) > skb_headlen(skb))
3882 return -EFAULT;
3883
3884 vh = (struct vlan_hdr *)(skb->data + depth);
3885 type = vh->h_vlan_encapsulated_proto;
3886 depth += VLAN_HLEN;
3887 }
3888
3889 skb_set_network_header(skb, depth);
3890
3891 if (type == htons(ETH_P_IP)) {
3892 const struct iphdr *iph = ip_hdr(skb);
3893
3894 depth += sizeof(struct iphdr);
3895 skb_set_transport_header(skb, depth);
3896 th = tcp_hdr(skb);
3897 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr,
3898 iph->daddr, 0);
3899 } else if (type == htons(ETH_P_IPV6)) {
3900 const struct ipv6hdr *iph = ipv6_hdr(skb);
3901
3902 depth += sizeof(struct ipv6hdr);
3903 skb_set_transport_header(skb, depth);
3904 th = tcp_hdr(skb);
3905 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr,
3906 &iph->daddr, 0);
3907 } else {
3908 hns3_rl_err(skb->dev,
3909 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n",
3910 be16_to_cpu(type), depth);
3911 return -EFAULT;
3912 }
3913
3914 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
3915 if (th->cwr)
3916 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN;
3917
3918 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B))
3919 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID;
3920
3921 skb->csum_start = (unsigned char *)th - skb->head;
3922 skb->csum_offset = offsetof(struct tcphdr, check);
3923 skb->ip_summed = CHECKSUM_PARTIAL;
3924
3925 trace_hns3_gro(skb);
3926
3927 return 0;
3928 }
3929
hns3_checksum_complete(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 ptype,u16 csum)3930 static void hns3_checksum_complete(struct hns3_enet_ring *ring,
3931 struct sk_buff *skb, u32 ptype, u16 csum)
3932 {
3933 if (ptype == HNS3_INVALID_PTYPE ||
3934 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE)
3935 return;
3936
3937 hns3_ring_stats_update(ring, csum_complete);
3938 skb->ip_summed = CHECKSUM_COMPLETE;
3939 skb->csum = csum_unfold((__force __sum16)csum);
3940 }
3941
hns3_rx_handle_csum(struct sk_buff * skb,u32 l234info,u32 ol_info,u32 ptype)3942 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info,
3943 u32 ol_info, u32 ptype)
3944 {
3945 int l3_type, l4_type;
3946 int ol4_type;
3947
3948 if (ptype != HNS3_INVALID_PTYPE) {
3949 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level;
3950 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed;
3951
3952 return;
3953 }
3954
3955 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M,
3956 HNS3_RXD_OL4ID_S);
3957 switch (ol4_type) {
3958 case HNS3_OL4_TYPE_MAC_IN_UDP:
3959 case HNS3_OL4_TYPE_NVGRE:
3960 skb->csum_level = 1;
3961 fallthrough;
3962 case HNS3_OL4_TYPE_NO_TUN:
3963 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
3964 HNS3_RXD_L3ID_S);
3965 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
3966 HNS3_RXD_L4ID_S);
3967 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
3968 if ((l3_type == HNS3_L3_TYPE_IPV4 ||
3969 l3_type == HNS3_L3_TYPE_IPV6) &&
3970 (l4_type == HNS3_L4_TYPE_UDP ||
3971 l4_type == HNS3_L4_TYPE_TCP ||
3972 l4_type == HNS3_L4_TYPE_SCTP))
3973 skb->ip_summed = CHECKSUM_UNNECESSARY;
3974 break;
3975 default:
3976 break;
3977 }
3978 }
3979
hns3_rx_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)3980 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
3981 u32 l234info, u32 bd_base_info, u32 ol_info,
3982 u16 csum)
3983 {
3984 struct net_device *netdev = ring_to_netdev(ring);
3985 struct hns3_nic_priv *priv = netdev_priv(netdev);
3986 u32 ptype = HNS3_INVALID_PTYPE;
3987
3988 skb->ip_summed = CHECKSUM_NONE;
3989
3990 skb_checksum_none_assert(skb);
3991
3992 if (!(netdev->features & NETIF_F_RXCSUM))
3993 return;
3994
3995 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state))
3996 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
3997 HNS3_RXD_PTYPE_S);
3998
3999 hns3_checksum_complete(ring, skb, ptype, csum);
4000
4001 /* check if hardware has done checksum */
4002 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))
4003 return;
4004
4005 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
4006 BIT(HNS3_RXD_OL3E_B) |
4007 BIT(HNS3_RXD_OL4E_B)))) {
4008 skb->ip_summed = CHECKSUM_NONE;
4009 hns3_ring_stats_update(ring, l3l4_csum_err);
4010
4011 return;
4012 }
4013
4014 hns3_rx_handle_csum(skb, l234info, ol_info, ptype);
4015 }
4016
hns3_rx_skb(struct hns3_enet_ring * ring,struct sk_buff * skb)4017 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb)
4018 {
4019 if (skb_has_frag_list(skb))
4020 napi_gro_flush(&ring->tqp_vector->napi, false);
4021
4022 napi_gro_receive(&ring->tqp_vector->napi, skb);
4023 }
4024
hns3_parse_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,u32 l234info,u16 * vlan_tag)4025 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
4026 struct hns3_desc *desc, u32 l234info,
4027 u16 *vlan_tag)
4028 {
4029 struct hnae3_handle *handle = ring->tqp->handle;
4030 struct pci_dev *pdev = ring->tqp->handle->pdev;
4031 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
4032
4033 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
4034 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4035 if (!(*vlan_tag & VLAN_VID_MASK))
4036 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4037
4038 return (*vlan_tag != 0);
4039 }
4040
4041 #define HNS3_STRP_OUTER_VLAN 0x1
4042 #define HNS3_STRP_INNER_VLAN 0x2
4043 #define HNS3_STRP_BOTH 0x3
4044
4045 /* Hardware always insert VLAN tag into RX descriptor when
4046 * remove the tag from packet, driver needs to determine
4047 * reporting which tag to stack.
4048 */
4049 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M,
4050 HNS3_RXD_STRP_TAGP_S)) {
4051 case HNS3_STRP_OUTER_VLAN:
4052 if (handle->port_base_vlan_state !=
4053 HNAE3_PORT_BASE_VLAN_DISABLE)
4054 return false;
4055
4056 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4057 return true;
4058 case HNS3_STRP_INNER_VLAN:
4059 if (handle->port_base_vlan_state !=
4060 HNAE3_PORT_BASE_VLAN_DISABLE)
4061 return false;
4062
4063 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4064 return true;
4065 case HNS3_STRP_BOTH:
4066 if (handle->port_base_vlan_state ==
4067 HNAE3_PORT_BASE_VLAN_DISABLE)
4068 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
4069 else
4070 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
4071
4072 return true;
4073 default:
4074 return false;
4075 }
4076 }
4077
hns3_rx_ring_move_fw(struct hns3_enet_ring * ring)4078 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
4079 {
4080 ring->desc[ring->next_to_clean].rx.bd_base_info &=
4081 cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
4082 ring->desc_cb[ring->next_to_clean].refill = 0;
4083 ring->next_to_clean += 1;
4084
4085 if (unlikely(ring->next_to_clean == ring->desc_num))
4086 ring->next_to_clean = 0;
4087 }
4088
hns3_alloc_skb(struct hns3_enet_ring * ring,unsigned int length,unsigned char * va)4089 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length,
4090 unsigned char *va)
4091 {
4092 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean];
4093 struct net_device *netdev = ring_to_netdev(ring);
4094 struct sk_buff *skb;
4095
4096 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE);
4097 skb = ring->skb;
4098 if (unlikely(!skb)) {
4099 hns3_rl_err(netdev, "alloc rx skb fail\n");
4100 hns3_ring_stats_update(ring, sw_err_cnt);
4101
4102 return -ENOMEM;
4103 }
4104
4105 trace_hns3_rx_desc(ring);
4106 prefetchw(skb->data);
4107
4108 ring->pending_buf = 1;
4109 ring->frag_num = 0;
4110 ring->tail_skb = NULL;
4111 if (length <= HNS3_RX_HEAD_SIZE) {
4112 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long)));
4113
4114 /* We can reuse buffer as-is, just make sure it is reusable */
4115 if (dev_page_is_reusable(desc_cb->priv))
4116 desc_cb->reuse_flag = 1;
4117 else if (desc_cb->type & DESC_TYPE_PP_FRAG)
4118 page_pool_put_full_page(ring->page_pool, desc_cb->priv,
4119 false);
4120 else /* This page cannot be reused so discard it */
4121 __page_frag_cache_drain(desc_cb->priv,
4122 desc_cb->pagecnt_bias);
4123
4124 hns3_rx_ring_move_fw(ring);
4125 return 0;
4126 }
4127
4128 if (ring->page_pool)
4129 skb_mark_for_recycle(skb);
4130
4131 hns3_ring_stats_update(ring, seg_pkt_cnt);
4132
4133 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE);
4134 __skb_put(skb, ring->pull_len);
4135 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len,
4136 desc_cb);
4137 hns3_rx_ring_move_fw(ring);
4138
4139 return 0;
4140 }
4141
hns3_add_frag(struct hns3_enet_ring * ring)4142 static int hns3_add_frag(struct hns3_enet_ring *ring)
4143 {
4144 struct sk_buff *skb = ring->skb;
4145 struct sk_buff *head_skb = skb;
4146 struct sk_buff *new_skb;
4147 struct hns3_desc_cb *desc_cb;
4148 struct hns3_desc *desc;
4149 u32 bd_base_info;
4150
4151 do {
4152 desc = &ring->desc[ring->next_to_clean];
4153 desc_cb = &ring->desc_cb[ring->next_to_clean];
4154 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4155 /* make sure HW write desc complete */
4156 dma_rmb();
4157 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B)))
4158 return -ENXIO;
4159
4160 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) {
4161 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0);
4162 if (unlikely(!new_skb)) {
4163 hns3_rl_err(ring_to_netdev(ring),
4164 "alloc rx fraglist skb fail\n");
4165 return -ENXIO;
4166 }
4167
4168 if (ring->page_pool)
4169 skb_mark_for_recycle(new_skb);
4170
4171 ring->frag_num = 0;
4172
4173 if (ring->tail_skb) {
4174 ring->tail_skb->next = new_skb;
4175 ring->tail_skb = new_skb;
4176 } else {
4177 skb_shinfo(skb)->frag_list = new_skb;
4178 ring->tail_skb = new_skb;
4179 }
4180 }
4181
4182 if (ring->tail_skb) {
4183 head_skb->truesize += hns3_buf_size(ring);
4184 head_skb->data_len += le16_to_cpu(desc->rx.size);
4185 head_skb->len += le16_to_cpu(desc->rx.size);
4186 skb = ring->tail_skb;
4187 }
4188
4189 dma_sync_single_for_cpu(ring_to_dev(ring),
4190 desc_cb->dma + desc_cb->page_offset,
4191 hns3_buf_size(ring),
4192 DMA_FROM_DEVICE);
4193
4194 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb);
4195 trace_hns3_rx_desc(ring);
4196 hns3_rx_ring_move_fw(ring);
4197 ring->pending_buf++;
4198 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B)));
4199
4200 return 0;
4201 }
4202
hns3_set_gro_and_checksum(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 l234info,u32 bd_base_info,u32 ol_info,u16 csum)4203 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring,
4204 struct sk_buff *skb, u32 l234info,
4205 u32 bd_base_info, u32 ol_info, u16 csum)
4206 {
4207 struct net_device *netdev = ring_to_netdev(ring);
4208 struct hns3_nic_priv *priv = netdev_priv(netdev);
4209 u32 l3_type;
4210
4211 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info,
4212 HNS3_RXD_GRO_SIZE_M,
4213 HNS3_RXD_GRO_SIZE_S);
4214 /* if there is no HW GRO, do not set gro params */
4215 if (!skb_shinfo(skb)->gso_size) {
4216 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info,
4217 csum);
4218 return 0;
4219 }
4220
4221 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info,
4222 HNS3_RXD_GRO_COUNT_M,
4223 HNS3_RXD_GRO_COUNT_S);
4224
4225 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4226 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4227 HNS3_RXD_PTYPE_S);
4228
4229 l3_type = hns3_rx_ptype_tbl[ptype].l3_type;
4230 } else {
4231 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4232 HNS3_RXD_L3ID_S);
4233 }
4234
4235 if (l3_type == HNS3_L3_TYPE_IPV4)
4236 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
4237 else if (l3_type == HNS3_L3_TYPE_IPV6)
4238 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
4239 else
4240 return -EFAULT;
4241
4242 return hns3_gro_complete(skb, l234info);
4243 }
4244
hns3_set_rx_skb_rss_type(struct hns3_enet_ring * ring,struct sk_buff * skb,u32 rss_hash,u32 l234info,u32 ol_info)4245 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring,
4246 struct sk_buff *skb, u32 rss_hash,
4247 u32 l234info, u32 ol_info)
4248 {
4249 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE;
4250 struct net_device *netdev = ring_to_netdev(ring);
4251 struct hns3_nic_priv *priv = netdev_priv(netdev);
4252
4253 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
4254 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M,
4255 HNS3_RXD_PTYPE_S);
4256
4257 rss_type = hns3_rx_ptype_tbl[ptype].hash_type;
4258 } else {
4259 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M,
4260 HNS3_RXD_L3ID_S);
4261 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
4262 HNS3_RXD_L4ID_S);
4263
4264 if (l3_type == HNS3_L3_TYPE_IPV4 ||
4265 l3_type == HNS3_L3_TYPE_IPV6) {
4266 if (l4_type == HNS3_L4_TYPE_UDP ||
4267 l4_type == HNS3_L4_TYPE_TCP ||
4268 l4_type == HNS3_L4_TYPE_SCTP)
4269 rss_type = PKT_HASH_TYPE_L4;
4270 else if (l4_type == HNS3_L4_TYPE_IGMP ||
4271 l4_type == HNS3_L4_TYPE_ICMP)
4272 rss_type = PKT_HASH_TYPE_L3;
4273 }
4274 }
4275
4276 skb_set_hash(skb, rss_hash, rss_type);
4277 }
4278
hns3_handle_rx_ts_info(struct net_device * netdev,struct hns3_desc * desc,struct sk_buff * skb,u32 bd_base_info)4279 static void hns3_handle_rx_ts_info(struct net_device *netdev,
4280 struct hns3_desc *desc, struct sk_buff *skb,
4281 u32 bd_base_info)
4282 {
4283 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
4284 struct hnae3_handle *h = hns3_get_handle(netdev);
4285 u32 nsec = le32_to_cpu(desc->ts_nsec);
4286 u32 sec = le32_to_cpu(desc->ts_sec);
4287
4288 if (h->ae_algo->ops->get_rx_hwts)
4289 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
4290 }
4291 }
4292
hns3_handle_rx_vlan_tag(struct hns3_enet_ring * ring,struct hns3_desc * desc,struct sk_buff * skb,u32 l234info)4293 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring,
4294 struct hns3_desc *desc, struct sk_buff *skb,
4295 u32 l234info)
4296 {
4297 struct net_device *netdev = ring_to_netdev(ring);
4298
4299 /* Based on hw strategy, the tag offloaded will be stored at
4300 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
4301 * in one layer tag case.
4302 */
4303 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
4304 u16 vlan_tag;
4305
4306 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag))
4307 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
4308 vlan_tag);
4309 }
4310 }
4311
hns3_handle_bdinfo(struct hns3_enet_ring * ring,struct sk_buff * skb)4312 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
4313 {
4314 struct net_device *netdev = ring_to_netdev(ring);
4315 enum hns3_pkt_l2t_type l2_frame_type;
4316 u32 bd_base_info, l234info, ol_info;
4317 struct hns3_desc *desc;
4318 unsigned int len;
4319 int pre_ntc, ret;
4320 u16 csum;
4321
4322 /* bdinfo handled below is only valid on the last BD of the
4323 * current packet, and ring->next_to_clean indicates the first
4324 * descriptor of next packet, so need - 1 below.
4325 */
4326 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) :
4327 (ring->desc_num - 1);
4328 desc = &ring->desc[pre_ntc];
4329 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4330 l234info = le32_to_cpu(desc->rx.l234_info);
4331 ol_info = le32_to_cpu(desc->rx.ol_info);
4332 csum = le16_to_cpu(desc->csum);
4333
4334 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info);
4335
4336 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info);
4337
4338 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) |
4339 BIT(HNS3_RXD_L2E_B))))) {
4340 u64_stats_update_begin(&ring->syncp);
4341 if (l234info & BIT(HNS3_RXD_L2E_B))
4342 ring->stats.l2_err++;
4343 else
4344 ring->stats.err_pkt_len++;
4345 u64_stats_update_end(&ring->syncp);
4346
4347 return -EFAULT;
4348 }
4349
4350 len = skb->len;
4351
4352 /* Do update ip stack process */
4353 skb->protocol = eth_type_trans(skb, netdev);
4354
4355 /* This is needed in order to enable forwarding support */
4356 ret = hns3_set_gro_and_checksum(ring, skb, l234info,
4357 bd_base_info, ol_info, csum);
4358 if (unlikely(ret)) {
4359 hns3_ring_stats_update(ring, rx_err_cnt);
4360 return ret;
4361 }
4362
4363 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M,
4364 HNS3_RXD_DMAC_S);
4365
4366 u64_stats_update_begin(&ring->syncp);
4367 ring->stats.rx_pkts++;
4368 ring->stats.rx_bytes += len;
4369
4370 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST)
4371 ring->stats.rx_multicast++;
4372
4373 u64_stats_update_end(&ring->syncp);
4374
4375 ring->tqp_vector->rx_group.total_bytes += len;
4376
4377 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash),
4378 l234info, ol_info);
4379 return 0;
4380 }
4381
hns3_handle_rx_bd(struct hns3_enet_ring * ring)4382 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
4383 {
4384 struct sk_buff *skb = ring->skb;
4385 struct hns3_desc_cb *desc_cb;
4386 struct hns3_desc *desc;
4387 unsigned int length;
4388 u32 bd_base_info;
4389 int ret;
4390
4391 desc = &ring->desc[ring->next_to_clean];
4392 desc_cb = &ring->desc_cb[ring->next_to_clean];
4393
4394 prefetch(desc);
4395
4396 if (!skb) {
4397 bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
4398 /* Check valid BD */
4399 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
4400 return -ENXIO;
4401
4402 dma_rmb();
4403 length = le16_to_cpu(desc->rx.size);
4404
4405 ring->va = desc_cb->buf + desc_cb->page_offset;
4406
4407 dma_sync_single_for_cpu(ring_to_dev(ring),
4408 desc_cb->dma + desc_cb->page_offset,
4409 hns3_buf_size(ring),
4410 DMA_FROM_DEVICE);
4411
4412 /* Prefetch first cache line of first page.
4413 * Idea is to cache few bytes of the header of the packet.
4414 * Our L1 Cache line size is 64B so need to prefetch twice to make
4415 * it 128B. But in actual we can have greater size of caches with
4416 * 128B Level 1 cache lines. In such a case, single fetch would
4417 * suffice to cache in the relevant part of the header.
4418 */
4419 net_prefetch(ring->va);
4420
4421 ret = hns3_alloc_skb(ring, length, ring->va);
4422 skb = ring->skb;
4423
4424 if (ret < 0) /* alloc buffer fail */
4425 return ret;
4426 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */
4427 ret = hns3_add_frag(ring);
4428 if (ret)
4429 return ret;
4430 }
4431 } else {
4432 ret = hns3_add_frag(ring);
4433 if (ret)
4434 return ret;
4435 }
4436
4437 /* As the head data may be changed when GRO enable, copy
4438 * the head data in after other data rx completed
4439 */
4440 if (skb->len > HNS3_RX_HEAD_SIZE)
4441 memcpy(skb->data, ring->va,
4442 ALIGN(ring->pull_len, sizeof(long)));
4443
4444 ret = hns3_handle_bdinfo(ring, skb);
4445 if (unlikely(ret)) {
4446 dev_kfree_skb_any(skb);
4447 return ret;
4448 }
4449
4450 skb_record_rx_queue(skb, ring->tqp->tqp_index);
4451 return 0;
4452 }
4453
hns3_clean_rx_ring(struct hns3_enet_ring * ring,int budget,void (* rx_fn)(struct hns3_enet_ring *,struct sk_buff *))4454 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
4455 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *))
4456 {
4457 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
4458 int unused_count = hns3_desc_unused(ring);
4459 bool failure = false;
4460 int recv_pkts = 0;
4461 int err;
4462
4463 unused_count -= ring->pending_buf;
4464
4465 while (recv_pkts < budget) {
4466 /* Reuse or realloc buffers */
4467 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
4468 failure = failure ||
4469 hns3_nic_alloc_rx_buffers(ring, unused_count);
4470 unused_count = 0;
4471 }
4472
4473 /* Poll one pkt */
4474 err = hns3_handle_rx_bd(ring);
4475 /* Do not get FE for the packet or failed to alloc skb */
4476 if (unlikely(!ring->skb || err == -ENXIO)) {
4477 goto out;
4478 } else if (likely(!err)) {
4479 rx_fn(ring, ring->skb);
4480 recv_pkts++;
4481 }
4482
4483 unused_count += ring->pending_buf;
4484 ring->skb = NULL;
4485 ring->pending_buf = 0;
4486 }
4487
4488 out:
4489 /* sync head pointer before exiting, since hardware will calculate
4490 * FBD number with head pointer
4491 */
4492 if (unused_count > 0)
4493 failure = failure ||
4494 hns3_nic_alloc_rx_buffers(ring, unused_count);
4495
4496 return failure ? budget : recv_pkts;
4497 }
4498
hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4499 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4500 {
4501 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group;
4502 struct dim_sample sample = {};
4503
4504 if (!rx_group->coal.adapt_enable)
4505 return;
4506
4507 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets,
4508 rx_group->total_bytes, &sample);
4509 net_dim(&rx_group->dim, &sample);
4510 }
4511
hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector * tqp_vector)4512 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector)
4513 {
4514 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group;
4515 struct dim_sample sample = {};
4516
4517 if (!tx_group->coal.adapt_enable)
4518 return;
4519
4520 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets,
4521 tx_group->total_bytes, &sample);
4522 net_dim(&tx_group->dim, &sample);
4523 }
4524
hns3_nic_common_poll(struct napi_struct * napi,int budget)4525 static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
4526 {
4527 struct hns3_nic_priv *priv = netdev_priv(napi->dev);
4528 struct hns3_enet_ring *ring;
4529 int rx_pkt_total = 0;
4530
4531 struct hns3_enet_tqp_vector *tqp_vector =
4532 container_of(napi, struct hns3_enet_tqp_vector, napi);
4533 bool clean_complete = true;
4534 int rx_budget = budget;
4535
4536 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4537 napi_complete(napi);
4538 return 0;
4539 }
4540
4541 /* Since the actual Tx work is minimal, we can give the Tx a larger
4542 * budget and be more aggressive about cleaning up the Tx descriptors.
4543 */
4544 hns3_for_each_ring(ring, tqp_vector->tx_group)
4545 hns3_clean_tx_ring(ring, budget);
4546
4547 /* make sure rx ring budget not smaller than 1 */
4548 if (tqp_vector->num_tqps > 1)
4549 rx_budget = max(budget / tqp_vector->num_tqps, 1);
4550
4551 hns3_for_each_ring(ring, tqp_vector->rx_group) {
4552 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
4553 hns3_rx_skb);
4554 if (rx_cleaned >= rx_budget)
4555 clean_complete = false;
4556
4557 rx_pkt_total += rx_cleaned;
4558 }
4559
4560 tqp_vector->rx_group.total_packets += rx_pkt_total;
4561
4562 if (!clean_complete)
4563 return budget;
4564
4565 if (napi_complete(napi) &&
4566 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) {
4567 hns3_update_rx_int_coalesce(tqp_vector);
4568 hns3_update_tx_int_coalesce(tqp_vector);
4569
4570 hns3_mask_vector_irq(tqp_vector, 1);
4571 }
4572
4573 return rx_pkt_total;
4574 }
4575
hns3_create_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node ** head,bool is_tx)4576 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4577 struct hnae3_ring_chain_node **head,
4578 bool is_tx)
4579 {
4580 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX;
4581 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX;
4582 struct hnae3_ring_chain_node *cur_chain = *head;
4583 struct pci_dev *pdev = tqp_vector->handle->pdev;
4584 struct hnae3_ring_chain_node *chain;
4585 struct hns3_enet_ring *ring;
4586
4587 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring;
4588
4589 if (cur_chain) {
4590 while (cur_chain->next)
4591 cur_chain = cur_chain->next;
4592 }
4593
4594 while (ring) {
4595 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL);
4596 if (!chain)
4597 return -ENOMEM;
4598 if (cur_chain)
4599 cur_chain->next = chain;
4600 else
4601 *head = chain;
4602 chain->tqp_index = ring->tqp->tqp_index;
4603 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B,
4604 bit_value);
4605 hnae3_set_field(chain->int_gl_idx,
4606 HNAE3_RING_GL_IDX_M,
4607 HNAE3_RING_GL_IDX_S, field_value);
4608
4609 cur_chain = chain;
4610
4611 ring = ring->next;
4612 }
4613
4614 return 0;
4615 }
4616
4617 static struct hnae3_ring_chain_node *
hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector)4618 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector)
4619 {
4620 struct pci_dev *pdev = tqp_vector->handle->pdev;
4621 struct hnae3_ring_chain_node *cur_chain = NULL;
4622 struct hnae3_ring_chain_node *chain;
4623
4624 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true))
4625 goto err_free_chain;
4626
4627 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false))
4628 goto err_free_chain;
4629
4630 return cur_chain;
4631
4632 err_free_chain:
4633 while (cur_chain) {
4634 chain = cur_chain->next;
4635 devm_kfree(&pdev->dev, cur_chain);
4636 cur_chain = chain;
4637 }
4638
4639 return NULL;
4640 }
4641
hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector * tqp_vector,struct hnae3_ring_chain_node * head)4642 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector,
4643 struct hnae3_ring_chain_node *head)
4644 {
4645 struct pci_dev *pdev = tqp_vector->handle->pdev;
4646 struct hnae3_ring_chain_node *chain_tmp, *chain;
4647
4648 chain = head;
4649
4650 while (chain) {
4651 chain_tmp = chain->next;
4652 devm_kfree(&pdev->dev, chain);
4653 chain = chain_tmp;
4654 }
4655 }
4656
hns3_add_ring_to_group(struct hns3_enet_ring_group * group,struct hns3_enet_ring * ring)4657 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group,
4658 struct hns3_enet_ring *ring)
4659 {
4660 ring->next = group->ring;
4661 group->ring = ring;
4662
4663 group->count++;
4664 }
4665
hns3_nic_set_cpumask(struct hns3_nic_priv * priv)4666 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv)
4667 {
4668 struct pci_dev *pdev = priv->ae_handle->pdev;
4669 struct hns3_enet_tqp_vector *tqp_vector;
4670 int num_vectors = priv->vector_num;
4671 int numa_node;
4672 int vector_i;
4673
4674 numa_node = dev_to_node(&pdev->dev);
4675
4676 for (vector_i = 0; vector_i < num_vectors; vector_i++) {
4677 tqp_vector = &priv->tqp_vector[vector_i];
4678 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node),
4679 &tqp_vector->affinity_mask);
4680 }
4681 }
4682
hns3_rx_dim_work(struct work_struct * work)4683 static void hns3_rx_dim_work(struct work_struct *work)
4684 {
4685 struct dim *dim = container_of(work, struct dim, work);
4686 struct hns3_enet_ring_group *group = container_of(dim,
4687 struct hns3_enet_ring_group, dim);
4688 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4689 struct dim_cq_moder cur_moder =
4690 net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
4691
4692 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec);
4693 tqp_vector->rx_group.coal.int_gl = cur_moder.usec;
4694
4695 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) {
4696 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts);
4697 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts;
4698 }
4699
4700 dim->state = DIM_START_MEASURE;
4701 }
4702
hns3_tx_dim_work(struct work_struct * work)4703 static void hns3_tx_dim_work(struct work_struct *work)
4704 {
4705 struct dim *dim = container_of(work, struct dim, work);
4706 struct hns3_enet_ring_group *group = container_of(dim,
4707 struct hns3_enet_ring_group, dim);
4708 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector;
4709 struct dim_cq_moder cur_moder =
4710 net_dim_get_tx_moderation(dim->mode, dim->profile_ix);
4711
4712 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec);
4713 tqp_vector->tx_group.coal.int_gl = cur_moder.usec;
4714
4715 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) {
4716 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts);
4717 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts;
4718 }
4719
4720 dim->state = DIM_START_MEASURE;
4721 }
4722
hns3_nic_init_dim(struct hns3_enet_tqp_vector * tqp_vector)4723 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector)
4724 {
4725 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work);
4726 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work);
4727 }
4728
hns3_nic_init_vector_data(struct hns3_nic_priv * priv)4729 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
4730 {
4731 struct hnae3_handle *h = priv->ae_handle;
4732 struct hns3_enet_tqp_vector *tqp_vector;
4733 int ret;
4734 int i;
4735
4736 hns3_nic_set_cpumask(priv);
4737
4738 for (i = 0; i < priv->vector_num; i++) {
4739 tqp_vector = &priv->tqp_vector[i];
4740 hns3_vector_coalesce_init_hw(tqp_vector, priv);
4741 tqp_vector->num_tqps = 0;
4742 hns3_nic_init_dim(tqp_vector);
4743 }
4744
4745 for (i = 0; i < h->kinfo.num_tqps; i++) {
4746 u16 vector_i = i % priv->vector_num;
4747 u16 tqp_num = h->kinfo.num_tqps;
4748
4749 tqp_vector = &priv->tqp_vector[vector_i];
4750
4751 hns3_add_ring_to_group(&tqp_vector->tx_group,
4752 &priv->ring[i]);
4753
4754 hns3_add_ring_to_group(&tqp_vector->rx_group,
4755 &priv->ring[i + tqp_num]);
4756
4757 priv->ring[i].tqp_vector = tqp_vector;
4758 priv->ring[i + tqp_num].tqp_vector = tqp_vector;
4759 tqp_vector->num_tqps++;
4760 }
4761
4762 for (i = 0; i < priv->vector_num; i++) {
4763 struct hnae3_ring_chain_node *vector_ring_chain;
4764
4765 tqp_vector = &priv->tqp_vector[i];
4766
4767 tqp_vector->rx_group.total_bytes = 0;
4768 tqp_vector->rx_group.total_packets = 0;
4769 tqp_vector->tx_group.total_bytes = 0;
4770 tqp_vector->tx_group.total_packets = 0;
4771 tqp_vector->handle = h;
4772
4773 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4774 if (!vector_ring_chain) {
4775 ret = -ENOMEM;
4776 goto map_ring_fail;
4777 }
4778
4779 ret = h->ae_algo->ops->map_ring_to_vector(h,
4780 tqp_vector->vector_irq, vector_ring_chain);
4781
4782 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4783
4784 if (ret)
4785 goto map_ring_fail;
4786
4787 netif_napi_add(priv->netdev, &tqp_vector->napi,
4788 hns3_nic_common_poll);
4789 }
4790
4791 return 0;
4792
4793 map_ring_fail:
4794 while (i--)
4795 netif_napi_del(&priv->tqp_vector[i].napi);
4796
4797 return ret;
4798 }
4799
hns3_nic_init_coal_cfg(struct hns3_nic_priv * priv)4800 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
4801 {
4802 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4803 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
4804 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
4805
4806 /* initialize the configuration for interrupt coalescing.
4807 * 1. GL (Interrupt Gap Limiter)
4808 * 2. RL (Interrupt Rate Limiter)
4809 * 3. QL (Interrupt Quantity Limiter)
4810 *
4811 * Default: enable interrupt coalescing self-adaptive and GL
4812 */
4813 tx_coal->adapt_enable = 1;
4814 rx_coal->adapt_enable = 1;
4815
4816 tx_coal->int_gl = HNS3_INT_GL_50K;
4817 rx_coal->int_gl = HNS3_INT_GL_50K;
4818
4819 rx_coal->flow_level = HNS3_FLOW_LOW;
4820 tx_coal->flow_level = HNS3_FLOW_LOW;
4821
4822 if (ae_dev->dev_specs.int_ql_max) {
4823 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4824 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
4825 }
4826 }
4827
hns3_nic_alloc_vector_data(struct hns3_nic_priv * priv)4828 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
4829 {
4830 struct hnae3_handle *h = priv->ae_handle;
4831 struct hns3_enet_tqp_vector *tqp_vector;
4832 struct hnae3_vector_info *vector;
4833 struct pci_dev *pdev = h->pdev;
4834 u16 tqp_num = h->kinfo.num_tqps;
4835 u16 vector_num;
4836 int ret = 0;
4837 u16 i;
4838
4839 /* RSS size, cpu online and vector_num should be the same */
4840 /* Should consider 2p/4p later */
4841 vector_num = min_t(u16, num_online_cpus(), tqp_num);
4842
4843 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
4844 GFP_KERNEL);
4845 if (!vector)
4846 return -ENOMEM;
4847
4848 /* save the actual available vector number */
4849 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector);
4850
4851 priv->vector_num = vector_num;
4852 priv->tqp_vector = (struct hns3_enet_tqp_vector *)
4853 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector),
4854 GFP_KERNEL);
4855 if (!priv->tqp_vector) {
4856 ret = -ENOMEM;
4857 goto out;
4858 }
4859
4860 for (i = 0; i < priv->vector_num; i++) {
4861 tqp_vector = &priv->tqp_vector[i];
4862 tqp_vector->idx = i;
4863 tqp_vector->mask_addr = vector[i].io_addr;
4864 tqp_vector->vector_irq = vector[i].vector;
4865 hns3_vector_coalesce_init(tqp_vector, priv);
4866 }
4867
4868 out:
4869 devm_kfree(&pdev->dev, vector);
4870 return ret;
4871 }
4872
hns3_clear_ring_group(struct hns3_enet_ring_group * group)4873 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group)
4874 {
4875 group->ring = NULL;
4876 group->count = 0;
4877 }
4878
hns3_nic_uninit_vector_data(struct hns3_nic_priv * priv)4879 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv)
4880 {
4881 struct hnae3_ring_chain_node *vector_ring_chain;
4882 struct hnae3_handle *h = priv->ae_handle;
4883 struct hns3_enet_tqp_vector *tqp_vector;
4884 int i;
4885
4886 for (i = 0; i < priv->vector_num; i++) {
4887 tqp_vector = &priv->tqp_vector[i];
4888
4889 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring)
4890 continue;
4891
4892 /* Since the mapping can be overwritten, when fail to get the
4893 * chain between vector and ring, we should go on to deal with
4894 * the remaining options.
4895 */
4896 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector);
4897 if (!vector_ring_chain)
4898 dev_warn(priv->dev, "failed to get ring chain\n");
4899
4900 h->ae_algo->ops->unmap_ring_from_vector(h,
4901 tqp_vector->vector_irq, vector_ring_chain);
4902
4903 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain);
4904
4905 hns3_clear_ring_group(&tqp_vector->rx_group);
4906 hns3_clear_ring_group(&tqp_vector->tx_group);
4907 netif_napi_del(&priv->tqp_vector[i].napi);
4908 }
4909 }
4910
hns3_nic_dealloc_vector_data(struct hns3_nic_priv * priv)4911 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv)
4912 {
4913 struct hnae3_handle *h = priv->ae_handle;
4914 struct pci_dev *pdev = h->pdev;
4915 int i, ret;
4916
4917 for (i = 0; i < priv->vector_num; i++) {
4918 struct hns3_enet_tqp_vector *tqp_vector;
4919
4920 tqp_vector = &priv->tqp_vector[i];
4921 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq);
4922 if (ret)
4923 return;
4924 }
4925
4926 devm_kfree(&pdev->dev, priv->tqp_vector);
4927 }
4928
hns3_update_tx_spare_buf_config(struct hns3_nic_priv * priv)4929 static void hns3_update_tx_spare_buf_config(struct hns3_nic_priv *priv)
4930 {
4931 #define HNS3_MIN_SPARE_BUF_SIZE (2 * 1024 * 1024)
4932 #define HNS3_MAX_PACKET_SIZE (64 * 1024)
4933
4934 struct iommu_domain *domain = iommu_get_domain_for_dev(priv->dev);
4935 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
4936 struct hnae3_handle *handle = priv->ae_handle;
4937
4938 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3)
4939 return;
4940
4941 if (!(domain && iommu_is_dma_domain(domain)))
4942 return;
4943
4944 priv->min_tx_copybreak = HNS3_MAX_PACKET_SIZE;
4945 priv->min_tx_spare_buf_size = HNS3_MIN_SPARE_BUF_SIZE;
4946
4947 if (priv->tx_copybreak < priv->min_tx_copybreak)
4948 priv->tx_copybreak = priv->min_tx_copybreak;
4949 if (handle->kinfo.tx_spare_buf_size < priv->min_tx_spare_buf_size)
4950 handle->kinfo.tx_spare_buf_size = priv->min_tx_spare_buf_size;
4951 }
4952
hns3_ring_get_cfg(struct hnae3_queue * q,struct hns3_nic_priv * priv,unsigned int ring_type)4953 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
4954 unsigned int ring_type)
4955 {
4956 int queue_num = priv->ae_handle->kinfo.num_tqps;
4957 struct hns3_enet_ring *ring;
4958 int desc_num;
4959
4960 if (ring_type == HNAE3_RING_TYPE_TX) {
4961 ring = &priv->ring[q->tqp_index];
4962 desc_num = priv->ae_handle->kinfo.num_tx_desc;
4963 ring->queue_index = q->tqp_index;
4964 ring->tx_copybreak = priv->tx_copybreak;
4965 ring->last_to_use = 0;
4966 } else {
4967 ring = &priv->ring[q->tqp_index + queue_num];
4968 desc_num = priv->ae_handle->kinfo.num_rx_desc;
4969 ring->queue_index = q->tqp_index;
4970 ring->rx_copybreak = priv->rx_copybreak;
4971 }
4972
4973 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
4974
4975 ring->tqp = q;
4976 ring->desc = NULL;
4977 ring->desc_cb = NULL;
4978 ring->dev = priv->dev;
4979 ring->desc_dma_addr = 0;
4980 ring->buf_size = q->buf_size;
4981 ring->desc_num = desc_num;
4982 ring->next_to_use = 0;
4983 ring->next_to_clean = 0;
4984 }
4985
hns3_queue_to_ring(struct hnae3_queue * tqp,struct hns3_nic_priv * priv)4986 static void hns3_queue_to_ring(struct hnae3_queue *tqp,
4987 struct hns3_nic_priv *priv)
4988 {
4989 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX);
4990 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX);
4991 }
4992
hns3_get_ring_config(struct hns3_nic_priv * priv)4993 static int hns3_get_ring_config(struct hns3_nic_priv *priv)
4994 {
4995 struct hnae3_handle *h = priv->ae_handle;
4996 struct pci_dev *pdev = h->pdev;
4997 int i;
4998
4999 priv->ring = devm_kzalloc(&pdev->dev,
5000 array3_size(h->kinfo.num_tqps,
5001 sizeof(*priv->ring), 2),
5002 GFP_KERNEL);
5003 if (!priv->ring)
5004 return -ENOMEM;
5005
5006 for (i = 0; i < h->kinfo.num_tqps; i++)
5007 hns3_queue_to_ring(h->kinfo.tqp[i], priv);
5008
5009 return 0;
5010 }
5011
hns3_put_ring_config(struct hns3_nic_priv * priv)5012 static void hns3_put_ring_config(struct hns3_nic_priv *priv)
5013 {
5014 if (!priv->ring)
5015 return;
5016
5017 devm_kfree(priv->dev, priv->ring);
5018 priv->ring = NULL;
5019 }
5020
hns3_alloc_page_pool(struct hns3_enet_ring * ring)5021 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring)
5022 {
5023 struct page_pool_params pp_params = {
5024 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
5025 .order = hns3_page_order(ring),
5026 .pool_size = ring->desc_num * hns3_buf_size(ring) /
5027 (PAGE_SIZE << hns3_page_order(ring)),
5028 .nid = dev_to_node(ring_to_dev(ring)),
5029 .dev = ring_to_dev(ring),
5030 .dma_dir = DMA_FROM_DEVICE,
5031 .offset = 0,
5032 .max_len = PAGE_SIZE << hns3_page_order(ring),
5033 };
5034
5035 ring->page_pool = page_pool_create(&pp_params);
5036 if (IS_ERR(ring->page_pool)) {
5037 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n",
5038 PTR_ERR(ring->page_pool));
5039 ring->page_pool = NULL;
5040 }
5041 }
5042
hns3_alloc_ring_memory(struct hns3_enet_ring * ring)5043 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
5044 {
5045 int ret;
5046
5047 if (ring->desc_num <= 0 || ring->buf_size <= 0)
5048 return -EINVAL;
5049
5050 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num,
5051 sizeof(ring->desc_cb[0]), GFP_KERNEL);
5052 if (!ring->desc_cb) {
5053 ret = -ENOMEM;
5054 goto out;
5055 }
5056
5057 ret = hns3_alloc_desc(ring);
5058 if (ret)
5059 goto out_with_desc_cb;
5060
5061 if (!HNAE3_IS_TX_RING(ring)) {
5062 if (page_pool_enabled)
5063 hns3_alloc_page_pool(ring);
5064
5065 ret = hns3_alloc_ring_buffers(ring);
5066 if (ret)
5067 goto out_with_desc;
5068 } else {
5069 hns3_init_tx_spare_buffer(ring);
5070 }
5071
5072 return 0;
5073
5074 out_with_desc:
5075 hns3_free_desc(ring);
5076 out_with_desc_cb:
5077 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5078 ring->desc_cb = NULL;
5079 out:
5080 return ret;
5081 }
5082
hns3_fini_ring(struct hns3_enet_ring * ring)5083 void hns3_fini_ring(struct hns3_enet_ring *ring)
5084 {
5085 hns3_free_desc(ring);
5086 devm_kfree(ring_to_dev(ring), ring->desc_cb);
5087 ring->desc_cb = NULL;
5088 ring->next_to_clean = 0;
5089 ring->next_to_use = 0;
5090 ring->last_to_use = 0;
5091 ring->pending_buf = 0;
5092 if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
5093 dev_kfree_skb_any(ring->skb);
5094 ring->skb = NULL;
5095 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
5096 struct hns3_tx_spare *tx_spare = ring->tx_spare;
5097
5098 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
5099 DMA_TO_DEVICE);
5100 free_pages((unsigned long)tx_spare->buf,
5101 get_order(tx_spare->len));
5102 devm_kfree(ring_to_dev(ring), tx_spare);
5103 ring->tx_spare = NULL;
5104 }
5105
5106 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) {
5107 page_pool_destroy(ring->page_pool);
5108 ring->page_pool = NULL;
5109 }
5110 }
5111
hns3_buf_size2type(u32 buf_size)5112 static int hns3_buf_size2type(u32 buf_size)
5113 {
5114 int bd_size_type;
5115
5116 switch (buf_size) {
5117 case 512:
5118 bd_size_type = HNS3_BD_SIZE_512_TYPE;
5119 break;
5120 case 1024:
5121 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
5122 break;
5123 case 2048:
5124 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5125 break;
5126 case 4096:
5127 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
5128 break;
5129 default:
5130 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
5131 }
5132
5133 return bd_size_type;
5134 }
5135
hns3_init_ring_hw(struct hns3_enet_ring * ring)5136 static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
5137 {
5138 dma_addr_t dma = ring->desc_dma_addr;
5139 struct hnae3_queue *q = ring->tqp;
5140
5141 if (!HNAE3_IS_TX_RING(ring)) {
5142 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma);
5143 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG,
5144 (u32)((dma >> 31) >> 1));
5145
5146 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG,
5147 hns3_buf_size2type(ring->buf_size));
5148 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
5149 ring->desc_num / 8 - 1);
5150 } else {
5151 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
5152 (u32)dma);
5153 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG,
5154 (u32)((dma >> 31) >> 1));
5155
5156 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG,
5157 ring->desc_num / 8 - 1);
5158 }
5159 }
5160
hns3_init_tx_ring_tc(struct hns3_nic_priv * priv)5161 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv)
5162 {
5163 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5164 struct hnae3_tc_info *tc_info = &kinfo->tc_info;
5165 int i;
5166
5167 for (i = 0; i < tc_info->num_tc; i++) {
5168 int j;
5169
5170 for (j = 0; j < tc_info->tqp_count[i]; j++) {
5171 struct hnae3_queue *q;
5172
5173 q = priv->ring[tc_info->tqp_offset[i] + j].tqp;
5174 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i);
5175 }
5176 }
5177 }
5178
hns3_init_all_ring(struct hns3_nic_priv * priv)5179 int hns3_init_all_ring(struct hns3_nic_priv *priv)
5180 {
5181 struct hnae3_handle *h = priv->ae_handle;
5182 int ring_num = h->kinfo.num_tqps * 2;
5183 int i, j;
5184 int ret;
5185
5186 hns3_update_tx_spare_buf_config(priv);
5187 for (i = 0; i < ring_num; i++) {
5188 ret = hns3_alloc_ring_memory(&priv->ring[i]);
5189 if (ret) {
5190 dev_err(priv->dev,
5191 "Alloc ring memory fail! ret=%d\n", ret);
5192 goto out_when_alloc_ring_memory;
5193 }
5194
5195 u64_stats_init(&priv->ring[i].syncp);
5196 cond_resched();
5197 }
5198
5199 return 0;
5200
5201 out_when_alloc_ring_memory:
5202 for (j = i - 1; j >= 0; j--)
5203 hns3_fini_ring(&priv->ring[j]);
5204
5205 return -ENOMEM;
5206 }
5207
hns3_uninit_all_ring(struct hns3_nic_priv * priv)5208 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv)
5209 {
5210 struct hnae3_handle *h = priv->ae_handle;
5211 int i;
5212
5213 for (i = 0; i < h->kinfo.num_tqps; i++) {
5214 hns3_fini_ring(&priv->ring[i]);
5215 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]);
5216 }
5217 }
5218
5219 /* Set mac addr if it is configured. or leave it to the AE driver */
hns3_init_mac_addr(struct net_device * netdev)5220 static int hns3_init_mac_addr(struct net_device *netdev)
5221 {
5222 struct hns3_nic_priv *priv = netdev_priv(netdev);
5223 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5224 struct hnae3_handle *h = priv->ae_handle;
5225 u8 mac_addr_temp[ETH_ALEN] = {0};
5226 int ret = 0;
5227
5228 if (h->ae_algo->ops->get_mac_addr)
5229 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp);
5230
5231 /* Check if the MAC address is valid, if not get a random one */
5232 if (!is_valid_ether_addr(mac_addr_temp)) {
5233 eth_hw_addr_random(netdev);
5234 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr);
5235 dev_warn(priv->dev, "using random MAC address %s\n",
5236 format_mac_addr);
5237 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) {
5238 eth_hw_addr_set(netdev, mac_addr_temp);
5239 ether_addr_copy(netdev->perm_addr, mac_addr_temp);
5240 } else {
5241 return 0;
5242 }
5243
5244 if (h->ae_algo->ops->set_mac_addr)
5245 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true);
5246
5247 return ret;
5248 }
5249
hns3_init_phy(struct net_device * netdev)5250 static int hns3_init_phy(struct net_device *netdev)
5251 {
5252 struct hnae3_handle *h = hns3_get_handle(netdev);
5253 int ret = 0;
5254
5255 if (h->ae_algo->ops->mac_connect_phy)
5256 ret = h->ae_algo->ops->mac_connect_phy(h);
5257
5258 return ret;
5259 }
5260
hns3_uninit_phy(struct net_device * netdev)5261 static void hns3_uninit_phy(struct net_device *netdev)
5262 {
5263 struct hnae3_handle *h = hns3_get_handle(netdev);
5264
5265 if (h->ae_algo->ops->mac_disconnect_phy)
5266 h->ae_algo->ops->mac_disconnect_phy(h);
5267 }
5268
hns3_client_start(struct hnae3_handle * handle)5269 static int hns3_client_start(struct hnae3_handle *handle)
5270 {
5271 if (!handle->ae_algo->ops->client_start)
5272 return 0;
5273
5274 return handle->ae_algo->ops->client_start(handle);
5275 }
5276
hns3_client_stop(struct hnae3_handle * handle)5277 static void hns3_client_stop(struct hnae3_handle *handle)
5278 {
5279 if (!handle->ae_algo->ops->client_stop)
5280 return;
5281
5282 handle->ae_algo->ops->client_stop(handle);
5283 }
5284
hns3_info_show(struct hns3_nic_priv * priv)5285 static void hns3_info_show(struct hns3_nic_priv *priv)
5286 {
5287 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
5288 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
5289
5290 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr);
5291 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr);
5292 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
5293 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
5294 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
5295 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
5296 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
5297 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
5298 dev_info(priv->dev, "Total number of enabled TCs: %u\n",
5299 kinfo->tc_info.num_tc);
5300 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
5301 }
5302
hns3_set_cq_period_mode(struct hns3_nic_priv * priv,enum dim_cq_period_mode mode,bool is_tx)5303 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv,
5304 enum dim_cq_period_mode mode, bool is_tx)
5305 {
5306 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle);
5307 struct hnae3_handle *handle = priv->ae_handle;
5308 int i;
5309
5310 if (is_tx) {
5311 priv->tx_cqe_mode = mode;
5312
5313 for (i = 0; i < priv->vector_num; i++)
5314 priv->tqp_vector[i].tx_group.dim.mode = mode;
5315 } else {
5316 priv->rx_cqe_mode = mode;
5317
5318 for (i = 0; i < priv->vector_num; i++)
5319 priv->tqp_vector[i].rx_group.dim.mode = mode;
5320 }
5321
5322 if (hnae3_ae_dev_cq_supported(ae_dev)) {
5323 u32 new_mode;
5324 u64 reg;
5325
5326 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ?
5327 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE;
5328 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG;
5329
5330 writel(new_mode, handle->kinfo.io_base + reg);
5331 }
5332 }
5333
hns3_cq_period_mode_init(struct hns3_nic_priv * priv,enum dim_cq_period_mode tx_mode,enum dim_cq_period_mode rx_mode)5334 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
5335 enum dim_cq_period_mode tx_mode,
5336 enum dim_cq_period_mode rx_mode)
5337 {
5338 hns3_set_cq_period_mode(priv, tx_mode, true);
5339 hns3_set_cq_period_mode(priv, rx_mode, false);
5340 }
5341
hns3_state_init(struct hnae3_handle * handle)5342 static void hns3_state_init(struct hnae3_handle *handle)
5343 {
5344 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
5345 struct net_device *netdev = handle->kinfo.netdev;
5346 struct hns3_nic_priv *priv = netdev_priv(netdev);
5347
5348 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5349
5350 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
5351 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
5352
5353 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
5354 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
5355
5356 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
5357 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
5358
5359 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
5360 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
5361 }
5362
hns3_state_uninit(struct hnae3_handle * handle)5363 static void hns3_state_uninit(struct hnae3_handle *handle)
5364 {
5365 struct hns3_nic_priv *priv = handle->priv;
5366
5367 clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
5368 }
5369
hns3_client_init(struct hnae3_handle * handle)5370 static int hns3_client_init(struct hnae3_handle *handle)
5371 {
5372 struct pci_dev *pdev = handle->pdev;
5373 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
5374 u16 alloc_tqps, max_rss_size;
5375 struct hns3_nic_priv *priv;
5376 struct net_device *netdev;
5377 int ret;
5378
5379 ae_dev->handle = handle;
5380
5381 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps,
5382 &max_rss_size);
5383 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps);
5384 if (!netdev)
5385 return -ENOMEM;
5386
5387 priv = netdev_priv(netdev);
5388 priv->dev = &pdev->dev;
5389 priv->netdev = netdev;
5390 priv->ae_handle = handle;
5391 priv->tx_timeout_count = 0;
5392 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num;
5393 priv->min_tx_copybreak = 0;
5394 priv->min_tx_spare_buf_size = 0;
5395 set_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5396
5397 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL);
5398
5399 handle->kinfo.netdev = netdev;
5400 handle->priv = (void *)priv;
5401
5402 hns3_init_mac_addr(netdev);
5403
5404 hns3_set_default_feature(netdev);
5405
5406 netdev->watchdog_timeo = HNS3_TX_TIMEOUT;
5407 netdev->priv_flags |= IFF_UNICAST_FLT;
5408 netdev->netdev_ops = &hns3_nic_netdev_ops;
5409 SET_NETDEV_DEV(netdev, &pdev->dev);
5410 hns3_ethtool_set_ops(netdev);
5411
5412 /* Carrier off reporting is important to ethtool even BEFORE open */
5413 netif_carrier_off(netdev);
5414
5415 ret = hns3_get_ring_config(priv);
5416 if (ret) {
5417 ret = -ENOMEM;
5418 goto out_get_ring_cfg;
5419 }
5420
5421 hns3_nic_init_coal_cfg(priv);
5422
5423 ret = hns3_nic_alloc_vector_data(priv);
5424 if (ret) {
5425 ret = -ENOMEM;
5426 goto out_alloc_vector_data;
5427 }
5428
5429 ret = hns3_nic_init_vector_data(priv);
5430 if (ret) {
5431 ret = -ENOMEM;
5432 goto out_init_vector_data;
5433 }
5434
5435 ret = hns3_init_all_ring(priv);
5436 if (ret) {
5437 ret = -ENOMEM;
5438 goto out_init_ring;
5439 }
5440
5441 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE,
5442 DIM_CQ_PERIOD_MODE_START_FROM_EQE);
5443
5444 ret = hns3_init_phy(netdev);
5445 if (ret)
5446 goto out_init_phy;
5447
5448 /* the device can work without cpu rmap, only aRFS needs it */
5449 ret = hns3_set_rx_cpu_rmap(netdev);
5450 if (ret)
5451 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5452
5453 ret = hns3_nic_init_irq(priv);
5454 if (ret) {
5455 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5456 hns3_free_rx_cpu_rmap(netdev);
5457 goto out_init_irq_fail;
5458 }
5459
5460 ret = hns3_client_start(handle);
5461 if (ret) {
5462 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5463 goto out_client_start;
5464 }
5465
5466 hns3_dcbnl_setup(handle);
5467
5468 ret = hns3_dbg_init(handle);
5469 if (ret) {
5470 dev_err(priv->dev, "failed to init debugfs, ret = %d\n",
5471 ret);
5472 goto out_client_start;
5473 }
5474
5475 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size);
5476
5477 hns3_state_init(handle);
5478
5479 ret = register_netdev(netdev);
5480 if (ret) {
5481 dev_err(priv->dev, "probe register netdev fail!\n");
5482 goto out_reg_netdev_fail;
5483 }
5484
5485 if (netif_msg_drv(handle))
5486 hns3_info_show(priv);
5487
5488 return ret;
5489
5490 out_reg_netdev_fail:
5491 hns3_state_uninit(handle);
5492 hns3_dbg_uninit(handle);
5493 hns3_client_stop(handle);
5494 out_client_start:
5495 hns3_free_rx_cpu_rmap(netdev);
5496 hns3_nic_uninit_irq(priv);
5497 out_init_irq_fail:
5498 hns3_uninit_phy(netdev);
5499 out_init_phy:
5500 hns3_uninit_all_ring(priv);
5501 out_init_ring:
5502 hns3_nic_uninit_vector_data(priv);
5503 out_init_vector_data:
5504 hns3_nic_dealloc_vector_data(priv);
5505 out_alloc_vector_data:
5506 priv->ring = NULL;
5507 out_get_ring_cfg:
5508 priv->ae_handle = NULL;
5509 free_netdev(netdev);
5510 return ret;
5511 }
5512
hns3_client_uninit(struct hnae3_handle * handle,bool reset)5513 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
5514 {
5515 struct net_device *netdev = handle->kinfo.netdev;
5516 struct hns3_nic_priv *priv = netdev_priv(netdev);
5517
5518 if (netdev->reg_state != NETREG_UNINITIALIZED)
5519 unregister_netdev(netdev);
5520
5521 hns3_client_stop(handle);
5522
5523 hns3_uninit_phy(netdev);
5524
5525 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5526 netdev_warn(netdev, "already uninitialized\n");
5527 goto out_netdev_free;
5528 }
5529
5530 hns3_free_rx_cpu_rmap(netdev);
5531
5532 hns3_nic_uninit_irq(priv);
5533
5534 hns3_clear_all_ring(handle, true);
5535
5536 hns3_nic_uninit_vector_data(priv);
5537
5538 hns3_nic_dealloc_vector_data(priv);
5539
5540 hns3_uninit_all_ring(priv);
5541
5542 hns3_put_ring_config(priv);
5543
5544 out_netdev_free:
5545 hns3_dbg_uninit(handle);
5546 free_netdev(netdev);
5547 }
5548
hns3_link_status_change(struct hnae3_handle * handle,bool linkup)5549 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup)
5550 {
5551 struct net_device *netdev = handle->kinfo.netdev;
5552
5553 if (!netdev)
5554 return;
5555
5556 if (linkup) {
5557 netif_tx_wake_all_queues(netdev);
5558 netif_carrier_on(netdev);
5559 if (netif_msg_link(handle))
5560 netdev_info(netdev, "link up\n");
5561 } else {
5562 netif_carrier_off(netdev);
5563 netif_tx_stop_all_queues(netdev);
5564 if (netif_msg_link(handle))
5565 netdev_info(netdev, "link down\n");
5566 }
5567 }
5568
hns3_clear_tx_ring(struct hns3_enet_ring * ring)5569 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring)
5570 {
5571 while (ring->next_to_clean != ring->next_to_use) {
5572 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0;
5573 hns3_free_buffer_detach(ring, ring->next_to_clean, 0);
5574 ring_ptr_move_fw(ring, next_to_clean);
5575 }
5576
5577 ring->pending_buf = 0;
5578 }
5579
hns3_clear_rx_ring(struct hns3_enet_ring * ring)5580 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring)
5581 {
5582 struct hns3_desc_cb res_cbs;
5583 int ret;
5584
5585 while (ring->next_to_use != ring->next_to_clean) {
5586 /* When a buffer is not reused, it's memory has been
5587 * freed in hns3_handle_rx_bd or will be freed by
5588 * stack, so we need to replace the buffer here.
5589 */
5590 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5591 ret = hns3_alloc_and_map_buffer(ring, &res_cbs);
5592 if (ret) {
5593 hns3_ring_stats_update(ring, sw_err_cnt);
5594 /* if alloc new buffer fail, exit directly
5595 * and reclear in up flow.
5596 */
5597 netdev_warn(ring_to_netdev(ring),
5598 "reserve buffer map failed, ret = %d\n",
5599 ret);
5600 return ret;
5601 }
5602 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
5603 }
5604 ring_ptr_move_fw(ring, next_to_use);
5605 }
5606
5607 /* Free the pending skb in rx ring */
5608 if (ring->skb) {
5609 dev_kfree_skb_any(ring->skb);
5610 ring->skb = NULL;
5611 ring->pending_buf = 0;
5612 }
5613
5614 return 0;
5615 }
5616
hns3_force_clear_rx_ring(struct hns3_enet_ring * ring)5617 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring)
5618 {
5619 while (ring->next_to_use != ring->next_to_clean) {
5620 /* When a buffer is not reused, it's memory has been
5621 * freed in hns3_handle_rx_bd or will be freed by
5622 * stack, so only need to unmap the buffer here.
5623 */
5624 if (!ring->desc_cb[ring->next_to_use].reuse_flag) {
5625 hns3_unmap_buffer(ring,
5626 &ring->desc_cb[ring->next_to_use]);
5627 ring->desc_cb[ring->next_to_use].dma = 0;
5628 }
5629
5630 ring_ptr_move_fw(ring, next_to_use);
5631 }
5632 }
5633
hns3_clear_all_ring(struct hnae3_handle * h,bool force)5634 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force)
5635 {
5636 struct net_device *ndev = h->kinfo.netdev;
5637 struct hns3_nic_priv *priv = netdev_priv(ndev);
5638 u32 i;
5639
5640 for (i = 0; i < h->kinfo.num_tqps; i++) {
5641 struct hns3_enet_ring *ring;
5642
5643 ring = &priv->ring[i];
5644 hns3_clear_tx_ring(ring);
5645
5646 ring = &priv->ring[i + h->kinfo.num_tqps];
5647 /* Continue to clear other rings even if clearing some
5648 * rings failed.
5649 */
5650 if (force)
5651 hns3_force_clear_rx_ring(ring);
5652 else
5653 hns3_clear_rx_ring(ring);
5654 }
5655 }
5656
hns3_nic_reset_all_ring(struct hnae3_handle * h)5657 int hns3_nic_reset_all_ring(struct hnae3_handle *h)
5658 {
5659 struct net_device *ndev = h->kinfo.netdev;
5660 struct hns3_nic_priv *priv = netdev_priv(ndev);
5661 struct hns3_enet_ring *rx_ring;
5662 int i, j;
5663 int ret;
5664
5665 ret = h->ae_algo->ops->reset_queue(h);
5666 if (ret)
5667 return ret;
5668
5669 for (i = 0; i < h->kinfo.num_tqps; i++) {
5670 hns3_init_ring_hw(&priv->ring[i]);
5671
5672 /* We need to clear tx ring here because self test will
5673 * use the ring and will not run down before up
5674 */
5675 hns3_clear_tx_ring(&priv->ring[i]);
5676 priv->ring[i].next_to_clean = 0;
5677 priv->ring[i].next_to_use = 0;
5678 priv->ring[i].last_to_use = 0;
5679
5680 rx_ring = &priv->ring[i + h->kinfo.num_tqps];
5681 hns3_init_ring_hw(rx_ring);
5682 ret = hns3_clear_rx_ring(rx_ring);
5683 if (ret)
5684 return ret;
5685
5686 /* We can not know the hardware head and tail when this
5687 * function is called in reset flow, so we reuse all desc.
5688 */
5689 for (j = 0; j < rx_ring->desc_num; j++)
5690 hns3_reuse_buffer(rx_ring, j);
5691
5692 rx_ring->next_to_clean = 0;
5693 rx_ring->next_to_use = 0;
5694 }
5695
5696 hns3_init_tx_ring_tc(priv);
5697
5698 return 0;
5699 }
5700
hns3_reset_notify_down_enet(struct hnae3_handle * handle)5701 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
5702 {
5703 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5704 struct net_device *ndev = kinfo->netdev;
5705 struct hns3_nic_priv *priv = netdev_priv(ndev);
5706
5707 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
5708 return 0;
5709
5710 if (!netif_running(ndev))
5711 return 0;
5712
5713 return hns3_nic_net_stop(ndev);
5714 }
5715
hns3_reset_notify_up_enet(struct hnae3_handle * handle)5716 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle)
5717 {
5718 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5719 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev);
5720 int ret = 0;
5721
5722 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5723 netdev_err(kinfo->netdev, "device is not initialized yet\n");
5724 return -EFAULT;
5725 }
5726
5727 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5728
5729 if (netif_running(kinfo->netdev)) {
5730 ret = hns3_nic_net_open(kinfo->netdev);
5731 if (ret) {
5732 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
5733 netdev_err(kinfo->netdev,
5734 "net up fail, ret=%d!\n", ret);
5735 return ret;
5736 }
5737 }
5738
5739 return ret;
5740 }
5741
hns3_reset_notify_init_enet(struct hnae3_handle * handle)5742 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
5743 {
5744 struct net_device *netdev = handle->kinfo.netdev;
5745 struct hns3_nic_priv *priv = netdev_priv(netdev);
5746 int ret;
5747
5748 /* Carrier off reporting is important to ethtool even BEFORE open */
5749 netif_carrier_off(netdev);
5750
5751 ret = hns3_get_ring_config(priv);
5752 if (ret)
5753 return ret;
5754
5755 ret = hns3_nic_alloc_vector_data(priv);
5756 if (ret)
5757 goto err_put_ring;
5758
5759 ret = hns3_nic_init_vector_data(priv);
5760 if (ret)
5761 goto err_dealloc_vector;
5762
5763 ret = hns3_init_all_ring(priv);
5764 if (ret)
5765 goto err_uninit_vector;
5766
5767 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode);
5768
5769 /* the device can work without cpu rmap, only aRFS needs it */
5770 ret = hns3_set_rx_cpu_rmap(netdev);
5771 if (ret)
5772 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret);
5773
5774 ret = hns3_nic_init_irq(priv);
5775 if (ret) {
5776 dev_err(priv->dev, "init irq failed! ret=%d\n", ret);
5777 hns3_free_rx_cpu_rmap(netdev);
5778 goto err_init_irq_fail;
5779 }
5780
5781 if (!hns3_is_phys_func(handle->pdev))
5782 hns3_init_mac_addr(netdev);
5783
5784 ret = hns3_client_start(handle);
5785 if (ret) {
5786 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret);
5787 goto err_client_start_fail;
5788 }
5789
5790 set_bit(HNS3_NIC_STATE_INITED, &priv->state);
5791
5792 return ret;
5793
5794 err_client_start_fail:
5795 hns3_free_rx_cpu_rmap(netdev);
5796 hns3_nic_uninit_irq(priv);
5797 err_init_irq_fail:
5798 hns3_uninit_all_ring(priv);
5799 err_uninit_vector:
5800 hns3_nic_uninit_vector_data(priv);
5801 err_dealloc_vector:
5802 hns3_nic_dealloc_vector_data(priv);
5803 err_put_ring:
5804 hns3_put_ring_config(priv);
5805
5806 return ret;
5807 }
5808
hns3_reset_notify_uninit_enet(struct hnae3_handle * handle)5809 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
5810 {
5811 struct net_device *netdev = handle->kinfo.netdev;
5812 struct hns3_nic_priv *priv = netdev_priv(netdev);
5813
5814 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5815 hns3_nic_net_stop(netdev);
5816
5817 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) {
5818 netdev_warn(netdev, "already uninitialized\n");
5819 return 0;
5820 }
5821
5822 hns3_free_rx_cpu_rmap(netdev);
5823 hns3_nic_uninit_irq(priv);
5824 hns3_clear_all_ring(handle, true);
5825 hns3_reset_tx_queue(priv->ae_handle);
5826
5827 hns3_nic_uninit_vector_data(priv);
5828
5829 hns3_nic_dealloc_vector_data(priv);
5830
5831 hns3_uninit_all_ring(priv);
5832
5833 hns3_put_ring_config(priv);
5834
5835 return 0;
5836 }
5837
hns3_reset_notify(struct hnae3_handle * handle,enum hnae3_reset_notify_type type)5838 int hns3_reset_notify(struct hnae3_handle *handle,
5839 enum hnae3_reset_notify_type type)
5840 {
5841 int ret = 0;
5842
5843 switch (type) {
5844 case HNAE3_UP_CLIENT:
5845 ret = hns3_reset_notify_up_enet(handle);
5846 break;
5847 case HNAE3_DOWN_CLIENT:
5848 ret = hns3_reset_notify_down_enet(handle);
5849 break;
5850 case HNAE3_INIT_CLIENT:
5851 ret = hns3_reset_notify_init_enet(handle);
5852 break;
5853 case HNAE3_UNINIT_CLIENT:
5854 ret = hns3_reset_notify_uninit_enet(handle);
5855 break;
5856 default:
5857 break;
5858 }
5859
5860 return ret;
5861 }
5862
hns3_change_channels(struct hnae3_handle * handle,u32 new_tqp_num,bool rxfh_configured)5863 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num,
5864 bool rxfh_configured)
5865 {
5866 int ret;
5867
5868 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num,
5869 rxfh_configured);
5870 if (ret) {
5871 dev_err(&handle->pdev->dev,
5872 "Change tqp num(%u) fail.\n", new_tqp_num);
5873 return ret;
5874 }
5875
5876 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT);
5877 if (ret)
5878 return ret;
5879
5880 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT);
5881 if (ret)
5882 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT);
5883
5884 return ret;
5885 }
5886
hns3_set_channels(struct net_device * netdev,struct ethtool_channels * ch)5887 int hns3_set_channels(struct net_device *netdev,
5888 struct ethtool_channels *ch)
5889 {
5890 struct hnae3_handle *h = hns3_get_handle(netdev);
5891 struct hnae3_knic_private_info *kinfo = &h->kinfo;
5892 bool rxfh_configured = netif_is_rxfh_configured(netdev);
5893 u32 new_tqp_num = ch->combined_count;
5894 u16 org_tqp_num;
5895 int ret;
5896
5897 if (hns3_nic_resetting(netdev))
5898 return -EBUSY;
5899
5900 if (ch->rx_count || ch->tx_count)
5901 return -EINVAL;
5902
5903 if (kinfo->tc_info.mqprio_active) {
5904 dev_err(&netdev->dev,
5905 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n");
5906 return -EINVAL;
5907 }
5908
5909 if (new_tqp_num > hns3_get_max_available_channels(h) ||
5910 new_tqp_num < 1) {
5911 dev_err(&netdev->dev,
5912 "Change tqps fail, the tqp range is from 1 to %u",
5913 hns3_get_max_available_channels(h));
5914 return -EINVAL;
5915 }
5916
5917 if (kinfo->rss_size == new_tqp_num)
5918 return 0;
5919
5920 netif_dbg(h, drv, netdev,
5921 "set channels: tqp_num=%u, rxfh=%d\n",
5922 new_tqp_num, rxfh_configured);
5923
5924 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
5925 if (ret)
5926 return ret;
5927
5928 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
5929 if (ret)
5930 return ret;
5931
5932 org_tqp_num = h->kinfo.num_tqps;
5933 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured);
5934 if (ret) {
5935 int ret1;
5936
5937 netdev_warn(netdev,
5938 "Change channels fail, revert to old value\n");
5939 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured);
5940 if (ret1) {
5941 netdev_err(netdev,
5942 "revert to old channel fail\n");
5943 return ret1;
5944 }
5945
5946 return ret;
5947 }
5948
5949 return 0;
5950 }
5951
hns3_external_lb_prepare(struct net_device * ndev,bool if_running)5952 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
5953 {
5954 struct hns3_nic_priv *priv = netdev_priv(ndev);
5955
5956 if (!if_running)
5957 return;
5958
5959 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5960 return;
5961
5962 netif_carrier_off(ndev);
5963 netif_tx_disable(ndev);
5964
5965 hns3_disable_irqs_and_tqps(ndev);
5966
5967 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet
5968 * during reset process, because driver may not be able
5969 * to disable the ring through firmware when downing the netdev.
5970 */
5971 if (!hns3_nic_resetting(ndev))
5972 hns3_nic_reset_all_ring(priv->ae_handle);
5973
5974 hns3_reset_tx_queue(priv->ae_handle);
5975 }
5976
hns3_external_lb_restore(struct net_device * ndev,bool if_running)5977 void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
5978 {
5979 struct hns3_nic_priv *priv = netdev_priv(ndev);
5980 struct hnae3_handle *h = priv->ae_handle;
5981
5982 if (!if_running)
5983 return;
5984
5985 if (hns3_nic_resetting(ndev))
5986 return;
5987
5988 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
5989 return;
5990
5991 if (hns3_nic_reset_all_ring(priv->ae_handle))
5992 return;
5993
5994 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
5995
5996 hns3_enable_irqs_and_tqps(ndev);
5997
5998 netif_tx_wake_all_queues(ndev);
5999
6000 if (h->ae_algo->ops->get_status(h))
6001 netif_carrier_on(ndev);
6002 }
6003
6004 static const struct hns3_hw_error_info hns3_hw_err[] = {
6005 { .type = HNAE3_PPU_POISON_ERROR,
6006 .msg = "PPU poison" },
6007 { .type = HNAE3_CMDQ_ECC_ERROR,
6008 .msg = "IMP CMDQ error" },
6009 { .type = HNAE3_IMP_RD_POISON_ERROR,
6010 .msg = "IMP RD poison" },
6011 { .type = HNAE3_ROCEE_AXI_RESP_ERROR,
6012 .msg = "ROCEE AXI RESP error" },
6013 };
6014
hns3_process_hw_error(struct hnae3_handle * handle,enum hnae3_hw_error_type type)6015 static void hns3_process_hw_error(struct hnae3_handle *handle,
6016 enum hnae3_hw_error_type type)
6017 {
6018 u32 i;
6019
6020 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) {
6021 if (hns3_hw_err[i].type == type) {
6022 dev_err(&handle->pdev->dev, "Detected %s!\n",
6023 hns3_hw_err[i].msg);
6024 break;
6025 }
6026 }
6027 }
6028
6029 static const struct hnae3_client_ops client_ops = {
6030 .init_instance = hns3_client_init,
6031 .uninit_instance = hns3_client_uninit,
6032 .link_status_change = hns3_link_status_change,
6033 .reset_notify = hns3_reset_notify,
6034 .process_hw_error = hns3_process_hw_error,
6035 };
6036
6037 /* hns3_init_module - Driver registration routine
6038 * hns3_init_module is the first routine called when the driver is
6039 * loaded. All it does is register with the PCI subsystem.
6040 */
hns3_init_module(void)6041 static int __init hns3_init_module(void)
6042 {
6043 int ret;
6044
6045 pr_debug("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
6046 pr_debug("%s: %s\n", hns3_driver_name, hns3_copyright);
6047
6048 client.type = HNAE3_CLIENT_KNIC;
6049 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s",
6050 hns3_driver_name);
6051
6052 client.ops = &client_ops;
6053
6054 INIT_LIST_HEAD(&client.node);
6055
6056 hns3_dbg_register_debugfs(hns3_driver_name);
6057
6058 ret = hnae3_register_client(&client);
6059 if (ret)
6060 goto err_reg_client;
6061
6062 ret = pci_register_driver(&hns3_driver);
6063 if (ret)
6064 goto err_reg_driver;
6065
6066 return ret;
6067
6068 err_reg_driver:
6069 hnae3_unregister_client(&client);
6070 err_reg_client:
6071 hns3_dbg_unregister_debugfs();
6072 return ret;
6073 }
6074 module_init(hns3_init_module);
6075
6076 /* hns3_exit_module - Driver exit cleanup routine
6077 * hns3_exit_module is called just before the driver is removed
6078 * from memory.
6079 */
hns3_exit_module(void)6080 static void __exit hns3_exit_module(void)
6081 {
6082 hnae3_acquire_unload_lock();
6083 pci_unregister_driver(&hns3_driver);
6084 hnae3_unregister_client(&client);
6085 hns3_dbg_unregister_debugfs();
6086 hnae3_release_unload_lock();
6087 }
6088 module_exit(hns3_exit_module);
6089
6090 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
6091 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6092 MODULE_LICENSE("GPL");
6093 MODULE_ALIAS("pci:hns-nic");
6094