1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/dma-mapping.h> 5 #include <linux/etherdevice.h> 6 #include <linux/interrupt.h> 7 #ifdef CONFIG_RFS_ACCEL 8 #include <linux/cpu_rmap.h> 9 #endif 10 #include <linux/if_vlan.h> 11 #include <linux/irq.h> 12 #include <linux/ip.h> 13 #include <linux/ipv6.h> 14 #include <linux/iommu.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/skbuff.h> 18 #include <linux/sctp.h> 19 #include <net/gre.h> 20 #include <net/gro.h> 21 #include <net/ip6_checksum.h> 22 #include <net/page_pool/helpers.h> 23 #include <net/pkt_cls.h> 24 #include <net/pkt_sched.h> 25 #include <net/tcp.h> 26 #include <net/vxlan.h> 27 #include <net/geneve.h> 28 29 #include "hnae3.h" 30 #include "hns3_enet.h" 31 /* All hns3 tracepoints are defined by the include below, which 32 * must be included exactly once across the whole kernel with 33 * CREATE_TRACE_POINTS defined 34 */ 35 #define CREATE_TRACE_POINTS 36 #include "hns3_trace.h" 37 38 #define hns3_set_field(origin, shift, val) ((origin) |= (val) << (shift)) 39 #define hns3_tx_bd_count(S) DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE) 40 41 #define hns3_rl_err(fmt, ...) \ 42 do { \ 43 if (net_ratelimit()) \ 44 netdev_err(fmt, ##__VA_ARGS__); \ 45 } while (0) 46 47 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force); 48 49 static const char hns3_driver_name[] = "hns3"; 50 static const char hns3_driver_string[] = 51 "Hisilicon Ethernet Network Driver for Hip08 Family"; 52 static const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation."; 53 static struct hnae3_client client; 54 55 static int debug = -1; 56 module_param(debug, int, 0); 57 MODULE_PARM_DESC(debug, " Network interface message level setting"); 58 59 static unsigned int tx_sgl = 1; 60 module_param(tx_sgl, uint, 0600); 61 MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping"); 62 63 static bool page_pool_enabled = true; 64 module_param(page_pool_enabled, bool, 0400); 65 66 #define HNS3_SGL_SIZE(nfrag) (sizeof(struct scatterlist) * (nfrag) + \ 67 sizeof(struct sg_table)) 68 #define HNS3_MAX_SGL_SIZE ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \ 69 dma_get_cache_alignment()) 70 71 #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 72 NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 73 74 #define HNS3_INNER_VLAN_TAG 1 75 #define HNS3_OUTER_VLAN_TAG 2 76 77 #define HNS3_MIN_TX_LEN 33U 78 #define HNS3_MIN_TUN_PKT_LEN 65U 79 80 /* hns3_pci_tbl - PCI Device ID Table 81 * 82 * Last entry must be all 0s 83 * 84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 85 * Class, Class Mask, private data (not used) } 86 */ 87 static const struct pci_device_id hns3_pci_tbl[] = { 88 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, 89 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, 90 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 91 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 92 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 93 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 94 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 95 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 96 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 97 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 98 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 99 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 100 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 101 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 102 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0}, 103 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 104 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS}, 105 /* required last entry */ 106 {0,} 107 }; 108 MODULE_DEVICE_TABLE(pci, hns3_pci_tbl); 109 110 #define HNS3_RX_PTYPE_ENTRY(ptype, l, s, t, h) \ 111 { ptype, \ 112 l, \ 113 CHECKSUM_##s, \ 114 HNS3_L3_TYPE_##t, \ 115 1, \ 116 h} 117 118 #define HNS3_RX_PTYPE_UNUSED_ENTRY(ptype) \ 119 { ptype, 0, CHECKSUM_NONE, HNS3_L3_TYPE_PARSE_FAIL, 0, \ 120 PKT_HASH_TYPE_NONE } 121 122 static const struct hns3_rx_ptype hns3_rx_ptype_tbl[] = { 123 HNS3_RX_PTYPE_UNUSED_ENTRY(0), 124 HNS3_RX_PTYPE_ENTRY(1, 0, COMPLETE, ARP, PKT_HASH_TYPE_NONE), 125 HNS3_RX_PTYPE_ENTRY(2, 0, COMPLETE, RARP, PKT_HASH_TYPE_NONE), 126 HNS3_RX_PTYPE_ENTRY(3, 0, COMPLETE, LLDP, PKT_HASH_TYPE_NONE), 127 HNS3_RX_PTYPE_ENTRY(4, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 128 HNS3_RX_PTYPE_ENTRY(5, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 129 HNS3_RX_PTYPE_ENTRY(6, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 130 HNS3_RX_PTYPE_ENTRY(7, 0, COMPLETE, CNM, PKT_HASH_TYPE_NONE), 131 HNS3_RX_PTYPE_ENTRY(8, 0, NONE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 132 HNS3_RX_PTYPE_UNUSED_ENTRY(9), 133 HNS3_RX_PTYPE_UNUSED_ENTRY(10), 134 HNS3_RX_PTYPE_UNUSED_ENTRY(11), 135 HNS3_RX_PTYPE_UNUSED_ENTRY(12), 136 HNS3_RX_PTYPE_UNUSED_ENTRY(13), 137 HNS3_RX_PTYPE_UNUSED_ENTRY(14), 138 HNS3_RX_PTYPE_UNUSED_ENTRY(15), 139 HNS3_RX_PTYPE_ENTRY(16, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 140 HNS3_RX_PTYPE_ENTRY(17, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE), 141 HNS3_RX_PTYPE_ENTRY(18, 0, COMPLETE, IPV4, PKT_HASH_TYPE_NONE), 142 HNS3_RX_PTYPE_ENTRY(19, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 143 HNS3_RX_PTYPE_ENTRY(20, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 144 HNS3_RX_PTYPE_ENTRY(21, 0, NONE, IPV4, PKT_HASH_TYPE_NONE), 145 HNS3_RX_PTYPE_ENTRY(22, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 146 HNS3_RX_PTYPE_ENTRY(23, 0, NONE, IPV4, PKT_HASH_TYPE_L3), 147 HNS3_RX_PTYPE_ENTRY(24, 0, NONE, IPV4, PKT_HASH_TYPE_L3), 148 HNS3_RX_PTYPE_ENTRY(25, 0, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 149 HNS3_RX_PTYPE_UNUSED_ENTRY(26), 150 HNS3_RX_PTYPE_UNUSED_ENTRY(27), 151 HNS3_RX_PTYPE_UNUSED_ENTRY(28), 152 HNS3_RX_PTYPE_ENTRY(29, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 153 HNS3_RX_PTYPE_ENTRY(30, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 154 HNS3_RX_PTYPE_ENTRY(31, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 155 HNS3_RX_PTYPE_ENTRY(32, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 156 HNS3_RX_PTYPE_ENTRY(33, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 157 HNS3_RX_PTYPE_ENTRY(34, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 158 HNS3_RX_PTYPE_ENTRY(35, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 159 HNS3_RX_PTYPE_ENTRY(36, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 160 HNS3_RX_PTYPE_ENTRY(37, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 161 HNS3_RX_PTYPE_UNUSED_ENTRY(38), 162 HNS3_RX_PTYPE_ENTRY(39, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 163 HNS3_RX_PTYPE_ENTRY(40, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 164 HNS3_RX_PTYPE_ENTRY(41, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 165 HNS3_RX_PTYPE_ENTRY(42, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 166 HNS3_RX_PTYPE_ENTRY(43, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 167 HNS3_RX_PTYPE_ENTRY(44, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 168 HNS3_RX_PTYPE_ENTRY(45, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 169 HNS3_RX_PTYPE_UNUSED_ENTRY(46), 170 HNS3_RX_PTYPE_UNUSED_ENTRY(47), 171 HNS3_RX_PTYPE_UNUSED_ENTRY(48), 172 HNS3_RX_PTYPE_UNUSED_ENTRY(49), 173 HNS3_RX_PTYPE_UNUSED_ENTRY(50), 174 HNS3_RX_PTYPE_UNUSED_ENTRY(51), 175 HNS3_RX_PTYPE_UNUSED_ENTRY(52), 176 HNS3_RX_PTYPE_UNUSED_ENTRY(53), 177 HNS3_RX_PTYPE_UNUSED_ENTRY(54), 178 HNS3_RX_PTYPE_UNUSED_ENTRY(55), 179 HNS3_RX_PTYPE_UNUSED_ENTRY(56), 180 HNS3_RX_PTYPE_UNUSED_ENTRY(57), 181 HNS3_RX_PTYPE_UNUSED_ENTRY(58), 182 HNS3_RX_PTYPE_UNUSED_ENTRY(59), 183 HNS3_RX_PTYPE_UNUSED_ENTRY(60), 184 HNS3_RX_PTYPE_UNUSED_ENTRY(61), 185 HNS3_RX_PTYPE_UNUSED_ENTRY(62), 186 HNS3_RX_PTYPE_UNUSED_ENTRY(63), 187 HNS3_RX_PTYPE_UNUSED_ENTRY(64), 188 HNS3_RX_PTYPE_UNUSED_ENTRY(65), 189 HNS3_RX_PTYPE_UNUSED_ENTRY(66), 190 HNS3_RX_PTYPE_UNUSED_ENTRY(67), 191 HNS3_RX_PTYPE_UNUSED_ENTRY(68), 192 HNS3_RX_PTYPE_UNUSED_ENTRY(69), 193 HNS3_RX_PTYPE_UNUSED_ENTRY(70), 194 HNS3_RX_PTYPE_UNUSED_ENTRY(71), 195 HNS3_RX_PTYPE_UNUSED_ENTRY(72), 196 HNS3_RX_PTYPE_UNUSED_ENTRY(73), 197 HNS3_RX_PTYPE_UNUSED_ENTRY(74), 198 HNS3_RX_PTYPE_UNUSED_ENTRY(75), 199 HNS3_RX_PTYPE_UNUSED_ENTRY(76), 200 HNS3_RX_PTYPE_UNUSED_ENTRY(77), 201 HNS3_RX_PTYPE_UNUSED_ENTRY(78), 202 HNS3_RX_PTYPE_UNUSED_ENTRY(79), 203 HNS3_RX_PTYPE_UNUSED_ENTRY(80), 204 HNS3_RX_PTYPE_UNUSED_ENTRY(81), 205 HNS3_RX_PTYPE_UNUSED_ENTRY(82), 206 HNS3_RX_PTYPE_UNUSED_ENTRY(83), 207 HNS3_RX_PTYPE_UNUSED_ENTRY(84), 208 HNS3_RX_PTYPE_UNUSED_ENTRY(85), 209 HNS3_RX_PTYPE_UNUSED_ENTRY(86), 210 HNS3_RX_PTYPE_UNUSED_ENTRY(87), 211 HNS3_RX_PTYPE_UNUSED_ENTRY(88), 212 HNS3_RX_PTYPE_UNUSED_ENTRY(89), 213 HNS3_RX_PTYPE_UNUSED_ENTRY(90), 214 HNS3_RX_PTYPE_UNUSED_ENTRY(91), 215 HNS3_RX_PTYPE_UNUSED_ENTRY(92), 216 HNS3_RX_PTYPE_UNUSED_ENTRY(93), 217 HNS3_RX_PTYPE_UNUSED_ENTRY(94), 218 HNS3_RX_PTYPE_UNUSED_ENTRY(95), 219 HNS3_RX_PTYPE_UNUSED_ENTRY(96), 220 HNS3_RX_PTYPE_UNUSED_ENTRY(97), 221 HNS3_RX_PTYPE_UNUSED_ENTRY(98), 222 HNS3_RX_PTYPE_UNUSED_ENTRY(99), 223 HNS3_RX_PTYPE_UNUSED_ENTRY(100), 224 HNS3_RX_PTYPE_UNUSED_ENTRY(101), 225 HNS3_RX_PTYPE_UNUSED_ENTRY(102), 226 HNS3_RX_PTYPE_UNUSED_ENTRY(103), 227 HNS3_RX_PTYPE_UNUSED_ENTRY(104), 228 HNS3_RX_PTYPE_UNUSED_ENTRY(105), 229 HNS3_RX_PTYPE_UNUSED_ENTRY(106), 230 HNS3_RX_PTYPE_UNUSED_ENTRY(107), 231 HNS3_RX_PTYPE_UNUSED_ENTRY(108), 232 HNS3_RX_PTYPE_UNUSED_ENTRY(109), 233 HNS3_RX_PTYPE_UNUSED_ENTRY(110), 234 HNS3_RX_PTYPE_ENTRY(111, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 235 HNS3_RX_PTYPE_ENTRY(112, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 236 HNS3_RX_PTYPE_ENTRY(113, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 237 HNS3_RX_PTYPE_ENTRY(114, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 238 HNS3_RX_PTYPE_ENTRY(115, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 239 HNS3_RX_PTYPE_ENTRY(116, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 240 HNS3_RX_PTYPE_ENTRY(117, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 241 HNS3_RX_PTYPE_ENTRY(118, 0, NONE, IPV6, PKT_HASH_TYPE_L3), 242 HNS3_RX_PTYPE_ENTRY(119, 0, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 243 HNS3_RX_PTYPE_UNUSED_ENTRY(120), 244 HNS3_RX_PTYPE_UNUSED_ENTRY(121), 245 HNS3_RX_PTYPE_UNUSED_ENTRY(122), 246 HNS3_RX_PTYPE_ENTRY(123, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 247 HNS3_RX_PTYPE_ENTRY(124, 0, COMPLETE, PARSE_FAIL, PKT_HASH_TYPE_NONE), 248 HNS3_RX_PTYPE_ENTRY(125, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 249 HNS3_RX_PTYPE_ENTRY(126, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 250 HNS3_RX_PTYPE_ENTRY(127, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 251 HNS3_RX_PTYPE_ENTRY(128, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 252 HNS3_RX_PTYPE_ENTRY(129, 1, UNNECESSARY, IPV4, PKT_HASH_TYPE_L4), 253 HNS3_RX_PTYPE_ENTRY(130, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 254 HNS3_RX_PTYPE_ENTRY(131, 0, COMPLETE, IPV4, PKT_HASH_TYPE_L3), 255 HNS3_RX_PTYPE_UNUSED_ENTRY(132), 256 HNS3_RX_PTYPE_ENTRY(133, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 257 HNS3_RX_PTYPE_ENTRY(134, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 258 HNS3_RX_PTYPE_ENTRY(135, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 259 HNS3_RX_PTYPE_ENTRY(136, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 260 HNS3_RX_PTYPE_ENTRY(137, 1, UNNECESSARY, IPV6, PKT_HASH_TYPE_L4), 261 HNS3_RX_PTYPE_ENTRY(138, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 262 HNS3_RX_PTYPE_ENTRY(139, 0, COMPLETE, IPV6, PKT_HASH_TYPE_L3), 263 HNS3_RX_PTYPE_UNUSED_ENTRY(140), 264 HNS3_RX_PTYPE_UNUSED_ENTRY(141), 265 HNS3_RX_PTYPE_UNUSED_ENTRY(142), 266 HNS3_RX_PTYPE_UNUSED_ENTRY(143), 267 HNS3_RX_PTYPE_UNUSED_ENTRY(144), 268 HNS3_RX_PTYPE_UNUSED_ENTRY(145), 269 HNS3_RX_PTYPE_UNUSED_ENTRY(146), 270 HNS3_RX_PTYPE_UNUSED_ENTRY(147), 271 HNS3_RX_PTYPE_UNUSED_ENTRY(148), 272 HNS3_RX_PTYPE_UNUSED_ENTRY(149), 273 HNS3_RX_PTYPE_UNUSED_ENTRY(150), 274 HNS3_RX_PTYPE_UNUSED_ENTRY(151), 275 HNS3_RX_PTYPE_UNUSED_ENTRY(152), 276 HNS3_RX_PTYPE_UNUSED_ENTRY(153), 277 HNS3_RX_PTYPE_UNUSED_ENTRY(154), 278 HNS3_RX_PTYPE_UNUSED_ENTRY(155), 279 HNS3_RX_PTYPE_UNUSED_ENTRY(156), 280 HNS3_RX_PTYPE_UNUSED_ENTRY(157), 281 HNS3_RX_PTYPE_UNUSED_ENTRY(158), 282 HNS3_RX_PTYPE_UNUSED_ENTRY(159), 283 HNS3_RX_PTYPE_UNUSED_ENTRY(160), 284 HNS3_RX_PTYPE_UNUSED_ENTRY(161), 285 HNS3_RX_PTYPE_UNUSED_ENTRY(162), 286 HNS3_RX_PTYPE_UNUSED_ENTRY(163), 287 HNS3_RX_PTYPE_UNUSED_ENTRY(164), 288 HNS3_RX_PTYPE_UNUSED_ENTRY(165), 289 HNS3_RX_PTYPE_UNUSED_ENTRY(166), 290 HNS3_RX_PTYPE_UNUSED_ENTRY(167), 291 HNS3_RX_PTYPE_UNUSED_ENTRY(168), 292 HNS3_RX_PTYPE_UNUSED_ENTRY(169), 293 HNS3_RX_PTYPE_UNUSED_ENTRY(170), 294 HNS3_RX_PTYPE_UNUSED_ENTRY(171), 295 HNS3_RX_PTYPE_UNUSED_ENTRY(172), 296 HNS3_RX_PTYPE_UNUSED_ENTRY(173), 297 HNS3_RX_PTYPE_UNUSED_ENTRY(174), 298 HNS3_RX_PTYPE_UNUSED_ENTRY(175), 299 HNS3_RX_PTYPE_UNUSED_ENTRY(176), 300 HNS3_RX_PTYPE_UNUSED_ENTRY(177), 301 HNS3_RX_PTYPE_UNUSED_ENTRY(178), 302 HNS3_RX_PTYPE_UNUSED_ENTRY(179), 303 HNS3_RX_PTYPE_UNUSED_ENTRY(180), 304 HNS3_RX_PTYPE_UNUSED_ENTRY(181), 305 HNS3_RX_PTYPE_UNUSED_ENTRY(182), 306 HNS3_RX_PTYPE_UNUSED_ENTRY(183), 307 HNS3_RX_PTYPE_UNUSED_ENTRY(184), 308 HNS3_RX_PTYPE_UNUSED_ENTRY(185), 309 HNS3_RX_PTYPE_UNUSED_ENTRY(186), 310 HNS3_RX_PTYPE_UNUSED_ENTRY(187), 311 HNS3_RX_PTYPE_UNUSED_ENTRY(188), 312 HNS3_RX_PTYPE_UNUSED_ENTRY(189), 313 HNS3_RX_PTYPE_UNUSED_ENTRY(190), 314 HNS3_RX_PTYPE_UNUSED_ENTRY(191), 315 HNS3_RX_PTYPE_UNUSED_ENTRY(192), 316 HNS3_RX_PTYPE_UNUSED_ENTRY(193), 317 HNS3_RX_PTYPE_UNUSED_ENTRY(194), 318 HNS3_RX_PTYPE_UNUSED_ENTRY(195), 319 HNS3_RX_PTYPE_UNUSED_ENTRY(196), 320 HNS3_RX_PTYPE_UNUSED_ENTRY(197), 321 HNS3_RX_PTYPE_UNUSED_ENTRY(198), 322 HNS3_RX_PTYPE_UNUSED_ENTRY(199), 323 HNS3_RX_PTYPE_UNUSED_ENTRY(200), 324 HNS3_RX_PTYPE_UNUSED_ENTRY(201), 325 HNS3_RX_PTYPE_UNUSED_ENTRY(202), 326 HNS3_RX_PTYPE_UNUSED_ENTRY(203), 327 HNS3_RX_PTYPE_UNUSED_ENTRY(204), 328 HNS3_RX_PTYPE_UNUSED_ENTRY(205), 329 HNS3_RX_PTYPE_UNUSED_ENTRY(206), 330 HNS3_RX_PTYPE_UNUSED_ENTRY(207), 331 HNS3_RX_PTYPE_UNUSED_ENTRY(208), 332 HNS3_RX_PTYPE_UNUSED_ENTRY(209), 333 HNS3_RX_PTYPE_UNUSED_ENTRY(210), 334 HNS3_RX_PTYPE_UNUSED_ENTRY(211), 335 HNS3_RX_PTYPE_UNUSED_ENTRY(212), 336 HNS3_RX_PTYPE_UNUSED_ENTRY(213), 337 HNS3_RX_PTYPE_UNUSED_ENTRY(214), 338 HNS3_RX_PTYPE_UNUSED_ENTRY(215), 339 HNS3_RX_PTYPE_UNUSED_ENTRY(216), 340 HNS3_RX_PTYPE_UNUSED_ENTRY(217), 341 HNS3_RX_PTYPE_UNUSED_ENTRY(218), 342 HNS3_RX_PTYPE_UNUSED_ENTRY(219), 343 HNS3_RX_PTYPE_UNUSED_ENTRY(220), 344 HNS3_RX_PTYPE_UNUSED_ENTRY(221), 345 HNS3_RX_PTYPE_UNUSED_ENTRY(222), 346 HNS3_RX_PTYPE_UNUSED_ENTRY(223), 347 HNS3_RX_PTYPE_UNUSED_ENTRY(224), 348 HNS3_RX_PTYPE_UNUSED_ENTRY(225), 349 HNS3_RX_PTYPE_UNUSED_ENTRY(226), 350 HNS3_RX_PTYPE_UNUSED_ENTRY(227), 351 HNS3_RX_PTYPE_UNUSED_ENTRY(228), 352 HNS3_RX_PTYPE_UNUSED_ENTRY(229), 353 HNS3_RX_PTYPE_UNUSED_ENTRY(230), 354 HNS3_RX_PTYPE_UNUSED_ENTRY(231), 355 HNS3_RX_PTYPE_UNUSED_ENTRY(232), 356 HNS3_RX_PTYPE_UNUSED_ENTRY(233), 357 HNS3_RX_PTYPE_UNUSED_ENTRY(234), 358 HNS3_RX_PTYPE_UNUSED_ENTRY(235), 359 HNS3_RX_PTYPE_UNUSED_ENTRY(236), 360 HNS3_RX_PTYPE_UNUSED_ENTRY(237), 361 HNS3_RX_PTYPE_UNUSED_ENTRY(238), 362 HNS3_RX_PTYPE_UNUSED_ENTRY(239), 363 HNS3_RX_PTYPE_UNUSED_ENTRY(240), 364 HNS3_RX_PTYPE_UNUSED_ENTRY(241), 365 HNS3_RX_PTYPE_UNUSED_ENTRY(242), 366 HNS3_RX_PTYPE_UNUSED_ENTRY(243), 367 HNS3_RX_PTYPE_UNUSED_ENTRY(244), 368 HNS3_RX_PTYPE_UNUSED_ENTRY(245), 369 HNS3_RX_PTYPE_UNUSED_ENTRY(246), 370 HNS3_RX_PTYPE_UNUSED_ENTRY(247), 371 HNS3_RX_PTYPE_UNUSED_ENTRY(248), 372 HNS3_RX_PTYPE_UNUSED_ENTRY(249), 373 HNS3_RX_PTYPE_UNUSED_ENTRY(250), 374 HNS3_RX_PTYPE_UNUSED_ENTRY(251), 375 HNS3_RX_PTYPE_UNUSED_ENTRY(252), 376 HNS3_RX_PTYPE_UNUSED_ENTRY(253), 377 HNS3_RX_PTYPE_UNUSED_ENTRY(254), 378 HNS3_RX_PTYPE_UNUSED_ENTRY(255), 379 }; 380 381 #define HNS3_INVALID_PTYPE \ 382 ARRAY_SIZE(hns3_rx_ptype_tbl) 383 384 static irqreturn_t hns3_irq_handle(int irq, void *vector) 385 { 386 struct hns3_enet_tqp_vector *tqp_vector = vector; 387 388 napi_schedule_irqoff(&tqp_vector->napi); 389 tqp_vector->event_cnt++; 390 391 return IRQ_HANDLED; 392 } 393 394 static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv) 395 { 396 struct hns3_enet_tqp_vector *tqp_vectors; 397 unsigned int i; 398 399 for (i = 0; i < priv->vector_num; i++) { 400 tqp_vectors = &priv->tqp_vector[i]; 401 402 if (tqp_vectors->irq_init_flag != HNS3_VECTOR_INITED) 403 continue; 404 405 /* clear the affinity mask */ 406 irq_set_affinity_hint(tqp_vectors->vector_irq, NULL); 407 408 /* release the irq resource */ 409 free_irq(tqp_vectors->vector_irq, tqp_vectors); 410 tqp_vectors->irq_init_flag = HNS3_VECTOR_NOT_INITED; 411 } 412 } 413 414 static int hns3_nic_init_irq(struct hns3_nic_priv *priv) 415 { 416 struct hns3_enet_tqp_vector *tqp_vectors; 417 int txrx_int_idx = 0; 418 int rx_int_idx = 0; 419 int tx_int_idx = 0; 420 unsigned int i; 421 int ret; 422 423 for (i = 0; i < priv->vector_num; i++) { 424 tqp_vectors = &priv->tqp_vector[i]; 425 426 if (tqp_vectors->irq_init_flag == HNS3_VECTOR_INITED) 427 continue; 428 429 if (tqp_vectors->tx_group.ring && tqp_vectors->rx_group.ring) { 430 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 431 "%s-%s-%s-%d", hns3_driver_name, 432 pci_name(priv->ae_handle->pdev), 433 "TxRx", txrx_int_idx++); 434 txrx_int_idx++; 435 } else if (tqp_vectors->rx_group.ring) { 436 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 437 "%s-%s-%s-%d", hns3_driver_name, 438 pci_name(priv->ae_handle->pdev), 439 "Rx", rx_int_idx++); 440 } else if (tqp_vectors->tx_group.ring) { 441 snprintf(tqp_vectors->name, HNAE3_INT_NAME_LEN, 442 "%s-%s-%s-%d", hns3_driver_name, 443 pci_name(priv->ae_handle->pdev), 444 "Tx", tx_int_idx++); 445 } else { 446 /* Skip this unused q_vector */ 447 continue; 448 } 449 450 tqp_vectors->name[HNAE3_INT_NAME_LEN - 1] = '\0'; 451 452 irq_set_status_flags(tqp_vectors->vector_irq, IRQ_NOAUTOEN); 453 ret = request_irq(tqp_vectors->vector_irq, hns3_irq_handle, 0, 454 tqp_vectors->name, tqp_vectors); 455 if (ret) { 456 netdev_err(priv->netdev, "request irq(%d) fail\n", 457 tqp_vectors->vector_irq); 458 hns3_nic_uninit_irq(priv); 459 return ret; 460 } 461 462 irq_set_affinity_hint(tqp_vectors->vector_irq, 463 &tqp_vectors->affinity_mask); 464 465 tqp_vectors->irq_init_flag = HNS3_VECTOR_INITED; 466 } 467 468 return 0; 469 } 470 471 static void hns3_mask_vector_irq(struct hns3_enet_tqp_vector *tqp_vector, 472 u32 mask_en) 473 { 474 writel(mask_en, tqp_vector->mask_addr); 475 } 476 477 static void hns3_irq_enable(struct hns3_enet_tqp_vector *tqp_vector) 478 { 479 napi_enable(&tqp_vector->napi); 480 enable_irq(tqp_vector->vector_irq); 481 } 482 483 static void hns3_irq_disable(struct hns3_enet_tqp_vector *tqp_vector) 484 { 485 disable_irq(tqp_vector->vector_irq); 486 napi_disable(&tqp_vector->napi); 487 cancel_work_sync(&tqp_vector->rx_group.dim.work); 488 cancel_work_sync(&tqp_vector->tx_group.dim.work); 489 } 490 491 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, 492 u32 rl_value) 493 { 494 u32 rl_reg = hns3_rl_usec_to_reg(rl_value); 495 496 /* this defines the configuration for RL (Interrupt Rate Limiter). 497 * Rl defines rate of interrupts i.e. number of interrupts-per-second 498 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing 499 */ 500 if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable && 501 !tqp_vector->rx_group.coal.adapt_enable) 502 /* According to the hardware, the range of rl_reg is 503 * 0-59 and the unit is 4. 504 */ 505 rl_reg |= HNS3_INT_RL_ENABLE_MASK; 506 507 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); 508 } 509 510 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector, 511 u32 gl_value) 512 { 513 u32 new_val; 514 515 if (tqp_vector->rx_group.coal.unit_1us) 516 new_val = gl_value | HNS3_INT_GL_1US; 517 else 518 new_val = hns3_gl_usec_to_reg(gl_value); 519 520 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); 521 } 522 523 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector, 524 u32 gl_value) 525 { 526 u32 new_val; 527 528 if (tqp_vector->tx_group.coal.unit_1us) 529 new_val = gl_value | HNS3_INT_GL_1US; 530 else 531 new_val = hns3_gl_usec_to_reg(gl_value); 532 533 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); 534 } 535 536 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector, 537 u32 ql_value) 538 { 539 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); 540 } 541 542 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector, 543 u32 ql_value) 544 { 545 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); 546 } 547 548 static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, 549 struct hns3_nic_priv *priv) 550 { 551 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 552 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 553 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); 554 struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal; 555 struct hns3_enet_coalesce *prx_coal = &priv->rx_coal; 556 557 tx_coal->adapt_enable = ptx_coal->adapt_enable; 558 rx_coal->adapt_enable = prx_coal->adapt_enable; 559 560 tx_coal->int_gl = ptx_coal->int_gl; 561 rx_coal->int_gl = prx_coal->int_gl; 562 563 rx_coal->flow_level = prx_coal->flow_level; 564 tx_coal->flow_level = ptx_coal->flow_level; 565 566 /* device version above V3(include V3), GL can configure 1us 567 * unit, so uses 1us unit. 568 */ 569 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) { 570 tx_coal->unit_1us = 1; 571 rx_coal->unit_1us = 1; 572 } 573 574 if (ae_dev->dev_specs.int_ql_max) { 575 tx_coal->ql_enable = 1; 576 rx_coal->ql_enable = 1; 577 tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 578 rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max; 579 tx_coal->int_ql = ptx_coal->int_ql; 580 rx_coal->int_ql = prx_coal->int_ql; 581 } 582 } 583 584 static void 585 hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector, 586 struct hns3_nic_priv *priv) 587 { 588 struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal; 589 struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal; 590 struct hnae3_handle *h = priv->ae_handle; 591 592 hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl); 593 hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl); 594 hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting); 595 596 if (tx_coal->ql_enable) 597 hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql); 598 599 if (rx_coal->ql_enable) 600 hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql); 601 } 602 603 static int hns3_nic_set_real_num_queue(struct net_device *netdev) 604 { 605 struct hnae3_handle *h = hns3_get_handle(netdev); 606 struct hnae3_knic_private_info *kinfo = &h->kinfo; 607 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 608 unsigned int queue_size = kinfo->num_tqps; 609 int i, ret; 610 611 if (tc_info->num_tc <= 1 && !tc_info->mqprio_active) { 612 netdev_reset_tc(netdev); 613 } else { 614 ret = netdev_set_num_tc(netdev, tc_info->num_tc); 615 if (ret) { 616 netdev_err(netdev, 617 "netdev_set_num_tc fail, ret=%d!\n", ret); 618 return ret; 619 } 620 621 for (i = 0; i < tc_info->num_tc; i++) 622 netdev_set_tc_queue(netdev, i, tc_info->tqp_count[i], 623 tc_info->tqp_offset[i]); 624 } 625 626 ret = netif_set_real_num_tx_queues(netdev, queue_size); 627 if (ret) { 628 netdev_err(netdev, 629 "netif_set_real_num_tx_queues fail, ret=%d!\n", ret); 630 return ret; 631 } 632 633 ret = netif_set_real_num_rx_queues(netdev, queue_size); 634 if (ret) { 635 netdev_err(netdev, 636 "netif_set_real_num_rx_queues fail, ret=%d!\n", ret); 637 return ret; 638 } 639 640 return 0; 641 } 642 643 u16 hns3_get_max_available_channels(struct hnae3_handle *h) 644 { 645 u16 alloc_tqps, max_rss_size, rss_size; 646 647 h->ae_algo->ops->get_tqps_and_rss_info(h, &alloc_tqps, &max_rss_size); 648 rss_size = alloc_tqps / h->kinfo.tc_info.num_tc; 649 650 return min_t(u16, rss_size, max_rss_size); 651 } 652 653 static void hns3_tqp_enable(struct hnae3_queue *tqp) 654 { 655 u32 rcb_reg; 656 657 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 658 rcb_reg |= BIT(HNS3_RING_EN_B); 659 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 660 } 661 662 static void hns3_tqp_disable(struct hnae3_queue *tqp) 663 { 664 u32 rcb_reg; 665 666 rcb_reg = hns3_read_dev(tqp, HNS3_RING_EN_REG); 667 rcb_reg &= ~BIT(HNS3_RING_EN_B); 668 hns3_write_dev(tqp, HNS3_RING_EN_REG, rcb_reg); 669 } 670 671 static void hns3_free_rx_cpu_rmap(struct net_device *netdev) 672 { 673 #ifdef CONFIG_RFS_ACCEL 674 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 675 netdev->rx_cpu_rmap = NULL; 676 #endif 677 } 678 679 static int hns3_set_rx_cpu_rmap(struct net_device *netdev) 680 { 681 #ifdef CONFIG_RFS_ACCEL 682 struct hns3_nic_priv *priv = netdev_priv(netdev); 683 struct hns3_enet_tqp_vector *tqp_vector; 684 int i, ret; 685 686 if (!netdev->rx_cpu_rmap) { 687 netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->vector_num); 688 if (!netdev->rx_cpu_rmap) 689 return -ENOMEM; 690 } 691 692 for (i = 0; i < priv->vector_num; i++) { 693 tqp_vector = &priv->tqp_vector[i]; 694 ret = irq_cpu_rmap_add(netdev->rx_cpu_rmap, 695 tqp_vector->vector_irq); 696 if (ret) { 697 hns3_free_rx_cpu_rmap(netdev); 698 return ret; 699 } 700 } 701 #endif 702 return 0; 703 } 704 705 static void hns3_enable_irqs_and_tqps(struct net_device *netdev) 706 { 707 struct hns3_nic_priv *priv = netdev_priv(netdev); 708 struct hnae3_handle *h = priv->ae_handle; 709 u16 i; 710 711 for (i = 0; i < priv->vector_num; i++) 712 hns3_irq_enable(&priv->tqp_vector[i]); 713 714 for (i = 0; i < priv->vector_num; i++) 715 hns3_mask_vector_irq(&priv->tqp_vector[i], 1); 716 717 for (i = 0; i < h->kinfo.num_tqps; i++) 718 hns3_tqp_enable(h->kinfo.tqp[i]); 719 } 720 721 static void hns3_disable_irqs_and_tqps(struct net_device *netdev) 722 { 723 struct hns3_nic_priv *priv = netdev_priv(netdev); 724 struct hnae3_handle *h = priv->ae_handle; 725 u16 i; 726 727 for (i = 0; i < h->kinfo.num_tqps; i++) 728 hns3_tqp_disable(h->kinfo.tqp[i]); 729 730 for (i = 0; i < priv->vector_num; i++) 731 hns3_mask_vector_irq(&priv->tqp_vector[i], 0); 732 733 for (i = 0; i < priv->vector_num; i++) 734 hns3_irq_disable(&priv->tqp_vector[i]); 735 } 736 737 static int hns3_nic_net_up(struct net_device *netdev) 738 { 739 struct hns3_nic_priv *priv = netdev_priv(netdev); 740 struct hnae3_handle *h = priv->ae_handle; 741 int ret; 742 743 ret = hns3_nic_reset_all_ring(h); 744 if (ret) 745 return ret; 746 747 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 748 749 hns3_enable_irqs_and_tqps(netdev); 750 751 /* start the ae_dev */ 752 ret = h->ae_algo->ops->start ? h->ae_algo->ops->start(h) : 0; 753 if (ret) { 754 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 755 hns3_disable_irqs_and_tqps(netdev); 756 } 757 758 return ret; 759 } 760 761 static void hns3_config_xps(struct hns3_nic_priv *priv) 762 { 763 int i; 764 765 for (i = 0; i < priv->vector_num; i++) { 766 struct hns3_enet_tqp_vector *tqp_vector = &priv->tqp_vector[i]; 767 struct hns3_enet_ring *ring = tqp_vector->tx_group.ring; 768 769 while (ring) { 770 int ret; 771 772 ret = netif_set_xps_queue(priv->netdev, 773 &tqp_vector->affinity_mask, 774 ring->tqp->tqp_index); 775 if (ret) 776 netdev_warn(priv->netdev, 777 "set xps queue failed: %d", ret); 778 779 ring = ring->next; 780 } 781 } 782 } 783 784 static int hns3_nic_net_open(struct net_device *netdev) 785 { 786 struct hns3_nic_priv *priv = netdev_priv(netdev); 787 struct hnae3_handle *h = hns3_get_handle(netdev); 788 struct hnae3_knic_private_info *kinfo; 789 int i, ret; 790 791 if (hns3_nic_resetting(netdev)) 792 return -EBUSY; 793 794 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 795 netdev_warn(netdev, "net open repeatedly!\n"); 796 return 0; 797 } 798 799 netif_carrier_off(netdev); 800 801 ret = hns3_nic_set_real_num_queue(netdev); 802 if (ret) 803 return ret; 804 805 ret = hns3_nic_net_up(netdev); 806 if (ret) { 807 netdev_err(netdev, "net up fail, ret=%d!\n", ret); 808 return ret; 809 } 810 811 kinfo = &h->kinfo; 812 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) 813 netdev_set_prio_tc_map(netdev, i, kinfo->tc_info.prio_tc[i]); 814 815 if (h->ae_algo->ops->set_timer_task) 816 h->ae_algo->ops->set_timer_task(priv->ae_handle, true); 817 818 hns3_config_xps(priv); 819 820 netif_dbg(h, drv, netdev, "net open\n"); 821 822 return 0; 823 } 824 825 static void hns3_reset_tx_queue(struct hnae3_handle *h) 826 { 827 struct net_device *ndev = h->kinfo.netdev; 828 struct hns3_nic_priv *priv = netdev_priv(ndev); 829 struct netdev_queue *dev_queue; 830 u32 i; 831 832 for (i = 0; i < h->kinfo.num_tqps; i++) { 833 dev_queue = netdev_get_tx_queue(ndev, 834 priv->ring[i].queue_index); 835 netdev_tx_reset_queue(dev_queue); 836 } 837 } 838 839 static void hns3_nic_net_down(struct net_device *netdev) 840 { 841 struct hns3_nic_priv *priv = netdev_priv(netdev); 842 const struct hnae3_ae_ops *ops; 843 844 hns3_disable_irqs_and_tqps(netdev); 845 846 /* stop ae_dev */ 847 ops = priv->ae_handle->ae_algo->ops; 848 if (ops->stop) 849 ops->stop(priv->ae_handle); 850 851 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 852 * during reset process, because driver may not be able 853 * to disable the ring through firmware when downing the netdev. 854 */ 855 if (!hns3_nic_resetting(netdev)) 856 hns3_clear_all_ring(priv->ae_handle, false); 857 858 hns3_reset_tx_queue(priv->ae_handle); 859 } 860 861 static int hns3_nic_net_stop(struct net_device *netdev) 862 { 863 struct hns3_nic_priv *priv = netdev_priv(netdev); 864 struct hnae3_handle *h = hns3_get_handle(netdev); 865 866 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 867 return 0; 868 869 netif_dbg(h, drv, netdev, "net stop\n"); 870 871 if (h->ae_algo->ops->set_timer_task) 872 h->ae_algo->ops->set_timer_task(priv->ae_handle, false); 873 874 netif_carrier_off(netdev); 875 netif_tx_disable(netdev); 876 877 hns3_nic_net_down(netdev); 878 879 return 0; 880 } 881 882 static int hns3_nic_uc_sync(struct net_device *netdev, 883 const unsigned char *addr) 884 { 885 struct hnae3_handle *h = hns3_get_handle(netdev); 886 887 if (h->ae_algo->ops->add_uc_addr) 888 return h->ae_algo->ops->add_uc_addr(h, addr); 889 890 return 0; 891 } 892 893 static int hns3_nic_uc_unsync(struct net_device *netdev, 894 const unsigned char *addr) 895 { 896 struct hnae3_handle *h = hns3_get_handle(netdev); 897 898 /* need ignore the request of removing device address, because 899 * we store the device address and other addresses of uc list 900 * in the function's mac filter list. 901 */ 902 if (ether_addr_equal(addr, netdev->dev_addr)) 903 return 0; 904 905 if (h->ae_algo->ops->rm_uc_addr) 906 return h->ae_algo->ops->rm_uc_addr(h, addr); 907 908 return 0; 909 } 910 911 static int hns3_nic_mc_sync(struct net_device *netdev, 912 const unsigned char *addr) 913 { 914 struct hnae3_handle *h = hns3_get_handle(netdev); 915 916 if (h->ae_algo->ops->add_mc_addr) 917 return h->ae_algo->ops->add_mc_addr(h, addr); 918 919 return 0; 920 } 921 922 static int hns3_nic_mc_unsync(struct net_device *netdev, 923 const unsigned char *addr) 924 { 925 struct hnae3_handle *h = hns3_get_handle(netdev); 926 927 if (h->ae_algo->ops->rm_mc_addr) 928 return h->ae_algo->ops->rm_mc_addr(h, addr); 929 930 return 0; 931 } 932 933 static u8 hns3_get_netdev_flags(struct net_device *netdev) 934 { 935 u8 flags = 0; 936 937 if (netdev->flags & IFF_PROMISC) 938 flags = HNAE3_USER_UPE | HNAE3_USER_MPE | HNAE3_BPE; 939 else if (netdev->flags & IFF_ALLMULTI) 940 flags = HNAE3_USER_MPE; 941 942 return flags; 943 } 944 945 static void hns3_nic_set_rx_mode(struct net_device *netdev) 946 { 947 struct hnae3_handle *h = hns3_get_handle(netdev); 948 u8 new_flags; 949 950 new_flags = hns3_get_netdev_flags(netdev); 951 952 __dev_uc_sync(netdev, hns3_nic_uc_sync, hns3_nic_uc_unsync); 953 __dev_mc_sync(netdev, hns3_nic_mc_sync, hns3_nic_mc_unsync); 954 955 /* User mode Promisc mode enable and vlan filtering is disabled to 956 * let all packets in. 957 */ 958 h->netdev_flags = new_flags; 959 hns3_request_update_promisc_mode(h); 960 } 961 962 void hns3_request_update_promisc_mode(struct hnae3_handle *handle) 963 { 964 const struct hnae3_ae_ops *ops = hns3_get_ops(handle); 965 966 if (ops->request_update_promisc_mode) 967 ops->request_update_promisc_mode(handle); 968 } 969 970 static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring) 971 { 972 struct hns3_tx_spare *tx_spare = ring->tx_spare; 973 u32 ntc, ntu; 974 975 /* This smp_load_acquire() pairs with smp_store_release() in 976 * hns3_tx_spare_update() called in tx desc cleaning process. 977 */ 978 ntc = smp_load_acquire(&tx_spare->last_to_clean); 979 ntu = tx_spare->next_to_use; 980 981 if (ntc > ntu) 982 return ntc - ntu - 1; 983 984 /* The free tx buffer is divided into two part, so pick the 985 * larger one. 986 */ 987 return max(ntc, tx_spare->len - ntu) - 1; 988 } 989 990 static void hns3_tx_spare_update(struct hns3_enet_ring *ring) 991 { 992 struct hns3_tx_spare *tx_spare = ring->tx_spare; 993 994 if (!tx_spare || 995 tx_spare->last_to_clean == tx_spare->next_to_clean) 996 return; 997 998 /* This smp_store_release() pairs with smp_load_acquire() in 999 * hns3_tx_spare_space() called in xmit process. 1000 */ 1001 smp_store_release(&tx_spare->last_to_clean, 1002 tx_spare->next_to_clean); 1003 } 1004 1005 static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring, 1006 struct sk_buff *skb, 1007 u32 space) 1008 { 1009 u32 len = skb->len <= ring->tx_copybreak ? skb->len : 1010 skb_headlen(skb); 1011 1012 if (len > ring->tx_copybreak) 1013 return false; 1014 1015 if (ALIGN(len, dma_get_cache_alignment()) > space) { 1016 hns3_ring_stats_update(ring, tx_spare_full); 1017 return false; 1018 } 1019 1020 return true; 1021 } 1022 1023 static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring, 1024 struct sk_buff *skb, 1025 u32 space) 1026 { 1027 if (skb->len <= ring->tx_copybreak || !tx_sgl || 1028 (!skb_has_frag_list(skb) && 1029 skb_shinfo(skb)->nr_frags < tx_sgl)) 1030 return false; 1031 1032 if (space < HNS3_MAX_SGL_SIZE) { 1033 hns3_ring_stats_update(ring, tx_spare_full); 1034 return false; 1035 } 1036 1037 return true; 1038 } 1039 1040 static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring) 1041 { 1042 u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size; 1043 struct net_device *netdev = ring_to_netdev(ring); 1044 struct hns3_nic_priv *priv = netdev_priv(netdev); 1045 struct hns3_tx_spare *tx_spare; 1046 struct page *page; 1047 dma_addr_t dma; 1048 int order; 1049 1050 if (!alloc_size) 1051 return; 1052 1053 order = get_order(alloc_size); 1054 if (order > MAX_PAGE_ORDER) { 1055 if (net_ratelimit()) 1056 dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n"); 1057 return; 1058 } 1059 1060 tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare), 1061 GFP_KERNEL); 1062 if (!tx_spare) { 1063 /* The driver still work without the tx spare buffer */ 1064 dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n"); 1065 goto devm_kzalloc_error; 1066 } 1067 1068 page = alloc_pages_node(dev_to_node(ring_to_dev(ring)), 1069 GFP_KERNEL, order); 1070 if (!page) { 1071 dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n"); 1072 goto alloc_pages_error; 1073 } 1074 1075 dma = dma_map_page(ring_to_dev(ring), page, 0, 1076 PAGE_SIZE << order, DMA_TO_DEVICE); 1077 if (dma_mapping_error(ring_to_dev(ring), dma)) { 1078 dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n"); 1079 goto dma_mapping_error; 1080 } 1081 1082 tx_spare->dma = dma; 1083 tx_spare->buf = page_address(page); 1084 tx_spare->len = PAGE_SIZE << order; 1085 ring->tx_spare = tx_spare; 1086 ring->tx_copybreak = priv->tx_copybreak; 1087 return; 1088 1089 dma_mapping_error: 1090 put_page(page); 1091 alloc_pages_error: 1092 devm_kfree(ring_to_dev(ring), tx_spare); 1093 devm_kzalloc_error: 1094 ring->tqp->handle->kinfo.tx_spare_buf_size = 0; 1095 } 1096 1097 /* Use hns3_tx_spare_space() to make sure there is enough buffer 1098 * before calling below function to allocate tx buffer. 1099 */ 1100 static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring, 1101 unsigned int size, dma_addr_t *dma, 1102 u32 *cb_len) 1103 { 1104 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1105 u32 ntu = tx_spare->next_to_use; 1106 1107 size = ALIGN(size, dma_get_cache_alignment()); 1108 *cb_len = size; 1109 1110 /* Tx spare buffer wraps back here because the end of 1111 * freed tx buffer is not enough. 1112 */ 1113 if (ntu + size > tx_spare->len) { 1114 *cb_len += (tx_spare->len - ntu); 1115 ntu = 0; 1116 } 1117 1118 tx_spare->next_to_use = ntu + size; 1119 if (tx_spare->next_to_use == tx_spare->len) 1120 tx_spare->next_to_use = 0; 1121 1122 *dma = tx_spare->dma + ntu; 1123 1124 return tx_spare->buf + ntu; 1125 } 1126 1127 static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len) 1128 { 1129 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1130 1131 if (len > tx_spare->next_to_use) { 1132 len -= tx_spare->next_to_use; 1133 tx_spare->next_to_use = tx_spare->len - len; 1134 } else { 1135 tx_spare->next_to_use -= len; 1136 } 1137 } 1138 1139 static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring, 1140 struct hns3_desc_cb *cb) 1141 { 1142 struct hns3_tx_spare *tx_spare = ring->tx_spare; 1143 u32 ntc = tx_spare->next_to_clean; 1144 u32 len = cb->length; 1145 1146 tx_spare->next_to_clean += len; 1147 1148 if (tx_spare->next_to_clean >= tx_spare->len) { 1149 tx_spare->next_to_clean -= tx_spare->len; 1150 1151 if (tx_spare->next_to_clean) { 1152 ntc = 0; 1153 len = tx_spare->next_to_clean; 1154 } 1155 } 1156 1157 /* This tx spare buffer is only really reclaimed after calling 1158 * hns3_tx_spare_update(), so it is still safe to use the info in 1159 * the tx buffer to do the dma sync or sg unmapping after 1160 * tx_spare->next_to_clean is moved forword. 1161 */ 1162 if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) { 1163 dma_addr_t dma = tx_spare->dma + ntc; 1164 1165 dma_sync_single_for_cpu(ring_to_dev(ring), dma, len, 1166 DMA_TO_DEVICE); 1167 } else { 1168 struct sg_table *sgt = tx_spare->buf + ntc; 1169 1170 dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 1171 DMA_TO_DEVICE); 1172 } 1173 } 1174 1175 static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs, 1176 u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes) 1177 { 1178 u32 l4_offset, hdr_len; 1179 union l3_hdr_info l3; 1180 union l4_hdr_info l4; 1181 u32 l4_paylen; 1182 int ret; 1183 1184 if (!skb_is_gso(skb)) 1185 return 0; 1186 1187 ret = skb_cow_head(skb, 0); 1188 if (unlikely(ret < 0)) 1189 return ret; 1190 1191 l3.hdr = skb_network_header(skb); 1192 l4.hdr = skb_transport_header(skb); 1193 1194 /* Software should clear the IPv4's checksum field when tso is 1195 * needed. 1196 */ 1197 if (l3.v4->version == 4) 1198 l3.v4->check = 0; 1199 1200 /* tunnel packet */ 1201 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 1202 SKB_GSO_GRE_CSUM | 1203 SKB_GSO_UDP_TUNNEL | 1204 SKB_GSO_UDP_TUNNEL_CSUM)) { 1205 /* reset l3&l4 pointers from outer to inner headers */ 1206 l3.hdr = skb_inner_network_header(skb); 1207 l4.hdr = skb_inner_transport_header(skb); 1208 1209 /* Software should clear the IPv4's checksum field when 1210 * tso is needed. 1211 */ 1212 if (l3.v4->version == 4) 1213 l3.v4->check = 0; 1214 } 1215 1216 /* normal or tunnel packet */ 1217 l4_offset = l4.hdr - skb->data; 1218 1219 /* remove payload length from inner pseudo checksum when tso */ 1220 l4_paylen = skb->len - l4_offset; 1221 1222 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 1223 hdr_len = sizeof(*l4.udp) + l4_offset; 1224 csum_replace_by_diff(&l4.udp->check, 1225 (__force __wsum)htonl(l4_paylen)); 1226 } else { 1227 hdr_len = (l4.tcp->doff << 2) + l4_offset; 1228 csum_replace_by_diff(&l4.tcp->check, 1229 (__force __wsum)htonl(l4_paylen)); 1230 } 1231 1232 *send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len; 1233 1234 /* find the txbd field values */ 1235 *paylen_fdop_ol4cs = skb->len - hdr_len; 1236 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1); 1237 1238 /* offload outer UDP header checksum */ 1239 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM) 1240 hns3_set_field(*paylen_fdop_ol4cs, HNS3_TXD_OL4CS_B, 1); 1241 1242 /* get MSS for TSO */ 1243 *mss = skb_shinfo(skb)->gso_size; 1244 1245 trace_hns3_tso(skb); 1246 1247 return 0; 1248 } 1249 1250 static int hns3_get_l4_protocol(struct sk_buff *skb, u8 *ol4_proto, 1251 u8 *il4_proto) 1252 { 1253 union l3_hdr_info l3; 1254 unsigned char *l4_hdr; 1255 unsigned char *exthdr; 1256 u8 l4_proto_tmp; 1257 __be16 frag_off; 1258 1259 /* find outer header point */ 1260 l3.hdr = skb_network_header(skb); 1261 l4_hdr = skb_transport_header(skb); 1262 1263 if (skb->protocol == htons(ETH_P_IPV6)) { 1264 exthdr = l3.hdr + sizeof(*l3.v6); 1265 l4_proto_tmp = l3.v6->nexthdr; 1266 if (l4_hdr != exthdr) 1267 ipv6_skip_exthdr(skb, exthdr - skb->data, 1268 &l4_proto_tmp, &frag_off); 1269 } else if (skb->protocol == htons(ETH_P_IP)) { 1270 l4_proto_tmp = l3.v4->protocol; 1271 } else { 1272 return -EINVAL; 1273 } 1274 1275 *ol4_proto = l4_proto_tmp; 1276 1277 /* tunnel packet */ 1278 if (!skb->encapsulation) { 1279 *il4_proto = 0; 1280 return 0; 1281 } 1282 1283 /* find inner header point */ 1284 l3.hdr = skb_inner_network_header(skb); 1285 l4_hdr = skb_inner_transport_header(skb); 1286 1287 if (l3.v6->version == 6) { 1288 exthdr = l3.hdr + sizeof(*l3.v6); 1289 l4_proto_tmp = l3.v6->nexthdr; 1290 if (l4_hdr != exthdr) 1291 ipv6_skip_exthdr(skb, exthdr - skb->data, 1292 &l4_proto_tmp, &frag_off); 1293 } else if (l3.v4->version == 4) { 1294 l4_proto_tmp = l3.v4->protocol; 1295 } 1296 1297 *il4_proto = l4_proto_tmp; 1298 1299 return 0; 1300 } 1301 1302 /* when skb->encapsulation is 0, skb->ip_summed is CHECKSUM_PARTIAL 1303 * and it is udp packet, which has a dest port as the IANA assigned. 1304 * the hardware is expected to do the checksum offload, but the 1305 * hardware will not do the checksum offload when udp dest port is 1306 * 4789, 4790 or 6081. 1307 */ 1308 static bool hns3_tunnel_csum_bug(struct sk_buff *skb) 1309 { 1310 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1311 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); 1312 union l4_hdr_info l4; 1313 1314 /* device version above V3(include V3), the hardware can 1315 * do this checksum offload. 1316 */ 1317 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 1318 return false; 1319 1320 l4.hdr = skb_transport_header(skb); 1321 1322 if (!(!skb->encapsulation && 1323 (l4.udp->dest == htons(IANA_VXLAN_UDP_PORT) || 1324 l4.udp->dest == htons(GENEVE_UDP_PORT) || 1325 l4.udp->dest == htons(IANA_VXLAN_GPE_UDP_PORT)))) 1326 return false; 1327 1328 return true; 1329 } 1330 1331 static void hns3_set_outer_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1332 u32 *ol_type_vlan_len_msec) 1333 { 1334 u32 l2_len, l3_len, l4_len; 1335 unsigned char *il2_hdr; 1336 union l3_hdr_info l3; 1337 union l4_hdr_info l4; 1338 1339 l3.hdr = skb_network_header(skb); 1340 l4.hdr = skb_transport_header(skb); 1341 1342 /* compute OL2 header size, defined in 2 Bytes */ 1343 l2_len = l3.hdr - skb->data; 1344 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L2LEN_S, l2_len >> 1); 1345 1346 /* compute OL3 header size, defined in 4 Bytes */ 1347 l3_len = l4.hdr - l3.hdr; 1348 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L3LEN_S, l3_len >> 2); 1349 1350 il2_hdr = skb_inner_mac_header(skb); 1351 /* compute OL4 header size, defined in 4 Bytes */ 1352 l4_len = il2_hdr - l4.hdr; 1353 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_L4LEN_S, l4_len >> 2); 1354 1355 /* define outer network header type */ 1356 if (skb->protocol == htons(ETH_P_IP)) { 1357 if (skb_is_gso(skb)) 1358 hns3_set_field(*ol_type_vlan_len_msec, 1359 HNS3_TXD_OL3T_S, 1360 HNS3_OL3T_IPV4_CSUM); 1361 else 1362 hns3_set_field(*ol_type_vlan_len_msec, 1363 HNS3_TXD_OL3T_S, 1364 HNS3_OL3T_IPV4_NO_CSUM); 1365 } else if (skb->protocol == htons(ETH_P_IPV6)) { 1366 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_OL3T_S, 1367 HNS3_OL3T_IPV6); 1368 } 1369 1370 if (ol4_proto == IPPROTO_UDP) 1371 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1372 HNS3_TUN_MAC_IN_UDP); 1373 else if (ol4_proto == IPPROTO_GRE) 1374 hns3_set_field(*ol_type_vlan_len_msec, HNS3_TXD_TUNTYPE_S, 1375 HNS3_TUN_NVGRE); 1376 } 1377 1378 static void hns3_set_l3_type(struct sk_buff *skb, union l3_hdr_info l3, 1379 u32 *type_cs_vlan_tso) 1380 { 1381 if (l3.v4->version == 4) { 1382 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1383 HNS3_L3T_IPV4); 1384 1385 /* the stack computes the IP header already, the only time we 1386 * need the hardware to recompute it is in the case of TSO. 1387 */ 1388 if (skb_is_gso(skb)) 1389 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3CS_B, 1); 1390 } else if (l3.v6->version == 6) { 1391 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3T_S, 1392 HNS3_L3T_IPV6); 1393 } 1394 } 1395 1396 static int hns3_set_l4_csum_length(struct sk_buff *skb, union l4_hdr_info l4, 1397 u32 l4_proto, u32 *type_cs_vlan_tso) 1398 { 1399 /* compute inner(/normal) L4 header size, defined in 4 Bytes */ 1400 switch (l4_proto) { 1401 case IPPROTO_TCP: 1402 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1403 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1404 HNS3_L4T_TCP); 1405 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1406 l4.tcp->doff); 1407 break; 1408 case IPPROTO_UDP: 1409 if (hns3_tunnel_csum_bug(skb)) { 1410 int ret = skb_put_padto(skb, HNS3_MIN_TUN_PKT_LEN); 1411 1412 return ret ? ret : skb_checksum_help(skb); 1413 } 1414 1415 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1416 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1417 HNS3_L4T_UDP); 1418 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1419 (sizeof(struct udphdr) >> 2)); 1420 break; 1421 case IPPROTO_SCTP: 1422 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4CS_B, 1); 1423 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4T_S, 1424 HNS3_L4T_SCTP); 1425 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L4LEN_S, 1426 (sizeof(struct sctphdr) >> 2)); 1427 break; 1428 default: 1429 /* drop the skb tunnel packet if hardware don't support, 1430 * because hardware can't calculate csum when TSO. 1431 */ 1432 if (skb_is_gso(skb)) 1433 return -EDOM; 1434 1435 /* the stack computes the IP header already, 1436 * driver calculate l4 checksum when not TSO. 1437 */ 1438 return skb_checksum_help(skb); 1439 } 1440 1441 return 0; 1442 } 1443 1444 static int hns3_set_l2l3l4(struct sk_buff *skb, u8 ol4_proto, 1445 u8 il4_proto, u32 *type_cs_vlan_tso, 1446 u32 *ol_type_vlan_len_msec) 1447 { 1448 unsigned char *l2_hdr = skb->data; 1449 u32 l4_proto = ol4_proto; 1450 union l4_hdr_info l4; 1451 union l3_hdr_info l3; 1452 u32 l2_len, l3_len; 1453 1454 l4.hdr = skb_transport_header(skb); 1455 l3.hdr = skb_network_header(skb); 1456 1457 /* handle encapsulation skb */ 1458 if (skb->encapsulation) { 1459 /* If this is a not UDP/GRE encapsulation skb */ 1460 if (!(ol4_proto == IPPROTO_UDP || ol4_proto == IPPROTO_GRE)) { 1461 /* drop the skb tunnel packet if hardware don't support, 1462 * because hardware can't calculate csum when TSO. 1463 */ 1464 if (skb_is_gso(skb)) 1465 return -EDOM; 1466 1467 /* the stack computes the IP header already, 1468 * driver calculate l4 checksum when not TSO. 1469 */ 1470 return skb_checksum_help(skb); 1471 } 1472 1473 hns3_set_outer_l2l3l4(skb, ol4_proto, ol_type_vlan_len_msec); 1474 1475 /* switch to inner header */ 1476 l2_hdr = skb_inner_mac_header(skb); 1477 l3.hdr = skb_inner_network_header(skb); 1478 l4.hdr = skb_inner_transport_header(skb); 1479 l4_proto = il4_proto; 1480 } 1481 1482 hns3_set_l3_type(skb, l3, type_cs_vlan_tso); 1483 1484 /* compute inner(/normal) L2 header size, defined in 2 Bytes */ 1485 l2_len = l3.hdr - l2_hdr; 1486 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L2LEN_S, l2_len >> 1); 1487 1488 /* compute inner(/normal) L3 header size, defined in 4 Bytes */ 1489 l3_len = l4.hdr - l3.hdr; 1490 hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_L3LEN_S, l3_len >> 2); 1491 1492 return hns3_set_l4_csum_length(skb, l4, l4_proto, type_cs_vlan_tso); 1493 } 1494 1495 static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring, 1496 struct sk_buff *skb) 1497 { 1498 struct hnae3_handle *handle = tx_ring->tqp->handle; 1499 struct hnae3_ae_dev *ae_dev; 1500 struct vlan_ethhdr *vhdr; 1501 int rc; 1502 1503 if (!(skb->protocol == htons(ETH_P_8021Q) || 1504 skb_vlan_tag_present(skb))) 1505 return 0; 1506 1507 /* For HW limitation on HNAE3_DEVICE_VERSION_V2, if port based insert 1508 * VLAN enabled, only one VLAN header is allowed in skb, otherwise it 1509 * will cause RAS error. 1510 */ 1511 ae_dev = hns3_get_ae_dev(handle); 1512 if (unlikely(skb_vlan_tagged_multi(skb) && 1513 ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 && 1514 handle->port_base_vlan_state == 1515 HNAE3_PORT_BASE_VLAN_ENABLE)) 1516 return -EINVAL; 1517 1518 if (skb->protocol == htons(ETH_P_8021Q) && 1519 !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { 1520 /* When HW VLAN acceleration is turned off, and the stack 1521 * sets the protocol to 802.1q, the driver just need to 1522 * set the protocol to the encapsulated ethertype. 1523 */ 1524 skb->protocol = vlan_get_protocol(skb); 1525 return 0; 1526 } 1527 1528 if (skb_vlan_tag_present(skb)) { 1529 /* Based on hw strategy, use out_vtag in two layer tag case, 1530 * and use inner_vtag in one tag case. 1531 */ 1532 if (skb->protocol == htons(ETH_P_8021Q) && 1533 handle->port_base_vlan_state == 1534 HNAE3_PORT_BASE_VLAN_DISABLE) 1535 rc = HNS3_OUTER_VLAN_TAG; 1536 else 1537 rc = HNS3_INNER_VLAN_TAG; 1538 1539 skb->protocol = vlan_get_protocol(skb); 1540 return rc; 1541 } 1542 1543 rc = skb_cow_head(skb, 0); 1544 if (unlikely(rc < 0)) 1545 return rc; 1546 1547 vhdr = skb_vlan_eth_hdr(skb); 1548 vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT) 1549 & VLAN_PRIO_MASK); 1550 1551 skb->protocol = vlan_get_protocol(skb); 1552 return 0; 1553 } 1554 1555 /* check if the hardware is capable of checksum offloading */ 1556 static bool hns3_check_hw_tx_csum(struct sk_buff *skb) 1557 { 1558 struct hns3_nic_priv *priv = netdev_priv(skb->dev); 1559 1560 /* Kindly note, due to backward compatibility of the TX descriptor, 1561 * HW checksum of the non-IP packets and GSO packets is handled at 1562 * different place in the following code 1563 */ 1564 if (skb_csum_is_sctp(skb) || skb_is_gso(skb) || 1565 !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state)) 1566 return false; 1567 1568 return true; 1569 } 1570 1571 struct hns3_desc_param { 1572 u32 paylen_ol4cs; 1573 u32 ol_type_vlan_len_msec; 1574 u32 type_cs_vlan_tso; 1575 u16 mss_hw_csum; 1576 u16 inner_vtag; 1577 u16 out_vtag; 1578 }; 1579 1580 static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa) 1581 { 1582 pa->paylen_ol4cs = skb->len; 1583 pa->ol_type_vlan_len_msec = 0; 1584 pa->type_cs_vlan_tso = 0; 1585 pa->mss_hw_csum = 0; 1586 pa->inner_vtag = 0; 1587 pa->out_vtag = 0; 1588 } 1589 1590 static int hns3_handle_vlan_info(struct hns3_enet_ring *ring, 1591 struct sk_buff *skb, 1592 struct hns3_desc_param *param) 1593 { 1594 int ret; 1595 1596 ret = hns3_handle_vtags(ring, skb); 1597 if (unlikely(ret < 0)) { 1598 hns3_ring_stats_update(ring, tx_vlan_err); 1599 return ret; 1600 } else if (ret == HNS3_INNER_VLAN_TAG) { 1601 param->inner_vtag = skb_vlan_tag_get(skb); 1602 param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1603 VLAN_PRIO_MASK; 1604 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1); 1605 } else if (ret == HNS3_OUTER_VLAN_TAG) { 1606 param->out_vtag = skb_vlan_tag_get(skb); 1607 param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) & 1608 VLAN_PRIO_MASK; 1609 hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B, 1610 1); 1611 } 1612 return 0; 1613 } 1614 1615 static int hns3_handle_csum_partial(struct hns3_enet_ring *ring, 1616 struct sk_buff *skb, 1617 struct hns3_desc_cb *desc_cb, 1618 struct hns3_desc_param *param) 1619 { 1620 u8 ol4_proto, il4_proto; 1621 int ret; 1622 1623 if (hns3_check_hw_tx_csum(skb)) { 1624 /* set checksum start and offset, defined in 2 Bytes */ 1625 hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S, 1626 skb_checksum_start_offset(skb) >> 1); 1627 hns3_set_field(param->ol_type_vlan_len_msec, 1628 HNS3_TXD_CSUM_OFFSET_S, 1629 skb->csum_offset >> 1); 1630 param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B); 1631 return 0; 1632 } 1633 1634 skb_reset_mac_len(skb); 1635 1636 ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto); 1637 if (unlikely(ret < 0)) { 1638 hns3_ring_stats_update(ring, tx_l4_proto_err); 1639 return ret; 1640 } 1641 1642 ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto, 1643 ¶m->type_cs_vlan_tso, 1644 ¶m->ol_type_vlan_len_msec); 1645 if (unlikely(ret < 0)) { 1646 hns3_ring_stats_update(ring, tx_l2l3l4_err); 1647 return ret; 1648 } 1649 1650 ret = hns3_set_tso(skb, ¶m->paylen_ol4cs, ¶m->mss_hw_csum, 1651 ¶m->type_cs_vlan_tso, &desc_cb->send_bytes); 1652 if (unlikely(ret < 0)) { 1653 hns3_ring_stats_update(ring, tx_tso_err); 1654 return ret; 1655 } 1656 return 0; 1657 } 1658 1659 static int hns3_fill_skb_desc(struct hns3_enet_ring *ring, 1660 struct sk_buff *skb, struct hns3_desc *desc, 1661 struct hns3_desc_cb *desc_cb) 1662 { 1663 struct hns3_desc_param param; 1664 int ret; 1665 1666 hns3_init_desc_data(skb, ¶m); 1667 ret = hns3_handle_vlan_info(ring, skb, ¶m); 1668 if (unlikely(ret < 0)) 1669 return ret; 1670 1671 desc_cb->send_bytes = skb->len; 1672 1673 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1674 ret = hns3_handle_csum_partial(ring, skb, desc_cb, ¶m); 1675 if (ret) 1676 return ret; 1677 } 1678 1679 /* Set txbd */ 1680 desc->tx.ol_type_vlan_len_msec = 1681 cpu_to_le32(param.ol_type_vlan_len_msec); 1682 desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso); 1683 desc->tx.paylen_ol4cs = cpu_to_le32(param.paylen_ol4cs); 1684 desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum); 1685 desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag); 1686 desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag); 1687 1688 return 0; 1689 } 1690 1691 static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma, 1692 unsigned int size) 1693 { 1694 #define HNS3_LIKELY_BD_NUM 1 1695 1696 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1697 unsigned int frag_buf_num, k; 1698 int sizeoflast; 1699 1700 if (likely(size <= HNS3_MAX_BD_SIZE)) { 1701 desc->addr = cpu_to_le64(dma); 1702 desc->tx.send_size = cpu_to_le16(size); 1703 desc->tx.bdtp_fe_sc_vld_ra_ri = 1704 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1705 1706 trace_hns3_tx_desc(ring, ring->next_to_use); 1707 ring_ptr_move_fw(ring, next_to_use); 1708 return HNS3_LIKELY_BD_NUM; 1709 } 1710 1711 frag_buf_num = hns3_tx_bd_count(size); 1712 sizeoflast = size % HNS3_MAX_BD_SIZE; 1713 sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE; 1714 1715 /* When frag size is bigger than hardware limit, split this frag */ 1716 for (k = 0; k < frag_buf_num; k++) { 1717 /* now, fill the descriptor */ 1718 desc->addr = cpu_to_le64(dma + HNS3_MAX_BD_SIZE * k); 1719 desc->tx.send_size = cpu_to_le16((k == frag_buf_num - 1) ? 1720 (u16)sizeoflast : (u16)HNS3_MAX_BD_SIZE); 1721 desc->tx.bdtp_fe_sc_vld_ra_ri = 1722 cpu_to_le16(BIT(HNS3_TXD_VLD_B)); 1723 1724 trace_hns3_tx_desc(ring, ring->next_to_use); 1725 /* move ring pointer to next */ 1726 ring_ptr_move_fw(ring, next_to_use); 1727 1728 desc = &ring->desc[ring->next_to_use]; 1729 } 1730 1731 return frag_buf_num; 1732 } 1733 1734 static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv, 1735 unsigned int type) 1736 { 1737 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 1738 struct device *dev = ring_to_dev(ring); 1739 unsigned int size; 1740 dma_addr_t dma; 1741 1742 if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) { 1743 struct sk_buff *skb = (struct sk_buff *)priv; 1744 1745 size = skb_headlen(skb); 1746 if (!size) 1747 return 0; 1748 1749 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); 1750 } else if (type & DESC_TYPE_BOUNCE_HEAD) { 1751 /* Head data has been filled in hns3_handle_tx_bounce(), 1752 * just return 0 here. 1753 */ 1754 return 0; 1755 } else { 1756 skb_frag_t *frag = (skb_frag_t *)priv; 1757 1758 size = skb_frag_size(frag); 1759 if (!size) 1760 return 0; 1761 1762 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); 1763 } 1764 1765 if (unlikely(dma_mapping_error(dev, dma))) { 1766 hns3_ring_stats_update(ring, sw_err_cnt); 1767 return -ENOMEM; 1768 } 1769 1770 desc_cb->priv = priv; 1771 desc_cb->length = size; 1772 desc_cb->dma = dma; 1773 desc_cb->type = type; 1774 1775 return hns3_fill_desc(ring, dma, size); 1776 } 1777 1778 static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1779 unsigned int bd_num) 1780 { 1781 unsigned int size; 1782 int i; 1783 1784 size = skb_headlen(skb); 1785 while (size > HNS3_MAX_BD_SIZE) { 1786 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1787 size -= HNS3_MAX_BD_SIZE; 1788 1789 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1790 return bd_num; 1791 } 1792 1793 if (size) { 1794 bd_size[bd_num++] = size; 1795 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1796 return bd_num; 1797 } 1798 1799 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1800 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1801 size = skb_frag_size(frag); 1802 if (!size) 1803 continue; 1804 1805 while (size > HNS3_MAX_BD_SIZE) { 1806 bd_size[bd_num++] = HNS3_MAX_BD_SIZE; 1807 size -= HNS3_MAX_BD_SIZE; 1808 1809 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1810 return bd_num; 1811 } 1812 1813 bd_size[bd_num++] = size; 1814 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1815 return bd_num; 1816 } 1817 1818 return bd_num; 1819 } 1820 1821 static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size, 1822 u8 max_non_tso_bd_num, unsigned int bd_num, 1823 unsigned int recursion_level) 1824 { 1825 #define HNS3_MAX_RECURSION_LEVEL 24 1826 1827 struct sk_buff *frag_skb; 1828 1829 /* If the total len is within the max bd limit */ 1830 if (likely(skb->len <= HNS3_MAX_BD_SIZE && !recursion_level && 1831 !skb_has_frag_list(skb) && 1832 skb_shinfo(skb)->nr_frags < max_non_tso_bd_num)) 1833 return skb_shinfo(skb)->nr_frags + 1U; 1834 1835 if (unlikely(recursion_level >= HNS3_MAX_RECURSION_LEVEL)) 1836 return UINT_MAX; 1837 1838 bd_num = hns3_skb_bd_num(skb, bd_size, bd_num); 1839 if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM) 1840 return bd_num; 1841 1842 skb_walk_frags(skb, frag_skb) { 1843 bd_num = hns3_tx_bd_num(frag_skb, bd_size, max_non_tso_bd_num, 1844 bd_num, recursion_level + 1); 1845 if (bd_num > HNS3_MAX_TSO_BD_NUM) 1846 return bd_num; 1847 } 1848 1849 return bd_num; 1850 } 1851 1852 static unsigned int hns3_gso_hdr_len(struct sk_buff *skb) 1853 { 1854 if (!skb->encapsulation) 1855 return skb_tcp_all_headers(skb); 1856 1857 return skb_inner_tcp_all_headers(skb); 1858 } 1859 1860 /* HW need every continuous max_non_tso_bd_num buffer data to be larger 1861 * than MSS, we simplify it by ensuring skb_headlen + the first continuous 1862 * max_non_tso_bd_num - 1 frags to be larger than gso header len + mss, 1863 * and the remaining continuous max_non_tso_bd_num - 1 frags to be larger 1864 * than MSS except the last max_non_tso_bd_num - 1 frags. 1865 */ 1866 static bool hns3_skb_need_linearized(struct sk_buff *skb, unsigned int *bd_size, 1867 unsigned int bd_num, u8 max_non_tso_bd_num) 1868 { 1869 unsigned int tot_len = 0; 1870 unsigned int i; 1871 1872 for (i = 0; i < max_non_tso_bd_num - 1U; i++) 1873 tot_len += bd_size[i]; 1874 1875 /* ensure the first max_non_tso_bd_num frags is greater than 1876 * mss + header 1877 */ 1878 if (tot_len + bd_size[max_non_tso_bd_num - 1U] < 1879 skb_shinfo(skb)->gso_size + hns3_gso_hdr_len(skb)) 1880 return true; 1881 1882 /* ensure every continuous max_non_tso_bd_num - 1 buffer is greater 1883 * than mss except the last one. 1884 */ 1885 for (i = 0; i < bd_num - max_non_tso_bd_num; i++) { 1886 tot_len -= bd_size[i]; 1887 tot_len += bd_size[i + max_non_tso_bd_num - 1U]; 1888 1889 if (tot_len < skb_shinfo(skb)->gso_size) 1890 return true; 1891 } 1892 1893 return false; 1894 } 1895 1896 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size) 1897 { 1898 u32 i; 1899 1900 for (i = 0; i < MAX_SKB_FRAGS; i++) 1901 size[i] = skb_frag_size(&shinfo->frags[i]); 1902 } 1903 1904 static int hns3_skb_linearize(struct hns3_enet_ring *ring, 1905 struct sk_buff *skb, 1906 unsigned int bd_num) 1907 { 1908 /* 'bd_num == UINT_MAX' means the skb' fraglist has a 1909 * recursion level of over HNS3_MAX_RECURSION_LEVEL. 1910 */ 1911 if (bd_num == UINT_MAX) { 1912 hns3_ring_stats_update(ring, over_max_recursion); 1913 return -ENOMEM; 1914 } 1915 1916 /* The skb->len has exceeded the hw limitation, linearization 1917 * will not help. 1918 */ 1919 if (skb->len > HNS3_MAX_TSO_SIZE || 1920 (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) { 1921 hns3_ring_stats_update(ring, hw_limitation); 1922 return -ENOMEM; 1923 } 1924 1925 if (__skb_linearize(skb)) { 1926 hns3_ring_stats_update(ring, sw_err_cnt); 1927 return -ENOMEM; 1928 } 1929 1930 return 0; 1931 } 1932 1933 static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring *ring, 1934 struct net_device *netdev, 1935 struct sk_buff *skb) 1936 { 1937 struct hns3_nic_priv *priv = netdev_priv(netdev); 1938 u8 max_non_tso_bd_num = priv->max_non_tso_bd_num; 1939 unsigned int bd_size[HNS3_MAX_TSO_BD_NUM + 1U]; 1940 unsigned int bd_num; 1941 1942 bd_num = hns3_tx_bd_num(skb, bd_size, max_non_tso_bd_num, 0, 0); 1943 if (unlikely(bd_num > max_non_tso_bd_num)) { 1944 if (bd_num <= HNS3_MAX_TSO_BD_NUM && skb_is_gso(skb) && 1945 !hns3_skb_need_linearized(skb, bd_size, bd_num, 1946 max_non_tso_bd_num)) { 1947 trace_hns3_over_max_bd(skb); 1948 goto out; 1949 } 1950 1951 if (hns3_skb_linearize(ring, skb, bd_num)) 1952 return -ENOMEM; 1953 1954 bd_num = hns3_tx_bd_count(skb->len); 1955 1956 hns3_ring_stats_update(ring, tx_copy); 1957 } 1958 1959 out: 1960 if (likely(ring_space(ring) >= bd_num)) 1961 return bd_num; 1962 1963 netif_stop_subqueue(netdev, ring->queue_index); 1964 smp_mb(); /* Memory barrier before checking ring_space */ 1965 1966 /* Start queue in case hns3_clean_tx_ring has just made room 1967 * available and has not seen the queue stopped state performed 1968 * by netif_stop_subqueue above. 1969 */ 1970 if (ring_space(ring) >= bd_num && netif_carrier_ok(netdev) && 1971 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 1972 netif_start_subqueue(netdev, ring->queue_index); 1973 return bd_num; 1974 } 1975 1976 hns3_ring_stats_update(ring, tx_busy); 1977 1978 return -EBUSY; 1979 } 1980 1981 static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig) 1982 { 1983 struct device *dev = ring_to_dev(ring); 1984 unsigned int i; 1985 1986 for (i = 0; i < ring->desc_num; i++) { 1987 struct hns3_desc *desc = &ring->desc[ring->next_to_use]; 1988 struct hns3_desc_cb *desc_cb; 1989 1990 memset(desc, 0, sizeof(*desc)); 1991 1992 /* check if this is where we started */ 1993 if (ring->next_to_use == next_to_use_orig) 1994 break; 1995 1996 /* rollback one */ 1997 ring_ptr_move_bw(ring, next_to_use); 1998 1999 desc_cb = &ring->desc_cb[ring->next_to_use]; 2000 2001 if (!desc_cb->dma) 2002 continue; 2003 2004 /* unmap the descriptor dma address */ 2005 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 2006 dma_unmap_single(dev, desc_cb->dma, desc_cb->length, 2007 DMA_TO_DEVICE); 2008 else if (desc_cb->type & 2009 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) 2010 hns3_tx_spare_rollback(ring, desc_cb->length); 2011 else if (desc_cb->length) 2012 dma_unmap_page(dev, desc_cb->dma, desc_cb->length, 2013 DMA_TO_DEVICE); 2014 2015 desc_cb->length = 0; 2016 desc_cb->dma = 0; 2017 desc_cb->type = DESC_TYPE_UNKNOWN; 2018 } 2019 } 2020 2021 static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring, 2022 struct sk_buff *skb, unsigned int type) 2023 { 2024 struct sk_buff *frag_skb; 2025 int i, ret, bd_num = 0; 2026 2027 ret = hns3_map_and_fill_desc(ring, skb, type); 2028 if (unlikely(ret < 0)) 2029 return ret; 2030 2031 bd_num += ret; 2032 2033 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2034 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2035 2036 ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE); 2037 if (unlikely(ret < 0)) 2038 return ret; 2039 2040 bd_num += ret; 2041 } 2042 2043 skb_walk_frags(skb, frag_skb) { 2044 ret = hns3_fill_skb_to_desc(ring, frag_skb, 2045 DESC_TYPE_FRAGLIST_SKB); 2046 if (unlikely(ret < 0)) 2047 return ret; 2048 2049 bd_num += ret; 2050 } 2051 2052 return bd_num; 2053 } 2054 2055 static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num) 2056 { 2057 #define HNS3_BYTES_PER_64BIT 8 2058 2059 struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {}; 2060 int offset = 0; 2061 2062 /* make sure everything is visible to device before 2063 * excuting tx push or updating doorbell 2064 */ 2065 dma_wmb(); 2066 2067 do { 2068 int idx = (ring->next_to_use - num + ring->desc_num) % 2069 ring->desc_num; 2070 2071 u64_stats_update_begin(&ring->syncp); 2072 ring->stats.tx_push++; 2073 u64_stats_update_end(&ring->syncp); 2074 memcpy(&desc[offset], &ring->desc[idx], 2075 sizeof(struct hns3_desc)); 2076 offset++; 2077 } while (--num); 2078 2079 __iowrite64_copy(ring->tqp->mem_base, desc, 2080 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) / 2081 HNS3_BYTES_PER_64BIT); 2082 } 2083 2084 static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring) 2085 { 2086 #define HNS3_MEM_DOORBELL_OFFSET 64 2087 2088 __le64 bd_num = cpu_to_le64((u64)ring->pending_buf); 2089 2090 /* make sure everything is visible to device before 2091 * excuting tx push or updating doorbell 2092 */ 2093 dma_wmb(); 2094 2095 __iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET, 2096 &bd_num, 1); 2097 u64_stats_update_begin(&ring->syncp); 2098 ring->stats.tx_mem_doorbell += ring->pending_buf; 2099 u64_stats_update_end(&ring->syncp); 2100 } 2101 2102 static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num, 2103 bool doorbell) 2104 { 2105 struct net_device *netdev = ring_to_netdev(ring); 2106 struct hns3_nic_priv *priv = netdev_priv(netdev); 2107 2108 /* when tx push is enabled, the packet whose number of BD below 2109 * HNS3_MAX_PUSH_BD_NUM can be pushed directly. 2110 */ 2111 if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num && 2112 !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) { 2113 /* This smp_store_release() pairs with smp_load_acquire() in 2114 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit 2115 * is updated. 2116 */ 2117 smp_store_release(&ring->last_to_use, ring->next_to_use); 2118 hns3_tx_push_bd(ring, num); 2119 return; 2120 } 2121 2122 ring->pending_buf += num; 2123 2124 if (!doorbell) { 2125 hns3_ring_stats_update(ring, tx_more); 2126 return; 2127 } 2128 2129 /* This smp_store_release() pairs with smp_load_acquire() in 2130 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated. 2131 */ 2132 smp_store_release(&ring->last_to_use, ring->next_to_use); 2133 2134 if (ring->tqp->mem_base) 2135 hns3_tx_mem_doorbell(ring); 2136 else 2137 writel(ring->pending_buf, 2138 ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG); 2139 2140 ring->pending_buf = 0; 2141 } 2142 2143 static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb, 2144 struct hns3_desc *desc) 2145 { 2146 struct hnae3_handle *h = hns3_get_handle(netdev); 2147 2148 if (!(h->ae_algo->ops->set_tx_hwts_info && 2149 h->ae_algo->ops->set_tx_hwts_info(h, skb))) 2150 return; 2151 2152 desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B)); 2153 } 2154 2155 static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring, 2156 struct sk_buff *skb) 2157 { 2158 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2159 unsigned int type = DESC_TYPE_BOUNCE_HEAD; 2160 unsigned int size = skb_headlen(skb); 2161 dma_addr_t dma; 2162 int bd_num = 0; 2163 u32 cb_len; 2164 void *buf; 2165 int ret; 2166 2167 if (skb->len <= ring->tx_copybreak) { 2168 size = skb->len; 2169 type = DESC_TYPE_BOUNCE_ALL; 2170 } 2171 2172 /* hns3_can_use_tx_bounce() is called to ensure the below 2173 * function can always return the tx buffer. 2174 */ 2175 buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len); 2176 2177 ret = skb_copy_bits(skb, 0, buf, size); 2178 if (unlikely(ret < 0)) { 2179 hns3_tx_spare_rollback(ring, cb_len); 2180 hns3_ring_stats_update(ring, copy_bits_err); 2181 return ret; 2182 } 2183 2184 desc_cb->priv = skb; 2185 desc_cb->length = cb_len; 2186 desc_cb->dma = dma; 2187 desc_cb->type = type; 2188 2189 bd_num += hns3_fill_desc(ring, dma, size); 2190 2191 if (type == DESC_TYPE_BOUNCE_HEAD) { 2192 ret = hns3_fill_skb_to_desc(ring, skb, 2193 DESC_TYPE_BOUNCE_HEAD); 2194 if (unlikely(ret < 0)) 2195 return ret; 2196 2197 bd_num += ret; 2198 } 2199 2200 dma_sync_single_for_device(ring_to_dev(ring), dma, size, 2201 DMA_TO_DEVICE); 2202 2203 hns3_ring_stats_update(ring, tx_bounce); 2204 2205 return bd_num; 2206 } 2207 2208 static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring, 2209 struct sk_buff *skb) 2210 { 2211 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2212 u32 nfrag = skb_shinfo(skb)->nr_frags + 1; 2213 struct sg_table *sgt; 2214 int bd_num = 0; 2215 dma_addr_t dma; 2216 u32 cb_len, i; 2217 int nents; 2218 2219 if (skb_has_frag_list(skb)) 2220 nfrag = HNS3_MAX_TSO_BD_NUM; 2221 2222 /* hns3_can_use_tx_sgl() is called to ensure the below 2223 * function can always return the tx buffer. 2224 */ 2225 sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag), 2226 &dma, &cb_len); 2227 2228 /* scatterlist follows by the sg table */ 2229 sgt->sgl = (struct scatterlist *)(sgt + 1); 2230 sg_init_table(sgt->sgl, nfrag); 2231 nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len); 2232 if (unlikely(nents < 0)) { 2233 hns3_tx_spare_rollback(ring, cb_len); 2234 hns3_ring_stats_update(ring, skb2sgl_err); 2235 return -ENOMEM; 2236 } 2237 2238 sgt->orig_nents = nents; 2239 sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents, 2240 DMA_TO_DEVICE); 2241 if (unlikely(!sgt->nents)) { 2242 hns3_tx_spare_rollback(ring, cb_len); 2243 hns3_ring_stats_update(ring, map_sg_err); 2244 return -ENOMEM; 2245 } 2246 2247 desc_cb->priv = skb; 2248 desc_cb->length = cb_len; 2249 desc_cb->dma = dma; 2250 desc_cb->type = DESC_TYPE_SGL_SKB; 2251 2252 for (i = 0; i < sgt->nents; i++) 2253 bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i), 2254 sg_dma_len(sgt->sgl + i)); 2255 hns3_ring_stats_update(ring, tx_sgl); 2256 2257 return bd_num; 2258 } 2259 2260 static int hns3_handle_desc_filling(struct hns3_enet_ring *ring, 2261 struct sk_buff *skb) 2262 { 2263 u32 space; 2264 2265 if (!ring->tx_spare) 2266 goto out; 2267 2268 space = hns3_tx_spare_space(ring); 2269 2270 if (hns3_can_use_tx_sgl(ring, skb, space)) 2271 return hns3_handle_tx_sgl(ring, skb); 2272 2273 if (hns3_can_use_tx_bounce(ring, skb, space)) 2274 return hns3_handle_tx_bounce(ring, skb); 2275 2276 out: 2277 return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB); 2278 } 2279 2280 static int hns3_handle_skb_desc(struct hns3_enet_ring *ring, 2281 struct sk_buff *skb, 2282 struct hns3_desc_cb *desc_cb, 2283 int next_to_use_head) 2284 { 2285 int ret; 2286 2287 ret = hns3_fill_skb_desc(ring, skb, &ring->desc[ring->next_to_use], 2288 desc_cb); 2289 if (unlikely(ret < 0)) 2290 goto fill_err; 2291 2292 /* 'ret < 0' means filling error, 'ret == 0' means skb->len is 2293 * zero, which is unlikely, and 'ret > 0' means how many tx desc 2294 * need to be notified to the hw. 2295 */ 2296 ret = hns3_handle_desc_filling(ring, skb); 2297 if (likely(ret > 0)) 2298 return ret; 2299 2300 fill_err: 2301 hns3_clear_desc(ring, next_to_use_head); 2302 return ret; 2303 } 2304 2305 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev) 2306 { 2307 struct hns3_nic_priv *priv = netdev_priv(netdev); 2308 struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping]; 2309 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use]; 2310 struct netdev_queue *dev_queue; 2311 int pre_ntu, ret; 2312 bool doorbell; 2313 2314 /* Hardware can only handle short frames above 32 bytes */ 2315 if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) { 2316 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2317 2318 hns3_ring_stats_update(ring, sw_err_cnt); 2319 2320 return NETDEV_TX_OK; 2321 } 2322 2323 /* Prefetch the data used later */ 2324 prefetch(skb->data); 2325 2326 ret = hns3_nic_maybe_stop_tx(ring, netdev, skb); 2327 if (unlikely(ret <= 0)) { 2328 if (ret == -EBUSY) { 2329 hns3_tx_doorbell(ring, 0, true); 2330 return NETDEV_TX_BUSY; 2331 } 2332 2333 hns3_rl_err(netdev, "xmit error: %d!\n", ret); 2334 goto out_err_tx_ok; 2335 } 2336 2337 ret = hns3_handle_skb_desc(ring, skb, desc_cb, ring->next_to_use); 2338 if (unlikely(ret <= 0)) 2339 goto out_err_tx_ok; 2340 2341 pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) : 2342 (ring->desc_num - 1); 2343 2344 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2345 hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]); 2346 2347 ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |= 2348 cpu_to_le16(BIT(HNS3_TXD_FE_B)); 2349 trace_hns3_tx_desc(ring, pre_ntu); 2350 2351 skb_tx_timestamp(skb); 2352 2353 /* Complete translate all packets */ 2354 dev_queue = netdev_get_tx_queue(netdev, ring->queue_index); 2355 doorbell = __netdev_tx_sent_queue(dev_queue, desc_cb->send_bytes, 2356 netdev_xmit_more()); 2357 hns3_tx_doorbell(ring, ret, doorbell); 2358 2359 return NETDEV_TX_OK; 2360 2361 out_err_tx_ok: 2362 dev_kfree_skb_any(skb); 2363 hns3_tx_doorbell(ring, 0, !netdev_xmit_more()); 2364 return NETDEV_TX_OK; 2365 } 2366 2367 static int hns3_nic_net_set_mac_address(struct net_device *netdev, void *p) 2368 { 2369 char format_mac_addr_perm[HNAE3_FORMAT_MAC_ADDR_LEN]; 2370 char format_mac_addr_sa[HNAE3_FORMAT_MAC_ADDR_LEN]; 2371 struct hnae3_handle *h = hns3_get_handle(netdev); 2372 struct sockaddr *mac_addr = p; 2373 int ret; 2374 2375 if (!mac_addr || !is_valid_ether_addr((const u8 *)mac_addr->sa_data)) 2376 return -EADDRNOTAVAIL; 2377 2378 if (ether_addr_equal(netdev->dev_addr, mac_addr->sa_data)) { 2379 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data); 2380 netdev_info(netdev, "already using mac address %s\n", 2381 format_mac_addr_sa); 2382 return 0; 2383 } 2384 2385 /* For VF device, if there is a perm_addr, then the user will not 2386 * be allowed to change the address. 2387 */ 2388 if (!hns3_is_phys_func(h->pdev) && 2389 !is_zero_ether_addr(netdev->perm_addr)) { 2390 hnae3_format_mac_addr(format_mac_addr_perm, netdev->perm_addr); 2391 hnae3_format_mac_addr(format_mac_addr_sa, mac_addr->sa_data); 2392 netdev_err(netdev, "has permanent MAC %s, user MAC %s not allow\n", 2393 format_mac_addr_perm, format_mac_addr_sa); 2394 return -EPERM; 2395 } 2396 2397 ret = h->ae_algo->ops->set_mac_addr(h, mac_addr->sa_data, false); 2398 if (ret) { 2399 netdev_err(netdev, "set_mac_address fail, ret=%d!\n", ret); 2400 return ret; 2401 } 2402 2403 eth_hw_addr_set(netdev, mac_addr->sa_data); 2404 2405 return 0; 2406 } 2407 2408 static int hns3_nic_do_ioctl(struct net_device *netdev, 2409 struct ifreq *ifr, int cmd) 2410 { 2411 struct hnae3_handle *h = hns3_get_handle(netdev); 2412 2413 if (!netif_running(netdev)) 2414 return -EINVAL; 2415 2416 if (!h->ae_algo->ops->do_ioctl) 2417 return -EOPNOTSUPP; 2418 2419 return h->ae_algo->ops->do_ioctl(h, ifr, cmd); 2420 } 2421 2422 static int hns3_nic_hwtstamp_get(struct net_device *netdev, 2423 struct kernel_hwtstamp_config *config) 2424 { 2425 struct hnae3_handle *h = hns3_get_handle(netdev); 2426 2427 if (!netif_running(netdev)) 2428 return -EINVAL; 2429 2430 if (!h->ae_algo->ops->hwtstamp_get) 2431 return -EOPNOTSUPP; 2432 2433 return h->ae_algo->ops->hwtstamp_get(h, config); 2434 } 2435 2436 static int hns3_nic_hwtstamp_set(struct net_device *netdev, 2437 struct kernel_hwtstamp_config *config, 2438 struct netlink_ext_ack *extack) 2439 { 2440 struct hnae3_handle *h = hns3_get_handle(netdev); 2441 2442 if (!netif_running(netdev)) 2443 return -EINVAL; 2444 2445 if (!h->ae_algo->ops->hwtstamp_set) 2446 return -EOPNOTSUPP; 2447 2448 return h->ae_algo->ops->hwtstamp_set(h, config, extack); 2449 } 2450 2451 static int hns3_nic_set_features(struct net_device *netdev, 2452 netdev_features_t features) 2453 { 2454 netdev_features_t changed = netdev->features ^ features; 2455 struct hns3_nic_priv *priv = netdev_priv(netdev); 2456 struct hnae3_handle *h = priv->ae_handle; 2457 bool enable; 2458 int ret; 2459 2460 if (changed & (NETIF_F_GRO_HW) && h->ae_algo->ops->set_gro_en) { 2461 enable = !!(features & NETIF_F_GRO_HW); 2462 ret = h->ae_algo->ops->set_gro_en(h, enable); 2463 if (ret) 2464 return ret; 2465 } 2466 2467 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && 2468 h->ae_algo->ops->enable_hw_strip_rxvtag) { 2469 enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 2470 ret = h->ae_algo->ops->enable_hw_strip_rxvtag(h, enable); 2471 if (ret) 2472 return ret; 2473 } 2474 2475 if ((changed & NETIF_F_NTUPLE) && h->ae_algo->ops->enable_fd) { 2476 enable = !!(features & NETIF_F_NTUPLE); 2477 h->ae_algo->ops->enable_fd(h, enable); 2478 } 2479 2480 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 2481 h->ae_algo->ops->cls_flower_active(h)) { 2482 netdev_err(netdev, 2483 "there are offloaded TC filters active, cannot disable HW TC offload\n"); 2484 return -EINVAL; 2485 } 2486 2487 if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) && 2488 h->ae_algo->ops->enable_vlan_filter) { 2489 enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER); 2490 ret = h->ae_algo->ops->enable_vlan_filter(h, enable); 2491 if (ret) 2492 return ret; 2493 } 2494 2495 return 0; 2496 } 2497 2498 static netdev_features_t hns3_features_check(struct sk_buff *skb, 2499 struct net_device *dev, 2500 netdev_features_t features) 2501 { 2502 #define HNS3_MAX_HDR_LEN 480U 2503 #define HNS3_MAX_L4_HDR_LEN 60U 2504 2505 size_t len; 2506 2507 if (skb->ip_summed != CHECKSUM_PARTIAL) 2508 return features; 2509 2510 if (skb->encapsulation) 2511 len = skb_inner_transport_offset(skb); 2512 else 2513 len = skb_transport_offset(skb); 2514 2515 /* Assume L4 is 60 byte as TCP is the only protocol with a 2516 * a flexible value, and it's max len is 60 bytes. 2517 */ 2518 len += HNS3_MAX_L4_HDR_LEN; 2519 2520 /* Hardware only supports checksum on the skb with a max header 2521 * len of 480 bytes. 2522 */ 2523 if (len > HNS3_MAX_HDR_LEN) 2524 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2525 2526 return features; 2527 } 2528 2529 static void hns3_fetch_stats(struct rtnl_link_stats64 *stats, 2530 struct hns3_enet_ring *ring, bool is_tx) 2531 { 2532 unsigned int start; 2533 2534 do { 2535 start = u64_stats_fetch_begin(&ring->syncp); 2536 if (is_tx) { 2537 stats->tx_bytes += ring->stats.tx_bytes; 2538 stats->tx_packets += ring->stats.tx_pkts; 2539 stats->tx_dropped += ring->stats.sw_err_cnt; 2540 stats->tx_dropped += ring->stats.tx_vlan_err; 2541 stats->tx_dropped += ring->stats.tx_l4_proto_err; 2542 stats->tx_dropped += ring->stats.tx_l2l3l4_err; 2543 stats->tx_dropped += ring->stats.tx_tso_err; 2544 stats->tx_dropped += ring->stats.over_max_recursion; 2545 stats->tx_dropped += ring->stats.hw_limitation; 2546 stats->tx_dropped += ring->stats.copy_bits_err; 2547 stats->tx_dropped += ring->stats.skb2sgl_err; 2548 stats->tx_dropped += ring->stats.map_sg_err; 2549 stats->tx_errors += ring->stats.sw_err_cnt; 2550 stats->tx_errors += ring->stats.tx_vlan_err; 2551 stats->tx_errors += ring->stats.tx_l4_proto_err; 2552 stats->tx_errors += ring->stats.tx_l2l3l4_err; 2553 stats->tx_errors += ring->stats.tx_tso_err; 2554 stats->tx_errors += ring->stats.over_max_recursion; 2555 stats->tx_errors += ring->stats.hw_limitation; 2556 stats->tx_errors += ring->stats.copy_bits_err; 2557 stats->tx_errors += ring->stats.skb2sgl_err; 2558 stats->tx_errors += ring->stats.map_sg_err; 2559 } else { 2560 stats->rx_bytes += ring->stats.rx_bytes; 2561 stats->rx_packets += ring->stats.rx_pkts; 2562 stats->rx_dropped += ring->stats.l2_err; 2563 stats->rx_errors += ring->stats.l2_err; 2564 stats->rx_errors += ring->stats.l3l4_csum_err; 2565 stats->rx_crc_errors += ring->stats.l2_err; 2566 stats->multicast += ring->stats.rx_multicast; 2567 stats->rx_length_errors += ring->stats.err_pkt_len; 2568 } 2569 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2570 } 2571 2572 static void hns3_nic_get_stats64(struct net_device *netdev, 2573 struct rtnl_link_stats64 *stats) 2574 { 2575 struct hns3_nic_priv *priv = netdev_priv(netdev); 2576 int queue_num = priv->ae_handle->kinfo.num_tqps; 2577 struct hnae3_handle *handle = priv->ae_handle; 2578 struct rtnl_link_stats64 ring_total_stats; 2579 struct hns3_enet_ring *ring; 2580 int idx; 2581 2582 if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 2583 return; 2584 2585 handle->ae_algo->ops->update_stats(handle); 2586 2587 memset(&ring_total_stats, 0, sizeof(ring_total_stats)); 2588 for (idx = 0; idx < queue_num; idx++) { 2589 /* fetch the tx stats */ 2590 ring = &priv->ring[idx]; 2591 hns3_fetch_stats(&ring_total_stats, ring, true); 2592 2593 /* fetch the rx stats */ 2594 ring = &priv->ring[idx + queue_num]; 2595 hns3_fetch_stats(&ring_total_stats, ring, false); 2596 } 2597 2598 stats->tx_bytes = ring_total_stats.tx_bytes; 2599 stats->tx_packets = ring_total_stats.tx_packets; 2600 stats->rx_bytes = ring_total_stats.rx_bytes; 2601 stats->rx_packets = ring_total_stats.rx_packets; 2602 2603 stats->rx_errors = ring_total_stats.rx_errors; 2604 stats->multicast = ring_total_stats.multicast; 2605 stats->rx_length_errors = ring_total_stats.rx_length_errors; 2606 stats->rx_crc_errors = ring_total_stats.rx_crc_errors; 2607 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 2608 2609 stats->tx_errors = ring_total_stats.tx_errors; 2610 stats->rx_dropped = ring_total_stats.rx_dropped; 2611 stats->tx_dropped = ring_total_stats.tx_dropped; 2612 stats->collisions = netdev->stats.collisions; 2613 stats->rx_over_errors = netdev->stats.rx_over_errors; 2614 stats->rx_frame_errors = netdev->stats.rx_frame_errors; 2615 stats->rx_fifo_errors = netdev->stats.rx_fifo_errors; 2616 stats->tx_aborted_errors = netdev->stats.tx_aborted_errors; 2617 stats->tx_carrier_errors = netdev->stats.tx_carrier_errors; 2618 stats->tx_fifo_errors = netdev->stats.tx_fifo_errors; 2619 stats->tx_heartbeat_errors = netdev->stats.tx_heartbeat_errors; 2620 stats->tx_window_errors = netdev->stats.tx_window_errors; 2621 stats->rx_compressed = netdev->stats.rx_compressed; 2622 stats->tx_compressed = netdev->stats.tx_compressed; 2623 } 2624 2625 static int hns3_setup_tc(struct net_device *netdev, void *type_data) 2626 { 2627 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; 2628 struct hnae3_knic_private_info *kinfo; 2629 u8 tc = mqprio_qopt->qopt.num_tc; 2630 u16 mode = mqprio_qopt->mode; 2631 u8 hw = mqprio_qopt->qopt.hw; 2632 struct hnae3_handle *h; 2633 2634 if (!((hw == TC_MQPRIO_HW_OFFLOAD_TCS && 2635 mode == TC_MQPRIO_MODE_CHANNEL) || (!hw && tc == 0))) 2636 return -EOPNOTSUPP; 2637 2638 if (tc > HNAE3_MAX_TC) 2639 return -EINVAL; 2640 2641 if (!netdev) 2642 return -EINVAL; 2643 2644 h = hns3_get_handle(netdev); 2645 kinfo = &h->kinfo; 2646 2647 netif_dbg(h, drv, netdev, "setup tc: num_tc=%u\n", tc); 2648 2649 return (kinfo->dcb_ops && kinfo->dcb_ops->setup_tc) ? 2650 kinfo->dcb_ops->setup_tc(h, mqprio_qopt) : -EOPNOTSUPP; 2651 } 2652 2653 static int hns3_setup_tc_cls_flower(struct hns3_nic_priv *priv, 2654 struct flow_cls_offload *flow) 2655 { 2656 int tc = tc_classid_to_hwtc(priv->netdev, flow->classid); 2657 struct hnae3_handle *h = hns3_get_handle(priv->netdev); 2658 2659 switch (flow->command) { 2660 case FLOW_CLS_REPLACE: 2661 if (h->ae_algo->ops->add_cls_flower) 2662 return h->ae_algo->ops->add_cls_flower(h, flow, tc); 2663 break; 2664 case FLOW_CLS_DESTROY: 2665 if (h->ae_algo->ops->del_cls_flower) 2666 return h->ae_algo->ops->del_cls_flower(h, flow); 2667 break; 2668 default: 2669 break; 2670 } 2671 2672 return -EOPNOTSUPP; 2673 } 2674 2675 static int hns3_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2676 void *cb_priv) 2677 { 2678 struct hns3_nic_priv *priv = cb_priv; 2679 2680 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data)) 2681 return -EOPNOTSUPP; 2682 2683 switch (type) { 2684 case TC_SETUP_CLSFLOWER: 2685 return hns3_setup_tc_cls_flower(priv, type_data); 2686 default: 2687 return -EOPNOTSUPP; 2688 } 2689 } 2690 2691 static LIST_HEAD(hns3_block_cb_list); 2692 2693 static int hns3_nic_setup_tc(struct net_device *dev, enum tc_setup_type type, 2694 void *type_data) 2695 { 2696 struct hns3_nic_priv *priv = netdev_priv(dev); 2697 int ret; 2698 2699 switch (type) { 2700 case TC_SETUP_QDISC_MQPRIO: 2701 ret = hns3_setup_tc(dev, type_data); 2702 break; 2703 case TC_SETUP_BLOCK: 2704 ret = flow_block_cb_setup_simple(type_data, 2705 &hns3_block_cb_list, 2706 hns3_setup_tc_block_cb, 2707 priv, priv, true); 2708 break; 2709 default: 2710 return -EOPNOTSUPP; 2711 } 2712 2713 return ret; 2714 } 2715 2716 static int hns3_vlan_rx_add_vid(struct net_device *netdev, 2717 __be16 proto, u16 vid) 2718 { 2719 struct hnae3_handle *h = hns3_get_handle(netdev); 2720 int ret = -EIO; 2721 2722 if (h->ae_algo->ops->set_vlan_filter) 2723 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false); 2724 2725 return ret; 2726 } 2727 2728 static int hns3_vlan_rx_kill_vid(struct net_device *netdev, 2729 __be16 proto, u16 vid) 2730 { 2731 struct hnae3_handle *h = hns3_get_handle(netdev); 2732 int ret = -EIO; 2733 2734 if (h->ae_algo->ops->set_vlan_filter) 2735 ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true); 2736 2737 return ret; 2738 } 2739 2740 static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2741 u8 qos, __be16 vlan_proto) 2742 { 2743 struct hnae3_handle *h = hns3_get_handle(netdev); 2744 int ret = -EIO; 2745 2746 netif_dbg(h, drv, netdev, 2747 "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n", 2748 vf, vlan, qos, ntohs(vlan_proto)); 2749 2750 if (h->ae_algo->ops->set_vf_vlan_filter) 2751 ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, 2752 qos, vlan_proto); 2753 2754 return ret; 2755 } 2756 2757 static int hns3_set_vf_spoofchk(struct net_device *netdev, int vf, bool enable) 2758 { 2759 struct hnae3_handle *handle = hns3_get_handle(netdev); 2760 2761 if (hns3_nic_resetting(netdev)) 2762 return -EBUSY; 2763 2764 if (!handle->ae_algo->ops->set_vf_spoofchk) 2765 return -EOPNOTSUPP; 2766 2767 return handle->ae_algo->ops->set_vf_spoofchk(handle, vf, enable); 2768 } 2769 2770 static int hns3_set_vf_trust(struct net_device *netdev, int vf, bool enable) 2771 { 2772 struct hnae3_handle *handle = hns3_get_handle(netdev); 2773 2774 if (!handle->ae_algo->ops->set_vf_trust) 2775 return -EOPNOTSUPP; 2776 2777 return handle->ae_algo->ops->set_vf_trust(handle, vf, enable); 2778 } 2779 2780 static int hns3_nic_change_mtu(struct net_device *netdev, int new_mtu) 2781 { 2782 struct hnae3_handle *h = hns3_get_handle(netdev); 2783 int ret; 2784 2785 if (hns3_nic_resetting(netdev)) 2786 return -EBUSY; 2787 2788 if (!h->ae_algo->ops->set_mtu) 2789 return -EOPNOTSUPP; 2790 2791 netif_dbg(h, drv, netdev, 2792 "change mtu from %u to %d\n", netdev->mtu, new_mtu); 2793 2794 ret = h->ae_algo->ops->set_mtu(h, new_mtu); 2795 if (ret) 2796 netdev_err(netdev, "failed to change MTU in hardware %d\n", 2797 ret); 2798 else 2799 WRITE_ONCE(netdev->mtu, new_mtu); 2800 2801 return ret; 2802 } 2803 2804 static int hns3_get_timeout_queue(struct net_device *ndev) 2805 { 2806 unsigned int i; 2807 2808 /* Find the stopped queue the same way the stack does */ 2809 for (i = 0; i < ndev->num_tx_queues; i++) { 2810 struct netdev_queue *q; 2811 unsigned long trans_start; 2812 2813 q = netdev_get_tx_queue(ndev, i); 2814 trans_start = READ_ONCE(q->trans_start); 2815 if (netif_xmit_stopped(q) && 2816 time_after(jiffies, 2817 (trans_start + ndev->watchdog_timeo))) { 2818 #ifdef CONFIG_BQL 2819 struct dql *dql = &q->dql; 2820 2821 netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n", 2822 dql->last_obj_cnt, dql->num_queued, 2823 dql->adj_limit, dql->num_completed); 2824 #endif 2825 netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n", 2826 q->state, 2827 jiffies_to_msecs(jiffies - trans_start)); 2828 break; 2829 } 2830 } 2831 2832 return i; 2833 } 2834 2835 static void hns3_dump_queue_stats(struct net_device *ndev, 2836 struct hns3_enet_ring *tx_ring, 2837 int timeout_queue) 2838 { 2839 struct napi_struct *napi = &tx_ring->tqp_vector->napi; 2840 struct hns3_nic_priv *priv = netdev_priv(ndev); 2841 2842 netdev_info(ndev, 2843 "tx_timeout count: %llu, queue id: %d, SW_NTU: 0x%x, SW_NTC: 0x%x, napi state: %lu\n", 2844 priv->tx_timeout_count, timeout_queue, tx_ring->next_to_use, 2845 tx_ring->next_to_clean, napi->state); 2846 2847 netdev_info(ndev, 2848 "tx_pkts: %llu, tx_bytes: %llu, sw_err_cnt: %llu, tx_pending: %d\n", 2849 tx_ring->stats.tx_pkts, tx_ring->stats.tx_bytes, 2850 tx_ring->stats.sw_err_cnt, tx_ring->pending_buf); 2851 2852 netdev_info(ndev, 2853 "seg_pkt_cnt: %llu, tx_more: %llu, restart_queue: %llu, tx_busy: %llu\n", 2854 tx_ring->stats.seg_pkt_cnt, tx_ring->stats.tx_more, 2855 tx_ring->stats.restart_queue, tx_ring->stats.tx_busy); 2856 2857 netdev_info(ndev, "tx_push: %llu, tx_mem_doorbell: %llu\n", 2858 tx_ring->stats.tx_push, tx_ring->stats.tx_mem_doorbell); 2859 } 2860 2861 static void hns3_dump_queue_reg(struct net_device *ndev, 2862 struct hns3_enet_ring *tx_ring) 2863 { 2864 netdev_info(ndev, 2865 "BD_NUM: 0x%x HW_HEAD: 0x%x, HW_TAIL: 0x%x, BD_ERR: 0x%x, INT: 0x%x\n", 2866 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_NUM_REG), 2867 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_HEAD_REG), 2868 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TAIL_REG), 2869 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_BD_ERR_REG), 2870 readl(tx_ring->tqp_vector->mask_addr)); 2871 netdev_info(ndev, 2872 "RING_EN: 0x%x, TC: 0x%x, FBD_NUM: 0x%x FBD_OFT: 0x%x, EBD_NUM: 0x%x, EBD_OFT: 0x%x\n", 2873 hns3_tqp_read_reg(tx_ring, HNS3_RING_EN_REG), 2874 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_TC_REG), 2875 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_FBDNUM_REG), 2876 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_OFFSET_REG), 2877 hns3_tqp_read_reg(tx_ring, HNS3_RING_TX_RING_EBDNUM_REG), 2878 hns3_tqp_read_reg(tx_ring, 2879 HNS3_RING_TX_RING_EBD_OFFSET_REG)); 2880 } 2881 2882 static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) 2883 { 2884 struct hns3_nic_priv *priv = netdev_priv(ndev); 2885 struct hnae3_handle *h = hns3_get_handle(ndev); 2886 struct hns3_enet_ring *tx_ring; 2887 u32 timeout_queue; 2888 2889 timeout_queue = hns3_get_timeout_queue(ndev); 2890 if (timeout_queue >= ndev->num_tx_queues) { 2891 netdev_info(ndev, 2892 "no netdev TX timeout queue found, timeout count: %llu\n", 2893 priv->tx_timeout_count); 2894 return false; 2895 } 2896 2897 priv->tx_timeout_count++; 2898 2899 tx_ring = &priv->ring[timeout_queue]; 2900 hns3_dump_queue_stats(ndev, tx_ring, timeout_queue); 2901 2902 /* When mac received many pause frames continuous, it's unable to send 2903 * packets, which may cause tx timeout 2904 */ 2905 if (h->ae_algo->ops->get_mac_stats) { 2906 struct hns3_mac_stats mac_stats; 2907 2908 h->ae_algo->ops->get_mac_stats(h, &mac_stats); 2909 netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n", 2910 mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt); 2911 } 2912 2913 hns3_dump_queue_reg(ndev, tx_ring); 2914 2915 return true; 2916 } 2917 2918 static void hns3_nic_net_timeout(struct net_device *ndev, unsigned int txqueue) 2919 { 2920 struct hns3_nic_priv *priv = netdev_priv(ndev); 2921 struct hnae3_handle *h = priv->ae_handle; 2922 2923 if (!hns3_get_tx_timeo_queue_info(ndev)) 2924 return; 2925 2926 /* request the reset, and let the hclge to determine 2927 * which reset level should be done 2928 */ 2929 if (h->ae_algo->ops->reset_event) 2930 h->ae_algo->ops->reset_event(h->pdev, h); 2931 } 2932 2933 #ifdef CONFIG_RFS_ACCEL 2934 static int hns3_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 2935 u16 rxq_index, u32 flow_id) 2936 { 2937 struct hnae3_handle *h = hns3_get_handle(dev); 2938 struct flow_keys fkeys; 2939 2940 if (!h->ae_algo->ops->add_arfs_entry) 2941 return -EOPNOTSUPP; 2942 2943 if (skb->encapsulation) 2944 return -EPROTONOSUPPORT; 2945 2946 if (!skb_flow_dissect_flow_keys(skb, &fkeys, 0)) 2947 return -EPROTONOSUPPORT; 2948 2949 if ((fkeys.basic.n_proto != htons(ETH_P_IP) && 2950 fkeys.basic.n_proto != htons(ETH_P_IPV6)) || 2951 (fkeys.basic.ip_proto != IPPROTO_TCP && 2952 fkeys.basic.ip_proto != IPPROTO_UDP)) 2953 return -EPROTONOSUPPORT; 2954 2955 return h->ae_algo->ops->add_arfs_entry(h, rxq_index, flow_id, &fkeys); 2956 } 2957 #endif 2958 2959 static int hns3_nic_get_vf_config(struct net_device *ndev, int vf, 2960 struct ifla_vf_info *ivf) 2961 { 2962 struct hnae3_handle *h = hns3_get_handle(ndev); 2963 2964 if (!h->ae_algo->ops->get_vf_config) 2965 return -EOPNOTSUPP; 2966 2967 return h->ae_algo->ops->get_vf_config(h, vf, ivf); 2968 } 2969 2970 static int hns3_nic_set_vf_link_state(struct net_device *ndev, int vf, 2971 int link_state) 2972 { 2973 struct hnae3_handle *h = hns3_get_handle(ndev); 2974 2975 if (!h->ae_algo->ops->set_vf_link_state) 2976 return -EOPNOTSUPP; 2977 2978 return h->ae_algo->ops->set_vf_link_state(h, vf, link_state); 2979 } 2980 2981 static int hns3_nic_set_vf_rate(struct net_device *ndev, int vf, 2982 int min_tx_rate, int max_tx_rate) 2983 { 2984 struct hnae3_handle *h = hns3_get_handle(ndev); 2985 2986 if (!h->ae_algo->ops->set_vf_rate) 2987 return -EOPNOTSUPP; 2988 2989 return h->ae_algo->ops->set_vf_rate(h, vf, min_tx_rate, max_tx_rate, 2990 false); 2991 } 2992 2993 static int hns3_nic_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) 2994 { 2995 struct hnae3_handle *h = hns3_get_handle(netdev); 2996 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 2997 2998 if (!h->ae_algo->ops->set_vf_mac) 2999 return -EOPNOTSUPP; 3000 3001 if (is_multicast_ether_addr(mac)) { 3002 hnae3_format_mac_addr(format_mac_addr, mac); 3003 netdev_err(netdev, 3004 "Invalid MAC:%s specified. Could not set MAC\n", 3005 format_mac_addr); 3006 return -EINVAL; 3007 } 3008 3009 return h->ae_algo->ops->set_vf_mac(h, vf_id, mac); 3010 } 3011 3012 #define HNS3_INVALID_DSCP 0xff 3013 #define HNS3_DSCP_SHIFT 2 3014 3015 static u8 hns3_get_skb_dscp(struct sk_buff *skb) 3016 { 3017 __be16 protocol = skb->protocol; 3018 u8 dscp = HNS3_INVALID_DSCP; 3019 3020 if (protocol == htons(ETH_P_8021Q)) 3021 protocol = vlan_get_protocol(skb); 3022 3023 if (protocol == htons(ETH_P_IP)) 3024 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> HNS3_DSCP_SHIFT; 3025 else if (protocol == htons(ETH_P_IPV6)) 3026 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> HNS3_DSCP_SHIFT; 3027 3028 return dscp; 3029 } 3030 3031 static u16 hns3_nic_select_queue(struct net_device *netdev, 3032 struct sk_buff *skb, 3033 struct net_device *sb_dev) 3034 { 3035 struct hnae3_handle *h = hns3_get_handle(netdev); 3036 u8 dscp; 3037 3038 if (h->kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP || 3039 !h->ae_algo->ops->get_dscp_prio) 3040 goto out; 3041 3042 dscp = hns3_get_skb_dscp(skb); 3043 if (unlikely(dscp >= HNAE3_MAX_DSCP)) 3044 goto out; 3045 3046 skb->priority = h->kinfo.dscp_prio[dscp]; 3047 if (skb->priority == HNAE3_PRIO_ID_INVALID) 3048 skb->priority = 0; 3049 3050 out: 3051 return netdev_pick_tx(netdev, skb, sb_dev); 3052 } 3053 3054 static const struct net_device_ops hns3_nic_netdev_ops = { 3055 .ndo_open = hns3_nic_net_open, 3056 .ndo_stop = hns3_nic_net_stop, 3057 .ndo_start_xmit = hns3_nic_net_xmit, 3058 .ndo_tx_timeout = hns3_nic_net_timeout, 3059 .ndo_set_mac_address = hns3_nic_net_set_mac_address, 3060 .ndo_eth_ioctl = hns3_nic_do_ioctl, 3061 .ndo_change_mtu = hns3_nic_change_mtu, 3062 .ndo_set_features = hns3_nic_set_features, 3063 .ndo_features_check = hns3_features_check, 3064 .ndo_get_stats64 = hns3_nic_get_stats64, 3065 .ndo_setup_tc = hns3_nic_setup_tc, 3066 .ndo_set_rx_mode = hns3_nic_set_rx_mode, 3067 .ndo_vlan_rx_add_vid = hns3_vlan_rx_add_vid, 3068 .ndo_vlan_rx_kill_vid = hns3_vlan_rx_kill_vid, 3069 .ndo_set_vf_vlan = hns3_ndo_set_vf_vlan, 3070 .ndo_set_vf_spoofchk = hns3_set_vf_spoofchk, 3071 .ndo_set_vf_trust = hns3_set_vf_trust, 3072 #ifdef CONFIG_RFS_ACCEL 3073 .ndo_rx_flow_steer = hns3_rx_flow_steer, 3074 #endif 3075 .ndo_get_vf_config = hns3_nic_get_vf_config, 3076 .ndo_set_vf_link_state = hns3_nic_set_vf_link_state, 3077 .ndo_set_vf_rate = hns3_nic_set_vf_rate, 3078 .ndo_set_vf_mac = hns3_nic_set_vf_mac, 3079 .ndo_select_queue = hns3_nic_select_queue, 3080 .ndo_hwtstamp_get = hns3_nic_hwtstamp_get, 3081 .ndo_hwtstamp_set = hns3_nic_hwtstamp_set, 3082 }; 3083 3084 bool hns3_is_phys_func(struct pci_dev *pdev) 3085 { 3086 u32 dev_id = pdev->device; 3087 3088 switch (dev_id) { 3089 case HNAE3_DEV_ID_GE: 3090 case HNAE3_DEV_ID_25GE: 3091 case HNAE3_DEV_ID_25GE_RDMA: 3092 case HNAE3_DEV_ID_25GE_RDMA_MACSEC: 3093 case HNAE3_DEV_ID_50GE_RDMA: 3094 case HNAE3_DEV_ID_50GE_RDMA_MACSEC: 3095 case HNAE3_DEV_ID_100G_RDMA_MACSEC: 3096 case HNAE3_DEV_ID_200G_RDMA: 3097 return true; 3098 case HNAE3_DEV_ID_VF: 3099 case HNAE3_DEV_ID_RDMA_DCB_PFC_VF: 3100 return false; 3101 default: 3102 dev_warn(&pdev->dev, "un-recognized pci device-id %u", 3103 dev_id); 3104 } 3105 3106 return false; 3107 } 3108 3109 static void hns3_disable_sriov(struct pci_dev *pdev) 3110 { 3111 /* If our VFs are assigned we cannot shut down SR-IOV 3112 * without causing issues, so just leave the hardware 3113 * available but disabled 3114 */ 3115 if (pci_vfs_assigned(pdev)) { 3116 dev_warn(&pdev->dev, 3117 "disabling driver while VFs are assigned\n"); 3118 return; 3119 } 3120 3121 pci_disable_sriov(pdev); 3122 } 3123 3124 /* hns3_probe - Device initialization routine 3125 * @pdev: PCI device information struct 3126 * @ent: entry in hns3_pci_tbl 3127 * 3128 * hns3_probe initializes a PF identified by a pci_dev structure. 3129 * The OS initialization, configuring of the PF private structure, 3130 * and a hardware reset occur. 3131 * 3132 * Returns 0 on success, negative on failure 3133 */ 3134 static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3135 { 3136 struct hnae3_ae_dev *ae_dev; 3137 int ret; 3138 3139 ae_dev = devm_kzalloc(&pdev->dev, sizeof(*ae_dev), GFP_KERNEL); 3140 if (!ae_dev) 3141 return -ENOMEM; 3142 3143 ae_dev->pdev = pdev; 3144 ae_dev->flag = ent->driver_data; 3145 pci_set_drvdata(pdev, ae_dev); 3146 3147 ret = hnae3_register_ae_dev(ae_dev); 3148 if (ret) 3149 pci_set_drvdata(pdev, NULL); 3150 3151 return ret; 3152 } 3153 3154 /** 3155 * hns3_clean_vf_config 3156 * @pdev: pointer to a pci_dev structure 3157 * @num_vfs: number of VFs allocated 3158 * 3159 * Clean residual vf config after disable sriov 3160 **/ 3161 static void hns3_clean_vf_config(struct pci_dev *pdev, int num_vfs) 3162 { 3163 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3164 3165 if (ae_dev->ops->clean_vf_config) 3166 ae_dev->ops->clean_vf_config(ae_dev, num_vfs); 3167 } 3168 3169 /* hns3_remove - Device removal routine 3170 * @pdev: PCI device information struct 3171 */ 3172 static void hns3_remove(struct pci_dev *pdev) 3173 { 3174 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3175 3176 if (hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV)) 3177 hns3_disable_sriov(pdev); 3178 3179 hnae3_unregister_ae_dev(ae_dev); 3180 pci_set_drvdata(pdev, NULL); 3181 } 3182 3183 /** 3184 * hns3_pci_sriov_configure 3185 * @pdev: pointer to a pci_dev structure 3186 * @num_vfs: number of VFs to allocate 3187 * 3188 * Enable or change the number of VFs. Called when the user updates the number 3189 * of VFs in sysfs. 3190 **/ 3191 static int hns3_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) 3192 { 3193 int ret; 3194 3195 if (!(hns3_is_phys_func(pdev) && IS_ENABLED(CONFIG_PCI_IOV))) { 3196 dev_warn(&pdev->dev, "Can not config SRIOV\n"); 3197 return -EINVAL; 3198 } 3199 3200 if (num_vfs) { 3201 ret = pci_enable_sriov(pdev, num_vfs); 3202 if (ret) 3203 dev_err(&pdev->dev, "SRIOV enable failed %d\n", ret); 3204 else 3205 return num_vfs; 3206 } else if (!pci_vfs_assigned(pdev)) { 3207 int num_vfs_pre = pci_num_vf(pdev); 3208 3209 pci_disable_sriov(pdev); 3210 hns3_clean_vf_config(pdev, num_vfs_pre); 3211 } else { 3212 dev_warn(&pdev->dev, 3213 "Unable to free VFs because some are assigned to VMs.\n"); 3214 } 3215 3216 return 0; 3217 } 3218 3219 static void hns3_shutdown(struct pci_dev *pdev) 3220 { 3221 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3222 3223 hnae3_unregister_ae_dev(ae_dev); 3224 pci_set_drvdata(pdev, NULL); 3225 3226 if (system_state == SYSTEM_POWER_OFF) 3227 pci_set_power_state(pdev, PCI_D3hot); 3228 } 3229 3230 static int __maybe_unused hns3_suspend(struct device *dev) 3231 { 3232 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3233 3234 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3235 dev_info(dev, "Begin to suspend.\n"); 3236 if (ae_dev->ops && ae_dev->ops->reset_prepare) 3237 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FUNC_RESET); 3238 } 3239 3240 return 0; 3241 } 3242 3243 static int __maybe_unused hns3_resume(struct device *dev) 3244 { 3245 struct hnae3_ae_dev *ae_dev = dev_get_drvdata(dev); 3246 3247 if (ae_dev && hns3_is_phys_func(ae_dev->pdev)) { 3248 dev_info(dev, "Begin to resume.\n"); 3249 if (ae_dev->ops && ae_dev->ops->reset_done) 3250 ae_dev->ops->reset_done(ae_dev); 3251 } 3252 3253 return 0; 3254 } 3255 3256 static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev, 3257 pci_channel_state_t state) 3258 { 3259 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3260 pci_ers_result_t ret; 3261 3262 dev_info(&pdev->dev, "PCI error detected, state(=%u)!!\n", state); 3263 3264 if (state == pci_channel_io_perm_failure) 3265 return PCI_ERS_RESULT_DISCONNECT; 3266 3267 if (!ae_dev || !ae_dev->ops) { 3268 dev_err(&pdev->dev, 3269 "Can't recover - error happened before device initialized\n"); 3270 return PCI_ERS_RESULT_NONE; 3271 } 3272 3273 if (ae_dev->ops->handle_hw_ras_error) 3274 ret = ae_dev->ops->handle_hw_ras_error(ae_dev); 3275 else 3276 return PCI_ERS_RESULT_NONE; 3277 3278 return ret; 3279 } 3280 3281 static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev) 3282 { 3283 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3284 const struct hnae3_ae_ops *ops; 3285 enum hnae3_reset_type reset_type; 3286 struct device *dev = &pdev->dev; 3287 3288 if (!ae_dev || !ae_dev->ops) 3289 return PCI_ERS_RESULT_NONE; 3290 3291 ops = ae_dev->ops; 3292 /* request the reset */ 3293 if (ops->reset_event && ops->get_reset_level && 3294 ops->set_default_reset_request) { 3295 if (ae_dev->hw_err_reset_req) { 3296 reset_type = ops->get_reset_level(ae_dev, 3297 &ae_dev->hw_err_reset_req); 3298 ops->set_default_reset_request(ae_dev, reset_type); 3299 dev_info(dev, "requesting reset due to PCI error\n"); 3300 ops->reset_event(pdev, NULL); 3301 } 3302 3303 return PCI_ERS_RESULT_RECOVERED; 3304 } 3305 3306 return PCI_ERS_RESULT_DISCONNECT; 3307 } 3308 3309 static void hns3_reset_prepare(struct pci_dev *pdev) 3310 { 3311 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3312 3313 dev_info(&pdev->dev, "FLR prepare\n"); 3314 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_prepare) 3315 ae_dev->ops->reset_prepare(ae_dev, HNAE3_FLR_RESET); 3316 } 3317 3318 static void hns3_reset_done(struct pci_dev *pdev) 3319 { 3320 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3321 3322 dev_info(&pdev->dev, "FLR done\n"); 3323 if (ae_dev && ae_dev->ops && ae_dev->ops->reset_done) 3324 ae_dev->ops->reset_done(ae_dev); 3325 } 3326 3327 static const struct pci_error_handlers hns3_err_handler = { 3328 .error_detected = hns3_error_detected, 3329 .slot_reset = hns3_slot_reset, 3330 .reset_prepare = hns3_reset_prepare, 3331 .reset_done = hns3_reset_done, 3332 }; 3333 3334 static SIMPLE_DEV_PM_OPS(hns3_pm_ops, hns3_suspend, hns3_resume); 3335 3336 static struct pci_driver hns3_driver = { 3337 .name = hns3_driver_name, 3338 .id_table = hns3_pci_tbl, 3339 .probe = hns3_probe, 3340 .remove = hns3_remove, 3341 .shutdown = hns3_shutdown, 3342 .driver.pm = &hns3_pm_ops, 3343 .sriov_configure = hns3_pci_sriov_configure, 3344 .err_handler = &hns3_err_handler, 3345 }; 3346 3347 /* set default feature to hns3 */ 3348 static void hns3_set_default_feature(struct net_device *netdev) 3349 { 3350 struct hnae3_handle *h = hns3_get_handle(netdev); 3351 struct pci_dev *pdev = h->pdev; 3352 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 3353 3354 netdev->priv_flags |= IFF_UNICAST_FLT; 3355 3356 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 3357 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 3358 NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO | 3359 NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE | 3360 NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL | 3361 NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST; 3362 3363 if (hnae3_ae_dev_gro_supported(ae_dev)) 3364 netdev->features |= NETIF_F_GRO_HW; 3365 3366 if (hnae3_ae_dev_fd_supported(ae_dev)) 3367 netdev->features |= NETIF_F_NTUPLE; 3368 3369 if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) 3370 netdev->features |= NETIF_F_GSO_UDP_L4; 3371 3372 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 3373 netdev->features |= NETIF_F_HW_CSUM; 3374 else 3375 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 3376 3377 if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps)) 3378 netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 3379 3380 if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps)) 3381 netdev->features |= NETIF_F_HW_TC; 3382 3383 netdev->hw_features |= netdev->features; 3384 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 3385 netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 3386 3387 netdev->vlan_features |= netdev->features & 3388 ~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX | 3389 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE | 3390 NETIF_F_HW_TC); 3391 3392 netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID; 3393 3394 /* The device_version V3 hardware can't offload the checksum for IP in 3395 * GRE packets, but can do it for NvGRE. So default to disable the 3396 * checksum and GSO offload for GRE. 3397 */ 3398 if (ae_dev->dev_version > HNAE3_DEVICE_VERSION_V2) { 3399 netdev->features &= ~NETIF_F_GSO_GRE; 3400 netdev->features &= ~NETIF_F_GSO_GRE_CSUM; 3401 } 3402 } 3403 3404 static int hns3_alloc_buffer(struct hns3_enet_ring *ring, 3405 struct hns3_desc_cb *cb) 3406 { 3407 unsigned int order = hns3_page_order(ring); 3408 struct page *p; 3409 3410 if (ring->page_pool) { 3411 p = page_pool_dev_alloc_frag(ring->page_pool, 3412 &cb->page_offset, 3413 hns3_buf_size(ring)); 3414 if (unlikely(!p)) 3415 return -ENOMEM; 3416 3417 cb->priv = p; 3418 cb->buf = page_address(p); 3419 cb->dma = page_pool_get_dma_addr(p); 3420 cb->type = DESC_TYPE_PP_FRAG; 3421 cb->reuse_flag = 0; 3422 return 0; 3423 } 3424 3425 p = dev_alloc_pages(order); 3426 if (!p) 3427 return -ENOMEM; 3428 3429 cb->priv = p; 3430 cb->page_offset = 0; 3431 cb->reuse_flag = 0; 3432 cb->buf = page_address(p); 3433 cb->length = hns3_page_size(ring); 3434 cb->type = DESC_TYPE_PAGE; 3435 page_ref_add(p, USHRT_MAX - 1); 3436 cb->pagecnt_bias = USHRT_MAX; 3437 3438 return 0; 3439 } 3440 3441 static void hns3_free_buffer(struct hns3_enet_ring *ring, 3442 struct hns3_desc_cb *cb, int budget) 3443 { 3444 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD | 3445 DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB)) 3446 napi_consume_skb(cb->priv, budget); 3447 else if (!HNAE3_IS_TX_RING(ring)) { 3448 if (cb->type & DESC_TYPE_PAGE && cb->pagecnt_bias) 3449 __page_frag_cache_drain(cb->priv, cb->pagecnt_bias); 3450 else if (cb->type & DESC_TYPE_PP_FRAG) 3451 page_pool_put_full_page(ring->page_pool, cb->priv, 3452 false); 3453 } 3454 memset(cb, 0, sizeof(*cb)); 3455 } 3456 3457 static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb) 3458 { 3459 cb->dma = dma_map_page(ring_to_dev(ring), cb->priv, 0, 3460 cb->length, ring_to_dma_dir(ring)); 3461 3462 if (unlikely(dma_mapping_error(ring_to_dev(ring), cb->dma))) 3463 return -EIO; 3464 3465 return 0; 3466 } 3467 3468 static void hns3_unmap_buffer(struct hns3_enet_ring *ring, 3469 struct hns3_desc_cb *cb) 3470 { 3471 if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB)) 3472 dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length, 3473 ring_to_dma_dir(ring)); 3474 else if ((cb->type & DESC_TYPE_PAGE) && cb->length) 3475 dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length, 3476 ring_to_dma_dir(ring)); 3477 else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD | 3478 DESC_TYPE_SGL_SKB)) 3479 hns3_tx_spare_reclaim_cb(ring, cb); 3480 } 3481 3482 static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i) 3483 { 3484 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3485 ring->desc[i].addr = 0; 3486 ring->desc_cb[i].refill = 0; 3487 } 3488 3489 static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i, 3490 int budget) 3491 { 3492 struct hns3_desc_cb *cb = &ring->desc_cb[i]; 3493 3494 if (!ring->desc_cb[i].dma) 3495 return; 3496 3497 hns3_buffer_detach(ring, i); 3498 hns3_free_buffer(ring, cb, budget); 3499 } 3500 3501 static void hns3_free_buffers(struct hns3_enet_ring *ring) 3502 { 3503 int i; 3504 3505 for (i = 0; i < ring->desc_num; i++) 3506 hns3_free_buffer_detach(ring, i, 0); 3507 } 3508 3509 /* free desc along with its attached buffer */ 3510 static void hns3_free_desc(struct hns3_enet_ring *ring) 3511 { 3512 int size = ring->desc_num * sizeof(ring->desc[0]); 3513 3514 hns3_free_buffers(ring); 3515 3516 if (ring->desc) { 3517 dma_free_coherent(ring_to_dev(ring), size, 3518 ring->desc, ring->desc_dma_addr); 3519 ring->desc = NULL; 3520 } 3521 } 3522 3523 static int hns3_alloc_desc(struct hns3_enet_ring *ring) 3524 { 3525 int size = ring->desc_num * sizeof(ring->desc[0]); 3526 3527 ring->desc = dma_alloc_coherent(ring_to_dev(ring), size, 3528 &ring->desc_dma_addr, GFP_KERNEL); 3529 if (!ring->desc) 3530 return -ENOMEM; 3531 3532 return 0; 3533 } 3534 3535 static int hns3_alloc_and_map_buffer(struct hns3_enet_ring *ring, 3536 struct hns3_desc_cb *cb) 3537 { 3538 int ret; 3539 3540 ret = hns3_alloc_buffer(ring, cb); 3541 if (ret || ring->page_pool) 3542 goto out; 3543 3544 ret = hns3_map_buffer(ring, cb); 3545 if (ret) 3546 goto out_with_buf; 3547 3548 return 0; 3549 3550 out_with_buf: 3551 hns3_free_buffer(ring, cb, 0); 3552 out: 3553 return ret; 3554 } 3555 3556 static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i) 3557 { 3558 int ret = hns3_alloc_and_map_buffer(ring, &ring->desc_cb[i]); 3559 3560 if (ret) 3561 return ret; 3562 3563 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3564 ring->desc_cb[i].page_offset); 3565 ring->desc_cb[i].refill = 1; 3566 3567 return 0; 3568 } 3569 3570 /* Allocate memory for raw pkg, and map with dma */ 3571 static int hns3_alloc_ring_buffers(struct hns3_enet_ring *ring) 3572 { 3573 int i, j, ret; 3574 3575 for (i = 0; i < ring->desc_num; i++) { 3576 ret = hns3_alloc_and_attach_buffer(ring, i); 3577 if (ret) 3578 goto out_buffer_fail; 3579 3580 if (!(i % HNS3_RESCHED_BD_NUM)) 3581 cond_resched(); 3582 } 3583 3584 return 0; 3585 3586 out_buffer_fail: 3587 for (j = i - 1; j >= 0; j--) 3588 hns3_free_buffer_detach(ring, j, 0); 3589 return ret; 3590 } 3591 3592 /* detach a in-used buffer and replace with a reserved one */ 3593 static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i, 3594 struct hns3_desc_cb *res_cb) 3595 { 3596 hns3_unmap_buffer(ring, &ring->desc_cb[i]); 3597 ring->desc_cb[i] = *res_cb; 3598 ring->desc_cb[i].refill = 1; 3599 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3600 ring->desc_cb[i].page_offset); 3601 ring->desc[i].rx.bd_base_info = 0; 3602 } 3603 3604 static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i) 3605 { 3606 ring->desc_cb[i].reuse_flag = 0; 3607 ring->desc_cb[i].refill = 1; 3608 ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma + 3609 ring->desc_cb[i].page_offset); 3610 ring->desc[i].rx.bd_base_info = 0; 3611 3612 dma_sync_single_for_device(ring_to_dev(ring), 3613 ring->desc_cb[i].dma + ring->desc_cb[i].page_offset, 3614 hns3_buf_size(ring), 3615 DMA_FROM_DEVICE); 3616 } 3617 3618 static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring, 3619 int *bytes, int *pkts, int budget) 3620 { 3621 /* This smp_load_acquire() pairs with smp_store_release() in 3622 * hns3_tx_doorbell(). 3623 */ 3624 int ltu = smp_load_acquire(&ring->last_to_use); 3625 int ntc = ring->next_to_clean; 3626 struct hns3_desc_cb *desc_cb; 3627 bool reclaimed = false; 3628 struct hns3_desc *desc; 3629 3630 while (ltu != ntc) { 3631 desc = &ring->desc[ntc]; 3632 3633 if (le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri) & 3634 BIT(HNS3_TXD_VLD_B)) 3635 break; 3636 3637 desc_cb = &ring->desc_cb[ntc]; 3638 3639 if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL | 3640 DESC_TYPE_BOUNCE_HEAD | 3641 DESC_TYPE_SGL_SKB)) { 3642 (*pkts)++; 3643 (*bytes) += desc_cb->send_bytes; 3644 } 3645 3646 /* desc_cb will be cleaned, after hnae3_free_buffer_detach */ 3647 hns3_free_buffer_detach(ring, ntc, budget); 3648 3649 if (++ntc == ring->desc_num) 3650 ntc = 0; 3651 3652 /* Issue prefetch for next Tx descriptor */ 3653 prefetch(&ring->desc_cb[ntc]); 3654 reclaimed = true; 3655 } 3656 3657 if (unlikely(!reclaimed)) 3658 return false; 3659 3660 /* This smp_store_release() pairs with smp_load_acquire() in 3661 * ring_space called by hns3_nic_net_xmit. 3662 */ 3663 smp_store_release(&ring->next_to_clean, ntc); 3664 3665 hns3_tx_spare_update(ring); 3666 3667 return true; 3668 } 3669 3670 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget) 3671 { 3672 struct net_device *netdev = ring_to_netdev(ring); 3673 struct hns3_nic_priv *priv = netdev_priv(netdev); 3674 struct netdev_queue *dev_queue; 3675 int bytes, pkts; 3676 3677 bytes = 0; 3678 pkts = 0; 3679 3680 if (unlikely(!hns3_nic_reclaim_desc(ring, &bytes, &pkts, budget))) 3681 return; 3682 3683 ring->tqp_vector->tx_group.total_bytes += bytes; 3684 ring->tqp_vector->tx_group.total_packets += pkts; 3685 3686 u64_stats_update_begin(&ring->syncp); 3687 ring->stats.tx_bytes += bytes; 3688 ring->stats.tx_pkts += pkts; 3689 u64_stats_update_end(&ring->syncp); 3690 3691 dev_queue = netdev_get_tx_queue(netdev, ring->tqp->tqp_index); 3692 netdev_tx_completed_queue(dev_queue, pkts, bytes); 3693 3694 if (unlikely(netif_carrier_ok(netdev) && 3695 ring_space(ring) > HNS3_MAX_TSO_BD_NUM)) { 3696 /* Make sure that anybody stopping the queue after this 3697 * sees the new next_to_clean. 3698 */ 3699 smp_mb(); 3700 if (netif_tx_queue_stopped(dev_queue) && 3701 !test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) { 3702 netif_tx_wake_queue(dev_queue); 3703 ring->stats.restart_queue++; 3704 } 3705 } 3706 } 3707 3708 static int hns3_desc_unused(struct hns3_enet_ring *ring) 3709 { 3710 int ntc = ring->next_to_clean; 3711 int ntu = ring->next_to_use; 3712 3713 if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill)) 3714 return ring->desc_num; 3715 3716 return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu; 3717 } 3718 3719 /* Return true if there is any allocation failure */ 3720 static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring, 3721 int cleand_count) 3722 { 3723 struct hns3_desc_cb *desc_cb; 3724 struct hns3_desc_cb res_cbs; 3725 int i, ret; 3726 3727 for (i = 0; i < cleand_count; i++) { 3728 desc_cb = &ring->desc_cb[ring->next_to_use]; 3729 if (desc_cb->reuse_flag) { 3730 hns3_ring_stats_update(ring, reuse_pg_cnt); 3731 3732 hns3_reuse_buffer(ring, ring->next_to_use); 3733 } else { 3734 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 3735 if (ret) { 3736 hns3_ring_stats_update(ring, sw_err_cnt); 3737 3738 hns3_rl_err(ring_to_netdev(ring), 3739 "alloc rx buffer failed: %d\n", 3740 ret); 3741 3742 writel(i, ring->tqp->io_base + 3743 HNS3_RING_RX_RING_HEAD_REG); 3744 return true; 3745 } 3746 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 3747 3748 hns3_ring_stats_update(ring, non_reuse_pg); 3749 } 3750 3751 ring_ptr_move_fw(ring, next_to_use); 3752 } 3753 3754 writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG); 3755 return false; 3756 } 3757 3758 static bool hns3_can_reuse_page(struct hns3_desc_cb *cb) 3759 { 3760 return page_count(cb->priv) == cb->pagecnt_bias; 3761 } 3762 3763 static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i, 3764 struct hns3_enet_ring *ring, 3765 int pull_len, 3766 struct hns3_desc_cb *desc_cb) 3767 { 3768 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3769 u32 frag_offset = desc_cb->page_offset + pull_len; 3770 int size = le16_to_cpu(desc->rx.size); 3771 u32 frag_size = size - pull_len; 3772 void *frag = napi_alloc_frag(frag_size); 3773 3774 if (unlikely(!frag)) { 3775 hns3_ring_stats_update(ring, frag_alloc_err); 3776 3777 hns3_rl_err(ring_to_netdev(ring), 3778 "failed to allocate rx frag\n"); 3779 return -ENOMEM; 3780 } 3781 3782 desc_cb->reuse_flag = 1; 3783 memcpy(frag, desc_cb->buf + frag_offset, frag_size); 3784 skb_add_rx_frag(skb, i, virt_to_page(frag), 3785 offset_in_page(frag), frag_size, frag_size); 3786 3787 hns3_ring_stats_update(ring, frag_alloc); 3788 return 0; 3789 } 3790 3791 static void hns3_nic_reuse_page(struct sk_buff *skb, int i, 3792 struct hns3_enet_ring *ring, int pull_len, 3793 struct hns3_desc_cb *desc_cb) 3794 { 3795 struct hns3_desc *desc = &ring->desc[ring->next_to_clean]; 3796 u32 frag_offset = desc_cb->page_offset + pull_len; 3797 int size = le16_to_cpu(desc->rx.size); 3798 u32 truesize = hns3_buf_size(ring); 3799 u32 frag_size = size - pull_len; 3800 int ret = 0; 3801 bool reused; 3802 3803 if (ring->page_pool) { 3804 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3805 frag_size, truesize); 3806 return; 3807 } 3808 3809 /* Avoid re-using remote or pfmem page */ 3810 if (unlikely(!dev_page_is_reusable(desc_cb->priv))) 3811 goto out; 3812 3813 reused = hns3_can_reuse_page(desc_cb); 3814 3815 /* Rx page can be reused when: 3816 * 1. Rx page is only owned by the driver when page_offset 3817 * is zero, which means 0 @ truesize will be used by 3818 * stack after skb_add_rx_frag() is called, and the rest 3819 * of rx page can be reused by driver. 3820 * Or 3821 * 2. Rx page is only owned by the driver when page_offset 3822 * is non-zero, which means page_offset @ truesize will 3823 * be used by stack after skb_add_rx_frag() is called, 3824 * and 0 @ truesize can be reused by driver. 3825 */ 3826 if ((!desc_cb->page_offset && reused) || 3827 ((desc_cb->page_offset + truesize + truesize) <= 3828 hns3_page_size(ring) && desc_cb->page_offset)) { 3829 desc_cb->page_offset += truesize; 3830 desc_cb->reuse_flag = 1; 3831 } else if (desc_cb->page_offset && reused) { 3832 desc_cb->page_offset = 0; 3833 desc_cb->reuse_flag = 1; 3834 } else if (frag_size <= ring->rx_copybreak) { 3835 ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb); 3836 if (!ret) 3837 return; 3838 } 3839 3840 out: 3841 desc_cb->pagecnt_bias--; 3842 3843 if (unlikely(!desc_cb->pagecnt_bias)) { 3844 page_ref_add(desc_cb->priv, USHRT_MAX); 3845 desc_cb->pagecnt_bias = USHRT_MAX; 3846 } 3847 3848 skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset, 3849 frag_size, truesize); 3850 3851 if (unlikely(!desc_cb->reuse_flag)) 3852 __page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias); 3853 } 3854 3855 static int hns3_gro_complete(struct sk_buff *skb, u32 l234info) 3856 { 3857 __be16 type = skb->protocol; 3858 struct tcphdr *th; 3859 u32 depth = 0; 3860 3861 while (eth_type_vlan(type)) { 3862 struct vlan_hdr *vh; 3863 3864 if ((depth + VLAN_HLEN) > skb_headlen(skb)) 3865 return -EFAULT; 3866 3867 vh = (struct vlan_hdr *)(skb->data + depth); 3868 type = vh->h_vlan_encapsulated_proto; 3869 depth += VLAN_HLEN; 3870 } 3871 3872 skb_set_network_header(skb, depth); 3873 3874 if (type == htons(ETH_P_IP)) { 3875 const struct iphdr *iph = ip_hdr(skb); 3876 3877 depth += sizeof(struct iphdr); 3878 skb_set_transport_header(skb, depth); 3879 th = tcp_hdr(skb); 3880 th->check = ~tcp_v4_check(skb->len - depth, iph->saddr, 3881 iph->daddr, 0); 3882 } else if (type == htons(ETH_P_IPV6)) { 3883 const struct ipv6hdr *iph = ipv6_hdr(skb); 3884 3885 depth += sizeof(struct ipv6hdr); 3886 skb_set_transport_header(skb, depth); 3887 th = tcp_hdr(skb); 3888 th->check = ~tcp_v6_check(skb->len - depth, &iph->saddr, 3889 &iph->daddr, 0); 3890 } else { 3891 hns3_rl_err(skb->dev, 3892 "Error: FW GRO supports only IPv4/IPv6, not 0x%04x, depth: %d\n", 3893 be16_to_cpu(type), depth); 3894 return -EFAULT; 3895 } 3896 3897 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 3898 if (th->cwr) 3899 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 3900 3901 if (l234info & BIT(HNS3_RXD_GRO_FIXID_B)) 3902 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 3903 3904 skb->csum_start = (unsigned char *)th - skb->head; 3905 skb->csum_offset = offsetof(struct tcphdr, check); 3906 skb->ip_summed = CHECKSUM_PARTIAL; 3907 3908 trace_hns3_gro(skb); 3909 3910 return 0; 3911 } 3912 3913 static void hns3_checksum_complete(struct hns3_enet_ring *ring, 3914 struct sk_buff *skb, u32 ptype, u16 csum) 3915 { 3916 if (ptype == HNS3_INVALID_PTYPE || 3917 hns3_rx_ptype_tbl[ptype].ip_summed != CHECKSUM_COMPLETE) 3918 return; 3919 3920 hns3_ring_stats_update(ring, csum_complete); 3921 skb->ip_summed = CHECKSUM_COMPLETE; 3922 skb->csum = csum_unfold((__force __sum16)csum); 3923 } 3924 3925 static void hns3_rx_handle_csum(struct sk_buff *skb, u32 l234info, 3926 u32 ol_info, u32 ptype) 3927 { 3928 int l3_type, l4_type; 3929 int ol4_type; 3930 3931 if (ptype != HNS3_INVALID_PTYPE) { 3932 skb->csum_level = hns3_rx_ptype_tbl[ptype].csum_level; 3933 skb->ip_summed = hns3_rx_ptype_tbl[ptype].ip_summed; 3934 3935 return; 3936 } 3937 3938 ol4_type = hnae3_get_field(ol_info, HNS3_RXD_OL4ID_M, 3939 HNS3_RXD_OL4ID_S); 3940 switch (ol4_type) { 3941 case HNS3_OL4_TYPE_MAC_IN_UDP: 3942 case HNS3_OL4_TYPE_NVGRE: 3943 skb->csum_level = 1; 3944 fallthrough; 3945 case HNS3_OL4_TYPE_NO_TUN: 3946 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 3947 HNS3_RXD_L3ID_S); 3948 l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 3949 HNS3_RXD_L4ID_S); 3950 /* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */ 3951 if ((l3_type == HNS3_L3_TYPE_IPV4 || 3952 l3_type == HNS3_L3_TYPE_IPV6) && 3953 (l4_type == HNS3_L4_TYPE_UDP || 3954 l4_type == HNS3_L4_TYPE_TCP || 3955 l4_type == HNS3_L4_TYPE_SCTP)) 3956 skb->ip_summed = CHECKSUM_UNNECESSARY; 3957 break; 3958 default: 3959 break; 3960 } 3961 } 3962 3963 static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb, 3964 u32 l234info, u32 bd_base_info, u32 ol_info, 3965 u16 csum) 3966 { 3967 struct net_device *netdev = ring_to_netdev(ring); 3968 struct hns3_nic_priv *priv = netdev_priv(netdev); 3969 u32 ptype = HNS3_INVALID_PTYPE; 3970 3971 skb->ip_summed = CHECKSUM_NONE; 3972 3973 skb_checksum_none_assert(skb); 3974 3975 if (!(netdev->features & NETIF_F_RXCSUM)) 3976 return; 3977 3978 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) 3979 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 3980 HNS3_RXD_PTYPE_S); 3981 3982 hns3_checksum_complete(ring, skb, ptype, csum); 3983 3984 /* check if hardware has done checksum */ 3985 if (!(bd_base_info & BIT(HNS3_RXD_L3L4P_B))) 3986 return; 3987 3988 if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) | 3989 BIT(HNS3_RXD_OL3E_B) | 3990 BIT(HNS3_RXD_OL4E_B)))) { 3991 skb->ip_summed = CHECKSUM_NONE; 3992 hns3_ring_stats_update(ring, l3l4_csum_err); 3993 3994 return; 3995 } 3996 3997 hns3_rx_handle_csum(skb, l234info, ol_info, ptype); 3998 } 3999 4000 static void hns3_rx_skb(struct hns3_enet_ring *ring, struct sk_buff *skb) 4001 { 4002 if (skb_has_frag_list(skb)) 4003 napi_gro_flush(&ring->tqp_vector->napi, false); 4004 4005 napi_gro_receive(&ring->tqp_vector->napi, skb); 4006 } 4007 4008 static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring, 4009 struct hns3_desc *desc, u32 l234info, 4010 u16 *vlan_tag) 4011 { 4012 struct hnae3_handle *handle = ring->tqp->handle; 4013 struct pci_dev *pdev = ring->tqp->handle->pdev; 4014 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4015 4016 if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) { 4017 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 4018 if (!(*vlan_tag & VLAN_VID_MASK)) 4019 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 4020 4021 return (*vlan_tag != 0); 4022 } 4023 4024 #define HNS3_STRP_OUTER_VLAN 0x1 4025 #define HNS3_STRP_INNER_VLAN 0x2 4026 #define HNS3_STRP_BOTH 0x3 4027 4028 /* Hardware always insert VLAN tag into RX descriptor when 4029 * remove the tag from packet, driver needs to determine 4030 * reporting which tag to stack. 4031 */ 4032 switch (hnae3_get_field(l234info, HNS3_RXD_STRP_TAGP_M, 4033 HNS3_RXD_STRP_TAGP_S)) { 4034 case HNS3_STRP_OUTER_VLAN: 4035 if (handle->port_base_vlan_state != 4036 HNAE3_PORT_BASE_VLAN_DISABLE) 4037 return false; 4038 4039 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 4040 return true; 4041 case HNS3_STRP_INNER_VLAN: 4042 if (handle->port_base_vlan_state != 4043 HNAE3_PORT_BASE_VLAN_DISABLE) 4044 return false; 4045 4046 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 4047 return true; 4048 case HNS3_STRP_BOTH: 4049 if (handle->port_base_vlan_state == 4050 HNAE3_PORT_BASE_VLAN_DISABLE) 4051 *vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag); 4052 else 4053 *vlan_tag = le16_to_cpu(desc->rx.vlan_tag); 4054 4055 return true; 4056 default: 4057 return false; 4058 } 4059 } 4060 4061 static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring) 4062 { 4063 ring->desc[ring->next_to_clean].rx.bd_base_info &= 4064 cpu_to_le32(~BIT(HNS3_RXD_VLD_B)); 4065 ring->desc_cb[ring->next_to_clean].refill = 0; 4066 ring->next_to_clean += 1; 4067 4068 if (unlikely(ring->next_to_clean == ring->desc_num)) 4069 ring->next_to_clean = 0; 4070 } 4071 4072 static int hns3_alloc_skb(struct hns3_enet_ring *ring, unsigned int length, 4073 unsigned char *va) 4074 { 4075 struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_clean]; 4076 struct net_device *netdev = ring_to_netdev(ring); 4077 struct sk_buff *skb; 4078 4079 ring->skb = napi_alloc_skb(&ring->tqp_vector->napi, HNS3_RX_HEAD_SIZE); 4080 skb = ring->skb; 4081 if (unlikely(!skb)) { 4082 hns3_rl_err(netdev, "alloc rx skb fail\n"); 4083 hns3_ring_stats_update(ring, sw_err_cnt); 4084 4085 return -ENOMEM; 4086 } 4087 4088 trace_hns3_rx_desc(ring); 4089 prefetchw(skb->data); 4090 4091 ring->pending_buf = 1; 4092 ring->frag_num = 0; 4093 ring->tail_skb = NULL; 4094 if (length <= HNS3_RX_HEAD_SIZE) { 4095 memcpy(__skb_put(skb, length), va, ALIGN(length, sizeof(long))); 4096 4097 /* We can reuse buffer as-is, just make sure it is reusable */ 4098 if (dev_page_is_reusable(desc_cb->priv)) 4099 desc_cb->reuse_flag = 1; 4100 else if (desc_cb->type & DESC_TYPE_PP_FRAG) 4101 page_pool_put_full_page(ring->page_pool, desc_cb->priv, 4102 false); 4103 else /* This page cannot be reused so discard it */ 4104 __page_frag_cache_drain(desc_cb->priv, 4105 desc_cb->pagecnt_bias); 4106 4107 hns3_rx_ring_move_fw(ring); 4108 return 0; 4109 } 4110 4111 if (ring->page_pool) 4112 skb_mark_for_recycle(skb); 4113 4114 hns3_ring_stats_update(ring, seg_pkt_cnt); 4115 4116 ring->pull_len = eth_get_headlen(netdev, va, HNS3_RX_HEAD_SIZE); 4117 __skb_put(skb, ring->pull_len); 4118 hns3_nic_reuse_page(skb, ring->frag_num++, ring, ring->pull_len, 4119 desc_cb); 4120 hns3_rx_ring_move_fw(ring); 4121 4122 return 0; 4123 } 4124 4125 static int hns3_add_frag(struct hns3_enet_ring *ring) 4126 { 4127 struct sk_buff *skb = ring->skb; 4128 struct sk_buff *head_skb = skb; 4129 struct sk_buff *new_skb; 4130 struct hns3_desc_cb *desc_cb; 4131 struct hns3_desc *desc; 4132 u32 bd_base_info; 4133 4134 do { 4135 desc = &ring->desc[ring->next_to_clean]; 4136 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4137 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4138 /* make sure HW write desc complete */ 4139 dma_rmb(); 4140 if (!(bd_base_info & BIT(HNS3_RXD_VLD_B))) 4141 return -ENXIO; 4142 4143 if (unlikely(ring->frag_num >= MAX_SKB_FRAGS)) { 4144 new_skb = napi_alloc_skb(&ring->tqp_vector->napi, 0); 4145 if (unlikely(!new_skb)) { 4146 hns3_rl_err(ring_to_netdev(ring), 4147 "alloc rx fraglist skb fail\n"); 4148 return -ENXIO; 4149 } 4150 4151 if (ring->page_pool) 4152 skb_mark_for_recycle(new_skb); 4153 4154 ring->frag_num = 0; 4155 4156 if (ring->tail_skb) { 4157 ring->tail_skb->next = new_skb; 4158 ring->tail_skb = new_skb; 4159 } else { 4160 skb_shinfo(skb)->frag_list = new_skb; 4161 ring->tail_skb = new_skb; 4162 } 4163 } 4164 4165 if (ring->tail_skb) { 4166 head_skb->truesize += hns3_buf_size(ring); 4167 head_skb->data_len += le16_to_cpu(desc->rx.size); 4168 head_skb->len += le16_to_cpu(desc->rx.size); 4169 skb = ring->tail_skb; 4170 } 4171 4172 dma_sync_single_for_cpu(ring_to_dev(ring), 4173 desc_cb->dma + desc_cb->page_offset, 4174 hns3_buf_size(ring), 4175 DMA_FROM_DEVICE); 4176 4177 hns3_nic_reuse_page(skb, ring->frag_num++, ring, 0, desc_cb); 4178 trace_hns3_rx_desc(ring); 4179 hns3_rx_ring_move_fw(ring); 4180 ring->pending_buf++; 4181 } while (!(bd_base_info & BIT(HNS3_RXD_FE_B))); 4182 4183 return 0; 4184 } 4185 4186 static int hns3_set_gro_and_checksum(struct hns3_enet_ring *ring, 4187 struct sk_buff *skb, u32 l234info, 4188 u32 bd_base_info, u32 ol_info, u16 csum) 4189 { 4190 struct net_device *netdev = ring_to_netdev(ring); 4191 struct hns3_nic_priv *priv = netdev_priv(netdev); 4192 u32 l3_type; 4193 4194 skb_shinfo(skb)->gso_size = hnae3_get_field(bd_base_info, 4195 HNS3_RXD_GRO_SIZE_M, 4196 HNS3_RXD_GRO_SIZE_S); 4197 /* if there is no HW GRO, do not set gro params */ 4198 if (!skb_shinfo(skb)->gso_size) { 4199 hns3_rx_checksum(ring, skb, l234info, bd_base_info, ol_info, 4200 csum); 4201 return 0; 4202 } 4203 4204 NAPI_GRO_CB(skb)->count = hnae3_get_field(l234info, 4205 HNS3_RXD_GRO_COUNT_M, 4206 HNS3_RXD_GRO_COUNT_S); 4207 4208 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 4209 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 4210 HNS3_RXD_PTYPE_S); 4211 4212 l3_type = hns3_rx_ptype_tbl[ptype].l3_type; 4213 } else { 4214 l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 4215 HNS3_RXD_L3ID_S); 4216 } 4217 4218 if (l3_type == HNS3_L3_TYPE_IPV4) 4219 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 4220 else if (l3_type == HNS3_L3_TYPE_IPV6) 4221 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 4222 else 4223 return -EFAULT; 4224 4225 return hns3_gro_complete(skb, l234info); 4226 } 4227 4228 static void hns3_set_rx_skb_rss_type(struct hns3_enet_ring *ring, 4229 struct sk_buff *skb, u32 rss_hash, 4230 u32 l234info, u32 ol_info) 4231 { 4232 enum pkt_hash_types rss_type = PKT_HASH_TYPE_NONE; 4233 struct net_device *netdev = ring_to_netdev(ring); 4234 struct hns3_nic_priv *priv = netdev_priv(netdev); 4235 4236 if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) { 4237 u32 ptype = hnae3_get_field(ol_info, HNS3_RXD_PTYPE_M, 4238 HNS3_RXD_PTYPE_S); 4239 4240 rss_type = hns3_rx_ptype_tbl[ptype].hash_type; 4241 } else { 4242 int l3_type = hnae3_get_field(l234info, HNS3_RXD_L3ID_M, 4243 HNS3_RXD_L3ID_S); 4244 int l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M, 4245 HNS3_RXD_L4ID_S); 4246 4247 if (l3_type == HNS3_L3_TYPE_IPV4 || 4248 l3_type == HNS3_L3_TYPE_IPV6) { 4249 if (l4_type == HNS3_L4_TYPE_UDP || 4250 l4_type == HNS3_L4_TYPE_TCP || 4251 l4_type == HNS3_L4_TYPE_SCTP) 4252 rss_type = PKT_HASH_TYPE_L4; 4253 else if (l4_type == HNS3_L4_TYPE_IGMP || 4254 l4_type == HNS3_L4_TYPE_ICMP) 4255 rss_type = PKT_HASH_TYPE_L3; 4256 } 4257 } 4258 4259 skb_set_hash(skb, rss_hash, rss_type); 4260 } 4261 4262 static void hns3_handle_rx_ts_info(struct net_device *netdev, 4263 struct hns3_desc *desc, struct sk_buff *skb, 4264 u32 bd_base_info) 4265 { 4266 if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) { 4267 struct hnae3_handle *h = hns3_get_handle(netdev); 4268 u32 nsec = le32_to_cpu(desc->ts_nsec); 4269 u32 sec = le32_to_cpu(desc->ts_sec); 4270 4271 if (h->ae_algo->ops->get_rx_hwts) 4272 h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec); 4273 } 4274 } 4275 4276 static void hns3_handle_rx_vlan_tag(struct hns3_enet_ring *ring, 4277 struct hns3_desc *desc, struct sk_buff *skb, 4278 u32 l234info) 4279 { 4280 struct net_device *netdev = ring_to_netdev(ring); 4281 4282 /* Based on hw strategy, the tag offloaded will be stored at 4283 * ot_vlan_tag in two layer tag case, and stored at vlan_tag 4284 * in one layer tag case. 4285 */ 4286 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 4287 u16 vlan_tag; 4288 4289 if (hns3_parse_vlan_tag(ring, desc, l234info, &vlan_tag)) 4290 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 4291 vlan_tag); 4292 } 4293 } 4294 4295 static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb) 4296 { 4297 struct net_device *netdev = ring_to_netdev(ring); 4298 enum hns3_pkt_l2t_type l2_frame_type; 4299 u32 bd_base_info, l234info, ol_info; 4300 struct hns3_desc *desc; 4301 unsigned int len; 4302 int pre_ntc, ret; 4303 u16 csum; 4304 4305 /* bdinfo handled below is only valid on the last BD of the 4306 * current packet, and ring->next_to_clean indicates the first 4307 * descriptor of next packet, so need - 1 below. 4308 */ 4309 pre_ntc = ring->next_to_clean ? (ring->next_to_clean - 1) : 4310 (ring->desc_num - 1); 4311 desc = &ring->desc[pre_ntc]; 4312 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4313 l234info = le32_to_cpu(desc->rx.l234_info); 4314 ol_info = le32_to_cpu(desc->rx.ol_info); 4315 csum = le16_to_cpu(desc->csum); 4316 4317 hns3_handle_rx_ts_info(netdev, desc, skb, bd_base_info); 4318 4319 hns3_handle_rx_vlan_tag(ring, desc, skb, l234info); 4320 4321 if (unlikely(!desc->rx.pkt_len || (l234info & (BIT(HNS3_RXD_TRUNCAT_B) | 4322 BIT(HNS3_RXD_L2E_B))))) { 4323 u64_stats_update_begin(&ring->syncp); 4324 if (l234info & BIT(HNS3_RXD_L2E_B)) 4325 ring->stats.l2_err++; 4326 else 4327 ring->stats.err_pkt_len++; 4328 u64_stats_update_end(&ring->syncp); 4329 4330 return -EFAULT; 4331 } 4332 4333 len = skb->len; 4334 4335 /* Do update ip stack process */ 4336 skb->protocol = eth_type_trans(skb, netdev); 4337 4338 /* This is needed in order to enable forwarding support */ 4339 ret = hns3_set_gro_and_checksum(ring, skb, l234info, 4340 bd_base_info, ol_info, csum); 4341 if (unlikely(ret)) { 4342 hns3_ring_stats_update(ring, rx_err_cnt); 4343 return ret; 4344 } 4345 4346 l2_frame_type = hnae3_get_field(l234info, HNS3_RXD_DMAC_M, 4347 HNS3_RXD_DMAC_S); 4348 4349 u64_stats_update_begin(&ring->syncp); 4350 ring->stats.rx_pkts++; 4351 ring->stats.rx_bytes += len; 4352 4353 if (l2_frame_type == HNS3_L2_TYPE_MULTICAST) 4354 ring->stats.rx_multicast++; 4355 4356 u64_stats_update_end(&ring->syncp); 4357 4358 ring->tqp_vector->rx_group.total_bytes += len; 4359 4360 hns3_set_rx_skb_rss_type(ring, skb, le32_to_cpu(desc->rx.rss_hash), 4361 l234info, ol_info); 4362 return 0; 4363 } 4364 4365 static int hns3_handle_rx_bd(struct hns3_enet_ring *ring) 4366 { 4367 struct sk_buff *skb = ring->skb; 4368 struct hns3_desc_cb *desc_cb; 4369 struct hns3_desc *desc; 4370 unsigned int length; 4371 u32 bd_base_info; 4372 int ret; 4373 4374 desc = &ring->desc[ring->next_to_clean]; 4375 desc_cb = &ring->desc_cb[ring->next_to_clean]; 4376 4377 prefetch(desc); 4378 4379 if (!skb) { 4380 bd_base_info = le32_to_cpu(desc->rx.bd_base_info); 4381 /* Check valid BD */ 4382 if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B)))) 4383 return -ENXIO; 4384 4385 dma_rmb(); 4386 length = le16_to_cpu(desc->rx.size); 4387 4388 ring->va = desc_cb->buf + desc_cb->page_offset; 4389 4390 dma_sync_single_for_cpu(ring_to_dev(ring), 4391 desc_cb->dma + desc_cb->page_offset, 4392 hns3_buf_size(ring), 4393 DMA_FROM_DEVICE); 4394 4395 /* Prefetch first cache line of first page. 4396 * Idea is to cache few bytes of the header of the packet. 4397 * Our L1 Cache line size is 64B so need to prefetch twice to make 4398 * it 128B. But in actual we can have greater size of caches with 4399 * 128B Level 1 cache lines. In such a case, single fetch would 4400 * suffice to cache in the relevant part of the header. 4401 */ 4402 net_prefetch(ring->va); 4403 4404 ret = hns3_alloc_skb(ring, length, ring->va); 4405 skb = ring->skb; 4406 4407 if (ret < 0) /* alloc buffer fail */ 4408 return ret; 4409 if (!(bd_base_info & BIT(HNS3_RXD_FE_B))) { /* need add frag */ 4410 ret = hns3_add_frag(ring); 4411 if (ret) 4412 return ret; 4413 } 4414 } else { 4415 ret = hns3_add_frag(ring); 4416 if (ret) 4417 return ret; 4418 } 4419 4420 /* As the head data may be changed when GRO enable, copy 4421 * the head data in after other data rx completed 4422 */ 4423 if (skb->len > HNS3_RX_HEAD_SIZE) 4424 memcpy(skb->data, ring->va, 4425 ALIGN(ring->pull_len, sizeof(long))); 4426 4427 ret = hns3_handle_bdinfo(ring, skb); 4428 if (unlikely(ret)) { 4429 dev_kfree_skb_any(skb); 4430 return ret; 4431 } 4432 4433 skb_record_rx_queue(skb, ring->tqp->tqp_index); 4434 return 0; 4435 } 4436 4437 int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget, 4438 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *)) 4439 { 4440 #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16 4441 int unused_count = hns3_desc_unused(ring); 4442 bool failure = false; 4443 int recv_pkts = 0; 4444 int err; 4445 4446 unused_count -= ring->pending_buf; 4447 4448 while (recv_pkts < budget) { 4449 /* Reuse or realloc buffers */ 4450 if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) { 4451 failure = failure || 4452 hns3_nic_alloc_rx_buffers(ring, unused_count); 4453 unused_count = 0; 4454 } 4455 4456 /* Poll one pkt */ 4457 err = hns3_handle_rx_bd(ring); 4458 /* Do not get FE for the packet or failed to alloc skb */ 4459 if (unlikely(!ring->skb || err == -ENXIO)) { 4460 goto out; 4461 } else if (likely(!err)) { 4462 rx_fn(ring, ring->skb); 4463 recv_pkts++; 4464 } 4465 4466 unused_count += ring->pending_buf; 4467 ring->skb = NULL; 4468 ring->pending_buf = 0; 4469 } 4470 4471 out: 4472 /* sync head pointer before exiting, since hardware will calculate 4473 * FBD number with head pointer 4474 */ 4475 if (unused_count > 0) 4476 failure = failure || 4477 hns3_nic_alloc_rx_buffers(ring, unused_count); 4478 4479 return failure ? budget : recv_pkts; 4480 } 4481 4482 static void hns3_update_rx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4483 { 4484 struct hns3_enet_ring_group *rx_group = &tqp_vector->rx_group; 4485 struct dim_sample sample = {}; 4486 4487 if (!rx_group->coal.adapt_enable) 4488 return; 4489 4490 dim_update_sample(tqp_vector->event_cnt, rx_group->total_packets, 4491 rx_group->total_bytes, &sample); 4492 net_dim(&rx_group->dim, &sample); 4493 } 4494 4495 static void hns3_update_tx_int_coalesce(struct hns3_enet_tqp_vector *tqp_vector) 4496 { 4497 struct hns3_enet_ring_group *tx_group = &tqp_vector->tx_group; 4498 struct dim_sample sample = {}; 4499 4500 if (!tx_group->coal.adapt_enable) 4501 return; 4502 4503 dim_update_sample(tqp_vector->event_cnt, tx_group->total_packets, 4504 tx_group->total_bytes, &sample); 4505 net_dim(&tx_group->dim, &sample); 4506 } 4507 4508 static int hns3_nic_common_poll(struct napi_struct *napi, int budget) 4509 { 4510 struct hns3_nic_priv *priv = netdev_priv(napi->dev); 4511 struct hns3_enet_ring *ring; 4512 int rx_pkt_total = 0; 4513 4514 struct hns3_enet_tqp_vector *tqp_vector = 4515 container_of(napi, struct hns3_enet_tqp_vector, napi); 4516 bool clean_complete = true; 4517 int rx_budget = budget; 4518 4519 if (unlikely(test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4520 napi_complete(napi); 4521 return 0; 4522 } 4523 4524 /* Since the actual Tx work is minimal, we can give the Tx a larger 4525 * budget and be more aggressive about cleaning up the Tx descriptors. 4526 */ 4527 hns3_for_each_ring(ring, tqp_vector->tx_group) 4528 hns3_clean_tx_ring(ring, budget); 4529 4530 /* make sure rx ring budget not smaller than 1 */ 4531 if (tqp_vector->num_tqps > 1) 4532 rx_budget = max(budget / tqp_vector->num_tqps, 1); 4533 4534 hns3_for_each_ring(ring, tqp_vector->rx_group) { 4535 int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget, 4536 hns3_rx_skb); 4537 if (rx_cleaned >= rx_budget) 4538 clean_complete = false; 4539 4540 rx_pkt_total += rx_cleaned; 4541 } 4542 4543 tqp_vector->rx_group.total_packets += rx_pkt_total; 4544 4545 if (!clean_complete) 4546 return budget; 4547 4548 if (napi_complete(napi) && 4549 likely(!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))) { 4550 hns3_update_rx_int_coalesce(tqp_vector); 4551 hns3_update_tx_int_coalesce(tqp_vector); 4552 4553 hns3_mask_vector_irq(tqp_vector, 1); 4554 } 4555 4556 return rx_pkt_total; 4557 } 4558 4559 static int hns3_create_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4560 struct hnae3_ring_chain_node **head, 4561 bool is_tx) 4562 { 4563 u32 bit_value = is_tx ? HNAE3_RING_TYPE_TX : HNAE3_RING_TYPE_RX; 4564 u32 field_value = is_tx ? HNAE3_RING_GL_TX : HNAE3_RING_GL_RX; 4565 struct hnae3_ring_chain_node *cur_chain = *head; 4566 struct pci_dev *pdev = tqp_vector->handle->pdev; 4567 struct hnae3_ring_chain_node *chain; 4568 struct hns3_enet_ring *ring; 4569 4570 ring = is_tx ? tqp_vector->tx_group.ring : tqp_vector->rx_group.ring; 4571 4572 if (cur_chain) { 4573 while (cur_chain->next) 4574 cur_chain = cur_chain->next; 4575 } 4576 4577 while (ring) { 4578 chain = devm_kzalloc(&pdev->dev, sizeof(*chain), GFP_KERNEL); 4579 if (!chain) 4580 return -ENOMEM; 4581 if (cur_chain) 4582 cur_chain->next = chain; 4583 else 4584 *head = chain; 4585 chain->tqp_index = ring->tqp->tqp_index; 4586 hnae3_set_bit(chain->flag, HNAE3_RING_TYPE_B, 4587 bit_value); 4588 hnae3_set_field(chain->int_gl_idx, 4589 HNAE3_RING_GL_IDX_M, 4590 HNAE3_RING_GL_IDX_S, field_value); 4591 4592 cur_chain = chain; 4593 4594 ring = ring->next; 4595 } 4596 4597 return 0; 4598 } 4599 4600 static struct hnae3_ring_chain_node * 4601 hns3_get_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector) 4602 { 4603 struct pci_dev *pdev = tqp_vector->handle->pdev; 4604 struct hnae3_ring_chain_node *cur_chain = NULL; 4605 struct hnae3_ring_chain_node *chain; 4606 4607 if (hns3_create_ring_chain(tqp_vector, &cur_chain, true)) 4608 goto err_free_chain; 4609 4610 if (hns3_create_ring_chain(tqp_vector, &cur_chain, false)) 4611 goto err_free_chain; 4612 4613 return cur_chain; 4614 4615 err_free_chain: 4616 while (cur_chain) { 4617 chain = cur_chain->next; 4618 devm_kfree(&pdev->dev, cur_chain); 4619 cur_chain = chain; 4620 } 4621 4622 return NULL; 4623 } 4624 4625 static void hns3_free_vector_ring_chain(struct hns3_enet_tqp_vector *tqp_vector, 4626 struct hnae3_ring_chain_node *head) 4627 { 4628 struct pci_dev *pdev = tqp_vector->handle->pdev; 4629 struct hnae3_ring_chain_node *chain_tmp, *chain; 4630 4631 chain = head; 4632 4633 while (chain) { 4634 chain_tmp = chain->next; 4635 devm_kfree(&pdev->dev, chain); 4636 chain = chain_tmp; 4637 } 4638 } 4639 4640 static void hns3_add_ring_to_group(struct hns3_enet_ring_group *group, 4641 struct hns3_enet_ring *ring) 4642 { 4643 ring->next = group->ring; 4644 group->ring = ring; 4645 4646 group->count++; 4647 } 4648 4649 static void hns3_nic_set_cpumask(struct hns3_nic_priv *priv) 4650 { 4651 struct pci_dev *pdev = priv->ae_handle->pdev; 4652 struct hns3_enet_tqp_vector *tqp_vector; 4653 int num_vectors = priv->vector_num; 4654 int numa_node; 4655 int vector_i; 4656 4657 numa_node = dev_to_node(&pdev->dev); 4658 4659 for (vector_i = 0; vector_i < num_vectors; vector_i++) { 4660 tqp_vector = &priv->tqp_vector[vector_i]; 4661 cpumask_set_cpu(cpumask_local_spread(vector_i, numa_node), 4662 &tqp_vector->affinity_mask); 4663 } 4664 } 4665 4666 static void hns3_rx_dim_work(struct work_struct *work) 4667 { 4668 struct dim *dim = container_of(work, struct dim, work); 4669 struct hns3_enet_ring_group *group = container_of(dim, 4670 struct hns3_enet_ring_group, dim); 4671 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4672 struct dim_cq_moder cur_moder = 4673 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 4674 4675 hns3_set_vector_coalesce_rx_gl(group->ring->tqp_vector, cur_moder.usec); 4676 tqp_vector->rx_group.coal.int_gl = cur_moder.usec; 4677 4678 if (cur_moder.pkts < tqp_vector->rx_group.coal.int_ql_max) { 4679 hns3_set_vector_coalesce_rx_ql(tqp_vector, cur_moder.pkts); 4680 tqp_vector->rx_group.coal.int_ql = cur_moder.pkts; 4681 } 4682 4683 dim->state = DIM_START_MEASURE; 4684 } 4685 4686 static void hns3_tx_dim_work(struct work_struct *work) 4687 { 4688 struct dim *dim = container_of(work, struct dim, work); 4689 struct hns3_enet_ring_group *group = container_of(dim, 4690 struct hns3_enet_ring_group, dim); 4691 struct hns3_enet_tqp_vector *tqp_vector = group->ring->tqp_vector; 4692 struct dim_cq_moder cur_moder = 4693 net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 4694 4695 hns3_set_vector_coalesce_tx_gl(tqp_vector, cur_moder.usec); 4696 tqp_vector->tx_group.coal.int_gl = cur_moder.usec; 4697 4698 if (cur_moder.pkts < tqp_vector->tx_group.coal.int_ql_max) { 4699 hns3_set_vector_coalesce_tx_ql(tqp_vector, cur_moder.pkts); 4700 tqp_vector->tx_group.coal.int_ql = cur_moder.pkts; 4701 } 4702 4703 dim->state = DIM_START_MEASURE; 4704 } 4705 4706 static void hns3_nic_init_dim(struct hns3_enet_tqp_vector *tqp_vector) 4707 { 4708 INIT_WORK(&tqp_vector->rx_group.dim.work, hns3_rx_dim_work); 4709 INIT_WORK(&tqp_vector->tx_group.dim.work, hns3_tx_dim_work); 4710 } 4711 4712 static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv) 4713 { 4714 struct hnae3_handle *h = priv->ae_handle; 4715 struct hns3_enet_tqp_vector *tqp_vector; 4716 int ret; 4717 int i; 4718 4719 hns3_nic_set_cpumask(priv); 4720 4721 for (i = 0; i < priv->vector_num; i++) { 4722 tqp_vector = &priv->tqp_vector[i]; 4723 hns3_vector_coalesce_init_hw(tqp_vector, priv); 4724 tqp_vector->num_tqps = 0; 4725 hns3_nic_init_dim(tqp_vector); 4726 } 4727 4728 for (i = 0; i < h->kinfo.num_tqps; i++) { 4729 u16 vector_i = i % priv->vector_num; 4730 u16 tqp_num = h->kinfo.num_tqps; 4731 4732 tqp_vector = &priv->tqp_vector[vector_i]; 4733 4734 hns3_add_ring_to_group(&tqp_vector->tx_group, 4735 &priv->ring[i]); 4736 4737 hns3_add_ring_to_group(&tqp_vector->rx_group, 4738 &priv->ring[i + tqp_num]); 4739 4740 priv->ring[i].tqp_vector = tqp_vector; 4741 priv->ring[i + tqp_num].tqp_vector = tqp_vector; 4742 tqp_vector->num_tqps++; 4743 } 4744 4745 for (i = 0; i < priv->vector_num; i++) { 4746 struct hnae3_ring_chain_node *vector_ring_chain; 4747 4748 tqp_vector = &priv->tqp_vector[i]; 4749 4750 tqp_vector->rx_group.total_bytes = 0; 4751 tqp_vector->rx_group.total_packets = 0; 4752 tqp_vector->tx_group.total_bytes = 0; 4753 tqp_vector->tx_group.total_packets = 0; 4754 tqp_vector->handle = h; 4755 4756 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector); 4757 if (!vector_ring_chain) { 4758 ret = -ENOMEM; 4759 goto map_ring_fail; 4760 } 4761 4762 ret = h->ae_algo->ops->map_ring_to_vector(h, 4763 tqp_vector->vector_irq, vector_ring_chain); 4764 4765 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain); 4766 4767 if (ret) 4768 goto map_ring_fail; 4769 4770 netif_napi_add(priv->netdev, &tqp_vector->napi, 4771 hns3_nic_common_poll); 4772 } 4773 4774 return 0; 4775 4776 map_ring_fail: 4777 while (i--) 4778 netif_napi_del(&priv->tqp_vector[i].napi); 4779 4780 return ret; 4781 } 4782 4783 static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv) 4784 { 4785 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); 4786 struct hns3_enet_coalesce *tx_coal = &priv->tx_coal; 4787 struct hns3_enet_coalesce *rx_coal = &priv->rx_coal; 4788 4789 /* initialize the configuration for interrupt coalescing. 4790 * 1. GL (Interrupt Gap Limiter) 4791 * 2. RL (Interrupt Rate Limiter) 4792 * 3. QL (Interrupt Quantity Limiter) 4793 * 4794 * Default: enable interrupt coalescing self-adaptive and GL 4795 */ 4796 tx_coal->adapt_enable = 1; 4797 rx_coal->adapt_enable = 1; 4798 4799 tx_coal->int_gl = HNS3_INT_GL_50K; 4800 rx_coal->int_gl = HNS3_INT_GL_50K; 4801 4802 rx_coal->flow_level = HNS3_FLOW_LOW; 4803 tx_coal->flow_level = HNS3_FLOW_LOW; 4804 4805 if (ae_dev->dev_specs.int_ql_max) { 4806 tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4807 rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG; 4808 } 4809 } 4810 4811 static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv) 4812 { 4813 struct hnae3_handle *h = priv->ae_handle; 4814 struct hns3_enet_tqp_vector *tqp_vector; 4815 struct hnae3_vector_info *vector; 4816 struct pci_dev *pdev = h->pdev; 4817 u16 tqp_num = h->kinfo.num_tqps; 4818 u16 vector_num; 4819 int ret = 0; 4820 u16 i; 4821 4822 /* RSS size, cpu online and vector_num should be the same */ 4823 /* Should consider 2p/4p later */ 4824 vector_num = min_t(u16, num_online_cpus(), tqp_num); 4825 4826 vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector), 4827 GFP_KERNEL); 4828 if (!vector) 4829 return -ENOMEM; 4830 4831 /* save the actual available vector number */ 4832 vector_num = h->ae_algo->ops->get_vector(h, vector_num, vector); 4833 4834 priv->vector_num = vector_num; 4835 priv->tqp_vector = (struct hns3_enet_tqp_vector *) 4836 devm_kcalloc(&pdev->dev, vector_num, sizeof(*priv->tqp_vector), 4837 GFP_KERNEL); 4838 if (!priv->tqp_vector) { 4839 ret = -ENOMEM; 4840 goto out; 4841 } 4842 4843 for (i = 0; i < priv->vector_num; i++) { 4844 tqp_vector = &priv->tqp_vector[i]; 4845 tqp_vector->idx = i; 4846 tqp_vector->mask_addr = vector[i].io_addr; 4847 tqp_vector->vector_irq = vector[i].vector; 4848 hns3_vector_coalesce_init(tqp_vector, priv); 4849 } 4850 4851 out: 4852 devm_kfree(&pdev->dev, vector); 4853 return ret; 4854 } 4855 4856 static void hns3_clear_ring_group(struct hns3_enet_ring_group *group) 4857 { 4858 group->ring = NULL; 4859 group->count = 0; 4860 } 4861 4862 static void hns3_nic_uninit_vector_data(struct hns3_nic_priv *priv) 4863 { 4864 struct hnae3_ring_chain_node *vector_ring_chain; 4865 struct hnae3_handle *h = priv->ae_handle; 4866 struct hns3_enet_tqp_vector *tqp_vector; 4867 int i; 4868 4869 for (i = 0; i < priv->vector_num; i++) { 4870 tqp_vector = &priv->tqp_vector[i]; 4871 4872 if (!tqp_vector->rx_group.ring && !tqp_vector->tx_group.ring) 4873 continue; 4874 4875 /* Since the mapping can be overwritten, when fail to get the 4876 * chain between vector and ring, we should go on to deal with 4877 * the remaining options. 4878 */ 4879 vector_ring_chain = hns3_get_vector_ring_chain(tqp_vector); 4880 if (!vector_ring_chain) 4881 dev_warn(priv->dev, "failed to get ring chain\n"); 4882 4883 h->ae_algo->ops->unmap_ring_from_vector(h, 4884 tqp_vector->vector_irq, vector_ring_chain); 4885 4886 hns3_free_vector_ring_chain(tqp_vector, vector_ring_chain); 4887 4888 hns3_clear_ring_group(&tqp_vector->rx_group); 4889 hns3_clear_ring_group(&tqp_vector->tx_group); 4890 netif_napi_del(&priv->tqp_vector[i].napi); 4891 } 4892 } 4893 4894 static void hns3_nic_dealloc_vector_data(struct hns3_nic_priv *priv) 4895 { 4896 struct hnae3_handle *h = priv->ae_handle; 4897 struct pci_dev *pdev = h->pdev; 4898 int i, ret; 4899 4900 for (i = 0; i < priv->vector_num; i++) { 4901 struct hns3_enet_tqp_vector *tqp_vector; 4902 4903 tqp_vector = &priv->tqp_vector[i]; 4904 ret = h->ae_algo->ops->put_vector(h, tqp_vector->vector_irq); 4905 if (ret) 4906 return; 4907 } 4908 4909 devm_kfree(&pdev->dev, priv->tqp_vector); 4910 } 4911 4912 static void hns3_update_tx_spare_buf_config(struct hns3_nic_priv *priv) 4913 { 4914 #define HNS3_MIN_SPARE_BUF_SIZE (2 * 1024 * 1024) 4915 #define HNS3_MAX_PACKET_SIZE (64 * 1024) 4916 4917 struct iommu_domain *domain = iommu_get_domain_for_dev(priv->dev); 4918 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); 4919 struct hnae3_handle *handle = priv->ae_handle; 4920 4921 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) 4922 return; 4923 4924 if (!(domain && iommu_is_dma_domain(domain))) 4925 return; 4926 4927 priv->min_tx_copybreak = HNS3_MAX_PACKET_SIZE; 4928 priv->min_tx_spare_buf_size = HNS3_MIN_SPARE_BUF_SIZE; 4929 4930 if (priv->tx_copybreak < priv->min_tx_copybreak) 4931 priv->tx_copybreak = priv->min_tx_copybreak; 4932 if (handle->kinfo.tx_spare_buf_size < priv->min_tx_spare_buf_size) 4933 handle->kinfo.tx_spare_buf_size = priv->min_tx_spare_buf_size; 4934 } 4935 4936 static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv, 4937 unsigned int ring_type) 4938 { 4939 int queue_num = priv->ae_handle->kinfo.num_tqps; 4940 struct hns3_enet_ring *ring; 4941 int desc_num; 4942 4943 if (ring_type == HNAE3_RING_TYPE_TX) { 4944 ring = &priv->ring[q->tqp_index]; 4945 desc_num = priv->ae_handle->kinfo.num_tx_desc; 4946 ring->queue_index = q->tqp_index; 4947 ring->tx_copybreak = priv->tx_copybreak; 4948 ring->last_to_use = 0; 4949 } else { 4950 ring = &priv->ring[q->tqp_index + queue_num]; 4951 desc_num = priv->ae_handle->kinfo.num_rx_desc; 4952 ring->queue_index = q->tqp_index; 4953 ring->rx_copybreak = priv->rx_copybreak; 4954 } 4955 4956 hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type); 4957 4958 ring->tqp = q; 4959 ring->desc = NULL; 4960 ring->desc_cb = NULL; 4961 ring->dev = priv->dev; 4962 ring->desc_dma_addr = 0; 4963 ring->buf_size = q->buf_size; 4964 ring->desc_num = desc_num; 4965 ring->next_to_use = 0; 4966 ring->next_to_clean = 0; 4967 } 4968 4969 static void hns3_queue_to_ring(struct hnae3_queue *tqp, 4970 struct hns3_nic_priv *priv) 4971 { 4972 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_TX); 4973 hns3_ring_get_cfg(tqp, priv, HNAE3_RING_TYPE_RX); 4974 } 4975 4976 static int hns3_get_ring_config(struct hns3_nic_priv *priv) 4977 { 4978 struct hnae3_handle *h = priv->ae_handle; 4979 struct pci_dev *pdev = h->pdev; 4980 int i; 4981 4982 priv->ring = devm_kzalloc(&pdev->dev, 4983 array3_size(h->kinfo.num_tqps, 4984 sizeof(*priv->ring), 2), 4985 GFP_KERNEL); 4986 if (!priv->ring) 4987 return -ENOMEM; 4988 4989 for (i = 0; i < h->kinfo.num_tqps; i++) 4990 hns3_queue_to_ring(h->kinfo.tqp[i], priv); 4991 4992 return 0; 4993 } 4994 4995 static void hns3_put_ring_config(struct hns3_nic_priv *priv) 4996 { 4997 if (!priv->ring) 4998 return; 4999 5000 devm_kfree(priv->dev, priv->ring); 5001 priv->ring = NULL; 5002 } 5003 5004 static void hns3_alloc_page_pool(struct hns3_enet_ring *ring) 5005 { 5006 struct page_pool_params pp_params = { 5007 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 5008 .order = hns3_page_order(ring), 5009 .pool_size = ring->desc_num * hns3_buf_size(ring) / 5010 (PAGE_SIZE << hns3_page_order(ring)), 5011 .nid = dev_to_node(ring_to_dev(ring)), 5012 .dev = ring_to_dev(ring), 5013 .dma_dir = DMA_FROM_DEVICE, 5014 .offset = 0, 5015 .max_len = PAGE_SIZE << hns3_page_order(ring), 5016 }; 5017 5018 ring->page_pool = page_pool_create(&pp_params); 5019 if (IS_ERR(ring->page_pool)) { 5020 dev_warn(ring_to_dev(ring), "page pool creation failed: %ld\n", 5021 PTR_ERR(ring->page_pool)); 5022 ring->page_pool = NULL; 5023 } 5024 } 5025 5026 static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring) 5027 { 5028 int ret; 5029 5030 if (ring->desc_num <= 0 || ring->buf_size <= 0) 5031 return -EINVAL; 5032 5033 ring->desc_cb = devm_kcalloc(ring_to_dev(ring), ring->desc_num, 5034 sizeof(ring->desc_cb[0]), GFP_KERNEL); 5035 if (!ring->desc_cb) { 5036 ret = -ENOMEM; 5037 goto out; 5038 } 5039 5040 ret = hns3_alloc_desc(ring); 5041 if (ret) 5042 goto out_with_desc_cb; 5043 5044 if (!HNAE3_IS_TX_RING(ring)) { 5045 if (page_pool_enabled) 5046 hns3_alloc_page_pool(ring); 5047 5048 ret = hns3_alloc_ring_buffers(ring); 5049 if (ret) 5050 goto out_with_desc; 5051 } else { 5052 hns3_init_tx_spare_buffer(ring); 5053 } 5054 5055 return 0; 5056 5057 out_with_desc: 5058 hns3_free_desc(ring); 5059 out_with_desc_cb: 5060 devm_kfree(ring_to_dev(ring), ring->desc_cb); 5061 ring->desc_cb = NULL; 5062 out: 5063 return ret; 5064 } 5065 5066 void hns3_fini_ring(struct hns3_enet_ring *ring) 5067 { 5068 hns3_free_desc(ring); 5069 devm_kfree(ring_to_dev(ring), ring->desc_cb); 5070 ring->desc_cb = NULL; 5071 ring->next_to_clean = 0; 5072 ring->next_to_use = 0; 5073 ring->last_to_use = 0; 5074 ring->pending_buf = 0; 5075 if (!HNAE3_IS_TX_RING(ring) && ring->skb) { 5076 dev_kfree_skb_any(ring->skb); 5077 ring->skb = NULL; 5078 } else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) { 5079 struct hns3_tx_spare *tx_spare = ring->tx_spare; 5080 5081 dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len, 5082 DMA_TO_DEVICE); 5083 free_pages((unsigned long)tx_spare->buf, 5084 get_order(tx_spare->len)); 5085 devm_kfree(ring_to_dev(ring), tx_spare); 5086 ring->tx_spare = NULL; 5087 } 5088 5089 if (!HNAE3_IS_TX_RING(ring) && ring->page_pool) { 5090 page_pool_destroy(ring->page_pool); 5091 ring->page_pool = NULL; 5092 } 5093 } 5094 5095 static int hns3_buf_size2type(u32 buf_size) 5096 { 5097 int bd_size_type; 5098 5099 switch (buf_size) { 5100 case 512: 5101 bd_size_type = HNS3_BD_SIZE_512_TYPE; 5102 break; 5103 case 1024: 5104 bd_size_type = HNS3_BD_SIZE_1024_TYPE; 5105 break; 5106 case 2048: 5107 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 5108 break; 5109 case 4096: 5110 bd_size_type = HNS3_BD_SIZE_4096_TYPE; 5111 break; 5112 default: 5113 bd_size_type = HNS3_BD_SIZE_2048_TYPE; 5114 } 5115 5116 return bd_size_type; 5117 } 5118 5119 static void hns3_init_ring_hw(struct hns3_enet_ring *ring) 5120 { 5121 dma_addr_t dma = ring->desc_dma_addr; 5122 struct hnae3_queue *q = ring->tqp; 5123 5124 if (!HNAE3_IS_TX_RING(ring)) { 5125 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_L_REG, (u32)dma); 5126 hns3_write_dev(q, HNS3_RING_RX_RING_BASEADDR_H_REG, 5127 (u32)((dma >> 31) >> 1)); 5128 5129 hns3_write_dev(q, HNS3_RING_RX_RING_BD_LEN_REG, 5130 hns3_buf_size2type(ring->buf_size)); 5131 hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG, 5132 ring->desc_num / 8 - 1); 5133 } else { 5134 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG, 5135 (u32)dma); 5136 hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_H_REG, 5137 (u32)((dma >> 31) >> 1)); 5138 5139 hns3_write_dev(q, HNS3_RING_TX_RING_BD_NUM_REG, 5140 ring->desc_num / 8 - 1); 5141 } 5142 } 5143 5144 static void hns3_init_tx_ring_tc(struct hns3_nic_priv *priv) 5145 { 5146 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5147 struct hnae3_tc_info *tc_info = &kinfo->tc_info; 5148 int i; 5149 5150 for (i = 0; i < tc_info->num_tc; i++) { 5151 int j; 5152 5153 for (j = 0; j < tc_info->tqp_count[i]; j++) { 5154 struct hnae3_queue *q; 5155 5156 q = priv->ring[tc_info->tqp_offset[i] + j].tqp; 5157 hns3_write_dev(q, HNS3_RING_TX_RING_TC_REG, i); 5158 } 5159 } 5160 } 5161 5162 int hns3_init_all_ring(struct hns3_nic_priv *priv) 5163 { 5164 struct hnae3_handle *h = priv->ae_handle; 5165 int ring_num = h->kinfo.num_tqps * 2; 5166 int i, j; 5167 int ret; 5168 5169 hns3_update_tx_spare_buf_config(priv); 5170 for (i = 0; i < ring_num; i++) { 5171 ret = hns3_alloc_ring_memory(&priv->ring[i]); 5172 if (ret) { 5173 dev_err(priv->dev, 5174 "Alloc ring memory fail! ret=%d\n", ret); 5175 goto out_when_alloc_ring_memory; 5176 } 5177 5178 u64_stats_init(&priv->ring[i].syncp); 5179 cond_resched(); 5180 } 5181 5182 return 0; 5183 5184 out_when_alloc_ring_memory: 5185 for (j = i - 1; j >= 0; j--) 5186 hns3_fini_ring(&priv->ring[j]); 5187 5188 return -ENOMEM; 5189 } 5190 5191 static void hns3_uninit_all_ring(struct hns3_nic_priv *priv) 5192 { 5193 struct hnae3_handle *h = priv->ae_handle; 5194 int i; 5195 5196 for (i = 0; i < h->kinfo.num_tqps; i++) { 5197 hns3_fini_ring(&priv->ring[i]); 5198 hns3_fini_ring(&priv->ring[i + h->kinfo.num_tqps]); 5199 } 5200 } 5201 5202 /* Set mac addr if it is configured. or leave it to the AE driver */ 5203 static int hns3_init_mac_addr(struct net_device *netdev) 5204 { 5205 struct hns3_nic_priv *priv = netdev_priv(netdev); 5206 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 5207 struct hnae3_handle *h = priv->ae_handle; 5208 u8 mac_addr_temp[ETH_ALEN] = {0}; 5209 int ret = 0; 5210 5211 if (h->ae_algo->ops->get_mac_addr) 5212 h->ae_algo->ops->get_mac_addr(h, mac_addr_temp); 5213 5214 /* Check if the MAC address is valid, if not get a random one */ 5215 if (!is_valid_ether_addr(mac_addr_temp)) { 5216 eth_hw_addr_random(netdev); 5217 hnae3_format_mac_addr(format_mac_addr, netdev->dev_addr); 5218 dev_warn(priv->dev, "using random MAC address %s\n", 5219 format_mac_addr); 5220 } else if (!ether_addr_equal(netdev->dev_addr, mac_addr_temp)) { 5221 eth_hw_addr_set(netdev, mac_addr_temp); 5222 ether_addr_copy(netdev->perm_addr, mac_addr_temp); 5223 } else { 5224 return 0; 5225 } 5226 5227 if (h->ae_algo->ops->set_mac_addr) 5228 ret = h->ae_algo->ops->set_mac_addr(h, netdev->dev_addr, true); 5229 5230 return ret; 5231 } 5232 5233 static int hns3_init_phy(struct net_device *netdev) 5234 { 5235 struct hnae3_handle *h = hns3_get_handle(netdev); 5236 int ret = 0; 5237 5238 if (h->ae_algo->ops->mac_connect_phy) 5239 ret = h->ae_algo->ops->mac_connect_phy(h); 5240 5241 return ret; 5242 } 5243 5244 static void hns3_uninit_phy(struct net_device *netdev) 5245 { 5246 struct hnae3_handle *h = hns3_get_handle(netdev); 5247 5248 if (h->ae_algo->ops->mac_disconnect_phy) 5249 h->ae_algo->ops->mac_disconnect_phy(h); 5250 } 5251 5252 static int hns3_client_start(struct hnae3_handle *handle) 5253 { 5254 if (!handle->ae_algo->ops->client_start) 5255 return 0; 5256 5257 return handle->ae_algo->ops->client_start(handle); 5258 } 5259 5260 static void hns3_client_stop(struct hnae3_handle *handle) 5261 { 5262 if (!handle->ae_algo->ops->client_stop) 5263 return; 5264 5265 handle->ae_algo->ops->client_stop(handle); 5266 } 5267 5268 static void hns3_info_show(struct hns3_nic_priv *priv) 5269 { 5270 struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; 5271 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 5272 5273 hnae3_format_mac_addr(format_mac_addr, priv->netdev->dev_addr); 5274 dev_info(priv->dev, "MAC address: %s\n", format_mac_addr); 5275 dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps); 5276 dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size); 5277 dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size); 5278 dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len); 5279 dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc); 5280 dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc); 5281 dev_info(priv->dev, "Total number of enabled TCs: %u\n", 5282 kinfo->tc_info.num_tc); 5283 dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu); 5284 } 5285 5286 static void hns3_set_cq_period_mode(struct hns3_nic_priv *priv, 5287 enum dim_cq_period_mode mode, bool is_tx) 5288 { 5289 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(priv->ae_handle); 5290 struct hnae3_handle *handle = priv->ae_handle; 5291 int i; 5292 5293 if (is_tx) { 5294 priv->tx_cqe_mode = mode; 5295 5296 for (i = 0; i < priv->vector_num; i++) 5297 priv->tqp_vector[i].tx_group.dim.mode = mode; 5298 } else { 5299 priv->rx_cqe_mode = mode; 5300 5301 for (i = 0; i < priv->vector_num; i++) 5302 priv->tqp_vector[i].rx_group.dim.mode = mode; 5303 } 5304 5305 if (hnae3_ae_dev_cq_supported(ae_dev)) { 5306 u32 new_mode; 5307 u64 reg; 5308 5309 new_mode = (mode == DIM_CQ_PERIOD_MODE_START_FROM_CQE) ? 5310 HNS3_CQ_MODE_CQE : HNS3_CQ_MODE_EQE; 5311 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG; 5312 5313 writel(new_mode, handle->kinfo.io_base + reg); 5314 } 5315 } 5316 5317 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv, 5318 enum dim_cq_period_mode tx_mode, 5319 enum dim_cq_period_mode rx_mode) 5320 { 5321 hns3_set_cq_period_mode(priv, tx_mode, true); 5322 hns3_set_cq_period_mode(priv, rx_mode, false); 5323 } 5324 5325 static void hns3_state_init(struct hnae3_handle *handle) 5326 { 5327 struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle); 5328 struct net_device *netdev = handle->kinfo.netdev; 5329 struct hns3_nic_priv *priv = netdev_priv(netdev); 5330 5331 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5332 5333 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 5334 set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state); 5335 5336 if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) 5337 set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags); 5338 5339 if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) 5340 set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state); 5341 5342 if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev)) 5343 set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state); 5344 } 5345 5346 static void hns3_state_uninit(struct hnae3_handle *handle) 5347 { 5348 struct hns3_nic_priv *priv = handle->priv; 5349 5350 clear_bit(HNS3_NIC_STATE_INITED, &priv->state); 5351 } 5352 5353 static int hns3_client_init(struct hnae3_handle *handle) 5354 { 5355 struct pci_dev *pdev = handle->pdev; 5356 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 5357 u16 alloc_tqps, max_rss_size; 5358 struct hns3_nic_priv *priv; 5359 struct net_device *netdev; 5360 int ret; 5361 5362 ae_dev->handle = handle; 5363 5364 handle->ae_algo->ops->get_tqps_and_rss_info(handle, &alloc_tqps, 5365 &max_rss_size); 5366 netdev = alloc_etherdev_mq(sizeof(struct hns3_nic_priv), alloc_tqps); 5367 if (!netdev) 5368 return -ENOMEM; 5369 5370 priv = netdev_priv(netdev); 5371 priv->dev = &pdev->dev; 5372 priv->netdev = netdev; 5373 priv->ae_handle = handle; 5374 priv->tx_timeout_count = 0; 5375 priv->max_non_tso_bd_num = ae_dev->dev_specs.max_non_tso_bd_num; 5376 priv->min_tx_copybreak = 0; 5377 priv->min_tx_spare_buf_size = 0; 5378 set_bit(HNS3_NIC_STATE_DOWN, &priv->state); 5379 5380 handle->msg_enable = netif_msg_init(debug, DEFAULT_MSG_LEVEL); 5381 5382 handle->kinfo.netdev = netdev; 5383 handle->priv = (void *)priv; 5384 5385 hns3_init_mac_addr(netdev); 5386 5387 hns3_set_default_feature(netdev); 5388 5389 netdev->watchdog_timeo = HNS3_TX_TIMEOUT; 5390 netdev->priv_flags |= IFF_UNICAST_FLT; 5391 netdev->netdev_ops = &hns3_nic_netdev_ops; 5392 SET_NETDEV_DEV(netdev, &pdev->dev); 5393 hns3_ethtool_set_ops(netdev); 5394 5395 /* Carrier off reporting is important to ethtool even BEFORE open */ 5396 netif_carrier_off(netdev); 5397 5398 ret = hns3_get_ring_config(priv); 5399 if (ret) { 5400 ret = -ENOMEM; 5401 goto out_get_ring_cfg; 5402 } 5403 5404 hns3_nic_init_coal_cfg(priv); 5405 5406 ret = hns3_nic_alloc_vector_data(priv); 5407 if (ret) { 5408 ret = -ENOMEM; 5409 goto out_alloc_vector_data; 5410 } 5411 5412 ret = hns3_nic_init_vector_data(priv); 5413 if (ret) { 5414 ret = -ENOMEM; 5415 goto out_init_vector_data; 5416 } 5417 5418 ret = hns3_init_all_ring(priv); 5419 if (ret) { 5420 ret = -ENOMEM; 5421 goto out_init_ring; 5422 } 5423 5424 hns3_cq_period_mode_init(priv, DIM_CQ_PERIOD_MODE_START_FROM_EQE, 5425 DIM_CQ_PERIOD_MODE_START_FROM_EQE); 5426 5427 ret = hns3_init_phy(netdev); 5428 if (ret) 5429 goto out_init_phy; 5430 5431 /* the device can work without cpu rmap, only aRFS needs it */ 5432 ret = hns3_set_rx_cpu_rmap(netdev); 5433 if (ret) 5434 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5435 5436 ret = hns3_nic_init_irq(priv); 5437 if (ret) { 5438 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5439 hns3_free_rx_cpu_rmap(netdev); 5440 goto out_init_irq_fail; 5441 } 5442 5443 ret = hns3_client_start(handle); 5444 if (ret) { 5445 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5446 goto out_client_start; 5447 } 5448 5449 hns3_dcbnl_setup(handle); 5450 5451 ret = hns3_dbg_init(handle); 5452 if (ret) { 5453 dev_err(priv->dev, "failed to init debugfs, ret = %d\n", 5454 ret); 5455 goto out_client_start; 5456 } 5457 5458 netdev->max_mtu = HNS3_MAX_MTU(ae_dev->dev_specs.max_frm_size); 5459 5460 hns3_state_init(handle); 5461 5462 ret = register_netdev(netdev); 5463 if (ret) { 5464 dev_err(priv->dev, "probe register netdev fail!\n"); 5465 goto out_reg_netdev_fail; 5466 } 5467 5468 if (netif_msg_drv(handle)) 5469 hns3_info_show(priv); 5470 5471 return ret; 5472 5473 out_reg_netdev_fail: 5474 hns3_state_uninit(handle); 5475 hns3_dbg_uninit(handle); 5476 hns3_client_stop(handle); 5477 out_client_start: 5478 hns3_free_rx_cpu_rmap(netdev); 5479 hns3_nic_uninit_irq(priv); 5480 out_init_irq_fail: 5481 hns3_uninit_phy(netdev); 5482 out_init_phy: 5483 hns3_uninit_all_ring(priv); 5484 out_init_ring: 5485 hns3_nic_uninit_vector_data(priv); 5486 out_init_vector_data: 5487 hns3_nic_dealloc_vector_data(priv); 5488 out_alloc_vector_data: 5489 priv->ring = NULL; 5490 out_get_ring_cfg: 5491 priv->ae_handle = NULL; 5492 free_netdev(netdev); 5493 return ret; 5494 } 5495 5496 static void hns3_client_uninit(struct hnae3_handle *handle, bool reset) 5497 { 5498 struct net_device *netdev = handle->kinfo.netdev; 5499 struct hns3_nic_priv *priv = netdev_priv(netdev); 5500 5501 if (netdev->reg_state != NETREG_UNINITIALIZED) 5502 unregister_netdev(netdev); 5503 5504 hns3_client_stop(handle); 5505 5506 hns3_uninit_phy(netdev); 5507 5508 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5509 netdev_warn(netdev, "already uninitialized\n"); 5510 goto out_netdev_free; 5511 } 5512 5513 hns3_free_rx_cpu_rmap(netdev); 5514 5515 hns3_nic_uninit_irq(priv); 5516 5517 hns3_clear_all_ring(handle, true); 5518 5519 hns3_nic_uninit_vector_data(priv); 5520 5521 hns3_nic_dealloc_vector_data(priv); 5522 5523 hns3_uninit_all_ring(priv); 5524 5525 hns3_put_ring_config(priv); 5526 5527 out_netdev_free: 5528 hns3_dbg_uninit(handle); 5529 free_netdev(netdev); 5530 } 5531 5532 static void hns3_link_status_change(struct hnae3_handle *handle, bool linkup) 5533 { 5534 struct net_device *netdev = handle->kinfo.netdev; 5535 5536 if (!netdev) 5537 return; 5538 5539 if (linkup) { 5540 netif_tx_wake_all_queues(netdev); 5541 netif_carrier_on(netdev); 5542 if (netif_msg_link(handle)) 5543 netdev_info(netdev, "link up\n"); 5544 } else { 5545 netif_carrier_off(netdev); 5546 netif_tx_stop_all_queues(netdev); 5547 if (netif_msg_link(handle)) 5548 netdev_info(netdev, "link down\n"); 5549 } 5550 } 5551 5552 static void hns3_clear_tx_ring(struct hns3_enet_ring *ring) 5553 { 5554 while (ring->next_to_clean != ring->next_to_use) { 5555 ring->desc[ring->next_to_clean].tx.bdtp_fe_sc_vld_ra_ri = 0; 5556 hns3_free_buffer_detach(ring, ring->next_to_clean, 0); 5557 ring_ptr_move_fw(ring, next_to_clean); 5558 } 5559 5560 ring->pending_buf = 0; 5561 } 5562 5563 static int hns3_clear_rx_ring(struct hns3_enet_ring *ring) 5564 { 5565 struct hns3_desc_cb res_cbs; 5566 int ret; 5567 5568 while (ring->next_to_use != ring->next_to_clean) { 5569 /* When a buffer is not reused, it's memory has been 5570 * freed in hns3_handle_rx_bd or will be freed by 5571 * stack, so we need to replace the buffer here. 5572 */ 5573 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5574 ret = hns3_alloc_and_map_buffer(ring, &res_cbs); 5575 if (ret) { 5576 hns3_ring_stats_update(ring, sw_err_cnt); 5577 /* if alloc new buffer fail, exit directly 5578 * and reclear in up flow. 5579 */ 5580 netdev_warn(ring_to_netdev(ring), 5581 "reserve buffer map failed, ret = %d\n", 5582 ret); 5583 return ret; 5584 } 5585 hns3_replace_buffer(ring, ring->next_to_use, &res_cbs); 5586 } 5587 ring_ptr_move_fw(ring, next_to_use); 5588 } 5589 5590 /* Free the pending skb in rx ring */ 5591 if (ring->skb) { 5592 dev_kfree_skb_any(ring->skb); 5593 ring->skb = NULL; 5594 ring->pending_buf = 0; 5595 } 5596 5597 return 0; 5598 } 5599 5600 static void hns3_force_clear_rx_ring(struct hns3_enet_ring *ring) 5601 { 5602 while (ring->next_to_use != ring->next_to_clean) { 5603 /* When a buffer is not reused, it's memory has been 5604 * freed in hns3_handle_rx_bd or will be freed by 5605 * stack, so only need to unmap the buffer here. 5606 */ 5607 if (!ring->desc_cb[ring->next_to_use].reuse_flag) { 5608 hns3_unmap_buffer(ring, 5609 &ring->desc_cb[ring->next_to_use]); 5610 ring->desc_cb[ring->next_to_use].dma = 0; 5611 } 5612 5613 ring_ptr_move_fw(ring, next_to_use); 5614 } 5615 } 5616 5617 static void hns3_clear_all_ring(struct hnae3_handle *h, bool force) 5618 { 5619 struct net_device *ndev = h->kinfo.netdev; 5620 struct hns3_nic_priv *priv = netdev_priv(ndev); 5621 u32 i; 5622 5623 for (i = 0; i < h->kinfo.num_tqps; i++) { 5624 struct hns3_enet_ring *ring; 5625 5626 ring = &priv->ring[i]; 5627 hns3_clear_tx_ring(ring); 5628 5629 ring = &priv->ring[i + h->kinfo.num_tqps]; 5630 /* Continue to clear other rings even if clearing some 5631 * rings failed. 5632 */ 5633 if (force) 5634 hns3_force_clear_rx_ring(ring); 5635 else 5636 hns3_clear_rx_ring(ring); 5637 } 5638 } 5639 5640 int hns3_nic_reset_all_ring(struct hnae3_handle *h) 5641 { 5642 struct net_device *ndev = h->kinfo.netdev; 5643 struct hns3_nic_priv *priv = netdev_priv(ndev); 5644 struct hns3_enet_ring *rx_ring; 5645 int i, j; 5646 int ret; 5647 5648 ret = h->ae_algo->ops->reset_queue(h); 5649 if (ret) 5650 return ret; 5651 5652 for (i = 0; i < h->kinfo.num_tqps; i++) { 5653 hns3_init_ring_hw(&priv->ring[i]); 5654 5655 /* We need to clear tx ring here because self test will 5656 * use the ring and will not run down before up 5657 */ 5658 hns3_clear_tx_ring(&priv->ring[i]); 5659 priv->ring[i].next_to_clean = 0; 5660 priv->ring[i].next_to_use = 0; 5661 priv->ring[i].last_to_use = 0; 5662 5663 rx_ring = &priv->ring[i + h->kinfo.num_tqps]; 5664 hns3_init_ring_hw(rx_ring); 5665 ret = hns3_clear_rx_ring(rx_ring); 5666 if (ret) 5667 return ret; 5668 5669 /* We can not know the hardware head and tail when this 5670 * function is called in reset flow, so we reuse all desc. 5671 */ 5672 for (j = 0; j < rx_ring->desc_num; j++) 5673 hns3_reuse_buffer(rx_ring, j); 5674 5675 rx_ring->next_to_clean = 0; 5676 rx_ring->next_to_use = 0; 5677 } 5678 5679 hns3_init_tx_ring_tc(priv); 5680 5681 return 0; 5682 } 5683 5684 static int hns3_reset_notify_down_enet(struct hnae3_handle *handle) 5685 { 5686 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5687 struct net_device *ndev = kinfo->netdev; 5688 struct hns3_nic_priv *priv = netdev_priv(ndev); 5689 5690 if (test_and_set_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) 5691 return 0; 5692 5693 if (!netif_running(ndev)) 5694 return 0; 5695 5696 return hns3_nic_net_stop(ndev); 5697 } 5698 5699 static int hns3_reset_notify_up_enet(struct hnae3_handle *handle) 5700 { 5701 struct hnae3_knic_private_info *kinfo = &handle->kinfo; 5702 struct hns3_nic_priv *priv = netdev_priv(kinfo->netdev); 5703 int ret = 0; 5704 5705 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5706 netdev_err(kinfo->netdev, "device is not initialized yet\n"); 5707 return -EFAULT; 5708 } 5709 5710 clear_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5711 5712 if (netif_running(kinfo->netdev)) { 5713 ret = hns3_nic_net_open(kinfo->netdev); 5714 if (ret) { 5715 set_bit(HNS3_NIC_STATE_RESETTING, &priv->state); 5716 netdev_err(kinfo->netdev, 5717 "net up fail, ret=%d!\n", ret); 5718 return ret; 5719 } 5720 } 5721 5722 return ret; 5723 } 5724 5725 static int hns3_reset_notify_init_enet(struct hnae3_handle *handle) 5726 { 5727 struct net_device *netdev = handle->kinfo.netdev; 5728 struct hns3_nic_priv *priv = netdev_priv(netdev); 5729 int ret; 5730 5731 /* Carrier off reporting is important to ethtool even BEFORE open */ 5732 netif_carrier_off(netdev); 5733 5734 ret = hns3_get_ring_config(priv); 5735 if (ret) 5736 return ret; 5737 5738 ret = hns3_nic_alloc_vector_data(priv); 5739 if (ret) 5740 goto err_put_ring; 5741 5742 ret = hns3_nic_init_vector_data(priv); 5743 if (ret) 5744 goto err_dealloc_vector; 5745 5746 ret = hns3_init_all_ring(priv); 5747 if (ret) 5748 goto err_uninit_vector; 5749 5750 hns3_cq_period_mode_init(priv, priv->tx_cqe_mode, priv->rx_cqe_mode); 5751 5752 /* the device can work without cpu rmap, only aRFS needs it */ 5753 ret = hns3_set_rx_cpu_rmap(netdev); 5754 if (ret) 5755 dev_warn(priv->dev, "set rx cpu rmap fail, ret=%d\n", ret); 5756 5757 ret = hns3_nic_init_irq(priv); 5758 if (ret) { 5759 dev_err(priv->dev, "init irq failed! ret=%d\n", ret); 5760 hns3_free_rx_cpu_rmap(netdev); 5761 goto err_init_irq_fail; 5762 } 5763 5764 if (!hns3_is_phys_func(handle->pdev)) 5765 hns3_init_mac_addr(netdev); 5766 5767 ret = hns3_client_start(handle); 5768 if (ret) { 5769 dev_err(priv->dev, "hns3_client_start fail! ret=%d\n", ret); 5770 goto err_client_start_fail; 5771 } 5772 5773 set_bit(HNS3_NIC_STATE_INITED, &priv->state); 5774 5775 return ret; 5776 5777 err_client_start_fail: 5778 hns3_free_rx_cpu_rmap(netdev); 5779 hns3_nic_uninit_irq(priv); 5780 err_init_irq_fail: 5781 hns3_uninit_all_ring(priv); 5782 err_uninit_vector: 5783 hns3_nic_uninit_vector_data(priv); 5784 err_dealloc_vector: 5785 hns3_nic_dealloc_vector_data(priv); 5786 err_put_ring: 5787 hns3_put_ring_config(priv); 5788 5789 return ret; 5790 } 5791 5792 static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle) 5793 { 5794 struct net_device *netdev = handle->kinfo.netdev; 5795 struct hns3_nic_priv *priv = netdev_priv(netdev); 5796 5797 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 5798 hns3_nic_net_stop(netdev); 5799 5800 if (!test_and_clear_bit(HNS3_NIC_STATE_INITED, &priv->state)) { 5801 netdev_warn(netdev, "already uninitialized\n"); 5802 return 0; 5803 } 5804 5805 hns3_free_rx_cpu_rmap(netdev); 5806 hns3_nic_uninit_irq(priv); 5807 hns3_clear_all_ring(handle, true); 5808 hns3_reset_tx_queue(priv->ae_handle); 5809 5810 hns3_nic_uninit_vector_data(priv); 5811 5812 hns3_nic_dealloc_vector_data(priv); 5813 5814 hns3_uninit_all_ring(priv); 5815 5816 hns3_put_ring_config(priv); 5817 5818 return 0; 5819 } 5820 5821 int hns3_reset_notify(struct hnae3_handle *handle, 5822 enum hnae3_reset_notify_type type) 5823 { 5824 int ret = 0; 5825 5826 switch (type) { 5827 case HNAE3_UP_CLIENT: 5828 ret = hns3_reset_notify_up_enet(handle); 5829 break; 5830 case HNAE3_DOWN_CLIENT: 5831 ret = hns3_reset_notify_down_enet(handle); 5832 break; 5833 case HNAE3_INIT_CLIENT: 5834 ret = hns3_reset_notify_init_enet(handle); 5835 break; 5836 case HNAE3_UNINIT_CLIENT: 5837 ret = hns3_reset_notify_uninit_enet(handle); 5838 break; 5839 default: 5840 break; 5841 } 5842 5843 return ret; 5844 } 5845 5846 static int hns3_change_channels(struct hnae3_handle *handle, u32 new_tqp_num, 5847 bool rxfh_configured) 5848 { 5849 int ret; 5850 5851 ret = handle->ae_algo->ops->set_channels(handle, new_tqp_num, 5852 rxfh_configured); 5853 if (ret) { 5854 dev_err(&handle->pdev->dev, 5855 "Change tqp num(%u) fail.\n", new_tqp_num); 5856 return ret; 5857 } 5858 5859 ret = hns3_reset_notify(handle, HNAE3_INIT_CLIENT); 5860 if (ret) 5861 return ret; 5862 5863 ret = hns3_reset_notify(handle, HNAE3_UP_CLIENT); 5864 if (ret) 5865 hns3_reset_notify(handle, HNAE3_UNINIT_CLIENT); 5866 5867 return ret; 5868 } 5869 5870 int hns3_set_channels(struct net_device *netdev, 5871 struct ethtool_channels *ch) 5872 { 5873 struct hnae3_handle *h = hns3_get_handle(netdev); 5874 struct hnae3_knic_private_info *kinfo = &h->kinfo; 5875 bool rxfh_configured = netif_is_rxfh_configured(netdev); 5876 u32 new_tqp_num = ch->combined_count; 5877 u16 org_tqp_num; 5878 int ret; 5879 5880 if (hns3_nic_resetting(netdev)) 5881 return -EBUSY; 5882 5883 if (ch->rx_count || ch->tx_count) 5884 return -EINVAL; 5885 5886 if (kinfo->tc_info.mqprio_active) { 5887 dev_err(&netdev->dev, 5888 "it's not allowed to set channels via ethtool when MQPRIO mode is on\n"); 5889 return -EINVAL; 5890 } 5891 5892 if (new_tqp_num > hns3_get_max_available_channels(h) || 5893 new_tqp_num < 1) { 5894 dev_err(&netdev->dev, 5895 "Change tqps fail, the tqp range is from 1 to %u", 5896 hns3_get_max_available_channels(h)); 5897 return -EINVAL; 5898 } 5899 5900 if (kinfo->rss_size == new_tqp_num) 5901 return 0; 5902 5903 netif_dbg(h, drv, netdev, 5904 "set channels: tqp_num=%u, rxfh=%d\n", 5905 new_tqp_num, rxfh_configured); 5906 5907 ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT); 5908 if (ret) 5909 return ret; 5910 5911 ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT); 5912 if (ret) 5913 return ret; 5914 5915 org_tqp_num = h->kinfo.num_tqps; 5916 ret = hns3_change_channels(h, new_tqp_num, rxfh_configured); 5917 if (ret) { 5918 int ret1; 5919 5920 netdev_warn(netdev, 5921 "Change channels fail, revert to old value\n"); 5922 ret1 = hns3_change_channels(h, org_tqp_num, rxfh_configured); 5923 if (ret1) { 5924 netdev_err(netdev, 5925 "revert to old channel fail\n"); 5926 return ret1; 5927 } 5928 5929 return ret; 5930 } 5931 5932 return 0; 5933 } 5934 5935 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running) 5936 { 5937 struct hns3_nic_priv *priv = netdev_priv(ndev); 5938 5939 if (!if_running) 5940 return; 5941 5942 if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 5943 return; 5944 5945 netif_carrier_off(ndev); 5946 netif_tx_disable(ndev); 5947 5948 hns3_disable_irqs_and_tqps(ndev); 5949 5950 /* delay ring buffer clearing to hns3_reset_notify_uninit_enet 5951 * during reset process, because driver may not be able 5952 * to disable the ring through firmware when downing the netdev. 5953 */ 5954 if (!hns3_nic_resetting(ndev)) 5955 hns3_nic_reset_all_ring(priv->ae_handle); 5956 5957 hns3_reset_tx_queue(priv->ae_handle); 5958 } 5959 5960 void hns3_external_lb_restore(struct net_device *ndev, bool if_running) 5961 { 5962 struct hns3_nic_priv *priv = netdev_priv(ndev); 5963 struct hnae3_handle *h = priv->ae_handle; 5964 5965 if (!if_running) 5966 return; 5967 5968 if (hns3_nic_resetting(ndev)) 5969 return; 5970 5971 if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) 5972 return; 5973 5974 if (hns3_nic_reset_all_ring(priv->ae_handle)) 5975 return; 5976 5977 clear_bit(HNS3_NIC_STATE_DOWN, &priv->state); 5978 5979 hns3_enable_irqs_and_tqps(ndev); 5980 5981 netif_tx_wake_all_queues(ndev); 5982 5983 if (h->ae_algo->ops->get_status(h)) 5984 netif_carrier_on(ndev); 5985 } 5986 5987 static const struct hns3_hw_error_info hns3_hw_err[] = { 5988 { .type = HNAE3_PPU_POISON_ERROR, 5989 .msg = "PPU poison" }, 5990 { .type = HNAE3_CMDQ_ECC_ERROR, 5991 .msg = "IMP CMDQ error" }, 5992 { .type = HNAE3_IMP_RD_POISON_ERROR, 5993 .msg = "IMP RD poison" }, 5994 { .type = HNAE3_ROCEE_AXI_RESP_ERROR, 5995 .msg = "ROCEE AXI RESP error" }, 5996 }; 5997 5998 static void hns3_process_hw_error(struct hnae3_handle *handle, 5999 enum hnae3_hw_error_type type) 6000 { 6001 u32 i; 6002 6003 for (i = 0; i < ARRAY_SIZE(hns3_hw_err); i++) { 6004 if (hns3_hw_err[i].type == type) { 6005 dev_err(&handle->pdev->dev, "Detected %s!\n", 6006 hns3_hw_err[i].msg); 6007 break; 6008 } 6009 } 6010 } 6011 6012 static const struct hnae3_client_ops client_ops = { 6013 .init_instance = hns3_client_init, 6014 .uninit_instance = hns3_client_uninit, 6015 .link_status_change = hns3_link_status_change, 6016 .reset_notify = hns3_reset_notify, 6017 .process_hw_error = hns3_process_hw_error, 6018 }; 6019 6020 /* hns3_init_module - Driver registration routine 6021 * hns3_init_module is the first routine called when the driver is 6022 * loaded. All it does is register with the PCI subsystem. 6023 */ 6024 static int __init hns3_init_module(void) 6025 { 6026 int ret; 6027 6028 pr_debug("%s: %s - version\n", hns3_driver_name, hns3_driver_string); 6029 pr_debug("%s: %s\n", hns3_driver_name, hns3_copyright); 6030 6031 client.type = HNAE3_CLIENT_KNIC; 6032 snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", 6033 hns3_driver_name); 6034 6035 client.ops = &client_ops; 6036 6037 INIT_LIST_HEAD(&client.node); 6038 6039 hns3_dbg_register_debugfs(hns3_driver_name); 6040 6041 ret = hnae3_register_client(&client); 6042 if (ret) 6043 goto err_reg_client; 6044 6045 ret = pci_register_driver(&hns3_driver); 6046 if (ret) 6047 goto err_reg_driver; 6048 6049 return ret; 6050 6051 err_reg_driver: 6052 hnae3_unregister_client(&client); 6053 err_reg_client: 6054 hns3_dbg_unregister_debugfs(); 6055 return ret; 6056 } 6057 module_init(hns3_init_module); 6058 6059 /* hns3_exit_module - Driver exit cleanup routine 6060 * hns3_exit_module is called just before the driver is removed 6061 * from memory. 6062 */ 6063 static void __exit hns3_exit_module(void) 6064 { 6065 hnae3_acquire_unload_lock(); 6066 pci_unregister_driver(&hns3_driver); 6067 hnae3_unregister_client(&client); 6068 hns3_dbg_unregister_debugfs(); 6069 hnae3_release_unload_lock(); 6070 } 6071 module_exit(hns3_exit_module); 6072 6073 MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver"); 6074 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 6075 MODULE_LICENSE("GPL"); 6076 MODULE_ALIAS("pci:hns-nic"); 6077