1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IOMMU API for Rockchip 4 * 5 * Module Authors: Simon Xue <xxm@rock-chips.com> 6 * Daniel Kurtz <djkurtz@chromium.org> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/compiler.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/errno.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iommu.h> 18 #include <linux/iopoll.h> 19 #include <linux/list.h> 20 #include <linux/mm.h> 21 #include <linux/init.h> 22 #include <linux/of.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 #include <linux/string_choices.h> 29 30 #include "iommu-pages.h" 31 32 /** MMU register offsets */ 33 #define RK_MMU_DTE_ADDR 0x00 /* Directory table address */ 34 #define RK_MMU_STATUS 0x04 35 #define RK_MMU_COMMAND 0x08 36 #define RK_MMU_PAGE_FAULT_ADDR 0x0C /* IOVA of last page fault */ 37 #define RK_MMU_ZAP_ONE_LINE 0x10 /* Shootdown one IOTLB entry */ 38 #define RK_MMU_INT_RAWSTAT 0x14 /* IRQ status ignoring mask */ 39 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */ 40 #define RK_MMU_INT_MASK 0x1C /* IRQ enable */ 41 #define RK_MMU_INT_STATUS 0x20 /* IRQ status after masking */ 42 #define RK_MMU_AUTO_GATING 0x24 43 44 #define DTE_ADDR_DUMMY 0xCAFEBABE 45 46 #define RK_MMU_POLL_PERIOD_US 100 47 #define RK_MMU_FORCE_RESET_TIMEOUT_US 100000 48 #define RK_MMU_POLL_TIMEOUT_US 1000 49 50 /* RK_MMU_STATUS fields */ 51 #define RK_MMU_STATUS_PAGING_ENABLED BIT(0) 52 #define RK_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) 53 #define RK_MMU_STATUS_STALL_ACTIVE BIT(2) 54 #define RK_MMU_STATUS_IDLE BIT(3) 55 #define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) 56 #define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) 57 #define RK_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) 58 59 /* RK_MMU_COMMAND command values */ 60 #define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */ 61 #define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */ 62 #define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */ 63 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */ 64 #define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */ 65 #define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */ 66 #define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */ 67 68 /* RK_MMU_INT_* register fields */ 69 #define RK_MMU_IRQ_PAGE_FAULT 0x01 /* page fault */ 70 #define RK_MMU_IRQ_BUS_ERROR 0x02 /* bus read error */ 71 #define RK_MMU_IRQ_MASK (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR) 72 73 #define NUM_DT_ENTRIES 1024 74 #define NUM_PT_ENTRIES 1024 75 76 #define SPAGE_ORDER 12 77 #define SPAGE_SIZE (1 << SPAGE_ORDER) 78 79 #define DISABLE_FETCH_DTE_TIME_LIMIT BIT(31) 80 81 /* 82 * Support mapping any size that fits in one page table: 83 * 4 KiB to 4 MiB 84 */ 85 #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000 86 87 struct rk_iommu_domain { 88 struct list_head iommus; 89 u32 *dt; /* page directory table */ 90 dma_addr_t dt_dma; 91 spinlock_t iommus_lock; /* lock for iommus list */ 92 spinlock_t dt_lock; /* lock for modifying page directory table */ 93 struct device *dma_dev; 94 95 struct iommu_domain domain; 96 }; 97 98 /* list of clocks required by IOMMU */ 99 static const char * const rk_iommu_clocks[] = { 100 "aclk", "iface", 101 }; 102 103 struct rk_iommu_ops { 104 phys_addr_t (*pt_address)(u32 dte); 105 u32 (*mk_dtentries)(dma_addr_t pt_dma); 106 u32 (*mk_ptentries)(phys_addr_t page, int prot); 107 u64 dma_bit_mask; 108 gfp_t gfp_flags; 109 }; 110 111 struct rk_iommu { 112 struct device *dev; 113 void __iomem **bases; 114 int num_mmu; 115 int num_irq; 116 struct clk_bulk_data *clocks; 117 int num_clocks; 118 bool reset_disabled; 119 struct iommu_device iommu; 120 struct list_head node; /* entry in rk_iommu_domain.iommus */ 121 struct iommu_domain *domain; /* domain to which iommu is attached */ 122 }; 123 124 struct rk_iommudata { 125 struct device_link *link; /* runtime PM link from IOMMU to master */ 126 struct rk_iommu *iommu; 127 }; 128 129 static const struct rk_iommu_ops *rk_ops; 130 static struct iommu_domain rk_identity_domain; 131 132 static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma, 133 unsigned int count) 134 { 135 size_t size = count * sizeof(u32); /* count of u32 entry */ 136 137 dma_sync_single_for_device(dom->dma_dev, dma, size, DMA_TO_DEVICE); 138 } 139 140 static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom) 141 { 142 return container_of(dom, struct rk_iommu_domain, domain); 143 } 144 145 /* 146 * The Rockchip rk3288 iommu uses a 2-level page table. 147 * The first level is the "Directory Table" (DT). 148 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing 149 * to a "Page Table". 150 * The second level is the 1024 Page Tables (PT). 151 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to 152 * a 4 KB page of physical memory. 153 * 154 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries). 155 * Each iommu device has a MMU_DTE_ADDR register that contains the physical 156 * address of the start of the DT page. 157 * 158 * The structure of the page table is as follows: 159 * 160 * DT 161 * MMU_DTE_ADDR -> +-----+ 162 * | | 163 * +-----+ PT 164 * | DTE | -> +-----+ 165 * +-----+ | | Memory 166 * | | +-----+ Page 167 * | | | PTE | -> +-----+ 168 * +-----+ +-----+ | | 169 * | | | | 170 * | | | | 171 * +-----+ | | 172 * | | 173 * | | 174 * +-----+ 175 */ 176 177 /* 178 * Each DTE has a PT address and a valid bit: 179 * +---------------------+-----------+-+ 180 * | PT address | Reserved |V| 181 * +---------------------+-----------+-+ 182 * 31:12 - PT address (PTs always starts on a 4 KB boundary) 183 * 11: 1 - Reserved 184 * 0 - 1 if PT @ PT address is valid 185 */ 186 #define RK_DTE_PT_ADDRESS_MASK 0xfffff000 187 #define RK_DTE_PT_VALID BIT(0) 188 189 static inline phys_addr_t rk_dte_pt_address(u32 dte) 190 { 191 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; 192 } 193 194 /* 195 * In v2: 196 * 31:12 - PT address bit 31:0 197 * 11: 8 - PT address bit 35:32 198 * 7: 4 - PT address bit 39:36 199 * 3: 1 - Reserved 200 * 0 - 1 if PT @ PT address is valid 201 */ 202 #define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4) 203 #define DTE_HI_MASK1 GENMASK(11, 8) 204 #define DTE_HI_MASK2 GENMASK(7, 4) 205 #define DTE_HI_SHIFT1 24 /* shift bit 8 to bit 32 */ 206 #define DTE_HI_SHIFT2 32 /* shift bit 4 to bit 36 */ 207 #define PAGE_DESC_HI_MASK1 GENMASK_ULL(35, 32) 208 #define PAGE_DESC_HI_MASK2 GENMASK_ULL(39, 36) 209 210 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) 211 { 212 u64 dte_v2 = dte; 213 214 dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) | 215 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) | 216 (dte_v2 & RK_DTE_PT_ADDRESS_MASK); 217 218 return (phys_addr_t)dte_v2; 219 } 220 221 static inline bool rk_dte_is_pt_valid(u32 dte) 222 { 223 return dte & RK_DTE_PT_VALID; 224 } 225 226 static inline u32 rk_mk_dte(dma_addr_t pt_dma) 227 { 228 return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID; 229 } 230 231 static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma) 232 { 233 pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) | 234 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) | 235 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2; 236 237 return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID; 238 } 239 240 /* 241 * Each PTE has a Page address, some flags and a valid bit: 242 * +---------------------+---+-------+-+ 243 * | Page address |Rsv| Flags |V| 244 * +---------------------+---+-------+-+ 245 * 31:12 - Page address (Pages always start on a 4 KB boundary) 246 * 11: 9 - Reserved 247 * 8: 1 - Flags 248 * 8 - Read allocate - allocate cache space on read misses 249 * 7 - Read cache - enable cache & prefetch of data 250 * 6 - Write buffer - enable delaying writes on their way to memory 251 * 5 - Write allocate - allocate cache space on write misses 252 * 4 - Write cache - different writes can be merged together 253 * 3 - Override cache attributes 254 * if 1, bits 4-8 control cache attributes 255 * if 0, the system bus defaults are used 256 * 2 - Writable 257 * 1 - Readable 258 * 0 - 1 if Page @ Page address is valid 259 */ 260 #define RK_PTE_PAGE_ADDRESS_MASK 0xfffff000 261 #define RK_PTE_PAGE_FLAGS_MASK 0x000001fe 262 #define RK_PTE_PAGE_WRITABLE BIT(2) 263 #define RK_PTE_PAGE_READABLE BIT(1) 264 #define RK_PTE_PAGE_VALID BIT(0) 265 266 static inline bool rk_pte_is_page_valid(u32 pte) 267 { 268 return pte & RK_PTE_PAGE_VALID; 269 } 270 271 /* TODO: set cache flags per prot IOMMU_CACHE */ 272 static u32 rk_mk_pte(phys_addr_t page, int prot) 273 { 274 u32 flags = 0; 275 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 276 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 277 page &= RK_PTE_PAGE_ADDRESS_MASK; 278 return page | flags | RK_PTE_PAGE_VALID; 279 } 280 281 /* 282 * In v2: 283 * 31:12 - Page address bit 31:0 284 * 11: 8 - Page address bit 35:32 285 * 7: 4 - Page address bit 39:36 286 * 3 - Security 287 * 2 - Writable 288 * 1 - Readable 289 * 0 - 1 if Page @ Page address is valid 290 */ 291 292 static u32 rk_mk_pte_v2(phys_addr_t page, int prot) 293 { 294 u32 flags = 0; 295 296 flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0; 297 flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0; 298 299 return rk_mk_dte_v2(page) | flags; 300 } 301 302 static u32 rk_mk_pte_invalid(u32 pte) 303 { 304 return pte & ~RK_PTE_PAGE_VALID; 305 } 306 307 /* 308 * rk3288 iova (IOMMU Virtual Address) format 309 * 31 22.21 12.11 0 310 * +-----------+-----------+-------------+ 311 * | DTE index | PTE index | Page offset | 312 * +-----------+-----------+-------------+ 313 * 31:22 - DTE index - index of DTE in DT 314 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address 315 * 11: 0 - Page offset - offset into page @ PTE.page_address 316 */ 317 #define RK_IOVA_DTE_MASK 0xffc00000 318 #define RK_IOVA_DTE_SHIFT 22 319 #define RK_IOVA_PTE_MASK 0x003ff000 320 #define RK_IOVA_PTE_SHIFT 12 321 #define RK_IOVA_PAGE_MASK 0x00000fff 322 #define RK_IOVA_PAGE_SHIFT 0 323 324 static u32 rk_iova_dte_index(dma_addr_t iova) 325 { 326 return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT; 327 } 328 329 static u32 rk_iova_pte_index(dma_addr_t iova) 330 { 331 return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT; 332 } 333 334 static u32 rk_iova_page_offset(dma_addr_t iova) 335 { 336 return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT; 337 } 338 339 static u32 rk_iommu_read(void __iomem *base, u32 offset) 340 { 341 return readl(base + offset); 342 } 343 344 static void rk_iommu_write(void __iomem *base, u32 offset, u32 value) 345 { 346 writel(value, base + offset); 347 } 348 349 static void rk_iommu_command(struct rk_iommu *iommu, u32 command) 350 { 351 int i; 352 353 for (i = 0; i < iommu->num_mmu; i++) 354 writel(command, iommu->bases[i] + RK_MMU_COMMAND); 355 } 356 357 static void rk_iommu_base_command(void __iomem *base, u32 command) 358 { 359 writel(command, base + RK_MMU_COMMAND); 360 } 361 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start, 362 size_t size) 363 { 364 int i; 365 dma_addr_t iova_end = iova_start + size; 366 /* 367 * TODO(djkurtz): Figure out when it is more efficient to shootdown the 368 * entire iotlb rather than iterate over individual iovas. 369 */ 370 for (i = 0; i < iommu->num_mmu; i++) { 371 dma_addr_t iova; 372 373 for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE) 374 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); 375 } 376 } 377 378 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu) 379 { 380 bool active = true; 381 int i; 382 383 for (i = 0; i < iommu->num_mmu; i++) 384 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 385 RK_MMU_STATUS_STALL_ACTIVE); 386 387 return active; 388 } 389 390 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu) 391 { 392 bool enable = true; 393 int i; 394 395 for (i = 0; i < iommu->num_mmu; i++) 396 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & 397 RK_MMU_STATUS_PAGING_ENABLED); 398 399 return enable; 400 } 401 402 static bool rk_iommu_is_reset_done(struct rk_iommu *iommu) 403 { 404 bool done = true; 405 int i; 406 407 for (i = 0; i < iommu->num_mmu; i++) 408 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; 409 410 return done; 411 } 412 413 static int rk_iommu_enable_stall(struct rk_iommu *iommu) 414 { 415 int ret, i; 416 bool val; 417 418 if (rk_iommu_is_stall_active(iommu)) 419 return 0; 420 421 /* Stall can only be enabled if paging is enabled */ 422 if (!rk_iommu_is_paging_enabled(iommu)) 423 return 0; 424 425 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL); 426 427 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 428 val, RK_MMU_POLL_PERIOD_US, 429 RK_MMU_POLL_TIMEOUT_US); 430 if (ret) 431 for (i = 0; i < iommu->num_mmu; i++) 432 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n", 433 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 434 435 return ret; 436 } 437 438 static int rk_iommu_disable_stall(struct rk_iommu *iommu) 439 { 440 int ret, i; 441 bool val; 442 443 if (!rk_iommu_is_stall_active(iommu)) 444 return 0; 445 446 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL); 447 448 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, 449 !val, RK_MMU_POLL_PERIOD_US, 450 RK_MMU_POLL_TIMEOUT_US); 451 if (ret) 452 for (i = 0; i < iommu->num_mmu; i++) 453 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n", 454 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 455 456 return ret; 457 } 458 459 static int rk_iommu_enable_paging(struct rk_iommu *iommu) 460 { 461 int ret, i; 462 bool val; 463 464 if (rk_iommu_is_paging_enabled(iommu)) 465 return 0; 466 467 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING); 468 469 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 470 val, RK_MMU_POLL_PERIOD_US, 471 RK_MMU_POLL_TIMEOUT_US); 472 if (ret) 473 for (i = 0; i < iommu->num_mmu; i++) 474 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n", 475 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 476 477 return ret; 478 } 479 480 static int rk_iommu_disable_paging(struct rk_iommu *iommu) 481 { 482 int ret, i; 483 bool val; 484 485 if (!rk_iommu_is_paging_enabled(iommu)) 486 return 0; 487 488 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING); 489 490 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, 491 !val, RK_MMU_POLL_PERIOD_US, 492 RK_MMU_POLL_TIMEOUT_US); 493 if (ret) 494 for (i = 0; i < iommu->num_mmu; i++) 495 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n", 496 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); 497 498 return ret; 499 } 500 501 static int rk_iommu_force_reset(struct rk_iommu *iommu) 502 { 503 int ret, i; 504 u32 dte_addr; 505 bool val; 506 507 if (iommu->reset_disabled) 508 return 0; 509 510 /* 511 * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY 512 * and verifying that upper 5 (v1) or 7 (v2) nybbles are read back. 513 */ 514 for (i = 0; i < iommu->num_mmu; i++) { 515 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY); 516 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr); 517 518 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) { 519 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n"); 520 return -EFAULT; 521 } 522 } 523 524 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET); 525 526 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val, 527 val, RK_MMU_FORCE_RESET_TIMEOUT_US, 528 RK_MMU_POLL_TIMEOUT_US); 529 if (ret) { 530 dev_err(iommu->dev, "FORCE_RESET command timed out\n"); 531 return ret; 532 } 533 534 return 0; 535 } 536 537 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova) 538 { 539 void __iomem *base = iommu->bases[index]; 540 u32 dte_index, pte_index, page_offset; 541 u32 mmu_dte_addr; 542 phys_addr_t mmu_dte_addr_phys, dte_addr_phys; 543 u32 *dte_addr; 544 u32 dte; 545 phys_addr_t pte_addr_phys = 0; 546 u32 *pte_addr = NULL; 547 u32 pte = 0; 548 phys_addr_t page_addr_phys = 0; 549 u32 page_flags = 0; 550 551 dte_index = rk_iova_dte_index(iova); 552 pte_index = rk_iova_pte_index(iova); 553 page_offset = rk_iova_page_offset(iova); 554 555 mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR); 556 mmu_dte_addr_phys = rk_ops->pt_address(mmu_dte_addr); 557 558 dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index); 559 dte_addr = phys_to_virt(dte_addr_phys); 560 dte = *dte_addr; 561 562 if (!rk_dte_is_pt_valid(dte)) 563 goto print_it; 564 565 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4); 566 pte_addr = phys_to_virt(pte_addr_phys); 567 pte = *pte_addr; 568 569 if (!rk_pte_is_page_valid(pte)) 570 goto print_it; 571 572 page_addr_phys = rk_ops->pt_address(pte) + page_offset; 573 page_flags = pte & RK_PTE_PAGE_FLAGS_MASK; 574 575 print_it: 576 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n", 577 &iova, dte_index, pte_index, page_offset); 578 dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n", 579 &mmu_dte_addr_phys, &dte_addr_phys, dte, 580 rk_dte_is_pt_valid(dte), &pte_addr_phys, pte, 581 rk_pte_is_page_valid(pte), &page_addr_phys, page_flags); 582 } 583 584 static irqreturn_t rk_iommu_irq(int irq, void *dev_id) 585 { 586 struct rk_iommu *iommu = dev_id; 587 u32 status; 588 u32 int_status; 589 dma_addr_t iova; 590 irqreturn_t ret = IRQ_NONE; 591 int i, err; 592 593 err = pm_runtime_get_if_in_use(iommu->dev); 594 if (!err || WARN_ON_ONCE(err < 0)) 595 return ret; 596 597 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) 598 goto out; 599 600 for (i = 0; i < iommu->num_mmu; i++) { 601 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); 602 if (int_status == 0) 603 continue; 604 605 ret = IRQ_HANDLED; 606 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); 607 608 if (int_status & RK_MMU_IRQ_PAGE_FAULT) { 609 int flags; 610 611 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); 612 flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ? 613 IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; 614 615 dev_err(iommu->dev, "Page fault at %pad of type %s\n", 616 &iova, 617 str_write_read(flags == IOMMU_FAULT_WRITE)); 618 619 log_iova(iommu, i, iova); 620 621 /* 622 * Report page fault to any installed handlers. 623 * Ignore the return code, though, since we always zap cache 624 * and clear the page fault anyway. 625 */ 626 if (iommu->domain != &rk_identity_domain) 627 report_iommu_fault(iommu->domain, iommu->dev, iova, 628 flags); 629 else 630 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n"); 631 632 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 633 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); 634 } 635 636 if (int_status & RK_MMU_IRQ_BUS_ERROR) 637 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova); 638 639 if (int_status & ~RK_MMU_IRQ_MASK) 640 dev_err(iommu->dev, "unexpected int_status: %#08x\n", 641 int_status); 642 643 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status); 644 } 645 646 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 647 648 out: 649 pm_runtime_put(iommu->dev); 650 return ret; 651 } 652 653 static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain, 654 dma_addr_t iova) 655 { 656 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 657 unsigned long flags; 658 phys_addr_t pt_phys, phys = 0; 659 u32 dte, pte; 660 u32 *page_table; 661 662 spin_lock_irqsave(&rk_domain->dt_lock, flags); 663 664 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 665 if (!rk_dte_is_pt_valid(dte)) 666 goto out; 667 668 pt_phys = rk_ops->pt_address(dte); 669 page_table = (u32 *)phys_to_virt(pt_phys); 670 pte = page_table[rk_iova_pte_index(iova)]; 671 if (!rk_pte_is_page_valid(pte)) 672 goto out; 673 674 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova); 675 out: 676 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 677 678 return phys; 679 } 680 681 static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain, 682 dma_addr_t iova, size_t size) 683 { 684 struct list_head *pos; 685 unsigned long flags; 686 687 /* shootdown these iova from all iommus using this domain */ 688 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 689 list_for_each(pos, &rk_domain->iommus) { 690 struct rk_iommu *iommu; 691 int ret; 692 693 iommu = list_entry(pos, struct rk_iommu, node); 694 695 /* Only zap TLBs of IOMMUs that are powered on. */ 696 ret = pm_runtime_get_if_in_use(iommu->dev); 697 if (WARN_ON_ONCE(ret < 0)) 698 continue; 699 if (ret) { 700 WARN_ON(clk_bulk_enable(iommu->num_clocks, 701 iommu->clocks)); 702 rk_iommu_zap_lines(iommu, iova, size); 703 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 704 pm_runtime_put(iommu->dev); 705 } 706 } 707 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 708 } 709 710 static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain, 711 dma_addr_t iova, size_t size) 712 { 713 rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE); 714 if (size > SPAGE_SIZE) 715 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE, 716 SPAGE_SIZE); 717 } 718 719 static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain, 720 dma_addr_t iova) 721 { 722 u32 *page_table, *dte_addr; 723 u32 dte_index, dte; 724 phys_addr_t pt_phys; 725 dma_addr_t pt_dma; 726 727 assert_spin_locked(&rk_domain->dt_lock); 728 729 dte_index = rk_iova_dte_index(iova); 730 dte_addr = &rk_domain->dt[dte_index]; 731 dte = *dte_addr; 732 if (rk_dte_is_pt_valid(dte)) 733 goto done; 734 735 page_table = iommu_alloc_pages_sz(GFP_ATOMIC | rk_ops->gfp_flags, 736 SPAGE_SIZE); 737 if (!page_table) 738 return ERR_PTR(-ENOMEM); 739 740 pt_dma = dma_map_single(rk_domain->dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE); 741 if (dma_mapping_error(rk_domain->dma_dev, pt_dma)) { 742 dev_err(rk_domain->dma_dev, "DMA mapping error while allocating page table\n"); 743 iommu_free_pages(page_table); 744 return ERR_PTR(-ENOMEM); 745 } 746 747 dte = rk_ops->mk_dtentries(pt_dma); 748 *dte_addr = dte; 749 750 rk_table_flush(rk_domain, 751 rk_domain->dt_dma + dte_index * sizeof(u32), 1); 752 done: 753 pt_phys = rk_ops->pt_address(dte); 754 return (u32 *)phys_to_virt(pt_phys); 755 } 756 757 static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain, 758 u32 *pte_addr, dma_addr_t pte_dma, 759 size_t size) 760 { 761 unsigned int pte_count; 762 unsigned int pte_total = size / SPAGE_SIZE; 763 764 assert_spin_locked(&rk_domain->dt_lock); 765 766 for (pte_count = 0; pte_count < pte_total; pte_count++) { 767 u32 pte = pte_addr[pte_count]; 768 if (!rk_pte_is_page_valid(pte)) 769 break; 770 771 pte_addr[pte_count] = rk_mk_pte_invalid(pte); 772 } 773 774 rk_table_flush(rk_domain, pte_dma, pte_count); 775 776 return pte_count * SPAGE_SIZE; 777 } 778 779 static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr, 780 dma_addr_t pte_dma, dma_addr_t iova, 781 phys_addr_t paddr, size_t size, int prot) 782 { 783 unsigned int pte_count; 784 unsigned int pte_total = size / SPAGE_SIZE; 785 phys_addr_t page_phys; 786 787 assert_spin_locked(&rk_domain->dt_lock); 788 789 for (pte_count = 0; pte_count < pte_total; pte_count++) { 790 u32 pte = pte_addr[pte_count]; 791 792 if (rk_pte_is_page_valid(pte)) 793 goto unwind; 794 795 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot); 796 797 paddr += SPAGE_SIZE; 798 } 799 800 rk_table_flush(rk_domain, pte_dma, pte_total); 801 802 /* 803 * Zap the first and last iova to evict from iotlb any previously 804 * mapped cachelines holding stale values for its dte and pte. 805 * We only zap the first and last iova, since only they could have 806 * dte or pte shared with an existing mapping. 807 */ 808 rk_iommu_zap_iova_first_last(rk_domain, iova, size); 809 810 return 0; 811 unwind: 812 /* Unmap the range of iovas that we just mapped */ 813 rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, 814 pte_count * SPAGE_SIZE); 815 816 iova += pte_count * SPAGE_SIZE; 817 page_phys = rk_ops->pt_address(pte_addr[pte_count]); 818 pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n", 819 &iova, &page_phys, &paddr, prot); 820 821 return -EADDRINUSE; 822 } 823 824 static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova, 825 phys_addr_t paddr, size_t size, size_t count, 826 int prot, gfp_t gfp, size_t *mapped) 827 { 828 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 829 unsigned long flags; 830 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 831 u32 *page_table, *pte_addr; 832 u32 dte_index, pte_index; 833 int ret; 834 835 spin_lock_irqsave(&rk_domain->dt_lock, flags); 836 837 /* 838 * pgsize_bitmap specifies iova sizes that fit in one page table 839 * (1024 4-KiB pages = 4 MiB). 840 * So, size will always be 4096 <= size <= 4194304. 841 * Since iommu_map() guarantees that both iova and size will be 842 * aligned, we will always only be mapping from a single dte here. 843 */ 844 page_table = rk_dte_get_page_table(rk_domain, iova); 845 if (IS_ERR(page_table)) { 846 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 847 return PTR_ERR(page_table); 848 } 849 850 dte_index = rk_domain->dt[rk_iova_dte_index(iova)]; 851 pte_index = rk_iova_pte_index(iova); 852 pte_addr = &page_table[pte_index]; 853 854 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32); 855 ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova, 856 paddr, size, prot); 857 858 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 859 if (!ret) 860 *mapped = size; 861 862 return ret; 863 } 864 865 static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova, 866 size_t size, size_t count, struct iommu_iotlb_gather *gather) 867 { 868 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 869 unsigned long flags; 870 dma_addr_t pte_dma, iova = (dma_addr_t)_iova; 871 phys_addr_t pt_phys; 872 u32 dte; 873 u32 *pte_addr; 874 size_t unmap_size; 875 876 spin_lock_irqsave(&rk_domain->dt_lock, flags); 877 878 /* 879 * pgsize_bitmap specifies iova sizes that fit in one page table 880 * (1024 4-KiB pages = 4 MiB). 881 * So, size will always be 4096 <= size <= 4194304. 882 * Since iommu_unmap() guarantees that both iova and size will be 883 * aligned, we will always only be unmapping from a single dte here. 884 */ 885 dte = rk_domain->dt[rk_iova_dte_index(iova)]; 886 /* Just return 0 if iova is unmapped */ 887 if (!rk_dte_is_pt_valid(dte)) { 888 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 889 return 0; 890 } 891 892 pt_phys = rk_ops->pt_address(dte); 893 pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova); 894 pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32); 895 unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size); 896 897 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); 898 899 /* Shootdown iotlb entries for iova range that was just unmapped */ 900 rk_iommu_zap_iova(rk_domain, iova, unmap_size); 901 902 return unmap_size; 903 } 904 905 static struct rk_iommu *rk_iommu_from_dev(struct device *dev) 906 { 907 struct rk_iommudata *data = dev_iommu_priv_get(dev); 908 909 return data ? data->iommu : NULL; 910 } 911 912 /* Must be called with iommu powered on and attached */ 913 static void rk_iommu_disable(struct rk_iommu *iommu) 914 { 915 int i; 916 917 /* Ignore error while disabling, just keep going */ 918 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)); 919 rk_iommu_enable_stall(iommu); 920 rk_iommu_disable_paging(iommu); 921 for (i = 0; i < iommu->num_mmu; i++) { 922 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0); 923 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0); 924 } 925 rk_iommu_disable_stall(iommu); 926 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 927 } 928 929 /* Must be called with iommu powered on and attached */ 930 static int rk_iommu_enable(struct rk_iommu *iommu) 931 { 932 struct iommu_domain *domain = iommu->domain; 933 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 934 int ret, i; 935 u32 auto_gate; 936 937 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); 938 if (ret) 939 return ret; 940 941 ret = rk_iommu_enable_stall(iommu); 942 if (ret) 943 goto out_disable_clocks; 944 945 ret = rk_iommu_force_reset(iommu); 946 if (ret) 947 goto out_disable_stall; 948 949 for (i = 0; i < iommu->num_mmu; i++) { 950 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 951 rk_ops->mk_dtentries(rk_domain->dt_dma)); 952 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); 953 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); 954 955 /* Workaround for iommu blocked, BIT(31) default to 1 */ 956 auto_gate = rk_iommu_read(iommu->bases[i], RK_MMU_AUTO_GATING); 957 auto_gate |= DISABLE_FETCH_DTE_TIME_LIMIT; 958 rk_iommu_write(iommu->bases[i], RK_MMU_AUTO_GATING, auto_gate); 959 } 960 961 ret = rk_iommu_enable_paging(iommu); 962 963 out_disable_stall: 964 rk_iommu_disable_stall(iommu); 965 out_disable_clocks: 966 clk_bulk_disable(iommu->num_clocks, iommu->clocks); 967 return ret; 968 } 969 970 static int rk_iommu_identity_attach(struct iommu_domain *identity_domain, 971 struct device *dev, 972 struct iommu_domain *old) 973 { 974 struct rk_iommu *iommu; 975 struct rk_iommu_domain *rk_domain; 976 unsigned long flags; 977 int ret; 978 979 /* Allow 'virtual devices' (eg drm) to detach from domain */ 980 iommu = rk_iommu_from_dev(dev); 981 if (!iommu) 982 return -ENODEV; 983 984 rk_domain = to_rk_domain(iommu->domain); 985 986 dev_dbg(dev, "Detaching from iommu domain\n"); 987 988 if (iommu->domain == identity_domain) 989 return 0; 990 991 iommu->domain = identity_domain; 992 993 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 994 list_del_init(&iommu->node); 995 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 996 997 ret = pm_runtime_get_if_in_use(iommu->dev); 998 WARN_ON_ONCE(ret < 0); 999 if (ret > 0) { 1000 rk_iommu_disable(iommu); 1001 pm_runtime_put(iommu->dev); 1002 } 1003 1004 return 0; 1005 } 1006 1007 static struct iommu_domain_ops rk_identity_ops = { 1008 .attach_dev = rk_iommu_identity_attach, 1009 }; 1010 1011 static struct iommu_domain rk_identity_domain = { 1012 .type = IOMMU_DOMAIN_IDENTITY, 1013 .ops = &rk_identity_ops, 1014 }; 1015 1016 static int rk_iommu_attach_device(struct iommu_domain *domain, 1017 struct device *dev, struct iommu_domain *old) 1018 { 1019 struct rk_iommu *iommu; 1020 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1021 unsigned long flags; 1022 int ret; 1023 1024 /* 1025 * Allow 'virtual devices' (e.g., drm) to attach to domain. 1026 * Such a device does not belong to an iommu group. 1027 */ 1028 iommu = rk_iommu_from_dev(dev); 1029 if (!iommu) 1030 return 0; 1031 1032 dev_dbg(dev, "Attaching to iommu domain\n"); 1033 1034 /* iommu already attached */ 1035 if (iommu->domain == domain) 1036 return 0; 1037 1038 ret = rk_iommu_identity_attach(&rk_identity_domain, dev, old); 1039 if (ret) 1040 return ret; 1041 1042 iommu->domain = domain; 1043 1044 spin_lock_irqsave(&rk_domain->iommus_lock, flags); 1045 list_add_tail(&iommu->node, &rk_domain->iommus); 1046 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); 1047 1048 ret = pm_runtime_get_if_in_use(iommu->dev); 1049 if (!ret || WARN_ON_ONCE(ret < 0)) 1050 return 0; 1051 1052 ret = rk_iommu_enable(iommu); 1053 if (ret) { 1054 /* 1055 * Note rk_iommu_identity_attach() might fail before physically 1056 * attaching the dev to iommu->domain, in which case the actual 1057 * old domain for this revert should be rk_identity_domain v.s. 1058 * iommu->domain. Since rk_iommu_identity_attach() does not care 1059 * about the old domain argument for now, this is not a problem. 1060 */ 1061 WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev, 1062 iommu->domain)); 1063 } 1064 1065 pm_runtime_put(iommu->dev); 1066 1067 return ret; 1068 } 1069 1070 static struct iommu_domain *rk_iommu_domain_alloc_paging(struct device *dev) 1071 { 1072 struct rk_iommu_domain *rk_domain; 1073 struct rk_iommu *iommu; 1074 1075 rk_domain = kzalloc_obj(*rk_domain); 1076 if (!rk_domain) 1077 return NULL; 1078 1079 /* 1080 * rk32xx iommus use a 2 level pagetable. 1081 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries. 1082 * Allocate one 4 KiB page for each table. 1083 */ 1084 rk_domain->dt = iommu_alloc_pages_sz(GFP_KERNEL | rk_ops->gfp_flags, 1085 SPAGE_SIZE); 1086 if (!rk_domain->dt) 1087 goto err_free_domain; 1088 1089 iommu = rk_iommu_from_dev(dev); 1090 rk_domain->dma_dev = iommu->dev; 1091 rk_domain->dt_dma = dma_map_single(rk_domain->dma_dev, rk_domain->dt, 1092 SPAGE_SIZE, DMA_TO_DEVICE); 1093 if (dma_mapping_error(rk_domain->dma_dev, rk_domain->dt_dma)) { 1094 dev_err(rk_domain->dma_dev, "DMA map error for DT\n"); 1095 goto err_free_dt; 1096 } 1097 1098 spin_lock_init(&rk_domain->iommus_lock); 1099 spin_lock_init(&rk_domain->dt_lock); 1100 INIT_LIST_HEAD(&rk_domain->iommus); 1101 1102 rk_domain->domain.pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP; 1103 1104 rk_domain->domain.geometry.aperture_start = 0; 1105 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32); 1106 rk_domain->domain.geometry.force_aperture = true; 1107 1108 return &rk_domain->domain; 1109 1110 err_free_dt: 1111 iommu_free_pages(rk_domain->dt); 1112 err_free_domain: 1113 kfree(rk_domain); 1114 1115 return NULL; 1116 } 1117 1118 static void rk_iommu_domain_free(struct iommu_domain *domain) 1119 { 1120 struct rk_iommu_domain *rk_domain = to_rk_domain(domain); 1121 int i; 1122 1123 WARN_ON(!list_empty(&rk_domain->iommus)); 1124 1125 for (i = 0; i < NUM_DT_ENTRIES; i++) { 1126 u32 dte = rk_domain->dt[i]; 1127 if (rk_dte_is_pt_valid(dte)) { 1128 phys_addr_t pt_phys = rk_ops->pt_address(dte); 1129 u32 *page_table = phys_to_virt(pt_phys); 1130 dma_unmap_single(rk_domain->dma_dev, pt_phys, 1131 SPAGE_SIZE, DMA_TO_DEVICE); 1132 iommu_free_pages(page_table); 1133 } 1134 } 1135 1136 dma_unmap_single(rk_domain->dma_dev, rk_domain->dt_dma, 1137 SPAGE_SIZE, DMA_TO_DEVICE); 1138 iommu_free_pages(rk_domain->dt); 1139 1140 kfree(rk_domain); 1141 } 1142 1143 static struct iommu_device *rk_iommu_probe_device(struct device *dev) 1144 { 1145 struct rk_iommudata *data; 1146 struct rk_iommu *iommu; 1147 1148 data = dev_iommu_priv_get(dev); 1149 if (!data) 1150 return ERR_PTR(-ENODEV); 1151 1152 iommu = rk_iommu_from_dev(dev); 1153 1154 data->link = device_link_add(dev, iommu->dev, 1155 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME); 1156 1157 return &iommu->iommu; 1158 } 1159 1160 static void rk_iommu_release_device(struct device *dev) 1161 { 1162 struct rk_iommudata *data = dev_iommu_priv_get(dev); 1163 1164 device_link_del(data->link); 1165 } 1166 1167 static int rk_iommu_of_xlate(struct device *dev, 1168 const struct of_phandle_args *args) 1169 { 1170 struct platform_device *iommu_dev; 1171 struct rk_iommudata *data; 1172 1173 iommu_dev = of_find_device_by_node(args->np); 1174 1175 data = devm_kzalloc(&iommu_dev->dev, sizeof(*data), GFP_KERNEL); 1176 if (!data) 1177 return -ENOMEM; 1178 1179 data->iommu = platform_get_drvdata(iommu_dev); 1180 dev_iommu_priv_set(dev, data); 1181 1182 platform_device_put(iommu_dev); 1183 1184 return 0; 1185 } 1186 1187 static const struct iommu_ops rk_iommu_ops = { 1188 .identity_domain = &rk_identity_domain, 1189 .domain_alloc_paging = rk_iommu_domain_alloc_paging, 1190 .probe_device = rk_iommu_probe_device, 1191 .release_device = rk_iommu_release_device, 1192 .device_group = generic_single_device_group, 1193 .of_xlate = rk_iommu_of_xlate, 1194 .default_domain_ops = &(const struct iommu_domain_ops) { 1195 .attach_dev = rk_iommu_attach_device, 1196 .map_pages = rk_iommu_map, 1197 .unmap_pages = rk_iommu_unmap, 1198 .iova_to_phys = rk_iommu_iova_to_phys, 1199 .free = rk_iommu_domain_free, 1200 } 1201 }; 1202 1203 static int rk_iommu_probe(struct platform_device *pdev) 1204 { 1205 struct device *dev = &pdev->dev; 1206 struct rk_iommu *iommu; 1207 struct resource *res; 1208 const struct rk_iommu_ops *ops; 1209 int num_res = pdev->num_resources; 1210 int err, i; 1211 1212 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); 1213 if (!iommu) 1214 return -ENOMEM; 1215 1216 iommu->domain = &rk_identity_domain; 1217 1218 platform_set_drvdata(pdev, iommu); 1219 iommu->dev = dev; 1220 iommu->num_mmu = 0; 1221 1222 ops = of_device_get_match_data(dev); 1223 if (!rk_ops) 1224 rk_ops = ops; 1225 1226 /* 1227 * That should not happen unless different versions of the 1228 * hardware block are embedded the same SoC 1229 */ 1230 if (WARN_ON(rk_ops != ops)) 1231 return -EINVAL; 1232 1233 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), 1234 GFP_KERNEL); 1235 if (!iommu->bases) 1236 return -ENOMEM; 1237 1238 for (i = 0; i < num_res; i++) { 1239 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 1240 if (!res) 1241 continue; 1242 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res); 1243 if (IS_ERR(iommu->bases[i])) 1244 continue; 1245 iommu->num_mmu++; 1246 } 1247 if (iommu->num_mmu == 0) 1248 return PTR_ERR(iommu->bases[0]); 1249 1250 iommu->num_irq = platform_irq_count(pdev); 1251 if (iommu->num_irq < 0) 1252 return iommu->num_irq; 1253 1254 iommu->reset_disabled = device_property_read_bool(dev, 1255 "rockchip,disable-mmu-reset"); 1256 1257 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks); 1258 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks, 1259 sizeof(*iommu->clocks), GFP_KERNEL); 1260 if (!iommu->clocks) 1261 return -ENOMEM; 1262 1263 for (i = 0; i < iommu->num_clocks; ++i) 1264 iommu->clocks[i].id = rk_iommu_clocks[i]; 1265 1266 /* 1267 * iommu clocks should be present for all new devices and devicetrees 1268 * but there are older devicetrees without clocks out in the wild. 1269 * So clocks as optional for the time being. 1270 */ 1271 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks); 1272 if (err == -ENOENT) 1273 iommu->num_clocks = 0; 1274 else if (err) 1275 return err; 1276 1277 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks); 1278 if (err) 1279 return err; 1280 1281 pm_runtime_enable(dev); 1282 1283 for (i = 0; i < iommu->num_irq; i++) { 1284 int irq = platform_get_irq(pdev, i); 1285 1286 if (irq < 0) { 1287 err = irq; 1288 goto err_pm_disable; 1289 } 1290 1291 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, 1292 IRQF_SHARED, dev_name(dev), iommu); 1293 if (err) 1294 goto err_pm_disable; 1295 } 1296 1297 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask); 1298 1299 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev)); 1300 if (err) 1301 goto err_pm_disable; 1302 1303 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev); 1304 if (err) 1305 goto err_remove_sysfs; 1306 1307 return 0; 1308 err_remove_sysfs: 1309 iommu_device_sysfs_remove(&iommu->iommu); 1310 err_pm_disable: 1311 pm_runtime_disable(dev); 1312 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks); 1313 return err; 1314 } 1315 1316 static void rk_iommu_shutdown(struct platform_device *pdev) 1317 { 1318 struct rk_iommu *iommu = platform_get_drvdata(pdev); 1319 int i; 1320 1321 for (i = 0; i < iommu->num_irq; i++) { 1322 int irq = platform_get_irq(pdev, i); 1323 1324 devm_free_irq(iommu->dev, irq, iommu); 1325 } 1326 1327 pm_runtime_force_suspend(&pdev->dev); 1328 } 1329 1330 static int __maybe_unused rk_iommu_suspend(struct device *dev) 1331 { 1332 struct rk_iommu *iommu = dev_get_drvdata(dev); 1333 1334 if (iommu->domain == &rk_identity_domain) 1335 return 0; 1336 1337 rk_iommu_disable(iommu); 1338 return 0; 1339 } 1340 1341 static int __maybe_unused rk_iommu_resume(struct device *dev) 1342 { 1343 struct rk_iommu *iommu = dev_get_drvdata(dev); 1344 1345 if (iommu->domain == &rk_identity_domain) 1346 return 0; 1347 1348 return rk_iommu_enable(iommu); 1349 } 1350 1351 static const struct dev_pm_ops rk_iommu_pm_ops = { 1352 SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL) 1353 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1354 pm_runtime_force_resume) 1355 }; 1356 1357 static struct rk_iommu_ops iommu_data_ops_v1 = { 1358 .pt_address = &rk_dte_pt_address, 1359 .mk_dtentries = &rk_mk_dte, 1360 .mk_ptentries = &rk_mk_pte, 1361 .dma_bit_mask = DMA_BIT_MASK(32), 1362 .gfp_flags = GFP_DMA32, 1363 }; 1364 1365 static struct rk_iommu_ops iommu_data_ops_v2 = { 1366 .pt_address = &rk_dte_pt_address_v2, 1367 .mk_dtentries = &rk_mk_dte_v2, 1368 .mk_ptentries = &rk_mk_pte_v2, 1369 .dma_bit_mask = DMA_BIT_MASK(40), 1370 .gfp_flags = 0, 1371 }; 1372 1373 static const struct of_device_id rk_iommu_dt_ids[] = { 1374 { .compatible = "rockchip,iommu", 1375 .data = &iommu_data_ops_v1, 1376 }, 1377 { .compatible = "rockchip,rk3568-iommu", 1378 .data = &iommu_data_ops_v2, 1379 }, 1380 { /* sentinel */ } 1381 }; 1382 1383 static struct platform_driver rk_iommu_driver = { 1384 .probe = rk_iommu_probe, 1385 .shutdown = rk_iommu_shutdown, 1386 .driver = { 1387 .name = "rk_iommu", 1388 .of_match_table = rk_iommu_dt_ids, 1389 .pm = &rk_iommu_pm_ops, 1390 .suppress_bind_attrs = true, 1391 }, 1392 }; 1393 builtin_platform_driver(rk_iommu_driver); 1394