1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Collabora Ltd.
5 *
6 * Author: Algea Cao <algea.cao@rock-chips.com>
7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
8 */
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/rational.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #define GRF_HDPTX_CON0 0x00
25 #define HDPTX_I_PLL_EN BIT(7)
26 #define HDPTX_I_BIAS_EN BIT(6)
27 #define HDPTX_I_BGR_EN BIT(5)
28 #define GRF_HDPTX_STATUS 0x80
29 #define HDPTX_O_PLL_LOCK_DONE BIT(3)
30 #define HDPTX_O_PHY_CLK_RDY BIT(2)
31 #define HDPTX_O_PHY_RDY BIT(1)
32 #define HDPTX_O_SB_RDY BIT(0)
33
34 #define HDTPX_REG(_n, _min, _max) \
35 ( \
36 BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
37 BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
38 ((0x##_n) * 4) \
39 )
40
41 #define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
42 #define SB_REG(n) HDTPX_REG(n, 0100, 0129)
43 #define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
44 #define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
45
46 /* CMN_REG(0008) */
47 #define LCPLL_EN_MASK BIT(6)
48 #define LCPLL_LCVCO_MODE_EN_MASK BIT(4)
49 /* CMN_REG(001e) */
50 #define LCPLL_PI_EN_MASK BIT(5)
51 #define LCPLL_100M_CLK_EN_MASK BIT(0)
52 /* CMN_REG(0025) */
53 #define LCPLL_PMS_IQDIV_RSTN BIT(4)
54 /* CMN_REG(0028) */
55 #define LCPLL_SDC_FRAC_EN BIT(2)
56 #define LCPLL_SDC_FRAC_RSTN BIT(0)
57 /* CMN_REG(002d) */
58 #define LCPLL_SDC_N_MASK GENMASK(3, 1)
59 /* CMN_REG(002e) */
60 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)
61 /* CMN_REG(002f) */
62 #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)
63 #define LCPLL_SDC_NDIV_RSTN BIT(0)
64 /* CMN_REG(003d) */
65 #define ROPLL_LCVCO_EN BIT(4)
66 /* CMN_REG(004e) */
67 #define ROPLL_PI_EN BIT(5)
68 /* CMN_REG(005c) */
69 #define ROPLL_PMS_IQDIV_RSTN BIT(5)
70 /* CMN_REG(005e) */
71 #define ROPLL_SDM_EN_MASK BIT(6)
72 #define ROPLL_SDM_FRAC_EN_RBR BIT(3)
73 #define ROPLL_SDM_FRAC_EN_HBR BIT(2)
74 #define ROPLL_SDM_FRAC_EN_HBR2 BIT(1)
75 #define ROPLL_SDM_FRAC_EN_HBR3 BIT(0)
76 /* CMN_REG(0064) */
77 #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
78 /* CMN_REG(0069) */
79 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
80 /* CMN_REG(0074) */
81 #define ROPLL_SDC_NDIV_RSTN BIT(2)
82 #define ROPLL_SSC_EN BIT(0)
83 /* CMN_REG(0081) */
84 #define OVRD_PLL_CD_CLK_EN BIT(8)
85 #define PLL_CD_HSCLK_EAST_EN BIT(0)
86 /* CMN_REG(0086) */
87 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
88 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
89 #define PLL_PCG_CLK_EN BIT(0)
90 /* CMN_REG(0087) */
91 #define PLL_FRL_MODE_EN BIT(3)
92 #define PLL_TX_HS_CLK_EN BIT(2)
93 /* CMN_REG(0089) */
94 #define LCPLL_ALONE_MODE BIT(1)
95 /* CMN_REG(0097) */
96 #define DIG_CLK_SEL BIT(1)
97 #define ROPLL_REF BIT(1)
98 #define LCPLL_REF 0
99 /* CMN_REG(0099) */
100 #define CMN_ROPLL_ALONE_MODE BIT(2)
101 #define ROPLL_ALONE_MODE BIT(2)
102 /* CMN_REG(009a) */
103 #define HS_SPEED_SEL BIT(0)
104 #define DIV_10_CLOCK BIT(0)
105 /* CMN_REG(009b) */
106 #define IS_SPEED_SEL BIT(4)
107 #define LINK_SYMBOL_CLOCK BIT(4)
108 #define LINK_SYMBOL_CLOCK1_2 0
109
110 /* SB_REG(0102) */
111 #define OVRD_SB_RXTERM_EN_MASK BIT(5)
112 #define SB_RXTERM_EN_MASK BIT(4)
113 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)
114 /* SB_REG(0103) */
115 #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3)
116 #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1)
117 #define SB_RX_RESCAL_DONE_MASK BIT(0)
118 /* SB_REG(0104) */
119 #define OVRD_SB_EN_MASK BIT(5)
120 #define SB_EN_MASK BIT(4)
121 /* SB_REG(0105) */
122 #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6)
123 #define SB_EARC_CMDC_EN_MASK BIT(5)
124 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)
125 /* SB_REG(0106) */
126 #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)
127 /* SB_REG(0109) */
128 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
129 /* SB_REG(010f) */
130 #define OVRD_SB_VREG_EN_MASK BIT(7)
131 #define SB_VREG_EN_MASK BIT(6)
132 #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5)
133 #define SB_VREG_LPF_BYPASS_MASK BIT(4)
134 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
135 /* SB_REG(0110) */
136 #define ANA_SB_VREG_REF_SEL_MASK BIT(0)
137 /* SB_REG(0113) */
138 #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)
139 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)
140 /* SB_REG(0114) */
141 #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3)
142 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)
143 /* SB_REG(0115) */
144 #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3)
145 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)
146 /* SB_REG(0116) */
147 #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)
148 /* SB_REG(0117) */
149 #define FAST_PULSE_TIME_MASK GENMASK(3, 0)
150 /* SB_REG(011b) */
151 #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4)
152 #define SB_AFC_TOL_MASK GENMASK(3, 0)
153 /* SB_REG(011f) */
154 #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)
155 #define SB_RCAL_RSTN_MASK BIT(1)
156 /* SB_REG(0120) */
157 #define SB_EARC_EN_MASK BIT(1)
158 #define SB_EARC_AFC_EN_MASK BIT(2)
159 /* SB_REG(0123) */
160 #define OVRD_SB_READY_MASK BIT(5)
161 #define SB_READY_MASK BIT(4)
162
163 /* LNTOP_REG(0200) */
164 #define PROTOCOL_SEL BIT(2)
165 #define HDMI_MODE BIT(2)
166 #define HDMI_TMDS_FRL_SEL BIT(1)
167 /* LNTOP_REG(0206) */
168 #define DATA_BUS_SEL BIT(0)
169 #define DATA_BUS_36_40 BIT(0)
170 /* LNTOP_REG(0207) */
171 #define LANE_EN 0xf
172 #define ALL_LANE_EN 0xf
173
174 /* LANE_REG(0312) */
175 #define LN0_TX_SER_RATE_SEL_RBR BIT(5)
176 #define LN0_TX_SER_RATE_SEL_HBR BIT(4)
177 #define LN0_TX_SER_RATE_SEL_HBR2 BIT(3)
178 #define LN0_TX_SER_RATE_SEL_HBR3 BIT(2)
179 /* LANE_REG(0412) */
180 #define LN1_TX_SER_RATE_SEL_RBR BIT(5)
181 #define LN1_TX_SER_RATE_SEL_HBR BIT(4)
182 #define LN1_TX_SER_RATE_SEL_HBR2 BIT(3)
183 #define LN1_TX_SER_RATE_SEL_HBR3 BIT(2)
184 /* LANE_REG(0512) */
185 #define LN2_TX_SER_RATE_SEL_RBR BIT(5)
186 #define LN2_TX_SER_RATE_SEL_HBR BIT(4)
187 #define LN2_TX_SER_RATE_SEL_HBR2 BIT(3)
188 #define LN2_TX_SER_RATE_SEL_HBR3 BIT(2)
189 /* LANE_REG(0612) */
190 #define LN3_TX_SER_RATE_SEL_RBR BIT(5)
191 #define LN3_TX_SER_RATE_SEL_HBR BIT(4)
192 #define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
193 #define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
194
195 #define HDMI20_MAX_RATE 600000000
196
197 struct lcpll_config {
198 u32 bit_rate;
199 u8 lcvco_mode_en;
200 u8 pi_en;
201 u8 clk_en_100m;
202 u8 pms_mdiv;
203 u8 pms_mdiv_afc;
204 u8 pms_pdiv;
205 u8 pms_refdiv;
206 u8 pms_sdiv;
207 u8 pi_cdiv_rstn;
208 u8 pi_cdiv_sel;
209 u8 sdm_en;
210 u8 sdm_rstn;
211 u8 sdc_frac_en;
212 u8 sdc_rstn;
213 u8 sdm_deno;
214 u8 sdm_num_sign;
215 u8 sdm_num;
216 u8 sdc_n;
217 u8 sdc_n2;
218 u8 sdc_num;
219 u8 sdc_deno;
220 u8 sdc_ndiv_rstn;
221 u8 ssc_en;
222 u8 ssc_fm_dev;
223 u8 ssc_fm_freq;
224 u8 ssc_clk_div_sel;
225 u8 cd_tx_ser_rate_sel;
226 };
227
228 struct ropll_config {
229 u32 bit_rate;
230 u8 pms_mdiv;
231 u8 pms_mdiv_afc;
232 u8 pms_pdiv;
233 u8 pms_refdiv;
234 u8 pms_sdiv;
235 u8 pms_iqdiv_rstn;
236 u8 ref_clk_sel;
237 u8 sdm_en;
238 u8 sdm_rstn;
239 u8 sdc_frac_en;
240 u8 sdc_rstn;
241 u8 sdm_clk_div;
242 u8 sdm_deno;
243 u8 sdm_num_sign;
244 u8 sdm_num;
245 u8 sdc_n;
246 u8 sdc_num;
247 u8 sdc_deno;
248 u8 sdc_ndiv_rstn;
249 u8 ssc_en;
250 u8 ssc_fm_dev;
251 u8 ssc_fm_freq;
252 u8 ssc_clk_div_sel;
253 u8 ana_cpp_ctrl;
254 u8 ana_lpf_c_sel;
255 u8 cd_tx_ser_rate_sel;
256 };
257
258 enum rk_hdptx_reset {
259 RST_APB = 0,
260 RST_INIT,
261 RST_CMN,
262 RST_LANE,
263 RST_MAX
264 };
265
266 struct rk_hdptx_phy {
267 struct device *dev;
268 struct regmap *regmap;
269 struct regmap *grf;
270
271 struct phy *phy;
272 struct phy_config *phy_cfg;
273 struct clk_bulk_data *clks;
274 int nr_clks;
275 struct reset_control_bulk_data rsts[RST_MAX];
276
277 /* clk provider */
278 struct clk_hw hw;
279 unsigned long rate;
280
281 atomic_t usage_count;
282 };
283
284 static const struct ropll_config ropll_tmds_cfg[] = {
285 { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
286 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
287 { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
288 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
289 { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
290 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
291 { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
292 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
293 { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
294 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
295 { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
296 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
297 { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5,
298 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
299 { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
300 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
301 { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
302 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
303 { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
304 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
305 { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
306 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
307 { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
308 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
309 { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
310 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
311 { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
312 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
313 { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
314 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
315 { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
316 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
317 { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
318 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
319 { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
320 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
321 { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
322 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
323 { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1,
324 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
325 };
326
327 static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
328 REG_SEQ0(CMN_REG(0009), 0x0c),
329 REG_SEQ0(CMN_REG(000a), 0x83),
330 REG_SEQ0(CMN_REG(000b), 0x06),
331 REG_SEQ0(CMN_REG(000c), 0x20),
332 REG_SEQ0(CMN_REG(000d), 0xb8),
333 REG_SEQ0(CMN_REG(000e), 0x0f),
334 REG_SEQ0(CMN_REG(000f), 0x0f),
335 REG_SEQ0(CMN_REG(0010), 0x04),
336 REG_SEQ0(CMN_REG(0011), 0x00),
337 REG_SEQ0(CMN_REG(0012), 0x26),
338 REG_SEQ0(CMN_REG(0013), 0x22),
339 REG_SEQ0(CMN_REG(0014), 0x24),
340 REG_SEQ0(CMN_REG(0015), 0x77),
341 REG_SEQ0(CMN_REG(0016), 0x08),
342 REG_SEQ0(CMN_REG(0017), 0x00),
343 REG_SEQ0(CMN_REG(0018), 0x04),
344 REG_SEQ0(CMN_REG(0019), 0x48),
345 REG_SEQ0(CMN_REG(001a), 0x01),
346 REG_SEQ0(CMN_REG(001b), 0x00),
347 REG_SEQ0(CMN_REG(001c), 0x01),
348 REG_SEQ0(CMN_REG(001d), 0x64),
349 REG_SEQ0(CMN_REG(001f), 0x00),
350 REG_SEQ0(CMN_REG(0026), 0x53),
351 REG_SEQ0(CMN_REG(0029), 0x01),
352 REG_SEQ0(CMN_REG(0030), 0x00),
353 REG_SEQ0(CMN_REG(0031), 0x20),
354 REG_SEQ0(CMN_REG(0032), 0x30),
355 REG_SEQ0(CMN_REG(0033), 0x0b),
356 REG_SEQ0(CMN_REG(0034), 0x23),
357 REG_SEQ0(CMN_REG(0035), 0x00),
358 REG_SEQ0(CMN_REG(0038), 0x00),
359 REG_SEQ0(CMN_REG(0039), 0x00),
360 REG_SEQ0(CMN_REG(003a), 0x00),
361 REG_SEQ0(CMN_REG(003b), 0x00),
362 REG_SEQ0(CMN_REG(003c), 0x80),
363 REG_SEQ0(CMN_REG(003e), 0x0c),
364 REG_SEQ0(CMN_REG(003f), 0x83),
365 REG_SEQ0(CMN_REG(0040), 0x06),
366 REG_SEQ0(CMN_REG(0041), 0x20),
367 REG_SEQ0(CMN_REG(0042), 0xb8),
368 REG_SEQ0(CMN_REG(0043), 0x00),
369 REG_SEQ0(CMN_REG(0044), 0x46),
370 REG_SEQ0(CMN_REG(0045), 0x24),
371 REG_SEQ0(CMN_REG(0046), 0xff),
372 REG_SEQ0(CMN_REG(0047), 0x00),
373 REG_SEQ0(CMN_REG(0048), 0x44),
374 REG_SEQ0(CMN_REG(0049), 0xfa),
375 REG_SEQ0(CMN_REG(004a), 0x08),
376 REG_SEQ0(CMN_REG(004b), 0x00),
377 REG_SEQ0(CMN_REG(004c), 0x01),
378 REG_SEQ0(CMN_REG(004d), 0x64),
379 REG_SEQ0(CMN_REG(004e), 0x14),
380 REG_SEQ0(CMN_REG(004f), 0x00),
381 REG_SEQ0(CMN_REG(0050), 0x00),
382 REG_SEQ0(CMN_REG(005d), 0x0c),
383 REG_SEQ0(CMN_REG(005f), 0x01),
384 REG_SEQ0(CMN_REG(006b), 0x04),
385 REG_SEQ0(CMN_REG(0073), 0x30),
386 REG_SEQ0(CMN_REG(0074), 0x00),
387 REG_SEQ0(CMN_REG(0075), 0x20),
388 REG_SEQ0(CMN_REG(0076), 0x30),
389 REG_SEQ0(CMN_REG(0077), 0x08),
390 REG_SEQ0(CMN_REG(0078), 0x0c),
391 REG_SEQ0(CMN_REG(0079), 0x00),
392 REG_SEQ0(CMN_REG(007b), 0x00),
393 REG_SEQ0(CMN_REG(007c), 0x00),
394 REG_SEQ0(CMN_REG(007d), 0x00),
395 REG_SEQ0(CMN_REG(007e), 0x00),
396 REG_SEQ0(CMN_REG(007f), 0x00),
397 REG_SEQ0(CMN_REG(0080), 0x00),
398 REG_SEQ0(CMN_REG(0081), 0x09),
399 REG_SEQ0(CMN_REG(0082), 0x04),
400 REG_SEQ0(CMN_REG(0083), 0x24),
401 REG_SEQ0(CMN_REG(0084), 0x20),
402 REG_SEQ0(CMN_REG(0085), 0x03),
403 REG_SEQ0(CMN_REG(0086), 0x01),
404 REG_SEQ0(CMN_REG(0087), 0x0c),
405 REG_SEQ0(CMN_REG(008a), 0x55),
406 REG_SEQ0(CMN_REG(008b), 0x25),
407 REG_SEQ0(CMN_REG(008c), 0x2c),
408 REG_SEQ0(CMN_REG(008d), 0x22),
409 REG_SEQ0(CMN_REG(008e), 0x14),
410 REG_SEQ0(CMN_REG(008f), 0x20),
411 REG_SEQ0(CMN_REG(0090), 0x00),
412 REG_SEQ0(CMN_REG(0091), 0x00),
413 REG_SEQ0(CMN_REG(0092), 0x00),
414 REG_SEQ0(CMN_REG(0093), 0x00),
415 REG_SEQ0(CMN_REG(009a), 0x11),
416 REG_SEQ0(CMN_REG(009b), 0x10),
417 };
418
419 static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
420 REG_SEQ0(CMN_REG(0008), 0x00),
421 REG_SEQ0(CMN_REG(0011), 0x01),
422 REG_SEQ0(CMN_REG(0017), 0x20),
423 REG_SEQ0(CMN_REG(001e), 0x14),
424 REG_SEQ0(CMN_REG(0020), 0x00),
425 REG_SEQ0(CMN_REG(0021), 0x00),
426 REG_SEQ0(CMN_REG(0022), 0x11),
427 REG_SEQ0(CMN_REG(0023), 0x00),
428 REG_SEQ0(CMN_REG(0024), 0x00),
429 REG_SEQ0(CMN_REG(0025), 0x53),
430 REG_SEQ0(CMN_REG(0026), 0x00),
431 REG_SEQ0(CMN_REG(0027), 0x00),
432 REG_SEQ0(CMN_REG(0028), 0x01),
433 REG_SEQ0(CMN_REG(002a), 0x00),
434 REG_SEQ0(CMN_REG(002b), 0x00),
435 REG_SEQ0(CMN_REG(002c), 0x00),
436 REG_SEQ0(CMN_REG(002d), 0x00),
437 REG_SEQ0(CMN_REG(002e), 0x04),
438 REG_SEQ0(CMN_REG(002f), 0x00),
439 REG_SEQ0(CMN_REG(0030), 0x20),
440 REG_SEQ0(CMN_REG(0031), 0x30),
441 REG_SEQ0(CMN_REG(0032), 0x0b),
442 REG_SEQ0(CMN_REG(0033), 0x23),
443 REG_SEQ0(CMN_REG(0034), 0x00),
444 REG_SEQ0(CMN_REG(003d), 0x40),
445 REG_SEQ0(CMN_REG(0042), 0x78),
446 REG_SEQ0(CMN_REG(004e), 0x34),
447 REG_SEQ0(CMN_REG(005c), 0x25),
448 REG_SEQ0(CMN_REG(005e), 0x4f),
449 REG_SEQ0(CMN_REG(0074), 0x04),
450 REG_SEQ0(CMN_REG(0081), 0x01),
451 REG_SEQ0(CMN_REG(0087), 0x04),
452 REG_SEQ0(CMN_REG(0089), 0x00),
453 REG_SEQ0(CMN_REG(0095), 0x00),
454 REG_SEQ0(CMN_REG(0097), 0x02),
455 REG_SEQ0(CMN_REG(0099), 0x04),
456 REG_SEQ0(CMN_REG(009b), 0x00),
457 };
458
459 static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
460 REG_SEQ0(SB_REG(0114), 0x00),
461 REG_SEQ0(SB_REG(0115), 0x00),
462 REG_SEQ0(SB_REG(0116), 0x00),
463 REG_SEQ0(SB_REG(0117), 0x00),
464 };
465
466 static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
467 REG_SEQ0(LNTOP_REG(0201), 0x00),
468 REG_SEQ0(LNTOP_REG(0202), 0x00),
469 REG_SEQ0(LNTOP_REG(0203), 0x0f),
470 REG_SEQ0(LNTOP_REG(0204), 0xff),
471 REG_SEQ0(LNTOP_REG(0205), 0xff),
472 };
473
474 static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
475 REG_SEQ0(LNTOP_REG(0201), 0x07),
476 REG_SEQ0(LNTOP_REG(0202), 0xc1),
477 REG_SEQ0(LNTOP_REG(0203), 0xf0),
478 REG_SEQ0(LNTOP_REG(0204), 0x7c),
479 REG_SEQ0(LNTOP_REG(0205), 0x1f),
480 };
481
482 static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
483 REG_SEQ0(LANE_REG(0303), 0x0c),
484 REG_SEQ0(LANE_REG(0307), 0x20),
485 REG_SEQ0(LANE_REG(030a), 0x17),
486 REG_SEQ0(LANE_REG(030b), 0x77),
487 REG_SEQ0(LANE_REG(030c), 0x77),
488 REG_SEQ0(LANE_REG(030d), 0x77),
489 REG_SEQ0(LANE_REG(030e), 0x38),
490 REG_SEQ0(LANE_REG(0310), 0x03),
491 REG_SEQ0(LANE_REG(0311), 0x0f),
492 REG_SEQ0(LANE_REG(0316), 0x02),
493 REG_SEQ0(LANE_REG(031b), 0x01),
494 REG_SEQ0(LANE_REG(031f), 0x15),
495 REG_SEQ0(LANE_REG(0320), 0xa0),
496 REG_SEQ0(LANE_REG(0403), 0x0c),
497 REG_SEQ0(LANE_REG(0407), 0x20),
498 REG_SEQ0(LANE_REG(040a), 0x17),
499 REG_SEQ0(LANE_REG(040b), 0x77),
500 REG_SEQ0(LANE_REG(040c), 0x77),
501 REG_SEQ0(LANE_REG(040d), 0x77),
502 REG_SEQ0(LANE_REG(040e), 0x38),
503 REG_SEQ0(LANE_REG(0410), 0x03),
504 REG_SEQ0(LANE_REG(0411), 0x0f),
505 REG_SEQ0(LANE_REG(0416), 0x02),
506 REG_SEQ0(LANE_REG(041b), 0x01),
507 REG_SEQ0(LANE_REG(041f), 0x15),
508 REG_SEQ0(LANE_REG(0420), 0xa0),
509 REG_SEQ0(LANE_REG(0503), 0x0c),
510 REG_SEQ0(LANE_REG(0507), 0x20),
511 REG_SEQ0(LANE_REG(050a), 0x17),
512 REG_SEQ0(LANE_REG(050b), 0x77),
513 REG_SEQ0(LANE_REG(050c), 0x77),
514 REG_SEQ0(LANE_REG(050d), 0x77),
515 REG_SEQ0(LANE_REG(050e), 0x38),
516 REG_SEQ0(LANE_REG(0510), 0x03),
517 REG_SEQ0(LANE_REG(0511), 0x0f),
518 REG_SEQ0(LANE_REG(0516), 0x02),
519 REG_SEQ0(LANE_REG(051b), 0x01),
520 REG_SEQ0(LANE_REG(051f), 0x15),
521 REG_SEQ0(LANE_REG(0520), 0xa0),
522 REG_SEQ0(LANE_REG(0603), 0x0c),
523 REG_SEQ0(LANE_REG(0607), 0x20),
524 REG_SEQ0(LANE_REG(060a), 0x17),
525 REG_SEQ0(LANE_REG(060b), 0x77),
526 REG_SEQ0(LANE_REG(060c), 0x77),
527 REG_SEQ0(LANE_REG(060d), 0x77),
528 REG_SEQ0(LANE_REG(060e), 0x38),
529 REG_SEQ0(LANE_REG(0610), 0x03),
530 REG_SEQ0(LANE_REG(0611), 0x0f),
531 REG_SEQ0(LANE_REG(0616), 0x02),
532 REG_SEQ0(LANE_REG(061b), 0x01),
533 REG_SEQ0(LANE_REG(061f), 0x15),
534 REG_SEQ0(LANE_REG(0620), 0xa0),
535 };
536
537 static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
538 REG_SEQ0(LANE_REG(0312), 0x00),
539 REG_SEQ0(LANE_REG(031e), 0x00),
540 REG_SEQ0(LANE_REG(0412), 0x00),
541 REG_SEQ0(LANE_REG(041e), 0x00),
542 REG_SEQ0(LANE_REG(0512), 0x00),
543 REG_SEQ0(LANE_REG(051e), 0x00),
544 REG_SEQ0(LANE_REG(0612), 0x00),
545 REG_SEQ0(LANE_REG(061e), 0x08),
546 REG_SEQ0(LANE_REG(0303), 0x2f),
547 REG_SEQ0(LANE_REG(0403), 0x2f),
548 REG_SEQ0(LANE_REG(0503), 0x2f),
549 REG_SEQ0(LANE_REG(0603), 0x2f),
550 REG_SEQ0(LANE_REG(0305), 0x03),
551 REG_SEQ0(LANE_REG(0405), 0x03),
552 REG_SEQ0(LANE_REG(0505), 0x03),
553 REG_SEQ0(LANE_REG(0605), 0x03),
554 REG_SEQ0(LANE_REG(0306), 0x1c),
555 REG_SEQ0(LANE_REG(0406), 0x1c),
556 REG_SEQ0(LANE_REG(0506), 0x1c),
557 REG_SEQ0(LANE_REG(0606), 0x1c),
558 };
559
rk_hdptx_phy_is_rw_reg(struct device * dev,unsigned int reg)560 static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
561 {
562 switch (reg) {
563 case 0x0000 ... 0x029c:
564 case 0x0400 ... 0x04a4:
565 case 0x0800 ... 0x08a4:
566 case 0x0c00 ... 0x0cb4:
567 case 0x1000 ... 0x10b4:
568 case 0x1400 ... 0x14b4:
569 case 0x1800 ... 0x18b4:
570 return true;
571 }
572
573 return false;
574 }
575
576 static const struct regmap_config rk_hdptx_phy_regmap_config = {
577 .reg_bits = 32,
578 .reg_stride = 4,
579 .val_bits = 32,
580 .writeable_reg = rk_hdptx_phy_is_rw_reg,
581 .readable_reg = rk_hdptx_phy_is_rw_reg,
582 .fast_io = true,
583 .max_register = 0x18b4,
584 };
585
586 #define rk_hdptx_multi_reg_write(hdptx, seq) \
587 regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq))
588
rk_hdptx_pre_power_up(struct rk_hdptx_phy * hdptx)589 static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx)
590 {
591 u32 val;
592
593 reset_control_assert(hdptx->rsts[RST_APB].rstc);
594 usleep_range(20, 25);
595 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
596
597 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
598 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
599 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
600
601 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
602 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
603 }
604
rk_hdptx_post_enable_lane(struct rk_hdptx_phy * hdptx)605 static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
606 {
607 u32 val;
608 int ret;
609
610 reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
611
612 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
613 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
614 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
615
616 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
617 (val & HDPTX_O_PHY_RDY) &&
618 (val & HDPTX_O_PLL_LOCK_DONE),
619 100, 5000);
620 if (ret) {
621 dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret);
622 return ret;
623 }
624
625 dev_dbg(hdptx->dev, "PHY lane locked\n");
626
627 return 0;
628 }
629
rk_hdptx_post_enable_pll(struct rk_hdptx_phy * hdptx)630 static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
631 {
632 u32 val;
633 int ret;
634
635 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
636 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
637 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
638
639 usleep_range(10, 15);
640 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
641
642 usleep_range(10, 15);
643 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
644 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
645
646 usleep_range(10, 15);
647 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
648
649 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
650 val & HDPTX_O_PHY_CLK_RDY, 20, 400);
651 if (ret) {
652 dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret);
653 return ret;
654 }
655
656 dev_dbg(hdptx->dev, "PHY clk ready\n");
657
658 return 0;
659 }
660
rk_hdptx_phy_disable(struct rk_hdptx_phy * hdptx)661 static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
662 {
663 u32 val;
664
665 reset_control_assert(hdptx->rsts[RST_APB].rstc);
666 usleep_range(20, 30);
667 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
668
669 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
670 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
671 regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
672 regmap_write(hdptx->regmap, LANE_REG(0301), 0x80);
673 regmap_write(hdptx->regmap, LANE_REG(0401), 0x80);
674 regmap_write(hdptx->regmap, LANE_REG(0501), 0x80);
675 regmap_write(hdptx->regmap, LANE_REG(0601), 0x80);
676
677 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
678 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
679 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
680
681 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
682 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
683 }
684
rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,struct ropll_config * cfg)685 static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
686 struct ropll_config *cfg)
687 {
688 const unsigned int fout = data_rate / 2, fref = 24000;
689 unsigned long k = 0, lc, k_sub, lc_sub;
690 unsigned int fvco, sdc;
691 u32 mdiv, sdiv, n = 8;
692
693 if (fout > 0xfffffff)
694 return false;
695
696 for (sdiv = 16; sdiv >= 1; sdiv--) {
697 if (sdiv % 2 && sdiv != 1)
698 continue;
699
700 fvco = fout * sdiv;
701
702 if (fvco < 2000000 || fvco > 4000000)
703 continue;
704
705 mdiv = DIV_ROUND_UP(fvco, fref);
706 if (mdiv < 20 || mdiv > 255)
707 continue;
708
709 if (fref * mdiv - fvco) {
710 for (sdc = 264000; sdc <= 750000; sdc += fref)
711 if (sdc * n > fref * mdiv)
712 break;
713
714 if (sdc > 750000)
715 continue;
716
717 rational_best_approximation(fref * mdiv - fvco,
718 sdc / 16,
719 GENMASK(6, 0),
720 GENMASK(7, 0),
721 &k, &lc);
722
723 rational_best_approximation(sdc * n - fref * mdiv,
724 sdc,
725 GENMASK(6, 0),
726 GENMASK(7, 0),
727 &k_sub, &lc_sub);
728 }
729
730 break;
731 }
732
733 if (sdiv < 1)
734 return false;
735
736 if (cfg) {
737 cfg->pms_mdiv = mdiv;
738 cfg->pms_mdiv_afc = mdiv;
739 cfg->pms_pdiv = 1;
740 cfg->pms_refdiv = 1;
741 cfg->pms_sdiv = sdiv - 1;
742
743 cfg->sdm_en = k > 0 ? 1 : 0;
744 if (cfg->sdm_en) {
745 cfg->sdm_deno = lc;
746 cfg->sdm_num_sign = 1;
747 cfg->sdm_num = k;
748 cfg->sdc_n = n - 3;
749 cfg->sdc_num = k_sub;
750 cfg->sdc_deno = lc_sub;
751 }
752 }
753
754 return true;
755 }
756
rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy * hdptx,unsigned int rate)757 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
758 unsigned int rate)
759 {
760 const struct ropll_config *cfg = NULL;
761 struct ropll_config rc = {0};
762 int i;
763
764 hdptx->rate = rate * 100;
765
766 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
767 if (rate == ropll_tmds_cfg[i].bit_rate) {
768 cfg = &ropll_tmds_cfg[i];
769 break;
770 }
771
772 if (!cfg) {
773 if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) {
774 cfg = &rc;
775 } else {
776 dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
777 return -EINVAL;
778 }
779 }
780
781 dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n",
782 cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
783 cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
784
785 rk_hdptx_pre_power_up(hdptx);
786
787 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
788 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
789
790 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
791 regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
792 regmap_write(hdptx->regmap, CMN_REG(0059),
793 (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
794 regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4);
795
796 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
797 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en));
798 if (!cfg->sdm_en)
799 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0);
800
801 regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK,
802 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign));
803
804 regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno);
805 regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num);
806
807 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
808 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n));
809
810 regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num);
811 regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno);
812
813 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
814 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
815
816 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN,
817 PLL_PCG_CLK_EN);
818
819 return rk_hdptx_post_enable_pll(hdptx);
820 }
821
rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy * hdptx,unsigned int rate)822 static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
823 unsigned int rate)
824 {
825 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
826
827 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
828
829 if (rate >= 3400000) {
830 /* For 1/40 bitrate clk */
831 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
832 } else {
833 /* For 1/10 bitrate clk */
834 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
835 }
836
837 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
838 regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
839
840 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
841 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
842
843 return rk_hdptx_post_enable_lane(hdptx);
844 }
845
rk_hdptx_phy_consumer_get(struct rk_hdptx_phy * hdptx,unsigned int rate)846 static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
847 unsigned int rate)
848 {
849 u32 status;
850 int ret;
851
852 if (atomic_inc_return(&hdptx->usage_count) > 1)
853 return 0;
854
855 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
856 if (ret)
857 goto dec_usage;
858
859 if (status & HDPTX_O_PLL_LOCK_DONE)
860 dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
861
862 if (rate) {
863 ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
864 if (ret)
865 goto dec_usage;
866 }
867
868 return 0;
869
870 dec_usage:
871 atomic_dec(&hdptx->usage_count);
872 return ret;
873 }
874
rk_hdptx_phy_consumer_put(struct rk_hdptx_phy * hdptx,bool force)875 static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
876 {
877 u32 status;
878 int ret;
879
880 ret = atomic_dec_return(&hdptx->usage_count);
881 if (ret > 0)
882 return 0;
883
884 if (ret < 0) {
885 dev_warn(hdptx->dev, "Usage count underflow!\n");
886 ret = -EINVAL;
887 } else {
888 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
889 if (!ret) {
890 if (status & HDPTX_O_PLL_LOCK_DONE)
891 rk_hdptx_phy_disable(hdptx);
892 return 0;
893 } else if (force) {
894 return 0;
895 }
896 }
897
898 atomic_inc(&hdptx->usage_count);
899 return ret;
900 }
901
rk_hdptx_phy_power_on(struct phy * phy)902 static int rk_hdptx_phy_power_on(struct phy *phy)
903 {
904 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
905 int bus_width = phy_get_bus_width(hdptx->phy);
906 int ret;
907
908 /*
909 * FIXME: Temporary workaround to pass pixel_clk_rate
910 * from the HDMI bridge driver until phy_configure_opts_hdmi
911 * becomes available in the PHY API.
912 */
913 unsigned int rate = bus_width & 0xfffffff;
914
915 dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
916 __func__, bus_width, rate);
917
918 ret = rk_hdptx_phy_consumer_get(hdptx, rate);
919 if (ret)
920 return ret;
921
922 ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
923 if (ret)
924 rk_hdptx_phy_consumer_put(hdptx, true);
925
926 return ret;
927 }
928
rk_hdptx_phy_power_off(struct phy * phy)929 static int rk_hdptx_phy_power_off(struct phy *phy)
930 {
931 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
932
933 return rk_hdptx_phy_consumer_put(hdptx, false);
934 }
935
936 static const struct phy_ops rk_hdptx_phy_ops = {
937 .power_on = rk_hdptx_phy_power_on,
938 .power_off = rk_hdptx_phy_power_off,
939 .owner = THIS_MODULE,
940 };
941
to_rk_hdptx_phy(struct clk_hw * hw)942 static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
943 {
944 return container_of(hw, struct rk_hdptx_phy, hw);
945 }
946
rk_hdptx_phy_clk_prepare(struct clk_hw * hw)947 static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
948 {
949 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
950
951 return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100);
952 }
953
rk_hdptx_phy_clk_unprepare(struct clk_hw * hw)954 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
955 {
956 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
957
958 rk_hdptx_phy_consumer_put(hdptx, true);
959 }
960
rk_hdptx_phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)961 static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
962 unsigned long parent_rate)
963 {
964 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
965
966 return hdptx->rate;
967 }
968
rk_hdptx_phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)969 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
970 unsigned long *parent_rate)
971 {
972 u32 bit_rate = rate / 100;
973 int i;
974
975 if (rate > HDMI20_MAX_RATE)
976 return rate;
977
978 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
979 if (bit_rate == ropll_tmds_cfg[i].bit_rate)
980 break;
981
982 if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
983 !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
984 return -EINVAL;
985
986 return rate;
987 }
988
rk_hdptx_phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)989 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
990 unsigned long parent_rate)
991 {
992 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
993
994 return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
995 }
996
997 static const struct clk_ops hdptx_phy_clk_ops = {
998 .prepare = rk_hdptx_phy_clk_prepare,
999 .unprepare = rk_hdptx_phy_clk_unprepare,
1000 .recalc_rate = rk_hdptx_phy_clk_recalc_rate,
1001 .round_rate = rk_hdptx_phy_clk_round_rate,
1002 .set_rate = rk_hdptx_phy_clk_set_rate,
1003 };
1004
rk_hdptx_phy_clk_register(struct rk_hdptx_phy * hdptx)1005 static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
1006 {
1007 struct device *dev = hdptx->dev;
1008 const char *name, *pname;
1009 struct clk *refclk;
1010 int ret, id;
1011
1012 refclk = devm_clk_get(dev, "ref");
1013 if (IS_ERR(refclk))
1014 return dev_err_probe(dev, PTR_ERR(refclk),
1015 "Failed to get ref clock\n");
1016
1017 id = of_alias_get_id(dev->of_node, "hdptxphy");
1018 name = id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
1019 pname = __clk_get_name(refclk);
1020
1021 hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
1022 CLK_GET_RATE_NOCACHE);
1023
1024 ret = devm_clk_hw_register(dev, &hdptx->hw);
1025 if (ret)
1026 return dev_err_probe(dev, ret, "Failed to register clock\n");
1027
1028 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
1029 if (ret)
1030 return dev_err_probe(dev, ret,
1031 "Failed to register clk provider\n");
1032 return 0;
1033 }
1034
rk_hdptx_phy_runtime_suspend(struct device * dev)1035 static int rk_hdptx_phy_runtime_suspend(struct device *dev)
1036 {
1037 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1038
1039 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
1040
1041 return 0;
1042 }
1043
rk_hdptx_phy_runtime_resume(struct device * dev)1044 static int rk_hdptx_phy_runtime_resume(struct device *dev)
1045 {
1046 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1047 int ret;
1048
1049 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
1050 if (ret)
1051 dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret);
1052
1053 return ret;
1054 }
1055
rk_hdptx_phy_probe(struct platform_device * pdev)1056 static int rk_hdptx_phy_probe(struct platform_device *pdev)
1057 {
1058 struct phy_provider *phy_provider;
1059 struct device *dev = &pdev->dev;
1060 struct rk_hdptx_phy *hdptx;
1061 void __iomem *regs;
1062 int ret;
1063
1064 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
1065 if (!hdptx)
1066 return -ENOMEM;
1067
1068 hdptx->dev = dev;
1069
1070 regs = devm_platform_ioremap_resource(pdev, 0);
1071 if (IS_ERR(regs))
1072 return dev_err_probe(dev, PTR_ERR(regs),
1073 "Failed to ioremap resource\n");
1074
1075 ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
1076 if (ret < 0)
1077 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1078 if (ret == 0)
1079 return dev_err_probe(dev, -EINVAL, "Missing clocks\n");
1080
1081 hdptx->nr_clks = ret;
1082
1083 hdptx->regmap = devm_regmap_init_mmio(dev, regs,
1084 &rk_hdptx_phy_regmap_config);
1085 if (IS_ERR(hdptx->regmap))
1086 return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
1087 "Failed to init regmap\n");
1088
1089 hdptx->rsts[RST_APB].id = "apb";
1090 hdptx->rsts[RST_INIT].id = "init";
1091 hdptx->rsts[RST_CMN].id = "cmn";
1092 hdptx->rsts[RST_LANE].id = "lane";
1093
1094 ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts);
1095 if (ret)
1096 return dev_err_probe(dev, ret, "Failed to get resets\n");
1097
1098 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1099 "rockchip,grf");
1100 if (IS_ERR(hdptx->grf))
1101 return dev_err_probe(dev, PTR_ERR(hdptx->grf),
1102 "Could not get GRF syscon\n");
1103
1104 platform_set_drvdata(pdev, hdptx);
1105
1106 ret = devm_pm_runtime_enable(dev);
1107 if (ret)
1108 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
1109
1110 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops);
1111 if (IS_ERR(hdptx->phy))
1112 return dev_err_probe(dev, PTR_ERR(hdptx->phy),
1113 "Failed to create HDMI PHY\n");
1114
1115 phy_set_drvdata(hdptx->phy, hdptx);
1116 phy_set_bus_width(hdptx->phy, 8);
1117
1118 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1119 if (IS_ERR(phy_provider))
1120 return dev_err_probe(dev, PTR_ERR(phy_provider),
1121 "Failed to register PHY provider\n");
1122
1123 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
1124 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
1125 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
1126
1127 return rk_hdptx_phy_clk_register(hdptx);
1128 }
1129
1130 static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
1131 RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend,
1132 rk_hdptx_phy_runtime_resume, NULL)
1133 };
1134
1135 static const struct of_device_id rk_hdptx_phy_of_match[] = {
1136 { .compatible = "rockchip,rk3588-hdptx-phy", },
1137 {}
1138 };
1139 MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match);
1140
1141 static struct platform_driver rk_hdptx_phy_driver = {
1142 .probe = rk_hdptx_phy_probe,
1143 .driver = {
1144 .name = "rockchip-hdptx-phy",
1145 .pm = &rk_hdptx_phy_pm_ops,
1146 .of_match_table = rk_hdptx_phy_of_match,
1147 },
1148 };
1149 module_platform_driver(rk_hdptx_phy_driver);
1150
1151 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
1152 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>");
1153 MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver");
1154 MODULE_LICENSE("GPL");
1155