1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic Register Files setup
4 *
5 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
6 */
7
8 #include <linux/err.h>
9 #include <linux/hw_bitfield.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14
15
16 struct rockchip_grf_value {
17 const char *desc;
18 u32 reg;
19 u32 val;
20 };
21
22 struct rockchip_grf_info {
23 const struct rockchip_grf_value *values;
24 int num_values;
25 };
26
27 #define RK3036_GRF_SOC_CON0 0x140
28
29 static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
30 /*
31 * Disable auto jtag/sdmmc switching that causes issues with the
32 * clock-framework and the mmc controllers making them unreliable.
33 */
34 { "jtag switching", RK3036_GRF_SOC_CON0, FIELD_PREP_WM16_CONST(BIT(11), 0) },
35 };
36
37 static const struct rockchip_grf_info rk3036_grf __initconst = {
38 .values = rk3036_defaults,
39 .num_values = ARRAY_SIZE(rk3036_defaults),
40 };
41
42 #define RK3128_GRF_SOC_CON0 0x140
43 #define RK3128_GRF_SOC_CON1 0x144
44
45 static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
46 { "jtag switching", RK3128_GRF_SOC_CON0, FIELD_PREP_WM16_CONST(BIT(8), 0) },
47 { "vpu main clock", RK3128_GRF_SOC_CON1, FIELD_PREP_WM16_CONST(BIT(10), 0) },
48 };
49
50 static const struct rockchip_grf_info rk3128_grf __initconst = {
51 .values = rk3128_defaults,
52 .num_values = ARRAY_SIZE(rk3128_defaults),
53 };
54
55 #define RK3228_GRF_SOC_CON6 0x418
56
57 static const struct rockchip_grf_value rk3228_defaults[] __initconst = {
58 { "jtag switching", RK3228_GRF_SOC_CON6, FIELD_PREP_WM16_CONST(BIT(8), 0) },
59 };
60
61 static const struct rockchip_grf_info rk3228_grf __initconst = {
62 .values = rk3228_defaults,
63 .num_values = ARRAY_SIZE(rk3228_defaults),
64 };
65
66 #define RK3288_GRF_SOC_CON0 0x244
67 #define RK3288_GRF_SOC_CON2 0x24c
68
69 static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
70 { "jtag switching", RK3288_GRF_SOC_CON0, FIELD_PREP_WM16_CONST(BIT(12), 0) },
71 { "pwm select", RK3288_GRF_SOC_CON2, FIELD_PREP_WM16_CONST(BIT(0), 1) },
72 };
73
74 static const struct rockchip_grf_info rk3288_grf __initconst = {
75 .values = rk3288_defaults,
76 .num_values = ARRAY_SIZE(rk3288_defaults),
77 };
78
79 #define RK3328_GRF_SOC_CON4 0x410
80
81 static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
82 { "jtag switching", RK3328_GRF_SOC_CON4, FIELD_PREP_WM16_CONST(BIT(12), 0) },
83 };
84
85 static const struct rockchip_grf_info rk3328_grf __initconst = {
86 .values = rk3328_defaults,
87 .num_values = ARRAY_SIZE(rk3328_defaults),
88 };
89
90 #define RK3368_GRF_SOC_CON15 0x43c
91
92 static const struct rockchip_grf_value rk3368_defaults[] __initconst = {
93 { "jtag switching", RK3368_GRF_SOC_CON15, FIELD_PREP_WM16_CONST(BIT(13), 0) },
94 { "pwm select", RK3368_GRF_SOC_CON15, FIELD_PREP_WM16_CONST(BIT(12), 1) },
95 };
96
97 static const struct rockchip_grf_info rk3368_grf __initconst = {
98 .values = rk3368_defaults,
99 .num_values = ARRAY_SIZE(rk3368_defaults),
100 };
101
102 #define RK3368_PMUGRF_SOC_CON0 0x100
103
104 static const struct rockchip_grf_value rk3368_pmugrf_defaults[] __initconst = {
105 { "pwm2 select", RK3368_PMUGRF_SOC_CON0, FIELD_PREP_WM16_CONST(BIT(7), 0) },
106 };
107
108 static const struct rockchip_grf_info rk3368_pmugrf __initconst = {
109 .values = rk3368_pmugrf_defaults,
110 .num_values = ARRAY_SIZE(rk3368_pmugrf_defaults),
111 };
112
113 #define RK3399_GRF_SOC_CON7 0xe21c
114
115 static const struct rockchip_grf_value rk3399_defaults[] __initconst = {
116 { "jtag switching", RK3399_GRF_SOC_CON7, FIELD_PREP_WM16_CONST(BIT(12), 0) },
117 };
118
119 static const struct rockchip_grf_info rk3399_grf __initconst = {
120 .values = rk3399_defaults,
121 .num_values = ARRAY_SIZE(rk3399_defaults),
122 };
123
124 #define RK3566_GRF_USB3OTG0_CON1 0x0104
125
126 static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
127 { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, FIELD_PREP_WM16_CONST(BIT(12), 0) },
128 { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, FIELD_PREP_WM16_CONST(BIT(7), 1) },
129 { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, FIELD_PREP_WM16_CONST(BIT(0), 1) },
130 };
131
132 static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
133 .values = rk3566_defaults,
134 .num_values = ARRAY_SIZE(rk3566_defaults),
135 };
136
137 #define RK3576_SYSGRF_SOC_CON1 0x0004
138
139 static const struct rockchip_grf_value rk3576_defaults_sys_grf[] __initconst = {
140 { "i3c0 weakpull", RK3576_SYSGRF_SOC_CON1, FIELD_PREP_WM16_CONST(GENMASK(7, 6), 3) },
141 { "i3c1 weakpull", RK3576_SYSGRF_SOC_CON1, FIELD_PREP_WM16_CONST(GENMASK(9, 8), 3) },
142 };
143
144 static const struct rockchip_grf_info rk3576_sysgrf __initconst = {
145 .values = rk3576_defaults_sys_grf,
146 .num_values = ARRAY_SIZE(rk3576_defaults_sys_grf),
147 };
148
149 #define RK3576_IOCGRF_MISC_CON 0x04F0
150
151 static const struct rockchip_grf_value rk3576_defaults_ioc_grf[] __initconst = {
152 { "jtag switching", RK3576_IOCGRF_MISC_CON, FIELD_PREP_WM16_CONST(BIT(1), 0) },
153 };
154
155 static const struct rockchip_grf_info rk3576_iocgrf __initconst = {
156 .values = rk3576_defaults_ioc_grf,
157 .num_values = ARRAY_SIZE(rk3576_defaults_ioc_grf),
158 };
159
160 #define RK3588_GRF_SOC_CON6 0x0318
161
162 static const struct rockchip_grf_value rk3588_defaults[] __initconst = {
163 { "jtag switching", RK3588_GRF_SOC_CON6, FIELD_PREP_WM16_CONST(BIT(14), 0) },
164 };
165
166 static const struct rockchip_grf_info rk3588_sysgrf __initconst = {
167 .values = rk3588_defaults,
168 .num_values = ARRAY_SIZE(rk3588_defaults),
169 };
170
171 static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
172 {
173 .compatible = "rockchip,rk3036-grf",
174 .data = (void *)&rk3036_grf,
175 }, {
176 .compatible = "rockchip,rk3128-grf",
177 .data = (void *)&rk3128_grf,
178 }, {
179 .compatible = "rockchip,rk3228-grf",
180 .data = (void *)&rk3228_grf,
181 }, {
182 .compatible = "rockchip,rk3288-grf",
183 .data = (void *)&rk3288_grf,
184 }, {
185 .compatible = "rockchip,rk3328-grf",
186 .data = (void *)&rk3328_grf,
187 }, {
188 .compatible = "rockchip,rk3368-grf",
189 .data = (void *)&rk3368_grf,
190 }, {
191 .compatible = "rockchip,rk3368-pmugrf",
192 .data = (void *)&rk3368_pmugrf,
193 }, {
194 .compatible = "rockchip,rk3399-grf",
195 .data = (void *)&rk3399_grf,
196 }, {
197 .compatible = "rockchip,rk3566-pipe-grf",
198 .data = (void *)&rk3566_pipegrf,
199 }, {
200 .compatible = "rockchip,rk3576-sys-grf",
201 .data = (void *)&rk3576_sysgrf,
202 }, {
203 .compatible = "rockchip,rk3576-ioc-grf",
204 .data = (void *)&rk3576_iocgrf,
205 }, {
206 .compatible = "rockchip,rk3588-sys-grf",
207 .data = (void *)&rk3588_sysgrf,
208 },
209 { /* sentinel */ },
210 };
211
rockchip_grf_init(void)212 static int __init rockchip_grf_init(void)
213 {
214 const struct rockchip_grf_info *grf_info;
215 const struct of_device_id *match;
216 struct device_node *np;
217 struct regmap *grf;
218 int ret, i;
219
220 np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match,
221 &match);
222 if (!np)
223 return -ENODEV;
224 if (!match || !match->data) {
225 pr_err("%s: missing grf data\n", __func__);
226 of_node_put(np);
227 return -EINVAL;
228 }
229
230 grf_info = match->data;
231
232 grf = syscon_node_to_regmap(np);
233 of_node_put(np);
234 if (IS_ERR(grf)) {
235 pr_err("%s: could not get grf syscon\n", __func__);
236 return PTR_ERR(grf);
237 }
238
239 for (i = 0; i < grf_info->num_values; i++) {
240 const struct rockchip_grf_value *val = &grf_info->values[i];
241
242 pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
243 val->desc, val->reg, val->val);
244 ret = regmap_write(grf, val->reg, val->val);
245 if (ret < 0)
246 pr_err("%s: write to %#6x failed with %d\n",
247 __func__, val->reg, ret);
248 }
249
250 return 0;
251 }
252 postcore_initcall(rockchip_grf_init);
253