1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <dt-bindings/reset/rockchip,rk3506-cru.h>
10 #include "clk.h"
11
12 /* 0xFF9A0000 + 0x0A00 */
13 #define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
14
15 /* mapping table for reset ID to register offset */
16 static const int rk3506_register_offset[] = {
17 /* CRU-->SOFTRST_CON00 */
18 RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0),
19 RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1),
20 RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2),
21 RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4),
22 RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5),
23 RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6),
24 RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8),
25 RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9),
26 RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10),
27
28 /* CRU-->SOFTRST_CON02 */
29 RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10),
30 RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14),
31 RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15),
32
33 /* CRU-->SOFTRST_CON03 */
34 RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1),
35 RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2),
36 RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4),
37 RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6),
38 RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
39 RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8),
40 RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9),
41
42 /* CRU-->SOFTRST_CON04 */
43 RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3),
44 RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5),
45 RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6),
46 RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
47 RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9),
48 RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10),
49 RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
50 RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12),
51 RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13),
52
53 /* CRU-->SOFTRST_CON05 */
54 RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3),
55 RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4),
56 RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5),
57 RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6),
58 RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7),
59 RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8),
60 RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9),
61 RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10),
62 RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11),
63 RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15),
64
65 /* CRU-->SOFTRST_CON06 */
66 RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0),
67 RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1),
68 RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2),
69 RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3),
70 RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4),
71 RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5),
72 RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6),
73 RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7),
74 RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8),
75 RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9),
76 RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10),
77 RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11),
78 RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12),
79 RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13),
80 RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14),
81 RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15),
82
83 /* CRU-->SOFTRST_CON07 */
84 RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0),
85 RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1),
86 RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2),
87 RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3),
88 RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4),
89 RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5),
90 RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7),
91 RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8),
92 RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10),
93 RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11),
94 RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12),
95 RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
96 RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14),
97
98 /* CRU-->SOFTRST_CON08 */
99 RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0),
100 RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1),
101
102 /* CRU-->SOFTRST_CON09 */
103 RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0),
104 RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1),
105
106 /* CRU-->SOFTRST_CON10 */
107 RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0),
108 RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1),
109 RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2),
110 RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3),
111 RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4),
112
113 /* CRU-->SOFTRST_CON11 */
114 RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2),
115 RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4),
116 RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5),
117 RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6),
118 RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7),
119 RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8),
120 RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9),
121 RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10),
122 RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11),
123 RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12),
124 RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
125 RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14),
126 RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15),
127
128 /* CRU-->SOFTRST_CON12 */
129 RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
130 RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1),
131 RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2),
132 RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3),
133 RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4),
134 RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5),
135 RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10),
136 RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11),
137 RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12),
138 RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13),
139 RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14),
140 RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15),
141
142 /* CRU-->SOFTRST_CON13 */
143 RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0),
144 RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1),
145 RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2),
146 RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3),
147 RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4),
148 RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5),
149 RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6),
150 RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7),
151 RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8),
152 RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9),
153 RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10),
154 RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11),
155 RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12),
156 RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13),
157 RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14),
158 RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15),
159
160 /* CRU-->SOFTRST_CON14 */
161 RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0),
162 RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2),
163 RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3),
164 RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5),
165 RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6),
166 RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7),
167 RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8),
168
169 /* CRU-->SOFTRST_CON17 */
170 RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4),
171 RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7),
172 RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8),
173 RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9),
174 RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10),
175 RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11),
176 RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12),
177
178 /* CRU-->SOFTRST_CON18 */
179 RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2),
180 RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3),
181 RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6),
182 RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7),
183 RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10),
184 RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11),
185 RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12),
186 RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13),
187 RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14),
188 RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15),
189
190 /* CRU-->SOFTRST_CON19 */
191 RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0),
192 RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1),
193 RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2),
194 RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3),
195 RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4),
196 RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5),
197 RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6),
198 RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7),
199 RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8),
200
201 /* CRU-->SOFTRST_CON21 */
202 RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3),
203 RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4),
204 RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6),
205 RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7),
206 RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8),
207 RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9),
208 RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10),
209 RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11),
210 RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12),
211 RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13),
212 RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14),
213 RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15),
214
215 /* CRU-->SOFTRST_CON22 */
216 RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1),
217 };
218
rk3506_rst_init(struct device_node * np,void __iomem * reg_base)219 void rk3506_rst_init(struct device_node *np, void __iomem *reg_base)
220 {
221 rockchip_register_softrst_lut(np,
222 rk3506_register_offset,
223 ARRAY_SIZE(rk3506_register_offset),
224 reg_base + RK3506_SOFTRST_CON(0),
225 ROCKCHIP_SOFTRST_HIWORD_MASK);
226 }
227