1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 *
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 *
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 */
9
10 #include <linux/stmmac.h>
11 #include <linux/hw_bitfield.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/phy.h>
15 #include <linux/of_net.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/delay.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/regmap.h>
23 #include <linux/pm_runtime.h>
24
25 #include "stmmac_platform.h"
26
27 struct rk_priv_data;
28
29 struct rk_reg_speed_data {
30 unsigned int rgmii_10;
31 unsigned int rgmii_100;
32 unsigned int rgmii_1000;
33 unsigned int rmii_10;
34 unsigned int rmii_100;
35 };
36
37 struct rk_gmac_ops {
38 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
39 int tx_delay, int rx_delay);
40 void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
41 int (*set_speed)(struct rk_priv_data *bsp_priv,
42 phy_interface_t interface, int speed);
43 void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
44 bool enable);
45 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
46 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);
47 bool php_grf_required;
48 bool regs_valid;
49 u32 regs[];
50 };
51
52 static const char * const rk_clocks[] = {
53 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
54 };
55
56 static const char * const rk_rmii_clocks[] = {
57 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout",
58 };
59
60 enum rk_clocks_index {
61 RK_ACLK_MAC = 0,
62 RK_PCLK_MAC,
63 RK_MAC_CLK_TX,
64 RK_CLK_MAC_SPEED,
65 RK_MAC_CLK_RX,
66 RK_CLK_MAC_REF,
67 RK_CLK_MAC_REFOUT,
68 };
69
70 struct rk_priv_data {
71 struct device *dev;
72 phy_interface_t phy_iface;
73 int id;
74 struct regulator *regulator;
75 const struct rk_gmac_ops *ops;
76
77 bool clk_enabled;
78 bool clock_input;
79 bool integrated_phy;
80
81 struct clk_bulk_data *clks;
82 int num_clks;
83 struct clk *clk_phy;
84
85 struct reset_control *phy_reset;
86
87 int tx_delay;
88 int rx_delay;
89
90 struct regmap *grf;
91 struct regmap *php_grf;
92 };
93
rk_set_reg_speed(struct rk_priv_data * bsp_priv,const struct rk_reg_speed_data * rsd,unsigned int reg,phy_interface_t interface,int speed)94 static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
95 const struct rk_reg_speed_data *rsd,
96 unsigned int reg, phy_interface_t interface,
97 int speed)
98 {
99 unsigned int val;
100
101 if (phy_interface_mode_is_rgmii(interface)) {
102 if (speed == SPEED_10) {
103 val = rsd->rgmii_10;
104 } else if (speed == SPEED_100) {
105 val = rsd->rgmii_100;
106 } else if (speed == SPEED_1000) {
107 val = rsd->rgmii_1000;
108 } else {
109 /* Phylink will not allow inappropriate speeds for
110 * interface modes, so this should never happen.
111 */
112 return -EINVAL;
113 }
114 } else if (interface == PHY_INTERFACE_MODE_RMII) {
115 if (speed == SPEED_10) {
116 val = rsd->rmii_10;
117 } else if (speed == SPEED_100) {
118 val = rsd->rmii_100;
119 } else {
120 /* Phylink will not allow inappropriate speeds for
121 * interface modes, so this should never happen.
122 */
123 return -EINVAL;
124 }
125 } else {
126 /* This should never happen, as .get_interfaces() limits
127 * the interface modes that are supported to RGMII and/or
128 * RMII.
129 */
130 return -EINVAL;
131 }
132
133 regmap_write(bsp_priv->grf, reg, val);
134
135 return 0;
136
137 }
138
rk_set_clk_mac_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)139 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
140 phy_interface_t interface, int speed)
141 {
142 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
143 long rate;
144
145 rate = rgmii_clock(speed);
146 if (rate < 0)
147 return rate;
148
149 return clk_set_rate(clk_mac_speed, rate);
150 }
151
152 #define GRF_FIELD(hi, lo, val) \
153 FIELD_PREP_WM16(GENMASK_U16(hi, lo), val)
154 #define GRF_FIELD_CONST(hi, lo, val) \
155 FIELD_PREP_WM16_CONST(GENMASK_U16(hi, lo), val)
156
157 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
158 #define GRF_CLR_BIT(nr) (BIT(nr+16))
159
160 #define DELAY_ENABLE(soc, tx, rx) \
161 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
162 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
163
164 #define RK_GRF_MACPHY_CON0 0xb00
165 #define RK_GRF_MACPHY_CON1 0xb04
166 #define RK_GRF_MACPHY_CON2 0xb08
167 #define RK_GRF_MACPHY_CON3 0xb0c
168
169 #define RK_MACPHY_ENABLE GRF_BIT(0)
170 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
171 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
172 #define RK_GMAC2PHY_RMII_MODE GRF_FIELD(7, 6, 1)
173 #define RK_GRF_CON2_MACPHY_ID GRF_FIELD(15, 0, 0x1234)
174 #define RK_GRF_CON3_MACPHY_ID GRF_FIELD(5, 0, 0x35)
175
rk_gmac_integrated_ephy_powerup(struct rk_priv_data * priv)176 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
177 {
178 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
179 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
180
181 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
182 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
183
184 if (priv->phy_reset) {
185 /* PHY needs to be disabled before trying to reset it */
186 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
187 if (priv->phy_reset)
188 reset_control_assert(priv->phy_reset);
189 usleep_range(10, 20);
190 if (priv->phy_reset)
191 reset_control_deassert(priv->phy_reset);
192 usleep_range(10, 20);
193 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
194 msleep(30);
195 }
196 }
197
rk_gmac_integrated_ephy_powerdown(struct rk_priv_data * priv)198 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
199 {
200 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
201 if (priv->phy_reset)
202 reset_control_assert(priv->phy_reset);
203 }
204
205 #define RK_FEPHY_SHUTDOWN GRF_BIT(1)
206 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
207 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
208 #define RK_FEPHY_24M_CLK_SEL GRF_FIELD(9, 8, 3)
209 #define RK_FEPHY_PHY_ID GRF_BIT(11)
210
rk_gmac_integrated_fephy_powerup(struct rk_priv_data * priv,unsigned int reg)211 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv,
212 unsigned int reg)
213 {
214 reset_control_assert(priv->phy_reset);
215 usleep_range(20, 30);
216
217 regmap_write(priv->grf, reg,
218 RK_FEPHY_POWERUP |
219 RK_FEPHY_INTERNAL_RMII_SEL |
220 RK_FEPHY_24M_CLK_SEL |
221 RK_FEPHY_PHY_ID);
222 usleep_range(10000, 12000);
223
224 reset_control_deassert(priv->phy_reset);
225 usleep_range(50000, 60000);
226 }
227
rk_gmac_integrated_fephy_powerdown(struct rk_priv_data * priv,unsigned int reg)228 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
229 unsigned int reg)
230 {
231 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN);
232 }
233
234 #define PX30_GRF_GMAC_CON1 0x0904
235
236 /* PX30_GRF_GMAC_CON1 */
237 #define PX30_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
238 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
239 #define PX30_GMAC_SPEED_100M GRF_BIT(2)
240
px30_set_to_rmii(struct rk_priv_data * bsp_priv)241 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
242 {
243 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
244 PX30_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
245 }
246
px30_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)247 static int px30_set_speed(struct rk_priv_data *bsp_priv,
248 phy_interface_t interface, int speed)
249 {
250 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
251 struct device *dev = bsp_priv->dev;
252 unsigned int con1;
253 long rate;
254
255 if (!clk_mac_speed) {
256 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
257 return -EINVAL;
258 }
259
260 if (speed == 10) {
261 con1 = PX30_GMAC_SPEED_10M;
262 rate = 2500000;
263 } else if (speed == 100) {
264 con1 = PX30_GMAC_SPEED_100M;
265 rate = 25000000;
266 } else {
267 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
268 return -EINVAL;
269 }
270
271 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, con1);
272
273 return clk_set_rate(clk_mac_speed, rate);
274 }
275
276 static const struct rk_gmac_ops px30_ops = {
277 .set_to_rmii = px30_set_to_rmii,
278 .set_speed = px30_set_speed,
279 };
280
281 #define RK3128_GRF_MAC_CON0 0x0168
282 #define RK3128_GRF_MAC_CON1 0x016c
283
284 /* RK3128_GRF_MAC_CON0 */
285 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
286 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
287 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
288 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
289 #define RK3128_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
290 #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
291
292 /* RK3128_GRF_MAC_CON1 */
293 #define RK3128_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val)
294 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
295 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
296 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
297 #define RK3128_GMAC_SPEED_100M GRF_BIT(10)
298 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
299 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
300 #define RK3128_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0)
301 #define RK3128_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3)
302 #define RK3128_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2)
303 #define RK3128_GMAC_RMII_MODE GRF_BIT(14)
304 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
305
rk3128_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)306 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
307 int tx_delay, int rx_delay)
308 {
309 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
310 RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
311 RK3128_GMAC_RMII_MODE_CLR);
312 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
313 DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
314 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
315 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
316 }
317
rk3128_set_to_rmii(struct rk_priv_data * bsp_priv)318 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
319 {
320 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
321 RK3128_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
322 RK3128_GMAC_RMII_MODE);
323 }
324
325 static const struct rk_reg_speed_data rk3128_reg_speed_data = {
326 .rgmii_10 = RK3128_GMAC_CLK_2_5M,
327 .rgmii_100 = RK3128_GMAC_CLK_25M,
328 .rgmii_1000 = RK3128_GMAC_CLK_125M,
329 .rmii_10 = RK3128_GMAC_RMII_CLK_2_5M | RK3128_GMAC_SPEED_10M,
330 .rmii_100 = RK3128_GMAC_RMII_CLK_25M | RK3128_GMAC_SPEED_100M,
331 };
332
rk3128_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)333 static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
334 phy_interface_t interface, int speed)
335 {
336 return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data,
337 RK3128_GRF_MAC_CON1, interface, speed);
338 }
339
340 static const struct rk_gmac_ops rk3128_ops = {
341 .set_to_rgmii = rk3128_set_to_rgmii,
342 .set_to_rmii = rk3128_set_to_rmii,
343 .set_speed = rk3128_set_speed,
344 };
345
346 #define RK3228_GRF_MAC_CON0 0x0900
347 #define RK3228_GRF_MAC_CON1 0x0904
348
349 #define RK3228_GRF_CON_MUX 0x50
350
351 /* RK3228_GRF_MAC_CON0 */
352 #define RK3228_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
353 #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
354
355 /* RK3228_GRF_MAC_CON1 */
356 #define RK3228_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
357 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
358 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
359 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
360 #define RK3228_GMAC_SPEED_100M GRF_BIT(2)
361 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
362 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
363 #define RK3228_GMAC_CLK_125M GRF_FIELD_CONST(9, 8, 0)
364 #define RK3228_GMAC_CLK_25M GRF_FIELD_CONST(9, 8, 3)
365 #define RK3228_GMAC_CLK_2_5M GRF_FIELD_CONST(9, 8, 2)
366 #define RK3228_GMAC_RMII_MODE GRF_BIT(10)
367 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
368 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
369 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
370 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
371 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
372
373 /* RK3228_GRF_COM_MUX */
374 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
375
rk3228_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)376 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
377 int tx_delay, int rx_delay)
378 {
379 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
380 RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
381 RK3228_GMAC_RMII_MODE_CLR |
382 DELAY_ENABLE(RK3228, tx_delay, rx_delay));
383
384 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
385 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
386 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
387 }
388
rk3228_set_to_rmii(struct rk_priv_data * bsp_priv)389 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
390 {
391 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
392 RK3228_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
393 RK3228_GMAC_RMII_MODE);
394
395 /* set MAC to RMII mode */
396 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
397 }
398
399 static const struct rk_reg_speed_data rk3228_reg_speed_data = {
400 .rgmii_10 = RK3228_GMAC_CLK_2_5M,
401 .rgmii_100 = RK3228_GMAC_CLK_25M,
402 .rgmii_1000 = RK3228_GMAC_CLK_125M,
403 .rmii_10 = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_SPEED_10M,
404 .rmii_100 = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_SPEED_100M,
405 };
406
rk3228_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)407 static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
408 phy_interface_t interface, int speed)
409 {
410 return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data,
411 RK3228_GRF_MAC_CON1, interface, speed);
412 }
413
rk3228_integrated_phy_powerup(struct rk_priv_data * priv)414 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
415 {
416 regmap_write(priv->grf, RK3228_GRF_CON_MUX,
417 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
418
419 rk_gmac_integrated_ephy_powerup(priv);
420 }
421
422 static const struct rk_gmac_ops rk3228_ops = {
423 .set_to_rgmii = rk3228_set_to_rgmii,
424 .set_to_rmii = rk3228_set_to_rmii,
425 .set_speed = rk3228_set_speed,
426 .integrated_phy_powerup = rk3228_integrated_phy_powerup,
427 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
428 };
429
430 #define RK3288_GRF_SOC_CON1 0x0248
431 #define RK3288_GRF_SOC_CON3 0x0250
432
433 /*RK3288_GRF_SOC_CON1*/
434 #define RK3288_GMAC_PHY_INTF_SEL(val) GRF_FIELD(8, 6, val)
435 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
436 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
437 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
438 #define RK3288_GMAC_SPEED_100M GRF_BIT(10)
439 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
440 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
441 #define RK3288_GMAC_CLK_125M GRF_FIELD_CONST(13, 12, 0)
442 #define RK3288_GMAC_CLK_25M GRF_FIELD_CONST(13, 12, 3)
443 #define RK3288_GMAC_CLK_2_5M GRF_FIELD_CONST(13, 12, 2)
444 #define RK3288_GMAC_RMII_MODE GRF_BIT(14)
445 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
446
447 /*RK3288_GRF_SOC_CON3*/
448 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
449 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
450 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
451 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
452 #define RK3288_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
453 #define RK3288_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
454
rk3288_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)455 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
456 int tx_delay, int rx_delay)
457 {
458 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
459 RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
460 RK3288_GMAC_RMII_MODE_CLR);
461 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
462 DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
463 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
464 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
465 }
466
rk3288_set_to_rmii(struct rk_priv_data * bsp_priv)467 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
468 {
469 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
470 RK3288_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
471 RK3288_GMAC_RMII_MODE);
472 }
473
474 static const struct rk_reg_speed_data rk3288_reg_speed_data = {
475 .rgmii_10 = RK3288_GMAC_CLK_2_5M,
476 .rgmii_100 = RK3288_GMAC_CLK_25M,
477 .rgmii_1000 = RK3288_GMAC_CLK_125M,
478 .rmii_10 = RK3288_GMAC_RMII_CLK_2_5M | RK3288_GMAC_SPEED_10M,
479 .rmii_100 = RK3288_GMAC_RMII_CLK_25M | RK3288_GMAC_SPEED_100M,
480 };
481
rk3288_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)482 static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
483 phy_interface_t interface, int speed)
484 {
485 return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data,
486 RK3288_GRF_SOC_CON1, interface, speed);
487 }
488
489 static const struct rk_gmac_ops rk3288_ops = {
490 .set_to_rgmii = rk3288_set_to_rgmii,
491 .set_to_rmii = rk3288_set_to_rmii,
492 .set_speed = rk3288_set_speed,
493 };
494
495 #define RK3308_GRF_MAC_CON0 0x04a0
496
497 /* RK3308_GRF_MAC_CON0 */
498 #define RK3308_GMAC_PHY_INTF_SEL(val) GRF_FIELD(4, 2, val)
499 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
500 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
501 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
502 #define RK3308_GMAC_SPEED_100M GRF_BIT(0)
503
rk3308_set_to_rmii(struct rk_priv_data * bsp_priv)504 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
505 {
506 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
507 RK3308_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
508 }
509
510 static const struct rk_reg_speed_data rk3308_reg_speed_data = {
511 .rmii_10 = RK3308_GMAC_SPEED_10M,
512 .rmii_100 = RK3308_GMAC_SPEED_100M,
513 };
514
rk3308_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)515 static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
516 phy_interface_t interface, int speed)
517 {
518 return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data,
519 RK3308_GRF_MAC_CON0, interface, speed);
520 }
521
522 static const struct rk_gmac_ops rk3308_ops = {
523 .set_to_rmii = rk3308_set_to_rmii,
524 .set_speed = rk3308_set_speed,
525 };
526
527 #define RK3328_GRF_MAC_CON0 0x0900
528 #define RK3328_GRF_MAC_CON1 0x0904
529 #define RK3328_GRF_MAC_CON2 0x0908
530 #define RK3328_GRF_MACPHY_CON1 0xb04
531
532 /* RK3328_GRF_MAC_CON0 */
533 #define RK3328_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
534 #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
535
536 /* RK3328_GRF_MAC_CON1 */
537 #define RK3328_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
538 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
539 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
540 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
541 #define RK3328_GMAC_SPEED_100M GRF_BIT(2)
542 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
543 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
544 #define RK3328_GMAC_CLK_125M GRF_FIELD_CONST(12, 11, 0)
545 #define RK3328_GMAC_CLK_25M GRF_FIELD_CONST(12, 11, 3)
546 #define RK3328_GMAC_CLK_2_5M GRF_FIELD_CONST(12, 11, 2)
547 #define RK3328_GMAC_RMII_MODE GRF_BIT(9)
548 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
549 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
550 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
551
552 /* RK3328_GRF_MACPHY_CON1 */
553 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
554
rk3328_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)555 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
556 int tx_delay, int rx_delay)
557 {
558 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
559 RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
560 RK3328_GMAC_RMII_MODE_CLR |
561 RK3328_GMAC_RXCLK_DLY_ENABLE |
562 RK3328_GMAC_TXCLK_DLY_ENABLE);
563
564 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
565 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
566 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
567 }
568
rk3328_set_to_rmii(struct rk_priv_data * bsp_priv)569 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
570 {
571 unsigned int reg;
572
573 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
574 RK3328_GRF_MAC_CON1;
575
576 regmap_write(bsp_priv->grf, reg,
577 RK3328_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
578 RK3328_GMAC_RMII_MODE);
579 }
580
581 static const struct rk_reg_speed_data rk3328_reg_speed_data = {
582 .rgmii_10 = RK3328_GMAC_CLK_2_5M,
583 .rgmii_100 = RK3328_GMAC_CLK_25M,
584 .rgmii_1000 = RK3328_GMAC_CLK_125M,
585 .rmii_10 = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_SPEED_10M,
586 .rmii_100 = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_SPEED_100M,
587 };
588
rk3328_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)589 static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
590 phy_interface_t interface, int speed)
591 {
592 unsigned int reg;
593
594 if (interface == PHY_INTERFACE_MODE_RMII && bsp_priv->integrated_phy)
595 reg = RK3328_GRF_MAC_CON2;
596 else
597 reg = RK3328_GRF_MAC_CON1;
598
599 return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data, reg,
600 interface, speed);
601 }
602
rk3328_integrated_phy_powerup(struct rk_priv_data * priv)603 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
604 {
605 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
606 RK3328_MACPHY_RMII_MODE);
607
608 rk_gmac_integrated_ephy_powerup(priv);
609 }
610
611 static const struct rk_gmac_ops rk3328_ops = {
612 .set_to_rgmii = rk3328_set_to_rgmii,
613 .set_to_rmii = rk3328_set_to_rmii,
614 .set_speed = rk3328_set_speed,
615 .integrated_phy_powerup = rk3328_integrated_phy_powerup,
616 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
617 };
618
619 #define RK3366_GRF_SOC_CON6 0x0418
620 #define RK3366_GRF_SOC_CON7 0x041c
621
622 /* RK3366_GRF_SOC_CON6 */
623 #define RK3366_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
624 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
625 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
626 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
627 #define RK3366_GMAC_SPEED_100M GRF_BIT(7)
628 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
629 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
630 #define RK3366_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
631 #define RK3366_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
632 #define RK3366_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
633 #define RK3366_GMAC_RMII_MODE GRF_BIT(6)
634 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
635
636 /* RK3366_GRF_SOC_CON7 */
637 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
638 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
639 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
640 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
641 #define RK3366_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
642 #define RK3366_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
643
rk3366_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)644 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
645 int tx_delay, int rx_delay)
646 {
647 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
648 RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
649 RK3366_GMAC_RMII_MODE_CLR);
650 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
651 DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
652 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
653 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
654 }
655
rk3366_set_to_rmii(struct rk_priv_data * bsp_priv)656 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
657 {
658 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
659 RK3366_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
660 RK3366_GMAC_RMII_MODE);
661 }
662
663 static const struct rk_reg_speed_data rk3366_reg_speed_data = {
664 .rgmii_10 = RK3366_GMAC_CLK_2_5M,
665 .rgmii_100 = RK3366_GMAC_CLK_25M,
666 .rgmii_1000 = RK3366_GMAC_CLK_125M,
667 .rmii_10 = RK3366_GMAC_RMII_CLK_2_5M | RK3366_GMAC_SPEED_10M,
668 .rmii_100 = RK3366_GMAC_RMII_CLK_25M | RK3366_GMAC_SPEED_100M,
669 };
670
rk3366_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)671 static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
672 phy_interface_t interface, int speed)
673 {
674 return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data,
675 RK3366_GRF_SOC_CON6, interface, speed);
676 }
677
678 static const struct rk_gmac_ops rk3366_ops = {
679 .set_to_rgmii = rk3366_set_to_rgmii,
680 .set_to_rmii = rk3366_set_to_rmii,
681 .set_speed = rk3366_set_speed,
682 };
683
684 #define RK3368_GRF_SOC_CON15 0x043c
685 #define RK3368_GRF_SOC_CON16 0x0440
686
687 /* RK3368_GRF_SOC_CON15 */
688 #define RK3368_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
689 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
690 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
691 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
692 #define RK3368_GMAC_SPEED_100M GRF_BIT(7)
693 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
694 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
695 #define RK3368_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
696 #define RK3368_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
697 #define RK3368_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
698 #define RK3368_GMAC_RMII_MODE GRF_BIT(6)
699 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
700
701 /* RK3368_GRF_SOC_CON16 */
702 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
703 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
704 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
705 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
706 #define RK3368_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
707 #define RK3368_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
708
rk3368_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)709 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
710 int tx_delay, int rx_delay)
711 {
712 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
713 RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
714 RK3368_GMAC_RMII_MODE_CLR);
715 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
716 DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
717 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
718 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
719 }
720
rk3368_set_to_rmii(struct rk_priv_data * bsp_priv)721 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
722 {
723 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
724 RK3368_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
725 RK3368_GMAC_RMII_MODE);
726 }
727
728 static const struct rk_reg_speed_data rk3368_reg_speed_data = {
729 .rgmii_10 = RK3368_GMAC_CLK_2_5M,
730 .rgmii_100 = RK3368_GMAC_CLK_25M,
731 .rgmii_1000 = RK3368_GMAC_CLK_125M,
732 .rmii_10 = RK3368_GMAC_RMII_CLK_2_5M | RK3368_GMAC_SPEED_10M,
733 .rmii_100 = RK3368_GMAC_RMII_CLK_25M | RK3368_GMAC_SPEED_100M,
734 };
735
rk3368_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)736 static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
737 phy_interface_t interface, int speed)
738 {
739 return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data,
740 RK3368_GRF_SOC_CON15, interface, speed);
741 }
742
743 static const struct rk_gmac_ops rk3368_ops = {
744 .set_to_rgmii = rk3368_set_to_rgmii,
745 .set_to_rmii = rk3368_set_to_rmii,
746 .set_speed = rk3368_set_speed,
747 };
748
749 #define RK3399_GRF_SOC_CON5 0xc214
750 #define RK3399_GRF_SOC_CON6 0xc218
751
752 /* RK3399_GRF_SOC_CON5 */
753 #define RK3399_GMAC_PHY_INTF_SEL(val) GRF_FIELD(11, 9, val)
754 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
755 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
756 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
757 #define RK3399_GMAC_SPEED_100M GRF_BIT(7)
758 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
759 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
760 #define RK3399_GMAC_CLK_125M GRF_FIELD_CONST(5, 4, 0)
761 #define RK3399_GMAC_CLK_25M GRF_FIELD_CONST(5, 4, 3)
762 #define RK3399_GMAC_CLK_2_5M GRF_FIELD_CONST(5, 4, 2)
763 #define RK3399_GMAC_RMII_MODE GRF_BIT(6)
764 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
765
766 /* RK3399_GRF_SOC_CON6 */
767 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
768 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
769 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
770 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
771 #define RK3399_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
772 #define RK3399_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
773
rk3399_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)774 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
775 int tx_delay, int rx_delay)
776 {
777 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
778 RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
779 RK3399_GMAC_RMII_MODE_CLR);
780 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
781 DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
782 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
783 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
784 }
785
rk3399_set_to_rmii(struct rk_priv_data * bsp_priv)786 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
787 {
788 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
789 RK3399_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII) |
790 RK3399_GMAC_RMII_MODE);
791 }
792
793 static const struct rk_reg_speed_data rk3399_reg_speed_data = {
794 .rgmii_10 = RK3399_GMAC_CLK_2_5M,
795 .rgmii_100 = RK3399_GMAC_CLK_25M,
796 .rgmii_1000 = RK3399_GMAC_CLK_125M,
797 .rmii_10 = RK3399_GMAC_RMII_CLK_2_5M | RK3399_GMAC_SPEED_10M,
798 .rmii_100 = RK3399_GMAC_RMII_CLK_25M | RK3399_GMAC_SPEED_100M,
799 };
800
rk3399_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)801 static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
802 phy_interface_t interface, int speed)
803 {
804 return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data,
805 RK3399_GRF_SOC_CON5, interface, speed);
806 }
807
808 static const struct rk_gmac_ops rk3399_ops = {
809 .set_to_rgmii = rk3399_set_to_rgmii,
810 .set_to_rmii = rk3399_set_to_rmii,
811 .set_speed = rk3399_set_speed,
812 };
813
814 #define RK3506_GRF_SOC_CON8 0x0020
815 #define RK3506_GRF_SOC_CON11 0x002c
816
817 #define RK3506_GMAC_RMII_MODE GRF_BIT(1)
818
819 #define RK3506_GMAC_CLK_RMII_DIV2 GRF_BIT(3)
820 #define RK3506_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(3)
821
822 #define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5)
823 #define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5)
824
825 #define RK3506_GMAC_CLK_RMII_GATE GRF_BIT(2)
826 #define RK3506_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(2)
827
rk3506_set_to_rmii(struct rk_priv_data * bsp_priv)828 static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
829 {
830 unsigned int id = bsp_priv->id, offset;
831
832 offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8;
833 regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
834 }
835
836 static const struct rk_reg_speed_data rk3506_reg_speed_data = {
837 .rmii_10 = RK3506_GMAC_CLK_RMII_DIV20,
838 .rmii_100 = RK3506_GMAC_CLK_RMII_DIV2,
839 };
840
rk3506_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)841 static int rk3506_set_speed(struct rk_priv_data *bsp_priv,
842 phy_interface_t interface, int speed)
843 {
844 unsigned int id = bsp_priv->id, offset;
845
846 offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8;
847 return rk_set_reg_speed(bsp_priv, &rk3506_reg_speed_data,
848 offset, interface, speed);
849 }
850
rk3506_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)851 static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
852 bool input, bool enable)
853 {
854 unsigned int value, offset, id = bsp_priv->id;
855
856 offset = (id == 1) ? RK3506_GRF_SOC_CON11 : RK3506_GRF_SOC_CON8;
857
858 value = input ? RK3506_GMAC_CLK_SELECT_IO :
859 RK3506_GMAC_CLK_SELECT_CRU;
860 value |= enable ? RK3506_GMAC_CLK_RMII_NOGATE :
861 RK3506_GMAC_CLK_RMII_GATE;
862 regmap_write(bsp_priv->grf, offset, value);
863 }
864
865 static const struct rk_gmac_ops rk3506_ops = {
866 .set_to_rmii = rk3506_set_to_rmii,
867 .set_speed = rk3506_set_speed,
868 .set_clock_selection = rk3506_set_clock_selection,
869 .regs_valid = true,
870 .regs = {
871 0xff4c8000, /* gmac0 */
872 0xff4d0000, /* gmac1 */
873 0x0, /* sentinel */
874 },
875 };
876
877 #define RK3528_VO_GRF_GMAC_CON 0x0018
878 #define RK3528_VO_GRF_MACPHY_CON0 0x001c
879 #define RK3528_VO_GRF_MACPHY_CON1 0x0020
880 #define RK3528_VPU_GRF_GMAC_CON5 0x0018
881 #define RK3528_VPU_GRF_GMAC_CON6 0x001c
882
883 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
884 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
885 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
886 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
887
888 #define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
889 #define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
890
891 #define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
892 #define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
893 #define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
894
895 #define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
896 #define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
897
898 #define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
899 #define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
900 #define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
901 #define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
902
903 #define RK3528_GMAC1_CLK_RGMII_DIV1 GRF_FIELD_CONST(11, 10, 0)
904 #define RK3528_GMAC1_CLK_RGMII_DIV5 GRF_FIELD_CONST(11, 10, 3)
905 #define RK3528_GMAC1_CLK_RGMII_DIV50 GRF_FIELD_CONST(11, 10, 2)
906
907 #define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
908 #define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
909 #define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
910 #define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
911
rk3528_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)912 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
913 int tx_delay, int rx_delay)
914 {
915 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
916 RK3528_GMAC1_PHY_INTF_SEL_RGMII);
917
918 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
919 DELAY_ENABLE(RK3528, tx_delay, rx_delay));
920
921 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
922 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
923 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
924 }
925
rk3528_set_to_rmii(struct rk_priv_data * bsp_priv)926 static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
927 {
928 if (bsp_priv->id == 1)
929 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
930 RK3528_GMAC1_PHY_INTF_SEL_RMII);
931 else
932 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
933 RK3528_GMAC0_PHY_INTF_SEL_RMII |
934 RK3528_GMAC0_CLK_RMII_DIV2);
935 }
936
937 static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = {
938 .rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20,
939 .rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2,
940 };
941
942 static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = {
943 .rgmii_10 = RK3528_GMAC1_CLK_RGMII_DIV50,
944 .rgmii_100 = RK3528_GMAC1_CLK_RGMII_DIV5,
945 .rgmii_1000 = RK3528_GMAC1_CLK_RGMII_DIV1,
946 .rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20,
947 .rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2,
948 };
949
rk3528_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)950 static int rk3528_set_speed(struct rk_priv_data *bsp_priv,
951 phy_interface_t interface, int speed)
952 {
953 const struct rk_reg_speed_data *rsd;
954 unsigned int reg;
955
956 if (bsp_priv->id == 1) {
957 rsd = &rk3528_gmac1_reg_speed_data;
958 reg = RK3528_VPU_GRF_GMAC_CON5;
959 } else {
960 rsd = &rk3528_gmac0_reg_speed_data;
961 reg = RK3528_VO_GRF_GMAC_CON;
962 }
963
964 return rk_set_reg_speed(bsp_priv, rsd, reg, interface, speed);
965 }
966
rk3528_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)967 static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
968 bool input, bool enable)
969 {
970 unsigned int val;
971
972 if (bsp_priv->id == 1) {
973 val = input ? RK3528_GMAC1_CLK_SELECT_IO :
974 RK3528_GMAC1_CLK_SELECT_CRU;
975 val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
976 RK3528_GMAC1_CLK_RMII_GATE;
977 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
978 } else {
979 val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
980 RK3528_GMAC0_CLK_RMII_GATE;
981 regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);
982 }
983 }
984
rk3528_integrated_phy_powerup(struct rk_priv_data * bsp_priv)985 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
986 {
987 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
988 }
989
rk3528_integrated_phy_powerdown(struct rk_priv_data * bsp_priv)990 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
991 {
992 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
993 }
994
995 static const struct rk_gmac_ops rk3528_ops = {
996 .set_to_rgmii = rk3528_set_to_rgmii,
997 .set_to_rmii = rk3528_set_to_rmii,
998 .set_speed = rk3528_set_speed,
999 .set_clock_selection = rk3528_set_clock_selection,
1000 .integrated_phy_powerup = rk3528_integrated_phy_powerup,
1001 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
1002 .regs_valid = true,
1003 .regs = {
1004 0xffbd0000, /* gmac0 */
1005 0xffbe0000, /* gmac1 */
1006 0x0, /* sentinel */
1007 },
1008 };
1009
1010 #define RK3568_GRF_GMAC0_CON0 0x0380
1011 #define RK3568_GRF_GMAC0_CON1 0x0384
1012 #define RK3568_GRF_GMAC1_CON0 0x0388
1013 #define RK3568_GRF_GMAC1_CON1 0x038c
1014
1015 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1016 #define RK3568_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
1017 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
1018 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1019 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
1020 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1021 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
1022 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1023
1024 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1025 #define RK3568_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
1026 #define RK3568_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
1027
rk3568_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1028 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1029 int tx_delay, int rx_delay)
1030 {
1031 u32 con0, con1;
1032
1033 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1034 RK3568_GRF_GMAC0_CON0;
1035 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1036 RK3568_GRF_GMAC0_CON1;
1037
1038 regmap_write(bsp_priv->grf, con0,
1039 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1040 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1041
1042 regmap_write(bsp_priv->grf, con1,
1043 RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
1044 RK3568_GMAC_RXCLK_DLY_ENABLE |
1045 RK3568_GMAC_TXCLK_DLY_ENABLE);
1046 }
1047
rk3568_set_to_rmii(struct rk_priv_data * bsp_priv)1048 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1049 {
1050 u32 con1;
1051
1052 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1053 RK3568_GRF_GMAC0_CON1;
1054 regmap_write(bsp_priv->grf, con1,
1055 RK3568_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
1056 }
1057
1058 static const struct rk_gmac_ops rk3568_ops = {
1059 .set_to_rgmii = rk3568_set_to_rgmii,
1060 .set_to_rmii = rk3568_set_to_rmii,
1061 .set_speed = rk_set_clk_mac_speed,
1062 .regs_valid = true,
1063 .regs = {
1064 0xfe2a0000, /* gmac0 */
1065 0xfe010000, /* gmac1 */
1066 0x0, /* sentinel */
1067 },
1068 };
1069
1070 /* VCCIO0_1_3_IOC */
1071 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408
1072 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c
1073 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410
1074 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414
1075
1076 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
1077 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
1078 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
1079 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
1080
1081 #define RK3576_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
1082 #define RK3576_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
1083
1084 /* SDGMAC_GRF */
1085 #define RK3576_GRF_GMAC_CON0 0X0020
1086 #define RK3576_GRF_GMAC_CON1 0X0024
1087
1088 #define RK3576_GMAC_RMII_MODE GRF_BIT(3)
1089 #define RK3576_GMAC_RGMII_MODE GRF_CLR_BIT(3)
1090
1091 #define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
1092 #define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
1093
1094 #define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
1095 #define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
1096
1097 #define RK3576_GMAC_CLK_RGMII_DIV1 GRF_FIELD_CONST(6, 5, 0)
1098 #define RK3576_GMAC_CLK_RGMII_DIV5 GRF_FIELD_CONST(6, 5, 3)
1099 #define RK3576_GMAC_CLK_RGMII_DIV50 GRF_FIELD_CONST(6, 5, 2)
1100
1101 #define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
1102 #define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
1103
rk3576_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1104 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
1105 int tx_delay, int rx_delay)
1106 {
1107 unsigned int offset_con;
1108
1109 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1110 RK3576_GRF_GMAC_CON0;
1111
1112 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RGMII_MODE);
1113
1114 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
1115 RK3576_VCCIO0_1_3_IOC_CON2;
1116
1117 /* m0 && m1 delay enabled */
1118 regmap_write(bsp_priv->php_grf, offset_con,
1119 DELAY_ENABLE(RK3576, tx_delay, rx_delay));
1120 regmap_write(bsp_priv->php_grf, offset_con + 0x4,
1121 DELAY_ENABLE(RK3576, tx_delay, rx_delay));
1122
1123 /* m0 && m1 delay value */
1124 regmap_write(bsp_priv->php_grf, offset_con,
1125 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
1126 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
1127 regmap_write(bsp_priv->php_grf, offset_con + 0x4,
1128 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
1129 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
1130 }
1131
rk3576_set_to_rmii(struct rk_priv_data * bsp_priv)1132 static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
1133 {
1134 unsigned int offset_con;
1135
1136 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1137 RK3576_GRF_GMAC_CON0;
1138
1139 regmap_write(bsp_priv->grf, offset_con, RK3576_GMAC_RMII_MODE);
1140 }
1141
1142 static const struct rk_reg_speed_data rk3578_reg_speed_data = {
1143 .rgmii_10 = RK3576_GMAC_CLK_RGMII_DIV50,
1144 .rgmii_100 = RK3576_GMAC_CLK_RGMII_DIV5,
1145 .rgmii_1000 = RK3576_GMAC_CLK_RGMII_DIV1,
1146 .rmii_10 = RK3576_GMAC_CLK_RMII_DIV20,
1147 .rmii_100 = RK3576_GMAC_CLK_RMII_DIV2,
1148 };
1149
rk3576_set_gmac_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)1150 static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv,
1151 phy_interface_t interface, int speed)
1152 {
1153 unsigned int offset_con;
1154
1155 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1156 RK3576_GRF_GMAC_CON0;
1157
1158 return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data, offset_con,
1159 interface, speed);
1160 }
1161
rk3576_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1162 static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1163 bool enable)
1164 {
1165 unsigned int val = input ? RK3576_GMAC_CLK_SELECT_IO :
1166 RK3576_GMAC_CLK_SELECT_CRU;
1167 unsigned int offset_con;
1168
1169 val |= enable ? RK3576_GMAC_CLK_RMII_NOGATE :
1170 RK3576_GMAC_CLK_RMII_GATE;
1171
1172 offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
1173 RK3576_GRF_GMAC_CON0;
1174
1175 regmap_write(bsp_priv->grf, offset_con, val);
1176 }
1177
1178 static const struct rk_gmac_ops rk3576_ops = {
1179 .set_to_rgmii = rk3576_set_to_rgmii,
1180 .set_to_rmii = rk3576_set_to_rmii,
1181 .set_speed = rk3576_set_gmac_speed,
1182 .set_clock_selection = rk3576_set_clock_selection,
1183 .php_grf_required = true,
1184 .regs_valid = true,
1185 .regs = {
1186 0x2a220000, /* gmac0 */
1187 0x2a230000, /* gmac1 */
1188 0x0, /* sentinel */
1189 },
1190 };
1191
1192 /* sys_grf */
1193 #define RK3588_GRF_GMAC_CON7 0X031c
1194 #define RK3588_GRF_GMAC_CON8 0X0320
1195 #define RK3588_GRF_GMAC_CON9 0X0324
1196
1197 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
1198 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
1199 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
1200 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
1201
1202 #define RK3588_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
1203 #define RK3588_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
1204
1205 /* php_grf */
1206 #define RK3588_GRF_GMAC_CON0 0X0008
1207 #define RK3588_GRF_CLK_CON1 0X0070
1208
1209 #define RK3588_GMAC_PHY_INTF_SEL(id, val) \
1210 (GRF_FIELD(5, 3, val) << ((id) * 6))
1211
1212 #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id))
1213 #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id))
1214
1215 #define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4)
1216 #define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4)
1217
1218 #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
1219 #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
1220
1221 #define RK3588_GMAC_CLK_RGMII_DIV1(id) \
1222 (GRF_FIELD_CONST(3, 2, 0) << ((id) * 5))
1223 #define RK3588_GMAC_CLK_RGMII_DIV5(id) \
1224 (GRF_FIELD_CONST(3, 2, 3) << ((id) * 5))
1225 #define RK3588_GMAC_CLK_RGMII_DIV50(id) \
1226 (GRF_FIELD_CONST(3, 2, 2) << ((id) * 5))
1227
1228 #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
1229 #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
1230
rk3588_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1231 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1232 int tx_delay, int rx_delay)
1233 {
1234 u32 offset_con, id = bsp_priv->id;
1235
1236 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
1237 RK3588_GRF_GMAC_CON8;
1238
1239 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1240 RK3588_GMAC_PHY_INTF_SEL(id, PHY_INTF_SEL_RGMII));
1241
1242 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1243 RK3588_GMAC_CLK_RGMII_MODE(id));
1244
1245 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1246 RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
1247 RK3588_GMAC_TXCLK_DLY_ENABLE(id));
1248
1249 regmap_write(bsp_priv->grf, offset_con,
1250 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
1251 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
1252 }
1253
rk3588_set_to_rmii(struct rk_priv_data * bsp_priv)1254 static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
1255 {
1256 regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
1257 RK3588_GMAC_PHY_INTF_SEL(bsp_priv->id, PHY_INTF_SEL_RMII));
1258
1259 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1,
1260 RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
1261 }
1262
rk3588_set_gmac_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)1263 static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv,
1264 phy_interface_t interface, int speed)
1265 {
1266 unsigned int val = 0, id = bsp_priv->id;
1267
1268 switch (speed) {
1269 case 10:
1270 if (interface == PHY_INTERFACE_MODE_RMII)
1271 val = RK3588_GMA_CLK_RMII_DIV20(id);
1272 else
1273 val = RK3588_GMAC_CLK_RGMII_DIV50(id);
1274 break;
1275 case 100:
1276 if (interface == PHY_INTERFACE_MODE_RMII)
1277 val = RK3588_GMA_CLK_RMII_DIV2(id);
1278 else
1279 val = RK3588_GMAC_CLK_RGMII_DIV5(id);
1280 break;
1281 case 1000:
1282 if (interface != PHY_INTERFACE_MODE_RMII)
1283 val = RK3588_GMAC_CLK_RGMII_DIV1(id);
1284 else
1285 goto err;
1286 break;
1287 default:
1288 goto err;
1289 }
1290
1291 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1292
1293 return 0;
1294 err:
1295 return -EINVAL;
1296 }
1297
rk3588_set_clock_selection(struct rk_priv_data * bsp_priv,bool input,bool enable)1298 static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
1299 bool enable)
1300 {
1301 unsigned int val = input ? RK3588_GMAC_CLK_SELECT_IO(bsp_priv->id) :
1302 RK3588_GMAC_CLK_SELECT_CRU(bsp_priv->id);
1303
1304 val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) :
1305 RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id);
1306
1307 regmap_write(bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val);
1308 }
1309
1310 static const struct rk_gmac_ops rk3588_ops = {
1311 .set_to_rgmii = rk3588_set_to_rgmii,
1312 .set_to_rmii = rk3588_set_to_rmii,
1313 .set_speed = rk3588_set_gmac_speed,
1314 .set_clock_selection = rk3588_set_clock_selection,
1315 .php_grf_required = true,
1316 .regs_valid = true,
1317 .regs = {
1318 0xfe1b0000, /* gmac0 */
1319 0xfe1c0000, /* gmac1 */
1320 0x0, /* sentinel */
1321 },
1322 };
1323
1324 #define RV1108_GRF_GMAC_CON0 0X0900
1325
1326 /* RV1108_GRF_GMAC_CON0 */
1327 #define RV1108_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
1328 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
1329 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1330 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
1331 #define RV1108_GMAC_SPEED_100M GRF_BIT(2)
1332 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
1333 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
1334
rv1108_set_to_rmii(struct rk_priv_data * bsp_priv)1335 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1336 {
1337 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1338 RV1108_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
1339 }
1340
1341 static const struct rk_reg_speed_data rv1108_reg_speed_data = {
1342 .rmii_10 = RV1108_GMAC_RMII_CLK_2_5M | RV1108_GMAC_SPEED_10M,
1343 .rmii_100 = RV1108_GMAC_RMII_CLK_25M | RV1108_GMAC_SPEED_100M,
1344 };
1345
rv1108_set_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)1346 static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
1347 phy_interface_t interface, int speed)
1348 {
1349 return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data,
1350 RV1108_GRF_GMAC_CON0, interface, speed);
1351 }
1352
1353 static const struct rk_gmac_ops rv1108_ops = {
1354 .set_to_rmii = rv1108_set_to_rmii,
1355 .set_speed = rv1108_set_speed,
1356 };
1357
1358 #define RV1126_GRF_GMAC_CON0 0X0070
1359 #define RV1126_GRF_GMAC_CON1 0X0074
1360 #define RV1126_GRF_GMAC_CON2 0X0078
1361
1362 /* RV1126_GRF_GMAC_CON0 */
1363 #define RV1126_GMAC_PHY_INTF_SEL(val) GRF_FIELD(6, 4, val)
1364 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
1365 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
1366 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
1367 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1368 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0)
1369 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1370 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3)
1371 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
1372 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2)
1373 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
1374
1375 /* RV1126_GRF_GMAC_CON1 */
1376 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
1377 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
1378 /* RV1126_GRF_GMAC_CON2 */
1379 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
1380 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
1381
rv1126_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1382 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
1383 int tx_delay, int rx_delay)
1384 {
1385 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1386 RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RGMII) |
1387 RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1388 RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1389 RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1390 RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
1391
1392 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1393 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1394 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
1395
1396 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1397 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1398 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
1399 }
1400
rv1126_set_to_rmii(struct rk_priv_data * bsp_priv)1401 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
1402 {
1403 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1404 RV1126_GMAC_PHY_INTF_SEL(PHY_INTF_SEL_RMII));
1405 }
1406
1407 static const struct rk_gmac_ops rv1126_ops = {
1408 .set_to_rgmii = rv1126_set_to_rgmii,
1409 .set_to_rmii = rv1126_set_to_rmii,
1410 .set_speed = rk_set_clk_mac_speed,
1411 };
1412
rk_gmac_clk_init(struct plat_stmmacenet_data * plat)1413 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1414 {
1415 struct rk_priv_data *bsp_priv = plat->bsp_priv;
1416 int phy_iface = bsp_priv->phy_iface;
1417 struct device *dev = bsp_priv->dev;
1418 int i, j, ret;
1419
1420 bsp_priv->clk_enabled = false;
1421
1422 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks);
1423 if (phy_iface == PHY_INTERFACE_MODE_RMII)
1424 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks);
1425
1426 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks,
1427 sizeof(*bsp_priv->clks), GFP_KERNEL);
1428 if (!bsp_priv->clks)
1429 return -ENOMEM;
1430
1431 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++)
1432 bsp_priv->clks[i].id = rk_clocks[i];
1433
1434 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1435 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++)
1436 bsp_priv->clks[i++].id = rk_rmii_clocks[j];
1437 }
1438
1439 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks,
1440 bsp_priv->clks);
1441 if (ret)
1442 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1443
1444 if (bsp_priv->clock_input) {
1445 dev_info(dev, "clock input from PHY\n");
1446 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1447 clk_set_rate(plat->stmmac_clk, 50000000);
1448 }
1449
1450 if (plat->phy_node && bsp_priv->integrated_phy) {
1451 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1452 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
1453 if (ret)
1454 return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
1455 clk_set_rate(bsp_priv->clk_phy, 50000000);
1456 }
1457
1458 return 0;
1459 }
1460
gmac_clk_enable(struct rk_priv_data * bsp_priv,bool enable)1461 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1462 {
1463 int ret;
1464
1465 if (enable) {
1466 if (!bsp_priv->clk_enabled) {
1467 ret = clk_bulk_prepare_enable(bsp_priv->num_clks,
1468 bsp_priv->clks);
1469 if (ret)
1470 return ret;
1471
1472 ret = clk_prepare_enable(bsp_priv->clk_phy);
1473 if (ret)
1474 return ret;
1475
1476 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1477 bsp_priv->ops->set_clock_selection(bsp_priv,
1478 bsp_priv->clock_input, true);
1479
1480 mdelay(5);
1481 bsp_priv->clk_enabled = true;
1482 }
1483 } else {
1484 if (bsp_priv->clk_enabled) {
1485 if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) {
1486 bsp_priv->ops->set_clock_selection(bsp_priv,
1487 bsp_priv->clock_input, false);
1488 }
1489
1490 clk_bulk_disable_unprepare(bsp_priv->num_clks,
1491 bsp_priv->clks);
1492 clk_disable_unprepare(bsp_priv->clk_phy);
1493
1494 bsp_priv->clk_enabled = false;
1495 }
1496 }
1497
1498 return 0;
1499 }
1500
phy_power_on(struct rk_priv_data * bsp_priv,bool enable)1501 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1502 {
1503 struct regulator *ldo = bsp_priv->regulator;
1504 struct device *dev = bsp_priv->dev;
1505 int ret;
1506
1507 if (enable) {
1508 ret = regulator_enable(ldo);
1509 if (ret)
1510 dev_err(dev, "fail to enable phy-supply\n");
1511 } else {
1512 ret = regulator_disable(ldo);
1513 if (ret)
1514 dev_err(dev, "fail to disable phy-supply\n");
1515 }
1516
1517 return 0;
1518 }
1519
rk_gmac_setup(struct platform_device * pdev,struct plat_stmmacenet_data * plat,const struct rk_gmac_ops * ops)1520 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1521 struct plat_stmmacenet_data *plat,
1522 const struct rk_gmac_ops *ops)
1523 {
1524 struct rk_priv_data *bsp_priv;
1525 struct device *dev = &pdev->dev;
1526 struct resource *res;
1527 int ret;
1528 const char *strings = NULL;
1529 int value;
1530
1531 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1532 if (!bsp_priv)
1533 return ERR_PTR(-ENOMEM);
1534
1535 bsp_priv->phy_iface = plat->phy_interface;
1536 bsp_priv->ops = ops;
1537
1538 /* Some SoCs have multiple MAC controllers, which need
1539 * to be distinguished.
1540 */
1541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1542 if (res && ops->regs_valid) {
1543 int i = 0;
1544
1545 while (ops->regs[i]) {
1546 if (ops->regs[i] == res->start) {
1547 bsp_priv->id = i;
1548 break;
1549 }
1550 i++;
1551 }
1552 }
1553
1554 bsp_priv->regulator = devm_regulator_get(dev, "phy");
1555 if (IS_ERR(bsp_priv->regulator)) {
1556 ret = PTR_ERR(bsp_priv->regulator);
1557 dev_err_probe(dev, ret, "failed to get phy regulator\n");
1558 return ERR_PTR(ret);
1559 }
1560
1561 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1562 if (ret) {
1563 dev_err(dev, "Can not read property: clock_in_out.\n");
1564 bsp_priv->clock_input = true;
1565 } else {
1566 dev_info(dev, "clock input or output? (%s).\n",
1567 strings);
1568 if (!strcmp(strings, "input"))
1569 bsp_priv->clock_input = true;
1570 else
1571 bsp_priv->clock_input = false;
1572 }
1573
1574 ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1575 if (ret) {
1576 bsp_priv->tx_delay = 0x30;
1577 dev_err(dev, "Can not read property: tx_delay.");
1578 dev_err(dev, "set tx_delay to 0x%x\n",
1579 bsp_priv->tx_delay);
1580 } else {
1581 dev_info(dev, "TX delay(0x%x).\n", value);
1582 bsp_priv->tx_delay = value;
1583 }
1584
1585 ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1586 if (ret) {
1587 bsp_priv->rx_delay = 0x10;
1588 dev_err(dev, "Can not read property: rx_delay.");
1589 dev_err(dev, "set rx_delay to 0x%x\n",
1590 bsp_priv->rx_delay);
1591 } else {
1592 dev_info(dev, "RX delay(0x%x).\n", value);
1593 bsp_priv->rx_delay = value;
1594 }
1595
1596 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1597 "rockchip,grf");
1598 if (IS_ERR(bsp_priv->grf)) {
1599 dev_err_probe(dev, PTR_ERR(bsp_priv->grf),
1600 "failed to lookup rockchip,grf\n");
1601 return ERR_CAST(bsp_priv->grf);
1602 }
1603
1604 if (ops->php_grf_required) {
1605 bsp_priv->php_grf =
1606 syscon_regmap_lookup_by_phandle(dev->of_node,
1607 "rockchip,php-grf");
1608 if (IS_ERR(bsp_priv->php_grf)) {
1609 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf),
1610 "failed to lookup rockchip,php-grf\n");
1611 return ERR_CAST(bsp_priv->php_grf);
1612 }
1613 }
1614
1615 if (plat->phy_node) {
1616 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1617 "phy-is-integrated");
1618 if (bsp_priv->integrated_phy) {
1619 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1620 if (IS_ERR(bsp_priv->phy_reset)) {
1621 dev_err(&pdev->dev, "No PHY reset control found.\n");
1622 bsp_priv->phy_reset = NULL;
1623 }
1624 }
1625 }
1626 dev_info(dev, "integrated PHY? (%s).\n",
1627 bsp_priv->integrated_phy ? "yes" : "no");
1628
1629 bsp_priv->dev = dev;
1630
1631 return bsp_priv;
1632 }
1633
rk_gmac_check_ops(struct rk_priv_data * bsp_priv)1634 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1635 {
1636 switch (bsp_priv->phy_iface) {
1637 case PHY_INTERFACE_MODE_RGMII:
1638 case PHY_INTERFACE_MODE_RGMII_ID:
1639 case PHY_INTERFACE_MODE_RGMII_RXID:
1640 case PHY_INTERFACE_MODE_RGMII_TXID:
1641 if (!bsp_priv->ops->set_to_rgmii)
1642 return -EINVAL;
1643 break;
1644 case PHY_INTERFACE_MODE_RMII:
1645 if (!bsp_priv->ops->set_to_rmii)
1646 return -EINVAL;
1647 break;
1648 default:
1649 dev_err(bsp_priv->dev,
1650 "unsupported interface %d", bsp_priv->phy_iface);
1651 }
1652 return 0;
1653 }
1654
rk_gmac_powerup(struct rk_priv_data * bsp_priv)1655 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1656 {
1657 struct device *dev = bsp_priv->dev;
1658 int ret;
1659
1660 ret = rk_gmac_check_ops(bsp_priv);
1661 if (ret)
1662 return ret;
1663
1664 ret = gmac_clk_enable(bsp_priv, true);
1665 if (ret)
1666 return ret;
1667
1668 /*rmii or rgmii*/
1669 switch (bsp_priv->phy_iface) {
1670 case PHY_INTERFACE_MODE_RGMII:
1671 dev_info(dev, "init for RGMII\n");
1672 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1673 bsp_priv->rx_delay);
1674 break;
1675 case PHY_INTERFACE_MODE_RGMII_ID:
1676 dev_info(dev, "init for RGMII_ID\n");
1677 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1678 break;
1679 case PHY_INTERFACE_MODE_RGMII_RXID:
1680 dev_info(dev, "init for RGMII_RXID\n");
1681 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1682 break;
1683 case PHY_INTERFACE_MODE_RGMII_TXID:
1684 dev_info(dev, "init for RGMII_TXID\n");
1685 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1686 break;
1687 case PHY_INTERFACE_MODE_RMII:
1688 dev_info(dev, "init for RMII\n");
1689 bsp_priv->ops->set_to_rmii(bsp_priv);
1690 break;
1691 default:
1692 dev_err(dev, "NO interface defined!\n");
1693 }
1694
1695 ret = phy_power_on(bsp_priv, true);
1696 if (ret) {
1697 gmac_clk_enable(bsp_priv, false);
1698 return ret;
1699 }
1700
1701 pm_runtime_get_sync(dev);
1702
1703 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup)
1704 bsp_priv->ops->integrated_phy_powerup(bsp_priv);
1705
1706 return 0;
1707 }
1708
rk_gmac_powerdown(struct rk_priv_data * gmac)1709 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1710 {
1711 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown)
1712 gmac->ops->integrated_phy_powerdown(gmac);
1713
1714 pm_runtime_put_sync(gmac->dev);
1715
1716 phy_power_on(gmac, false);
1717 gmac_clk_enable(gmac, false);
1718 }
1719
rk_get_interfaces(struct stmmac_priv * priv,void * bsp_priv,unsigned long * interfaces)1720 static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv,
1721 unsigned long *interfaces)
1722 {
1723 struct rk_priv_data *rk = bsp_priv;
1724
1725 if (rk->ops->set_to_rgmii)
1726 phy_interface_set_rgmii(interfaces);
1727
1728 if (rk->ops->set_to_rmii)
1729 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces);
1730 }
1731
rk_set_clk_tx_rate(void * bsp_priv_,struct clk * clk_tx_i,phy_interface_t interface,int speed)1732 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i,
1733 phy_interface_t interface, int speed)
1734 {
1735 struct rk_priv_data *bsp_priv = bsp_priv_;
1736
1737 if (bsp_priv->ops->set_speed)
1738 return bsp_priv->ops->set_speed(bsp_priv, interface, speed);
1739
1740 return -EINVAL;
1741 }
1742
rk_gmac_suspend(struct device * dev,void * bsp_priv_)1743 static int rk_gmac_suspend(struct device *dev, void *bsp_priv_)
1744 {
1745 struct rk_priv_data *bsp_priv = bsp_priv_;
1746
1747 /* Keep the PHY up if we use Wake-on-Lan. */
1748 if (!device_may_wakeup(dev))
1749 rk_gmac_powerdown(bsp_priv);
1750
1751 return 0;
1752 }
1753
rk_gmac_resume(struct device * dev,void * bsp_priv_)1754 static int rk_gmac_resume(struct device *dev, void *bsp_priv_)
1755 {
1756 struct rk_priv_data *bsp_priv = bsp_priv_;
1757
1758 /* The PHY was up for Wake-on-Lan. */
1759 if (!device_may_wakeup(dev))
1760 rk_gmac_powerup(bsp_priv);
1761
1762 return 0;
1763 }
1764
rk_gmac_init(struct device * dev,void * bsp_priv)1765 static int rk_gmac_init(struct device *dev, void *bsp_priv)
1766 {
1767 return rk_gmac_powerup(bsp_priv);
1768 }
1769
rk_gmac_exit(struct device * dev,void * bsp_priv_)1770 static void rk_gmac_exit(struct device *dev, void *bsp_priv_)
1771 {
1772 struct stmmac_priv *priv = netdev_priv(dev_get_drvdata(dev));
1773 struct rk_priv_data *bsp_priv = bsp_priv_;
1774
1775 rk_gmac_powerdown(bsp_priv);
1776
1777 if (priv->plat->phy_node && bsp_priv->integrated_phy)
1778 clk_put(bsp_priv->clk_phy);
1779 }
1780
rk_gmac_probe(struct platform_device * pdev)1781 static int rk_gmac_probe(struct platform_device *pdev)
1782 {
1783 struct plat_stmmacenet_data *plat_dat;
1784 struct stmmac_resources stmmac_res;
1785 const struct rk_gmac_ops *data;
1786 int ret;
1787
1788 data = of_device_get_match_data(&pdev->dev);
1789 if (!data) {
1790 dev_err(&pdev->dev, "no of match data provided\n");
1791 return -EINVAL;
1792 }
1793
1794 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1795 if (ret)
1796 return ret;
1797
1798 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
1799 if (IS_ERR(plat_dat))
1800 return PTR_ERR(plat_dat);
1801
1802 /* If the stmmac is not already selected as gmac4,
1803 * then make sure we fallback to gmac.
1804 */
1805 if (plat_dat->core_type != DWMAC_CORE_GMAC4) {
1806 plat_dat->core_type = DWMAC_CORE_GMAC;
1807 plat_dat->rx_fifo_size = 4096;
1808 plat_dat->tx_fifo_size = 2048;
1809 }
1810
1811 plat_dat->get_interfaces = rk_get_interfaces;
1812 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate;
1813 plat_dat->init = rk_gmac_init;
1814 plat_dat->exit = rk_gmac_exit;
1815 plat_dat->suspend = rk_gmac_suspend;
1816 plat_dat->resume = rk_gmac_resume;
1817
1818 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1819 if (IS_ERR(plat_dat->bsp_priv))
1820 return PTR_ERR(plat_dat->bsp_priv);
1821
1822 ret = rk_gmac_clk_init(plat_dat);
1823 if (ret)
1824 return ret;
1825
1826 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
1827 }
1828
1829 static const struct of_device_id rk_gmac_dwmac_match[] = {
1830 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
1831 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1832 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1833 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1834 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1835 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1836 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1837 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1838 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1839 { .compatible = "rockchip,rk3506-gmac", .data = &rk3506_ops },
1840 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
1841 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1842 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
1843 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
1844 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1845 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
1846 { }
1847 };
1848 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1849
1850 static struct platform_driver rk_gmac_dwmac_driver = {
1851 .probe = rk_gmac_probe,
1852 .driver = {
1853 .name = "rk_gmac-dwmac",
1854 .pm = &stmmac_simple_pm_ops,
1855 .of_match_table = rk_gmac_dwmac_match,
1856 },
1857 };
1858 module_platform_driver(rk_gmac_dwmac_driver);
1859
1860 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1861 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1862 MODULE_LICENSE("GPL");
1863