1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 * Jeffy Chen <jeffy.chen@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "hantro_g1_regs.h"
14 #include "hantro_h1_regs.h"
15 #include "rockchip_vpu2_regs.h"
16 #include "rockchip_vpu981_regs.h"
17
18 #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
19 #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
20 #define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000)
21
22 #define ROCKCHIP_VPU981_MIN_SIZE 64
23
24 /*
25 * Supported formats.
26 */
27
28 static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
29 {
30 .fourcc = V4L2_PIX_FMT_YUV420M,
31 .codec_mode = HANTRO_MODE_NONE,
32 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
33 },
34 {
35 .fourcc = V4L2_PIX_FMT_NV12M,
36 .codec_mode = HANTRO_MODE_NONE,
37 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
38 },
39 {
40 .fourcc = V4L2_PIX_FMT_YUYV,
41 .codec_mode = HANTRO_MODE_NONE,
42 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
43 },
44 {
45 .fourcc = V4L2_PIX_FMT_UYVY,
46 .codec_mode = HANTRO_MODE_NONE,
47 .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
48 },
49 {
50 .fourcc = V4L2_PIX_FMT_JPEG,
51 .codec_mode = HANTRO_MODE_JPEG_ENC,
52 .max_depth = 2,
53 .header_size = JPEG_HEADER_SIZE,
54 .frmsize = {
55 .min_width = 96,
56 .max_width = 8192,
57 .step_width = MB_DIM,
58 .min_height = 32,
59 .max_height = 8192,
60 .step_height = MB_DIM,
61 },
62 },
63 };
64
65 static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
66 {
67 .fourcc = V4L2_PIX_FMT_YUYV,
68 .codec_mode = HANTRO_MODE_NONE,
69 .postprocessed = true,
70 .frmsize = {
71 .min_width = FMT_MIN_WIDTH,
72 .max_width = FMT_FHD_WIDTH,
73 .step_width = MB_DIM,
74 .min_height = FMT_MIN_HEIGHT,
75 .max_height = FMT_FHD_HEIGHT,
76 .step_height = MB_DIM,
77 },
78 },
79 };
80
81 static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
82 {
83 .fourcc = V4L2_PIX_FMT_NV12,
84 .codec_mode = HANTRO_MODE_NONE,
85 .postprocessed = true,
86 .frmsize = {
87 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
88 .max_width = FMT_UHD_WIDTH,
89 .step_width = MB_DIM,
90 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
91 .max_height = FMT_UHD_HEIGHT,
92 .step_height = MB_DIM,
93 },
94 },
95 {
96 .fourcc = V4L2_PIX_FMT_P010,
97 .codec_mode = HANTRO_MODE_NONE,
98 .match_depth = true,
99 .postprocessed = true,
100 .frmsize = {
101 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
102 .max_width = FMT_UHD_WIDTH,
103 .step_width = MB_DIM,
104 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
105 .max_height = FMT_UHD_HEIGHT,
106 .step_height = MB_DIM,
107 },
108 },
109 };
110
111 static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
112 {
113 .fourcc = V4L2_PIX_FMT_NV12,
114 .codec_mode = HANTRO_MODE_NONE,
115 .frmsize = {
116 .min_width = FMT_MIN_WIDTH,
117 .max_width = FMT_FHD_WIDTH,
118 .step_width = MB_DIM,
119 .min_height = FMT_MIN_HEIGHT,
120 .max_height = FMT_FHD_HEIGHT,
121 .step_height = MB_DIM,
122 },
123 },
124 {
125 .fourcc = V4L2_PIX_FMT_H264_SLICE,
126 .codec_mode = HANTRO_MODE_H264_DEC,
127 .max_depth = 2,
128 .frmsize = {
129 .min_width = FMT_MIN_WIDTH,
130 .max_width = FMT_FHD_WIDTH,
131 .step_width = MB_DIM,
132 .min_height = FMT_MIN_HEIGHT,
133 .max_height = FMT_FHD_HEIGHT,
134 .step_height = MB_DIM,
135 },
136 },
137 {
138 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
139 .codec_mode = HANTRO_MODE_MPEG2_DEC,
140 .max_depth = 2,
141 .frmsize = {
142 .min_width = FMT_MIN_WIDTH,
143 .max_width = FMT_FHD_WIDTH,
144 .step_width = MB_DIM,
145 .min_height = FMT_MIN_HEIGHT,
146 .max_height = FMT_FHD_HEIGHT,
147 .step_height = MB_DIM,
148 },
149 },
150 {
151 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
152 .codec_mode = HANTRO_MODE_VP8_DEC,
153 .max_depth = 2,
154 .frmsize = {
155 .min_width = FMT_MIN_WIDTH,
156 .max_width = FMT_FHD_WIDTH,
157 .step_width = MB_DIM,
158 .min_height = FMT_MIN_HEIGHT,
159 .max_height = FMT_FHD_HEIGHT,
160 .step_height = MB_DIM,
161 },
162 },
163 };
164
165 static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
166 {
167 .fourcc = V4L2_PIX_FMT_NV12,
168 .codec_mode = HANTRO_MODE_NONE,
169 .frmsize = {
170 .min_width = FMT_MIN_WIDTH,
171 .max_width = FMT_4K_WIDTH,
172 .step_width = MB_DIM,
173 .min_height = FMT_MIN_HEIGHT,
174 .max_height = FMT_4K_HEIGHT,
175 .step_height = MB_DIM,
176 },
177 },
178 {
179 .fourcc = V4L2_PIX_FMT_H264_SLICE,
180 .codec_mode = HANTRO_MODE_H264_DEC,
181 .max_depth = 2,
182 .frmsize = {
183 .min_width = FMT_MIN_WIDTH,
184 .max_width = FMT_4K_WIDTH,
185 .step_width = MB_DIM,
186 .min_height = FMT_MIN_HEIGHT,
187 .max_height = FMT_4K_HEIGHT,
188 .step_height = MB_DIM,
189 },
190 },
191 {
192 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
193 .codec_mode = HANTRO_MODE_MPEG2_DEC,
194 .max_depth = 2,
195 .frmsize = {
196 .min_width = FMT_MIN_WIDTH,
197 .max_width = FMT_FHD_WIDTH,
198 .step_width = MB_DIM,
199 .min_height = FMT_MIN_HEIGHT,
200 .max_height = FMT_FHD_HEIGHT,
201 .step_height = MB_DIM,
202 },
203 },
204 {
205 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
206 .codec_mode = HANTRO_MODE_VP8_DEC,
207 .max_depth = 2,
208 .frmsize = {
209 .min_width = FMT_MIN_WIDTH,
210 .max_width = FMT_UHD_WIDTH,
211 .step_width = MB_DIM,
212 .min_height = FMT_MIN_HEIGHT,
213 .max_height = FMT_UHD_HEIGHT,
214 .step_height = MB_DIM,
215 },
216 },
217 };
218
219 static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
220 {
221 .fourcc = V4L2_PIX_FMT_NV12,
222 .codec_mode = HANTRO_MODE_NONE,
223 .frmsize = {
224 .min_width = FMT_MIN_WIDTH,
225 .max_width = FMT_FHD_WIDTH,
226 .step_width = MB_DIM,
227 .min_height = FMT_MIN_HEIGHT,
228 .max_height = FMT_FHD_HEIGHT,
229 .step_height = MB_DIM,
230 },
231 },
232 {
233 .fourcc = V4L2_PIX_FMT_H264_SLICE,
234 .codec_mode = HANTRO_MODE_H264_DEC,
235 .max_depth = 2,
236 .frmsize = {
237 .min_width = FMT_MIN_WIDTH,
238 .max_width = FMT_FHD_WIDTH,
239 .step_width = MB_DIM,
240 .min_height = FMT_MIN_HEIGHT,
241 .max_height = FMT_FHD_HEIGHT,
242 .step_height = MB_DIM,
243 },
244 },
245 {
246 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
247 .codec_mode = HANTRO_MODE_MPEG2_DEC,
248 .max_depth = 2,
249 .frmsize = {
250 .min_width = FMT_MIN_WIDTH,
251 .max_width = FMT_FHD_WIDTH,
252 .step_width = MB_DIM,
253 .min_height = FMT_MIN_HEIGHT,
254 .max_height = FMT_FHD_HEIGHT,
255 .step_height = MB_DIM,
256 },
257 },
258 {
259 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
260 .codec_mode = HANTRO_MODE_VP8_DEC,
261 .max_depth = 2,
262 .frmsize = {
263 .min_width = FMT_MIN_WIDTH,
264 .max_width = FMT_UHD_WIDTH,
265 .step_width = MB_DIM,
266 .min_height = FMT_MIN_HEIGHT,
267 .max_height = FMT_UHD_HEIGHT,
268 .step_height = MB_DIM,
269 },
270 },
271 };
272
273 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
274 {
275 .fourcc = V4L2_PIX_FMT_NV12,
276 .codec_mode = HANTRO_MODE_NONE,
277 .frmsize = {
278 .min_width = FMT_MIN_WIDTH,
279 .max_width = FMT_FHD_WIDTH,
280 .step_width = MB_DIM,
281 .min_height = FMT_MIN_HEIGHT,
282 .max_height = FMT_FHD_HEIGHT,
283 .step_height = MB_DIM,
284 },
285 },
286 {
287 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
288 .codec_mode = HANTRO_MODE_MPEG2_DEC,
289 .max_depth = 2,
290 .frmsize = {
291 .min_width = FMT_MIN_WIDTH,
292 .max_width = FMT_FHD_WIDTH,
293 .step_width = MB_DIM,
294 .min_height = FMT_MIN_HEIGHT,
295 .max_height = FMT_FHD_HEIGHT,
296 .step_height = MB_DIM,
297 },
298 },
299 {
300 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
301 .codec_mode = HANTRO_MODE_VP8_DEC,
302 .max_depth = 2,
303 .frmsize = {
304 .min_width = FMT_MIN_WIDTH,
305 .max_width = FMT_UHD_WIDTH,
306 .step_width = MB_DIM,
307 .min_height = FMT_MIN_HEIGHT,
308 .max_height = FMT_UHD_HEIGHT,
309 .step_height = MB_DIM,
310 },
311 },
312 };
313
314 static const struct hantro_fmt rockchip_vpu981_dec_fmts[] = {
315 {
316 .fourcc = V4L2_PIX_FMT_NV12_4L4,
317 .codec_mode = HANTRO_MODE_NONE,
318 .match_depth = true,
319 .frmsize = {
320 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
321 .max_width = FMT_UHD_WIDTH,
322 .step_width = MB_DIM,
323 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
324 .max_height = FMT_UHD_HEIGHT,
325 .step_height = MB_DIM,
326 },
327 },
328 {
329 .fourcc = V4L2_PIX_FMT_NV15_4L4,
330 .codec_mode = HANTRO_MODE_NONE,
331 .match_depth = true,
332 .frmsize = {
333 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
334 .max_width = FMT_UHD_WIDTH,
335 .step_width = MB_DIM,
336 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
337 .max_height = FMT_UHD_HEIGHT,
338 .step_height = MB_DIM,
339 },
340 },
341 {
342 .fourcc = V4L2_PIX_FMT_AV1_FRAME,
343 .codec_mode = HANTRO_MODE_AV1_DEC,
344 .max_depth = 2,
345 .frmsize = {
346 .min_width = ROCKCHIP_VPU981_MIN_SIZE,
347 .max_width = FMT_UHD_WIDTH,
348 .step_width = MB_DIM,
349 .min_height = ROCKCHIP_VPU981_MIN_SIZE,
350 .max_height = FMT_UHD_HEIGHT,
351 .step_height = MB_DIM,
352 },
353 },
354 };
355
rockchip_vpu1_vepu_irq(int irq,void * dev_id)356 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
357 {
358 struct hantro_dev *vpu = dev_id;
359 enum vb2_buffer_state state;
360 u32 status;
361
362 status = vepu_read(vpu, H1_REG_INTERRUPT);
363 state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
364 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
365
366 vepu_write(vpu, 0, H1_REG_INTERRUPT);
367 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
368
369 hantro_irq_done(vpu, state);
370
371 return IRQ_HANDLED;
372 }
373
rockchip_vpu2_vdpu_irq(int irq,void * dev_id)374 static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
375 {
376 struct hantro_dev *vpu = dev_id;
377 enum vb2_buffer_state state;
378 u32 status;
379
380 status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
381 state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
382 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
383
384 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
385 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
386
387 hantro_irq_done(vpu, state);
388
389 return IRQ_HANDLED;
390 }
391
rockchip_vpu2_vepu_irq(int irq,void * dev_id)392 static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
393 {
394 struct hantro_dev *vpu = dev_id;
395 enum vb2_buffer_state state;
396 u32 status;
397
398 status = vepu_read(vpu, VEPU_REG_INTERRUPT);
399 state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
400 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
401
402 vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
403 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
404
405 hantro_irq_done(vpu, state);
406
407 return IRQ_HANDLED;
408 }
409
rk3588_vpu981_irq(int irq,void * dev_id)410 static irqreturn_t rk3588_vpu981_irq(int irq, void *dev_id)
411 {
412 struct hantro_dev *vpu = dev_id;
413 enum vb2_buffer_state state;
414 u32 status;
415
416 status = vdpu_read(vpu, AV1_REG_INTERRUPT);
417 state = (status & AV1_REG_INTERRUPT_DEC_RDY_INT) ?
418 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
419
420 vdpu_write(vpu, 0, AV1_REG_INTERRUPT);
421 vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG);
422
423 hantro_irq_done(vpu, state);
424
425 return IRQ_HANDLED;
426 }
427
rk3036_vpu_hw_init(struct hantro_dev * vpu)428 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
429 {
430 /* Bump ACLK to max. possible freq. to improve performance. */
431 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
432 return 0;
433 }
434
rk3066_vpu_hw_init(struct hantro_dev * vpu)435 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
436 {
437 /* Bump ACLKs to max. possible freq. to improve performance. */
438 clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
439 clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
440 return 0;
441 }
442
rk3588_vpu981_hw_init(struct hantro_dev * vpu)443 static int rk3588_vpu981_hw_init(struct hantro_dev *vpu)
444 {
445 /* Bump ACLKs to max. possible freq. to improve performance. */
446 clk_set_rate(vpu->clocks[0].clk, RK3588_ACLK_MAX_FREQ);
447 return 0;
448 }
449
rockchip_vpu_hw_init(struct hantro_dev * vpu)450 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
451 {
452 /* Bump ACLK to max. possible freq. to improve performance. */
453 clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
454 return 0;
455 }
456
rk3066_vpu_dec_reset(struct hantro_ctx * ctx)457 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
458 {
459 struct hantro_dev *vpu = ctx->dev;
460
461 vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
462 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
463 }
464
rockchip_vpu1_enc_reset(struct hantro_ctx * ctx)465 static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
466 {
467 struct hantro_dev *vpu = ctx->dev;
468
469 vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
470 vepu_write(vpu, 0, H1_REG_ENC_CTRL);
471 vepu_write(vpu, 0, H1_REG_AXI_CTRL);
472 }
473
rockchip_vpu2_dec_reset(struct hantro_ctx * ctx)474 static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
475 {
476 struct hantro_dev *vpu = ctx->dev;
477
478 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
479 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
480 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
481 }
482
rockchip_vpu2_enc_reset(struct hantro_ctx * ctx)483 static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
484 {
485 struct hantro_dev *vpu = ctx->dev;
486
487 vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
488 vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
489 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
490 }
491
492 /*
493 * Supported codec ops.
494 */
495 static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
496 [HANTRO_MODE_H264_DEC] = {
497 .run = hantro_g1_h264_dec_run,
498 .reset = hantro_g1_reset,
499 .init = hantro_h264_dec_init,
500 .exit = hantro_h264_dec_exit,
501 },
502 [HANTRO_MODE_MPEG2_DEC] = {
503 .run = hantro_g1_mpeg2_dec_run,
504 .reset = hantro_g1_reset,
505 .init = hantro_mpeg2_dec_init,
506 .exit = hantro_mpeg2_dec_exit,
507 },
508 [HANTRO_MODE_VP8_DEC] = {
509 .run = hantro_g1_vp8_dec_run,
510 .reset = hantro_g1_reset,
511 .init = hantro_vp8_dec_init,
512 .exit = hantro_vp8_dec_exit,
513 },
514 };
515
516 static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
517 [HANTRO_MODE_JPEG_ENC] = {
518 .run = hantro_h1_jpeg_enc_run,
519 .reset = rockchip_vpu1_enc_reset,
520 .done = hantro_h1_jpeg_enc_done,
521 },
522 [HANTRO_MODE_H264_DEC] = {
523 .run = hantro_g1_h264_dec_run,
524 .reset = rk3066_vpu_dec_reset,
525 .init = hantro_h264_dec_init,
526 .exit = hantro_h264_dec_exit,
527 },
528 [HANTRO_MODE_MPEG2_DEC] = {
529 .run = hantro_g1_mpeg2_dec_run,
530 .reset = rk3066_vpu_dec_reset,
531 .init = hantro_mpeg2_dec_init,
532 .exit = hantro_mpeg2_dec_exit,
533 },
534 [HANTRO_MODE_VP8_DEC] = {
535 .run = hantro_g1_vp8_dec_run,
536 .reset = rk3066_vpu_dec_reset,
537 .init = hantro_vp8_dec_init,
538 .exit = hantro_vp8_dec_exit,
539 },
540 };
541
542 static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
543 [HANTRO_MODE_JPEG_ENC] = {
544 .run = hantro_h1_jpeg_enc_run,
545 .reset = rockchip_vpu1_enc_reset,
546 .done = hantro_h1_jpeg_enc_done,
547 },
548 [HANTRO_MODE_H264_DEC] = {
549 .run = hantro_g1_h264_dec_run,
550 .reset = hantro_g1_reset,
551 .init = hantro_h264_dec_init,
552 .exit = hantro_h264_dec_exit,
553 },
554 [HANTRO_MODE_MPEG2_DEC] = {
555 .run = hantro_g1_mpeg2_dec_run,
556 .reset = hantro_g1_reset,
557 .init = hantro_mpeg2_dec_init,
558 .exit = hantro_mpeg2_dec_exit,
559 },
560 [HANTRO_MODE_VP8_DEC] = {
561 .run = hantro_g1_vp8_dec_run,
562 .reset = hantro_g1_reset,
563 .init = hantro_vp8_dec_init,
564 .exit = hantro_vp8_dec_exit,
565 },
566 };
567
568 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
569 [HANTRO_MODE_JPEG_ENC] = {
570 .run = rockchip_vpu2_jpeg_enc_run,
571 .reset = rockchip_vpu2_enc_reset,
572 .done = rockchip_vpu2_jpeg_enc_done,
573 },
574 [HANTRO_MODE_H264_DEC] = {
575 .run = rockchip_vpu2_h264_dec_run,
576 .reset = rockchip_vpu2_dec_reset,
577 .init = hantro_h264_dec_init,
578 .exit = hantro_h264_dec_exit,
579 },
580 [HANTRO_MODE_MPEG2_DEC] = {
581 .run = rockchip_vpu2_mpeg2_dec_run,
582 .reset = rockchip_vpu2_dec_reset,
583 .init = hantro_mpeg2_dec_init,
584 .exit = hantro_mpeg2_dec_exit,
585 },
586 [HANTRO_MODE_VP8_DEC] = {
587 .run = rockchip_vpu2_vp8_dec_run,
588 .reset = rockchip_vpu2_dec_reset,
589 .init = hantro_vp8_dec_init,
590 .exit = hantro_vp8_dec_exit,
591 },
592 };
593
594 static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = {
595 [HANTRO_MODE_JPEG_ENC] = {
596 .run = rockchip_vpu2_jpeg_enc_run,
597 .reset = rockchip_vpu2_enc_reset,
598 .done = rockchip_vpu2_jpeg_enc_done,
599 },
600 };
601
602 static const struct hantro_codec_ops rk3588_vpu981_codec_ops[] = {
603 [HANTRO_MODE_AV1_DEC] = {
604 .run = rockchip_vpu981_av1_dec_run,
605 .init = rockchip_vpu981_av1_dec_init,
606 .exit = rockchip_vpu981_av1_dec_exit,
607 .done = rockchip_vpu981_av1_dec_done,
608 },
609 };
610 /*
611 * VPU variant.
612 */
613
614 static const struct hantro_irq rockchip_vdpu1_irqs[] = {
615 { "vdpu", hantro_g1_irq },
616 };
617
618 static const struct hantro_irq rockchip_vpu1_irqs[] = {
619 { "vepu", rockchip_vpu1_vepu_irq },
620 { "vdpu", hantro_g1_irq },
621 };
622
623 static const struct hantro_irq rockchip_vdpu2_irqs[] = {
624 { "vdpu", rockchip_vpu2_vdpu_irq },
625 };
626
627 static const struct hantro_irq rockchip_vpu2_irqs[] = {
628 { "vepu", rockchip_vpu2_vepu_irq },
629 { "vdpu", rockchip_vpu2_vdpu_irq },
630 };
631
632 static const struct hantro_irq rk3568_vepu_irqs[] = {
633 { "vepu", rockchip_vpu2_vepu_irq },
634 };
635
636 static const char * const rk3066_vpu_clk_names[] = {
637 "aclk_vdpu", "hclk_vdpu",
638 "aclk_vepu", "hclk_vepu"
639 };
640
641 static const struct hantro_irq rk3588_vpu981_irqs[] = {
642 { "vdpu", rk3588_vpu981_irq },
643 };
644
645 static const char * const rockchip_vpu_clk_names[] = {
646 "aclk", "hclk"
647 };
648
649 static const char * const rk3588_vpu981_vpu_clk_names[] = {
650 "aclk", "hclk",
651 };
652
653 /* VDPU1/VEPU1 */
654
655 const struct hantro_variant rk3036_vpu_variant = {
656 .dec_offset = 0x400,
657 .dec_fmts = rk3066_vpu_dec_fmts,
658 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
659 .postproc_fmts = rockchip_vpu1_postproc_fmts,
660 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
661 .postproc_ops = &hantro_g1_postproc_ops,
662 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
663 HANTRO_H264_DECODER,
664 .codec_ops = rk3036_vpu_codec_ops,
665 .irqs = rockchip_vdpu1_irqs,
666 .num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
667 .init = rk3036_vpu_hw_init,
668 .clk_names = rockchip_vpu_clk_names,
669 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
670 };
671
672 /*
673 * Despite this variant has separate clocks for decoder and encoder,
674 * it's still required to enable all four of them for either decoding
675 * or encoding and we can't split it in separate g1/h1 variants.
676 */
677 const struct hantro_variant rk3066_vpu_variant = {
678 .enc_offset = 0x0,
679 .enc_fmts = rockchip_vpu_enc_fmts,
680 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
681 .dec_offset = 0x400,
682 .dec_fmts = rk3066_vpu_dec_fmts,
683 .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
684 .postproc_fmts = rockchip_vpu1_postproc_fmts,
685 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
686 .postproc_ops = &hantro_g1_postproc_ops,
687 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
688 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
689 .codec_ops = rk3066_vpu_codec_ops,
690 .irqs = rockchip_vpu1_irqs,
691 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
692 .init = rk3066_vpu_hw_init,
693 .clk_names = rk3066_vpu_clk_names,
694 .num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
695 };
696
697 const struct hantro_variant rk3288_vpu_variant = {
698 .enc_offset = 0x0,
699 .enc_fmts = rockchip_vpu_enc_fmts,
700 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
701 .dec_offset = 0x400,
702 .dec_fmts = rk3288_vpu_dec_fmts,
703 .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
704 .postproc_fmts = rockchip_vpu1_postproc_fmts,
705 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
706 .postproc_ops = &hantro_g1_postproc_ops,
707 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
708 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
709 .codec_ops = rk3288_vpu_codec_ops,
710 .irqs = rockchip_vpu1_irqs,
711 .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
712 .init = rockchip_vpu_hw_init,
713 .clk_names = rockchip_vpu_clk_names,
714 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
715 };
716
717 /* VDPU2/VEPU2 */
718
719 const struct hantro_variant rk3328_vpu_variant = {
720 .dec_offset = 0x400,
721 .dec_fmts = rockchip_vdpu2_dec_fmts,
722 .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
723 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
724 HANTRO_H264_DECODER,
725 .codec_ops = rk3399_vpu_codec_ops,
726 .irqs = rockchip_vdpu2_irqs,
727 .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
728 .init = rockchip_vpu_hw_init,
729 .clk_names = rockchip_vpu_clk_names,
730 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
731 };
732
733 /*
734 * H.264 decoding explicitly disabled in RK3399.
735 * This ensures userspace applications use the Rockchip VDEC core,
736 * which has better performance.
737 */
738 const struct hantro_variant rk3399_vpu_variant = {
739 .enc_offset = 0x0,
740 .enc_fmts = rockchip_vpu_enc_fmts,
741 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
742 .dec_offset = 0x400,
743 .dec_fmts = rk3399_vpu_dec_fmts,
744 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
745 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
746 HANTRO_VP8_DECODER,
747 .codec_ops = rk3399_vpu_codec_ops,
748 .irqs = rockchip_vpu2_irqs,
749 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
750 .init = rockchip_vpu_hw_init,
751 .clk_names = rockchip_vpu_clk_names,
752 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
753 };
754
755 const struct hantro_variant rk3568_vepu_variant = {
756 .enc_offset = 0x0,
757 .enc_fmts = rockchip_vpu_enc_fmts,
758 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
759 .codec = HANTRO_JPEG_ENCODER,
760 .codec_ops = rk3568_vepu_codec_ops,
761 .irqs = rk3568_vepu_irqs,
762 .num_irqs = ARRAY_SIZE(rk3568_vepu_irqs),
763 .init = rockchip_vpu_hw_init,
764 .clk_names = rockchip_vpu_clk_names,
765 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
766 };
767
768 const struct hantro_variant rk3568_vpu_variant = {
769 .dec_offset = 0x400,
770 .dec_fmts = rockchip_vdpu2_dec_fmts,
771 .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
772 .codec = HANTRO_MPEG2_DECODER |
773 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
774 .codec_ops = rk3399_vpu_codec_ops,
775 .irqs = rockchip_vdpu2_irqs,
776 .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
777 .init = rockchip_vpu_hw_init,
778 .clk_names = rockchip_vpu_clk_names,
779 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
780 };
781
782 const struct hantro_variant px30_vpu_variant = {
783 .enc_offset = 0x0,
784 .enc_fmts = rockchip_vpu_enc_fmts,
785 .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
786 .dec_offset = 0x400,
787 .dec_fmts = rockchip_vdpu2_dec_fmts,
788 .num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
789 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
790 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
791 .codec_ops = rk3399_vpu_codec_ops,
792 .irqs = rockchip_vpu2_irqs,
793 .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
794 .init = rk3036_vpu_hw_init,
795 .clk_names = rockchip_vpu_clk_names,
796 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
797 };
798
799 const struct hantro_variant rk3588_vpu981_variant = {
800 .dec_offset = 0x0,
801 .dec_fmts = rockchip_vpu981_dec_fmts,
802 .num_dec_fmts = ARRAY_SIZE(rockchip_vpu981_dec_fmts),
803 .postproc_fmts = rockchip_vpu981_postproc_fmts,
804 .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu981_postproc_fmts),
805 .postproc_ops = &rockchip_vpu981_postproc_ops,
806 .codec = HANTRO_AV1_DECODER,
807 .codec_ops = rk3588_vpu981_codec_ops,
808 .irqs = rk3588_vpu981_irqs,
809 .num_irqs = ARRAY_SIZE(rk3588_vpu981_irqs),
810 .init = rk3588_vpu981_hw_init,
811 .clk_names = rk3588_vpu981_vpu_clk_names,
812 .num_clocks = ARRAY_SIZE(rk3588_vpu981_vpu_clk_names)
813 };
814