1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
5 * Copyright (c) 2013 MundoReader S.L.
6 * Author: Heiko Stuebner <heiko@sntech.de>
7 *
8 * With some ideas taken from pinctrl-samsung:
9 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
10 * http://www.samsung.com
11 * Copyright (c) 2012 Linaro Ltd
12 * https://www.linaro.org
13 *
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 */
17
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22 #include <linux/bitops.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/of.h>
25 #include <linux/of_platform.h>
26 #include <linux/pinctrl/machine.h>
27 #include <linux/pinctrl/pinconf.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/irqchip/chained_irq.h>
32 #include <linux/clk.h>
33 #include <linux/regmap.h>
34 #include <linux/mfd/syscon.h>
35 #include <linux/string_helpers.h>
36
37 #include <dt-bindings/pinctrl/rockchip.h>
38
39 #include "core.h"
40 #include "pinconf.h"
41 #include "pinctrl-rockchip.h"
42
43 /*
44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
45 * register 31:16 area.
46 */
47 #define WRITE_MASK_VAL(h, l, v) \
48 (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
49
50 /*
51 * Encode variants of iomux registers into a type variable
52 */
53 #define IOMUX_GPIO_ONLY BIT(0)
54 #define IOMUX_WIDTH_4BIT BIT(1)
55 #define IOMUX_SOURCE_PMU BIT(2)
56 #define IOMUX_UNROUTED BIT(3)
57 #define IOMUX_WIDTH_3BIT BIT(4)
58 #define IOMUX_WIDTH_2BIT BIT(5)
59 #define IOMUX_L_SOURCE_PMU BIT(6)
60
61 #define PIN_BANK(id, pins, label) \
62 { \
63 .bank_num = id, \
64 .nr_pins = pins, \
65 .name = label, \
66 .iomux = { \
67 { .offset = -1 }, \
68 { .offset = -1 }, \
69 { .offset = -1 }, \
70 { .offset = -1 }, \
71 }, \
72 }
73
74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
75 { \
76 .bank_num = id, \
77 .nr_pins = pins, \
78 .name = label, \
79 .iomux = { \
80 { .type = iom0, .offset = -1 }, \
81 { .type = iom1, .offset = -1 }, \
82 { .type = iom2, .offset = -1 }, \
83 { .type = iom3, .offset = -1 }, \
84 }, \
85 }
86
87 #define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \
88 iom1, iom2, iom3, \
89 offset0, offset1, \
90 offset2, offset3, pull0, \
91 pull1, pull2, pull3) \
92 { \
93 .bank_num = id, \
94 .nr_pins = pins, \
95 .name = label, \
96 .iomux = { \
97 { .type = iom0, .offset = offset0 }, \
98 { .type = iom1, .offset = offset1 }, \
99 { .type = iom2, .offset = offset2 }, \
100 { .type = iom3, .offset = offset3 }, \
101 }, \
102 .pull_type[0] = pull0, \
103 .pull_type[1] = pull1, \
104 .pull_type[2] = pull2, \
105 .pull_type[3] = pull3, \
106 }
107
108 #define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(id, pins, label, iom0, \
109 iom1, iom2, iom3, \
110 offset0, offset1, \
111 offset2, offset3, drv0, \
112 drv1, drv2, drv3) \
113 { \
114 .bank_num = id, \
115 .nr_pins = pins, \
116 .name = label, \
117 .iomux = { \
118 { .type = iom0, .offset = offset0 }, \
119 { .type = iom1, .offset = offset1 }, \
120 { .type = iom2, .offset = offset2 }, \
121 { .type = iom3, .offset = offset3 }, \
122 }, \
123 .drv = { \
124 { .drv_type = drv0, .offset = -1 }, \
125 { .drv_type = drv1, .offset = -1 }, \
126 { .drv_type = drv2, .offset = -1 }, \
127 { .drv_type = drv3, .offset = -1 }, \
128 }, \
129 }
130
131 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
132 { \
133 .bank_num = id, \
134 .nr_pins = pins, \
135 .name = label, \
136 .iomux = { \
137 { .offset = -1 }, \
138 { .offset = -1 }, \
139 { .offset = -1 }, \
140 { .offset = -1 }, \
141 }, \
142 .drv = { \
143 { .drv_type = type0, .offset = -1 }, \
144 { .drv_type = type1, .offset = -1 }, \
145 { .drv_type = type2, .offset = -1 }, \
146 { .drv_type = type3, .offset = -1 }, \
147 }, \
148 }
149
150 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1, \
151 iom2, iom3, pull0, pull1, \
152 pull2, pull3) \
153 { \
154 .bank_num = id, \
155 .nr_pins = pins, \
156 .name = label, \
157 .iomux = { \
158 { .type = iom0, .offset = -1 }, \
159 { .type = iom1, .offset = -1 }, \
160 { .type = iom2, .offset = -1 }, \
161 { .type = iom3, .offset = -1 }, \
162 }, \
163 .pull_type[0] = pull0, \
164 .pull_type[1] = pull1, \
165 .pull_type[2] = pull2, \
166 .pull_type[3] = pull3, \
167 }
168
169 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
170 drv2, drv3, pull0, pull1, \
171 pull2, pull3) \
172 { \
173 .bank_num = id, \
174 .nr_pins = pins, \
175 .name = label, \
176 .iomux = { \
177 { .offset = -1 }, \
178 { .offset = -1 }, \
179 { .offset = -1 }, \
180 { .offset = -1 }, \
181 }, \
182 .drv = { \
183 { .drv_type = drv0, .offset = -1 }, \
184 { .drv_type = drv1, .offset = -1 }, \
185 { .drv_type = drv2, .offset = -1 }, \
186 { .drv_type = drv3, .offset = -1 }, \
187 }, \
188 .pull_type[0] = pull0, \
189 .pull_type[1] = pull1, \
190 .pull_type[2] = pull2, \
191 .pull_type[3] = pull3, \
192 }
193
194 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
195 iom3, offset0, offset1, offset2, \
196 offset3) \
197 { \
198 .bank_num = id, \
199 .nr_pins = pins, \
200 .name = label, \
201 .iomux = { \
202 { .type = iom0, .offset = offset0 }, \
203 { .type = iom1, .offset = offset1 }, \
204 { .type = iom2, .offset = offset2 }, \
205 { .type = iom3, .offset = offset3 }, \
206 }, \
207 }
208
209 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
210 iom2, iom3, drv0, drv1, drv2, \
211 drv3, offset0, offset1, \
212 offset2, offset3) \
213 { \
214 .bank_num = id, \
215 .nr_pins = pins, \
216 .name = label, \
217 .iomux = { \
218 { .type = iom0, .offset = -1 }, \
219 { .type = iom1, .offset = -1 }, \
220 { .type = iom2, .offset = -1 }, \
221 { .type = iom3, .offset = -1 }, \
222 }, \
223 .drv = { \
224 { .drv_type = drv0, .offset = offset0 }, \
225 { .drv_type = drv1, .offset = offset1 }, \
226 { .drv_type = drv2, .offset = offset2 }, \
227 { .drv_type = drv3, .offset = offset3 }, \
228 }, \
229 }
230
231 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
232 label, iom0, iom1, iom2, \
233 iom3, drv0, drv1, drv2, \
234 drv3, offset0, offset1, \
235 offset2, offset3, pull0, \
236 pull1, pull2, pull3) \
237 { \
238 .bank_num = id, \
239 .nr_pins = pins, \
240 .name = label, \
241 .iomux = { \
242 { .type = iom0, .offset = -1 }, \
243 { .type = iom1, .offset = -1 }, \
244 { .type = iom2, .offset = -1 }, \
245 { .type = iom3, .offset = -1 }, \
246 }, \
247 .drv = { \
248 { .drv_type = drv0, .offset = offset0 }, \
249 { .drv_type = drv1, .offset = offset1 }, \
250 { .drv_type = drv2, .offset = offset2 }, \
251 { .drv_type = drv3, .offset = offset3 }, \
252 }, \
253 .pull_type[0] = pull0, \
254 .pull_type[1] = pull1, \
255 .pull_type[2] = pull2, \
256 .pull_type[3] = pull3, \
257 }
258
259 #define PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(id, pins, \
260 label, iom0, iom1, \
261 iom2, iom3, offset0, \
262 offset1, offset2, \
263 offset3, drv0, drv1, \
264 drv2, drv3, pull0, \
265 pull1, pull2, pull3) \
266 { \
267 .bank_num = id, \
268 .nr_pins = pins, \
269 .name = label, \
270 .iomux = { \
271 { .type = iom0, .offset = offset0 }, \
272 { .type = iom1, .offset = offset1 }, \
273 { .type = iom2, .offset = offset2 }, \
274 { .type = iom3, .offset = offset3 }, \
275 }, \
276 .drv = { \
277 { .drv_type = drv0, .offset = -1 }, \
278 { .drv_type = drv1, .offset = -1 }, \
279 { .drv_type = drv2, .offset = -1 }, \
280 { .drv_type = drv3, .offset = -1 }, \
281 }, \
282 .pull_type[0] = pull0, \
283 .pull_type[1] = pull1, \
284 .pull_type[2] = pull2, \
285 .pull_type[3] = pull3, \
286 }
287
288 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
289 { \
290 .bank_num = ID, \
291 .pin = PIN, \
292 .func = FUNC, \
293 .route_offset = REG, \
294 .route_val = VAL, \
295 .route_location = FLAG, \
296 }
297
298 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
299 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
300
301 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
302 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
303
304 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
305 PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
306
307 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
308 PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
309
310 static struct regmap_config rockchip_regmap_config = {
311 .reg_bits = 32,
312 .val_bits = 32,
313 .reg_stride = 4,
314 };
315
pinctrl_name_to_group(const struct rockchip_pinctrl * info,const char * name)316 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
317 const struct rockchip_pinctrl *info,
318 const char *name)
319 {
320 int i;
321
322 for (i = 0; i < info->ngroups; i++) {
323 if (!strcmp(info->groups[i].name, name))
324 return &info->groups[i];
325 }
326
327 return NULL;
328 }
329
330 /*
331 * given a pin number that is local to a pin controller, find out the pin bank
332 * and the register base of the pin bank.
333 */
pin_to_bank(struct rockchip_pinctrl * info,unsigned pin)334 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
335 unsigned pin)
336 {
337 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
338
339 while (pin >= (b->pin_base + b->nr_pins))
340 b++;
341
342 return b;
343 }
344
bank_num_to_bank(struct rockchip_pinctrl * info,unsigned num)345 static struct rockchip_pin_bank *bank_num_to_bank(
346 struct rockchip_pinctrl *info,
347 unsigned num)
348 {
349 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
350 int i;
351
352 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
353 if (b->bank_num == num)
354 return b;
355 }
356
357 return ERR_PTR(-EINVAL);
358 }
359
360 /*
361 * Pinctrl_ops handling
362 */
363
rockchip_get_groups_count(struct pinctrl_dev * pctldev)364 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
365 {
366 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
367
368 return info->ngroups;
369 }
370
rockchip_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)371 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
372 unsigned selector)
373 {
374 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
375
376 return info->groups[selector].name;
377 }
378
rockchip_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)379 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
380 unsigned selector, const unsigned **pins,
381 unsigned *npins)
382 {
383 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
384
385 if (selector >= info->ngroups)
386 return -EINVAL;
387
388 *pins = info->groups[selector].pins;
389 *npins = info->groups[selector].npins;
390
391 return 0;
392 }
393
rockchip_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)394 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
395 struct device_node *np,
396 struct pinctrl_map **map, unsigned *num_maps)
397 {
398 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
399 const struct rockchip_pin_group *grp;
400 struct device *dev = info->dev;
401 struct pinctrl_map *new_map;
402 struct device_node *parent;
403 int map_num = 1;
404 int i;
405
406 /*
407 * first find the group of this node and check if we need to create
408 * config maps for pins
409 */
410 grp = pinctrl_name_to_group(info, np->name);
411 if (!grp) {
412 dev_err(dev, "unable to find group for node %pOFn\n", np);
413 return -EINVAL;
414 }
415
416 map_num += grp->npins;
417
418 new_map = kzalloc_objs(*new_map, map_num);
419 if (!new_map)
420 return -ENOMEM;
421
422 *map = new_map;
423 *num_maps = map_num;
424
425 /* create mux map */
426 parent = of_get_parent(np);
427 if (!parent) {
428 kfree(new_map);
429 return -EINVAL;
430 }
431 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
432 new_map[0].data.mux.function = parent->name;
433 new_map[0].data.mux.group = np->name;
434 of_node_put(parent);
435
436 /* create config map */
437 new_map++;
438 for (i = 0; i < grp->npins; i++) {
439 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
440 new_map[i].data.configs.group_or_pin =
441 pin_get_name(pctldev, grp->pins[i]);
442 new_map[i].data.configs.configs = grp->data[i].configs;
443 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
444 }
445
446 dev_dbg(dev, "maps: function %s group %s num %d\n",
447 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
448
449 return 0;
450 }
451
rockchip_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)452 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
453 struct pinctrl_map *map, unsigned num_maps)
454 {
455 kfree(map);
456 }
457
458 static const struct pinctrl_ops rockchip_pctrl_ops = {
459 .get_groups_count = rockchip_get_groups_count,
460 .get_group_name = rockchip_get_group_name,
461 .get_group_pins = rockchip_get_group_pins,
462 .dt_node_to_map = rockchip_dt_node_to_map,
463 .dt_free_map = rockchip_dt_free_map,
464 };
465
466 /*
467 * Hardware access
468 */
469
470 static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = {
471 {
472 .num = 1,
473 .pin = 6,
474 .reg = 0x10024,
475 .bit = 8,
476 .mask = 0xf
477 }, {
478 .num = 1,
479 .pin = 7,
480 .reg = 0x10024,
481 .bit = 12,
482 .mask = 0xf
483 },
484 };
485
486 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
487 {
488 .num = 1,
489 .pin = 0,
490 .reg = 0x418,
491 .bit = 0,
492 .mask = 0x3
493 }, {
494 .num = 1,
495 .pin = 1,
496 .reg = 0x418,
497 .bit = 2,
498 .mask = 0x3
499 }, {
500 .num = 1,
501 .pin = 2,
502 .reg = 0x418,
503 .bit = 4,
504 .mask = 0x3
505 }, {
506 .num = 1,
507 .pin = 3,
508 .reg = 0x418,
509 .bit = 6,
510 .mask = 0x3
511 }, {
512 .num = 1,
513 .pin = 4,
514 .reg = 0x418,
515 .bit = 8,
516 .mask = 0x3
517 }, {
518 .num = 1,
519 .pin = 5,
520 .reg = 0x418,
521 .bit = 10,
522 .mask = 0x3
523 }, {
524 .num = 1,
525 .pin = 6,
526 .reg = 0x418,
527 .bit = 12,
528 .mask = 0x3
529 }, {
530 .num = 1,
531 .pin = 7,
532 .reg = 0x418,
533 .bit = 14,
534 .mask = 0x3
535 }, {
536 .num = 1,
537 .pin = 8,
538 .reg = 0x41c,
539 .bit = 0,
540 .mask = 0x3
541 }, {
542 .num = 1,
543 .pin = 9,
544 .reg = 0x41c,
545 .bit = 2,
546 .mask = 0x3
547 },
548 };
549
550 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
551 {
552 .num = 0,
553 .pin = 20,
554 .reg = 0x10000,
555 .bit = 0,
556 .mask = 0xf
557 },
558 {
559 .num = 0,
560 .pin = 21,
561 .reg = 0x10000,
562 .bit = 4,
563 .mask = 0xf
564 },
565 {
566 .num = 0,
567 .pin = 22,
568 .reg = 0x10000,
569 .bit = 8,
570 .mask = 0xf
571 },
572 {
573 .num = 0,
574 .pin = 23,
575 .reg = 0x10000,
576 .bit = 12,
577 .mask = 0xf
578 },
579 };
580
581 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
582 {
583 .num = 2,
584 .pin = 20,
585 .reg = 0xe8,
586 .bit = 0,
587 .mask = 0x7
588 }, {
589 .num = 2,
590 .pin = 21,
591 .reg = 0xe8,
592 .bit = 4,
593 .mask = 0x7
594 }, {
595 .num = 2,
596 .pin = 22,
597 .reg = 0xe8,
598 .bit = 8,
599 .mask = 0x7
600 }, {
601 .num = 2,
602 .pin = 23,
603 .reg = 0xe8,
604 .bit = 12,
605 .mask = 0x7
606 }, {
607 .num = 2,
608 .pin = 24,
609 .reg = 0xd4,
610 .bit = 12,
611 .mask = 0x7
612 },
613 };
614
615 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
616 {
617 /* gpio1b6_sel */
618 .num = 1,
619 .pin = 14,
620 .reg = 0x28,
621 .bit = 12,
622 .mask = 0xf
623 }, {
624 /* gpio1b7_sel */
625 .num = 1,
626 .pin = 15,
627 .reg = 0x2c,
628 .bit = 0,
629 .mask = 0x3
630 }, {
631 /* gpio1c2_sel */
632 .num = 1,
633 .pin = 18,
634 .reg = 0x30,
635 .bit = 4,
636 .mask = 0xf
637 }, {
638 /* gpio1c3_sel */
639 .num = 1,
640 .pin = 19,
641 .reg = 0x30,
642 .bit = 8,
643 .mask = 0xf
644 }, {
645 /* gpio1c4_sel */
646 .num = 1,
647 .pin = 20,
648 .reg = 0x30,
649 .bit = 12,
650 .mask = 0xf
651 }, {
652 /* gpio1c5_sel */
653 .num = 1,
654 .pin = 21,
655 .reg = 0x34,
656 .bit = 0,
657 .mask = 0xf
658 }, {
659 /* gpio1c6_sel */
660 .num = 1,
661 .pin = 22,
662 .reg = 0x34,
663 .bit = 4,
664 .mask = 0xf
665 }, {
666 /* gpio1c7_sel */
667 .num = 1,
668 .pin = 23,
669 .reg = 0x34,
670 .bit = 8,
671 .mask = 0xf
672 }, {
673 /* gpio2a2_sel */
674 .num = 2,
675 .pin = 2,
676 .reg = 0x40,
677 .bit = 4,
678 .mask = 0x3
679 }, {
680 /* gpio2a3_sel */
681 .num = 2,
682 .pin = 3,
683 .reg = 0x40,
684 .bit = 6,
685 .mask = 0x3
686 }, {
687 /* gpio2c0_sel */
688 .num = 2,
689 .pin = 16,
690 .reg = 0x50,
691 .bit = 0,
692 .mask = 0x3
693 }, {
694 /* gpio3b2_sel */
695 .num = 3,
696 .pin = 10,
697 .reg = 0x68,
698 .bit = 4,
699 .mask = 0x3
700 }, {
701 /* gpio3b3_sel */
702 .num = 3,
703 .pin = 11,
704 .reg = 0x68,
705 .bit = 6,
706 .mask = 0x3
707 }, {
708 /* gpio3b4_sel */
709 .num = 3,
710 .pin = 12,
711 .reg = 0x68,
712 .bit = 8,
713 .mask = 0xf
714 }, {
715 /* gpio3b5_sel */
716 .num = 3,
717 .pin = 13,
718 .reg = 0x68,
719 .bit = 12,
720 .mask = 0xf
721 },
722 };
723
724 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
725 {
726 /* gpio2_b7_sel */
727 .num = 2,
728 .pin = 15,
729 .reg = 0x28,
730 .bit = 0,
731 .mask = 0x7
732 }, {
733 /* gpio2_c7_sel */
734 .num = 2,
735 .pin = 23,
736 .reg = 0x30,
737 .bit = 14,
738 .mask = 0x3
739 }, {
740 /* gpio3_b1_sel */
741 .num = 3,
742 .pin = 9,
743 .reg = 0x44,
744 .bit = 2,
745 .mask = 0x3
746 }, {
747 /* gpio3_b2_sel */
748 .num = 3,
749 .pin = 10,
750 .reg = 0x44,
751 .bit = 4,
752 .mask = 0x3
753 }, {
754 /* gpio3_b3_sel */
755 .num = 3,
756 .pin = 11,
757 .reg = 0x44,
758 .bit = 6,
759 .mask = 0x3
760 }, {
761 /* gpio3_b4_sel */
762 .num = 3,
763 .pin = 12,
764 .reg = 0x44,
765 .bit = 8,
766 .mask = 0x3
767 }, {
768 /* gpio3_b5_sel */
769 .num = 3,
770 .pin = 13,
771 .reg = 0x44,
772 .bit = 10,
773 .mask = 0x3
774 }, {
775 /* gpio3_b6_sel */
776 .num = 3,
777 .pin = 14,
778 .reg = 0x44,
779 .bit = 12,
780 .mask = 0x3
781 }, {
782 /* gpio3_b7_sel */
783 .num = 3,
784 .pin = 15,
785 .reg = 0x44,
786 .bit = 14,
787 .mask = 0x3
788 },
789 };
790
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)791 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
792 int *reg, u8 *bit, int *mask)
793 {
794 struct rockchip_pinctrl *info = bank->drvdata;
795 struct rockchip_pin_ctrl *ctrl = info->ctrl;
796 struct rockchip_mux_recalced_data *data;
797 int i;
798
799 for (i = 0; i < ctrl->niomux_recalced; i++) {
800 data = &ctrl->iomux_recalced[i];
801 if (data->num == bank->bank_num &&
802 data->pin == pin)
803 break;
804 }
805
806 if (i >= ctrl->niomux_recalced)
807 return;
808
809 *reg = data->reg;
810 *mask = data->mask;
811 *bit = data->bit;
812 }
813
814 static struct rockchip_mux_route_data px30_mux_route_data[] = {
815 RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
816 RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
817 RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
818 RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
819 RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
820 RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
821 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
822 RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
823 RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
824 RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
825 RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
826 RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
827 RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
828 RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
829 RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
830 RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
831 RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
832 RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
833 RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
834 RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
835 RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
836 RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
837 RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
838 RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
839 RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
840 RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
841 RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
842 RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
843 RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
844 RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
845 RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
846 RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
847 RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
848 RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
849 RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
850 RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
851 RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
852 RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
853 RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
854 RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
855 RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
856 RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
857 RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
858 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
859 RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
860 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
861 RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
862 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
863 };
864
865 static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
866 RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
867 RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
868
869 RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
870 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
871 RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
872
873 RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
874 RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
875
876 RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
877 RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
878
879 RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
880 RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
881
882 RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
883 RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
884 RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
885
886 RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
887 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
888
889 RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
890 RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
891 RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
892
893 RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
894 RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
895 RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
896
897 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
898 RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
899
900 RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
901 RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
902
903 RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
904 RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
905
906 RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
907 RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
908
909 RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
910 RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
911
912 RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
913 RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
914
915 RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
916 RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
917
918 RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
919 RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
920 RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
921
922 RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
923 RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
924 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
925
926 RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
927 RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
928 RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
929
930 RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
931 RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
932
933 RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
934 RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
935
936 RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
937 RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
938
939 RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
940 RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
941
942 RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
943 RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
944
945 RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
946 RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
947
948 RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
949 RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
950
951 RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
952 RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
953
954 RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
955 RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
956 RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
957
958 RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
959 RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
960 };
961
962 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
963 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
964 RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
965 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
966 RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
967 RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
968 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
969 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
970 };
971
972 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
973 RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
974 RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
975 };
976
977 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
978 RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
979 RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
980 RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
981 RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
982 RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
983 RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
984 RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
985 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
986 RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
987 RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
988 RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
989 RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
990 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
991 RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
992 RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
993 RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
994 RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
995 RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
996 };
997
998 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
999 RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
1000 RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
1001 };
1002
1003 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
1004 RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
1005 RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
1006 RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
1007 RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
1008 RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */
1009 RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
1010 RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
1011 RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
1012 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
1013 RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
1014 RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
1015 RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
1016 RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
1017 };
1018
1019 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
1020 RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
1021 RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
1022 RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
1023 RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
1024 RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
1025 RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
1026 RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
1027 RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
1028 RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
1029 RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
1030 RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
1031 RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
1032 };
1033
1034 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
1035 RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
1036 RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
1037 RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
1038 RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
1039 RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
1040 };
1041
1042 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
1043 RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
1044 RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
1045 RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
1046 RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
1047 RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
1048 RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
1049 RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
1050 RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
1051 RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
1052 RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
1053 RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
1054 RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
1055 RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
1056 RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
1057 RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
1058 RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
1059 RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
1060 RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
1061 RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
1062 RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
1063 RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
1064 RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
1065 RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
1066 RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
1067 RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1068 RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1069 RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1070 RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1071 RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1072 RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1073 RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1074 RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1075 RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1076 RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1077 RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1078 RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1079 RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1080 RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1081 RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1082 RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1083 RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1084 RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1085 RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1086 RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1087 RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1088 RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1089 RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1090 RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1091 RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1092 RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1093 RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1094 RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1095 RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1096 RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1097 RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1098 RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1099 RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1100 RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1101 RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1102 RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1103 RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1104 RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1105 RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1106 RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1107 RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1108 RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1109 RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1110 RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1111 RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1112 RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1113 RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1114 RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1115 RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1116 RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1117 RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1118 RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1119 RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1120 RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1121 RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1122 RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1123 RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1124 RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1125 RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1126 RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1127 RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1128 RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1129 RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1130 RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1131 RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1132 RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1133 RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1134 RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1135 RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1136 };
1137
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * loc,u32 * reg,u32 * value)1138 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1139 int mux, u32 *loc, u32 *reg, u32 *value)
1140 {
1141 struct rockchip_pinctrl *info = bank->drvdata;
1142 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1143 struct rockchip_mux_route_data *data;
1144 int i;
1145
1146 for (i = 0; i < ctrl->niomux_routes; i++) {
1147 data = &ctrl->iomux_routes[i];
1148 if ((data->bank_num == bank->bank_num) &&
1149 (data->pin == pin) && (data->func == mux))
1150 break;
1151 }
1152
1153 if (i >= ctrl->niomux_routes)
1154 return false;
1155
1156 *loc = data->route_location;
1157 *reg = data->route_offset;
1158 *value = data->route_val;
1159
1160 return true;
1161 }
1162
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)1163 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1164 {
1165 struct rockchip_pinctrl *info = bank->drvdata;
1166 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1167 int iomux_num = (pin / 8);
1168 struct regmap *regmap;
1169 unsigned int val;
1170 int reg, ret, mask, mux_type;
1171 u8 bit;
1172
1173 if (iomux_num > 3)
1174 return -EINVAL;
1175
1176 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1177 dev_err(info->dev, "pin %d is unrouted\n", pin);
1178 return -EINVAL;
1179 }
1180
1181 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1182 return RK_FUNC_GPIO;
1183
1184 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1185 regmap = info->regmap_pmu;
1186 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1187 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1188 else
1189 regmap = info->regmap_base;
1190
1191 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
1192 return 0;
1193
1194 if (ctrl->type == RK3506) {
1195 if (bank->bank_num == 1)
1196 regmap = info->regmap_ioc1;
1197 else if (bank->bank_num == 4)
1198 return 0;
1199 }
1200
1201 /* get basic quadrupel of mux registers and the correct reg inside */
1202 mux_type = bank->iomux[iomux_num].type;
1203 reg = bank->iomux[iomux_num].offset;
1204 if (mux_type & IOMUX_WIDTH_4BIT) {
1205 if ((pin % 8) >= 4)
1206 reg += 0x4;
1207 bit = (pin % 4) * 4;
1208 mask = 0xf;
1209 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1210 if ((pin % 8) >= 5)
1211 reg += 0x4;
1212 bit = (pin % 8 % 5) * 3;
1213 mask = 0x7;
1214 } else {
1215 bit = (pin % 8) * 2;
1216 mask = 0x3;
1217 }
1218
1219 if (bank->recalced_mask & BIT(pin))
1220 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1221
1222 if (ctrl->type == RK3576) {
1223 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1224 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1225 }
1226
1227 if (ctrl->type == RK3588) {
1228 if (bank->bank_num == 0) {
1229 if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1230 u32 reg0 = 0;
1231
1232 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1233 ret = regmap_read(regmap, reg0, &val);
1234 if (ret)
1235 return ret;
1236
1237 if (!(val & BIT(8)))
1238 return ((val >> bit) & mask);
1239
1240 reg = reg + 0x8000; /* BUS_IOC_BASE */
1241 regmap = info->regmap_base;
1242 }
1243 } else if (bank->bank_num > 0) {
1244 reg += 0x8000; /* BUS_IOC_BASE */
1245 }
1246 }
1247
1248 ret = regmap_read(regmap, reg, &val);
1249 if (ret)
1250 return ret;
1251
1252 return ((val >> bit) & mask);
1253 }
1254
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)1255 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1256 int pin, int mux)
1257 {
1258 struct rockchip_pinctrl *info = bank->drvdata;
1259 struct device *dev = info->dev;
1260 int iomux_num = (pin / 8);
1261
1262 if (iomux_num > 3)
1263 return -EINVAL;
1264
1265 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1266 dev_err(dev, "pin %d is unrouted\n", pin);
1267 return -EINVAL;
1268 }
1269
1270 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1271 if (mux != RK_FUNC_GPIO) {
1272 dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1273 return -ENOTSUPP;
1274 }
1275 }
1276
1277 return 0;
1278 }
1279
1280 /*
1281 * Set a new mux function for a pin.
1282 *
1283 * The register is divided into the upper and lower 16 bit. When changing
1284 * a value, the previous register value is not read and changed. Instead
1285 * it seems the changed bits are marked in the upper 16 bit, while the
1286 * changed value gets set in the same offset in the lower 16 bit.
1287 * All pin settings seem to be 2 bit wide in both the upper and lower
1288 * parts.
1289 * @bank: pin bank to change
1290 * @pin: pin to change
1291 * @mux: new mux function to set
1292 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)1293 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1294 {
1295 struct rockchip_pinctrl *info = bank->drvdata;
1296 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1297 struct device *dev = info->dev;
1298 int iomux_num = (pin / 8);
1299 struct regmap *regmap;
1300 int reg, ret, mask, mux_type;
1301 u8 bit;
1302 u32 data, rmask, route_location, route_reg, route_val;
1303
1304 ret = rockchip_verify_mux(bank, pin, mux);
1305 if (ret < 0)
1306 return ret;
1307
1308 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1309 return 0;
1310
1311 dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1312
1313 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1314 regmap = info->regmap_pmu;
1315 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1316 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1317 else
1318 regmap = info->regmap_base;
1319
1320 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin >= 12)
1321 return 0;
1322
1323 if (ctrl->type == RK3506) {
1324 if (bank->bank_num == 1)
1325 regmap = info->regmap_ioc1;
1326 else if (bank->bank_num == 4)
1327 return 0;
1328 }
1329
1330 /* get basic quadrupel of mux registers and the correct reg inside */
1331 mux_type = bank->iomux[iomux_num].type;
1332 reg = bank->iomux[iomux_num].offset;
1333 if (mux_type & IOMUX_WIDTH_4BIT) {
1334 if ((pin % 8) >= 4)
1335 reg += 0x4;
1336 bit = (pin % 4) * 4;
1337 mask = 0xf;
1338 } else if (mux_type & IOMUX_WIDTH_3BIT) {
1339 if ((pin % 8) >= 5)
1340 reg += 0x4;
1341 bit = (pin % 8 % 5) * 3;
1342 mask = 0x7;
1343 } else {
1344 bit = (pin % 8) * 2;
1345 mask = 0x3;
1346 }
1347
1348 if (bank->recalced_mask & BIT(pin))
1349 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
1350
1351 if (ctrl->type == RK3576) {
1352 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1353 reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1354 }
1355
1356 if (ctrl->type == RK3588) {
1357 if (bank->bank_num == 0) {
1358 if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1359 if (mux < 8) {
1360 reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
1361 data = (mask << (bit + 16));
1362 rmask = data | (data >> 16);
1363 data |= (mux & mask) << bit;
1364 ret = regmap_update_bits(regmap, reg, rmask, data);
1365 } else {
1366 u32 reg0 = 0;
1367
1368 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1369 data = (mask << (bit + 16));
1370 rmask = data | (data >> 16);
1371 data |= 8 << bit;
1372 ret = regmap_update_bits(regmap, reg0, rmask, data);
1373
1374 reg0 = reg + 0x8000; /* BUS_IOC_BASE */
1375 data = (mask << (bit + 16));
1376 rmask = data | (data >> 16);
1377 data |= mux << bit;
1378 regmap = info->regmap_base;
1379 ret |= regmap_update_bits(regmap, reg0, rmask, data);
1380 }
1381 } else {
1382 data = (mask << (bit + 16));
1383 rmask = data | (data >> 16);
1384 data |= (mux & mask) << bit;
1385 ret = regmap_update_bits(regmap, reg, rmask, data);
1386 }
1387 return ret;
1388 } else if (bank->bank_num > 0) {
1389 reg += 0x8000; /* BUS_IOC_BASE */
1390 }
1391 }
1392
1393 if (mux > mask)
1394 return -EINVAL;
1395
1396 if (bank->route_mask & BIT(pin)) {
1397 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1398 &route_reg, &route_val)) {
1399 struct regmap *route_regmap = regmap;
1400
1401 /* handle special locations */
1402 switch (route_location) {
1403 case ROCKCHIP_ROUTE_PMU:
1404 route_regmap = info->regmap_pmu;
1405 break;
1406 case ROCKCHIP_ROUTE_GRF:
1407 route_regmap = info->regmap_base;
1408 break;
1409 }
1410
1411 ret = regmap_write(route_regmap, route_reg, route_val);
1412 if (ret)
1413 return ret;
1414 }
1415 }
1416
1417 data = (mask << (bit + 16));
1418 rmask = data | (data >> 16);
1419 data |= (mux & mask) << bit;
1420 ret = regmap_update_bits(regmap, reg, rmask, data);
1421
1422 return ret;
1423 }
1424
1425 #define PX30_PULL_PMU_OFFSET 0x10
1426 #define PX30_PULL_GRF_OFFSET 0x60
1427 #define PX30_PULL_BITS_PER_PIN 2
1428 #define PX30_PULL_PINS_PER_REG 8
1429 #define PX30_PULL_BANK_STRIDE 16
1430
px30_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1431 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1432 int pin_num, struct regmap **regmap,
1433 int *reg, u8 *bit)
1434 {
1435 struct rockchip_pinctrl *info = bank->drvdata;
1436
1437 /* The first 32 pins of the first bank are located in PMU */
1438 if (bank->bank_num == 0) {
1439 *regmap = info->regmap_pmu;
1440 *reg = PX30_PULL_PMU_OFFSET;
1441 } else {
1442 *regmap = info->regmap_base;
1443 *reg = PX30_PULL_GRF_OFFSET;
1444
1445 /* correct the offset, as we're starting with the 2nd bank */
1446 *reg -= 0x10;
1447 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1448 }
1449
1450 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1451 *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1452 *bit *= PX30_PULL_BITS_PER_PIN;
1453
1454 return 0;
1455 }
1456
1457 #define PX30_DRV_PMU_OFFSET 0x20
1458 #define PX30_DRV_GRF_OFFSET 0xf0
1459 #define PX30_DRV_BITS_PER_PIN 2
1460 #define PX30_DRV_PINS_PER_REG 8
1461 #define PX30_DRV_BANK_STRIDE 16
1462
px30_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1463 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1464 int pin_num, struct regmap **regmap,
1465 int *reg, u8 *bit)
1466 {
1467 struct rockchip_pinctrl *info = bank->drvdata;
1468
1469 /* The first 32 pins of the first bank are located in PMU */
1470 if (bank->bank_num == 0) {
1471 *regmap = info->regmap_pmu;
1472 *reg = PX30_DRV_PMU_OFFSET;
1473 } else {
1474 *regmap = info->regmap_base;
1475 *reg = PX30_DRV_GRF_OFFSET;
1476
1477 /* correct the offset, as we're starting with the 2nd bank */
1478 *reg -= 0x10;
1479 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1480 }
1481
1482 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1483 *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1484 *bit *= PX30_DRV_BITS_PER_PIN;
1485
1486 return 0;
1487 }
1488
1489 #define PX30_SCHMITT_PMU_OFFSET 0x38
1490 #define PX30_SCHMITT_GRF_OFFSET 0xc0
1491 #define PX30_SCHMITT_PINS_PER_PMU_REG 16
1492 #define PX30_SCHMITT_BANK_STRIDE 16
1493 #define PX30_SCHMITT_PINS_PER_GRF_REG 8
1494
px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1495 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1496 int pin_num,
1497 struct regmap **regmap,
1498 int *reg, u8 *bit)
1499 {
1500 struct rockchip_pinctrl *info = bank->drvdata;
1501 int pins_per_reg;
1502
1503 if (bank->bank_num == 0) {
1504 *regmap = info->regmap_pmu;
1505 *reg = PX30_SCHMITT_PMU_OFFSET;
1506 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1507 } else {
1508 *regmap = info->regmap_base;
1509 *reg = PX30_SCHMITT_GRF_OFFSET;
1510 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1511 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
1512 }
1513
1514 *reg += ((pin_num / pins_per_reg) * 4);
1515 *bit = pin_num % pins_per_reg;
1516
1517 return 0;
1518 }
1519
1520 #define RV1103B_DRV_BITS_PER_PIN 8
1521 #define RV1103B_DRV_PINS_PER_REG 2
1522 #define RV1103B_DRV_GPIO0_A_OFFSET 0x40100
1523 #define RV1103B_DRV_GPIO0_B_OFFSET 0x50110
1524 #define RV1103B_DRV_GPIO1_A01_OFFSET 0x140
1525 #define RV1103B_DRV_GPIO1_A67_OFFSET 0x1014C
1526 #define RV1103B_DRV_GPIO2_OFFSET 0x30180
1527 #define RV1103B_DRV_GPIO2_SARADC_OFFSET 0x3080C
1528
rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1529 static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1530 int pin_num, struct regmap **regmap,
1531 int *reg, u8 *bit)
1532 {
1533 struct rockchip_pinctrl *info = bank->drvdata;
1534 int ret = 0;
1535
1536 *regmap = info->regmap_base;
1537 switch (bank->bank_num) {
1538 case 0:
1539 if (pin_num < 7)
1540 *reg = RV1103B_DRV_GPIO0_A_OFFSET;
1541 else if (pin_num > 7 && pin_num < 14)
1542 *reg = RV1103B_DRV_GPIO0_B_OFFSET - 0x10;
1543 else
1544 ret = -EINVAL;
1545 break;
1546
1547 case 1:
1548 if (pin_num < 6)
1549 *reg = RV1103B_DRV_GPIO1_A01_OFFSET;
1550 else if (pin_num >= 6 && pin_num < 23)
1551 *reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
1552 else if (pin_num >= 24 && pin_num < 30)
1553 *reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
1554 else
1555 ret = -EINVAL;
1556 break;
1557
1558 case 2:
1559 if (pin_num < 12) {
1560 *reg = RV1103B_DRV_GPIO2_OFFSET;
1561 } else if (pin_num >= 16) {
1562 ret = -EINVAL;
1563 } else {
1564 *reg = RV1103B_DRV_GPIO2_SARADC_OFFSET;
1565 *bit = 10;
1566
1567 return 0;
1568 }
1569 break;
1570
1571 default:
1572 ret = -EINVAL;
1573 break;
1574 }
1575
1576 if (ret) {
1577 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1578
1579 return ret;
1580 }
1581
1582 *reg += ((pin_num / RV1103B_DRV_PINS_PER_REG) * 4);
1583 *bit = pin_num % RV1103B_DRV_PINS_PER_REG;
1584 *bit *= RV1103B_DRV_BITS_PER_PIN;
1585
1586 return 0;
1587 }
1588
1589 #define RV1103B_PULL_BITS_PER_PIN 2
1590 #define RV1103B_PULL_PINS_PER_REG 8
1591 #define RV1103B_PULL_GPIO0_A_OFFSET 0x40200
1592 #define RV1103B_PULL_GPIO0_B_OFFSET 0x50204
1593 #define RV1103B_PULL_GPIO1_A01_OFFSET 0x210
1594 #define RV1103B_PULL_GPIO1_A67_OFFSET 0x10210
1595 #define RV1103B_PULL_GPIO2_OFFSET 0x30220
1596 #define RV1103B_PULL_GPIO2_SARADC_OFFSET 0x3080C
1597
rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1598 static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1599 int pin_num, struct regmap **regmap,
1600 int *reg, u8 *bit)
1601 {
1602 struct rockchip_pinctrl *info = bank->drvdata;
1603 int ret = 0;
1604
1605 *regmap = info->regmap_base;
1606 switch (bank->bank_num) {
1607 case 0:
1608 if (pin_num < 7)
1609 *reg = RV1103B_PULL_GPIO0_A_OFFSET;
1610 else if (pin_num > 7 && pin_num < 14)
1611 *reg = RV1103B_PULL_GPIO0_B_OFFSET - 0x4;
1612 else
1613 ret = -EINVAL;
1614 break;
1615
1616 case 1:
1617 if (pin_num < 6)
1618 *reg = RV1103B_PULL_GPIO1_A01_OFFSET;
1619 else if (pin_num >= 6 && pin_num < 23)
1620 *reg = RV1103B_PULL_GPIO1_A67_OFFSET;
1621 else if (pin_num >= 24 && pin_num < 30)
1622 *reg = RV1103B_PULL_GPIO1_A67_OFFSET;
1623 else
1624 ret = -EINVAL;
1625 break;
1626
1627 case 2:
1628 if (pin_num < 12) {
1629 *reg = RV1103B_PULL_GPIO2_OFFSET;
1630 } else if (pin_num >= 16) {
1631 ret = -EINVAL;
1632 } else {
1633 *reg = RV1103B_PULL_GPIO2_SARADC_OFFSET;
1634 *bit = 13;
1635
1636 return 0;
1637 }
1638 break;
1639
1640 default:
1641 ret = -EINVAL;
1642 break;
1643 }
1644
1645 if (ret) {
1646 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1647
1648 return ret;
1649 }
1650
1651 *reg += ((pin_num / RV1103B_PULL_PINS_PER_REG) * 4);
1652 *bit = pin_num % RV1103B_PULL_PINS_PER_REG;
1653 *bit *= RV1103B_PULL_BITS_PER_PIN;
1654
1655 return 0;
1656 }
1657
1658 #define RV1103B_SMT_BITS_PER_PIN 1
1659 #define RV1103B_SMT_PINS_PER_REG 8
1660 #define RV1103B_SMT_GPIO0_A_OFFSET 0x40400
1661 #define RV1103B_SMT_GPIO0_B_OFFSET 0x50404
1662 #define RV1103B_SMT_GPIO1_A01_OFFSET 0x410
1663 #define RV1103B_SMT_GPIO1_A67_OFFSET 0x10410
1664 #define RV1103B_SMT_GPIO2_OFFSET 0x30420
1665 #define RV1103B_SMT_GPIO2_SARADC_OFFSET 0x3080C
1666
rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1667 static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1668 int pin_num,
1669 struct regmap **regmap,
1670 int *reg, u8 *bit)
1671 {
1672 struct rockchip_pinctrl *info = bank->drvdata;
1673 int ret = 0;
1674
1675 *regmap = info->regmap_base;
1676 switch (bank->bank_num) {
1677 case 0:
1678 if (pin_num < 7)
1679 *reg = RV1103B_SMT_GPIO0_A_OFFSET;
1680 else if (pin_num > 7 && pin_num < 14)
1681 *reg = RV1103B_SMT_GPIO0_B_OFFSET - 0x4;
1682 else
1683 ret = -EINVAL;
1684 break;
1685
1686 case 1:
1687 if (pin_num < 6)
1688 *reg = RV1103B_SMT_GPIO1_A01_OFFSET;
1689 else if (pin_num >= 6 && pin_num < 23)
1690 *reg = RV1103B_SMT_GPIO1_A67_OFFSET;
1691 else if (pin_num >= 24 && pin_num < 30)
1692 *reg = RV1103B_SMT_GPIO1_A67_OFFSET;
1693 else
1694 ret = -EINVAL;
1695 break;
1696
1697 case 2:
1698 if (pin_num < 12) {
1699 *reg = RV1103B_SMT_GPIO2_OFFSET;
1700 } else if (pin_num >= 16) {
1701 ret = -EINVAL;
1702 } else {
1703 *reg = RV1103B_SMT_GPIO2_SARADC_OFFSET;
1704 *bit = 8;
1705
1706 return 0;
1707 }
1708 break;
1709
1710 default:
1711 ret = -EINVAL;
1712 break;
1713 }
1714
1715 if (ret) {
1716 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
1717
1718 return ret;
1719 }
1720
1721 *reg += ((pin_num / RV1103B_SMT_PINS_PER_REG) * 4);
1722 *bit = pin_num % RV1103B_SMT_PINS_PER_REG;
1723 *bit *= RV1103B_SMT_BITS_PER_PIN;
1724
1725 return 0;
1726 }
1727
1728 #define RV1108_PULL_PMU_OFFSET 0x10
1729 #define RV1108_PULL_OFFSET 0x110
1730 #define RV1108_PULL_PINS_PER_REG 8
1731 #define RV1108_PULL_BITS_PER_PIN 2
1732 #define RV1108_PULL_BANK_STRIDE 16
1733
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1734 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1735 int pin_num, struct regmap **regmap,
1736 int *reg, u8 *bit)
1737 {
1738 struct rockchip_pinctrl *info = bank->drvdata;
1739
1740 /* The first 24 pins of the first bank are located in PMU */
1741 if (bank->bank_num == 0) {
1742 *regmap = info->regmap_pmu;
1743 *reg = RV1108_PULL_PMU_OFFSET;
1744 } else {
1745 *reg = RV1108_PULL_OFFSET;
1746 *regmap = info->regmap_base;
1747 /* correct the offset, as we're starting with the 2nd bank */
1748 *reg -= 0x10;
1749 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1750 }
1751
1752 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1753 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1754 *bit *= RV1108_PULL_BITS_PER_PIN;
1755
1756 return 0;
1757 }
1758
1759 #define RV1108_DRV_PMU_OFFSET 0x20
1760 #define RV1108_DRV_GRF_OFFSET 0x210
1761 #define RV1108_DRV_BITS_PER_PIN 2
1762 #define RV1108_DRV_PINS_PER_REG 8
1763 #define RV1108_DRV_BANK_STRIDE 16
1764
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1765 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1766 int pin_num, struct regmap **regmap,
1767 int *reg, u8 *bit)
1768 {
1769 struct rockchip_pinctrl *info = bank->drvdata;
1770
1771 /* The first 24 pins of the first bank are located in PMU */
1772 if (bank->bank_num == 0) {
1773 *regmap = info->regmap_pmu;
1774 *reg = RV1108_DRV_PMU_OFFSET;
1775 } else {
1776 *regmap = info->regmap_base;
1777 *reg = RV1108_DRV_GRF_OFFSET;
1778
1779 /* correct the offset, as we're starting with the 2nd bank */
1780 *reg -= 0x10;
1781 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1782 }
1783
1784 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1785 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1786 *bit *= RV1108_DRV_BITS_PER_PIN;
1787
1788 return 0;
1789 }
1790
1791 #define RV1108_SCHMITT_PMU_OFFSET 0x30
1792 #define RV1108_SCHMITT_GRF_OFFSET 0x388
1793 #define RV1108_SCHMITT_BANK_STRIDE 8
1794 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1795 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1796
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1797 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1798 int pin_num,
1799 struct regmap **regmap,
1800 int *reg, u8 *bit)
1801 {
1802 struct rockchip_pinctrl *info = bank->drvdata;
1803 int pins_per_reg;
1804
1805 if (bank->bank_num == 0) {
1806 *regmap = info->regmap_pmu;
1807 *reg = RV1108_SCHMITT_PMU_OFFSET;
1808 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1809 } else {
1810 *regmap = info->regmap_base;
1811 *reg = RV1108_SCHMITT_GRF_OFFSET;
1812 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1813 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1814 }
1815 *reg += ((pin_num / pins_per_reg) * 4);
1816 *bit = pin_num % pins_per_reg;
1817
1818 return 0;
1819 }
1820
1821 #define RV1126_PULL_PMU_OFFSET 0x40
1822 #define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
1823 #define RV1126_PULL_PINS_PER_REG 8
1824 #define RV1126_PULL_BITS_PER_PIN 2
1825 #define RV1126_PULL_BANK_STRIDE 16
1826 #define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1827
rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1828 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1829 int pin_num, struct regmap **regmap,
1830 int *reg, u8 *bit)
1831 {
1832 struct rockchip_pinctrl *info = bank->drvdata;
1833
1834 /* The first 24 pins of the first bank are located in PMU */
1835 if (bank->bank_num == 0) {
1836 if (RV1126_GPIO_C4_D7(pin_num)) {
1837 *regmap = info->regmap_base;
1838 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1839 *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1840 *bit = pin_num % RV1126_PULL_PINS_PER_REG;
1841 *bit *= RV1126_PULL_BITS_PER_PIN;
1842 return 0;
1843 }
1844 *regmap = info->regmap_pmu;
1845 *reg = RV1126_PULL_PMU_OFFSET;
1846 } else {
1847 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1848 *regmap = info->regmap_base;
1849 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1850 }
1851
1852 *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
1853 *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1854 *bit *= RV1126_PULL_BITS_PER_PIN;
1855
1856 return 0;
1857 }
1858
1859 #define RV1126_DRV_PMU_OFFSET 0x20
1860 #define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
1861 #define RV1126_DRV_BITS_PER_PIN 4
1862 #define RV1126_DRV_PINS_PER_REG 4
1863 #define RV1126_DRV_BANK_STRIDE 32
1864
rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1865 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1866 int pin_num, struct regmap **regmap,
1867 int *reg, u8 *bit)
1868 {
1869 struct rockchip_pinctrl *info = bank->drvdata;
1870
1871 /* The first 24 pins of the first bank are located in PMU */
1872 if (bank->bank_num == 0) {
1873 if (RV1126_GPIO_C4_D7(pin_num)) {
1874 *regmap = info->regmap_base;
1875 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1876 *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1877 *reg -= 0x4;
1878 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1879 *bit *= RV1126_DRV_BITS_PER_PIN;
1880 return 0;
1881 }
1882 *regmap = info->regmap_pmu;
1883 *reg = RV1126_DRV_PMU_OFFSET;
1884 } else {
1885 *regmap = info->regmap_base;
1886 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1887 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
1888 }
1889
1890 *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
1891 *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1892 *bit *= RV1126_DRV_BITS_PER_PIN;
1893
1894 return 0;
1895 }
1896
1897 #define RV1126_SCHMITT_PMU_OFFSET 0x60
1898 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
1899 #define RV1126_SCHMITT_BANK_STRIDE 16
1900 #define RV1126_SCHMITT_PINS_PER_GRF_REG 8
1901 #define RV1126_SCHMITT_PINS_PER_PMU_REG 8
1902
rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1903 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1904 int pin_num,
1905 struct regmap **regmap,
1906 int *reg, u8 *bit)
1907 {
1908 struct rockchip_pinctrl *info = bank->drvdata;
1909 int pins_per_reg;
1910
1911 if (bank->bank_num == 0) {
1912 if (RV1126_GPIO_C4_D7(pin_num)) {
1913 *regmap = info->regmap_base;
1914 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1915 *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
1916 *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
1917 return 0;
1918 }
1919 *regmap = info->regmap_pmu;
1920 *reg = RV1126_SCHMITT_PMU_OFFSET;
1921 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
1922 } else {
1923 *regmap = info->regmap_base;
1924 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1925 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
1926 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
1927 }
1928 *reg += ((pin_num / pins_per_reg) * 4);
1929 *bit = pin_num % pins_per_reg;
1930
1931 return 0;
1932 }
1933
1934 #define RK3308_SCHMITT_PINS_PER_REG 8
1935 #define RK3308_SCHMITT_BANK_STRIDE 16
1936 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0
1937
rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1938 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1939 int pin_num, struct regmap **regmap,
1940 int *reg, u8 *bit)
1941 {
1942 struct rockchip_pinctrl *info = bank->drvdata;
1943
1944 *regmap = info->regmap_base;
1945 *reg = RK3308_SCHMITT_GRF_OFFSET;
1946
1947 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1948 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1949 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1950
1951 return 0;
1952 }
1953
1954 #define RK2928_PULL_OFFSET 0x118
1955 #define RK2928_PULL_PINS_PER_REG 16
1956 #define RK2928_PULL_BANK_STRIDE 8
1957
rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1958 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1959 int pin_num, struct regmap **regmap,
1960 int *reg, u8 *bit)
1961 {
1962 struct rockchip_pinctrl *info = bank->drvdata;
1963
1964 *regmap = info->regmap_base;
1965 *reg = RK2928_PULL_OFFSET;
1966 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1967 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1968
1969 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1970
1971 return 0;
1972 };
1973
1974 #define RK3128_PULL_OFFSET 0x118
1975
rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1976 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1977 int pin_num, struct regmap **regmap,
1978 int *reg, u8 *bit)
1979 {
1980 struct rockchip_pinctrl *info = bank->drvdata;
1981
1982 *regmap = info->regmap_base;
1983 *reg = RK3128_PULL_OFFSET;
1984 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1985 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1986
1987 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1988
1989 return 0;
1990 }
1991
1992 #define RK3188_PULL_OFFSET 0x164
1993 #define RK3188_PULL_BITS_PER_PIN 2
1994 #define RK3188_PULL_PINS_PER_REG 8
1995 #define RK3188_PULL_BANK_STRIDE 16
1996 #define RK3188_PULL_PMU_OFFSET 0x64
1997
rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)1998 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1999 int pin_num, struct regmap **regmap,
2000 int *reg, u8 *bit)
2001 {
2002 struct rockchip_pinctrl *info = bank->drvdata;
2003
2004 /* The first 12 pins of the first bank are located elsewhere */
2005 if (bank->bank_num == 0 && pin_num < 12) {
2006 *regmap = info->regmap_pmu ? info->regmap_pmu
2007 : bank->regmap_pull;
2008 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
2009 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2010 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2011 *bit *= RK3188_PULL_BITS_PER_PIN;
2012 } else {
2013 *regmap = info->regmap_pull ? info->regmap_pull
2014 : info->regmap_base;
2015 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
2016
2017 /* correct the offset, as it is the 2nd pull register */
2018 *reg -= 4;
2019 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2020 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2021
2022 /*
2023 * The bits in these registers have an inverse ordering
2024 * with the lowest pin being in bits 15:14 and the highest
2025 * pin in bits 1:0
2026 */
2027 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
2028 *bit *= RK3188_PULL_BITS_PER_PIN;
2029 }
2030
2031 return 0;
2032 }
2033
2034 #define RK3288_PULL_OFFSET 0x140
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2035 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2036 int pin_num, struct regmap **regmap,
2037 int *reg, u8 *bit)
2038 {
2039 struct rockchip_pinctrl *info = bank->drvdata;
2040
2041 /* The first 24 pins of the first bank are located in PMU */
2042 if (bank->bank_num == 0) {
2043 *regmap = info->regmap_pmu;
2044 *reg = RK3188_PULL_PMU_OFFSET;
2045
2046 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2047 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2048 *bit *= RK3188_PULL_BITS_PER_PIN;
2049 } else {
2050 *regmap = info->regmap_base;
2051 *reg = RK3288_PULL_OFFSET;
2052
2053 /* correct the offset, as we're starting with the 2nd bank */
2054 *reg -= 0x10;
2055 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2056 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2057
2058 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2059 *bit *= RK3188_PULL_BITS_PER_PIN;
2060 }
2061
2062 return 0;
2063 }
2064
2065 #define RK3288_DRV_PMU_OFFSET 0x70
2066 #define RK3288_DRV_GRF_OFFSET 0x1c0
2067 #define RK3288_DRV_BITS_PER_PIN 2
2068 #define RK3288_DRV_PINS_PER_REG 8
2069 #define RK3288_DRV_BANK_STRIDE 16
2070
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2071 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2072 int pin_num, struct regmap **regmap,
2073 int *reg, u8 *bit)
2074 {
2075 struct rockchip_pinctrl *info = bank->drvdata;
2076
2077 /* The first 24 pins of the first bank are located in PMU */
2078 if (bank->bank_num == 0) {
2079 *regmap = info->regmap_pmu;
2080 *reg = RK3288_DRV_PMU_OFFSET;
2081
2082 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2083 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2084 *bit *= RK3288_DRV_BITS_PER_PIN;
2085 } else {
2086 *regmap = info->regmap_base;
2087 *reg = RK3288_DRV_GRF_OFFSET;
2088
2089 /* correct the offset, as we're starting with the 2nd bank */
2090 *reg -= 0x10;
2091 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2092 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2093
2094 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2095 *bit *= RK3288_DRV_BITS_PER_PIN;
2096 }
2097
2098 return 0;
2099 }
2100
2101 #define RK3228_PULL_OFFSET 0x100
2102
rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2103 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2104 int pin_num, struct regmap **regmap,
2105 int *reg, u8 *bit)
2106 {
2107 struct rockchip_pinctrl *info = bank->drvdata;
2108
2109 *regmap = info->regmap_base;
2110 *reg = RK3228_PULL_OFFSET;
2111 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2112 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2113
2114 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2115 *bit *= RK3188_PULL_BITS_PER_PIN;
2116
2117 return 0;
2118 }
2119
2120 #define RK3228_DRV_GRF_OFFSET 0x200
2121
rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2122 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2123 int pin_num, struct regmap **regmap,
2124 int *reg, u8 *bit)
2125 {
2126 struct rockchip_pinctrl *info = bank->drvdata;
2127
2128 *regmap = info->regmap_base;
2129 *reg = RK3228_DRV_GRF_OFFSET;
2130 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2131 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2132
2133 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2134 *bit *= RK3288_DRV_BITS_PER_PIN;
2135
2136 return 0;
2137 }
2138
2139 #define RK3308_PULL_OFFSET 0xa0
2140
rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2141 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2142 int pin_num, struct regmap **regmap,
2143 int *reg, u8 *bit)
2144 {
2145 struct rockchip_pinctrl *info = bank->drvdata;
2146
2147 *regmap = info->regmap_base;
2148 *reg = RK3308_PULL_OFFSET;
2149 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2150 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2151
2152 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2153 *bit *= RK3188_PULL_BITS_PER_PIN;
2154
2155 return 0;
2156 }
2157
2158 #define RK3308_DRV_GRF_OFFSET 0x100
2159
rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2160 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2161 int pin_num, struct regmap **regmap,
2162 int *reg, u8 *bit)
2163 {
2164 struct rockchip_pinctrl *info = bank->drvdata;
2165
2166 *regmap = info->regmap_base;
2167 *reg = RK3308_DRV_GRF_OFFSET;
2168 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2169 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2170
2171 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2172 *bit *= RK3288_DRV_BITS_PER_PIN;
2173
2174 return 0;
2175 }
2176
2177 #define RK3368_PULL_GRF_OFFSET 0x100
2178 #define RK3368_PULL_PMU_OFFSET 0x10
2179
rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2180 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2181 int pin_num, struct regmap **regmap,
2182 int *reg, u8 *bit)
2183 {
2184 struct rockchip_pinctrl *info = bank->drvdata;
2185
2186 /* The first 32 pins of the first bank are located in PMU */
2187 if (bank->bank_num == 0) {
2188 *regmap = info->regmap_pmu;
2189 *reg = RK3368_PULL_PMU_OFFSET;
2190
2191 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2192 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2193 *bit *= RK3188_PULL_BITS_PER_PIN;
2194 } else {
2195 *regmap = info->regmap_base;
2196 *reg = RK3368_PULL_GRF_OFFSET;
2197
2198 /* correct the offset, as we're starting with the 2nd bank */
2199 *reg -= 0x10;
2200 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2201 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2202
2203 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2204 *bit *= RK3188_PULL_BITS_PER_PIN;
2205 }
2206
2207 return 0;
2208 }
2209
2210 #define RK3368_DRV_PMU_OFFSET 0x20
2211 #define RK3368_DRV_GRF_OFFSET 0x200
2212
rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2213 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2214 int pin_num, struct regmap **regmap,
2215 int *reg, u8 *bit)
2216 {
2217 struct rockchip_pinctrl *info = bank->drvdata;
2218
2219 /* The first 32 pins of the first bank are located in PMU */
2220 if (bank->bank_num == 0) {
2221 *regmap = info->regmap_pmu;
2222 *reg = RK3368_DRV_PMU_OFFSET;
2223
2224 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2225 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
2226 *bit *= RK3288_DRV_BITS_PER_PIN;
2227 } else {
2228 *regmap = info->regmap_base;
2229 *reg = RK3368_DRV_GRF_OFFSET;
2230
2231 /* correct the offset, as we're starting with the 2nd bank */
2232 *reg -= 0x10;
2233 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
2234 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
2235
2236 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
2237 *bit *= RK3288_DRV_BITS_PER_PIN;
2238 }
2239
2240 return 0;
2241 }
2242
2243 #define RK3399_PULL_GRF_OFFSET 0xe040
2244 #define RK3399_PULL_PMU_OFFSET 0x40
2245 #define RK3399_DRV_3BITS_PER_PIN 3
2246
rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2247 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2248 int pin_num, struct regmap **regmap,
2249 int *reg, u8 *bit)
2250 {
2251 struct rockchip_pinctrl *info = bank->drvdata;
2252
2253 /* The bank0:16 and bank1:32 pins are located in PMU */
2254 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
2255 *regmap = info->regmap_pmu;
2256 *reg = RK3399_PULL_PMU_OFFSET;
2257
2258 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2259
2260 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2261 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
2262 *bit *= RK3188_PULL_BITS_PER_PIN;
2263 } else {
2264 *regmap = info->regmap_base;
2265 *reg = RK3399_PULL_GRF_OFFSET;
2266
2267 /* correct the offset, as we're starting with the 3rd bank */
2268 *reg -= 0x20;
2269 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
2270 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
2271
2272 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
2273 *bit *= RK3188_PULL_BITS_PER_PIN;
2274 }
2275
2276 return 0;
2277 }
2278
rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2279 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2280 int pin_num, struct regmap **regmap,
2281 int *reg, u8 *bit)
2282 {
2283 struct rockchip_pinctrl *info = bank->drvdata;
2284 int drv_num = (pin_num / 8);
2285
2286 /* The bank0:16 and bank1:32 pins are located in PMU */
2287 if ((bank->bank_num == 0) || (bank->bank_num == 1))
2288 *regmap = info->regmap_pmu;
2289 else
2290 *regmap = info->regmap_base;
2291
2292 *reg = bank->drv[drv_num].offset;
2293 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2294 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
2295 *bit = (pin_num % 8) * 3;
2296 else
2297 *bit = (pin_num % 8) * 2;
2298
2299 return 0;
2300 }
2301
2302 #define RK3506_DRV_BITS_PER_PIN 8
2303 #define RK3506_DRV_PINS_PER_REG 2
2304 #define RK3506_DRV_GPIO0_A_OFFSET 0x100
2305 #define RK3506_DRV_GPIO0_D_OFFSET 0x830
2306 #define RK3506_DRV_GPIO1_OFFSET 0x140
2307 #define RK3506_DRV_GPIO2_OFFSET 0x180
2308 #define RK3506_DRV_GPIO3_OFFSET 0x1c0
2309 #define RK3506_DRV_GPIO4_OFFSET 0x840
2310
rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2311 static int rk3506_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2312 int pin_num, struct regmap **regmap,
2313 int *reg, u8 *bit)
2314 {
2315 struct rockchip_pinctrl *info = bank->drvdata;
2316 int ret = 0;
2317
2318 switch (bank->bank_num) {
2319 case 0:
2320 *regmap = info->regmap_pmu;
2321 if (pin_num > 24) {
2322 ret = -EINVAL;
2323 } else if (pin_num < 24) {
2324 *reg = RK3506_DRV_GPIO0_A_OFFSET;
2325 } else {
2326 *reg = RK3506_DRV_GPIO0_D_OFFSET;
2327 *bit = 3;
2328
2329 return 0;
2330 }
2331 break;
2332
2333 case 1:
2334 *regmap = info->regmap_ioc1;
2335 if (pin_num < 28)
2336 *reg = RK3506_DRV_GPIO1_OFFSET;
2337 else
2338 ret = -EINVAL;
2339 break;
2340
2341 case 2:
2342 *regmap = info->regmap_base;
2343 if (pin_num < 17)
2344 *reg = RK3506_DRV_GPIO2_OFFSET;
2345 else
2346 ret = -EINVAL;
2347 break;
2348
2349 case 3:
2350 *regmap = info->regmap_base;
2351 if (pin_num < 15)
2352 *reg = RK3506_DRV_GPIO3_OFFSET;
2353 else
2354 ret = -EINVAL;
2355 break;
2356
2357 case 4:
2358 *regmap = info->regmap_base;
2359 if (pin_num < 8 || pin_num > 11) {
2360 ret = -EINVAL;
2361 } else {
2362 *reg = RK3506_DRV_GPIO4_OFFSET;
2363 *bit = 10;
2364
2365 return 0;
2366 }
2367 break;
2368
2369 default:
2370 ret = -EINVAL;
2371 break;
2372 }
2373
2374 if (ret) {
2375 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
2376
2377 return ret;
2378 }
2379
2380 *reg += ((pin_num / RK3506_DRV_PINS_PER_REG) * 4);
2381 *bit = pin_num % RK3506_DRV_PINS_PER_REG;
2382 *bit *= RK3506_DRV_BITS_PER_PIN;
2383
2384 return 0;
2385 }
2386
2387 #define RK3506_PULL_BITS_PER_PIN 2
2388 #define RK3506_PULL_PINS_PER_REG 8
2389 #define RK3506_PULL_GPIO0_A_OFFSET 0x200
2390 #define RK3506_PULL_GPIO0_D_OFFSET 0x830
2391 #define RK3506_PULL_GPIO1_OFFSET 0x210
2392 #define RK3506_PULL_GPIO2_OFFSET 0x220
2393 #define RK3506_PULL_GPIO3_OFFSET 0x230
2394 #define RK3506_PULL_GPIO4_OFFSET 0x840
2395
rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2396 static int rk3506_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2397 int pin_num, struct regmap **regmap,
2398 int *reg, u8 *bit)
2399 {
2400 struct rockchip_pinctrl *info = bank->drvdata;
2401 int ret = 0;
2402
2403 switch (bank->bank_num) {
2404 case 0:
2405 *regmap = info->regmap_pmu;
2406 if (pin_num > 24) {
2407 ret = -EINVAL;
2408 } else if (pin_num < 24) {
2409 *reg = RK3506_PULL_GPIO0_A_OFFSET;
2410 } else {
2411 *reg = RK3506_PULL_GPIO0_D_OFFSET;
2412 *bit = 5;
2413
2414 return 0;
2415 }
2416 break;
2417
2418 case 1:
2419 *regmap = info->regmap_ioc1;
2420 if (pin_num < 28)
2421 *reg = RK3506_PULL_GPIO1_OFFSET;
2422 else
2423 ret = -EINVAL;
2424 break;
2425
2426 case 2:
2427 *regmap = info->regmap_base;
2428 if (pin_num < 17)
2429 *reg = RK3506_PULL_GPIO2_OFFSET;
2430 else
2431 ret = -EINVAL;
2432 break;
2433
2434 case 3:
2435 *regmap = info->regmap_base;
2436 if (pin_num < 15)
2437 *reg = RK3506_PULL_GPIO3_OFFSET;
2438 else
2439 ret = -EINVAL;
2440 break;
2441
2442 case 4:
2443 *regmap = info->regmap_base;
2444 if (pin_num < 8 || pin_num > 11) {
2445 ret = -EINVAL;
2446 } else {
2447 *reg = RK3506_PULL_GPIO4_OFFSET;
2448 *bit = 13;
2449
2450 return 0;
2451 }
2452 break;
2453
2454 default:
2455 ret = -EINVAL;
2456 break;
2457 }
2458
2459 if (ret) {
2460 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
2461
2462 return ret;
2463 }
2464
2465 *reg += ((pin_num / RK3506_PULL_PINS_PER_REG) * 4);
2466 *bit = pin_num % RK3506_PULL_PINS_PER_REG;
2467 *bit *= RK3506_PULL_BITS_PER_PIN;
2468
2469 return 0;
2470 }
2471
2472 #define RK3506_SMT_BITS_PER_PIN 1
2473 #define RK3506_SMT_PINS_PER_REG 8
2474 #define RK3506_SMT_GPIO0_A_OFFSET 0x400
2475 #define RK3506_SMT_GPIO0_D_OFFSET 0x830
2476 #define RK3506_SMT_GPIO1_OFFSET 0x410
2477 #define RK3506_SMT_GPIO2_OFFSET 0x420
2478 #define RK3506_SMT_GPIO3_OFFSET 0x430
2479 #define RK3506_SMT_GPIO4_OFFSET 0x840
2480
rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2481 static int rk3506_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2482 int pin_num,
2483 struct regmap **regmap,
2484 int *reg, u8 *bit)
2485 {
2486 struct rockchip_pinctrl *info = bank->drvdata;
2487 int ret = 0;
2488
2489 switch (bank->bank_num) {
2490 case 0:
2491 *regmap = info->regmap_pmu;
2492 if (pin_num > 24) {
2493 ret = -EINVAL;
2494 } else if (pin_num < 24) {
2495 *reg = RK3506_SMT_GPIO0_A_OFFSET;
2496 } else {
2497 *reg = RK3506_SMT_GPIO0_D_OFFSET;
2498 *bit = 9;
2499
2500 return 0;
2501 }
2502 break;
2503
2504 case 1:
2505 *regmap = info->regmap_ioc1;
2506 if (pin_num < 28)
2507 *reg = RK3506_SMT_GPIO1_OFFSET;
2508 else
2509 ret = -EINVAL;
2510 break;
2511
2512 case 2:
2513 *regmap = info->regmap_base;
2514 if (pin_num < 17)
2515 *reg = RK3506_SMT_GPIO2_OFFSET;
2516 else
2517 ret = -EINVAL;
2518 break;
2519
2520 case 3:
2521 *regmap = info->regmap_base;
2522 if (pin_num < 15)
2523 *reg = RK3506_SMT_GPIO3_OFFSET;
2524 else
2525 ret = -EINVAL;
2526 break;
2527
2528 case 4:
2529 *regmap = info->regmap_base;
2530 if (pin_num < 8 || pin_num > 11) {
2531 ret = -EINVAL;
2532 } else {
2533 *reg = RK3506_SMT_GPIO4_OFFSET;
2534 *bit = 8;
2535
2536 return 0;
2537 }
2538 break;
2539
2540 default:
2541 ret = -EINVAL;
2542 break;
2543 }
2544
2545 if (ret) {
2546 dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
2547
2548 return ret;
2549 }
2550
2551 *reg += ((pin_num / RK3506_SMT_PINS_PER_REG) * 4);
2552 *bit = pin_num % RK3506_SMT_PINS_PER_REG;
2553 *bit *= RK3506_SMT_BITS_PER_PIN;
2554
2555 return 0;
2556 }
2557
2558 #define RK3528_DRV_BITS_PER_PIN 8
2559 #define RK3528_DRV_PINS_PER_REG 2
2560 #define RK3528_DRV_GPIO0_OFFSET 0x100
2561 #define RK3528_DRV_GPIO1_OFFSET 0x20120
2562 #define RK3528_DRV_GPIO2_OFFSET 0x30160
2563 #define RK3528_DRV_GPIO3_OFFSET 0x20190
2564 #define RK3528_DRV_GPIO4_OFFSET 0x101C0
2565
rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2566 static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2567 int pin_num, struct regmap **regmap,
2568 int *reg, u8 *bit)
2569 {
2570 struct rockchip_pinctrl *info = bank->drvdata;
2571
2572 *regmap = info->regmap_base;
2573
2574 if (bank->bank_num == 0)
2575 *reg = RK3528_DRV_GPIO0_OFFSET;
2576 else if (bank->bank_num == 1)
2577 *reg = RK3528_DRV_GPIO1_OFFSET;
2578 else if (bank->bank_num == 2)
2579 *reg = RK3528_DRV_GPIO2_OFFSET;
2580 else if (bank->bank_num == 3)
2581 *reg = RK3528_DRV_GPIO3_OFFSET;
2582 else if (bank->bank_num == 4)
2583 *reg = RK3528_DRV_GPIO4_OFFSET;
2584 else
2585 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2586
2587 *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
2588 *bit = pin_num % RK3528_DRV_PINS_PER_REG;
2589 *bit *= RK3528_DRV_BITS_PER_PIN;
2590
2591 return 0;
2592 }
2593
2594 #define RK3528_PULL_BITS_PER_PIN 2
2595 #define RK3528_PULL_PINS_PER_REG 8
2596 #define RK3528_PULL_GPIO0_OFFSET 0x200
2597 #define RK3528_PULL_GPIO1_OFFSET 0x20210
2598 #define RK3528_PULL_GPIO2_OFFSET 0x30220
2599 #define RK3528_PULL_GPIO3_OFFSET 0x20230
2600 #define RK3528_PULL_GPIO4_OFFSET 0x10240
2601
rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2602 static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2603 int pin_num, struct regmap **regmap,
2604 int *reg, u8 *bit)
2605 {
2606 struct rockchip_pinctrl *info = bank->drvdata;
2607
2608 *regmap = info->regmap_base;
2609
2610 if (bank->bank_num == 0)
2611 *reg = RK3528_PULL_GPIO0_OFFSET;
2612 else if (bank->bank_num == 1)
2613 *reg = RK3528_PULL_GPIO1_OFFSET;
2614 else if (bank->bank_num == 2)
2615 *reg = RK3528_PULL_GPIO2_OFFSET;
2616 else if (bank->bank_num == 3)
2617 *reg = RK3528_PULL_GPIO3_OFFSET;
2618 else if (bank->bank_num == 4)
2619 *reg = RK3528_PULL_GPIO4_OFFSET;
2620 else
2621 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2622
2623 *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
2624 *bit = pin_num % RK3528_PULL_PINS_PER_REG;
2625 *bit *= RK3528_PULL_BITS_PER_PIN;
2626
2627 return 0;
2628 }
2629
2630 #define RK3528_SMT_BITS_PER_PIN 1
2631 #define RK3528_SMT_PINS_PER_REG 8
2632 #define RK3528_SMT_GPIO0_OFFSET 0x400
2633 #define RK3528_SMT_GPIO1_OFFSET 0x20410
2634 #define RK3528_SMT_GPIO2_OFFSET 0x30420
2635 #define RK3528_SMT_GPIO3_OFFSET 0x20430
2636 #define RK3528_SMT_GPIO4_OFFSET 0x10440
2637
rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2638 static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2639 int pin_num,
2640 struct regmap **regmap,
2641 int *reg, u8 *bit)
2642 {
2643 struct rockchip_pinctrl *info = bank->drvdata;
2644
2645 *regmap = info->regmap_base;
2646
2647 if (bank->bank_num == 0)
2648 *reg = RK3528_SMT_GPIO0_OFFSET;
2649 else if (bank->bank_num == 1)
2650 *reg = RK3528_SMT_GPIO1_OFFSET;
2651 else if (bank->bank_num == 2)
2652 *reg = RK3528_SMT_GPIO2_OFFSET;
2653 else if (bank->bank_num == 3)
2654 *reg = RK3528_SMT_GPIO3_OFFSET;
2655 else if (bank->bank_num == 4)
2656 *reg = RK3528_SMT_GPIO4_OFFSET;
2657 else
2658 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2659
2660 *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
2661 *bit = pin_num % RK3528_SMT_PINS_PER_REG;
2662 *bit *= RK3528_SMT_BITS_PER_PIN;
2663
2664 return 0;
2665 }
2666
2667 #define RK3562_DRV_BITS_PER_PIN 8
2668 #define RK3562_DRV_PINS_PER_REG 2
2669 #define RK3562_DRV_GPIO0_OFFSET 0x20070
2670 #define RK3562_DRV_GPIO1_OFFSET 0x200
2671 #define RK3562_DRV_GPIO2_OFFSET 0x240
2672 #define RK3562_DRV_GPIO3_OFFSET 0x10280
2673 #define RK3562_DRV_GPIO4_OFFSET 0x102C0
2674
rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2675 static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2676 int pin_num, struct regmap **regmap,
2677 int *reg, u8 *bit)
2678 {
2679 struct rockchip_pinctrl *info = bank->drvdata;
2680
2681 *regmap = info->regmap_base;
2682 switch (bank->bank_num) {
2683 case 0:
2684 *reg = RK3562_DRV_GPIO0_OFFSET;
2685 break;
2686
2687 case 1:
2688 *reg = RK3562_DRV_GPIO1_OFFSET;
2689 break;
2690
2691 case 2:
2692 *reg = RK3562_DRV_GPIO2_OFFSET;
2693 break;
2694
2695 case 3:
2696 *reg = RK3562_DRV_GPIO3_OFFSET;
2697 break;
2698
2699 case 4:
2700 *reg = RK3562_DRV_GPIO4_OFFSET;
2701 break;
2702
2703 default:
2704 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2705 break;
2706 }
2707
2708 *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
2709 *bit = pin_num % RK3562_DRV_PINS_PER_REG;
2710 *bit *= RK3562_DRV_BITS_PER_PIN;
2711
2712 return 0;
2713 }
2714
2715 #define RK3562_PULL_BITS_PER_PIN 2
2716 #define RK3562_PULL_PINS_PER_REG 8
2717 #define RK3562_PULL_GPIO0_OFFSET 0x20020
2718 #define RK3562_PULL_GPIO1_OFFSET 0x80
2719 #define RK3562_PULL_GPIO2_OFFSET 0x90
2720 #define RK3562_PULL_GPIO3_OFFSET 0x100A0
2721 #define RK3562_PULL_GPIO4_OFFSET 0x100B0
2722
rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2723 static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2724 int pin_num, struct regmap **regmap,
2725 int *reg, u8 *bit)
2726 {
2727 struct rockchip_pinctrl *info = bank->drvdata;
2728
2729 *regmap = info->regmap_base;
2730 switch (bank->bank_num) {
2731 case 0:
2732 *reg = RK3562_PULL_GPIO0_OFFSET;
2733 break;
2734
2735 case 1:
2736 *reg = RK3562_PULL_GPIO1_OFFSET;
2737 break;
2738
2739 case 2:
2740 *reg = RK3562_PULL_GPIO2_OFFSET;
2741 break;
2742
2743 case 3:
2744 *reg = RK3562_PULL_GPIO3_OFFSET;
2745 break;
2746
2747 case 4:
2748 *reg = RK3562_PULL_GPIO4_OFFSET;
2749 break;
2750
2751 default:
2752 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2753 break;
2754 }
2755
2756 *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
2757 *bit = pin_num % RK3562_PULL_PINS_PER_REG;
2758 *bit *= RK3562_PULL_BITS_PER_PIN;
2759
2760 return 0;
2761 }
2762
2763 #define RK3562_SMT_BITS_PER_PIN 2
2764 #define RK3562_SMT_PINS_PER_REG 8
2765 #define RK3562_SMT_GPIO0_OFFSET 0x20030
2766 #define RK3562_SMT_GPIO1_OFFSET 0xC0
2767 #define RK3562_SMT_GPIO2_OFFSET 0xD0
2768 #define RK3562_SMT_GPIO3_OFFSET 0x100E0
2769 #define RK3562_SMT_GPIO4_OFFSET 0x100F0
2770
rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2771 static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2772 int pin_num,
2773 struct regmap **regmap,
2774 int *reg, u8 *bit)
2775 {
2776 struct rockchip_pinctrl *info = bank->drvdata;
2777
2778 *regmap = info->regmap_base;
2779 switch (bank->bank_num) {
2780 case 0:
2781 *reg = RK3562_SMT_GPIO0_OFFSET;
2782 break;
2783
2784 case 1:
2785 *reg = RK3562_SMT_GPIO1_OFFSET;
2786 break;
2787
2788 case 2:
2789 *reg = RK3562_SMT_GPIO2_OFFSET;
2790 break;
2791
2792 case 3:
2793 *reg = RK3562_SMT_GPIO3_OFFSET;
2794 break;
2795
2796 case 4:
2797 *reg = RK3562_SMT_GPIO4_OFFSET;
2798 break;
2799
2800 default:
2801 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2802 break;
2803 }
2804
2805 *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
2806 *bit = pin_num % RK3562_SMT_PINS_PER_REG;
2807 *bit *= RK3562_SMT_BITS_PER_PIN;
2808
2809 return 0;
2810 }
2811
2812 #define RK3568_PULL_PMU_OFFSET 0x20
2813 #define RK3568_PULL_GRF_OFFSET 0x80
2814 #define RK3568_PULL_BITS_PER_PIN 2
2815 #define RK3568_PULL_PINS_PER_REG 8
2816 #define RK3568_PULL_BANK_STRIDE 0x10
2817
rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2818 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2819 int pin_num, struct regmap **regmap,
2820 int *reg, u8 *bit)
2821 {
2822 struct rockchip_pinctrl *info = bank->drvdata;
2823
2824 if (bank->bank_num == 0) {
2825 *regmap = info->regmap_pmu;
2826 *reg = RK3568_PULL_PMU_OFFSET;
2827 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
2828 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2829
2830 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
2831 *bit *= RK3568_PULL_BITS_PER_PIN;
2832 } else {
2833 *regmap = info->regmap_base;
2834 *reg = RK3568_PULL_GRF_OFFSET;
2835 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
2836 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2837
2838 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2839 *bit *= RK3568_PULL_BITS_PER_PIN;
2840 }
2841
2842 return 0;
2843 }
2844
2845 #define RK3568_DRV_PMU_OFFSET 0x70
2846 #define RK3568_DRV_GRF_OFFSET 0x200
2847 #define RK3568_DRV_BITS_PER_PIN 8
2848 #define RK3568_DRV_PINS_PER_REG 2
2849 #define RK3568_DRV_BANK_STRIDE 0x40
2850
rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2851 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2852 int pin_num, struct regmap **regmap,
2853 int *reg, u8 *bit)
2854 {
2855 struct rockchip_pinctrl *info = bank->drvdata;
2856
2857 /* The first 32 pins of the first bank are located in PMU */
2858 if (bank->bank_num == 0) {
2859 *regmap = info->regmap_pmu;
2860 *reg = RK3568_DRV_PMU_OFFSET;
2861 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2862
2863 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
2864 *bit *= RK3568_DRV_BITS_PER_PIN;
2865 } else {
2866 *regmap = info->regmap_base;
2867 *reg = RK3568_DRV_GRF_OFFSET;
2868 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2869 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2870
2871 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2872 *bit *= RK3568_DRV_BITS_PER_PIN;
2873 }
2874
2875 return 0;
2876 }
2877
2878 #define RK3576_DRV_BITS_PER_PIN 4
2879 #define RK3576_DRV_PINS_PER_REG 4
2880 #define RK3576_DRV_GPIO0_AL_OFFSET 0x10
2881 #define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
2882 #define RK3576_DRV_GPIO1_OFFSET 0x6020
2883 #define RK3576_DRV_GPIO2_OFFSET 0x6040
2884 #define RK3576_DRV_GPIO3_OFFSET 0x6060
2885 #define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
2886 #define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
2887 #define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
2888
rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2889 static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2890 int pin_num, struct regmap **regmap,
2891 int *reg, u8 *bit)
2892 {
2893 struct rockchip_pinctrl *info = bank->drvdata;
2894
2895 *regmap = info->regmap_base;
2896
2897 if (bank->bank_num == 0 && pin_num < 12)
2898 *reg = RK3576_DRV_GPIO0_AL_OFFSET;
2899 else if (bank->bank_num == 0)
2900 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
2901 else if (bank->bank_num == 1)
2902 *reg = RK3576_DRV_GPIO1_OFFSET;
2903 else if (bank->bank_num == 2)
2904 *reg = RK3576_DRV_GPIO2_OFFSET;
2905 else if (bank->bank_num == 3)
2906 *reg = RK3576_DRV_GPIO3_OFFSET;
2907 else if (bank->bank_num == 4 && pin_num < 16)
2908 *reg = RK3576_DRV_GPIO4_AL_OFFSET;
2909 else if (bank->bank_num == 4 && pin_num < 24)
2910 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
2911 else if (bank->bank_num == 4)
2912 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
2913 else
2914 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2915
2916 *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
2917 *bit = pin_num % RK3576_DRV_PINS_PER_REG;
2918 *bit *= RK3576_DRV_BITS_PER_PIN;
2919
2920 return 0;
2921 }
2922
2923 #define RK3576_PULL_BITS_PER_PIN 2
2924 #define RK3576_PULL_PINS_PER_REG 8
2925 #define RK3576_PULL_GPIO0_AL_OFFSET 0x20
2926 #define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
2927 #define RK3576_PULL_GPIO1_OFFSET 0x6110
2928 #define RK3576_PULL_GPIO2_OFFSET 0x6120
2929 #define RK3576_PULL_GPIO3_OFFSET 0x6130
2930 #define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
2931 #define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
2932 #define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
2933
rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2934 static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2935 int pin_num, struct regmap **regmap,
2936 int *reg, u8 *bit)
2937 {
2938 struct rockchip_pinctrl *info = bank->drvdata;
2939
2940 *regmap = info->regmap_base;
2941
2942 if (bank->bank_num == 0 && pin_num < 12)
2943 *reg = RK3576_PULL_GPIO0_AL_OFFSET;
2944 else if (bank->bank_num == 0)
2945 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
2946 else if (bank->bank_num == 1)
2947 *reg = RK3576_PULL_GPIO1_OFFSET;
2948 else if (bank->bank_num == 2)
2949 *reg = RK3576_PULL_GPIO2_OFFSET;
2950 else if (bank->bank_num == 3)
2951 *reg = RK3576_PULL_GPIO3_OFFSET;
2952 else if (bank->bank_num == 4 && pin_num < 16)
2953 *reg = RK3576_PULL_GPIO4_AL_OFFSET;
2954 else if (bank->bank_num == 4 && pin_num < 24)
2955 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
2956 else if (bank->bank_num == 4)
2957 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
2958 else
2959 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2960
2961 *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
2962 *bit = pin_num % RK3576_PULL_PINS_PER_REG;
2963 *bit *= RK3576_PULL_BITS_PER_PIN;
2964
2965 return 0;
2966 }
2967
2968 #define RK3576_SMT_BITS_PER_PIN 1
2969 #define RK3576_SMT_PINS_PER_REG 8
2970 #define RK3576_SMT_GPIO0_AL_OFFSET 0x30
2971 #define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
2972 #define RK3576_SMT_GPIO1_OFFSET 0x6210
2973 #define RK3576_SMT_GPIO2_OFFSET 0x6220
2974 #define RK3576_SMT_GPIO3_OFFSET 0x6230
2975 #define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
2976 #define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
2977 #define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
2978
rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)2979 static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2980 int pin_num,
2981 struct regmap **regmap,
2982 int *reg, u8 *bit)
2983 {
2984 struct rockchip_pinctrl *info = bank->drvdata;
2985
2986 *regmap = info->regmap_base;
2987
2988 if (bank->bank_num == 0 && pin_num < 12)
2989 *reg = RK3576_SMT_GPIO0_AL_OFFSET;
2990 else if (bank->bank_num == 0)
2991 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
2992 else if (bank->bank_num == 1)
2993 *reg = RK3576_SMT_GPIO1_OFFSET;
2994 else if (bank->bank_num == 2)
2995 *reg = RK3576_SMT_GPIO2_OFFSET;
2996 else if (bank->bank_num == 3)
2997 *reg = RK3576_SMT_GPIO3_OFFSET;
2998 else if (bank->bank_num == 4 && pin_num < 16)
2999 *reg = RK3576_SMT_GPIO4_AL_OFFSET;
3000 else if (bank->bank_num == 4 && pin_num < 24)
3001 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
3002 else if (bank->bank_num == 4)
3003 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
3004 else
3005 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
3006
3007 *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
3008 *bit = pin_num % RK3576_SMT_PINS_PER_REG;
3009 *bit *= RK3576_SMT_BITS_PER_PIN;
3010
3011 return 0;
3012 }
3013
3014 #define RK3588_PMU1_IOC_REG (0x0000)
3015 #define RK3588_PMU2_IOC_REG (0x4000)
3016 #define RK3588_BUS_IOC_REG (0x8000)
3017 #define RK3588_VCCIO1_4_IOC_REG (0x9000)
3018 #define RK3588_VCCIO3_5_IOC_REG (0xA000)
3019 #define RK3588_VCCIO2_IOC_REG (0xB000)
3020 #define RK3588_VCCIO6_IOC_REG (0xC000)
3021 #define RK3588_EMMC_IOC_REG (0xD000)
3022
3023 static const u32 rk3588_ds_regs[][2] = {
3024 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
3025 {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
3026 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
3027 {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
3028 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
3029 {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
3030 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
3031 {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
3032 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
3033 {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
3034 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
3035 {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
3036 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
3037 {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
3038 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
3039 {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
3040 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
3041 {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
3042 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
3043 {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
3044 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
3045 {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
3046 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
3047 {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
3048 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
3049 {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
3050 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
3051 {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
3052 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
3053 {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
3054 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
3055 {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
3056 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
3057 {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
3058 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
3059 {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
3060 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
3061 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
3062 {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
3063 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
3064 {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
3065 };
3066
3067 static const u32 rk3588_p_regs[][2] = {
3068 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
3069 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
3070 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
3071 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
3072 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
3073 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
3074 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
3075 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
3076 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
3077 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
3078 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
3079 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
3080 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
3081 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
3082 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
3083 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
3084 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
3085 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
3086 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
3087 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
3088 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
3089 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
3090 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
3091 };
3092
3093 static const u32 rk3588_smt_regs[][2] = {
3094 {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
3095 {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
3096 {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
3097 {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
3098 {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
3099 {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
3100 {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
3101 {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
3102 {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
3103 {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
3104 {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
3105 {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
3106 {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
3107 {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
3108 {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
3109 {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
3110 {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
3111 {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
3112 {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
3113 {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
3114 {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
3115 {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
3116 {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
3117 };
3118
3119 #define RK3588_PULL_BITS_PER_PIN 2
3120 #define RK3588_PULL_PINS_PER_REG 8
3121
rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3122 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
3123 int pin_num, struct regmap **regmap,
3124 int *reg, u8 *bit)
3125 {
3126 struct rockchip_pinctrl *info = bank->drvdata;
3127 u8 bank_num = bank->bank_num;
3128 u32 pin = bank_num * 32 + pin_num;
3129 int i;
3130
3131 for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
3132 if (pin >= rk3588_p_regs[i][0]) {
3133 *reg = rk3588_p_regs[i][1];
3134 *regmap = info->regmap_base;
3135 *bit = pin_num % RK3588_PULL_PINS_PER_REG;
3136 *bit *= RK3588_PULL_BITS_PER_PIN;
3137 return 0;
3138 }
3139 }
3140
3141 return -EINVAL;
3142 }
3143
3144 #define RK3588_DRV_BITS_PER_PIN 4
3145 #define RK3588_DRV_PINS_PER_REG 4
3146
rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3147 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
3148 int pin_num, struct regmap **regmap,
3149 int *reg, u8 *bit)
3150 {
3151 struct rockchip_pinctrl *info = bank->drvdata;
3152 u8 bank_num = bank->bank_num;
3153 u32 pin = bank_num * 32 + pin_num;
3154 int i;
3155
3156 for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
3157 if (pin >= rk3588_ds_regs[i][0]) {
3158 *reg = rk3588_ds_regs[i][1];
3159 *regmap = info->regmap_base;
3160 *bit = pin_num % RK3588_DRV_PINS_PER_REG;
3161 *bit *= RK3588_DRV_BITS_PER_PIN;
3162 return 0;
3163 }
3164 }
3165
3166 return -EINVAL;
3167 }
3168
3169 #define RK3588_SMT_BITS_PER_PIN 1
3170 #define RK3588_SMT_PINS_PER_REG 8
3171
rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3172 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3173 int pin_num,
3174 struct regmap **regmap,
3175 int *reg, u8 *bit)
3176 {
3177 struct rockchip_pinctrl *info = bank->drvdata;
3178 u8 bank_num = bank->bank_num;
3179 u32 pin = bank_num * 32 + pin_num;
3180 int i;
3181
3182 for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
3183 if (pin >= rk3588_smt_regs[i][0]) {
3184 *reg = rk3588_smt_regs[i][1];
3185 *regmap = info->regmap_base;
3186 *bit = pin_num % RK3588_SMT_PINS_PER_REG;
3187 *bit *= RK3588_SMT_BITS_PER_PIN;
3188 return 0;
3189 }
3190 }
3191
3192 return -EINVAL;
3193 }
3194
3195 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
3196 { 2, 4, 8, 12, -1, -1, -1, -1 },
3197 { 3, 6, 9, 12, -1, -1, -1, -1 },
3198 { 5, 10, 15, 20, -1, -1, -1, -1 },
3199 { 4, 6, 8, 10, 12, 14, 16, 18 },
3200 { 4, 7, 10, 13, 16, 19, 22, 26 }
3201 };
3202
rockchip_get_drive_perpin(struct rockchip_pin_bank * bank,int pin_num)3203 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
3204 int pin_num)
3205 {
3206 struct rockchip_pinctrl *info = bank->drvdata;
3207 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3208 struct device *dev = info->dev;
3209 struct regmap *regmap;
3210 int reg, ret;
3211 u32 data, temp, rmask_bits;
3212 u8 bit;
3213 int drv_type = bank->drv[pin_num / 8].drv_type;
3214
3215 if (ctrl->type == RV1103B && pin_num >= 12)
3216 drv_type = DRV_TYPE_IO_LEVEL_2_BIT;
3217
3218 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
3219 if (ret)
3220 return ret;
3221
3222 switch (drv_type) {
3223 case DRV_TYPE_IO_1V8_3V0_AUTO:
3224 case DRV_TYPE_IO_3V3_ONLY:
3225 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
3226 switch (bit) {
3227 case 0 ... 12:
3228 /* regular case, nothing to do */
3229 break;
3230 case 15:
3231 /*
3232 * drive-strength offset is special, as it is
3233 * spread over 2 registers
3234 */
3235 ret = regmap_read(regmap, reg, &data);
3236 if (ret)
3237 return ret;
3238
3239 ret = regmap_read(regmap, reg + 0x4, &temp);
3240 if (ret)
3241 return ret;
3242
3243 /*
3244 * the bit data[15] contains bit 0 of the value
3245 * while temp[1:0] contains bits 2 and 1
3246 */
3247 data >>= 15;
3248 temp &= 0x3;
3249 temp <<= 1;
3250 data |= temp;
3251
3252 return rockchip_perpin_drv_list[drv_type][data];
3253 case 18 ... 21:
3254 /* setting fully enclosed in the second register */
3255 reg += 4;
3256 bit -= 16;
3257 break;
3258 default:
3259 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
3260 bit, drv_type);
3261 return -EINVAL;
3262 }
3263
3264 break;
3265 case DRV_TYPE_IO_DEFAULT:
3266 case DRV_TYPE_IO_1V8_OR_3V0:
3267 case DRV_TYPE_IO_1V8_ONLY:
3268 rmask_bits = RK3288_DRV_BITS_PER_PIN;
3269 break;
3270 default:
3271 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
3272 return -EINVAL;
3273 }
3274
3275 ret = regmap_read(regmap, reg, &data);
3276 if (ret)
3277 return ret;
3278
3279 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3280 data = data >> 10;
3281 return data & 0x3;
3282 }
3283
3284 data >>= bit;
3285 data &= (1 << rmask_bits) - 1;
3286
3287 return rockchip_perpin_drv_list[drv_type][data];
3288 }
3289
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)3290 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
3291 int pin_num, int strength)
3292 {
3293 struct rockchip_pinctrl *info = bank->drvdata;
3294 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3295 struct device *dev = info->dev;
3296 struct regmap *regmap;
3297 int reg, ret, i;
3298 u32 data, rmask, rmask_bits, temp;
3299 u8 bit;
3300 int drv_type = bank->drv[pin_num / 8].drv_type;
3301
3302 dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
3303 bank->bank_num, pin_num, strength);
3304
3305 ret = ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
3306 if (ret)
3307 return ret;
3308 if (ctrl->type == RK3588) {
3309 rmask_bits = RK3588_DRV_BITS_PER_PIN;
3310 ret = strength;
3311 goto config;
3312 } else if (ctrl->type == RV1103B ||
3313 ctrl->type == RK3506 ||
3314 ctrl->type == RK3528 ||
3315 ctrl->type == RK3562 ||
3316 ctrl->type == RK3568) {
3317 rmask_bits = RK3568_DRV_BITS_PER_PIN;
3318 ret = (1 << (strength + 1)) - 1;
3319 goto config;
3320 } else if (ctrl->type == RK3576) {
3321 rmask_bits = RK3576_DRV_BITS_PER_PIN;
3322 ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
3323 goto config;
3324 }
3325
3326 if (ctrl->type == RV1126) {
3327 rmask_bits = RV1126_DRV_BITS_PER_PIN;
3328 ret = strength;
3329 goto config;
3330 }
3331
3332 ret = -EINVAL;
3333 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
3334 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
3335 ret = i;
3336 break;
3337 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
3338 ret = rockchip_perpin_drv_list[drv_type][i];
3339 break;
3340 }
3341 }
3342
3343 if (ret < 0) {
3344 dev_err(dev, "unsupported driver strength %d\n", strength);
3345 return ret;
3346 }
3347
3348 switch (drv_type) {
3349 case DRV_TYPE_IO_1V8_3V0_AUTO:
3350 case DRV_TYPE_IO_3V3_ONLY:
3351 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
3352 switch (bit) {
3353 case 0 ... 12:
3354 /* regular case, nothing to do */
3355 break;
3356 case 15:
3357 /*
3358 * drive-strength offset is special, as it is spread
3359 * over 2 registers, the bit data[15] contains bit 0
3360 * of the value while temp[1:0] contains bits 2 and 1
3361 */
3362 data = (ret & 0x1) << 15;
3363 temp = (ret >> 0x1) & 0x3;
3364
3365 rmask = BIT(15) | BIT(31);
3366 data |= BIT(31);
3367 ret = regmap_update_bits(regmap, reg, rmask, data);
3368 if (ret)
3369 return ret;
3370
3371 rmask = 0x3 | (0x3 << 16);
3372 temp |= (0x3 << 16);
3373 reg += 0x4;
3374 ret = regmap_update_bits(regmap, reg, rmask, temp);
3375
3376 return ret;
3377 case 18 ... 21:
3378 /* setting fully enclosed in the second register */
3379 reg += 4;
3380 bit -= 16;
3381 break;
3382 default:
3383 dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
3384 bit, drv_type);
3385 return -EINVAL;
3386 }
3387 break;
3388 case DRV_TYPE_IO_DEFAULT:
3389 case DRV_TYPE_IO_1V8_OR_3V0:
3390 case DRV_TYPE_IO_1V8_ONLY:
3391 rmask_bits = RK3288_DRV_BITS_PER_PIN;
3392 break;
3393 case DRV_TYPE_IO_LEVEL_2_BIT:
3394 ret = regmap_read(regmap, reg, &data);
3395 if (ret)
3396 return ret;
3397 data >>= bit;
3398
3399 return data & 0x3;
3400 case DRV_TYPE_IO_LEVEL_8_BIT:
3401 ret = regmap_read(regmap, reg, &data);
3402 if (ret)
3403 return ret;
3404 data >>= bit;
3405 data &= (1 << 8) - 1;
3406
3407 ret = hweight8(data);
3408 if (ret > 0)
3409 return ret - 1;
3410 else
3411 return -EINVAL;
3412 default:
3413 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
3414 return -EINVAL;
3415 }
3416
3417 config:
3418 if (ctrl->type == RK3506) {
3419 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
3420 rmask_bits = 2;
3421 ret = strength;
3422 }
3423 }
3424
3425 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3426 rmask_bits = 2;
3427 ret = strength;
3428 }
3429
3430 /* enable the write to the equivalent lower bits */
3431 data = ((1 << rmask_bits) - 1) << (bit + 16);
3432 rmask = data | (data >> 16);
3433 data |= (ret << bit);
3434
3435 ret = regmap_update_bits(regmap, reg, rmask, data);
3436
3437 return ret;
3438 }
3439
3440 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
3441 {
3442 PIN_CONFIG_BIAS_DISABLE,
3443 PIN_CONFIG_BIAS_PULL_UP,
3444 PIN_CONFIG_BIAS_PULL_DOWN,
3445 PIN_CONFIG_BIAS_BUS_HOLD
3446 },
3447 {
3448 PIN_CONFIG_BIAS_DISABLE,
3449 PIN_CONFIG_BIAS_PULL_DOWN,
3450 PIN_CONFIG_BIAS_DISABLE,
3451 PIN_CONFIG_BIAS_PULL_UP
3452 },
3453 };
3454
rockchip_get_pull(struct rockchip_pin_bank * bank,int pin_num)3455 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
3456 {
3457 struct rockchip_pinctrl *info = bank->drvdata;
3458 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3459 struct device *dev = info->dev;
3460 struct regmap *regmap;
3461 int reg, ret, pull_type;
3462 u8 bit;
3463 u32 data;
3464
3465 /* rk3066b does support any pulls */
3466 if (ctrl->type == RK3066B)
3467 return PIN_CONFIG_BIAS_DISABLE;
3468
3469 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
3470 if (ret)
3471 return ret;
3472
3473 ret = regmap_read(regmap, reg, &data);
3474 if (ret)
3475 return ret;
3476
3477 switch (ctrl->type) {
3478 case RK2928:
3479 case RK3128:
3480 return !(data & BIT(bit))
3481 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
3482 : PIN_CONFIG_BIAS_DISABLE;
3483 case PX30:
3484 case RV1103B:
3485 case RV1108:
3486 case RK3188:
3487 case RK3288:
3488 case RK3308:
3489 case RK3328:
3490 case RK3368:
3491 case RK3399:
3492 case RK3528:
3493 case RK3562:
3494 case RK3568:
3495 case RK3576:
3496 case RK3588:
3497 pull_type = bank->pull_type[pin_num / 8];
3498 data >>= bit;
3499 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
3500
3501 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
3502 pull_type = 1;
3503 /*
3504 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
3505 * where that pull up value becomes 3.
3506 */
3507 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
3508 if (data == 3)
3509 data = 1;
3510 }
3511
3512 return rockchip_pull_list[pull_type][data];
3513 default:
3514 dev_err(dev, "unsupported pinctrl type\n");
3515 return -EINVAL;
3516 };
3517 }
3518
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)3519 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
3520 int pin_num, int pull)
3521 {
3522 struct rockchip_pinctrl *info = bank->drvdata;
3523 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3524 struct device *dev = info->dev;
3525 struct regmap *regmap;
3526 int reg, ret, i, pull_type;
3527 u8 bit;
3528 u32 data, rmask;
3529
3530 dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
3531
3532 /* rk3066b does support any pulls */
3533 if (ctrl->type == RK3066B)
3534 return pull ? -EINVAL : 0;
3535
3536 ret = ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
3537 if (ret)
3538 return ret;
3539
3540 switch (ctrl->type) {
3541 case RK2928:
3542 case RK3128:
3543 data = BIT(bit + 16);
3544 if (pull == PIN_CONFIG_BIAS_DISABLE)
3545 data |= BIT(bit);
3546 ret = regmap_write(regmap, reg, data);
3547 break;
3548 case PX30:
3549 case RV1103B:
3550 case RV1108:
3551 case RV1126:
3552 case RK3188:
3553 case RK3288:
3554 case RK3308:
3555 case RK3328:
3556 case RK3368:
3557 case RK3399:
3558 case RK3506:
3559 case RK3528:
3560 case RK3562:
3561 case RK3568:
3562 case RK3576:
3563 case RK3588:
3564 pull_type = bank->pull_type[pin_num / 8];
3565 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12)
3566 pull_type = 1;
3567 ret = -EINVAL;
3568 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
3569 i++) {
3570 if (rockchip_pull_list[pull_type][i] == pull) {
3571 ret = i;
3572 break;
3573 }
3574 }
3575 /*
3576 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
3577 * where that pull up value becomes 3.
3578 */
3579 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
3580 if (ret == 1)
3581 ret = 3;
3582 }
3583
3584 if (ret < 0) {
3585 dev_err(dev, "unsupported pull setting %d\n", pull);
3586 return ret;
3587 }
3588
3589 /* enable the write to the equivalent lower bits */
3590 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
3591 rmask = data | (data >> 16);
3592 data |= (ret << bit);
3593
3594 ret = regmap_update_bits(regmap, reg, rmask, data);
3595 break;
3596 default:
3597 dev_err(dev, "unsupported pinctrl type\n");
3598 return -EINVAL;
3599 }
3600
3601 return ret;
3602 }
3603
3604 #define RK3328_SCHMITT_BITS_PER_PIN 1
3605 #define RK3328_SCHMITT_PINS_PER_REG 16
3606 #define RK3328_SCHMITT_BANK_STRIDE 8
3607 #define RK3328_SCHMITT_GRF_OFFSET 0x380
3608
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3609 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3610 int pin_num,
3611 struct regmap **regmap,
3612 int *reg, u8 *bit)
3613 {
3614 struct rockchip_pinctrl *info = bank->drvdata;
3615
3616 *regmap = info->regmap_base;
3617 *reg = RK3328_SCHMITT_GRF_OFFSET;
3618
3619 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
3620 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
3621 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
3622
3623 return 0;
3624 }
3625
3626 #define RK3568_SCHMITT_BITS_PER_PIN 2
3627 #define RK3568_SCHMITT_PINS_PER_REG 8
3628 #define RK3568_SCHMITT_BANK_STRIDE 0x10
3629 #define RK3568_SCHMITT_GRF_OFFSET 0xc0
3630 #define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
3631
rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)3632 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
3633 int pin_num,
3634 struct regmap **regmap,
3635 int *reg, u8 *bit)
3636 {
3637 struct rockchip_pinctrl *info = bank->drvdata;
3638
3639 if (bank->bank_num == 0) {
3640 *regmap = info->regmap_pmu;
3641 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
3642 } else {
3643 *regmap = info->regmap_base;
3644 *reg = RK3568_SCHMITT_GRF_OFFSET;
3645 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
3646 }
3647
3648 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
3649 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
3650 *bit *= RK3568_SCHMITT_BITS_PER_PIN;
3651
3652 return 0;
3653 }
3654
rockchip_get_schmitt(struct rockchip_pin_bank * bank,int pin_num)3655 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
3656 {
3657 struct rockchip_pinctrl *info = bank->drvdata;
3658 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3659 struct regmap *regmap;
3660 int reg, ret;
3661 u8 bit;
3662 u32 data;
3663
3664 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
3665 if (ret)
3666 return ret;
3667
3668 ret = regmap_read(regmap, reg, &data);
3669 if (ret)
3670 return ret;
3671
3672 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3673 data >>= 8;
3674 return data & 0x3;
3675 }
3676
3677 data >>= bit;
3678 switch (ctrl->type) {
3679 case RK3562:
3680 case RK3568:
3681 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
3682 default:
3683 break;
3684 }
3685
3686 if (ctrl->type == RK3506)
3687 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4)
3688 return data & 0x3;
3689
3690 return data & 0x1;
3691 }
3692
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)3693 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
3694 int pin_num, int enable)
3695 {
3696 struct rockchip_pinctrl *info = bank->drvdata;
3697 struct rockchip_pin_ctrl *ctrl = info->ctrl;
3698 struct device *dev = info->dev;
3699 struct regmap *regmap;
3700 int reg, ret;
3701 u8 bit;
3702 u32 data, rmask;
3703
3704 dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
3705 bank->bank_num, pin_num, enable);
3706
3707 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
3708 if (ret)
3709 return ret;
3710
3711 /* enable the write to the equivalent lower bits */
3712 switch (ctrl->type) {
3713 case RK3562:
3714 case RK3568:
3715 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
3716 rmask = data | (data >> 16);
3717 data |= ((enable ? 0x2 : 0x1) << bit);
3718 break;
3719 default:
3720 data = BIT(bit + 16) | (enable << bit);
3721 rmask = BIT(bit + 16) | BIT(bit);
3722 break;
3723 }
3724
3725 if (ctrl->type == RK3506) {
3726 if ((bank->bank_num == 0 && pin_num == 24) || bank->bank_num == 4) {
3727 data = 0x3 << (bit + 16);
3728 rmask = data | (data >> 16);
3729 data |= ((enable ? 0x3 : 0) << bit);
3730 }
3731 }
3732
3733 if (ctrl->type == RV1103B && bank->bank_num == 2 && pin_num >= 12) {
3734 data = 0x3 << (bit + 16);
3735 rmask = data | (data >> 16);
3736 data |= ((enable ? 0x3 : 0) << bit);
3737 }
3738
3739 return regmap_update_bits(regmap, reg, rmask, data);
3740 }
3741
3742 /*
3743 * Pinmux_ops handling
3744 */
3745
rockchip_pmx_get_funcs_count(struct pinctrl_dev * pctldev)3746 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
3747 {
3748 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3749
3750 return info->nfunctions;
3751 }
3752
rockchip_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned selector)3753 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
3754 unsigned selector)
3755 {
3756 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3757
3758 return info->functions[selector].name;
3759 }
3760
rockchip_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)3761 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
3762 unsigned selector, const char * const **groups,
3763 unsigned * const num_groups)
3764 {
3765 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3766
3767 *groups = info->functions[selector].groups;
3768 *num_groups = info->functions[selector].ngroups;
3769
3770 return 0;
3771 }
3772
rockchip_pmx_set(struct pinctrl_dev * pctldev,unsigned selector,unsigned group)3773 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
3774 unsigned group)
3775 {
3776 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3777 const unsigned int *pins = info->groups[group].pins;
3778 const struct rockchip_pin_config *data = info->groups[group].data;
3779 struct device *dev = info->dev;
3780 struct rockchip_pin_bank *bank;
3781 int cnt, ret = 0;
3782
3783 dev_dbg(dev, "enable function %s group %s\n",
3784 info->functions[selector].name, info->groups[group].name);
3785
3786 /*
3787 * for each pin in the pin group selected, program the corresponding
3788 * pin function number in the config register.
3789 */
3790 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
3791 bank = pin_to_bank(info, pins[cnt]);
3792 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
3793 data[cnt].func);
3794 if (ret)
3795 break;
3796 }
3797
3798 if (ret) {
3799 /* revert the already done pin settings */
3800 for (cnt--; cnt >= 0; cnt--) {
3801 bank = pin_to_bank(info, pins[cnt]);
3802 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
3803 }
3804
3805 return ret;
3806 }
3807
3808 return 0;
3809 }
3810
rockchip_pmx_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)3811 static int rockchip_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
3812 struct pinctrl_gpio_range *range,
3813 unsigned int offset)
3814 {
3815 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3816 struct rockchip_pin_bank *bank;
3817
3818 bank = pin_to_bank(info, offset);
3819 return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
3820 }
3821
3822 static const struct pinmux_ops rockchip_pmx_ops = {
3823 .get_functions_count = rockchip_pmx_get_funcs_count,
3824 .get_function_name = rockchip_pmx_get_func_name,
3825 .get_function_groups = rockchip_pmx_get_groups,
3826 .set_mux = rockchip_pmx_set,
3827 .gpio_request_enable = rockchip_pmx_gpio_request_enable,
3828 };
3829
3830 /*
3831 * Pinconf_ops handling
3832 */
3833
rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl * ctrl,enum pin_config_param pull)3834 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
3835 enum pin_config_param pull)
3836 {
3837 switch (ctrl->type) {
3838 case RK2928:
3839 case RK3128:
3840 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
3841 pull == PIN_CONFIG_BIAS_DISABLE);
3842 case RK3066B:
3843 return pull ? false : true;
3844 case PX30:
3845 case RV1103B:
3846 case RV1108:
3847 case RV1126:
3848 case RK3188:
3849 case RK3288:
3850 case RK3308:
3851 case RK3328:
3852 case RK3368:
3853 case RK3399:
3854 case RK3506:
3855 case RK3528:
3856 case RK3562:
3857 case RK3568:
3858 case RK3576:
3859 case RK3588:
3860 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
3861 }
3862
3863 return false;
3864 }
3865
rockchip_pinconf_defer_pin(struct rockchip_pin_bank * bank,unsigned int pin,u32 param,u32 arg)3866 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
3867 unsigned int pin, u32 param, u32 arg)
3868 {
3869 struct rockchip_pin_deferred *cfg;
3870
3871 cfg = kzalloc_obj(*cfg);
3872 if (!cfg)
3873 return -ENOMEM;
3874
3875 cfg->pin = pin;
3876 cfg->param = param;
3877 cfg->arg = arg;
3878
3879 list_add_tail(&cfg->head, &bank->deferred_pins);
3880
3881 return 0;
3882 }
3883
3884 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned num_configs)3885 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
3886 unsigned long *configs, unsigned num_configs)
3887 {
3888 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3889 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3890 struct gpio_chip *gpio = &bank->gpio_chip;
3891 enum pin_config_param param;
3892 u32 arg;
3893 int i;
3894 int rc;
3895
3896 for (i = 0; i < num_configs; i++) {
3897 param = pinconf_to_config_param(configs[i]);
3898 arg = pinconf_to_config_argument(configs[i]);
3899
3900 if (param == PIN_CONFIG_LEVEL || param == PIN_CONFIG_INPUT_ENABLE) {
3901 /*
3902 * Check for gpio driver not being probed yet.
3903 * The lock makes sure that either gpio-probe has completed
3904 * or the gpio driver hasn't probed yet.
3905 */
3906 scoped_guard(mutex, &bank->deferred_lock) {
3907 if (!gpio || !gpio->direction_output)
3908 return rockchip_pinconf_defer_pin(bank,
3909 pin - bank->pin_base,
3910 param, arg);
3911 }
3912 }
3913
3914 switch (param) {
3915 case PIN_CONFIG_BIAS_DISABLE:
3916 rc = rockchip_set_pull(bank, pin - bank->pin_base,
3917 param);
3918 if (rc)
3919 return rc;
3920 break;
3921 case PIN_CONFIG_BIAS_PULL_UP:
3922 case PIN_CONFIG_BIAS_PULL_DOWN:
3923 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3924 case PIN_CONFIG_BIAS_BUS_HOLD:
3925 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
3926 return -ENOTSUPP;
3927
3928 if (!arg)
3929 return -EINVAL;
3930
3931 rc = rockchip_set_pull(bank, pin - bank->pin_base,
3932 param);
3933 if (rc)
3934 return rc;
3935 break;
3936 case PIN_CONFIG_LEVEL:
3937 rc = rockchip_set_mux(bank, pin - bank->pin_base,
3938 RK_FUNC_GPIO);
3939 if (rc != RK_FUNC_GPIO)
3940 return -EINVAL;
3941
3942 rc = gpio->direction_output(gpio, pin - bank->pin_base,
3943 arg);
3944 if (rc)
3945 return rc;
3946 break;
3947 case PIN_CONFIG_INPUT_ENABLE:
3948 rc = rockchip_set_mux(bank, pin - bank->pin_base,
3949 RK_FUNC_GPIO);
3950 if (rc != RK_FUNC_GPIO)
3951 return -EINVAL;
3952
3953 rc = gpio->direction_input(gpio, pin - bank->pin_base);
3954 if (rc)
3955 return rc;
3956 break;
3957 case PIN_CONFIG_DRIVE_STRENGTH:
3958 /* rk3288 is the first with per-pin drive-strength */
3959 if (!info->ctrl->drv_calc_reg)
3960 return -ENOTSUPP;
3961
3962 rc = rockchip_set_drive_perpin(bank,
3963 pin - bank->pin_base, arg);
3964 if (rc < 0)
3965 return rc;
3966 break;
3967 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3968 if (!info->ctrl->schmitt_calc_reg)
3969 return -ENOTSUPP;
3970
3971 rc = rockchip_set_schmitt(bank,
3972 pin - bank->pin_base, arg);
3973 if (rc < 0)
3974 return rc;
3975 break;
3976 default:
3977 return -ENOTSUPP;
3978 break;
3979 }
3980 } /* for each config */
3981
3982 return 0;
3983 }
3984
3985 /* get the pin config settings for a specified pin */
rockchip_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)3986 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
3987 unsigned long *config)
3988 {
3989 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3990 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3991 struct gpio_chip *gpio = &bank->gpio_chip;
3992 enum pin_config_param param = pinconf_to_config_param(*config);
3993 u16 arg;
3994 int rc;
3995
3996 switch (param) {
3997 case PIN_CONFIG_BIAS_DISABLE:
3998 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
3999 return -EINVAL;
4000
4001 arg = 0;
4002 break;
4003 case PIN_CONFIG_BIAS_PULL_UP:
4004 case PIN_CONFIG_BIAS_PULL_DOWN:
4005 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
4006 case PIN_CONFIG_BIAS_BUS_HOLD:
4007 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
4008 return -ENOTSUPP;
4009
4010 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
4011 return -EINVAL;
4012
4013 arg = 1;
4014 break;
4015 case PIN_CONFIG_LEVEL:
4016 rc = rockchip_get_mux(bank, pin - bank->pin_base);
4017 if (rc != RK_FUNC_GPIO)
4018 return -EINVAL;
4019
4020 if (!gpio || !gpio->get) {
4021 arg = 0;
4022 break;
4023 }
4024
4025 rc = gpio->get(gpio, pin - bank->pin_base);
4026 if (rc < 0)
4027 return rc;
4028
4029 arg = rc ? 1 : 0;
4030 break;
4031 case PIN_CONFIG_DRIVE_STRENGTH:
4032 /* rk3288 is the first with per-pin drive-strength */
4033 if (!info->ctrl->drv_calc_reg)
4034 return -ENOTSUPP;
4035
4036 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
4037 if (rc < 0)
4038 return rc;
4039
4040 arg = rc;
4041 break;
4042 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
4043 if (!info->ctrl->schmitt_calc_reg)
4044 return -ENOTSUPP;
4045
4046 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
4047 if (rc < 0)
4048 return rc;
4049
4050 arg = rc;
4051 break;
4052 default:
4053 return -ENOTSUPP;
4054 break;
4055 }
4056
4057 *config = pinconf_to_config_packed(param, arg);
4058
4059 return 0;
4060 }
4061
4062 static const struct pinconf_ops rockchip_pinconf_ops = {
4063 .pin_config_get = rockchip_pinconf_get,
4064 .pin_config_set = rockchip_pinconf_set,
4065 .is_generic = true,
4066 };
4067
4068 static const struct of_device_id rockchip_bank_match[] = {
4069 { .compatible = "rockchip,gpio-bank" },
4070 { .compatible = "rockchip,rk3188-gpio-bank0" },
4071 {},
4072 };
4073
rockchip_pinctrl_child_count(struct rockchip_pinctrl * info,struct device_node * np)4074 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
4075 struct device_node *np)
4076 {
4077 struct device_node *child;
4078
4079 for_each_child_of_node(np, child) {
4080 if (of_match_node(rockchip_bank_match, child))
4081 continue;
4082
4083 info->nfunctions++;
4084 info->ngroups += of_get_child_count(child);
4085 }
4086 }
4087
rockchip_pinctrl_parse_groups(struct device_node * np,struct rockchip_pin_group * grp,struct rockchip_pinctrl * info,u32 index)4088 static int rockchip_pinctrl_parse_groups(struct device_node *np,
4089 struct rockchip_pin_group *grp,
4090 struct rockchip_pinctrl *info,
4091 u32 index)
4092 {
4093 struct device *dev = info->dev;
4094 struct rockchip_pin_bank *bank;
4095 int size;
4096 const __be32 *list;
4097 int num;
4098 int i, j;
4099 int ret;
4100
4101 dev_dbg(dev, "group(%d): %pOFn\n", index, np);
4102
4103 /* Initialise group */
4104 grp->name = np->name;
4105
4106 /*
4107 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
4108 * do sanity check and calculate pins number
4109 */
4110 list = of_get_property(np, "rockchip,pins", &size);
4111 /* we do not check return since it's safe node passed down */
4112 size /= sizeof(*list);
4113 if (!size || size % 4)
4114 return dev_err_probe(dev, -EINVAL,
4115 "%pOF: rockchip,pins: expected one or more of <bank pin mux CONFIG>, got %d args instead\n",
4116 np, size);
4117
4118 grp->npins = size / 4;
4119
4120 grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
4121 grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
4122 if (!grp->pins || !grp->data)
4123 return -ENOMEM;
4124
4125 for (i = 0, j = 0; i < size; i += 4, j++) {
4126 const __be32 *phandle;
4127 struct device_node *np_config;
4128
4129 num = be32_to_cpu(*list++);
4130 bank = bank_num_to_bank(info, num);
4131 if (IS_ERR(bank))
4132 return PTR_ERR(bank);
4133
4134 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
4135 grp->data[j].func = be32_to_cpu(*list++);
4136
4137 phandle = list++;
4138 if (!phandle)
4139 return -EINVAL;
4140
4141 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
4142 ret = pinconf_generic_parse_dt_config(np_config, NULL,
4143 &grp->data[j].configs, &grp->data[j].nconfigs);
4144 of_node_put(np_config);
4145 if (ret)
4146 return ret;
4147 }
4148
4149 return 0;
4150 }
4151
rockchip_pinctrl_parse_functions(struct device_node * np,struct rockchip_pinctrl * info,u32 index)4152 static int rockchip_pinctrl_parse_functions(struct device_node *np,
4153 struct rockchip_pinctrl *info,
4154 u32 index)
4155 {
4156 struct device *dev = info->dev;
4157 struct rockchip_pmx_func *func;
4158 struct rockchip_pin_group *grp;
4159 int ret;
4160 static u32 grp_index;
4161 u32 i = 0;
4162
4163 dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
4164
4165 func = &info->functions[index];
4166
4167 /* Initialise function */
4168 func->name = np->name;
4169 func->ngroups = of_get_child_count(np);
4170 if (func->ngroups <= 0)
4171 return 0;
4172
4173 func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
4174 if (!func->groups)
4175 return -ENOMEM;
4176
4177 for_each_child_of_node_scoped(np, child) {
4178 func->groups[i] = child->name;
4179 grp = &info->groups[grp_index++];
4180 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
4181 if (ret)
4182 return ret;
4183 }
4184
4185 return 0;
4186 }
4187
rockchip_pinctrl_parse_dt(struct platform_device * pdev,struct rockchip_pinctrl * info)4188 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
4189 struct rockchip_pinctrl *info)
4190 {
4191 struct device *dev = &pdev->dev;
4192 struct device_node *np = dev->of_node;
4193 int ret;
4194 int i;
4195
4196 rockchip_pinctrl_child_count(info, np);
4197
4198 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
4199 dev_dbg(dev, "ngroups = %d\n", info->ngroups);
4200
4201 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
4202 if (!info->functions)
4203 return -ENOMEM;
4204
4205 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
4206 if (!info->groups)
4207 return -ENOMEM;
4208
4209 i = 0;
4210
4211 for_each_child_of_node_scoped(np, child) {
4212 if (of_match_node(rockchip_bank_match, child))
4213 continue;
4214
4215 ret = rockchip_pinctrl_parse_functions(child, info, i++);
4216 if (ret) {
4217 dev_err(dev, "failed to parse function\n");
4218 return ret;
4219 }
4220 }
4221
4222 return 0;
4223 }
4224
rockchip_pinctrl_register(struct platform_device * pdev,struct rockchip_pinctrl * info)4225 static int rockchip_pinctrl_register(struct platform_device *pdev,
4226 struct rockchip_pinctrl *info)
4227 {
4228 struct pinctrl_desc *ctrldesc = &info->pctl;
4229 struct pinctrl_pin_desc *pindesc, *pdesc;
4230 struct rockchip_pin_bank *pin_bank;
4231 struct device *dev = &pdev->dev;
4232 char **pin_names;
4233 int pin, bank, ret;
4234 int k;
4235
4236 ctrldesc->name = "rockchip-pinctrl";
4237 ctrldesc->owner = THIS_MODULE;
4238 ctrldesc->pctlops = &rockchip_pctrl_ops;
4239 ctrldesc->pmxops = &rockchip_pmx_ops;
4240 ctrldesc->confops = &rockchip_pinconf_ops;
4241
4242 pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
4243 if (!pindesc)
4244 return -ENOMEM;
4245
4246 ctrldesc->pins = pindesc;
4247 ctrldesc->npins = info->ctrl->nr_pins;
4248
4249 pdesc = pindesc;
4250 for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
4251 pin_bank = &info->ctrl->pin_banks[bank];
4252
4253 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
4254 if (IS_ERR(pin_names))
4255 return PTR_ERR(pin_names);
4256
4257 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
4258 pdesc->number = k;
4259 pdesc->name = pin_names[pin];
4260 pdesc++;
4261 }
4262
4263 INIT_LIST_HEAD(&pin_bank->deferred_pins);
4264 mutex_init(&pin_bank->deferred_lock);
4265 }
4266
4267 ret = rockchip_pinctrl_parse_dt(pdev, info);
4268 if (ret)
4269 return ret;
4270
4271 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
4272 if (IS_ERR(info->pctl_dev))
4273 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
4274
4275 return 0;
4276 }
4277
4278 static const struct of_device_id rockchip_pinctrl_dt_match[];
4279
4280 /* retrieve the soc specific data */
rockchip_pinctrl_get_soc_data(struct rockchip_pinctrl * d,struct platform_device * pdev)4281 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
4282 struct rockchip_pinctrl *d,
4283 struct platform_device *pdev)
4284 {
4285 struct device *dev = &pdev->dev;
4286 struct device_node *node = dev->of_node;
4287 const struct of_device_id *match;
4288 struct rockchip_pin_ctrl *ctrl;
4289 struct rockchip_pin_bank *bank;
4290 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
4291
4292 match = of_match_node(rockchip_pinctrl_dt_match, node);
4293 ctrl = (struct rockchip_pin_ctrl *)match->data;
4294
4295 grf_offs = ctrl->grf_mux_offset;
4296 pmu_offs = ctrl->pmu_mux_offset;
4297 drv_pmu_offs = ctrl->pmu_drv_offset;
4298 drv_grf_offs = ctrl->grf_drv_offset;
4299 bank = ctrl->pin_banks;
4300 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
4301 int bank_pins = 0;
4302
4303 raw_spin_lock_init(&bank->slock);
4304 bank->drvdata = d;
4305 bank->pin_base = ctrl->nr_pins;
4306 ctrl->nr_pins += bank->nr_pins;
4307
4308 /* calculate iomux and drv offsets */
4309 for (j = 0; j < 4; j++) {
4310 struct rockchip_iomux *iom = &bank->iomux[j];
4311 struct rockchip_drv *drv = &bank->drv[j];
4312 int inc;
4313
4314 if (bank_pins >= bank->nr_pins)
4315 break;
4316
4317 /* preset iomux offset value, set new start value */
4318 if (iom->offset >= 0) {
4319 if ((iom->type & IOMUX_SOURCE_PMU) ||
4320 (iom->type & IOMUX_L_SOURCE_PMU))
4321 pmu_offs = iom->offset;
4322 else
4323 grf_offs = iom->offset;
4324 } else { /* set current iomux offset */
4325 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
4326 (iom->type & IOMUX_L_SOURCE_PMU)) ?
4327 pmu_offs : grf_offs;
4328 }
4329
4330 /* preset drv offset value, set new start value */
4331 if (drv->offset >= 0) {
4332 if (iom->type & IOMUX_SOURCE_PMU)
4333 drv_pmu_offs = drv->offset;
4334 else
4335 drv_grf_offs = drv->offset;
4336 } else { /* set current drv offset */
4337 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
4338 drv_pmu_offs : drv_grf_offs;
4339 }
4340
4341 dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
4342 i, j, iom->offset, drv->offset);
4343
4344 /*
4345 * Increase offset according to iomux width.
4346 * 4bit iomux'es are spread over two registers.
4347 */
4348 inc = (iom->type & (IOMUX_WIDTH_4BIT |
4349 IOMUX_WIDTH_3BIT |
4350 IOMUX_WIDTH_2BIT)) ? 8 : 4;
4351 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
4352 pmu_offs += inc;
4353 else
4354 grf_offs += inc;
4355
4356 /*
4357 * Increase offset according to drv width.
4358 * 3bit drive-strenth'es are spread over two registers.
4359 */
4360 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
4361 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
4362 inc = 8;
4363 else
4364 inc = 4;
4365
4366 if (iom->type & IOMUX_SOURCE_PMU)
4367 drv_pmu_offs += inc;
4368 else
4369 drv_grf_offs += inc;
4370
4371 bank_pins += 8;
4372 }
4373
4374 /* calculate the per-bank recalced_mask */
4375 for (j = 0; j < ctrl->niomux_recalced; j++) {
4376 int pin = 0;
4377
4378 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
4379 pin = ctrl->iomux_recalced[j].pin;
4380 bank->recalced_mask |= BIT(pin);
4381 }
4382 }
4383
4384 /* calculate the per-bank route_mask */
4385 for (j = 0; j < ctrl->niomux_routes; j++) {
4386 int pin = 0;
4387
4388 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
4389 pin = ctrl->iomux_routes[j].pin;
4390 bank->route_mask |= BIT(pin);
4391 }
4392 }
4393 }
4394
4395 return ctrl;
4396 }
4397
4398 #define RK3288_GRF_GPIO6C_IOMUX 0x64
4399 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
4400
4401 static u32 rk3288_grf_gpio6c_iomux;
4402
rockchip_pinctrl_suspend(struct device * dev)4403 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
4404 {
4405 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
4406 int ret = pinctrl_force_sleep(info->pctl_dev);
4407
4408 if (ret)
4409 return ret;
4410
4411 /*
4412 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
4413 * the setting here, and restore it at resume.
4414 */
4415 if (info->ctrl->type == RK3288) {
4416 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
4417 &rk3288_grf_gpio6c_iomux);
4418 if (ret) {
4419 pinctrl_force_default(info->pctl_dev);
4420 return ret;
4421 }
4422 }
4423
4424 return 0;
4425 }
4426
rockchip_pinctrl_resume(struct device * dev)4427 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
4428 {
4429 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
4430 int ret;
4431
4432 if (info->ctrl->type == RK3288) {
4433 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
4434 rk3288_grf_gpio6c_iomux |
4435 GPIO6C6_SEL_WRITE_ENABLE);
4436 if (ret)
4437 return ret;
4438 }
4439
4440 return pinctrl_force_default(info->pctl_dev);
4441 }
4442
4443 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
4444 rockchip_pinctrl_resume);
4445
rockchip_pinctrl_probe(struct platform_device * pdev)4446 static int rockchip_pinctrl_probe(struct platform_device *pdev)
4447 {
4448 struct rockchip_pinctrl *info;
4449 struct device *dev = &pdev->dev;
4450 struct device_node *np = dev->of_node, *node;
4451 struct rockchip_pin_ctrl *ctrl;
4452 struct resource *res;
4453 void __iomem *base;
4454 int ret;
4455
4456 if (!dev->of_node)
4457 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
4458
4459 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
4460 if (!info)
4461 return -ENOMEM;
4462
4463 info->dev = dev;
4464
4465 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
4466 if (!ctrl)
4467 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
4468 info->ctrl = ctrl;
4469
4470 node = of_parse_phandle(np, "rockchip,grf", 0);
4471 if (node) {
4472 info->regmap_base = syscon_node_to_regmap(node);
4473 of_node_put(node);
4474 if (IS_ERR(info->regmap_base))
4475 return PTR_ERR(info->regmap_base);
4476 } else {
4477 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
4478 if (IS_ERR(base))
4479 return PTR_ERR(base);
4480
4481 rockchip_regmap_config.max_register = resource_size(res) - 4;
4482 rockchip_regmap_config.name = "rockchip,pinctrl";
4483 info->regmap_base =
4484 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
4485
4486 /* to check for the old dt-bindings */
4487 info->reg_size = resource_size(res);
4488
4489 /* Honor the old binding, with pull registers as 2nd resource */
4490 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
4491 base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
4492 if (IS_ERR(base))
4493 return PTR_ERR(base);
4494
4495 rockchip_regmap_config.max_register = resource_size(res) - 4;
4496 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
4497 info->regmap_pull =
4498 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
4499 }
4500 }
4501
4502 /* try to find the optional reference to the pmu syscon */
4503 info->regmap_pmu = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,pmu");
4504
4505 /* try to find the optional reference to the ioc1 syscon */
4506 info->regmap_ioc1 = syscon_regmap_lookup_by_phandle_optional(np, "rockchip,ioc1");
4507
4508 ret = rockchip_pinctrl_register(pdev, info);
4509 if (ret)
4510 return ret;
4511
4512 platform_set_drvdata(pdev, info);
4513
4514 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
4515 if (ret)
4516 return dev_err_probe(dev, ret, "failed to register gpio device\n");
4517
4518 return 0;
4519 }
4520
rockchip_pinctrl_remove(struct platform_device * pdev)4521 static void rockchip_pinctrl_remove(struct platform_device *pdev)
4522 {
4523 struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
4524 struct rockchip_pin_bank *bank;
4525 struct rockchip_pin_deferred *cfg;
4526 int i;
4527
4528 of_platform_depopulate(&pdev->dev);
4529
4530 for (i = 0; i < info->ctrl->nr_banks; i++) {
4531 bank = &info->ctrl->pin_banks[i];
4532
4533 mutex_lock(&bank->deferred_lock);
4534 while (!list_empty(&bank->deferred_pins)) {
4535 cfg = list_first_entry(&bank->deferred_pins,
4536 struct rockchip_pin_deferred, head);
4537 list_del(&cfg->head);
4538 kfree(cfg);
4539 }
4540 mutex_unlock(&bank->deferred_lock);
4541 }
4542 }
4543
4544 static struct rockchip_pin_bank px30_pin_banks[] = {
4545 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4546 IOMUX_SOURCE_PMU,
4547 IOMUX_SOURCE_PMU,
4548 IOMUX_SOURCE_PMU
4549 ),
4550 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4551 IOMUX_WIDTH_4BIT,
4552 IOMUX_WIDTH_4BIT,
4553 IOMUX_WIDTH_4BIT
4554 ),
4555 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4556 IOMUX_WIDTH_4BIT,
4557 IOMUX_WIDTH_4BIT,
4558 IOMUX_WIDTH_4BIT
4559 ),
4560 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4561 IOMUX_WIDTH_4BIT,
4562 IOMUX_WIDTH_4BIT,
4563 IOMUX_WIDTH_4BIT
4564 ),
4565 };
4566
4567 static struct rockchip_pin_ctrl px30_pin_ctrl = {
4568 .pin_banks = px30_pin_banks,
4569 .nr_banks = ARRAY_SIZE(px30_pin_banks),
4570 .label = "PX30-GPIO",
4571 .type = PX30,
4572 .grf_mux_offset = 0x0,
4573 .pmu_mux_offset = 0x0,
4574 .iomux_routes = px30_mux_route_data,
4575 .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
4576 .pull_calc_reg = px30_calc_pull_reg_and_bit,
4577 .drv_calc_reg = px30_calc_drv_reg_and_bit,
4578 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
4579 };
4580
4581 static struct rockchip_pin_bank rv1103b_pin_banks[] = {
4582 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(0, 32, "gpio0",
4583 IOMUX_WIDTH_4BIT,
4584 IOMUX_WIDTH_4BIT,
4585 IOMUX_WIDTH_4BIT,
4586 IOMUX_WIDTH_4BIT,
4587 0x40000, 0x50008, 0x50010, 0x50018,
4588 DRV_TYPE_IO_LEVEL_8_BIT,
4589 DRV_TYPE_IO_LEVEL_8_BIT,
4590 DRV_TYPE_IO_LEVEL_8_BIT,
4591 DRV_TYPE_IO_LEVEL_8_BIT),
4592 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
4593 IOMUX_WIDTH_4BIT,
4594 IOMUX_WIDTH_4BIT,
4595 IOMUX_WIDTH_4BIT,
4596 IOMUX_WIDTH_4BIT,
4597 0x20, 0x10028, 0x10030, 0x10038,
4598 DRV_TYPE_IO_LEVEL_8_BIT,
4599 DRV_TYPE_IO_LEVEL_8_BIT,
4600 DRV_TYPE_IO_LEVEL_8_BIT,
4601 DRV_TYPE_IO_LEVEL_8_BIT),
4602 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
4603 IOMUX_WIDTH_4BIT,
4604 IOMUX_WIDTH_4BIT,
4605 IOMUX_WIDTH_4BIT,
4606 IOMUX_WIDTH_4BIT,
4607 0x30040, 0x30048, 0x30050, 0x30058,
4608 DRV_TYPE_IO_LEVEL_8_BIT,
4609 DRV_TYPE_IO_LEVEL_8_BIT,
4610 DRV_TYPE_IO_LEVEL_8_BIT,
4611 DRV_TYPE_IO_LEVEL_8_BIT),
4612 };
4613
4614 static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = {
4615 .pin_banks = rv1103b_pin_banks,
4616 .nr_banks = ARRAY_SIZE(rv1103b_pin_banks),
4617 .label = "RV1103B-GPIO",
4618 .type = RV1103B,
4619 .iomux_recalced = rv1103b_mux_recalced_data,
4620 .niomux_recalced = ARRAY_SIZE(rv1103b_mux_recalced_data),
4621 .pull_calc_reg = rv1103b_calc_pull_reg_and_bit,
4622 .drv_calc_reg = rv1103b_calc_drv_reg_and_bit,
4623 .schmitt_calc_reg = rv1103b_calc_schmitt_reg_and_bit,
4624 };
4625
4626 static struct rockchip_pin_bank rv1108_pin_banks[] = {
4627 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4628 IOMUX_SOURCE_PMU,
4629 IOMUX_SOURCE_PMU,
4630 IOMUX_SOURCE_PMU),
4631 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4632 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
4633 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
4634 };
4635
4636 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
4637 .pin_banks = rv1108_pin_banks,
4638 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
4639 .label = "RV1108-GPIO",
4640 .type = RV1108,
4641 .grf_mux_offset = 0x10,
4642 .pmu_mux_offset = 0x0,
4643 .iomux_recalced = rv1108_mux_recalced_data,
4644 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
4645 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
4646 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
4647 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
4648 };
4649
4650 static struct rockchip_pin_bank rv1126_pin_banks[] = {
4651 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
4652 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
4653 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
4654 IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
4655 IOMUX_WIDTH_4BIT),
4656 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
4657 IOMUX_WIDTH_4BIT,
4658 IOMUX_WIDTH_4BIT,
4659 IOMUX_WIDTH_4BIT,
4660 IOMUX_WIDTH_4BIT,
4661 0x10010, 0x10018, 0x10020, 0x10028),
4662 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
4663 IOMUX_WIDTH_4BIT,
4664 IOMUX_WIDTH_4BIT,
4665 IOMUX_WIDTH_4BIT,
4666 IOMUX_WIDTH_4BIT),
4667 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4668 IOMUX_WIDTH_4BIT,
4669 IOMUX_WIDTH_4BIT,
4670 IOMUX_WIDTH_4BIT,
4671 IOMUX_WIDTH_4BIT),
4672 PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
4673 IOMUX_WIDTH_4BIT, 0, 0, 0),
4674 };
4675
4676 static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
4677 .pin_banks = rv1126_pin_banks,
4678 .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
4679 .label = "RV1126-GPIO",
4680 .type = RV1126,
4681 .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
4682 .pmu_mux_offset = 0x0,
4683 .iomux_routes = rv1126_mux_route_data,
4684 .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
4685 .iomux_recalced = rv1126_mux_recalced_data,
4686 .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
4687 .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
4688 .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
4689 .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
4690 };
4691
4692 static struct rockchip_pin_bank rk2928_pin_banks[] = {
4693 PIN_BANK(0, 32, "gpio0"),
4694 PIN_BANK(1, 32, "gpio1"),
4695 PIN_BANK(2, 32, "gpio2"),
4696 PIN_BANK(3, 32, "gpio3"),
4697 };
4698
4699 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
4700 .pin_banks = rk2928_pin_banks,
4701 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
4702 .label = "RK2928-GPIO",
4703 .type = RK2928,
4704 .grf_mux_offset = 0xa8,
4705 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4706 };
4707
4708 static struct rockchip_pin_bank rk3036_pin_banks[] = {
4709 PIN_BANK(0, 32, "gpio0"),
4710 PIN_BANK(1, 32, "gpio1"),
4711 PIN_BANK(2, 32, "gpio2"),
4712 };
4713
4714 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
4715 .pin_banks = rk3036_pin_banks,
4716 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
4717 .label = "RK3036-GPIO",
4718 .type = RK2928,
4719 .grf_mux_offset = 0xa8,
4720 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4721 };
4722
4723 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
4724 PIN_BANK(0, 32, "gpio0"),
4725 PIN_BANK(1, 32, "gpio1"),
4726 PIN_BANK(2, 32, "gpio2"),
4727 PIN_BANK(3, 32, "gpio3"),
4728 PIN_BANK(4, 32, "gpio4"),
4729 PIN_BANK(6, 16, "gpio6"),
4730 };
4731
4732 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
4733 .pin_banks = rk3066a_pin_banks,
4734 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
4735 .label = "RK3066a-GPIO",
4736 .type = RK2928,
4737 .grf_mux_offset = 0xa8,
4738 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
4739 };
4740
4741 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
4742 PIN_BANK(0, 32, "gpio0"),
4743 PIN_BANK(1, 32, "gpio1"),
4744 PIN_BANK(2, 32, "gpio2"),
4745 PIN_BANK(3, 32, "gpio3"),
4746 };
4747
4748 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
4749 .pin_banks = rk3066b_pin_banks,
4750 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
4751 .label = "RK3066b-GPIO",
4752 .type = RK3066B,
4753 .grf_mux_offset = 0x60,
4754 };
4755
4756 static struct rockchip_pin_bank rk3128_pin_banks[] = {
4757 PIN_BANK(0, 32, "gpio0"),
4758 PIN_BANK(1, 32, "gpio1"),
4759 PIN_BANK(2, 32, "gpio2"),
4760 PIN_BANK(3, 32, "gpio3"),
4761 };
4762
4763 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
4764 .pin_banks = rk3128_pin_banks,
4765 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
4766 .label = "RK3128-GPIO",
4767 .type = RK3128,
4768 .grf_mux_offset = 0xa8,
4769 .iomux_recalced = rk3128_mux_recalced_data,
4770 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
4771 .iomux_routes = rk3128_mux_route_data,
4772 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
4773 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
4774 };
4775
4776 static struct rockchip_pin_bank rk3188_pin_banks[] = {
4777 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
4778 PIN_BANK(1, 32, "gpio1"),
4779 PIN_BANK(2, 32, "gpio2"),
4780 PIN_BANK(3, 32, "gpio3"),
4781 };
4782
4783 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
4784 .pin_banks = rk3188_pin_banks,
4785 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
4786 .label = "RK3188-GPIO",
4787 .type = RK3188,
4788 .grf_mux_offset = 0x60,
4789 .iomux_routes = rk3188_mux_route_data,
4790 .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data),
4791 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
4792 };
4793
4794 static struct rockchip_pin_bank rk3228_pin_banks[] = {
4795 PIN_BANK(0, 32, "gpio0"),
4796 PIN_BANK(1, 32, "gpio1"),
4797 PIN_BANK(2, 32, "gpio2"),
4798 PIN_BANK(3, 32, "gpio3"),
4799 };
4800
4801 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
4802 .pin_banks = rk3228_pin_banks,
4803 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
4804 .label = "RK3228-GPIO",
4805 .type = RK3288,
4806 .grf_mux_offset = 0x0,
4807 .iomux_routes = rk3228_mux_route_data,
4808 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
4809 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4810 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4811 };
4812
4813 static struct rockchip_pin_bank rk3288_pin_banks[] = {
4814 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
4815 IOMUX_SOURCE_PMU,
4816 IOMUX_SOURCE_PMU,
4817 IOMUX_UNROUTED
4818 ),
4819 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
4820 IOMUX_UNROUTED,
4821 IOMUX_UNROUTED,
4822 0
4823 ),
4824 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
4825 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
4826 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4827 IOMUX_WIDTH_4BIT,
4828 0,
4829 0
4830 ),
4831 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
4832 0,
4833 0,
4834 IOMUX_UNROUTED
4835 ),
4836 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
4837 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
4838 0,
4839 IOMUX_WIDTH_4BIT,
4840 IOMUX_UNROUTED
4841 ),
4842 PIN_BANK(8, 16, "gpio8"),
4843 };
4844
4845 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
4846 .pin_banks = rk3288_pin_banks,
4847 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
4848 .label = "RK3288-GPIO",
4849 .type = RK3288,
4850 .grf_mux_offset = 0x0,
4851 .pmu_mux_offset = 0x84,
4852 .iomux_routes = rk3288_mux_route_data,
4853 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
4854 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
4855 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
4856 };
4857
4858 static struct rockchip_pin_bank rk3308_pin_banks[] = {
4859 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
4860 IOMUX_WIDTH_2BIT,
4861 IOMUX_WIDTH_2BIT,
4862 IOMUX_WIDTH_2BIT),
4863 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
4864 IOMUX_WIDTH_2BIT,
4865 IOMUX_WIDTH_2BIT,
4866 IOMUX_WIDTH_2BIT),
4867 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
4868 IOMUX_WIDTH_2BIT,
4869 IOMUX_WIDTH_2BIT,
4870 IOMUX_WIDTH_2BIT),
4871 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
4872 IOMUX_WIDTH_2BIT,
4873 IOMUX_WIDTH_2BIT,
4874 IOMUX_WIDTH_2BIT),
4875 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
4876 IOMUX_WIDTH_2BIT,
4877 IOMUX_WIDTH_2BIT,
4878 IOMUX_WIDTH_2BIT),
4879 };
4880
4881 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
4882 .pin_banks = rk3308_pin_banks,
4883 .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
4884 .label = "RK3308-GPIO",
4885 .type = RK3308,
4886 .grf_mux_offset = 0x0,
4887 .iomux_recalced = rk3308_mux_recalced_data,
4888 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
4889 .iomux_routes = rk3308_mux_route_data,
4890 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
4891 .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
4892 .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
4893 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
4894 };
4895
4896 static struct rockchip_pin_bank rk3328_pin_banks[] = {
4897 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
4898 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
4899 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
4900 IOMUX_WIDTH_2BIT,
4901 IOMUX_WIDTH_3BIT,
4902 0),
4903 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
4904 IOMUX_WIDTH_3BIT,
4905 IOMUX_WIDTH_3BIT,
4906 0,
4907 0),
4908 };
4909
4910 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
4911 .pin_banks = rk3328_pin_banks,
4912 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
4913 .label = "RK3328-GPIO",
4914 .type = RK3328,
4915 .grf_mux_offset = 0x0,
4916 .iomux_recalced = rk3328_mux_recalced_data,
4917 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
4918 .iomux_routes = rk3328_mux_route_data,
4919 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
4920 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
4921 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
4922 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
4923 };
4924
4925 static struct rockchip_pin_bank rk3368_pin_banks[] = {
4926 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
4927 IOMUX_SOURCE_PMU,
4928 IOMUX_SOURCE_PMU,
4929 IOMUX_SOURCE_PMU
4930 ),
4931 PIN_BANK(1, 32, "gpio1"),
4932 PIN_BANK(2, 32, "gpio2"),
4933 PIN_BANK(3, 32, "gpio3"),
4934 };
4935
4936 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4937 .pin_banks = rk3368_pin_banks,
4938 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
4939 .label = "RK3368-GPIO",
4940 .type = RK3368,
4941 .grf_mux_offset = 0x0,
4942 .pmu_mux_offset = 0x0,
4943 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
4944 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
4945 };
4946
4947 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4948 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4949 IOMUX_SOURCE_PMU,
4950 IOMUX_SOURCE_PMU,
4951 IOMUX_SOURCE_PMU,
4952 IOMUX_SOURCE_PMU,
4953 DRV_TYPE_IO_1V8_ONLY,
4954 DRV_TYPE_IO_1V8_ONLY,
4955 DRV_TYPE_IO_DEFAULT,
4956 DRV_TYPE_IO_DEFAULT,
4957 0x80,
4958 0x88,
4959 -1,
4960 -1,
4961 PULL_TYPE_IO_1V8_ONLY,
4962 PULL_TYPE_IO_1V8_ONLY,
4963 PULL_TYPE_IO_DEFAULT,
4964 PULL_TYPE_IO_DEFAULT
4965 ),
4966 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4967 IOMUX_SOURCE_PMU,
4968 IOMUX_SOURCE_PMU,
4969 IOMUX_SOURCE_PMU,
4970 DRV_TYPE_IO_1V8_OR_3V0,
4971 DRV_TYPE_IO_1V8_OR_3V0,
4972 DRV_TYPE_IO_1V8_OR_3V0,
4973 DRV_TYPE_IO_1V8_OR_3V0,
4974 0xa0,
4975 0xa8,
4976 0xb0,
4977 0xb8
4978 ),
4979 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4980 DRV_TYPE_IO_1V8_OR_3V0,
4981 DRV_TYPE_IO_1V8_ONLY,
4982 DRV_TYPE_IO_1V8_ONLY,
4983 PULL_TYPE_IO_DEFAULT,
4984 PULL_TYPE_IO_DEFAULT,
4985 PULL_TYPE_IO_1V8_ONLY,
4986 PULL_TYPE_IO_1V8_ONLY
4987 ),
4988 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4989 DRV_TYPE_IO_3V3_ONLY,
4990 DRV_TYPE_IO_3V3_ONLY,
4991 DRV_TYPE_IO_1V8_OR_3V0
4992 ),
4993 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4994 DRV_TYPE_IO_1V8_3V0_AUTO,
4995 DRV_TYPE_IO_1V8_OR_3V0,
4996 DRV_TYPE_IO_1V8_OR_3V0
4997 ),
4998 };
4999
5000 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
5001 .pin_banks = rk3399_pin_banks,
5002 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
5003 .label = "RK3399-GPIO",
5004 .type = RK3399,
5005 .grf_mux_offset = 0xe000,
5006 .pmu_mux_offset = 0x0,
5007 .grf_drv_offset = 0xe100,
5008 .pmu_drv_offset = 0x80,
5009 .iomux_routes = rk3399_mux_route_data,
5010 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
5011 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
5012 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
5013 };
5014
5015 static struct rockchip_pin_bank rk3506_pin_banks[] = {
5016 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(0, 32, "gpio0",
5017 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
5018 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
5019 IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
5020 IOMUX_WIDTH_2BIT | IOMUX_SOURCE_PMU,
5021 0x0, 0x8, 0x10, 0x830,
5022 DRV_TYPE_IO_LEVEL_8_BIT,
5023 DRV_TYPE_IO_LEVEL_8_BIT,
5024 DRV_TYPE_IO_LEVEL_8_BIT,
5025 DRV_TYPE_IO_LEVEL_2_BIT,
5026 0, 0, 0, 1),
5027 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(1, 32, "gpio1",
5028 IOMUX_WIDTH_4BIT,
5029 IOMUX_WIDTH_4BIT,
5030 IOMUX_WIDTH_4BIT,
5031 IOMUX_WIDTH_4BIT,
5032 0x20, 0x28, 0x30, 0x38,
5033 DRV_TYPE_IO_LEVEL_8_BIT,
5034 DRV_TYPE_IO_LEVEL_8_BIT,
5035 DRV_TYPE_IO_LEVEL_8_BIT,
5036 DRV_TYPE_IO_LEVEL_8_BIT),
5037 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(2, 32, "gpio2",
5038 IOMUX_WIDTH_4BIT,
5039 IOMUX_WIDTH_4BIT,
5040 IOMUX_WIDTH_4BIT,
5041 IOMUX_WIDTH_4BIT,
5042 0x40, 0x48, 0x50, 0x58,
5043 DRV_TYPE_IO_LEVEL_8_BIT,
5044 DRV_TYPE_IO_LEVEL_8_BIT,
5045 DRV_TYPE_IO_LEVEL_8_BIT,
5046 DRV_TYPE_IO_LEVEL_8_BIT),
5047 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS(3, 32, "gpio3",
5048 IOMUX_WIDTH_4BIT,
5049 IOMUX_WIDTH_4BIT,
5050 IOMUX_WIDTH_4BIT,
5051 IOMUX_WIDTH_4BIT,
5052 0x60, 0x68, 0x70, 0x78,
5053 DRV_TYPE_IO_LEVEL_8_BIT,
5054 DRV_TYPE_IO_LEVEL_8_BIT,
5055 DRV_TYPE_IO_LEVEL_8_BIT,
5056 DRV_TYPE_IO_LEVEL_8_BIT),
5057 PIN_BANK_IOMUX_FLAGS_OFFSET_DRV_FLAGS_PULL_FLAGS(4, 32, "gpio4",
5058 IOMUX_WIDTH_4BIT,
5059 IOMUX_WIDTH_4BIT,
5060 IOMUX_WIDTH_4BIT,
5061 IOMUX_WIDTH_4BIT,
5062 0x80, 0x88, 0x90, 0x98,
5063 DRV_TYPE_IO_LEVEL_2_BIT,
5064 DRV_TYPE_IO_LEVEL_2_BIT,
5065 DRV_TYPE_IO_LEVEL_2_BIT,
5066 DRV_TYPE_IO_LEVEL_2_BIT,
5067 1, 1, 1, 1),
5068 };
5069
5070 static struct rockchip_pin_ctrl rk3506_pin_ctrl __maybe_unused = {
5071 .pin_banks = rk3506_pin_banks,
5072 .nr_banks = ARRAY_SIZE(rk3506_pin_banks),
5073 .label = "RK3506-GPIO",
5074 .type = RK3506,
5075 .pull_calc_reg = rk3506_calc_pull_reg_and_bit,
5076 .drv_calc_reg = rk3506_calc_drv_reg_and_bit,
5077 .schmitt_calc_reg = rk3506_calc_schmitt_reg_and_bit,
5078 };
5079
5080 static struct rockchip_pin_bank rk3528_pin_banks[] = {
5081 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
5082 IOMUX_WIDTH_4BIT,
5083 IOMUX_WIDTH_4BIT,
5084 IOMUX_WIDTH_4BIT,
5085 IOMUX_WIDTH_4BIT,
5086 0, 0, 0, 0),
5087 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
5088 IOMUX_WIDTH_4BIT,
5089 IOMUX_WIDTH_4BIT,
5090 IOMUX_WIDTH_4BIT,
5091 IOMUX_WIDTH_4BIT,
5092 0x20020, 0x20028, 0x20030, 0x20038),
5093 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
5094 IOMUX_WIDTH_4BIT,
5095 IOMUX_WIDTH_4BIT,
5096 IOMUX_WIDTH_4BIT,
5097 IOMUX_WIDTH_4BIT,
5098 0x30040, 0, 0, 0),
5099 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
5100 IOMUX_WIDTH_4BIT,
5101 IOMUX_WIDTH_4BIT,
5102 IOMUX_WIDTH_4BIT,
5103 IOMUX_WIDTH_4BIT,
5104 0x20060, 0x20068, 0x20070, 0),
5105 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
5106 IOMUX_WIDTH_4BIT,
5107 IOMUX_WIDTH_4BIT,
5108 IOMUX_WIDTH_4BIT,
5109 IOMUX_WIDTH_4BIT,
5110 0x10080, 0x10088, 0x10090, 0x10098),
5111 };
5112
5113 static struct rockchip_pin_ctrl rk3528_pin_ctrl = {
5114 .pin_banks = rk3528_pin_banks,
5115 .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
5116 .label = "RK3528-GPIO",
5117 .type = RK3528,
5118 .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
5119 .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
5120 .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
5121 };
5122
5123 static struct rockchip_pin_bank rk3562_pin_banks[] = {
5124 PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
5125 IOMUX_WIDTH_4BIT,
5126 IOMUX_WIDTH_4BIT,
5127 IOMUX_WIDTH_4BIT,
5128 IOMUX_WIDTH_4BIT,
5129 0x20000, 0x20008, 0x20010, 0x20018),
5130 PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
5131 IOMUX_WIDTH_4BIT,
5132 IOMUX_WIDTH_4BIT,
5133 IOMUX_WIDTH_4BIT,
5134 IOMUX_WIDTH_4BIT,
5135 0, 0x08, 0x10, 0x18),
5136 PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
5137 IOMUX_WIDTH_4BIT,
5138 IOMUX_WIDTH_4BIT,
5139 IOMUX_WIDTH_4BIT,
5140 IOMUX_WIDTH_4BIT,
5141 0x20, 0, 0, 0),
5142 PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
5143 IOMUX_WIDTH_4BIT,
5144 IOMUX_WIDTH_4BIT,
5145 IOMUX_WIDTH_4BIT,
5146 IOMUX_WIDTH_4BIT,
5147 0x10040, 0x10048, 0x10050, 0x10058),
5148 PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
5149 IOMUX_WIDTH_4BIT,
5150 IOMUX_WIDTH_4BIT,
5151 0,
5152 0,
5153 0x10060, 0x10068, 0, 0),
5154 };
5155
5156 static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
5157 .pin_banks = rk3562_pin_banks,
5158 .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
5159 .label = "RK3562-GPIO",
5160 .type = RK3562,
5161 .pull_calc_reg = rk3562_calc_pull_reg_and_bit,
5162 .drv_calc_reg = rk3562_calc_drv_reg_and_bit,
5163 .schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
5164 };
5165
5166 static struct rockchip_pin_bank rk3568_pin_banks[] = {
5167 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
5168 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
5169 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
5170 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
5171 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
5172 IOMUX_WIDTH_4BIT,
5173 IOMUX_WIDTH_4BIT,
5174 IOMUX_WIDTH_4BIT),
5175 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
5176 IOMUX_WIDTH_4BIT,
5177 IOMUX_WIDTH_4BIT,
5178 IOMUX_WIDTH_4BIT),
5179 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
5180 IOMUX_WIDTH_4BIT,
5181 IOMUX_WIDTH_4BIT,
5182 IOMUX_WIDTH_4BIT),
5183 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
5184 IOMUX_WIDTH_4BIT,
5185 IOMUX_WIDTH_4BIT,
5186 IOMUX_WIDTH_4BIT),
5187 };
5188
5189 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
5190 .pin_banks = rk3568_pin_banks,
5191 .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
5192 .label = "RK3568-GPIO",
5193 .type = RK3568,
5194 .grf_mux_offset = 0x0,
5195 .pmu_mux_offset = 0x0,
5196 .grf_drv_offset = 0x0200,
5197 .pmu_drv_offset = 0x0070,
5198 .iomux_routes = rk3568_mux_route_data,
5199 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
5200 .pull_calc_reg = rk3568_calc_pull_reg_and_bit,
5201 .drv_calc_reg = rk3568_calc_drv_reg_and_bit,
5202 .schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
5203 };
5204
5205 #define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
5206 PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
5207 IOMUX_WIDTH_4BIT, \
5208 IOMUX_WIDTH_4BIT, \
5209 IOMUX_WIDTH_4BIT, \
5210 IOMUX_WIDTH_4BIT, \
5211 OFFSET0, OFFSET1, \
5212 OFFSET2, OFFSET3, \
5213 PULL_TYPE_IO_1V8_ONLY, \
5214 PULL_TYPE_IO_1V8_ONLY, \
5215 PULL_TYPE_IO_1V8_ONLY, \
5216 PULL_TYPE_IO_1V8_ONLY)
5217
5218 static struct rockchip_pin_bank rk3576_pin_banks[] = {
5219 RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
5220 RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
5221 RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
5222 RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
5223 RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
5224 };
5225
5226 static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
5227 .pin_banks = rk3576_pin_banks,
5228 .nr_banks = ARRAY_SIZE(rk3576_pin_banks),
5229 .label = "RK3576-GPIO",
5230 .type = RK3576,
5231 .pull_calc_reg = rk3576_calc_pull_reg_and_bit,
5232 .drv_calc_reg = rk3576_calc_drv_reg_and_bit,
5233 .schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit,
5234 };
5235
5236 static struct rockchip_pin_bank rk3588_pin_banks[] = {
5237 RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
5238 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5239 RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
5240 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5241 RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
5242 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5243 RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
5244 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5245 RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
5246 IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
5247 };
5248
5249 static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
5250 .pin_banks = rk3588_pin_banks,
5251 .nr_banks = ARRAY_SIZE(rk3588_pin_banks),
5252 .label = "RK3588-GPIO",
5253 .type = RK3588,
5254 .pull_calc_reg = rk3588_calc_pull_reg_and_bit,
5255 .drv_calc_reg = rk3588_calc_drv_reg_and_bit,
5256 .schmitt_calc_reg = rk3588_calc_schmitt_reg_and_bit,
5257 };
5258
5259 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
5260 { .compatible = "rockchip,px30-pinctrl",
5261 .data = &px30_pin_ctrl },
5262 { .compatible = "rockchip,rv1103b-pinctrl",
5263 .data = &rv1103b_pin_ctrl },
5264 { .compatible = "rockchip,rv1108-pinctrl",
5265 .data = &rv1108_pin_ctrl },
5266 { .compatible = "rockchip,rv1126-pinctrl",
5267 .data = &rv1126_pin_ctrl },
5268 { .compatible = "rockchip,rk2928-pinctrl",
5269 .data = &rk2928_pin_ctrl },
5270 { .compatible = "rockchip,rk3036-pinctrl",
5271 .data = &rk3036_pin_ctrl },
5272 { .compatible = "rockchip,rk3066a-pinctrl",
5273 .data = &rk3066a_pin_ctrl },
5274 { .compatible = "rockchip,rk3066b-pinctrl",
5275 .data = &rk3066b_pin_ctrl },
5276 { .compatible = "rockchip,rk3128-pinctrl",
5277 .data = (void *)&rk3128_pin_ctrl },
5278 { .compatible = "rockchip,rk3188-pinctrl",
5279 .data = &rk3188_pin_ctrl },
5280 { .compatible = "rockchip,rk3228-pinctrl",
5281 .data = &rk3228_pin_ctrl },
5282 { .compatible = "rockchip,rk3288-pinctrl",
5283 .data = &rk3288_pin_ctrl },
5284 { .compatible = "rockchip,rk3308-pinctrl",
5285 .data = &rk3308_pin_ctrl },
5286 { .compatible = "rockchip,rk3328-pinctrl",
5287 .data = &rk3328_pin_ctrl },
5288 { .compatible = "rockchip,rk3368-pinctrl",
5289 .data = &rk3368_pin_ctrl },
5290 { .compatible = "rockchip,rk3399-pinctrl",
5291 .data = &rk3399_pin_ctrl },
5292 { .compatible = "rockchip,rk3506-pinctrl",
5293 .data = &rk3506_pin_ctrl },
5294 { .compatible = "rockchip,rk3528-pinctrl",
5295 .data = &rk3528_pin_ctrl },
5296 { .compatible = "rockchip,rk3562-pinctrl",
5297 .data = &rk3562_pin_ctrl },
5298 { .compatible = "rockchip,rk3568-pinctrl",
5299 .data = &rk3568_pin_ctrl },
5300 { .compatible = "rockchip,rk3576-pinctrl",
5301 .data = &rk3576_pin_ctrl },
5302 { .compatible = "rockchip,rk3588-pinctrl",
5303 .data = &rk3588_pin_ctrl },
5304 {},
5305 };
5306
5307 static struct platform_driver rockchip_pinctrl_driver = {
5308 .probe = rockchip_pinctrl_probe,
5309 .remove = rockchip_pinctrl_remove,
5310 .driver = {
5311 .name = "rockchip-pinctrl",
5312 .pm = &rockchip_pinctrl_dev_pm_ops,
5313 .of_match_table = rockchip_pinctrl_dt_match,
5314 },
5315 };
5316
rockchip_pinctrl_drv_register(void)5317 static int __init rockchip_pinctrl_drv_register(void)
5318 {
5319 return platform_driver_register(&rockchip_pinctrl_driver);
5320 }
5321 postcore_initcall(rockchip_pinctrl_drv_register);
5322
rockchip_pinctrl_drv_unregister(void)5323 static void __exit rockchip_pinctrl_drv_unregister(void)
5324 {
5325 platform_driver_unregister(&rockchip_pinctrl_driver);
5326 }
5327 module_exit(rockchip_pinctrl_drv_unregister);
5328
5329 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
5330 MODULE_LICENSE("GPL");
5331 MODULE_ALIAS("platform:pinctrl-rockchip");
5332 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
5333