1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copied from arch/arm64/kernel/cpufeature.c
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/ctype.h>
14 #include <linux/log2.h>
15 #include <linux/memory.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <asm/acpi.h>
19 #include <asm/alternative.h>
20 #include <asm/bugs.h>
21 #include <asm/cacheflush.h>
22 #include <asm/cpufeature.h>
23 #include <asm/hwcap.h>
24 #include <asm/text-patching.h>
25 #include <asm/hwprobe.h>
26 #include <asm/processor.h>
27 #include <asm/sbi.h>
28 #include <asm/vector.h>
29 #include <asm/vendor_extensions.h>
30 #include <asm/vendor_extensions/thead.h>
31
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33
34 static bool any_cpu_has_zicboz;
35 static bool any_cpu_has_zicbop;
36 static bool any_cpu_has_zicbom;
37
38 unsigned long elf_hwcap __read_mostly;
39
40 /* Host ISA bitmap */
41 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
42
43 /* Per-cpu ISA extensions. */
44 struct riscv_isainfo hart_isa[NR_CPUS];
45
46 u32 thead_vlenb_of;
47
48 /**
49 * riscv_isa_extension_base() - Get base extension word
50 *
51 * @isa_bitmap: ISA bitmap to use
52 * Return: base extension word as unsigned long value
53 *
54 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
55 */
riscv_isa_extension_base(const unsigned long * isa_bitmap)56 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
57 {
58 return !isa_bitmap ? riscv_isa[0] : isa_bitmap[0];
59 }
60 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
61
62 /**
63 * __riscv_isa_extension_available() - Check whether given extension
64 * is available or not
65 *
66 * @isa_bitmap: ISA bitmap to use
67 * @bit: bit position of the desired extension
68 * Return: true or false
69 *
70 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
71 */
__riscv_isa_extension_available(const unsigned long * isa_bitmap,unsigned int bit)72 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit)
73 {
74 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
75
76 if (bit >= RISCV_ISA_EXT_MAX)
77 return false;
78
79 return test_bit(bit, bmap);
80 }
81 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
82
riscv_ext_f_depends(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)83 static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data,
84 const unsigned long *isa_bitmap)
85 {
86 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
87 return 0;
88
89 return -EPROBE_DEFER;
90 }
91
riscv_ext_zicbom_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)92 static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
93 const unsigned long *isa_bitmap)
94 {
95 if (!riscv_cbom_block_size) {
96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
97 return -EINVAL;
98 }
99 if (!is_power_of_2(riscv_cbom_block_size)) {
100 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
101 return -EINVAL;
102 }
103
104 any_cpu_has_zicbom = true;
105 return 0;
106 }
107
riscv_ext_zicboz_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)108 static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
109 const unsigned long *isa_bitmap)
110 {
111 if (!riscv_cboz_block_size) {
112 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");
113 return -EINVAL;
114 }
115 if (!is_power_of_2(riscv_cboz_block_size)) {
116 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");
117 return -EINVAL;
118 }
119 any_cpu_has_zicboz = true;
120 return 0;
121 }
122
riscv_ext_zicbop_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)123 static int riscv_ext_zicbop_validate(const struct riscv_isa_ext_data *data,
124 const unsigned long *isa_bitmap)
125 {
126 if (!riscv_cbop_block_size) {
127 pr_err("Zicbop detected in ISA string, disabling as no cbop-block-size found\n");
128 return -EINVAL;
129 }
130 if (!is_power_of_2(riscv_cbop_block_size)) {
131 pr_err("Zicbop disabled as cbop-block-size present, but is not a power-of-2\n");
132 return -EINVAL;
133 }
134 any_cpu_has_zicbop = true;
135 return 0;
136 }
137
riscv_ext_f_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)138 static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data,
139 const unsigned long *isa_bitmap)
140 {
141 if (!IS_ENABLED(CONFIG_FPU))
142 return -EINVAL;
143
144 /*
145 * Due to extension ordering, d is checked before f, so no deferral
146 * is required.
147 */
148 if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) {
149 pr_warn_once("This kernel does not support systems with F but not D\n");
150 return -EINVAL;
151 }
152
153 return 0;
154 }
155
riscv_ext_d_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)156 static int riscv_ext_d_validate(const struct riscv_isa_ext_data *data,
157 const unsigned long *isa_bitmap)
158 {
159 if (!IS_ENABLED(CONFIG_FPU))
160 return -EINVAL;
161
162 return 0;
163 }
164
riscv_ext_vector_x_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)165 static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *data,
166 const unsigned long *isa_bitmap)
167 {
168 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
169 return -EINVAL;
170
171 return 0;
172 }
173
riscv_ext_vector_float_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)174 static int riscv_ext_vector_float_validate(const struct riscv_isa_ext_data *data,
175 const unsigned long *isa_bitmap)
176 {
177 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
178 return -EINVAL;
179
180 if (!IS_ENABLED(CONFIG_FPU))
181 return -EINVAL;
182
183 /*
184 * The kernel doesn't support systems that don't implement both of
185 * F and D, so if any of the vector extensions that do floating point
186 * are to be usable, both floating point extensions need to be usable.
187 *
188 * Since this function validates vector only, and v/Zve* are probed
189 * after f/d, there's no need for a deferral here.
190 */
191 if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
192 return -EINVAL;
193
194 return 0;
195 }
196
riscv_ext_vector_crypto_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)197 static int riscv_ext_vector_crypto_validate(const struct riscv_isa_ext_data *data,
198 const unsigned long *isa_bitmap)
199 {
200 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
201 return -EINVAL;
202
203 /*
204 * It isn't the kernel's job to check that the binding is correct, so
205 * it should be enough to check that any of the vector extensions are
206 * enabled, which in-turn means that vector is usable in this kernel
207 */
208 if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32X))
209 return -EPROBE_DEFER;
210
211 return 0;
212 }
213
riscv_ext_zca_depends(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)214 static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data,
215 const unsigned long *isa_bitmap)
216 {
217 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA))
218 return 0;
219
220 return -EPROBE_DEFER;
221 }
riscv_ext_zcd_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)222 static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data,
223 const unsigned long *isa_bitmap)
224 {
225 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
226 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
227 return 0;
228
229 return -EPROBE_DEFER;
230 }
231
riscv_ext_zcf_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)232 static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
233 const unsigned long *isa_bitmap)
234 {
235 if (IS_ENABLED(CONFIG_64BIT))
236 return -EINVAL;
237
238 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
239 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
240 return 0;
241
242 return -EPROBE_DEFER;
243 }
244
riscv_vector_f_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)245 static int riscv_vector_f_validate(const struct riscv_isa_ext_data *data,
246 const unsigned long *isa_bitmap)
247 {
248 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
249 return -EINVAL;
250
251 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32F))
252 return 0;
253
254 return -EPROBE_DEFER;
255 }
256
riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)257 static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,
258 const unsigned long *isa_bitmap)
259 {
260 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZFBFMIN) &&
261 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVFBFMIN))
262 return 0;
263
264 return -EPROBE_DEFER;
265 }
266
riscv_ext_svadu_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)267 static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
268 const unsigned long *isa_bitmap)
269 {
270 /* SVADE has already been detected, use SVADE only */
271 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE))
272 return -EOPNOTSUPP;
273
274 return 0;
275 }
276
277 static const unsigned int riscv_a_exts[] = {
278 RISCV_ISA_EXT_ZAAMO,
279 RISCV_ISA_EXT_ZALRSC,
280 };
281
282 static const unsigned int riscv_zk_bundled_exts[] = {
283 RISCV_ISA_EXT_ZBKB,
284 RISCV_ISA_EXT_ZBKC,
285 RISCV_ISA_EXT_ZBKX,
286 RISCV_ISA_EXT_ZKND,
287 RISCV_ISA_EXT_ZKNE,
288 RISCV_ISA_EXT_ZKR,
289 RISCV_ISA_EXT_ZKT,
290 };
291
292 static const unsigned int riscv_zkn_bundled_exts[] = {
293 RISCV_ISA_EXT_ZBKB,
294 RISCV_ISA_EXT_ZBKC,
295 RISCV_ISA_EXT_ZBKX,
296 RISCV_ISA_EXT_ZKND,
297 RISCV_ISA_EXT_ZKNE,
298 RISCV_ISA_EXT_ZKNH,
299 };
300
301 static const unsigned int riscv_zks_bundled_exts[] = {
302 RISCV_ISA_EXT_ZBKB,
303 RISCV_ISA_EXT_ZBKC,
304 RISCV_ISA_EXT_ZKSED,
305 RISCV_ISA_EXT_ZKSH
306 };
307
308 #define RISCV_ISA_EXT_ZVKN \
309 RISCV_ISA_EXT_ZVKNED, \
310 RISCV_ISA_EXT_ZVKNHB, \
311 RISCV_ISA_EXT_ZVKB, \
312 RISCV_ISA_EXT_ZVKT
313
314 static const unsigned int riscv_zvkn_bundled_exts[] = {
315 RISCV_ISA_EXT_ZVKN
316 };
317
318 static const unsigned int riscv_zvknc_bundled_exts[] = {
319 RISCV_ISA_EXT_ZVKN,
320 RISCV_ISA_EXT_ZVBC
321 };
322
323 static const unsigned int riscv_zvkng_bundled_exts[] = {
324 RISCV_ISA_EXT_ZVKN,
325 RISCV_ISA_EXT_ZVKG
326 };
327
328 #define RISCV_ISA_EXT_ZVKS \
329 RISCV_ISA_EXT_ZVKSED, \
330 RISCV_ISA_EXT_ZVKSH, \
331 RISCV_ISA_EXT_ZVKB, \
332 RISCV_ISA_EXT_ZVKT
333
334 static const unsigned int riscv_zvks_bundled_exts[] = {
335 RISCV_ISA_EXT_ZVKS
336 };
337
338 static const unsigned int riscv_zvksc_bundled_exts[] = {
339 RISCV_ISA_EXT_ZVKS,
340 RISCV_ISA_EXT_ZVBC
341 };
342
343 static const unsigned int riscv_zvksg_bundled_exts[] = {
344 RISCV_ISA_EXT_ZVKS,
345 RISCV_ISA_EXT_ZVKG
346 };
347
348 static const unsigned int riscv_zvbb_exts[] = {
349 RISCV_ISA_EXT_ZVKB
350 };
351
352 #define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \
353 RISCV_ISA_EXT_ZVE64X, \
354 RISCV_ISA_EXT_ZVE32F, \
355 RISCV_ISA_EXT_ZVE32X
356
357 #define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \
358 RISCV_ISA_EXT_ZVE64F, \
359 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
360
361 #define RISCV_ISA_EXT_V_IMPLY_LIST \
362 RISCV_ISA_EXT_ZVE64D, \
363 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
364
365 static const unsigned int riscv_zve32f_exts[] = {
366 RISCV_ISA_EXT_ZVE32X
367 };
368
369 static const unsigned int riscv_zve64f_exts[] = {
370 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
371 };
372
373 static const unsigned int riscv_zve64d_exts[] = {
374 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
375 };
376
377 static const unsigned int riscv_v_exts[] = {
378 RISCV_ISA_EXT_V_IMPLY_LIST
379 };
380
381 static const unsigned int riscv_zve64x_exts[] = {
382 RISCV_ISA_EXT_ZVE32X,
383 RISCV_ISA_EXT_ZVE64X
384 };
385
386 /*
387 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
388 * privileged ISA, the existence of the CSRs is implied by any extension which
389 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
390 * existence of the CSR, and treat it as a subset of those other extensions.
391 */
392 static const unsigned int riscv_xlinuxenvcfg_exts[] = {
393 RISCV_ISA_EXT_XLINUXENVCFG
394 };
395
396 /*
397 * Zc* spec states that:
398 * - C always implies Zca
399 * - C+F implies Zcf (RV32 only)
400 * - C+D implies Zcd
401 *
402 * These extensions will be enabled and then validated depending on the
403 * availability of F/D RV32.
404 */
405 static const unsigned int riscv_c_exts[] = {
406 RISCV_ISA_EXT_ZCA,
407 RISCV_ISA_EXT_ZCF,
408 RISCV_ISA_EXT_ZCD,
409 };
410
411 /*
412 * The canonical order of ISA extension names in the ISA string is defined in
413 * chapter 27 of the unprivileged specification.
414 *
415 * Ordinarily, for in-kernel data structures, this order is unimportant but
416 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
417 *
418 * The specification uses vague wording, such as should, when it comes to
419 * ordering, so for our purposes the following rules apply:
420 *
421 * 1. All multi-letter extensions must be separated from other extensions by an
422 * underscore.
423 *
424 * 2. Additional standard extensions (starting with 'Z') must be sorted after
425 * single-letter extensions and before any higher-privileged extensions.
426 *
427 * 3. The first letter following the 'Z' conventionally indicates the most
428 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
429 * If multiple 'Z' extensions are named, they must be ordered first by
430 * category, then alphabetically within a category.
431 *
432 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
433 * after standard unprivileged extensions. If multiple supervisor-level
434 * extensions are listed, they must be ordered alphabetically.
435 *
436 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
437 * after any lower-privileged, standard extensions. If multiple
438 * machine-level extensions are listed, they must be ordered
439 * alphabetically.
440 *
441 * 5. Non-standard extensions (starting with 'X') must be listed after all
442 * standard extensions. If multiple non-standard extensions are listed, they
443 * must be ordered alphabetically.
444 *
445 * An example string following the order is:
446 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
447 *
448 * New entries to this struct should follow the ordering rules described above.
449 */
450 const struct riscv_isa_ext_data riscv_isa_ext[] = {
451 __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
452 __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
453 __RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_a, riscv_a_exts),
454 __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate),
455 __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate),
456 __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
457 __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
458 __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
459 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
460 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
461 __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
462 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
463 __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
464 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
465 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
466 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
467 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
468 __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
469 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
470 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
471 __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
472 __RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
473 __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
474 __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
475 __RISCV_ISA_EXT_DATA(zalrsc, RISCV_ISA_EXT_ZALRSC),
476 __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
477 __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
478 __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends),
479 __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
480 __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
481 __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
482 __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends),
483 __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
484 __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate),
485 __RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends),
486 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
487 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
488 __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
489 __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
490 __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
491 __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
492 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
493 __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts),
494 __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts),
495 __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
496 __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
497 __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
498 __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
499 __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts),
500 __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
501 __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
502 __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
503 __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
504 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts, riscv_ext_vector_crypto_validate),
505 __RISCV_ISA_EXT_DATA_VALIDATE(zvbc, RISCV_ISA_EXT_ZVBC, riscv_ext_vector_crypto_validate),
506 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts, riscv_ext_vector_float_validate),
507 __RISCV_ISA_EXT_DATA_VALIDATE(zve32x, RISCV_ISA_EXT_ZVE32X, riscv_ext_vector_x_validate),
508 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts, riscv_ext_vector_float_validate),
509 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts, riscv_ext_vector_float_validate),
510 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts, riscv_ext_vector_x_validate),
511 __RISCV_ISA_EXT_DATA_VALIDATE(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN, riscv_vector_f_validate),
512 __RISCV_ISA_EXT_DATA_VALIDATE(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA, riscv_ext_zvfbfwma_validate),
513 __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
514 __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
515 __RISCV_ISA_EXT_DATA_VALIDATE(zvkb, RISCV_ISA_EXT_ZVKB, riscv_ext_vector_crypto_validate),
516 __RISCV_ISA_EXT_DATA_VALIDATE(zvkg, RISCV_ISA_EXT_ZVKG, riscv_ext_vector_crypto_validate),
517 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkn, riscv_zvkn_bundled_exts, riscv_ext_vector_crypto_validate),
518 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvknc, riscv_zvknc_bundled_exts, riscv_ext_vector_crypto_validate),
519 __RISCV_ISA_EXT_DATA_VALIDATE(zvkned, RISCV_ISA_EXT_ZVKNED, riscv_ext_vector_crypto_validate),
520 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkng, riscv_zvkng_bundled_exts, riscv_ext_vector_crypto_validate),
521 __RISCV_ISA_EXT_DATA_VALIDATE(zvknha, RISCV_ISA_EXT_ZVKNHA, riscv_ext_vector_crypto_validate),
522 __RISCV_ISA_EXT_DATA_VALIDATE(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_ext_vector_crypto_validate),
523 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvks, riscv_zvks_bundled_exts, riscv_ext_vector_crypto_validate),
524 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksc, riscv_zvksc_bundled_exts, riscv_ext_vector_crypto_validate),
525 __RISCV_ISA_EXT_DATA_VALIDATE(zvksed, RISCV_ISA_EXT_ZVKSED, riscv_ext_vector_crypto_validate),
526 __RISCV_ISA_EXT_DATA_VALIDATE(zvksh, RISCV_ISA_EXT_ZVKSH, riscv_ext_vector_crypto_validate),
527 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ext_vector_crypto_validate),
528 __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_crypto_validate),
529 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
530 __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
531 __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts),
532 __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
533 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
534 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
535 __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
536 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
537 __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
538 __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
539 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
540 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
541 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
542 __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
543 };
544
545 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
546
riscv_isa_set_ext(const struct riscv_isa_ext_data * ext,unsigned long * bitmap)547 static void riscv_isa_set_ext(const struct riscv_isa_ext_data *ext, unsigned long *bitmap)
548 {
549 if (ext->id != RISCV_ISA_EXT_INVALID)
550 set_bit(ext->id, bitmap);
551
552 for (int i = 0; i < ext->subset_ext_size; i++) {
553 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID)
554 set_bit(ext->subset_ext_ids[i], bitmap);
555 }
556 }
557
riscv_get_isa_ext_data(unsigned int ext_id)558 static const struct riscv_isa_ext_data *riscv_get_isa_ext_data(unsigned int ext_id)
559 {
560 for (int i = 0; i < riscv_isa_ext_count; i++) {
561 if (riscv_isa_ext[i].id == ext_id)
562 return &riscv_isa_ext[i];
563 }
564
565 return NULL;
566 }
567
568 /*
569 * "Resolve" a source ISA bitmap into one that matches kernel configuration as
570 * well as correct extension dependencies. Some extensions depends on specific
571 * kernel configuration to be usable (V needs CONFIG_RISCV_ISA_V for instance)
572 * and this function will actually validate all the extensions provided in
573 * source_isa into the resolved_isa based on extensions validate() callbacks.
574 */
riscv_resolve_isa(unsigned long * source_isa,unsigned long * resolved_isa,unsigned long * this_hwcap,unsigned long * isa2hwcap)575 static void __init riscv_resolve_isa(unsigned long *source_isa,
576 unsigned long *resolved_isa, unsigned long *this_hwcap,
577 unsigned long *isa2hwcap)
578 {
579 bool loop;
580 const struct riscv_isa_ext_data *ext;
581 DECLARE_BITMAP(prev_resolved_isa, RISCV_ISA_EXT_MAX);
582 int max_loop_count = riscv_isa_ext_count, ret;
583 unsigned int bit;
584
585 do {
586 loop = false;
587 if (max_loop_count-- < 0) {
588 pr_err("Failed to reach a stable ISA state\n");
589 return;
590 }
591 bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX);
592 for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) {
593 ext = riscv_get_isa_ext_data(bit);
594
595 if (ext && ext->validate) {
596 ret = ext->validate(ext, resolved_isa);
597 if (ret == -EPROBE_DEFER) {
598 loop = true;
599 continue;
600 } else if (ret) {
601 /* Disable the extension entirely */
602 clear_bit(bit, source_isa);
603 continue;
604 }
605 }
606
607 set_bit(bit, resolved_isa);
608 /* No need to keep it in source isa now that it is enabled */
609 clear_bit(bit, source_isa);
610
611 /* Single letter extensions get set in hwcap */
612 if (bit < RISCV_ISA_EXT_BASE)
613 *this_hwcap |= isa2hwcap[bit];
614 }
615 } while (loop && !bitmap_equal(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX));
616 }
617
match_isa_ext(const char * name,const char * name_end,unsigned long * bitmap)618 static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap)
619 {
620 for (int i = 0; i < riscv_isa_ext_count; i++) {
621 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
622
623 if ((name_end - name == strlen(ext->name)) &&
624 !strncasecmp(name, ext->name, name_end - name)) {
625 riscv_isa_set_ext(ext, bitmap);
626 break;
627 }
628 }
629 }
630
riscv_parse_isa_string(const char * isa,unsigned long * bitmap)631 static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap)
632 {
633 /*
634 * For all possible cpus, we have already validated in
635 * the boot process that they at least contain "rv" and
636 * whichever of "32"/"64" this kernel supports, and so this
637 * section can be skipped.
638 */
639 isa += 4;
640
641 while (*isa) {
642 const char *ext = isa++;
643 const char *ext_end = isa;
644 bool ext_err = false;
645
646 switch (*ext) {
647 case 'x':
648 case 'X':
649 if (acpi_disabled)
650 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
651 /*
652 * To skip an extension, we find its end.
653 * As multi-letter extensions must be split from other multi-letter
654 * extensions with an "_", the end of a multi-letter extension will
655 * either be the null character or the "_" at the start of the next
656 * multi-letter extension.
657 */
658 for (; *isa && *isa != '_'; ++isa)
659 ;
660 ext_err = true;
661 break;
662 case 's':
663 /*
664 * Workaround for invalid single-letter 's' & 'u' (QEMU).
665 * No need to set the bit in riscv_isa as 's' & 'u' are
666 * not valid ISA extensions. It works unless the first
667 * multi-letter extension in the ISA string begins with
668 * "Su" and is not prefixed with an underscore.
669 */
670 if (ext[-1] != '_' && ext[1] == 'u') {
671 ++isa;
672 ext_err = true;
673 break;
674 }
675 fallthrough;
676 case 'S':
677 case 'z':
678 case 'Z':
679 /*
680 * Before attempting to parse the extension itself, we find its end.
681 * As multi-letter extensions must be split from other multi-letter
682 * extensions with an "_", the end of a multi-letter extension will
683 * either be the null character or the "_" at the start of the next
684 * multi-letter extension.
685 *
686 * Next, as the extensions version is currently ignored, we
687 * eliminate that portion. This is done by parsing backwards from
688 * the end of the extension, removing any numbers. This may be a
689 * major or minor number however, so the process is repeated if a
690 * minor number was found.
691 *
692 * ext_end is intended to represent the first character *after* the
693 * name portion of an extension, but will be decremented to the last
694 * character itself while eliminating the extensions version number.
695 * A simple re-increment solves this problem.
696 */
697 for (; *isa && *isa != '_'; ++isa)
698 if (unlikely(!isalnum(*isa)))
699 ext_err = true;
700
701 ext_end = isa;
702 if (unlikely(ext_err))
703 break;
704
705 if (!isdigit(ext_end[-1]))
706 break;
707
708 while (isdigit(*--ext_end))
709 ;
710
711 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
712 ++ext_end;
713 break;
714 }
715
716 while (isdigit(*--ext_end))
717 ;
718
719 ++ext_end;
720 break;
721 default:
722 /*
723 * Things are a little easier for single-letter extensions, as they
724 * are parsed forwards.
725 *
726 * After checking that our starting position is valid, we need to
727 * ensure that, when isa was incremented at the start of the loop,
728 * that it arrived at the start of the next extension.
729 *
730 * If we are already on a non-digit, there is nothing to do. Either
731 * we have a multi-letter extension's _, or the start of an
732 * extension.
733 *
734 * Otherwise we have found the current extension's major version
735 * number. Parse past it, and a subsequent p/minor version number
736 * if present. The `p` extension must not appear immediately after
737 * a number, so there is no fear of missing it.
738 *
739 */
740 if (unlikely(!isalpha(*ext))) {
741 ext_err = true;
742 break;
743 }
744
745 if (!isdigit(*isa))
746 break;
747
748 while (isdigit(*++isa))
749 ;
750
751 if (tolower(*isa) != 'p')
752 break;
753
754 if (!isdigit(*++isa)) {
755 --isa;
756 break;
757 }
758
759 while (isdigit(*++isa))
760 ;
761
762 break;
763 }
764
765 /*
766 * The parser expects that at the start of an iteration isa points to the
767 * first character of the next extension. As we stop parsing an extension
768 * on meeting a non-alphanumeric character, an extra increment is needed
769 * where the succeeding extension is a multi-letter prefixed with an "_".
770 */
771 if (*isa == '_')
772 ++isa;
773
774 if (unlikely(ext_err))
775 continue;
776
777 match_isa_ext(ext, ext_end, bitmap);
778 }
779 }
780
riscv_fill_hwcap_from_isa_string(unsigned long * isa2hwcap)781 static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
782 {
783 struct device_node *node;
784 const char *isa;
785 int rc;
786 struct acpi_table_header *rhct;
787 acpi_status status;
788 unsigned int cpu;
789 u64 boot_vendorid;
790 u64 boot_archid;
791
792 if (!acpi_disabled) {
793 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
794 if (ACPI_FAILURE(status))
795 return;
796 }
797
798 boot_vendorid = riscv_get_mvendorid();
799 boot_archid = riscv_get_marchid();
800
801 for_each_possible_cpu(cpu) {
802 struct riscv_isainfo *isainfo = &hart_isa[cpu];
803 unsigned long this_hwcap = 0;
804 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
805
806 if (acpi_disabled) {
807 node = of_cpu_device_node_get(cpu);
808 if (!node) {
809 pr_warn("Unable to find cpu node\n");
810 continue;
811 }
812
813 rc = of_property_read_string(node, "riscv,isa", &isa);
814 of_node_put(node);
815 if (rc) {
816 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
817 continue;
818 }
819 } else {
820 rc = acpi_get_riscv_isa(rhct, cpu, &isa);
821 if (rc < 0) {
822 pr_warn("Unable to get ISA for the hart - %d\n", cpu);
823 continue;
824 }
825 }
826
827 riscv_parse_isa_string(isa, source_isa);
828
829 /*
830 * These ones were as they were part of the base ISA when the
831 * port & dt-bindings were upstreamed, and so can be set
832 * unconditionally where `i` is in riscv,isa on DT systems.
833 */
834 if (acpi_disabled) {
835 set_bit(RISCV_ISA_EXT_ZICSR, source_isa);
836 set_bit(RISCV_ISA_EXT_ZIFENCEI, source_isa);
837 set_bit(RISCV_ISA_EXT_ZICNTR, source_isa);
838 set_bit(RISCV_ISA_EXT_ZIHPM, source_isa);
839 }
840
841 /*
842 * "V" in ISA strings is ambiguous in practice: it should mean
843 * just the standard V-1.0 but vendors aren't well behaved.
844 * Many vendors with T-Head CPU cores which implement the 0.7.1
845 * version of the vector specification put "v" into their DTs.
846 * CPU cores with the ratified spec will contain non-zero
847 * marchid.
848 */
849 if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) {
850 this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
851 clear_bit(RISCV_ISA_EXT_v, source_isa);
852 }
853
854 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
855
856 /*
857 * All "okay" hart should have same isa. Set HWCAP based on
858 * common capabilities of every "okay" hart, in case they don't
859 * have.
860 */
861 if (elf_hwcap)
862 elf_hwcap &= this_hwcap;
863 else
864 elf_hwcap = this_hwcap;
865
866 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
867 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
868 else
869 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
870 }
871
872 if (!acpi_disabled && rhct)
873 acpi_put_table((struct acpi_table_header *)rhct);
874 }
875
riscv_fill_cpu_vendor_ext(struct device_node * cpu_node,int cpu)876 static void __init riscv_fill_cpu_vendor_ext(struct device_node *cpu_node, int cpu)
877 {
878 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
879 return;
880
881 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
882 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
883
884 for (int j = 0; j < ext_list->ext_data_count; j++) {
885 const struct riscv_isa_ext_data ext = ext_list->ext_data[j];
886 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu];
887
888 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
889 ext.property) < 0)
890 continue;
891
892 /*
893 * Assume that subset extensions are all members of the
894 * same vendor.
895 */
896 if (ext.subset_ext_size)
897 for (int k = 0; k < ext.subset_ext_size; k++)
898 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa);
899
900 set_bit(ext.id, isavendorinfo->isa);
901 }
902 }
903 }
904
905 /*
906 * Populate all_harts_isa_bitmap for each vendor with all of the extensions that
907 * are shared across CPUs for that vendor.
908 */
riscv_fill_vendor_ext_list(int cpu)909 static void __init riscv_fill_vendor_ext_list(int cpu)
910 {
911 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
912 return;
913
914 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
915 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
916
917 if (!ext_list->is_initialized) {
918 bitmap_copy(ext_list->all_harts_isa_bitmap.isa,
919 ext_list->per_hart_isa_bitmap[cpu].isa,
920 RISCV_ISA_VENDOR_EXT_MAX);
921 ext_list->is_initialized = true;
922 } else {
923 bitmap_and(ext_list->all_harts_isa_bitmap.isa,
924 ext_list->all_harts_isa_bitmap.isa,
925 ext_list->per_hart_isa_bitmap[cpu].isa,
926 RISCV_ISA_VENDOR_EXT_MAX);
927 }
928 }
929 }
930
has_thead_homogeneous_vlenb(void)931 static int has_thead_homogeneous_vlenb(void)
932 {
933 int cpu;
934 u32 prev_vlenb = 0;
935 u32 vlenb;
936
937 /* Ignore thead,vlenb property if xtheavector is not enabled in the kernel */
938 if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR))
939 return 0;
940
941 for_each_possible_cpu(cpu) {
942 struct device_node *cpu_node;
943
944 cpu_node = of_cpu_device_node_get(cpu);
945 if (!cpu_node) {
946 pr_warn("Unable to find cpu node\n");
947 return -ENOENT;
948 }
949
950 if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) {
951 of_node_put(cpu_node);
952
953 if (prev_vlenb)
954 return -ENOENT;
955 continue;
956 }
957
958 if (prev_vlenb && vlenb != prev_vlenb) {
959 of_node_put(cpu_node);
960 return -ENOENT;
961 }
962
963 prev_vlenb = vlenb;
964 of_node_put(cpu_node);
965 }
966
967 thead_vlenb_of = vlenb;
968 return 0;
969 }
970
riscv_fill_hwcap_from_ext_list(unsigned long * isa2hwcap)971 static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
972 {
973 unsigned int cpu;
974 bool mitigated;
975
976 for_each_possible_cpu(cpu) {
977 unsigned long this_hwcap = 0;
978 struct device_node *cpu_node;
979 struct riscv_isainfo *isainfo = &hart_isa[cpu];
980 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
981
982 cpu_node = of_cpu_device_node_get(cpu);
983 if (!cpu_node) {
984 pr_warn("Unable to find cpu node\n");
985 continue;
986 }
987
988 if (!of_property_present(cpu_node, "riscv,isa-extensions")) {
989 of_node_put(cpu_node);
990 continue;
991 }
992
993 for (int i = 0; i < riscv_isa_ext_count; i++) {
994 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
995
996 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
997 ext->property) < 0)
998 continue;
999
1000 riscv_isa_set_ext(ext, source_isa);
1001 }
1002
1003 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
1004 riscv_fill_cpu_vendor_ext(cpu_node, cpu);
1005
1006 of_node_put(cpu_node);
1007
1008 /*
1009 * All "okay" harts should have same isa. Set HWCAP based on
1010 * common capabilities of every "okay" hart, in case they don't.
1011 */
1012 if (elf_hwcap)
1013 elf_hwcap &= this_hwcap;
1014 else
1015 elf_hwcap = this_hwcap;
1016
1017 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
1018 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
1019 else
1020 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
1021
1022 riscv_fill_vendor_ext_list(cpu);
1023 }
1024
1025 /*
1026 * Execute ghostwrite mitigation immediately after detecting extensions
1027 * to disable xtheadvector if necessary.
1028 */
1029 mitigated = ghostwrite_enable_mitigation();
1030
1031 if (!mitigated && has_xtheadvector_no_alternatives() && has_thead_homogeneous_vlenb() < 0) {
1032 pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n");
1033 disable_xtheadvector();
1034 }
1035
1036 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
1037 return -ENOENT;
1038
1039 return 0;
1040 }
1041
1042 #ifdef CONFIG_RISCV_ISA_FALLBACK
1043 bool __initdata riscv_isa_fallback = true;
1044 #else
1045 bool __initdata riscv_isa_fallback;
riscv_isa_fallback_setup(char * __unused)1046 static int __init riscv_isa_fallback_setup(char *__unused)
1047 {
1048 riscv_isa_fallback = true;
1049 return 1;
1050 }
1051 early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
1052 #endif
1053
riscv_fill_hwcap(void)1054 void __init riscv_fill_hwcap(void)
1055 {
1056 char print_str[NUM_ALPHA_EXTS + 1];
1057 unsigned long isa2hwcap[26] = {0};
1058 int i, j;
1059
1060 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
1061 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
1062 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
1063 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
1064 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
1065 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
1066 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
1067
1068 if (!acpi_disabled) {
1069 riscv_fill_hwcap_from_isa_string(isa2hwcap);
1070 } else {
1071 int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
1072
1073 if (ret && riscv_isa_fallback) {
1074 pr_info("Falling back to deprecated \"riscv,isa\"\n");
1075 riscv_fill_hwcap_from_isa_string(isa2hwcap);
1076 }
1077 }
1078
1079 /*
1080 * We don't support systems with F but without D, so mask those out
1081 * here.
1082 */
1083 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
1084 pr_info("This kernel does not support systems with F but not D\n");
1085 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
1086 }
1087
1088 if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X) ||
1089 has_xtheadvector_no_alternatives()) {
1090 /*
1091 * This cannot fail when called on the boot hart
1092 */
1093 riscv_v_setup_vsize();
1094 }
1095
1096 memset(print_str, 0, sizeof(print_str));
1097 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
1098 if (riscv_isa[0] & BIT_MASK(i))
1099 print_str[j++] = (char)('a' + i);
1100 pr_info("riscv: base ISA extensions %s\n", print_str);
1101
1102 memset(print_str, 0, sizeof(print_str));
1103 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
1104 if (elf_hwcap & BIT_MASK(i))
1105 print_str[j++] = (char)('a' + i);
1106 pr_info("riscv: ELF capabilities %s\n", print_str);
1107 }
1108
riscv_get_elf_hwcap(void)1109 unsigned long riscv_get_elf_hwcap(void)
1110 {
1111 unsigned long hwcap;
1112
1113 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
1114
1115 if (!riscv_v_vstate_ctrl_user_allowed())
1116 hwcap &= ~COMPAT_HWCAP_ISA_V;
1117
1118 return hwcap;
1119 }
1120
riscv_user_isa_enable(void)1121 void __init riscv_user_isa_enable(void)
1122 {
1123 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ))
1124 current->thread.envcfg |= ENVCFG_CBZE;
1125 else if (any_cpu_has_zicboz)
1126 pr_warn("Zicboz disabled as it is unavailable on some harts\n");
1127
1128 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM))
1129 current->thread.envcfg |= ENVCFG_CBCFE;
1130 else if (any_cpu_has_zicbom)
1131 pr_warn("Zicbom disabled as it is unavailable on some harts\n");
1132
1133 if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOP) &&
1134 any_cpu_has_zicbop)
1135 pr_warn("Zicbop disabled as it is unavailable on some harts\n");
1136 }
1137
1138 #ifdef CONFIG_RISCV_ALTERNATIVE
1139 /*
1140 * Alternative patch sites consider 48 bits when determining when to patch
1141 * the old instruction sequence with the new. These bits are broken into a
1142 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
1143 * patch site is for an erratum, identified by the 32-bit patch ID. When
1144 * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
1145 * further break down patch ID into two 16-bit numbers. The lower 16 bits
1146 * are the cpufeature ID and the upper 16 bits are used for a value specific
1147 * to the cpufeature and patch site. If the upper 16 bits are zero, then it
1148 * implies no specific value is specified. cpufeatures that want to control
1149 * patching on a per-site basis will provide non-zero values and implement
1150 * checks here. The checks return true when patching should be done, and
1151 * false otherwise.
1152 */
riscv_cpufeature_patch_check(u16 id,u16 value)1153 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
1154 {
1155 if (!value)
1156 return true;
1157
1158 switch (id) {
1159 case RISCV_ISA_EXT_ZICBOZ:
1160 /*
1161 * Zicboz alternative applications provide the maximum
1162 * supported block size order, or zero when it doesn't
1163 * matter. If the current block size exceeds the maximum,
1164 * then the alternative cannot be applied.
1165 */
1166 return riscv_cboz_block_size <= (1U << value);
1167 }
1168
1169 return false;
1170 }
1171
riscv_cpufeature_patch_func(struct alt_entry * begin,struct alt_entry * end,unsigned int stage)1172 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
1173 struct alt_entry *end,
1174 unsigned int stage)
1175 {
1176 struct alt_entry *alt;
1177 void *oldptr, *altptr;
1178 u16 id, value, vendor;
1179
1180 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
1181 return;
1182
1183 for (alt = begin; alt < end; alt++) {
1184 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
1185 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id);
1186
1187 /*
1188 * Any alternative with a patch_id that is less than
1189 * RISCV_ISA_EXT_MAX is interpreted as a standard extension.
1190 *
1191 * Any alternative with patch_id that is greater than or equal
1192 * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a
1193 * vendor extension.
1194 */
1195 if (id < RISCV_ISA_EXT_MAX) {
1196 /*
1197 * This patch should be treated as errata so skip
1198 * processing here.
1199 */
1200 if (alt->vendor_id != 0)
1201 continue;
1202
1203 if (!__riscv_isa_extension_available(NULL, id))
1204 continue;
1205
1206 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
1207 if (!riscv_cpufeature_patch_check(id, value))
1208 continue;
1209 } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) {
1210 if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor,
1211 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE))
1212 continue;
1213 } else {
1214 WARN(1, "This extension id:%d is not in ISA extension list", id);
1215 continue;
1216 }
1217
1218 oldptr = ALT_OLD_PTR(alt);
1219 altptr = ALT_ALT_PTR(alt);
1220
1221 mutex_lock(&text_mutex);
1222 patch_text_nosync(oldptr, altptr, alt->alt_len);
1223 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
1224 mutex_unlock(&text_mutex);
1225 }
1226 }
1227 #endif
1228