xref: /linux/drivers/clocksource/timer-riscv.c (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2012 Regents of the University of California
4  * Copyright (C) 2017 SiFive
5  *
6  * All RISC-V systems have a timer attached to every hart.  These timers can
7  * either be read from the "time" and "timeh" CSRs, and can use the SBI to
8  * setup events, or directly accessed using MMIO registers.
9  */
10 
11 #define pr_fmt(fmt) "riscv-timer: " fmt
12 
13 #include <linux/acpi.h>
14 #include <linux/clocksource.h>
15 #include <linux/clockchips.h>
16 #include <linux/cpu.h>
17 #include <linux/delay.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/module.h>
21 #include <linux/sched_clock.h>
22 #include <linux/io-64-nonatomic-lo-hi.h>
23 #include <linux/interrupt.h>
24 #include <linux/of_irq.h>
25 #include <linux/limits.h>
26 #include <clocksource/timer-riscv.h>
27 #include <asm/smp.h>
28 #include <asm/cpufeature.h>
29 #include <asm/sbi.h>
30 #include <asm/timex.h>
31 
32 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
33 static bool riscv_timer_cannot_wake_cpu;
34 
riscv_clock_event_stop(void)35 static void riscv_clock_event_stop(void)
36 {
37 	if (static_branch_likely(&riscv_sstc_available)) {
38 		csr_write(CSR_STIMECMP, ULONG_MAX);
39 		if (IS_ENABLED(CONFIG_32BIT))
40 			csr_write(CSR_STIMECMPH, ULONG_MAX);
41 	} else {
42 		sbi_set_timer(U64_MAX);
43 	}
44 }
45 
riscv_clock_next_event(unsigned long delta,struct clock_event_device * ce)46 static int riscv_clock_next_event(unsigned long delta,
47 		struct clock_event_device *ce)
48 {
49 	u64 next_tval = get_cycles64() + delta;
50 
51 	if (static_branch_likely(&riscv_sstc_available)) {
52 #if defined(CONFIG_32BIT)
53 		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
54 		csr_write(CSR_STIMECMPH, next_tval >> 32);
55 #else
56 		csr_write(CSR_STIMECMP, next_tval);
57 #endif
58 	} else
59 		sbi_set_timer(next_tval);
60 
61 	return 0;
62 }
63 
riscv_clock_shutdown(struct clock_event_device * evt)64 static int riscv_clock_shutdown(struct clock_event_device *evt)
65 {
66 	riscv_clock_event_stop();
67 	return 0;
68 }
69 
70 static unsigned int riscv_clock_event_irq;
71 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
72 	.name			= "riscv_timer_clockevent",
73 	.features		= CLOCK_EVT_FEAT_ONESHOT,
74 	.rating			= 100,
75 	.set_next_event		= riscv_clock_next_event,
76 	.set_state_shutdown	= riscv_clock_shutdown,
77 };
78 
79 /*
80  * It is guaranteed that all the timers across all the harts are synchronized
81  * within one tick of each other, so while this could technically go
82  * backwards when hopping between CPUs, practically it won't happen.
83  */
riscv_clocksource_rdtime(struct clocksource * cs)84 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
85 {
86 	return get_cycles64();
87 }
88 
riscv_sched_clock(void)89 static u64 notrace riscv_sched_clock(void)
90 {
91 	return get_cycles64();
92 }
93 
94 static struct clocksource riscv_clocksource = {
95 	.name		= "riscv_clocksource",
96 	.rating		= 400,
97 	.mask		= CLOCKSOURCE_MASK(64),
98 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
99 	.read		= riscv_clocksource_rdtime,
100 #if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
101 	.vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
102 #else
103 	.vdso_clock_mode = VDSO_CLOCKMODE_NONE,
104 #endif
105 };
106 
riscv_timer_starting_cpu(unsigned int cpu)107 static int riscv_timer_starting_cpu(unsigned int cpu)
108 {
109 	struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
110 
111 	/* Clear timer interrupt */
112 	riscv_clock_event_stop();
113 
114 	ce->cpumask = cpumask_of(cpu);
115 	ce->irq = riscv_clock_event_irq;
116 	if (riscv_timer_cannot_wake_cpu)
117 		ce->features |= CLOCK_EVT_FEAT_C3STOP;
118 	if (static_branch_likely(&riscv_sstc_available))
119 		ce->rating = 450;
120 	clockevents_config_and_register(ce, riscv_timebase, 100, ULONG_MAX);
121 
122 	enable_percpu_irq(riscv_clock_event_irq,
123 			  irq_get_trigger_type(riscv_clock_event_irq));
124 	return 0;
125 }
126 
riscv_timer_dying_cpu(unsigned int cpu)127 static int riscv_timer_dying_cpu(unsigned int cpu)
128 {
129 	disable_percpu_irq(riscv_clock_event_irq);
130 	return 0;
131 }
132 
riscv_cs_get_mult_shift(u32 * mult,u32 * shift)133 void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
134 {
135 	*mult = riscv_clocksource.mult;
136 	*shift = riscv_clocksource.shift;
137 }
138 EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
139 
140 /* called directly from the low-level interrupt handler */
riscv_timer_interrupt(int irq,void * dev_id)141 static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
142 {
143 	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
144 
145 	riscv_clock_event_stop();
146 	evdev->event_handler(evdev);
147 
148 	return IRQ_HANDLED;
149 }
150 
riscv_timer_init_common(void)151 static int __init riscv_timer_init_common(void)
152 {
153 	int error;
154 	struct irq_domain *domain;
155 	struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
156 
157 	domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
158 	if (!domain) {
159 		pr_err("Failed to find irq_domain for INTC node [%pfwP]\n",
160 		       intc_fwnode);
161 		return -ENODEV;
162 	}
163 
164 	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
165 	if (!riscv_clock_event_irq) {
166 		pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode);
167 		return -ENODEV;
168 	}
169 
170 	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
171 	if (error) {
172 		pr_err("RISCV timer registration failed [%d]\n", error);
173 		return error;
174 	}
175 
176 	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
177 
178 	error = request_percpu_irq(riscv_clock_event_irq,
179 				    riscv_timer_interrupt,
180 				    "riscv-timer", &riscv_clock_event);
181 	if (error) {
182 		pr_err("registering percpu irq failed [%d]\n", error);
183 		return error;
184 	}
185 
186 	if (riscv_isa_extension_available(NULL, SSTC)) {
187 		pr_info("Timer interrupt in S-mode is available via sstc extension\n");
188 		static_branch_enable(&riscv_sstc_available);
189 	}
190 
191 	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
192 			 "clockevents/riscv/timer:starting",
193 			 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
194 	if (error)
195 		pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
196 		       error);
197 
198 	return error;
199 }
200 
riscv_timer_init_dt(struct device_node * n)201 static int __init riscv_timer_init_dt(struct device_node *n)
202 {
203 	int cpuid, error;
204 	unsigned long hartid;
205 	struct device_node *child;
206 
207 	error = riscv_of_processor_hartid(n, &hartid);
208 	if (error < 0) {
209 		pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n",
210 			n, hartid);
211 		return error;
212 	}
213 
214 	cpuid = riscv_hartid_to_cpuid(hartid);
215 	if (cpuid < 0) {
216 		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
217 		return cpuid;
218 	}
219 
220 	if (cpuid != smp_processor_id())
221 		return 0;
222 
223 	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
224 	if (child) {
225 		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
226 					"riscv,timer-cannot-wake-cpu");
227 		of_node_put(child);
228 	}
229 
230 	return riscv_timer_init_common();
231 }
232 
233 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
234 
235 #ifdef CONFIG_ACPI
riscv_timer_acpi_init(struct acpi_table_header * table)236 static int __init riscv_timer_acpi_init(struct acpi_table_header *table)
237 {
238 	struct acpi_table_rhct *rhct = (struct acpi_table_rhct *)table;
239 
240 	riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU;
241 
242 	return riscv_timer_init_common();
243 }
244 
245 TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init);
246 
247 #endif
248