1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copied from arch/arm64/kernel/cpufeature.c
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 * Copyright (C) 2017 SiFive
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitmap.h>
11 #include <linux/cpu.h>
12 #include <linux/cpuhotplug.h>
13 #include <linux/ctype.h>
14 #include <linux/log2.h>
15 #include <linux/memory.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <asm/acpi.h>
19 #include <asm/alternative.h>
20 #include <asm/bugs.h>
21 #include <asm/cacheflush.h>
22 #include <asm/cpufeature.h>
23 #include <asm/hwcap.h>
24 #include <asm/text-patching.h>
25 #include <asm/hwprobe.h>
26 #include <asm/processor.h>
27 #include <asm/sbi.h>
28 #include <asm/vector.h>
29 #include <asm/vendor_extensions.h>
30 #include <asm/vendor_extensions/thead.h>
31
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
33
34 static bool any_cpu_has_zicboz;
35 static bool any_cpu_has_zicbop;
36 static bool any_cpu_has_zicbom;
37
38 unsigned long elf_hwcap __read_mostly;
39
40 /* Host ISA bitmap */
41 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
42
43 /* Per-cpu ISA extensions. */
44 struct riscv_isainfo hart_isa[NR_CPUS];
45
46 u32 thead_vlenb_of;
47
48 /**
49 * riscv_isa_extension_base() - Get base extension word
50 *
51 * @isa_bitmap: ISA bitmap to use
52 * Return: base extension word as unsigned long value
53 *
54 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
55 */
riscv_isa_extension_base(const unsigned long * isa_bitmap)56 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
57 {
58 return !isa_bitmap ? riscv_isa[0] : isa_bitmap[0];
59 }
60 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
61
62 /**
63 * __riscv_isa_extension_available() - Check whether given extension
64 * is available or not
65 *
66 * @isa_bitmap: ISA bitmap to use
67 * @bit: bit position of the desired extension
68 * Return: true or false
69 *
70 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
71 */
__riscv_isa_extension_available(const unsigned long * isa_bitmap,unsigned int bit)72 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit)
73 {
74 const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
75
76 if (bit >= RISCV_ISA_EXT_MAX)
77 return false;
78
79 return test_bit(bit, bmap);
80 }
81 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
82
riscv_ext_f_depends(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)83 static int riscv_ext_f_depends(const struct riscv_isa_ext_data *data,
84 const unsigned long *isa_bitmap)
85 {
86 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
87 return 0;
88
89 return -EPROBE_DEFER;
90 }
91
riscv_ext_zicbom_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)92 static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data,
93 const unsigned long *isa_bitmap)
94 {
95 if (!riscv_cbom_block_size) {
96 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
97 return -EINVAL;
98 }
99 if (!is_power_of_2(riscv_cbom_block_size)) {
100 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
101 return -EINVAL;
102 }
103
104 any_cpu_has_zicbom = true;
105 return 0;
106 }
107
riscv_ext_zicboz_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)108 static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
109 const unsigned long *isa_bitmap)
110 {
111 if (!riscv_cboz_block_size) {
112 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");
113 return -EINVAL;
114 }
115 if (!is_power_of_2(riscv_cboz_block_size)) {
116 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");
117 return -EINVAL;
118 }
119 any_cpu_has_zicboz = true;
120 return 0;
121 }
122
riscv_ext_zicbop_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)123 static int riscv_ext_zicbop_validate(const struct riscv_isa_ext_data *data,
124 const unsigned long *isa_bitmap)
125 {
126 if (!riscv_cbop_block_size) {
127 pr_err("Zicbop detected in ISA string, disabling as no cbop-block-size found\n");
128 return -EINVAL;
129 }
130 if (!is_power_of_2(riscv_cbop_block_size)) {
131 pr_err("Zicbop disabled as cbop-block-size present, but is not a power-of-2\n");
132 return -EINVAL;
133 }
134 any_cpu_has_zicbop = true;
135 return 0;
136 }
137
riscv_ext_f_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)138 static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data,
139 const unsigned long *isa_bitmap)
140 {
141 if (!IS_ENABLED(CONFIG_FPU))
142 return -EINVAL;
143
144 /*
145 * Due to extension ordering, d is checked before f, so no deferral
146 * is required.
147 */
148 if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) {
149 pr_warn_once("This kernel does not support systems with F but not D\n");
150 return -EINVAL;
151 }
152
153 return 0;
154 }
155
riscv_ext_d_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)156 static int riscv_ext_d_validate(const struct riscv_isa_ext_data *data,
157 const unsigned long *isa_bitmap)
158 {
159 if (!IS_ENABLED(CONFIG_FPU))
160 return -EINVAL;
161
162 return 0;
163 }
164
riscv_ext_vector_x_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)165 static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *data,
166 const unsigned long *isa_bitmap)
167 {
168 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
169 return -EINVAL;
170
171 return 0;
172 }
173
riscv_ext_vector_float_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)174 static int riscv_ext_vector_float_validate(const struct riscv_isa_ext_data *data,
175 const unsigned long *isa_bitmap)
176 {
177 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
178 return -EINVAL;
179
180 if (!IS_ENABLED(CONFIG_FPU))
181 return -EINVAL;
182
183 /*
184 * The kernel doesn't support systems that don't implement both of
185 * F and D, so if any of the vector extensions that do floating point
186 * are to be usable, both floating point extensions need to be usable.
187 *
188 * Since this function validates vector only, and v/Zve* are probed
189 * after f/d, there's no need for a deferral here.
190 */
191 if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
192 return -EINVAL;
193
194 return 0;
195 }
196
riscv_ext_vector_crypto_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)197 static int riscv_ext_vector_crypto_validate(const struct riscv_isa_ext_data *data,
198 const unsigned long *isa_bitmap)
199 {
200 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
201 return -EINVAL;
202
203 /*
204 * It isn't the kernel's job to check that the binding is correct, so
205 * it should be enough to check that any of the vector extensions are
206 * enabled, which in-turn means that vector is usable in this kernel
207 */
208 if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32X))
209 return -EPROBE_DEFER;
210
211 return 0;
212 }
213
riscv_ext_zca_depends(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)214 static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data,
215 const unsigned long *isa_bitmap)
216 {
217 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA))
218 return 0;
219
220 return -EPROBE_DEFER;
221 }
riscv_ext_zcd_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)222 static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data,
223 const unsigned long *isa_bitmap)
224 {
225 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
226 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d))
227 return 0;
228
229 return -EPROBE_DEFER;
230 }
231
riscv_ext_zcf_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)232 static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data,
233 const unsigned long *isa_bitmap)
234 {
235 if (IS_ENABLED(CONFIG_64BIT))
236 return -EINVAL;
237
238 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) &&
239 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f))
240 return 0;
241
242 return -EPROBE_DEFER;
243 }
244
riscv_ext_zilsd_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)245 static int riscv_ext_zilsd_validate(const struct riscv_isa_ext_data *data,
246 const unsigned long *isa_bitmap)
247 {
248 if (IS_ENABLED(CONFIG_64BIT))
249 return -EINVAL;
250
251 return 0;
252 }
253
riscv_ext_zclsd_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)254 static int riscv_ext_zclsd_validate(const struct riscv_isa_ext_data *data,
255 const unsigned long *isa_bitmap)
256 {
257 if (IS_ENABLED(CONFIG_64BIT))
258 return -EINVAL;
259
260 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZILSD) &&
261 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA))
262 return 0;
263
264 return -EPROBE_DEFER;
265 }
266
riscv_vector_f_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)267 static int riscv_vector_f_validate(const struct riscv_isa_ext_data *data,
268 const unsigned long *isa_bitmap)
269 {
270 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
271 return -EINVAL;
272
273 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32F))
274 return 0;
275
276 return -EPROBE_DEFER;
277 }
278
riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)279 static int riscv_ext_zvfbfwma_validate(const struct riscv_isa_ext_data *data,
280 const unsigned long *isa_bitmap)
281 {
282 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZFBFMIN) &&
283 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVFBFMIN))
284 return 0;
285
286 return -EPROBE_DEFER;
287 }
288
riscv_ext_svadu_validate(const struct riscv_isa_ext_data * data,const unsigned long * isa_bitmap)289 static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
290 const unsigned long *isa_bitmap)
291 {
292 /* SVADE has already been detected, use SVADE only */
293 if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE))
294 return -EOPNOTSUPP;
295
296 return 0;
297 }
298
299 static const unsigned int riscv_a_exts[] = {
300 RISCV_ISA_EXT_ZAAMO,
301 RISCV_ISA_EXT_ZALRSC,
302 };
303
304 static const unsigned int riscv_zk_bundled_exts[] = {
305 RISCV_ISA_EXT_ZBKB,
306 RISCV_ISA_EXT_ZBKC,
307 RISCV_ISA_EXT_ZBKX,
308 RISCV_ISA_EXT_ZKND,
309 RISCV_ISA_EXT_ZKNE,
310 RISCV_ISA_EXT_ZKR,
311 RISCV_ISA_EXT_ZKT,
312 };
313
314 static const unsigned int riscv_zkn_bundled_exts[] = {
315 RISCV_ISA_EXT_ZBKB,
316 RISCV_ISA_EXT_ZBKC,
317 RISCV_ISA_EXT_ZBKX,
318 RISCV_ISA_EXT_ZKND,
319 RISCV_ISA_EXT_ZKNE,
320 RISCV_ISA_EXT_ZKNH,
321 };
322
323 static const unsigned int riscv_zks_bundled_exts[] = {
324 RISCV_ISA_EXT_ZBKB,
325 RISCV_ISA_EXT_ZBKC,
326 RISCV_ISA_EXT_ZKSED,
327 RISCV_ISA_EXT_ZKSH
328 };
329
330 #define RISCV_ISA_EXT_ZVKN \
331 RISCV_ISA_EXT_ZVKNED, \
332 RISCV_ISA_EXT_ZVKNHB, \
333 RISCV_ISA_EXT_ZVKB, \
334 RISCV_ISA_EXT_ZVKT
335
336 static const unsigned int riscv_zvkn_bundled_exts[] = {
337 RISCV_ISA_EXT_ZVKN
338 };
339
340 static const unsigned int riscv_zvknc_bundled_exts[] = {
341 RISCV_ISA_EXT_ZVKN,
342 RISCV_ISA_EXT_ZVBC
343 };
344
345 static const unsigned int riscv_zvkng_bundled_exts[] = {
346 RISCV_ISA_EXT_ZVKN,
347 RISCV_ISA_EXT_ZVKG
348 };
349
350 #define RISCV_ISA_EXT_ZVKS \
351 RISCV_ISA_EXT_ZVKSED, \
352 RISCV_ISA_EXT_ZVKSH, \
353 RISCV_ISA_EXT_ZVKB, \
354 RISCV_ISA_EXT_ZVKT
355
356 static const unsigned int riscv_zvks_bundled_exts[] = {
357 RISCV_ISA_EXT_ZVKS
358 };
359
360 static const unsigned int riscv_zvksc_bundled_exts[] = {
361 RISCV_ISA_EXT_ZVKS,
362 RISCV_ISA_EXT_ZVBC
363 };
364
365 static const unsigned int riscv_zvksg_bundled_exts[] = {
366 RISCV_ISA_EXT_ZVKS,
367 RISCV_ISA_EXT_ZVKG
368 };
369
370 static const unsigned int riscv_zvbb_exts[] = {
371 RISCV_ISA_EXT_ZVKB
372 };
373
374 #define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \
375 RISCV_ISA_EXT_ZVE64X, \
376 RISCV_ISA_EXT_ZVE32F, \
377 RISCV_ISA_EXT_ZVE32X
378
379 #define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \
380 RISCV_ISA_EXT_ZVE64F, \
381 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
382
383 #define RISCV_ISA_EXT_V_IMPLY_LIST \
384 RISCV_ISA_EXT_ZVE64D, \
385 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
386
387 static const unsigned int riscv_zve32f_exts[] = {
388 RISCV_ISA_EXT_ZVE32X
389 };
390
391 static const unsigned int riscv_zve64f_exts[] = {
392 RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
393 };
394
395 static const unsigned int riscv_zve64d_exts[] = {
396 RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
397 };
398
399 static const unsigned int riscv_v_exts[] = {
400 RISCV_ISA_EXT_V_IMPLY_LIST
401 };
402
403 static const unsigned int riscv_zve64x_exts[] = {
404 RISCV_ISA_EXT_ZVE32X,
405 RISCV_ISA_EXT_ZVE64X
406 };
407
408 /*
409 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
410 * privileged ISA, the existence of the CSRs is implied by any extension which
411 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
412 * existence of the CSR, and treat it as a subset of those other extensions.
413 */
414 static const unsigned int riscv_xlinuxenvcfg_exts[] = {
415 RISCV_ISA_EXT_XLINUXENVCFG
416 };
417
418 /*
419 * Zc* spec states that:
420 * - C always implies Zca
421 * - C+F implies Zcf (RV32 only)
422 * - C+D implies Zcd
423 *
424 * These extensions will be enabled and then validated depending on the
425 * availability of F/D RV32.
426 */
427 static const unsigned int riscv_c_exts[] = {
428 RISCV_ISA_EXT_ZCA,
429 RISCV_ISA_EXT_ZCF,
430 RISCV_ISA_EXT_ZCD,
431 };
432
433 /*
434 * The canonical order of ISA extension names in the ISA string is defined in
435 * chapter 27 of the unprivileged specification.
436 *
437 * Ordinarily, for in-kernel data structures, this order is unimportant but
438 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
439 *
440 * The specification uses vague wording, such as should, when it comes to
441 * ordering, so for our purposes the following rules apply:
442 *
443 * 1. All multi-letter extensions must be separated from other extensions by an
444 * underscore.
445 *
446 * 2. Additional standard extensions (starting with 'Z') must be sorted after
447 * single-letter extensions and before any higher-privileged extensions.
448 *
449 * 3. The first letter following the 'Z' conventionally indicates the most
450 * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
451 * If multiple 'Z' extensions are named, they must be ordered first by
452 * category, then alphabetically within a category.
453 *
454 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
455 * after standard unprivileged extensions. If multiple supervisor-level
456 * extensions are listed, they must be ordered alphabetically.
457 *
458 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
459 * after any lower-privileged, standard extensions. If multiple
460 * machine-level extensions are listed, they must be ordered
461 * alphabetically.
462 *
463 * 5. Non-standard extensions (starting with 'X') must be listed after all
464 * standard extensions. If multiple non-standard extensions are listed, they
465 * must be ordered alphabetically.
466 *
467 * An example string following the order is:
468 * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
469 *
470 * New entries to this struct should follow the ordering rules described above.
471 */
472 const struct riscv_isa_ext_data riscv_isa_ext[] = {
473 __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i),
474 __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m),
475 __RISCV_ISA_EXT_SUPERSET(a, RISCV_ISA_EXT_a, riscv_a_exts),
476 __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate),
477 __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate),
478 __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
479 __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
480 __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
481 __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
482 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
483 __RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
484 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
485 __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
486 __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
487 __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
488 __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
489 __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
490 __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
491 __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
492 __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
493 __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
494 __RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
495 __RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
496 __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
497 __RISCV_ISA_EXT_DATA(zalasr, RISCV_ISA_EXT_ZALASR),
498 __RISCV_ISA_EXT_DATA(zalrsc, RISCV_ISA_EXT_ZALRSC),
499 __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
500 __RISCV_ISA_EXT_DATA_VALIDATE(zfa, RISCV_ISA_EXT_ZFA, riscv_ext_f_depends),
501 __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends),
502 __RISCV_ISA_EXT_DATA_VALIDATE(zfh, RISCV_ISA_EXT_ZFH, riscv_ext_f_depends),
503 __RISCV_ISA_EXT_DATA_VALIDATE(zfhmin, RISCV_ISA_EXT_ZFHMIN, riscv_ext_f_depends),
504 __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
505 __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends),
506 __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate),
507 __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate),
508 __RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends),
509 __RISCV_ISA_EXT_DATA_VALIDATE(zclsd, RISCV_ISA_EXT_ZCLSD, riscv_ext_zclsd_validate),
510 __RISCV_ISA_EXT_DATA_VALIDATE(zilsd, RISCV_ISA_EXT_ZILSD, riscv_ext_zilsd_validate),
511 __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
512 __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
513 __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),
514 __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB),
515 __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC),
516 __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX),
517 __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
518 __RISCV_ISA_EXT_BUNDLE(zk, riscv_zk_bundled_exts),
519 __RISCV_ISA_EXT_BUNDLE(zkn, riscv_zkn_bundled_exts),
520 __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND),
521 __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE),
522 __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH),
523 __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR),
524 __RISCV_ISA_EXT_BUNDLE(zks, riscv_zks_bundled_exts),
525 __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT),
526 __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED),
527 __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH),
528 __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
529 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts, riscv_ext_vector_crypto_validate),
530 __RISCV_ISA_EXT_DATA_VALIDATE(zvbc, RISCV_ISA_EXT_ZVBC, riscv_ext_vector_crypto_validate),
531 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts, riscv_ext_vector_float_validate),
532 __RISCV_ISA_EXT_DATA_VALIDATE(zve32x, RISCV_ISA_EXT_ZVE32X, riscv_ext_vector_x_validate),
533 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts, riscv_ext_vector_float_validate),
534 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts, riscv_ext_vector_float_validate),
535 __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts, riscv_ext_vector_x_validate),
536 __RISCV_ISA_EXT_DATA_VALIDATE(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN, riscv_vector_f_validate),
537 __RISCV_ISA_EXT_DATA_VALIDATE(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA, riscv_ext_zvfbfwma_validate),
538 __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
539 __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
540 __RISCV_ISA_EXT_DATA_VALIDATE(zvkb, RISCV_ISA_EXT_ZVKB, riscv_ext_vector_crypto_validate),
541 __RISCV_ISA_EXT_DATA_VALIDATE(zvkg, RISCV_ISA_EXT_ZVKG, riscv_ext_vector_crypto_validate),
542 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkn, riscv_zvkn_bundled_exts, riscv_ext_vector_crypto_validate),
543 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvknc, riscv_zvknc_bundled_exts, riscv_ext_vector_crypto_validate),
544 __RISCV_ISA_EXT_DATA_VALIDATE(zvkned, RISCV_ISA_EXT_ZVKNED, riscv_ext_vector_crypto_validate),
545 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkng, riscv_zvkng_bundled_exts, riscv_ext_vector_crypto_validate),
546 __RISCV_ISA_EXT_DATA_VALIDATE(zvknha, RISCV_ISA_EXT_ZVKNHA, riscv_ext_vector_crypto_validate),
547 __RISCV_ISA_EXT_DATA_VALIDATE(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_ext_vector_crypto_validate),
548 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvks, riscv_zvks_bundled_exts, riscv_ext_vector_crypto_validate),
549 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksc, riscv_zvksc_bundled_exts, riscv_ext_vector_crypto_validate),
550 __RISCV_ISA_EXT_DATA_VALIDATE(zvksed, RISCV_ISA_EXT_ZVKSED, riscv_ext_vector_crypto_validate),
551 __RISCV_ISA_EXT_DATA_VALIDATE(zvksh, RISCV_ISA_EXT_ZVKSH, riscv_ext_vector_crypto_validate),
552 __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ext_vector_crypto_validate),
553 __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_crypto_validate),
554 __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
555 __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
556 __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts),
557 __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
558 __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
559 __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
560 __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
561 __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
562 __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
563 __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
564 __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
565 __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
566 __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
567 __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B),
568 __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC),
569 };
570
571 const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext);
572
riscv_isa_set_ext(const struct riscv_isa_ext_data * ext,unsigned long * bitmap)573 static void riscv_isa_set_ext(const struct riscv_isa_ext_data *ext, unsigned long *bitmap)
574 {
575 if (ext->id != RISCV_ISA_EXT_INVALID)
576 set_bit(ext->id, bitmap);
577
578 for (int i = 0; i < ext->subset_ext_size; i++) {
579 if (ext->subset_ext_ids[i] != RISCV_ISA_EXT_INVALID)
580 set_bit(ext->subset_ext_ids[i], bitmap);
581 }
582 }
583
riscv_get_isa_ext_data(unsigned int ext_id)584 static const struct riscv_isa_ext_data *riscv_get_isa_ext_data(unsigned int ext_id)
585 {
586 for (int i = 0; i < riscv_isa_ext_count; i++) {
587 if (riscv_isa_ext[i].id == ext_id)
588 return &riscv_isa_ext[i];
589 }
590
591 return NULL;
592 }
593
594 /*
595 * "Resolve" a source ISA bitmap into one that matches kernel configuration as
596 * well as correct extension dependencies. Some extensions depends on specific
597 * kernel configuration to be usable (V needs CONFIG_RISCV_ISA_V for instance)
598 * and this function will actually validate all the extensions provided in
599 * source_isa into the resolved_isa based on extensions validate() callbacks.
600 */
riscv_resolve_isa(unsigned long * source_isa,unsigned long * resolved_isa,unsigned long * this_hwcap,unsigned long * isa2hwcap)601 static void __init riscv_resolve_isa(unsigned long *source_isa,
602 unsigned long *resolved_isa, unsigned long *this_hwcap,
603 unsigned long *isa2hwcap)
604 {
605 bool loop;
606 const struct riscv_isa_ext_data *ext;
607 DECLARE_BITMAP(prev_resolved_isa, RISCV_ISA_EXT_MAX);
608 int max_loop_count = riscv_isa_ext_count, ret;
609 unsigned int bit;
610
611 do {
612 loop = false;
613 if (max_loop_count-- < 0) {
614 pr_err("Failed to reach a stable ISA state\n");
615 return;
616 }
617 bitmap_copy(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX);
618 for_each_set_bit(bit, source_isa, RISCV_ISA_EXT_MAX) {
619 ext = riscv_get_isa_ext_data(bit);
620
621 if (ext && ext->validate) {
622 ret = ext->validate(ext, resolved_isa);
623 if (ret == -EPROBE_DEFER) {
624 loop = true;
625 continue;
626 } else if (ret) {
627 /* Disable the extension entirely */
628 clear_bit(bit, source_isa);
629 continue;
630 }
631 }
632
633 set_bit(bit, resolved_isa);
634 /* No need to keep it in source isa now that it is enabled */
635 clear_bit(bit, source_isa);
636
637 /* Single letter extensions get set in hwcap */
638 if (bit < RISCV_ISA_EXT_BASE)
639 *this_hwcap |= isa2hwcap[bit];
640 }
641 } while (loop && !bitmap_equal(prev_resolved_isa, resolved_isa, RISCV_ISA_EXT_MAX));
642 }
643
match_isa_ext(const char * name,const char * name_end,unsigned long * bitmap)644 static void __init match_isa_ext(const char *name, const char *name_end, unsigned long *bitmap)
645 {
646 for (int i = 0; i < riscv_isa_ext_count; i++) {
647 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
648
649 if ((name_end - name == strlen(ext->name)) &&
650 !strncasecmp(name, ext->name, name_end - name)) {
651 riscv_isa_set_ext(ext, bitmap);
652 break;
653 }
654 }
655 }
656
riscv_parse_isa_string(const char * isa,unsigned long * bitmap)657 static void __init riscv_parse_isa_string(const char *isa, unsigned long *bitmap)
658 {
659 /*
660 * For all possible cpus, we have already validated in
661 * the boot process that they at least contain "rv" and
662 * whichever of "32"/"64" this kernel supports, and so this
663 * section can be skipped.
664 */
665 isa += 4;
666
667 while (*isa) {
668 const char *ext = isa++;
669 const char *ext_end = isa;
670 bool ext_err = false;
671
672 switch (*ext) {
673 case 'x':
674 case 'X':
675 if (acpi_disabled)
676 pr_warn_once("Vendor extensions are ignored in riscv,isa. Use riscv,isa-extensions instead.");
677 /*
678 * To skip an extension, we find its end.
679 * As multi-letter extensions must be split from other multi-letter
680 * extensions with an "_", the end of a multi-letter extension will
681 * either be the null character or the "_" at the start of the next
682 * multi-letter extension.
683 */
684 for (; *isa && *isa != '_'; ++isa)
685 ;
686 ext_err = true;
687 break;
688 case 's':
689 /*
690 * Workaround for invalid single-letter 's' & 'u' (QEMU).
691 * No need to set the bit in riscv_isa as 's' & 'u' are
692 * not valid ISA extensions. It works unless the first
693 * multi-letter extension in the ISA string begins with
694 * "Su" and is not prefixed with an underscore.
695 */
696 if (ext[-1] != '_' && ext[1] == 'u') {
697 ++isa;
698 ext_err = true;
699 break;
700 }
701 fallthrough;
702 case 'S':
703 case 'z':
704 case 'Z':
705 /*
706 * Before attempting to parse the extension itself, we find its end.
707 * As multi-letter extensions must be split from other multi-letter
708 * extensions with an "_", the end of a multi-letter extension will
709 * either be the null character or the "_" at the start of the next
710 * multi-letter extension.
711 *
712 * Next, as the extensions version is currently ignored, we
713 * eliminate that portion. This is done by parsing backwards from
714 * the end of the extension, removing any numbers. This may be a
715 * major or minor number however, so the process is repeated if a
716 * minor number was found.
717 *
718 * ext_end is intended to represent the first character *after* the
719 * name portion of an extension, but will be decremented to the last
720 * character itself while eliminating the extensions version number.
721 * A simple re-increment solves this problem.
722 */
723 for (; *isa && *isa != '_'; ++isa)
724 if (unlikely(!isalnum(*isa)))
725 ext_err = true;
726
727 ext_end = isa;
728 if (unlikely(ext_err))
729 break;
730
731 if (!isdigit(ext_end[-1]))
732 break;
733
734 while (isdigit(*--ext_end))
735 ;
736
737 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
738 ++ext_end;
739 break;
740 }
741
742 while (isdigit(*--ext_end))
743 ;
744
745 ++ext_end;
746 break;
747 default:
748 /*
749 * Things are a little easier for single-letter extensions, as they
750 * are parsed forwards.
751 *
752 * After checking that our starting position is valid, we need to
753 * ensure that, when isa was incremented at the start of the loop,
754 * that it arrived at the start of the next extension.
755 *
756 * If we are already on a non-digit, there is nothing to do. Either
757 * we have a multi-letter extension's _, or the start of an
758 * extension.
759 *
760 * Otherwise we have found the current extension's major version
761 * number. Parse past it, and a subsequent p/minor version number
762 * if present. The `p` extension must not appear immediately after
763 * a number, so there is no fear of missing it.
764 *
765 */
766 if (unlikely(!isalpha(*ext))) {
767 ext_err = true;
768 break;
769 }
770
771 if (!isdigit(*isa))
772 break;
773
774 while (isdigit(*++isa))
775 ;
776
777 if (tolower(*isa) != 'p')
778 break;
779
780 if (!isdigit(*++isa)) {
781 --isa;
782 break;
783 }
784
785 while (isdigit(*++isa))
786 ;
787
788 break;
789 }
790
791 /*
792 * The parser expects that at the start of an iteration isa points to the
793 * first character of the next extension. As we stop parsing an extension
794 * on meeting a non-alphanumeric character, an extra increment is needed
795 * where the succeeding extension is a multi-letter prefixed with an "_".
796 */
797 if (*isa == '_')
798 ++isa;
799
800 if (unlikely(ext_err))
801 continue;
802
803 match_isa_ext(ext, ext_end, bitmap);
804 }
805 }
806
riscv_fill_hwcap_from_isa_string(unsigned long * isa2hwcap)807 static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
808 {
809 struct device_node *node;
810 const char *isa;
811 int rc;
812 struct acpi_table_header *rhct;
813 acpi_status status;
814 unsigned int cpu;
815 u64 boot_vendorid;
816 u64 boot_archid;
817
818 if (!acpi_disabled) {
819 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
820 if (ACPI_FAILURE(status))
821 return;
822 }
823
824 boot_vendorid = riscv_get_mvendorid();
825 boot_archid = riscv_get_marchid();
826
827 for_each_possible_cpu(cpu) {
828 struct riscv_isainfo *isainfo = &hart_isa[cpu];
829 unsigned long this_hwcap = 0;
830 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
831
832 if (acpi_disabled) {
833 node = of_cpu_device_node_get(cpu);
834 if (!node) {
835 pr_warn("Unable to find cpu node\n");
836 continue;
837 }
838
839 rc = of_property_read_string(node, "riscv,isa", &isa);
840 of_node_put(node);
841 if (rc) {
842 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
843 continue;
844 }
845 } else {
846 rc = acpi_get_riscv_isa(rhct, cpu, &isa);
847 if (rc < 0) {
848 pr_warn("Unable to get ISA for the hart - %d\n", cpu);
849 continue;
850 }
851 }
852
853 riscv_parse_isa_string(isa, source_isa);
854
855 /*
856 * These ones were as they were part of the base ISA when the
857 * port & dt-bindings were upstreamed, and so can be set
858 * unconditionally where `i` is in riscv,isa on DT systems.
859 */
860 if (acpi_disabled) {
861 set_bit(RISCV_ISA_EXT_ZICSR, source_isa);
862 set_bit(RISCV_ISA_EXT_ZIFENCEI, source_isa);
863 set_bit(RISCV_ISA_EXT_ZICNTR, source_isa);
864 set_bit(RISCV_ISA_EXT_ZIHPM, source_isa);
865 }
866
867 /*
868 * "V" in ISA strings is ambiguous in practice: it should mean
869 * just the standard V-1.0 but vendors aren't well behaved.
870 * Many vendors with T-Head CPU cores which implement the 0.7.1
871 * version of the vector specification put "v" into their DTs.
872 * CPU cores with the ratified spec will contain non-zero
873 * marchid.
874 */
875 if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) {
876 this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v];
877 clear_bit(RISCV_ISA_EXT_v, source_isa);
878 }
879
880 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
881
882 /*
883 * All "okay" hart should have same isa. Set HWCAP based on
884 * common capabilities of every "okay" hart, in case they don't
885 * have.
886 */
887 if (elf_hwcap)
888 elf_hwcap &= this_hwcap;
889 else
890 elf_hwcap = this_hwcap;
891
892 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
893 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
894 else
895 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
896 }
897
898 if (!acpi_disabled && rhct)
899 acpi_put_table((struct acpi_table_header *)rhct);
900 }
901
riscv_fill_cpu_vendor_ext(struct device_node * cpu_node,int cpu)902 static void __init riscv_fill_cpu_vendor_ext(struct device_node *cpu_node, int cpu)
903 {
904 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
905 return;
906
907 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
908 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
909
910 for (int j = 0; j < ext_list->ext_data_count; j++) {
911 const struct riscv_isa_ext_data ext = ext_list->ext_data[j];
912 struct riscv_isavendorinfo *isavendorinfo = &ext_list->per_hart_isa_bitmap[cpu];
913
914 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
915 ext.property) < 0)
916 continue;
917
918 /*
919 * Assume that subset extensions are all members of the
920 * same vendor.
921 */
922 if (ext.subset_ext_size)
923 for (int k = 0; k < ext.subset_ext_size; k++)
924 set_bit(ext.subset_ext_ids[k], isavendorinfo->isa);
925
926 set_bit(ext.id, isavendorinfo->isa);
927 }
928 }
929 }
930
931 /*
932 * Populate all_harts_isa_bitmap for each vendor with all of the extensions that
933 * are shared across CPUs for that vendor.
934 */
riscv_fill_vendor_ext_list(int cpu)935 static void __init riscv_fill_vendor_ext_list(int cpu)
936 {
937 if (!IS_ENABLED(CONFIG_RISCV_ISA_VENDOR_EXT))
938 return;
939
940 for (int i = 0; i < riscv_isa_vendor_ext_list_size; i++) {
941 struct riscv_isa_vendor_ext_data_list *ext_list = riscv_isa_vendor_ext_list[i];
942
943 if (!ext_list->is_initialized) {
944 bitmap_copy(ext_list->all_harts_isa_bitmap.isa,
945 ext_list->per_hart_isa_bitmap[cpu].isa,
946 RISCV_ISA_VENDOR_EXT_MAX);
947 ext_list->is_initialized = true;
948 } else {
949 bitmap_and(ext_list->all_harts_isa_bitmap.isa,
950 ext_list->all_harts_isa_bitmap.isa,
951 ext_list->per_hart_isa_bitmap[cpu].isa,
952 RISCV_ISA_VENDOR_EXT_MAX);
953 }
954 }
955 }
956
has_thead_homogeneous_vlenb(void)957 static int has_thead_homogeneous_vlenb(void)
958 {
959 int cpu;
960 u32 prev_vlenb = 0;
961 u32 vlenb = 0;
962
963 /* Ignore thead,vlenb property if xtheadvector is not enabled in the kernel */
964 if (!IS_ENABLED(CONFIG_RISCV_ISA_XTHEADVECTOR))
965 return 0;
966
967 for_each_possible_cpu(cpu) {
968 struct device_node *cpu_node;
969
970 cpu_node = of_cpu_device_node_get(cpu);
971 if (!cpu_node) {
972 pr_warn("Unable to find cpu node\n");
973 return -ENOENT;
974 }
975
976 if (of_property_read_u32(cpu_node, "thead,vlenb", &vlenb)) {
977 of_node_put(cpu_node);
978
979 if (prev_vlenb)
980 return -ENOENT;
981 continue;
982 }
983
984 if (prev_vlenb && vlenb != prev_vlenb) {
985 of_node_put(cpu_node);
986 return -ENOENT;
987 }
988
989 prev_vlenb = vlenb;
990 of_node_put(cpu_node);
991 }
992
993 thead_vlenb_of = vlenb;
994 return 0;
995 }
996
riscv_fill_hwcap_from_ext_list(unsigned long * isa2hwcap)997 static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap)
998 {
999 unsigned int cpu;
1000 bool mitigated;
1001
1002 for_each_possible_cpu(cpu) {
1003 unsigned long this_hwcap = 0;
1004 struct device_node *cpu_node;
1005 struct riscv_isainfo *isainfo = &hart_isa[cpu];
1006 DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
1007
1008 cpu_node = of_cpu_device_node_get(cpu);
1009 if (!cpu_node) {
1010 pr_warn("Unable to find cpu node\n");
1011 continue;
1012 }
1013
1014 if (!of_property_present(cpu_node, "riscv,isa-extensions")) {
1015 of_node_put(cpu_node);
1016 continue;
1017 }
1018
1019 for (int i = 0; i < riscv_isa_ext_count; i++) {
1020 const struct riscv_isa_ext_data *ext = &riscv_isa_ext[i];
1021
1022 if (of_property_match_string(cpu_node, "riscv,isa-extensions",
1023 ext->property) < 0)
1024 continue;
1025
1026 riscv_isa_set_ext(ext, source_isa);
1027 }
1028
1029 riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
1030 riscv_fill_cpu_vendor_ext(cpu_node, cpu);
1031
1032 of_node_put(cpu_node);
1033
1034 /*
1035 * All "okay" harts should have same isa. Set HWCAP based on
1036 * common capabilities of every "okay" hart, in case they don't.
1037 */
1038 if (elf_hwcap)
1039 elf_hwcap &= this_hwcap;
1040 else
1041 elf_hwcap = this_hwcap;
1042
1043 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
1044 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
1045 else
1046 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
1047
1048 riscv_fill_vendor_ext_list(cpu);
1049 }
1050
1051 /*
1052 * Execute ghostwrite mitigation immediately after detecting extensions
1053 * to disable xtheadvector if necessary.
1054 */
1055 mitigated = ghostwrite_enable_mitigation();
1056
1057 if (!mitigated && has_xtheadvector_no_alternatives() && has_thead_homogeneous_vlenb() < 0) {
1058 pr_warn("Unsupported heterogeneous vlenb detected, vector extension disabled.\n");
1059 disable_xtheadvector();
1060 }
1061
1062 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
1063 return -ENOENT;
1064
1065 return 0;
1066 }
1067
1068 #ifdef CONFIG_RISCV_ISA_FALLBACK
1069 bool __initdata riscv_isa_fallback = true;
1070 #else
1071 bool __initdata riscv_isa_fallback;
riscv_isa_fallback_setup(char * __unused)1072 static int __init riscv_isa_fallback_setup(char *__unused)
1073 {
1074 riscv_isa_fallback = true;
1075 return 1;
1076 }
1077 early_param("riscv_isa_fallback", riscv_isa_fallback_setup);
1078 #endif
1079
riscv_fill_hwcap(void)1080 void __init riscv_fill_hwcap(void)
1081 {
1082 char print_str[NUM_ALPHA_EXTS + 1];
1083 unsigned long isa2hwcap[26] = {0};
1084 int i, j;
1085
1086 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
1087 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
1088 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
1089 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
1090 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
1091 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
1092 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
1093
1094 if (!acpi_disabled) {
1095 riscv_fill_hwcap_from_isa_string(isa2hwcap);
1096 } else {
1097 int ret = riscv_fill_hwcap_from_ext_list(isa2hwcap);
1098
1099 if (ret && riscv_isa_fallback) {
1100 pr_info("Falling back to deprecated \"riscv,isa\"\n");
1101 riscv_fill_hwcap_from_isa_string(isa2hwcap);
1102 }
1103 }
1104
1105 /*
1106 * We don't support systems with F but without D, so mask those out
1107 * here.
1108 */
1109 if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
1110 pr_info("This kernel does not support systems with F but not D\n");
1111 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
1112 }
1113
1114 if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X) ||
1115 has_xtheadvector_no_alternatives()) {
1116 /*
1117 * This cannot fail when called on the boot hart
1118 */
1119 riscv_v_setup_vsize();
1120 }
1121
1122 memset(print_str, 0, sizeof(print_str));
1123 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
1124 if (riscv_isa[0] & BIT_MASK(i))
1125 print_str[j++] = (char)('a' + i);
1126 pr_info("riscv: base ISA extensions %s\n", print_str);
1127
1128 memset(print_str, 0, sizeof(print_str));
1129 for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
1130 if (elf_hwcap & BIT_MASK(i))
1131 print_str[j++] = (char)('a' + i);
1132 pr_info("riscv: ELF capabilities %s\n", print_str);
1133 }
1134
riscv_get_elf_hwcap(void)1135 unsigned long riscv_get_elf_hwcap(void)
1136 {
1137 unsigned long hwcap;
1138
1139 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
1140
1141 if (!riscv_v_vstate_ctrl_user_allowed())
1142 hwcap &= ~COMPAT_HWCAP_ISA_V;
1143
1144 return hwcap;
1145 }
1146
riscv_user_isa_enable(void)1147 void __init riscv_user_isa_enable(void)
1148 {
1149 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ))
1150 current->thread.envcfg |= ENVCFG_CBZE;
1151 else if (any_cpu_has_zicboz)
1152 pr_warn("Zicboz disabled as it is unavailable on some harts\n");
1153
1154 if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM))
1155 current->thread.envcfg |= ENVCFG_CBCFE;
1156 else if (any_cpu_has_zicbom)
1157 pr_warn("Zicbom disabled as it is unavailable on some harts\n");
1158
1159 if (!riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOP) &&
1160 any_cpu_has_zicbop)
1161 pr_warn("Zicbop disabled as it is unavailable on some harts\n");
1162 }
1163
1164 #ifdef CONFIG_RISCV_ALTERNATIVE
1165 /*
1166 * Alternative patch sites consider 48 bits when determining when to patch
1167 * the old instruction sequence with the new. These bits are broken into a
1168 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
1169 * patch site is for an erratum, identified by the 32-bit patch ID. When
1170 * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
1171 * further break down patch ID into two 16-bit numbers. The lower 16 bits
1172 * are the cpufeature ID and the upper 16 bits are used for a value specific
1173 * to the cpufeature and patch site. If the upper 16 bits are zero, then it
1174 * implies no specific value is specified. cpufeatures that want to control
1175 * patching on a per-site basis will provide non-zero values and implement
1176 * checks here. The checks return true when patching should be done, and
1177 * false otherwise.
1178 */
riscv_cpufeature_patch_check(u16 id,u16 value)1179 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
1180 {
1181 if (!value)
1182 return true;
1183
1184 switch (id) {
1185 case RISCV_ISA_EXT_ZICBOZ:
1186 /*
1187 * Zicboz alternative applications provide the maximum
1188 * supported block size order, or zero when it doesn't
1189 * matter. If the current block size exceeds the maximum,
1190 * then the alternative cannot be applied.
1191 */
1192 return riscv_cboz_block_size <= (1U << value);
1193 }
1194
1195 return false;
1196 }
1197
riscv_cpufeature_patch_func(struct alt_entry * begin,struct alt_entry * end,unsigned int stage)1198 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
1199 struct alt_entry *end,
1200 unsigned int stage)
1201 {
1202 struct alt_entry *alt;
1203 void *oldptr, *altptr;
1204 u16 id, value, vendor;
1205
1206 if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
1207 return;
1208
1209 for (alt = begin; alt < end; alt++) {
1210 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
1211 vendor = PATCH_ID_CPUFEATURE_ID(alt->vendor_id);
1212
1213 /*
1214 * Any alternative with a patch_id that is less than
1215 * RISCV_ISA_EXT_MAX is interpreted as a standard extension.
1216 *
1217 * Any alternative with patch_id that is greater than or equal
1218 * to RISCV_VENDOR_EXT_ALTERNATIVES_BASE is interpreted as a
1219 * vendor extension.
1220 */
1221 if (id < RISCV_ISA_EXT_MAX) {
1222 /*
1223 * This patch should be treated as errata so skip
1224 * processing here.
1225 */
1226 if (alt->vendor_id != 0)
1227 continue;
1228
1229 if (!__riscv_isa_extension_available(NULL, id))
1230 continue;
1231
1232 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
1233 if (!riscv_cpufeature_patch_check(id, value))
1234 continue;
1235 } else if (id >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE) {
1236 if (!__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor,
1237 id - RISCV_VENDOR_EXT_ALTERNATIVES_BASE))
1238 continue;
1239 } else {
1240 WARN(1, "This extension id:%d is not in ISA extension list", id);
1241 continue;
1242 }
1243
1244 oldptr = ALT_OLD_PTR(alt);
1245 altptr = ALT_ALT_PTR(alt);
1246
1247 mutex_lock(&text_mutex);
1248 patch_text_nosync(oldptr, altptr, alt->alt_len);
1249 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
1250 mutex_unlock(&text_mutex);
1251 }
1252 }
1253 #endif
1254