1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-19, Linaro Limited
3
4 #include <linux/module.h>
5 #include <linux/of.h>
6 #include <linux/of_net.h>
7 #include <linux/platform_device.h>
8 #include <linux/phy.h>
9 #include <linux/phy/phy.h>
10
11 #include "stmmac.h"
12 #include "stmmac_platform.h"
13
14 #define RGMII_IO_MACRO_CONFIG 0x0
15 #define SDCC_HC_REG_DLL_CONFIG 0x4
16 #define SDCC_TEST_CTL 0x8
17 #define SDCC_HC_REG_DDR_CONFIG 0xC
18 #define SDCC_HC_REG_DLL_CONFIG2 0x10
19 #define SDC4_STATUS 0x14
20 #define SDCC_USR_CTL 0x18
21 #define RGMII_IO_MACRO_CONFIG2 0x1C
22 #define RGMII_IO_MACRO_DEBUG1 0x20
23 #define EMAC_SYSTEM_LOW_POWER_DEBUG 0x28
24 #define EMAC_WRAPPER_SGMII_PHY_CNTRL1 0xf4
25
26 /* RGMII_IO_MACRO_CONFIG fields */
27 #define RGMII_CONFIG_FUNC_CLK_EN BIT(30)
28 #define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23)
29 #define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)
30 #define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)
31 #define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)
32 #define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)
33 #define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)
34 #define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3)
35 #define RGMII_CONFIG_LOOPBACK_EN BIT(2)
36 #define RGMII_CONFIG_PROG_SWAP BIT(1)
37 #define RGMII_CONFIG_DDR_MODE BIT(0)
38 #define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10)
39
40 /* SDCC_HC_REG_DLL_CONFIG fields */
41 #define SDCC_DLL_CONFIG_DLL_RST BIT(30)
42 #define SDCC_DLL_CONFIG_PDN BIT(29)
43 #define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)
44 #define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)
45 #define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19)
46 #define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18)
47 #define SDCC_DLL_CONFIG_CDR_EN BIT(17)
48 #define SDCC_DLL_CONFIG_DLL_EN BIT(16)
49 #define SDCC_DLL_MCLK_GATING_EN BIT(5)
50 #define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2)
51
52 /* SDCC_HC_REG_DDR_CONFIG fields */
53 #define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31)
54 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21)
55 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27)
56 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30)
57 #define SDCC_DDR_CONFIG_TCXO_CYCLES_CNT GENMASK(11, 9)
58 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0)
59
60 /* SDCC_HC_REG_DLL_CONFIG2 fields */
61 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21)
62 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10)
63 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2)
64 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1)
65 #define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0)
66
67 /* SDC4_STATUS bits */
68 #define SDC4_STATUS_DLL_LOCK BIT(7)
69
70 /* RGMII_IO_MACRO_CONFIG2 fields */
71 #define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17)
72 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16)
73 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13)
74 #define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12)
75 #define RGMII_CONFIG2_RX_PROG_SWAP BIT(7)
76 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6)
77 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5)
78
79 /* MAC_CTRL_REG bits */
80 #define ETHQOS_MAC_CTRL_SPEED_MODE BIT(14)
81 #define ETHQOS_MAC_CTRL_PORT_SEL BIT(15)
82
83 /* EMAC_WRAPPER_SGMII_PHY_CNTRL1 bits */
84 #define SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN BIT(3)
85
86 #define SGMII_10M_RX_CLK_DVDR 0x31
87
88 struct ethqos_emac_por {
89 unsigned int offset;
90 unsigned int value;
91 };
92
93 struct ethqos_emac_driver_data {
94 const struct ethqos_emac_por *por;
95 unsigned int num_por;
96 bool rgmii_config_loopback_en;
97 bool has_emac_ge_3;
98 const char *link_clk_name;
99 bool has_integrated_pcs;
100 u32 dma_addr_width;
101 struct dwmac4_addrs dwmac4_addrs;
102 bool needs_sgmii_loopback;
103 };
104
105 struct qcom_ethqos {
106 struct platform_device *pdev;
107 void __iomem *rgmii_base;
108 void __iomem *mac_base;
109 int (*configure_func)(struct qcom_ethqos *ethqos, int speed);
110
111 unsigned int link_clk_rate;
112 struct clk *link_clk;
113 struct phy *serdes_phy;
114 int serdes_speed;
115 phy_interface_t phy_mode;
116
117 const struct ethqos_emac_por *por;
118 unsigned int num_por;
119 bool rgmii_config_loopback_en;
120 bool has_emac_ge_3;
121 bool needs_sgmii_loopback;
122 };
123
rgmii_readl(struct qcom_ethqos * ethqos,unsigned int offset)124 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
125 {
126 return readl(ethqos->rgmii_base + offset);
127 }
128
rgmii_writel(struct qcom_ethqos * ethqos,int value,unsigned int offset)129 static void rgmii_writel(struct qcom_ethqos *ethqos,
130 int value, unsigned int offset)
131 {
132 writel(value, ethqos->rgmii_base + offset);
133 }
134
rgmii_updatel(struct qcom_ethqos * ethqos,int mask,int val,unsigned int offset)135 static void rgmii_updatel(struct qcom_ethqos *ethqos,
136 int mask, int val, unsigned int offset)
137 {
138 unsigned int temp;
139
140 temp = rgmii_readl(ethqos, offset);
141 temp = (temp & ~(mask)) | val;
142 rgmii_writel(ethqos, temp, offset);
143 }
144
rgmii_dump(void * priv)145 static void rgmii_dump(void *priv)
146 {
147 struct qcom_ethqos *ethqos = priv;
148 struct device *dev = ðqos->pdev->dev;
149
150 dev_dbg(dev, "Rgmii register dump\n");
151 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %x\n",
152 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
153 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
154 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
155 dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
156 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
157 dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
158 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
159 dev_dbg(dev, "SDC4_STATUS: %x\n",
160 rgmii_readl(ethqos, SDC4_STATUS));
161 dev_dbg(dev, "SDCC_USR_CTL: %x\n",
162 rgmii_readl(ethqos, SDCC_USR_CTL));
163 dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
164 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
165 dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
166 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
167 dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
168 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
169 }
170
171 static void
ethqos_update_link_clk(struct qcom_ethqos * ethqos,int speed)172 ethqos_update_link_clk(struct qcom_ethqos *ethqos, int speed)
173 {
174 long rate;
175
176 if (!phy_interface_mode_is_rgmii(ethqos->phy_mode))
177 return;
178
179 rate = rgmii_clock(speed);
180 if (rate > 0)
181 ethqos->link_clk_rate = rate * 2;
182
183 clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
184 }
185
186 static void
qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos * ethqos,bool enable)187 qcom_ethqos_set_sgmii_loopback(struct qcom_ethqos *ethqos, bool enable)
188 {
189 if (!ethqos->needs_sgmii_loopback ||
190 ethqos->phy_mode != PHY_INTERFACE_MODE_2500BASEX)
191 return;
192
193 rgmii_updatel(ethqos,
194 SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN,
195 enable ? SGMII_PHY_CNTRL1_SGMII_TX_TO_RX_LOOPBACK_EN : 0,
196 EMAC_WRAPPER_SGMII_PHY_CNTRL1);
197 }
198
ethqos_set_func_clk_en(struct qcom_ethqos * ethqos)199 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
200 {
201 qcom_ethqos_set_sgmii_loopback(ethqos, true);
202 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
203 RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
204 }
205
206 static const struct ethqos_emac_por emac_v2_3_0_por[] = {
207 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x00C01343 },
208 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
209 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
210 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
211 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
212 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
213 };
214
215 static const struct ethqos_emac_driver_data emac_v2_3_0_data = {
216 .por = emac_v2_3_0_por,
217 .num_por = ARRAY_SIZE(emac_v2_3_0_por),
218 .rgmii_config_loopback_en = true,
219 .has_emac_ge_3 = false,
220 };
221
222 static const struct ethqos_emac_por emac_v2_1_0_por[] = {
223 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40C01343 },
224 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642C },
225 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x00000000 },
226 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
227 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
228 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
229 };
230
231 static const struct ethqos_emac_driver_data emac_v2_1_0_data = {
232 .por = emac_v2_1_0_por,
233 .num_por = ARRAY_SIZE(emac_v2_1_0_por),
234 .rgmii_config_loopback_en = false,
235 .has_emac_ge_3 = false,
236 };
237
238 static const struct ethqos_emac_por emac_v3_0_0_por[] = {
239 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
240 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
241 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
242 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
243 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
244 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
245 };
246
247 static const struct ethqos_emac_driver_data emac_v3_0_0_data = {
248 .por = emac_v3_0_0_por,
249 .num_por = ARRAY_SIZE(emac_v3_0_0_por),
250 .rgmii_config_loopback_en = false,
251 .has_emac_ge_3 = true,
252 .dwmac4_addrs = {
253 .dma_chan = 0x00008100,
254 .dma_chan_offset = 0x1000,
255 .mtl_chan = 0x00008000,
256 .mtl_chan_offset = 0x1000,
257 .mtl_ets_ctrl = 0x00008010,
258 .mtl_ets_ctrl_offset = 0x1000,
259 .mtl_txq_weight = 0x00008018,
260 .mtl_txq_weight_offset = 0x1000,
261 .mtl_send_slp_cred = 0x0000801c,
262 .mtl_send_slp_cred_offset = 0x1000,
263 .mtl_high_cred = 0x00008020,
264 .mtl_high_cred_offset = 0x1000,
265 .mtl_low_cred = 0x00008024,
266 .mtl_low_cred_offset = 0x1000,
267 },
268 };
269
270 static const struct ethqos_emac_por emac_v4_0_0_por[] = {
271 { .offset = RGMII_IO_MACRO_CONFIG, .value = 0x40c01343 },
272 { .offset = SDCC_HC_REG_DLL_CONFIG, .value = 0x2004642c },
273 { .offset = SDCC_HC_REG_DDR_CONFIG, .value = 0x80040800 },
274 { .offset = SDCC_HC_REG_DLL_CONFIG2, .value = 0x00200000 },
275 { .offset = SDCC_USR_CTL, .value = 0x00010800 },
276 { .offset = RGMII_IO_MACRO_CONFIG2, .value = 0x00002060 },
277 };
278
279 static const struct ethqos_emac_driver_data emac_v4_0_0_data = {
280 .por = emac_v4_0_0_por,
281 .num_por = ARRAY_SIZE(emac_v4_0_0_por),
282 .rgmii_config_loopback_en = false,
283 .has_emac_ge_3 = true,
284 .link_clk_name = "phyaux",
285 .has_integrated_pcs = true,
286 .needs_sgmii_loopback = true,
287 .dma_addr_width = 36,
288 .dwmac4_addrs = {
289 .dma_chan = 0x00008100,
290 .dma_chan_offset = 0x1000,
291 .mtl_chan = 0x00008000,
292 .mtl_chan_offset = 0x1000,
293 .mtl_ets_ctrl = 0x00008010,
294 .mtl_ets_ctrl_offset = 0x1000,
295 .mtl_txq_weight = 0x00008018,
296 .mtl_txq_weight_offset = 0x1000,
297 .mtl_send_slp_cred = 0x0000801c,
298 .mtl_send_slp_cred_offset = 0x1000,
299 .mtl_high_cred = 0x00008020,
300 .mtl_high_cred_offset = 0x1000,
301 .mtl_low_cred = 0x00008024,
302 .mtl_low_cred_offset = 0x1000,
303 },
304 };
305
ethqos_dll_configure(struct qcom_ethqos * ethqos)306 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
307 {
308 struct device *dev = ðqos->pdev->dev;
309 unsigned int val;
310 int retry = 1000;
311
312 /* Set CDR_EN */
313 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
314 SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
315
316 /* Set CDR_EXT_EN */
317 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
318 SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
319
320 /* Clear CK_OUT_EN */
321 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
322 0, SDCC_HC_REG_DLL_CONFIG);
323
324 /* Set DLL_EN */
325 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
326 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
327
328 if (!ethqos->has_emac_ge_3) {
329 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
330 0, SDCC_HC_REG_DLL_CONFIG);
331
332 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
333 0, SDCC_HC_REG_DLL_CONFIG);
334 }
335
336 /* Wait for CK_OUT_EN clear */
337 do {
338 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
339 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
340 if (!val)
341 break;
342 mdelay(1);
343 retry--;
344 } while (retry > 0);
345 if (!retry)
346 dev_err(dev, "Clear CK_OUT_EN timedout\n");
347
348 /* Set CK_OUT_EN */
349 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
350 SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
351
352 /* Wait for CK_OUT_EN set */
353 retry = 1000;
354 do {
355 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
356 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
357 if (val)
358 break;
359 mdelay(1);
360 retry--;
361 } while (retry > 0);
362 if (!retry)
363 dev_err(dev, "Set CK_OUT_EN timedout\n");
364
365 /* Set DDR_CAL_EN */
366 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
367 SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
368
369 if (!ethqos->has_emac_ge_3) {
370 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
371 0, SDCC_HC_REG_DLL_CONFIG2);
372
373 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
374 0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
375
376 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
377 BIT(2), SDCC_HC_REG_DLL_CONFIG2);
378
379 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
380 SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
381 SDCC_HC_REG_DLL_CONFIG2);
382 }
383
384 return 0;
385 }
386
ethqos_rgmii_macro_init(struct qcom_ethqos * ethqos,int speed)387 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
388 {
389 struct device *dev = ðqos->pdev->dev;
390 int phase_shift;
391 int loopback;
392
393 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */
394 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID ||
395 ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_TXID)
396 phase_shift = 0;
397 else
398 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN;
399
400 /* Disable loopback mode */
401 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
402 0, RGMII_IO_MACRO_CONFIG2);
403
404 /* Determine if this platform wants loopback enabled after programming */
405 if (ethqos->rgmii_config_loopback_en)
406 loopback = RGMII_CONFIG_LOOPBACK_EN;
407 else
408 loopback = 0;
409
410 /* Select RGMII, write 0 to interface select */
411 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
412 0, RGMII_IO_MACRO_CONFIG);
413
414 switch (speed) {
415 case SPEED_1000:
416 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
417 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
418 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
419 0, RGMII_IO_MACRO_CONFIG);
420 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
421 RGMII_CONFIG_POS_NEG_DATA_SEL,
422 RGMII_IO_MACRO_CONFIG);
423 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
424 RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
425 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
426 0, RGMII_IO_MACRO_CONFIG2);
427
428 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
429 phase_shift, RGMII_IO_MACRO_CONFIG2);
430 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
431 0, RGMII_IO_MACRO_CONFIG2);
432 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
433 RGMII_CONFIG2_RX_PROG_SWAP,
434 RGMII_IO_MACRO_CONFIG2);
435
436 /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
437 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
438 */
439 if (ethqos->has_emac_ge_3) {
440 /* 0.9 ns */
441 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
442 115, SDCC_HC_REG_DDR_CONFIG);
443 } else {
444 /* 1.8 ns */
445 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
446 57, SDCC_HC_REG_DDR_CONFIG);
447 }
448 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
449 SDCC_DDR_CONFIG_PRG_DLY_EN,
450 SDCC_HC_REG_DDR_CONFIG);
451 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
452 loopback, RGMII_IO_MACRO_CONFIG);
453 break;
454
455 case SPEED_100:
456 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
457 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
458 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
459 RGMII_CONFIG_BYPASS_TX_ID_EN,
460 RGMII_IO_MACRO_CONFIG);
461 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
462 0, RGMII_IO_MACRO_CONFIG);
463 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
464 0, RGMII_IO_MACRO_CONFIG);
465 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
466 0, RGMII_IO_MACRO_CONFIG2);
467 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
468 phase_shift, RGMII_IO_MACRO_CONFIG2);
469 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
470 BIT(6), RGMII_IO_MACRO_CONFIG);
471 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
472 0, RGMII_IO_MACRO_CONFIG2);
473
474 if (ethqos->has_emac_ge_3)
475 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
476 RGMII_CONFIG2_RX_PROG_SWAP,
477 RGMII_IO_MACRO_CONFIG2);
478 else
479 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
480 0, RGMII_IO_MACRO_CONFIG2);
481
482 /* Write 0x5 to PRG_RCLK_DLY_CODE */
483 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
484 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
485 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
486 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
487 SDCC_HC_REG_DDR_CONFIG);
488 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
489 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
490 SDCC_HC_REG_DDR_CONFIG);
491 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
492 loopback, RGMII_IO_MACRO_CONFIG);
493 break;
494
495 case SPEED_10:
496 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
497 RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
498 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
499 RGMII_CONFIG_BYPASS_TX_ID_EN,
500 RGMII_IO_MACRO_CONFIG);
501 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
502 0, RGMII_IO_MACRO_CONFIG);
503 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
504 0, RGMII_IO_MACRO_CONFIG);
505 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
506 0, RGMII_IO_MACRO_CONFIG2);
507 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
508 phase_shift, RGMII_IO_MACRO_CONFIG2);
509 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
510 BIT(12) | GENMASK(9, 8),
511 RGMII_IO_MACRO_CONFIG);
512 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
513 0, RGMII_IO_MACRO_CONFIG2);
514 if (ethqos->has_emac_ge_3)
515 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
516 RGMII_CONFIG2_RX_PROG_SWAP,
517 RGMII_IO_MACRO_CONFIG2);
518 else
519 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
520 0, RGMII_IO_MACRO_CONFIG2);
521 /* Write 0x5 to PRG_RCLK_DLY_CODE */
522 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
523 (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
524 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
525 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
526 SDCC_HC_REG_DDR_CONFIG);
527 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
528 SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
529 SDCC_HC_REG_DDR_CONFIG);
530 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
531 loopback, RGMII_IO_MACRO_CONFIG);
532 break;
533 default:
534 dev_err(dev, "Invalid speed %d\n", speed);
535 return -EINVAL;
536 }
537
538 return 0;
539 }
540
ethqos_configure_rgmii(struct qcom_ethqos * ethqos,int speed)541 static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed)
542 {
543 struct device *dev = ðqos->pdev->dev;
544 volatile unsigned int dll_lock;
545 unsigned int i, retry = 1000;
546
547 /* Reset to POR values and enable clk */
548 for (i = 0; i < ethqos->num_por; i++)
549 rgmii_writel(ethqos, ethqos->por[i].value,
550 ethqos->por[i].offset);
551 ethqos_set_func_clk_en(ethqos);
552
553 /* Initialize the DLL first */
554
555 /* Set DLL_RST */
556 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
557 SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
558
559 /* Set PDN */
560 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
561 SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
562
563 if (ethqos->has_emac_ge_3) {
564 if (speed == SPEED_1000) {
565 rgmii_writel(ethqos, 0x1800000, SDCC_TEST_CTL);
566 rgmii_writel(ethqos, 0x2C010800, SDCC_USR_CTL);
567 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
568 } else {
569 rgmii_writel(ethqos, 0x40010800, SDCC_USR_CTL);
570 rgmii_writel(ethqos, 0xA001, SDCC_HC_REG_DLL_CONFIG2);
571 }
572 }
573
574 /* Clear DLL_RST */
575 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
576 SDCC_HC_REG_DLL_CONFIG);
577
578 /* Clear PDN */
579 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
580 SDCC_HC_REG_DLL_CONFIG);
581
582 if (speed != SPEED_100 && speed != SPEED_10) {
583 /* Set DLL_EN */
584 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
585 SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
586
587 /* Set CK_OUT_EN */
588 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
589 SDCC_DLL_CONFIG_CK_OUT_EN,
590 SDCC_HC_REG_DLL_CONFIG);
591
592 /* Set USR_CTL bit 26 with mask of 3 bits */
593 if (!ethqos->has_emac_ge_3)
594 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26),
595 SDCC_USR_CTL);
596
597 /* wait for DLL LOCK */
598 do {
599 mdelay(1);
600 dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
601 if (dll_lock & SDC4_STATUS_DLL_LOCK)
602 break;
603 retry--;
604 } while (retry > 0);
605 if (!retry)
606 dev_err(dev, "Timeout while waiting for DLL lock\n");
607 }
608
609 if (speed == SPEED_1000)
610 ethqos_dll_configure(ethqos);
611
612 ethqos_rgmii_macro_init(ethqos, speed);
613
614 return 0;
615 }
616
ethqos_set_serdes_speed(struct qcom_ethqos * ethqos,int speed)617 static void ethqos_set_serdes_speed(struct qcom_ethqos *ethqos, int speed)
618 {
619 if (ethqos->serdes_speed != speed) {
620 phy_set_speed(ethqos->serdes_phy, speed);
621 ethqos->serdes_speed = speed;
622 }
623 }
624
ethqos_pcs_set_inband(struct stmmac_priv * priv,bool enable)625 static void ethqos_pcs_set_inband(struct stmmac_priv *priv, bool enable)
626 {
627 stmmac_pcs_ctrl_ane(priv, enable, 0, 0);
628 }
629
630 /* On interface toggle MAC registers gets reset.
631 * Configure MAC block for SGMII on ethernet phy link up
632 */
ethqos_configure_sgmii(struct qcom_ethqos * ethqos,int speed)633 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos, int speed)
634 {
635 struct net_device *dev = platform_get_drvdata(ethqos->pdev);
636 struct stmmac_priv *priv = netdev_priv(dev);
637 int val;
638
639 val = readl(ethqos->mac_base + MAC_CTRL_REG);
640
641 switch (speed) {
642 case SPEED_2500:
643 val &= ~ETHQOS_MAC_CTRL_PORT_SEL;
644 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
645 RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
646 RGMII_IO_MACRO_CONFIG2);
647 ethqos_set_serdes_speed(ethqos, SPEED_2500);
648 ethqos_pcs_set_inband(priv, false);
649 break;
650 case SPEED_1000:
651 val &= ~ETHQOS_MAC_CTRL_PORT_SEL;
652 rgmii_updatel(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
653 RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
654 RGMII_IO_MACRO_CONFIG2);
655 ethqos_set_serdes_speed(ethqos, SPEED_1000);
656 ethqos_pcs_set_inband(priv, true);
657 break;
658 case SPEED_100:
659 val |= ETHQOS_MAC_CTRL_PORT_SEL | ETHQOS_MAC_CTRL_SPEED_MODE;
660 ethqos_set_serdes_speed(ethqos, SPEED_1000);
661 ethqos_pcs_set_inband(priv, true);
662 break;
663 case SPEED_10:
664 val |= ETHQOS_MAC_CTRL_PORT_SEL;
665 val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
666 rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
667 FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR,
668 SGMII_10M_RX_CLK_DVDR),
669 RGMII_IO_MACRO_CONFIG);
670 ethqos_set_serdes_speed(ethqos, SPEED_1000);
671 ethqos_pcs_set_inband(priv, true);
672 break;
673 }
674
675 writel(val, ethqos->mac_base + MAC_CTRL_REG);
676
677 return val;
678 }
679
ethqos_configure(struct qcom_ethqos * ethqos,int speed)680 static int ethqos_configure(struct qcom_ethqos *ethqos, int speed)
681 {
682 return ethqos->configure_func(ethqos, speed);
683 }
684
ethqos_fix_mac_speed(void * priv,int speed,unsigned int mode)685 static void ethqos_fix_mac_speed(void *priv, int speed, unsigned int mode)
686 {
687 struct qcom_ethqos *ethqos = priv;
688
689 qcom_ethqos_set_sgmii_loopback(ethqos, false);
690 ethqos_update_link_clk(ethqos, speed);
691 ethqos_configure(ethqos, speed);
692 }
693
qcom_ethqos_serdes_powerup(struct net_device * ndev,void * priv)694 static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv)
695 {
696 struct qcom_ethqos *ethqos = priv;
697 int ret;
698
699 ret = phy_init(ethqos->serdes_phy);
700 if (ret)
701 return ret;
702
703 ret = phy_power_on(ethqos->serdes_phy);
704 if (ret)
705 return ret;
706
707 return phy_set_speed(ethqos->serdes_phy, ethqos->serdes_speed);
708 }
709
qcom_ethqos_serdes_powerdown(struct net_device * ndev,void * priv)710 static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv)
711 {
712 struct qcom_ethqos *ethqos = priv;
713
714 phy_power_off(ethqos->serdes_phy);
715 phy_exit(ethqos->serdes_phy);
716 }
717
ethqos_clks_config(void * priv,bool enabled)718 static int ethqos_clks_config(void *priv, bool enabled)
719 {
720 struct qcom_ethqos *ethqos = priv;
721 int ret = 0;
722
723 if (enabled) {
724 ret = clk_prepare_enable(ethqos->link_clk);
725 if (ret) {
726 dev_err(ðqos->pdev->dev, "link_clk enable failed\n");
727 return ret;
728 }
729
730 /* Enable functional clock to prevent DMA reset to timeout due
731 * to lacking PHY clock after the hardware block has been power
732 * cycled. The actual configuration will be adjusted once
733 * ethqos_fix_mac_speed() is invoked.
734 */
735 ethqos_set_func_clk_en(ethqos);
736 } else {
737 clk_disable_unprepare(ethqos->link_clk);
738 }
739
740 return ret;
741 }
742
ethqos_clks_disable(void * data)743 static void ethqos_clks_disable(void *data)
744 {
745 ethqos_clks_config(data, false);
746 }
747
ethqos_ptp_clk_freq_config(struct stmmac_priv * priv)748 static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv)
749 {
750 struct plat_stmmacenet_data *plat_dat = priv->plat;
751 int err;
752
753 if (!plat_dat->clk_ptp_ref)
754 return;
755
756 /* Max the PTP ref clock out to get the best resolution possible */
757 err = clk_set_rate(plat_dat->clk_ptp_ref, ULONG_MAX);
758 if (err)
759 netdev_err(priv->dev, "Failed to max out clk_ptp_ref: %d\n", err);
760 plat_dat->clk_ptp_rate = clk_get_rate(plat_dat->clk_ptp_ref);
761
762 netdev_dbg(priv->dev, "PTP rate %lu\n", plat_dat->clk_ptp_rate);
763 }
764
qcom_ethqos_probe(struct platform_device * pdev)765 static int qcom_ethqos_probe(struct platform_device *pdev)
766 {
767 struct device_node *np = pdev->dev.of_node;
768 const struct ethqos_emac_driver_data *data;
769 struct plat_stmmacenet_data *plat_dat;
770 struct stmmac_resources stmmac_res;
771 struct device *dev = &pdev->dev;
772 struct qcom_ethqos *ethqos;
773 int ret, i;
774
775 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
776 if (ret)
777 return dev_err_probe(dev, ret,
778 "Failed to get platform resources\n");
779
780 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
781 if (IS_ERR(plat_dat)) {
782 return dev_err_probe(dev, PTR_ERR(plat_dat),
783 "dt configuration failed\n");
784 }
785
786 plat_dat->clks_config = ethqos_clks_config;
787
788 ethqos = devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL);
789 if (!ethqos)
790 return -ENOMEM;
791
792 ethqos->phy_mode = plat_dat->phy_interface;
793 switch (ethqos->phy_mode) {
794 case PHY_INTERFACE_MODE_RGMII:
795 case PHY_INTERFACE_MODE_RGMII_ID:
796 case PHY_INTERFACE_MODE_RGMII_RXID:
797 case PHY_INTERFACE_MODE_RGMII_TXID:
798 ethqos->configure_func = ethqos_configure_rgmii;
799 break;
800 case PHY_INTERFACE_MODE_2500BASEX:
801 case PHY_INTERFACE_MODE_SGMII:
802 ethqos->configure_func = ethqos_configure_sgmii;
803 break;
804 default:
805 dev_err(dev, "Unsupported phy mode %s\n",
806 phy_modes(ethqos->phy_mode));
807 return -EINVAL;
808 }
809
810 ethqos->pdev = pdev;
811 ethqos->rgmii_base = devm_platform_ioremap_resource_byname(pdev, "rgmii");
812 if (IS_ERR(ethqos->rgmii_base))
813 return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base),
814 "Failed to map rgmii resource\n");
815
816 ethqos->mac_base = stmmac_res.addr;
817
818 data = of_device_get_match_data(dev);
819 ethqos->por = data->por;
820 ethqos->num_por = data->num_por;
821 ethqos->rgmii_config_loopback_en = data->rgmii_config_loopback_en;
822 ethqos->has_emac_ge_3 = data->has_emac_ge_3;
823 ethqos->needs_sgmii_loopback = data->needs_sgmii_loopback;
824
825 ethqos->link_clk = devm_clk_get(dev, data->link_clk_name ?: "rgmii");
826 if (IS_ERR(ethqos->link_clk))
827 return dev_err_probe(dev, PTR_ERR(ethqos->link_clk),
828 "Failed to get link_clk\n");
829
830 ret = ethqos_clks_config(ethqos, true);
831 if (ret)
832 return ret;
833
834 ret = devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos);
835 if (ret)
836 return ret;
837
838 ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
839 if (IS_ERR(ethqos->serdes_phy))
840 return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy),
841 "Failed to get serdes phy\n");
842
843 ethqos->serdes_speed = SPEED_1000;
844 ethqos_update_link_clk(ethqos, SPEED_1000);
845 ethqos_set_func_clk_en(ethqos);
846
847 plat_dat->bsp_priv = ethqos;
848 plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
849 plat_dat->dump_debug_regs = rgmii_dump;
850 plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
851 plat_dat->has_gmac4 = 1;
852 if (ethqos->has_emac_ge_3)
853 plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
854 plat_dat->pmt = 1;
855 if (of_property_read_bool(np, "snps,tso"))
856 plat_dat->flags |= STMMAC_FLAG_TSO_EN;
857 if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
858 plat_dat->flags |= STMMAC_FLAG_RX_CLK_RUNS_IN_LPI;
859 if (data->has_integrated_pcs)
860 plat_dat->flags |= STMMAC_FLAG_HAS_INTEGRATED_PCS;
861 if (data->dma_addr_width)
862 plat_dat->host_dma_width = data->dma_addr_width;
863
864 if (ethqos->serdes_phy) {
865 plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
866 plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown;
867 }
868
869 /* Enable TSO on queue0 and enable TBS on rest of the queues */
870 for (i = 1; i < plat_dat->tx_queues_to_use; i++)
871 plat_dat->tx_queues_cfg[i].tbs_en = 1;
872
873 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
874 }
875
876 static const struct of_device_id qcom_ethqos_match[] = {
877 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
878 { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data},
879 { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data},
880 { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data},
881 { }
882 };
883 MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
884
885 static struct platform_driver qcom_ethqos_driver = {
886 .probe = qcom_ethqos_probe,
887 .driver = {
888 .name = "qcom-ethqos",
889 .pm = &stmmac_pltfr_pm_ops,
890 .of_match_table = qcom_ethqos_match,
891 },
892 };
893 module_platform_driver(qcom_ethqos_driver);
894
895 MODULE_DESCRIPTION("Qualcomm ETHQOS driver");
896 MODULE_LICENSE("GPL v2");
897