1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_FW_H__
6 #define __RTW89_FW_H__
7
8 #include "core.h"
9
10 enum rtw89_fw_dl_status {
11 RTW89_FWDL_INITIAL_STATE = 0,
12 RTW89_FWDL_FWDL_ONGOING = 1,
13 RTW89_FWDL_CHECKSUM_FAIL = 2,
14 RTW89_FWDL_SECURITY_FAIL = 3,
15 RTW89_FWDL_CV_NOT_MATCH = 4,
16 RTW89_FWDL_RSVD0 = 5,
17 RTW89_FWDL_WCPU_FWDL_RDY = 6,
18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7
19 };
20
21 struct rtw89_c2hreg_hdr {
22 u32 w0;
23 };
24
25 #define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
27 #define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)
28 #define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)
29
30 struct rtw89_c2hreg_phycap {
31 u32 w0;
32 u32 w1;
33 u32 w2;
34 u32 w3;
35 } __packed;
36
37 #define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
39 #define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)
40 #define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)
41 #define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
43 #define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)
44 #define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)
45 #define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
47 #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)
48 #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)
49 #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)
50 #define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)
51
52 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)
53 #define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)
54 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)
55 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)
56 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)
57 #define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)
58 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)
59 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1
60 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2
61 #define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3
62 #define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)
63
64 #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)
65 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)
66 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)
67 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)
68 #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)
69 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)
70 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)
71 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)
72 #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)
73 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)
74 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)
75 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)
76 #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)
77 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)
78 #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)
79 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)
80 #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)
81 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)
82 #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)
83 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)
84 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)
85 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)
86 #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)
87 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)
88 #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)
89
90 #define RTW89_C2HREG_PS_LEAVE_ACK_RET GENMASK(7, 0)
91 #define RTW89_C2HREG_PS_LEAVE_ACK_MACID GENMASK(31, 16)
92
93 struct rtw89_h2creg_hdr {
94 u32 w0;
95 };
96
97 #define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)
98 #define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)
99
100 struct rtw89_h2creg_sch_tx_en {
101 u32 w0;
102 u32 w1;
103 } __packed;
104
105 #define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)
106 #define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)
107 #define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)
108
109 #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)
110
111 #define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)
112
113 #define RTW89_H2CREG_MAX 4
114 #define RTW89_C2HREG_MAX 4
115 #define RTW89_C2HREG_HDR_LEN 2
116 #define RTW89_H2CREG_HDR_LEN 2
117 #define RTW89_C2H_TIMEOUT 1000000
118 #define RTW89_C2H_TIMEOUT_USB 4000
119
120 struct rtw89_mac_c2h_info {
121 u8 id;
122 u8 content_len;
123 union {
124 u32 c2hreg[RTW89_C2HREG_MAX];
125 struct rtw89_c2hreg_hdr hdr;
126 struct rtw89_c2hreg_phycap phycap;
127 } u;
128 };
129
130 struct rtw89_mac_h2c_info {
131 u8 id;
132 u8 content_len;
133 union {
134 u32 h2creg[RTW89_H2CREG_MAX];
135 struct rtw89_h2creg_hdr hdr;
136 struct rtw89_h2creg_sch_tx_en sch_tx_en;
137 } u;
138 };
139
140 enum rtw89_mac_h2c_type {
141 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,
142 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,
143 RTW89_FWCMD_H2CREG_FUNC_FWERR,
144 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,
145 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,
146 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN,
147 RTW89_FWCMD_H2CREG_FUNC_WOW_TRX_STOP,
148 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_1,
149 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_2,
150 RTW89_FWCMD_H2CREG_FUNC_AOAC_RPT_3_REQ,
151 RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL,
152 };
153
154 enum rtw89_mac_c2h_type {
155 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,
156 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,
157 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,
158 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,
159 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,
160 RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK = 0xA,
161 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1 = 0xC,
162 RTW89_FWCMD_C2HREG_FUNC_PS_LEAVE_ACK = 0xD,
163 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF,
164 };
165
166 enum rtw89_fw_c2h_category {
167 RTW89_C2H_CAT_TEST,
168 RTW89_C2H_CAT_MAC,
169 RTW89_C2H_CAT_OUTSRC,
170 };
171
172 enum rtw89_fw_log_level {
173 RTW89_FW_LOG_LEVEL_OFF,
174 RTW89_FW_LOG_LEVEL_CRT,
175 RTW89_FW_LOG_LEVEL_SER,
176 RTW89_FW_LOG_LEVEL_WARN,
177 RTW89_FW_LOG_LEVEL_LOUD,
178 RTW89_FW_LOG_LEVEL_TR,
179 };
180
181 enum rtw89_fw_log_path {
182 RTW89_FW_LOG_LEVEL_UART,
183 RTW89_FW_LOG_LEVEL_C2H,
184 RTW89_FW_LOG_LEVEL_SNI,
185 };
186
187 enum rtw89_fw_log_comp {
188 RTW89_FW_LOG_COMP_VER,
189 RTW89_FW_LOG_COMP_INIT,
190 RTW89_FW_LOG_COMP_TASK,
191 RTW89_FW_LOG_COMP_CNS,
192 RTW89_FW_LOG_COMP_H2C,
193 RTW89_FW_LOG_COMP_C2H,
194 RTW89_FW_LOG_COMP_TX,
195 RTW89_FW_LOG_COMP_RX,
196 RTW89_FW_LOG_COMP_IPSEC,
197 RTW89_FW_LOG_COMP_TIMER,
198 RTW89_FW_LOG_COMP_DBGPKT,
199 RTW89_FW_LOG_COMP_PS,
200 RTW89_FW_LOG_COMP_ERROR,
201 RTW89_FW_LOG_COMP_WOWLAN,
202 RTW89_FW_LOG_COMP_SECURE_BOOT,
203 RTW89_FW_LOG_COMP_BTC,
204 RTW89_FW_LOG_COMP_BB,
205 RTW89_FW_LOG_COMP_TWT,
206 RTW89_FW_LOG_COMP_RF,
207 RTW89_FW_LOG_COMP_MCC = 20,
208 RTW89_FW_LOG_COMP_MLO = 26,
209 RTW89_FW_LOG_COMP_SCAN = 28,
210 };
211
212 enum rtw89_pkt_offload_op {
213 RTW89_PKT_OFLD_OP_ADD,
214 RTW89_PKT_OFLD_OP_DEL,
215 RTW89_PKT_OFLD_OP_READ,
216
217 NUM_OF_RTW89_PKT_OFFLOAD_OP,
218 };
219
220 #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \
221 ((pkt_id) * NUM_OF_RTW89_PKT_OFFLOAD_OP + (pkt_op))
222
223 enum rtw89_scanofld_notify_reason {
224 RTW89_SCAN_DWELL_NOTIFY,
225 RTW89_SCAN_PRE_TX_NOTIFY,
226 RTW89_SCAN_POST_TX_NOTIFY,
227 RTW89_SCAN_ENTER_CH_NOTIFY,
228 RTW89_SCAN_LEAVE_CH_NOTIFY,
229 RTW89_SCAN_END_SCAN_NOTIFY,
230 RTW89_SCAN_REPORT_NOTIFY,
231 RTW89_SCAN_CHKPT_NOTIFY,
232 RTW89_SCAN_ENTER_OP_NOTIFY,
233 RTW89_SCAN_LEAVE_OP_NOTIFY,
234 };
235
236 enum rtw89_scanofld_status {
237 RTW89_SCAN_STATUS_NOTIFY,
238 RTW89_SCAN_STATUS_SUCCESS,
239 RTW89_SCAN_STATUS_FAIL,
240 };
241
242 enum rtw89_chan_type {
243 RTW89_CHAN_OPERATE = 0,
244 RTW89_CHAN_ACTIVE,
245 RTW89_CHAN_DFS,
246 RTW89_CHAN_EXTRA_OP,
247 };
248
249 enum rtw89_p2pps_action {
250 RTW89_P2P_ACT_INIT = 0,
251 RTW89_P2P_ACT_UPDATE = 1,
252 RTW89_P2P_ACT_REMOVE = 2,
253 RTW89_P2P_ACT_TERMINATE = 3,
254 };
255
256 #define RTW89_DEFAULT_CQM_HYST 4
257 #define RTW89_DEFAULT_CQM_THOLD -70
258
259 enum rtw89_bcn_fltr_offload_mode {
260 RTW89_BCN_FLTR_OFFLOAD_MODE_0 = 0,
261 RTW89_BCN_FLTR_OFFLOAD_MODE_1,
262 RTW89_BCN_FLTR_OFFLOAD_MODE_2,
263 RTW89_BCN_FLTR_OFFLOAD_MODE_3,
264
265 RTW89_BCN_FLTR_OFFLOAD_MODE_DEFAULT = RTW89_BCN_FLTR_OFFLOAD_MODE_0,
266 };
267
268 enum rtw89_bcn_fltr_type {
269 RTW89_BCN_FLTR_BEACON_LOSS,
270 RTW89_BCN_FLTR_RSSI,
271 RTW89_BCN_FLTR_NOTIFY,
272 };
273
274 enum rtw89_bcn_fltr_rssi_event {
275 RTW89_BCN_FLTR_RSSI_NOT_CHANGED,
276 RTW89_BCN_FLTR_RSSI_HIGH,
277 RTW89_BCN_FLTR_RSSI_LOW,
278 };
279
280 #define FWDL_SECTION_MAX_NUM 10
281 #define FWDL_SECTION_CHKSUM_LEN 8
282 #define FWDL_SECTION_PER_PKT_LEN 2020
283
284 struct rtw89_fw_hdr_section_info {
285 u8 redl;
286 const u8 *addr;
287 u32 len;
288 u32 len_override;
289 u32 dladdr;
290 u32 mssc;
291 u8 type;
292 bool ignore;
293 const u8 *key_addr;
294 u32 key_len;
295 u32 key_idx;
296 };
297
298 struct rtw89_fw_bin_info {
299 u8 section_num;
300 u32 hdr_len;
301 bool dynamic_hdr_en;
302 u32 dynamic_hdr_len;
303 u8 idmem_share_mode;
304 bool dsp_checksum;
305 bool secure_section_exist;
306 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];
307 };
308
309 struct rtw89_fw_macid_pause_grp {
310 __le32 pause_grp[4];
311 __le32 mask_grp[4];
312 } __packed;
313
314 struct rtw89_fw_macid_pause_sleep_grp {
315 struct {
316 __le32 pause_grp[4];
317 __le32 pause_mask_grp[4];
318 __le32 sleep_grp[4];
319 __le32 sleep_mask_grp[4];
320 } __packed n[4];
321 } __packed;
322
323 #define RTW89_H2C_MAX_SIZE 2048
324 #define RTW89_CHANNEL_TIME 45
325 #define RTW89_CHANNEL_TIME_6G 20
326 #define RTW89_CHANNEL_TIME_EXTRA_OP 30
327 #define RTW89_DFS_CHAN_TIME 105
328 #define RTW89_OFF_CHAN_TIME 100
329 #define RTW89_P2P_CHAN_TIME 105
330 #define RTW89_DWELL_TIME 20
331 #define RTW89_DWELL_TIME_6G 10
332 #define RTW89_SCAN_WIDTH 0
333 #define RTW89_SCANOFLD_MAX_SSID 8
334 #define RTW89_SCANOFLD_MAX_IE_LEN 512
335 #define RTW89_SCANOFLD_PKT_NONE 0xFF
336 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F
337 #define RTW89_CHAN_INVALID 0xFF
338 #define RTW89_MAC_CHINFO_SIZE 28
339 #define RTW89_MAC_CHINFO_SIZE_BE 32
340 #define RTW89_SCAN_LIST_GUARD 4
341 #define RTW89_SCAN_LIST_LIMIT(size) \
342 ((RTW89_H2C_MAX_SIZE / (size)) - RTW89_SCAN_LIST_GUARD)
343 #define RTW89_SCAN_LIST_LIMIT_AX RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE)
344 #define RTW89_SCAN_LIST_LIMIT_BE RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE_BE)
345
346 #define RTW89_BCN_LOSS_CNT 60
347
348 struct rtw89_mac_chinfo_ax {
349 u8 period;
350 u8 dwell_time;
351 u8 central_ch;
352 u8 pri_ch;
353 u8 bw:3;
354 u8 notify_action:5;
355 u8 num_pkt:4;
356 u8 tx_pkt:1;
357 u8 pause_data:1;
358 u8 ch_band:2;
359 u8 probe_id;
360 u8 dfs_ch:1;
361 u8 tx_null:1;
362 u8 rand_seq_num:1;
363 u8 cfg_tx_pwr:1;
364 u8 macid_tx: 1;
365 u8 rsvd0: 3;
366 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
367 u16 tx_pwr_idx;
368 u8 rsvd1;
369 struct list_head list;
370 bool is_psc;
371 };
372
373 struct rtw89_mac_chinfo_be {
374 u8 period;
375 u8 dwell_time;
376 u8 central_ch;
377 u8 pri_ch;
378 u8 bw:3;
379 u8 ch_band:2;
380 u8 dfs_ch:1;
381 u8 pause_data:1;
382 u8 tx_null:1;
383 u8 rand_seq_num:1;
384 u8 notify_action:5;
385 u8 probe_id;
386 u8 leave_crit;
387 u8 chkpt_timer;
388 u8 leave_time;
389 u8 leave_th;
390 u16 tx_pkt_ctrl;
391 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID];
392 u8 sw_def;
393 u16 fw_probe0_ssids;
394 u16 fw_probe0_shortssids;
395 u16 fw_probe0_bssids;
396
397 struct list_head list;
398 bool is_psc;
399 };
400
401 struct rtw89_pktofld_info {
402 struct list_head list;
403 u8 id;
404 bool wildcard_6ghz;
405
406 /* Below fields are for WiFi 6 chips 6 GHz RNR use only */
407 u8 ssid[IEEE80211_MAX_SSID_LEN];
408 u8 ssid_len;
409 u8 bssid[ETH_ALEN];
410 u16 channel_6ghz;
411 bool cancel;
412 };
413
414 struct rtw89_h2c_ra {
415 __le32 w0;
416 __le32 w1;
417 __le32 w2;
418 __le32 w3;
419 } __packed;
420
421 #define RTW89_H2C_RA_W0_IS_DIS BIT(0)
422 #define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)
423 #define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)
424 #define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)
425 #define RTW89_H2C_RA_W0_DCM BIT(16)
426 #define RTW89_H2C_RA_W0_ER BIT(17)
427 #define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)
428 #define RTW89_H2C_RA_W0_UPD_ALL BIT(20)
429 #define RTW89_H2C_RA_W0_SGI BIT(21)
430 #define RTW89_H2C_RA_W0_LDPC BIT(22)
431 #define RTW89_H2C_RA_W0_STBC BIT(23)
432 #define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)
433 #define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)
434 #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)
435 #define RTW89_H2C_RA_W0_UPD_MASK BIT(31)
436 #define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)
437 #define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)
438 #define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)
439 #define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)
440 #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)
441 #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)
442 #define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)
443 #define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)
444 #define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)
445 #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)
446 #define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)
447 #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)
448 #define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)
449
450 struct rtw89_h2c_ra_v1 {
451 struct rtw89_h2c_ra v0;
452 __le32 w4;
453 __le32 w5;
454 } __packed;
455
456 #define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)
457 #define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)
458 #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
459 #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
460
RTW89_SET_FWCMD_SEC_IDX(void * cmd,u32 val)461 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
462 {
463 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
464 }
465
RTW89_SET_FWCMD_SEC_OFFSET(void * cmd,u32 val)466 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)
467 {
468 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8));
469 }
470
RTW89_SET_FWCMD_SEC_LEN(void * cmd,u32 val)471 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)
472 {
473 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16));
474 }
475
RTW89_SET_FWCMD_SEC_TYPE(void * cmd,u32 val)476 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)
477 {
478 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0));
479 }
480
RTW89_SET_FWCMD_SEC_EXT_KEY(void * cmd,u32 val)481 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)
482 {
483 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4));
484 }
485
RTW89_SET_FWCMD_SEC_SPP_MODE(void * cmd,u32 val)486 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)
487 {
488 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5));
489 }
490
RTW89_SET_FWCMD_SEC_KEY0(void * cmd,u32 val)491 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)
492 {
493 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0));
494 }
495
RTW89_SET_FWCMD_SEC_KEY1(void * cmd,u32 val)496 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)
497 {
498 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0));
499 }
500
RTW89_SET_FWCMD_SEC_KEY2(void * cmd,u32 val)501 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)
502 {
503 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0));
504 }
505
RTW89_SET_FWCMD_SEC_KEY3(void * cmd,u32 val)506 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)
507 {
508 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0));
509 }
510
RTW89_SET_EDCA_SEL(void * cmd,u32 val)511 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)
512 {
513 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0));
514 }
515
RTW89_SET_EDCA_BAND(void * cmd,u32 val)516 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)
517 {
518 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3));
519 }
520
RTW89_SET_EDCA_WMM(void * cmd,u32 val)521 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)
522 {
523 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4));
524 }
525
RTW89_SET_EDCA_AC(void * cmd,u32 val)526 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)
527 {
528 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5));
529 }
530
RTW89_SET_EDCA_PARAM(void * cmd,u32 val)531 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)
532 {
533 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0));
534 }
535 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)
536 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)
537 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)
538 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)
539
540 #define FWDL_SECURITY_SECTION_TYPE 9
541 #define FWDL_SECURITY_SIGLEN 512
542 #define FWDL_SECURITY_CHKSUM_LEN 8
543
544 struct rtw89_fw_dynhdr_sec {
545 __le32 w0;
546 u8 content[];
547 } __packed;
548
549 struct rtw89_fw_dynhdr_hdr {
550 __le32 hdr_len;
551 __le32 setcion_count;
552 /* struct rtw89_fw_dynhdr_sec (nested flexible structures) */
553 } __packed;
554
555 struct rtw89_fw_hdr_section {
556 __le32 w0;
557 __le32 w1;
558 __le32 w2;
559 __le32 w3;
560 } __packed;
561
562 #define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)
563 #define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)
564 #define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)
565 #define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)
566 #define FWSECTION_HDR_W1_CHECKSUM BIT(28)
567 #define FWSECTION_HDR_W1_REDL BIT(29)
568 #define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)
569
570 struct rtw89_fw_hdr {
571 __le32 w0;
572 __le32 w1;
573 __le32 w2;
574 __le32 w3;
575 __le32 w4;
576 __le32 w5;
577 __le32 w6;
578 __le32 w7;
579 struct rtw89_fw_hdr_section sections[];
580 /* struct rtw89_fw_dynhdr_hdr (optional) */
581 } __packed;
582
583 #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)
584 #define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)
585 #define FW_HDR_W1_SUBVERSION GENMASK(23, 16)
586 #define FW_HDR_W1_SUBINDEX GENMASK(31, 24)
587 #define FW_HDR_W2_COMMITID GENMASK(31, 0)
588 #define FW_HDR_W3_LEN GENMASK(23, 16)
589 #define FW_HDR_W3_HDR_VER GENMASK(31, 24)
590 #define FW_HDR_W4_MONTH GENMASK(7, 0)
591 #define FW_HDR_W4_DATE GENMASK(15, 8)
592 #define FW_HDR_W4_HOUR GENMASK(23, 16)
593 #define FW_HDR_W4_MIN GENMASK(31, 24)
594 #define FW_HDR_W5_YEAR GENMASK(31, 0)
595 #define FW_HDR_W6_SEC_NUM GENMASK(15, 8)
596 #define FW_HDR_W7_PART_SIZE GENMASK(15, 0)
597 #define FW_HDR_W7_DYN_HDR BIT(16)
598 #define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
599 #define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)
600
601 struct rtw89_fw_hdr_section_v1 {
602 __le32 w0;
603 __le32 w1;
604 __le32 w2;
605 __le32 w3;
606 } __packed;
607
608 #define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)
609 #define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)
610 #define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)
611 #define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)
612 #define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)
613 #define FWSECTION_HDR_V1_W1_REDL BIT(29)
614 #define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)
615 #define FORMATTED_MSSC 0xFF
616 #define FORMATTED_MSSC_MASK GENMASK(7, 0)
617 #define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)
618
619 struct rtw89_fw_hdr_v1 {
620 __le32 w0;
621 __le32 w1;
622 __le32 w2;
623 __le32 w3;
624 __le32 w4;
625 __le32 w5;
626 __le32 w6;
627 __le32 w7;
628 __le32 w8;
629 __le32 w9;
630 __le32 w10;
631 __le32 w11;
632 struct rtw89_fw_hdr_section_v1 sections[];
633 } __packed;
634
635 #define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)
636 #define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)
637 #define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)
638 #define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)
639 #define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)
640 #define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)
641 #define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)
642 #define FW_HDR_V1_W4_MONTH GENMASK(7, 0)
643 #define FW_HDR_V1_W4_DATE GENMASK(15, 8)
644 #define FW_HDR_V1_W4_HOUR GENMASK(23, 16)
645 #define FW_HDR_V1_W4_MIN GENMASK(31, 24)
646 #define FW_HDR_V1_W5_YEAR GENMASK(15, 0)
647 #define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)
648 #define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)
649 #define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)
650 #define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)
651 #define FW_HDR_V1_W7_DYN_HDR BIT(16)
652 #define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)
653
654 enum rtw89_fw_mss_pool_rmp_tbl_type {
655 MSS_POOL_RMP_TBL_BITMASK = 0x0,
656 MSS_POOL_RMP_TBL_RECORD = 0x1,
657 };
658
659 #define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8
660
661 struct rtw89_fw_mss_pool_hdr {
662 u8 signature[8]; /* equal to mss_signature[] */
663 __le32 rmp_tbl_offset;
664 __le32 key_raw_offset;
665 u8 defen;
666 u8 rsvd[3];
667 u8 rmpfmt; /* enum rtw89_fw_mss_pool_rmp_tbl_type */
668 u8 mssdev_max;
669 __le16 keypair_num;
670 __le16 msscust_max;
671 __le16 msskey_num_max;
672 __le32 rsvd3;
673 u8 rmp_tbl[];
674 } __packed;
675
676 union rtw89_fw_section_mssc_content {
677 struct {
678 u8 pad[0x20];
679 u8 bit_in_chip_list;
680 u8 ver;
681 } __packed blacklist;
682 struct {
683 u8 pad[58];
684 __le32 v;
685 } __packed sb_sel_ver;
686 struct {
687 u8 pad[60];
688 __le16 v;
689 } __packed key_sign_len;
690 } __packed;
691
692 struct rtw89_fw_blacklist {
693 u8 ver;
694 u8 list[32];
695 };
696
697 extern const struct rtw89_fw_blacklist rtw89_fw_blacklist_default;
698
SET_CTRL_INFO_MACID(void * table,u32 val)699 static inline void SET_CTRL_INFO_MACID(void *table, u32 val)
700 {
701 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0));
702 }
703
SET_CTRL_INFO_OPERATION(void * table,u32 val)704 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)
705 {
706 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7));
707 }
708 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)
SET_CMC_TBL_DATARATE(void * table,u32 val)709 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)
710 {
711 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0));
712 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE,
713 GENMASK(8, 0));
714 }
715 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)
SET_CMC_TBL_FORCE_TXOP(void * table,u32 val)716 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)
717 {
718 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9));
719 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP,
720 BIT(9));
721 }
722 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)
SET_CMC_TBL_DATA_BW(void * table,u32 val)723 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)
724 {
725 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10));
726 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW,
727 GENMASK(11, 10));
728 }
729 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_DATA_GI_LTF(void * table,u32 val)730 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)
731 {
732 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12));
733 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF,
734 GENMASK(14, 12));
735 }
736 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)
SET_CMC_TBL_DARF_TC_INDEX(void * table,u32 val)737 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)
738 {
739 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15));
740 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX,
741 BIT(15));
742 }
743 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)
SET_CMC_TBL_ARFR_CTRL(void * table,u32 val)744 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)
745 {
746 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16));
747 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL,
748 GENMASK(19, 16));
749 }
750 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)
SET_CMC_TBL_ACQ_RPT_EN(void * table,u32 val)751 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)
752 {
753 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20));
754 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN,
755 BIT(20));
756 }
757 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)
SET_CMC_TBL_MGQ_RPT_EN(void * table,u32 val)758 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)
759 {
760 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21));
761 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN,
762 BIT(21));
763 }
764 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)
SET_CMC_TBL_ULQ_RPT_EN(void * table,u32 val)765 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)
766 {
767 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22));
768 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN,
769 BIT(22));
770 }
771 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)
SET_CMC_TBL_TWTQ_RPT_EN(void * table,u32 val)772 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)
773 {
774 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23));
775 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN,
776 BIT(23));
777 }
778 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0)
SET_CMC_TBL_DISRTSFB(void * table,u32 val)779 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)
780 {
781 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25));
782 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB,
783 BIT(25));
784 }
785 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0)
SET_CMC_TBL_DISDATAFB(void * table,u32 val)786 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)
787 {
788 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26));
789 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB,
790 BIT(26));
791 }
792 #define SET_CMC_TBL_MASK_TRYRATE BIT(0)
SET_CMC_TBL_TRYRATE(void * table,u32 val)793 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)
794 {
795 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27));
796 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE,
797 BIT(27));
798 }
799 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)
SET_CMC_TBL_AMPDU_DENSITY(void * table,u32 val)800 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)
801 {
802 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28));
803 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY,
804 GENMASK(31, 28));
805 }
806 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)
SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void * table,u32 val)807 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)
808 {
809 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0));
810 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE,
811 GENMASK(8, 0));
812 }
813 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)
SET_CMC_TBL_AMPDU_TIME_SEL(void * table,u32 val)814 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)
815 {
816 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9));
817 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL,
818 BIT(9));
819 }
820 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)
SET_CMC_TBL_AMPDU_LEN_SEL(void * table,u32 val)821 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)
822 {
823 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10));
824 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL,
825 BIT(10));
826 }
827 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void * table,u32 val)828 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)
829 {
830 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11));
831 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL,
832 BIT(11));
833 }
834 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)
SET_CMC_TBL_RTS_TXCNT_LMT(void * table,u32 val)835 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)
836 {
837 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12));
838 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT,
839 GENMASK(15, 12));
840 }
841 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)
SET_CMC_TBL_RTSRATE(void * table,u32 val)842 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)
843 {
844 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16));
845 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE,
846 GENMASK(24, 16));
847 }
848 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0)
SET_CMC_TBL_VCS_STBC(void * table,u32 val)849 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)
850 {
851 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27));
852 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC,
853 BIT(27));
854 }
855 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)
SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void * table,u32 val)856 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)
857 {
858 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28));
859 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE,
860 GENMASK(31, 28));
861 }
862 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)
SET_CMC_TBL_DATA_TX_CNT_LMT(void * table,u32 val)863 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)
864 {
865 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0));
866 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT,
867 GENMASK(5, 0));
868 }
869 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)
SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void * table,u32 val)870 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)
871 {
872 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6));
873 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL,
874 BIT(6));
875 }
876 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)
SET_CMC_TBL_MAX_AGG_NUM_SEL(void * table,u32 val)877 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)
878 {
879 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7));
880 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL,
881 BIT(7));
882 }
883 #define SET_CMC_TBL_MASK_RTS_EN BIT(0)
SET_CMC_TBL_RTS_EN(void * table,u32 val)884 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)
885 {
886 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8));
887 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN,
888 BIT(8));
889 }
890 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)
SET_CMC_TBL_CTS2SELF_EN(void * table,u32 val)891 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)
892 {
893 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9));
894 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN,
895 BIT(9));
896 }
897 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)
SET_CMC_TBL_CCA_RTS(void * table,u32 val)898 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)
899 {
900 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10));
901 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS,
902 GENMASK(11, 10));
903 }
904 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)
SET_CMC_TBL_HW_RTS_EN(void * table,u32 val)905 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)
906 {
907 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12));
908 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN,
909 BIT(12));
910 }
911 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)
SET_CMC_TBL_RTS_DROP_DATA_MODE(void * table,u32 val)912 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)
913 {
914 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13));
915 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE,
916 GENMASK(14, 13));
917 }
918 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)
SET_CMC_TBL_AMPDU_MAX_LEN(void * table,u32 val)919 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)
920 {
921 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16));
922 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN,
923 GENMASK(26, 16));
924 }
925 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)
SET_CMC_TBL_UL_MU_DIS(void * table,u32 val)926 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)
927 {
928 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27));
929 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS,
930 BIT(27));
931 }
932 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)
SET_CMC_TBL_AMPDU_MAX_TIME(void * table,u32 val)933 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)
934 {
935 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28));
936 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME,
937 GENMASK(31, 28));
938 }
939 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)
SET_CMC_TBL_MAX_AGG_NUM(void * table,u32 val)940 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)
941 {
942 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0));
943 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM,
944 GENMASK(7, 0));
945 }
946 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)
SET_CMC_TBL_BA_BMAP(void * table,u32 val)947 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)
948 {
949 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8));
950 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP,
951 GENMASK(9, 8));
952 }
953 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VO_LFTIME_SEL(void * table,u32 val)954 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)
955 {
956 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16));
957 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL,
958 GENMASK(18, 16));
959 }
960 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_VI_LFTIME_SEL(void * table,u32 val)961 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)
962 {
963 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19));
964 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL,
965 GENMASK(21, 19));
966 }
967 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BE_LFTIME_SEL(void * table,u32 val)968 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)
969 {
970 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22));
971 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL,
972 GENMASK(24, 22));
973 }
974 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)
SET_CMC_TBL_BK_LFTIME_SEL(void * table,u32 val)975 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)
976 {
977 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25));
978 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL,
979 GENMASK(27, 25));
980 }
981 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)
SET_CMC_TBL_SECTYPE(void * table,u32 val)982 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)
983 {
984 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28));
985 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE,
986 GENMASK(31, 28));
987 }
988 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)
SET_CMC_TBL_MULTI_PORT_ID(void * table,u32 val)989 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)
990 {
991 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0));
992 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID,
993 GENMASK(2, 0));
994 }
995 #define SET_CMC_TBL_MASK_BMC BIT(0)
SET_CMC_TBL_BMC(void * table,u32 val)996 static inline void SET_CMC_TBL_BMC(void *table, u32 val)
997 {
998 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3));
999 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC,
1000 BIT(3));
1001 }
1002 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)
SET_CMC_TBL_MBSSID(void * table,u32 val)1003 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)
1004 {
1005 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4));
1006 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID,
1007 GENMASK(7, 4));
1008 }
1009 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)
SET_CMC_TBL_NAVUSEHDR(void * table,u32 val)1010 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)
1011 {
1012 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8));
1013 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR,
1014 BIT(8));
1015 }
1016 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)
SET_CMC_TBL_TXPWR_MODE(void * table,u32 val)1017 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)
1018 {
1019 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9));
1020 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE,
1021 GENMASK(11, 9));
1022 }
1023 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0)
SET_CMC_TBL_DATA_DCM(void * table,u32 val)1024 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)
1025 {
1026 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12));
1027 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM,
1028 BIT(12));
1029 }
1030 #define SET_CMC_TBL_MASK_DATA_ER BIT(0)
SET_CMC_TBL_DATA_ER(void * table,u32 val)1031 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)
1032 {
1033 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13));
1034 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER,
1035 BIT(13));
1036 }
1037 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)
SET_CMC_TBL_DATA_LDPC(void * table,u32 val)1038 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)
1039 {
1040 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14));
1041 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC,
1042 BIT(14));
1043 }
1044 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0)
SET_CMC_TBL_DATA_STBC(void * table,u32 val)1045 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)
1046 {
1047 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15));
1048 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC,
1049 BIT(15));
1050 }
1051 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)
SET_CMC_TBL_A_CTRL_BQR(void * table,u32 val)1052 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)
1053 {
1054 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16));
1055 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR,
1056 BIT(16));
1057 }
1058 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)
SET_CMC_TBL_A_CTRL_UPH(void * table,u32 val)1059 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)
1060 {
1061 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17));
1062 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH,
1063 BIT(17));
1064 }
1065 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)
SET_CMC_TBL_A_CTRL_BSR(void * table,u32 val)1066 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)
1067 {
1068 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18));
1069 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR,
1070 BIT(18));
1071 }
1072 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)
SET_CMC_TBL_A_CTRL_CAS(void * table,u32 val)1073 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)
1074 {
1075 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19));
1076 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS,
1077 BIT(19));
1078 }
1079 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)
SET_CMC_TBL_DATA_BW_ER(void * table,u32 val)1080 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)
1081 {
1082 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20));
1083 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER,
1084 BIT(20));
1085 }
1086 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)
SET_CMC_TBL_LSIG_TXOP_EN(void * table,u32 val)1087 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)
1088 {
1089 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21));
1090 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN,
1091 BIT(21));
1092 }
1093 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)
SET_CMC_TBL_CTRL_CNT_VLD(void * table,u32 val)1094 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)
1095 {
1096 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27));
1097 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD,
1098 BIT(27));
1099 }
1100 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)
SET_CMC_TBL_CTRL_CNT(void * table,u32 val)1101 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)
1102 {
1103 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28));
1104 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT,
1105 GENMASK(31, 28));
1106 }
1107 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)
SET_CMC_TBL_RESP_REF_RATE(void * table,u32 val)1108 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)
1109 {
1110 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0));
1111 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE,
1112 GENMASK(8, 0));
1113 }
1114 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)
SET_CMC_TBL_ALL_ACK_SUPPORT(void * table,u32 val)1115 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)
1116 {
1117 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12));
1118 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT,
1119 BIT(12));
1120 }
1121 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void * table,u32 val)1122 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)
1123 {
1124 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13));
1125 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT,
1126 BIT(13));
1127 }
1128 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)
SET_CMC_TBL_NTX_PATH_EN(void * table,u32 val)1129 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)
1130 {
1131 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16));
1132 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN,
1133 GENMASK(19, 16));
1134 }
1135 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_A(void * table,u32 val)1136 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)
1137 {
1138 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20));
1139 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A,
1140 GENMASK(21, 20));
1141 }
1142 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_B(void * table,u32 val)1143 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)
1144 {
1145 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22));
1146 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B,
1147 GENMASK(23, 22));
1148 }
1149 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_C(void * table,u32 val)1150 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)
1151 {
1152 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24));
1153 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C,
1154 GENMASK(25, 24));
1155 }
1156 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)
SET_CMC_TBL_PATH_MAP_D(void * table,u32 val)1157 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)
1158 {
1159 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26));
1160 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D,
1161 GENMASK(27, 26));
1162 }
1163 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)
SET_CMC_TBL_ANTSEL_A(void * table,u32 val)1164 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)
1165 {
1166 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28));
1167 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A,
1168 BIT(28));
1169 }
1170 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)
SET_CMC_TBL_ANTSEL_B(void * table,u32 val)1171 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)
1172 {
1173 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29));
1174 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B,
1175 BIT(29));
1176 }
1177 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)
SET_CMC_TBL_ANTSEL_C(void * table,u32 val)1178 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)
1179 {
1180 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30));
1181 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C,
1182 BIT(30));
1183 }
1184 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)
SET_CMC_TBL_ANTSEL_D(void * table,u32 val)1185 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)
1186 {
1187 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31));
1188 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D,
1189 BIT(31));
1190 }
1191
1192 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)
SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void * table,u32 val)1193 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)
1194 {
1195 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0));
1196 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1197 GENMASK(1, 0));
1198 }
1199
SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void * table,u32 val)1200 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)
1201 {
1202 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2));
1203 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1204 GENMASK(3, 2));
1205 }
1206
SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void * table,u32 val)1207 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)
1208 {
1209 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4));
1210 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1211 GENMASK(5, 4));
1212 }
1213
SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void * table,u32 val)1214 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)
1215 {
1216 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6));
1217 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1218 GENMASK(7, 6));
1219 }
1220
1221 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)
SET_CMC_TBL_ADDR_CAM_INDEX(void * table,u32 val)1222 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)
1223 {
1224 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0));
1225 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX,
1226 GENMASK(7, 0));
1227 }
1228 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)
SET_CMC_TBL_PAID(void * table,u32 val)1229 static inline void SET_CMC_TBL_PAID(void *table, u32 val)
1230 {
1231 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8));
1232 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID,
1233 GENMASK(16, 8));
1234 }
1235 #define SET_CMC_TBL_MASK_ULDL BIT(0)
SET_CMC_TBL_ULDL(void * table,u32 val)1236 static inline void SET_CMC_TBL_ULDL(void *table, u32 val)
1237 {
1238 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17));
1239 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL,
1240 BIT(17));
1241 }
1242 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)
SET_CMC_TBL_DOPPLER_CTRL(void * table,u32 val)1243 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)
1244 {
1245 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18));
1246 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL,
1247 GENMASK(19, 18));
1248 }
SET_CMC_TBL_NOMINAL_PKT_PADDING(void * table,u32 val)1249 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)
1250 {
1251 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20));
1252 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1253 GENMASK(21, 20));
1254 }
1255
SET_CMC_TBL_NOMINAL_PKT_PADDING40(void * table,u32 val)1256 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)
1257 {
1258 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22));
1259 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1260 GENMASK(23, 22));
1261 }
1262 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)
SET_CMC_TBL_TXPWR_TOLERENCE(void * table,u32 val)1263 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)
1264 {
1265 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24));
1266 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE,
1267 GENMASK(27, 24));
1268 }
1269
SET_CMC_TBL_NOMINAL_PKT_PADDING80(void * table,u32 val)1270 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)
1271 {
1272 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30));
1273 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1274 GENMASK(31, 30));
1275 }
1276 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0)
SET_CMC_TBL_NC(void * table,u32 val)1277 static inline void SET_CMC_TBL_NC(void *table, u32 val)
1278 {
1279 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0));
1280 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC,
1281 GENMASK(2, 0));
1282 }
1283 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0)
SET_CMC_TBL_NR(void * table,u32 val)1284 static inline void SET_CMC_TBL_NR(void *table, u32 val)
1285 {
1286 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3));
1287 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR,
1288 GENMASK(5, 3));
1289 }
1290 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0)
SET_CMC_TBL_NG(void * table,u32 val)1291 static inline void SET_CMC_TBL_NG(void *table, u32 val)
1292 {
1293 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6));
1294 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG,
1295 GENMASK(7, 6));
1296 }
1297 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0)
SET_CMC_TBL_CB(void * table,u32 val)1298 static inline void SET_CMC_TBL_CB(void *table, u32 val)
1299 {
1300 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8));
1301 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB,
1302 GENMASK(9, 8));
1303 }
1304 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0)
SET_CMC_TBL_CS(void * table,u32 val)1305 static inline void SET_CMC_TBL_CS(void *table, u32 val)
1306 {
1307 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10));
1308 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS,
1309 GENMASK(11, 10));
1310 }
1311 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)
SET_CMC_TBL_CSI_TXBF_EN(void * table,u32 val)1312 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)
1313 {
1314 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12));
1315 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN,
1316 BIT(12));
1317 }
1318 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)
SET_CMC_TBL_CSI_STBC_EN(void * table,u32 val)1319 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)
1320 {
1321 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13));
1322 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN,
1323 BIT(13));
1324 }
1325 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)
SET_CMC_TBL_CSI_LDPC_EN(void * table,u32 val)1326 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)
1327 {
1328 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14));
1329 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN,
1330 BIT(14));
1331 }
1332 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)
SET_CMC_TBL_CSI_PARA_EN(void * table,u32 val)1333 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)
1334 {
1335 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15));
1336 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN,
1337 BIT(15));
1338 }
1339 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)
SET_CMC_TBL_CSI_FIX_RATE(void * table,u32 val)1340 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)
1341 {
1342 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16));
1343 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE,
1344 GENMASK(24, 16));
1345 }
1346 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)
SET_CMC_TBL_CSI_GI_LTF(void * table,u32 val)1347 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)
1348 {
1349 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25));
1350 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF,
1351 GENMASK(27, 25));
1352 }
1353
SET_CMC_TBL_NOMINAL_PKT_PADDING160(void * table,u32 val)1354 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)
1355 {
1356 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28));
1357 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING,
1358 GENMASK(29, 28));
1359 }
1360
1361 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)
SET_CMC_TBL_CSI_BW(void * table,u32 val)1362 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)
1363 {
1364 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30));
1365 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW,
1366 GENMASK(31, 30));
1367 }
1368
1369 struct rtw89_h2c_cctlinfo_ud_g7 {
1370 __le32 c0;
1371 __le32 w0;
1372 __le32 w1;
1373 __le32 w2;
1374 __le32 w3;
1375 __le32 w4;
1376 __le32 w5;
1377 __le32 w6;
1378 __le32 w7;
1379 __le32 w8;
1380 __le32 w9;
1381 __le32 w10;
1382 __le32 w11;
1383 __le32 w12;
1384 __le32 w13;
1385 __le32 w14;
1386 __le32 w15;
1387 __le32 m0;
1388 __le32 m1;
1389 __le32 m2;
1390 __le32 m3;
1391 __le32 m4;
1392 __le32 m5;
1393 __le32 m6;
1394 __le32 m7;
1395 __le32 m8;
1396 __le32 m9;
1397 __le32 m10;
1398 __le32 m11;
1399 __le32 m12;
1400 __le32 m13;
1401 __le32 m14;
1402 __le32 m15;
1403 } __packed;
1404
1405 #define CCTLINFO_G7_C0_MACID GENMASK(6, 0)
1406 #define CCTLINFO_G7_C0_OP BIT(7)
1407
1408 #define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)
1409 #define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)
1410 #define CCTLINFO_G7_W0_TRYRATE BIT(15)
1411 #define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)
1412 #define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)
1413 #define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)
1414 #define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)
1415 #define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)
1416 #define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)
1417 #define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)
1418 #define CCTLINFO_G7_W0_DISRTSFB BIT(25)
1419 #define CCTLINFO_G7_W0_DISDATAFB BIT(26)
1420 #define CCTLINFO_G7_W0_NSTR_EN BIT(27)
1421 #define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)
1422 #define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))
1423 #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)
1424 #define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)
1425 #define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)
1426 #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)
1427 #define CCTLINFO_G7_W1_ALL GENMASK(31, 0)
1428 #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)
1429 #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)
1430 #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)
1431 #define CCTLINFO_G7_W2_RTS_EN BIT(8)
1432 #define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)
1433 #define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)
1434 #define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)
1435 #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)
1436 #define CCTLINFO_G7_W2_PRELD_EN BIT(15)
1437 #define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)
1438 #define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)
1439 #define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)
1440 #define CCTLINFO_G7_W2_ALL GENMASK(31, 0)
1441 #define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)
1442 #define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)
1443 #define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)
1444 #define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)
1445 #define CCTLINFO_G7_W3_VCS_STBC BIT(15)
1446 #define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)
1447 #define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)
1448 #define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)
1449 #define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)
1450 #define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)
1451 #define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)
1452 #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)
1453 #define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)
1454 #define CCTLINFO_G7_W3_ALL GENMASK(31, 0)
1455 #define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)
1456 #define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)
1457 #define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)
1458 #define CCTLINFO_G7_W4_DATA_DCM BIT(8)
1459 #define CCTLINFO_G7_W4_DATA_ER BIT(9)
1460 #define CCTLINFO_G7_W4_DATA_LDPC BIT(10)
1461 #define CCTLINFO_G7_W4_DATA_STBC BIT(11)
1462 #define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)
1463 #define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)
1464 #define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)
1465 #define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)
1466 #define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))
1467 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)
1468 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)
1469 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)
1470 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)
1471 #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)
1472 #define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)
1473 #define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)
1474 #define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)
1475 #define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))
1476 #define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)
1477 #define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)
1478 #define CCTLINFO_G7_W6_ULDL BIT(31)
1479 #define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))
1480 #define CCTLINFO_G7_W7_NC GENMASK(2, 0)
1481 #define CCTLINFO_G7_W7_NR GENMASK(5, 3)
1482 #define CCTLINFO_G7_W7_NG GENMASK(7, 6)
1483 #define CCTLINFO_G7_W7_CB GENMASK(9, 8)
1484 #define CCTLINFO_G7_W7_CS GENMASK(11, 10)
1485 #define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)
1486 #define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)
1487 #define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)
1488 #define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)
1489 #define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)
1490 #define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))
1491 #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)
1492 #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)
1493 #define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)
1494 #define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)
1495 #define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)
1496 #define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)
1497 #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)
1498 #define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)
1499 #define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)
1500 #define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)
1501 #define CCTLINFO_G7_W8_ALL GENMASK(15, 0)
1502 /* W9~13 are reserved */
1503 #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)
1504 #define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)
1505 #define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)
1506 #define CCTLINFO_G7_W14_ALL GENMASK(31, 0)
1507 #define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)
1508 #define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)
1509 #define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)
1510 #define CCTLINFO_G7_W15_ALL GENMASK(27, 0)
1511
1512 struct rtw89_h2c_bcn_upd {
1513 __le32 w0;
1514 __le32 w1;
1515 __le32 w2;
1516 } __packed;
1517
1518 #define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)
1519 #define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)
1520 #define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)
1521 #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)
1522 #define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)
1523 #define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)
1524 #define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)
1525 #define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)
1526 #define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)
1527 #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)
1528 #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)
1529 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)
1530 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)
1531 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)
1532 #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)
1533 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)
1534 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)
1535 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)
1536 #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)
1537 #define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)
1538
1539 struct rtw89_h2c_bcn_upd_be {
1540 __le32 w0;
1541 __le32 w1;
1542 __le32 w2;
1543 __le32 w3;
1544 __le32 w4;
1545 __le32 w5;
1546 __le32 w6;
1547 __le32 w7;
1548 __le32 w8;
1549 __le32 w9;
1550 __le32 w10;
1551 __le32 w11;
1552 __le32 w12;
1553 __le32 w13;
1554 __le32 w14;
1555 __le32 w15;
1556 __le32 w16;
1557 __le32 w17;
1558 __le32 w18;
1559 __le32 w19;
1560 __le32 w20;
1561 __le32 w21;
1562 __le32 w22;
1563 __le32 w23;
1564 __le32 w24;
1565 __le32 w25;
1566 __le32 w26;
1567 __le32 w27;
1568 __le32 w28;
1569 __le32 w29;
1570 } __packed;
1571
1572 #define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)
1573 #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)
1574 #define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)
1575 #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)
1576 #define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)
1577 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)
1578 #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)
1579 #define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)
1580 #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)
1581 #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)
1582 #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)
1583 #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)
1584 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)
1585 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)
1586 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)
1587 #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)
1588 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)
1589 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)
1590 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)
1591 #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)
1592 #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)
1593 #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)
1594 #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)
1595 #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)
1596 #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)
1597 #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)
1598 #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)
1599 #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)
1600 #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)
1601 #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)
1602 #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)
1603 #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)
1604
1605 struct rtw89_h2c_role_maintain {
1606 __le32 w0;
1607 };
1608
1609 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID GENMASK(7, 0)
1610 #define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8)
1611 #define RTW89_H2C_ROLE_MAINTAIN_W0_UPD_MODE GENMASK(12, 10)
1612 #define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13)
1613 #define RTW89_H2C_ROLE_MAINTAIN_W0_BAND GENMASK(18, 17)
1614 #define RTW89_H2C_ROLE_MAINTAIN_W0_PORT GENMASK(21, 19)
1615 #define RTW89_H2C_ROLE_MAINTAIN_W0_MACID_EXT GENMASK(31, 24)
1616
1617 enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */
1618 RTW89_FW_N_AC_STA = 0,
1619 RTW89_FW_AX_STA = 1,
1620 RTW89_FW_BE_STA = 2,
1621 };
1622
1623 struct rtw89_h2c_join {
1624 __le32 w0;
1625 } __packed;
1626
1627 struct rtw89_h2c_join_v1 {
1628 __le32 w0;
1629 __le32 w1;
1630 __le32 w2;
1631 } __packed;
1632
1633 #define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)
1634 #define RTW89_H2C_JOININFO_W0_OP BIT(8)
1635 #define RTW89_H2C_JOININFO_W0_BAND BIT(9)
1636 #define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)
1637 #define RTW89_H2C_JOININFO_W0_TGR BIT(12)
1638 #define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)
1639 #define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)
1640 #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)
1641 #define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)
1642 #define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)
1643 #define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)
1644 #define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)
1645 #define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)
1646 #define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)
1647 #define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)
1648 #define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)
1649 #define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)
1650 #define RTW89_H2C_JOININFO_MLO_MODE_MLMR 0
1651 #define RTW89_H2C_JOININFO_MLO_MODE_MLSR 1
1652 #define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)
1653 #define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)
1654 #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)
1655 #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)
1656 #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)
1657 #define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)
1658 #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)
1659
1660 struct rtw89_h2c_notify_dbcc {
1661 __le32 w0;
1662 } __packed;
1663
1664 #define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)
1665
SET_GENERAL_PKT_MACID(void * h2c,u32 val)1666 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)
1667 {
1668 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1669 }
1670
SET_GENERAL_PKT_PROBRSP_ID(void * h2c,u32 val)1671 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)
1672 {
1673 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1674 }
1675
SET_GENERAL_PKT_PSPOLL_ID(void * h2c,u32 val)1676 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)
1677 {
1678 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1679 }
1680
SET_GENERAL_PKT_NULL_ID(void * h2c,u32 val)1681 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)
1682 {
1683 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1684 }
1685
SET_GENERAL_PKT_QOS_NULL_ID(void * h2c,u32 val)1686 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)
1687 {
1688 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1689 }
1690
SET_GENERAL_PKT_CTS2SELF_ID(void * h2c,u32 val)1691 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)
1692 {
1693 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1694 }
1695
SET_LOG_CFG_LEVEL(void * h2c,u32 val)1696 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)
1697 {
1698 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1699 }
1700
SET_LOG_CFG_PATH(void * h2c,u32 val)1701 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)
1702 {
1703 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1704 }
1705
SET_LOG_CFG_COMP(void * h2c,u32 val)1706 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)
1707 {
1708 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0));
1709 }
1710
SET_LOG_CFG_COMP_EXT(void * h2c,u32 val)1711 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)
1712 {
1713 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0));
1714 }
1715
1716 struct rtw89_h2c_ba_cam {
1717 __le32 w0;
1718 __le32 w1;
1719 } __packed;
1720
1721 #define RTW89_H2C_BA_CAM_W0_VALID BIT(0)
1722 #define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)
1723 #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)
1724 #define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)
1725 #define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)
1726 #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)
1727 #define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)
1728 #define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)
1729 #define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)
1730 #define RTW89_H2C_BA_CAM_W1_BAND BIT(9)
1731 #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)
1732
1733 struct rtw89_h2c_ba_cam_v1 {
1734 __le32 w0;
1735 __le32 w1;
1736 } __packed;
1737
1738 #define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)
1739 #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)
1740 #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)
1741 #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)
1742 #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)
1743 #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)
1744 #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)
1745 #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)
1746 #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)
1747 #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)
1748 #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)
1749
1750 struct rtw89_h2c_ba_cam_init {
1751 __le32 w0;
1752 } __packed;
1753
1754 #define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)
1755 #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)
1756 #define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)
1757
SET_LPS_PARM_MACID(void * h2c,u32 val)1758 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)
1759 {
1760 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0));
1761 }
1762
SET_LPS_PARM_PSMODE(void * h2c,u32 val)1763 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)
1764 {
1765 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1766 }
1767
SET_LPS_PARM_RLBM(void * h2c,u32 val)1768 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)
1769 {
1770 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16));
1771 }
1772
SET_LPS_PARM_SMARTPS(void * h2c,u32 val)1773 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)
1774 {
1775 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20));
1776 }
1777
SET_LPS_PARM_AWAKEINTERVAL(void * h2c,u32 val)1778 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)
1779 {
1780 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1781 }
1782
SET_LPS_PARM_VOUAPSD(void * h2c,u32 val)1783 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)
1784 {
1785 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0));
1786 }
1787
SET_LPS_PARM_VIUAPSD(void * h2c,u32 val)1788 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)
1789 {
1790 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1));
1791 }
1792
SET_LPS_PARM_BEUAPSD(void * h2c,u32 val)1793 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)
1794 {
1795 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2));
1796 }
1797
SET_LPS_PARM_BKUAPSD(void * h2c,u32 val)1798 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)
1799 {
1800 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3));
1801 }
1802
SET_LPS_PARM_LASTRPWM(void * h2c,u32 val)1803 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)
1804 {
1805 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8));
1806 }
1807
1808 struct rtw89_h2c_lps_ch_info {
1809 struct {
1810 u8 pri_ch;
1811 u8 central_ch;
1812 u8 bw;
1813 u8 band;
1814 } __packed info[2];
1815
1816 __le32 mlo_dbcc_mode_lps;
1817 } __packed;
1818
1819 struct rtw89_h2c_lps_ml_cmn_info {
1820 u8 fmt_id;
1821 u8 rfe_type;
1822 u8 rsvd0[2];
1823 __le32 mlo_dbcc_mode;
1824 u8 central_ch[RTW89_PHY_NUM];
1825 u8 pri_ch[RTW89_PHY_NUM];
1826 u8 bw[RTW89_PHY_NUM];
1827 u8 band[RTW89_PHY_NUM];
1828 u8 bcn_rate_type[RTW89_PHY_NUM];
1829 u8 rsvd1[2];
1830 __le16 tia_gain[RTW89_PHY_NUM][TIA_GAIN_NUM];
1831 u8 lna_gain[RTW89_PHY_NUM][LNA_GAIN_NUM];
1832 u8 rsvd2[2];
1833 u8 tia_lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM + 1];
1834 u8 lna_op1db[RTW89_PHY_NUM][LNA_GAIN_NUM];
1835 u8 dup_bcn_ofst[RTW89_PHY_NUM];
1836 } __packed;
1837
1838 struct rtw89_h2c_trig_cpu_except {
1839 __le32 w0;
1840 } __packed;
1841
1842 #define RTW89_H2C_CPU_EXCEPTION_TYPE GENMASK(31, 0)
1843
RTW89_SET_FWCMD_PKT_DROP_SEL(void * cmd,u32 val)1844 static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)
1845 {
1846 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
1847 }
1848
RTW89_SET_FWCMD_PKT_DROP_MACID(void * cmd,u32 val)1849 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)
1850 {
1851 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
1852 }
1853
RTW89_SET_FWCMD_PKT_DROP_BAND(void * cmd,u32 val)1854 static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)
1855 {
1856 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
1857 }
1858
RTW89_SET_FWCMD_PKT_DROP_PORT(void * cmd,u32 val)1859 static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)
1860 {
1861 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
1862 }
1863
RTW89_SET_FWCMD_PKT_DROP_MBSSID(void * cmd,u32 val)1864 static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)
1865 {
1866 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 0));
1867 }
1868
RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void * cmd,u32 val)1869 static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)
1870 {
1871 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(15, 8));
1872 }
1873
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void * cmd,u32 val)1874 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)
1875 {
1876 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
1877 }
1878
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void * cmd,u32 val)1879 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)
1880 {
1881 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
1882 }
1883
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void * cmd,u32 val)1884 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)
1885 {
1886 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
1887 }
1888
RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void * cmd,u32 val)1889 static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)
1890 {
1891 le32p_replace_bits((__le32 *)cmd + 5, val, GENMASK(31, 0));
1892 }
1893
RTW89_SET_KEEP_ALIVE_ENABLE(void * h2c,u32 val)1894 static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)
1895 {
1896 le32p_replace_bits((__le32 *)h2c, val, GENMASK(1, 0));
1897 }
1898
RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void * h2c,u32 val)1899 static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)
1900 {
1901 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1902 }
1903
RTW89_SET_KEEP_ALIVE_PERIOD(void * h2c,u32 val)1904 static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)
1905 {
1906 le32p_replace_bits((__le32 *)h2c, val, GENMASK(24, 16));
1907 }
1908
RTW89_SET_KEEP_ALIVE_MACID(void * h2c,u32 val)1909 static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)
1910 {
1911 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1912 }
1913
RTW89_SET_DISCONNECT_DETECT_ENABLE(void * h2c,u32 val)1914 static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)
1915 {
1916 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1917 }
1918
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void * h2c,u32 val)1919 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)
1920 {
1921 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1922 }
1923
RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void * h2c,u32 val)1924 static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)
1925 {
1926 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1927 }
1928
RTW89_SET_DISCONNECT_DETECT_MAC_ID(void * h2c,u32 val)1929 static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)
1930 {
1931 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8));
1932 }
1933
RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void * h2c,u32 val)1934 static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)
1935 {
1936 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16));
1937 }
1938
RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void * h2c,u32 val)1939 static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)
1940 {
1941 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
1942 }
1943
RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void * h2c,u32 val)1944 static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)
1945 {
1946 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0));
1947 }
1948
1949 struct rtw89_h2c_wow_global {
1950 __le32 w0;
1951 struct rtw89_wow_key_info key_info;
1952 } __packed;
1953
1954 #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)
1955 #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)
1956 #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)
1957 #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)
1958 #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)
1959 #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)
1960 #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)
1961
1962 #define RTW89_MAX_SUPPORT_NL_NUM 16
1963 struct rtw89_h2c_cfg_nlo {
1964 __le32 w0;
1965 u8 nlo_cnt;
1966 u8 rsvd[3];
1967 __le32 patterncheck;
1968 __le32 rsvd1;
1969 __le32 rsvd2;
1970 u8 ssid_len[RTW89_MAX_SUPPORT_NL_NUM];
1971 u8 chiper[RTW89_MAX_SUPPORT_NL_NUM];
1972 u8 rsvd3[24];
1973 u8 ssid[RTW89_MAX_SUPPORT_NL_NUM][IEEE80211_MAX_SSID_LEN];
1974 } __packed;
1975
1976 #define RTW89_H2C_NLO_W0_ENABLE BIT(0)
1977 #define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)
1978 #define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)
1979
RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void * h2c,u32 val)1980 static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)
1981 {
1982 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
1983 }
1984
RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void * h2c,u32 val)1985 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)
1986 {
1987 le32p_replace_bits((__le32 *)h2c, val, BIT(1));
1988 }
1989
RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void * h2c,u32 val)1990 static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)
1991 {
1992 le32p_replace_bits((__le32 *)h2c, val, BIT(2));
1993 }
1994
RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void * h2c,u32 val)1995 static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)
1996 {
1997 le32p_replace_bits((__le32 *)h2c, val, BIT(3));
1998 }
1999
RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void * h2c,u32 val)2000 static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)
2001 {
2002 le32p_replace_bits((__le32 *)h2c, val, BIT(4));
2003 }
2004
RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void * h2c,u32 val)2005 static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)
2006 {
2007 le32p_replace_bits((__le32 *)h2c, val, BIT(5));
2008 }
2009
RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void * h2c,u32 val)2010 static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)
2011 {
2012 le32p_replace_bits((__le32 *)h2c, val, BIT(6));
2013 }
2014
RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void * h2c,u32 val)2015 static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)
2016 {
2017 le32p_replace_bits((__le32 *)h2c, val, BIT(7));
2018 }
2019
RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void * h2c,u32 val)2020 static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)
2021 {
2022 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24));
2023 }
2024
RTW89_SET_WOW_CAM_UPD_R_W(void * h2c,u32 val)2025 static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)
2026 {
2027 le32p_replace_bits((__le32 *)h2c, val, BIT(0));
2028 }
2029
RTW89_SET_WOW_CAM_UPD_IDX(void * h2c,u32 val)2030 static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)
2031 {
2032 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 1));
2033 }
2034
RTW89_SET_WOW_CAM_UPD_WKFM1(void * h2c,u32 val)2035 static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)
2036 {
2037 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 0));
2038 }
2039
RTW89_SET_WOW_CAM_UPD_WKFM2(void * h2c,u32 val)2040 static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)
2041 {
2042 le32p_replace_bits((__le32 *)h2c + 2, val, GENMASK(31, 0));
2043 }
2044
RTW89_SET_WOW_CAM_UPD_WKFM3(void * h2c,u32 val)2045 static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
2046 {
2047 le32p_replace_bits((__le32 *)h2c + 3, val, GENMASK(31, 0));
2048 }
2049
RTW89_SET_WOW_CAM_UPD_WKFM4(void * h2c,u32 val)2050 static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val)
2051 {
2052 le32p_replace_bits((__le32 *)h2c + 4, val, GENMASK(31, 0));
2053 }
2054
RTW89_SET_WOW_CAM_UPD_CRC(void * h2c,u32 val)2055 static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val)
2056 {
2057 le32p_replace_bits((__le32 *)h2c + 5, val, GENMASK(15, 0));
2058 }
2059
RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void * h2c,u32 val)2060 static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val)
2061 {
2062 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(22));
2063 }
2064
RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void * h2c,u32 val)2065 static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val)
2066 {
2067 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(23));
2068 }
2069
RTW89_SET_WOW_CAM_UPD_UC(void * h2c,u32 val)2070 static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val)
2071 {
2072 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(24));
2073 }
2074
RTW89_SET_WOW_CAM_UPD_MC(void * h2c,u32 val)2075 static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val)
2076 {
2077 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(25));
2078 }
2079
RTW89_SET_WOW_CAM_UPD_BC(void * h2c,u32 val)2080 static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val)
2081 {
2082 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(26));
2083 }
2084
RTW89_SET_WOW_CAM_UPD_VALID(void * h2c,u32 val)2085 static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val)
2086 {
2087 le32p_replace_bits((__le32 *)h2c + 5, val, BIT(31));
2088 }
2089
2090 struct rtw89_h2c_wow_gtk_ofld {
2091 __le32 w0;
2092 __le32 w1;
2093 struct rtw89_wow_gtk_info gtk_info;
2094 } __packed;
2095
2096 #define RTW89_H2C_WOW_GTK_OFLD_W0_EN BIT(0)
2097 #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN BIT(1)
2098 #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN BIT(2)
2099 #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP BIT(3)
2100 #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP BIT(4)
2101 #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID GENMASK(23, 16)
2102 #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID GENMASK(31, 24)
2103 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID GENMASK(7, 0)
2104 #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO GENMASK(9, 8)
2105 #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT GENMASK(17, 10)
2106
2107 struct rtw89_h2c_arp_offload {
2108 __le32 w0;
2109 __le32 w1;
2110 } __packed;
2111
2112 #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE BIT(0)
2113 #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION BIT(1)
2114 #define RTW89_H2C_ARP_OFFLOAD_W0_MACID GENMASK(23, 16)
2115 #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID GENMASK(31, 24)
2116 #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT GENMASK(31, 0)
2117
2118 enum rtw89_btc_btf_h2c_class {
2119 BTFC_SET = 0x10,
2120 BTFC_GET = 0x11,
2121 BTFC_FW_EVENT = 0x12,
2122 };
2123
2124 enum rtw89_btc_btf_set {
2125 SET_REPORT_EN = 0x0,
2126 SET_SLOT_TABLE,
2127 SET_MREG_TABLE,
2128 SET_CX_POLICY,
2129 SET_GPIO_DBG,
2130 SET_DRV_INFO,
2131 SET_DRV_EVENT,
2132 SET_BT_WREG_ADDR,
2133 SET_BT_WREG_VAL,
2134 SET_BT_RREG_ADDR,
2135 SET_BT_WL_CH_INFO,
2136 SET_BT_INFO_REPORT,
2137 SET_BT_IGNORE_WLAN_ACT,
2138 SET_BT_TX_PWR,
2139 SET_BT_LNA_CONSTRAIN,
2140 SET_BT_QUERY_DEV_LIST,
2141 SET_BT_QUERY_DEV_INFO,
2142 SET_BT_PSD_REPORT,
2143 SET_H2C_TEST,
2144 SET_IOFLD_RF,
2145 SET_IOFLD_BB,
2146 SET_IOFLD_MAC,
2147 SET_IOFLD_SCBD,
2148 SET_H2C_MACRO,
2149 SET_MAX1,
2150 };
2151
2152 enum rtw89_btc_cxdrvinfo {
2153 CXDRVINFO_INIT = 0,
2154 CXDRVINFO_ROLE,
2155 CXDRVINFO_DBCC,
2156 CXDRVINFO_SMAP,
2157 CXDRVINFO_RFK,
2158 CXDRVINFO_RUN,
2159 CXDRVINFO_CTRL,
2160 CXDRVINFO_SCAN,
2161 CXDRVINFO_TRX, /* WL traffic to WL fw */
2162 CXDRVINFO_TXPWR,
2163 CXDRVINFO_FDDT,
2164 CXDRVINFO_MLO,
2165 CXDRVINFO_OSI,
2166 CXDRVINFO_MAX,
2167 };
2168
2169 enum rtw89_scan_mode {
2170 RTW89_SCAN_IMMEDIATE,
2171 RTW89_SCAN_DELAY,
2172 };
2173
2174 enum rtw89_scan_type {
2175 RTW89_SCAN_ONCE,
2176 RTW89_SCAN_NORMAL,
2177 RTW89_SCAN_NORMAL_SLOW,
2178 RTW89_SCAN_SEAMLESS,
2179 RTW89_SCAN_MAX,
2180 };
2181
RTW89_SET_FWCMD_CXHDR_TYPE(void * cmd,u8 val)2182 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val)
2183 {
2184 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0));
2185 }
2186
RTW89_SET_FWCMD_CXHDR_LEN(void * cmd,u8 val)2187 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val)
2188 {
2189 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0));
2190 }
2191
2192 struct rtw89_h2c_cxhdr {
2193 u8 type;
2194 u8 len;
2195 } __packed;
2196
2197 struct rtw89_h2c_cxhdr_v7 {
2198 u8 type;
2199 u8 ver;
2200 u8 len;
2201 } __packed;
2202
2203 struct rtw89_h2c_cxctrl_v7 {
2204 struct rtw89_h2c_cxhdr_v7 hdr;
2205 struct rtw89_btc_ctrl_v7 ctrl;
2206 } __packed;
2207
2208 #define H2C_LEN_CXDRVHDR sizeof(struct rtw89_h2c_cxhdr)
2209 #define H2C_LEN_CXDRVHDR_V7 sizeof(struct rtw89_h2c_cxhdr_v7)
2210
2211 struct rtw89_btc_wl_role_info_v7_u8 {
2212 u8 connect_cnt;
2213 u8 link_mode;
2214 u8 link_mode_chg;
2215 u8 p2p_2g;
2216
2217 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
2218 } __packed;
2219
2220 struct rtw89_btc_wl_role_info_v7_u32 {
2221 __le32 role_map;
2222 __le32 mrole_type;
2223 __le32 mrole_noa_duration;
2224 __le32 dbcc_en;
2225 __le32 dbcc_chg;
2226 __le32 dbcc_2g_phy;
2227 } __packed;
2228
2229 struct rtw89_h2c_cxrole_v7 {
2230 struct rtw89_h2c_cxhdr_v7 hdr;
2231 struct rtw89_btc_wl_role_info_v7_u8 _u8;
2232 struct rtw89_btc_wl_role_info_v7_u32 _u32;
2233 } __packed;
2234
2235 struct rtw89_btc_wl_role_info_v8_u8 {
2236 u8 connect_cnt;
2237 u8 link_mode;
2238 u8 link_mode_chg;
2239 u8 p2p_2g;
2240
2241 u8 pta_req_band;
2242 u8 dbcc_en;
2243 u8 dbcc_chg;
2244 u8 dbcc_2g_phy;
2245
2246 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
2247 } __packed;
2248
2249 struct rtw89_btc_wl_role_info_v8_u32 {
2250 __le32 role_map;
2251 __le32 mrole_type;
2252 __le32 mrole_noa_duration;
2253 } __packed;
2254
2255 struct rtw89_h2c_cxrole_v8 {
2256 struct rtw89_h2c_cxhdr_v7 hdr;
2257 struct rtw89_btc_wl_role_info_v8_u8 _u8;
2258 struct rtw89_btc_wl_role_info_v8_u32 _u32;
2259 } __packed;
2260
2261 struct rtw89_h2c_cxosi {
2262 struct rtw89_h2c_cxhdr_v7 hdr;
2263 struct rtw89_btc_fbtc_outsrc_set_info osi;
2264 } __packed;
2265
2266 struct rtw89_h2c_cxinit {
2267 struct rtw89_h2c_cxhdr hdr;
2268 u8 ant_type;
2269 u8 ant_num;
2270 u8 ant_iso;
2271 u8 ant_info;
2272 u8 mod_rfe;
2273 u8 mod_cv;
2274 u8 mod_info;
2275 u8 mod_adie_kt;
2276 u8 wl_gch;
2277 u8 info;
2278 u8 rsvd;
2279 u8 rsvd1;
2280 } __packed;
2281
2282 #define RTW89_H2C_CXINIT_ANT_INFO_POS BIT(0)
2283 #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY BIT(1)
2284 #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS GENMASK(3, 2)
2285 #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT GENMASK(7, 4)
2286
2287 #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO BIT(0)
2288 #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS BIT(1)
2289 #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE BIT(2)
2290 #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE GENMASK(5, 3)
2291
2292 #define RTW89_H2C_CXINIT_INFO_WL_ONLY BIT(0)
2293 #define RTW89_H2C_CXINIT_INFO_WL_INITOK BIT(1)
2294 #define RTW89_H2C_CXINIT_INFO_DBCC_EN BIT(2)
2295 #define RTW89_H2C_CXINIT_INFO_CX_OTHER BIT(3)
2296 #define RTW89_H2C_CXINIT_INFO_BT_ONLY BIT(4)
2297
2298 struct rtw89_h2c_cxinit_v7 {
2299 struct rtw89_h2c_cxhdr_v7 hdr;
2300 struct rtw89_btc_init_info_v7 init;
2301 } __packed;
2302
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void * cmd,u8 val)2303 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val)
2304 {
2305 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0));
2306 }
2307
RTW89_SET_FWCMD_CXROLE_LINK_MODE(void * cmd,u8 val)2308 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val)
2309 {
2310 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0));
2311 }
2312
RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void * cmd,u16 val)2313 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val)
2314 {
2315 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0));
2316 }
2317
RTW89_SET_FWCMD_CXROLE_ROLE_STA(void * cmd,u16 val)2318 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val)
2319 {
2320 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1));
2321 }
2322
RTW89_SET_FWCMD_CXROLE_ROLE_AP(void * cmd,u16 val)2323 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val)
2324 {
2325 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2));
2326 }
2327
RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void * cmd,u16 val)2328 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val)
2329 {
2330 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3));
2331 }
2332
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void * cmd,u16 val)2333 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val)
2334 {
2335 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4));
2336 }
2337
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void * cmd,u16 val)2338 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val)
2339 {
2340 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5));
2341 }
2342
RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void * cmd,u16 val)2343 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val)
2344 {
2345 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6));
2346 }
2347
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void * cmd,u16 val)2348 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val)
2349 {
2350 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7));
2351 }
2352
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void * cmd,u16 val)2353 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val)
2354 {
2355 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8));
2356 }
2357
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void * cmd,u16 val)2358 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val)
2359 {
2360 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9));
2361 }
2362
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void * cmd,u16 val)2363 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val)
2364 {
2365 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10));
2366 }
2367
RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void * cmd,u16 val)2368 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val)
2369 {
2370 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11));
2371 }
2372
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void * cmd,u8 val,int n,u8 offset)2373 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset)
2374 {
2375 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2376 }
2377
RTW89_SET_FWCMD_CXROLE_ACT_PID(void * cmd,u8 val,int n,u8 offset)2378 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset)
2379 {
2380 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2381 }
2382
RTW89_SET_FWCMD_CXROLE_ACT_PHY(void * cmd,u8 val,int n,u8 offset)2383 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset)
2384 {
2385 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2386 }
2387
RTW89_SET_FWCMD_CXROLE_ACT_NOA(void * cmd,u8 val,int n,u8 offset)2388 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset)
2389 {
2390 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2391 }
2392
RTW89_SET_FWCMD_CXROLE_ACT_BAND(void * cmd,u8 val,int n,u8 offset)2393 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset)
2394 {
2395 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2396 }
2397
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void * cmd,u8 val,int n,u8 offset)2398 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset)
2399 {
2400 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2401 }
2402
RTW89_SET_FWCMD_CXROLE_ACT_BW(void * cmd,u8 val,int n,u8 offset)2403 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset)
2404 {
2405 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2406 }
2407
RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void * cmd,u8 val,int n,u8 offset)2408 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset)
2409 {
2410 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2411 }
2412
RTW89_SET_FWCMD_CXROLE_ACT_CH(void * cmd,u8 val,int n,u8 offset)2413 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset)
2414 {
2415 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2416 }
2417
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void * cmd,u16 val,int n,u8 offset)2418 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset)
2419 {
2420 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0));
2421 }
2422
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void * cmd,u16 val,int n,u8 offset)2423 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset)
2424 {
2425 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0));
2426 }
2427
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void * cmd,u16 val,int n,u8 offset)2428 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset)
2429 {
2430 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0));
2431 }
2432
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void * cmd,u16 val,int n,u8 offset)2433 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset)
2434 {
2435 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0));
2436 }
2437
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void * cmd,u32 val,int n,u8 offset)2438 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset)
2439 {
2440 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0));
2441 }
2442
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void * cmd,u8 val,int n,u8 offset)2443 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset)
2444 {
2445 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0));
2446 }
2447
RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void * cmd,u8 val,int n,u8 offset)2448 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset)
2449 {
2450 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1));
2451 }
2452
RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void * cmd,u8 val,int n,u8 offset)2453 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset)
2454 {
2455 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4));
2456 }
2457
RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void * cmd,u8 val,int n,u8 offset)2458 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset)
2459 {
2460 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5));
2461 }
2462
RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void * cmd,u8 val,int n,u8 offset)2463 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset)
2464 {
2465 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6));
2466 }
2467
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void * cmd,u8 val,int n,u8 offset)2468 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset)
2469 {
2470 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0));
2471 }
2472
RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void * cmd,u8 val,int n,u8 offset)2473 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset)
2474 {
2475 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1));
2476 }
2477
RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void * cmd,u8 val,int n,u8 offset)2478 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset)
2479 {
2480 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0));
2481 }
2482
RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void * cmd,u8 val,int n,u8 offset)2483 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset)
2484 {
2485 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0));
2486 }
2487
RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void * cmd,u32 val,int n,u8 offset)2488 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset)
2489 {
2490 le32p_replace_bits((__le32 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(31, 0));
2491 }
2492
RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void * cmd,u32 val,u8 offset)2493 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset)
2494 {
2495 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0));
2496 }
2497
RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void * cmd,u32 val,u8 offset)2498 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset)
2499 {
2500 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0));
2501 }
2502
RTW89_SET_FWCMD_CXROLE_DBCC_EN(void * cmd,u32 val,u8 offset)2503 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset)
2504 {
2505 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0));
2506 }
2507
RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void * cmd,u32 val,u8 offset)2508 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset)
2509 {
2510 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1));
2511 }
2512
RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void * cmd,u32 val,u8 offset)2513 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset)
2514 {
2515 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2));
2516 }
2517
RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void * cmd,u32 val,u8 offset)2518 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset)
2519 {
2520 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4));
2521 }
2522
RTW89_SET_FWCMD_CXCTRL_MANUAL(void * cmd,u32 val)2523 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val)
2524 {
2525 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0));
2526 }
2527
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void * cmd,u32 val)2528 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val)
2529 {
2530 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1));
2531 }
2532
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void * cmd,u32 val)2533 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val)
2534 {
2535 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2));
2536 }
2537
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void * cmd,u32 val)2538 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val)
2539 {
2540 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3));
2541 }
2542
RTW89_SET_FWCMD_CXTRX_TXLV(void * cmd,u8 val)2543 static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val)
2544 {
2545 u8p_replace_bits((u8 *)cmd + 2, val, GENMASK(7, 0));
2546 }
2547
RTW89_SET_FWCMD_CXTRX_RXLV(void * cmd,u8 val)2548 static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val)
2549 {
2550 u8p_replace_bits((u8 *)cmd + 3, val, GENMASK(7, 0));
2551 }
2552
RTW89_SET_FWCMD_CXTRX_WLRSSI(void * cmd,u8 val)2553 static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val)
2554 {
2555 u8p_replace_bits((u8 *)cmd + 4, val, GENMASK(7, 0));
2556 }
2557
RTW89_SET_FWCMD_CXTRX_BTRSSI(void * cmd,u8 val)2558 static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val)
2559 {
2560 u8p_replace_bits((u8 *)cmd + 5, val, GENMASK(7, 0));
2561 }
2562
RTW89_SET_FWCMD_CXTRX_TXPWR(void * cmd,s8 val)2563 static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val)
2564 {
2565 u8p_replace_bits((u8 *)cmd + 6, val, GENMASK(7, 0));
2566 }
2567
RTW89_SET_FWCMD_CXTRX_RXGAIN(void * cmd,s8 val)2568 static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val)
2569 {
2570 u8p_replace_bits((u8 *)cmd + 7, val, GENMASK(7, 0));
2571 }
2572
RTW89_SET_FWCMD_CXTRX_BTTXPWR(void * cmd,s8 val)2573 static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val)
2574 {
2575 u8p_replace_bits((u8 *)cmd + 8, val, GENMASK(7, 0));
2576 }
2577
RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void * cmd,s8 val)2578 static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val)
2579 {
2580 u8p_replace_bits((u8 *)cmd + 9, val, GENMASK(7, 0));
2581 }
2582
RTW89_SET_FWCMD_CXTRX_CN(void * cmd,u8 val)2583 static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val)
2584 {
2585 u8p_replace_bits((u8 *)cmd + 10, val, GENMASK(7, 0));
2586 }
2587
RTW89_SET_FWCMD_CXTRX_NHM(void * cmd,s8 val)2588 static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val)
2589 {
2590 u8p_replace_bits((u8 *)cmd + 11, val, GENMASK(7, 0));
2591 }
2592
RTW89_SET_FWCMD_CXTRX_BTPROFILE(void * cmd,u8 val)2593 static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val)
2594 {
2595 u8p_replace_bits((u8 *)cmd + 12, val, GENMASK(7, 0));
2596 }
2597
RTW89_SET_FWCMD_CXTRX_RSVD2(void * cmd,u8 val)2598 static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val)
2599 {
2600 u8p_replace_bits((u8 *)cmd + 13, val, GENMASK(7, 0));
2601 }
2602
RTW89_SET_FWCMD_CXTRX_TXRATE(void * cmd,u16 val)2603 static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val)
2604 {
2605 le16p_replace_bits((__le16 *)((u8 *)cmd + 14), val, GENMASK(15, 0));
2606 }
2607
RTW89_SET_FWCMD_CXTRX_RXRATE(void * cmd,u16 val)2608 static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val)
2609 {
2610 le16p_replace_bits((__le16 *)((u8 *)cmd + 16), val, GENMASK(15, 0));
2611 }
2612
RTW89_SET_FWCMD_CXTRX_TXTP(void * cmd,u32 val)2613 static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val)
2614 {
2615 le32p_replace_bits((__le32 *)((u8 *)cmd + 18), val, GENMASK(31, 0));
2616 }
2617
RTW89_SET_FWCMD_CXTRX_RXTP(void * cmd,u32 val)2618 static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val)
2619 {
2620 le32p_replace_bits((__le32 *)((u8 *)cmd + 22), val, GENMASK(31, 0));
2621 }
2622
RTW89_SET_FWCMD_CXTRX_RXERRRA(void * cmd,u32 val)2623 static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val)
2624 {
2625 le32p_replace_bits((__le32 *)((u8 *)cmd + 26), val, GENMASK(31, 0));
2626 }
2627
RTW89_SET_FWCMD_CXRFK_STATE(void * cmd,u32 val)2628 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val)
2629 {
2630 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0));
2631 }
2632
RTW89_SET_FWCMD_CXRFK_PATH_MAP(void * cmd,u32 val)2633 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val)
2634 {
2635 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2));
2636 }
2637
RTW89_SET_FWCMD_CXRFK_PHY_MAP(void * cmd,u32 val)2638 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val)
2639 {
2640 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6));
2641 }
2642
RTW89_SET_FWCMD_CXRFK_BAND(void * cmd,u32 val)2643 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val)
2644 {
2645 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8));
2646 }
2647
RTW89_SET_FWCMD_CXRFK_TYPE(void * cmd,u32 val)2648 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val)
2649 {
2650 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10));
2651 }
2652
RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void * cmd,u32 val)2653 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val)
2654 {
2655 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0));
2656 }
2657
RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void * cmd,u32 val)2658 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val)
2659 {
2660 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8));
2661 }
2662
RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void * cmd,u32 val)2663 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val)
2664 {
2665 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16));
2666 }
2667
2668 struct rtw89_h2c_chinfo_elem {
2669 __le32 w0;
2670 __le32 w1;
2671 __le32 w2;
2672 __le32 w3;
2673 __le32 w4;
2674 __le32 w5;
2675 __le32 w6;
2676 } __packed;
2677
2678 #define RTW89_H2C_CHINFO_W0_PERIOD GENMASK(7, 0)
2679 #define RTW89_H2C_CHINFO_W0_DWELL GENMASK(15, 8)
2680 #define RTW89_H2C_CHINFO_W0_CENTER_CH GENMASK(23, 16)
2681 #define RTW89_H2C_CHINFO_W0_PRI_CH GENMASK(31, 24)
2682 #define RTW89_H2C_CHINFO_W1_BW GENMASK(2, 0)
2683 #define RTW89_H2C_CHINFO_W1_ACTION GENMASK(7, 3)
2684 #define RTW89_H2C_CHINFO_W1_NUM_PKT GENMASK(11, 8)
2685 #define RTW89_H2C_CHINFO_W1_TX BIT(12)
2686 #define RTW89_H2C_CHINFO_W1_PAUSE_DATA BIT(13)
2687 #define RTW89_H2C_CHINFO_W1_BAND GENMASK(15, 14)
2688 #define RTW89_H2C_CHINFO_W1_PKT_ID GENMASK(23, 16)
2689 #define RTW89_H2C_CHINFO_W1_DFS BIT(24)
2690 #define RTW89_H2C_CHINFO_W1_TX_NULL BIT(25)
2691 #define RTW89_H2C_CHINFO_W1_RANDOM BIT(26)
2692 #define RTW89_H2C_CHINFO_W1_CFG_TX BIT(27)
2693 #define RTW89_H2C_CHINFO_W1_MACID_TX BIT(29)
2694 #define RTW89_H2C_CHINFO_W2_PKT0 GENMASK(7, 0)
2695 #define RTW89_H2C_CHINFO_W2_PKT1 GENMASK(15, 8)
2696 #define RTW89_H2C_CHINFO_W2_PKT2 GENMASK(23, 16)
2697 #define RTW89_H2C_CHINFO_W2_PKT3 GENMASK(31, 24)
2698 #define RTW89_H2C_CHINFO_W3_PKT4 GENMASK(7, 0)
2699 #define RTW89_H2C_CHINFO_W3_PKT5 GENMASK(15, 8)
2700 #define RTW89_H2C_CHINFO_W3_PKT6 GENMASK(23, 16)
2701 #define RTW89_H2C_CHINFO_W3_PKT7 GENMASK(31, 24)
2702 #define RTW89_H2C_CHINFO_W4_POWER_IDX GENMASK(15, 0)
2703
2704 struct rtw89_h2c_chinfo_elem_be {
2705 __le32 w0;
2706 __le32 w1;
2707 __le32 w2;
2708 __le32 w3;
2709 __le32 w4;
2710 __le32 w5;
2711 __le32 w6;
2712 __le32 w7;
2713 } __packed;
2714
2715 #define RTW89_H2C_CHINFO_BE_W0_PERIOD GENMASK(7, 0)
2716 #define RTW89_H2C_CHINFO_BE_W0_DWELL GENMASK(15, 8)
2717 #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH GENMASK(23, 16)
2718 #define RTW89_H2C_CHINFO_BE_W0_PRI_CH GENMASK(31, 24)
2719 #define RTW89_H2C_CHINFO_BE_W1_BW GENMASK(2, 0)
2720 #define RTW89_H2C_CHINFO_BE_W1_CH_BAND GENMASK(4, 3)
2721 #define RTW89_H2C_CHINFO_BE_W1_DFS BIT(5)
2722 #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA BIT(6)
2723 #define RTW89_H2C_CHINFO_BE_W1_TX_NULL BIT(7)
2724 #define RTW89_H2C_CHINFO_BE_W1_RANDOM BIT(8)
2725 #define RTW89_H2C_CHINFO_BE_W1_NOTIFY GENMASK(13, 9)
2726 #define RTW89_H2C_CHINFO_BE_W1_PROBE BIT(14)
2727 #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT GENMASK(17, 15)
2728 #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER GENMASK(31, 24)
2729 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME GENMASK(7, 0)
2730 #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH GENMASK(15, 8)
2731 #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL GENMASK(31, 16)
2732 #define RTW89_H2C_CHINFO_BE_W3_PKT0 GENMASK(7, 0)
2733 #define RTW89_H2C_CHINFO_BE_W3_PKT1 GENMASK(15, 8)
2734 #define RTW89_H2C_CHINFO_BE_W3_PKT2 GENMASK(23, 16)
2735 #define RTW89_H2C_CHINFO_BE_W3_PKT3 GENMASK(31, 24)
2736 #define RTW89_H2C_CHINFO_BE_W4_PKT4 GENMASK(7, 0)
2737 #define RTW89_H2C_CHINFO_BE_W4_PKT5 GENMASK(15, 8)
2738 #define RTW89_H2C_CHINFO_BE_W4_PKT6 GENMASK(23, 16)
2739 #define RTW89_H2C_CHINFO_BE_W4_PKT7 GENMASK(31, 24)
2740 #define RTW89_H2C_CHINFO_BE_W5_SW_DEF GENMASK(7, 0)
2741 #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS GENMASK(31, 16)
2742 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS GENMASK(15, 0)
2743 #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS GENMASK(31, 16)
2744 #define RTW89_H2C_CHINFO_BE_W7_PERIOD_V1 GENMASK(15, 0)
2745
2746 struct rtw89_h2c_chinfo {
2747 u8 ch_num;
2748 u8 elem_size;
2749 u8 arg;
2750 u8 rsvd0;
2751 struct rtw89_h2c_chinfo_elem elem[] __counted_by(ch_num);
2752 } __packed;
2753
2754 struct rtw89_h2c_chinfo_be {
2755 u8 ch_num;
2756 u8 elem_size;
2757 u8 arg;
2758 u8 rsvd0;
2759 struct rtw89_h2c_chinfo_elem_be elem[] __counted_by(ch_num);
2760 } __packed;
2761
2762 #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK BIT(0)
2763 #define RTW89_H2C_CHINFO_ARG_APPEND_MASK BIT(1)
2764
2765 struct rtw89_h2c_scanofld {
2766 __le32 w0;
2767 __le32 w1;
2768 __le32 w2;
2769 __le32 tsf_high;
2770 __le32 tsf_low;
2771 __le32 w5;
2772 __le32 w6;
2773 } __packed;
2774
2775 #define RTW89_H2C_SCANOFLD_W0_MACID GENMASK(7, 0)
2776 #define RTW89_H2C_SCANOFLD_W0_NORM_CY GENMASK(15, 8)
2777 #define RTW89_H2C_SCANOFLD_W0_PORT_ID GENMASK(18, 16)
2778 #define RTW89_H2C_SCANOFLD_W0_BAND BIT(19)
2779 #define RTW89_H2C_SCANOFLD_W0_OPERATION GENMASK(21, 20)
2780 #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND GENMASK(23, 22)
2781 #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END BIT(0)
2782 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE BIT(1)
2783 #define RTW89_H2C_SCANOFLD_W1_START_MODE BIT(2)
2784 #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE GENMASK(4, 3)
2785 #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW GENMASK(7, 5)
2786 #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH GENMASK(15, 8)
2787 #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH GENMASK(23, 16)
2788 #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID GENMASK(31, 24)
2789 #define RTW89_H2C_SCANOFLD_W2_NORM_PD GENMASK(15, 0)
2790 #define RTW89_H2C_SCANOFLD_W2_SLOW_PD GENMASK(23, 16)
2791 #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH GENMASK(31, 0)
2792 #define RTW89_H2C_SCANOFLD_W4_TSF_LOW GENMASK(31, 0)
2793 #define RTW89_H2C_SCANOFLD_W6_SECOND_MACID GENMASK(31, 24)
2794
2795 struct rtw89_h2c_scanofld_be_macc_role {
2796 __le32 w0;
2797 } __packed;
2798
2799 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND GENMASK(1, 0)
2800 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT GENMASK(4, 2)
2801 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID GENMASK(23, 8)
2802 #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END GENMASK(31, 24)
2803
2804 struct rtw89_h2c_scanofld_be_opch {
2805 __le32 w0;
2806 __le32 w1;
2807 __le32 w2;
2808 __le32 w3;
2809 __le32 w4;
2810 } __packed;
2811
2812 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID GENMASK(15, 0)
2813 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND GENMASK(17, 16)
2814 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT GENMASK(20, 18)
2815 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY GENMASK(22, 21)
2816 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL BIT(23)
2817 #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL GENMASK(31, 24)
2818 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION GENMASK(7, 0)
2819 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND GENMASK(9, 8)
2820 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW GENMASK(12, 10)
2821 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY GENMASK(14, 13)
2822 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH GENMASK(23, 16)
2823 #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH GENMASK(31, 24)
2824 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL GENMASK(7, 0)
2825 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF GENMASK(15, 8)
2826 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS GENMASK(18, 16)
2827 #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_TXBCN BIT(19)
2828 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 GENMASK(7, 0)
2829 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 GENMASK(15, 8)
2830 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 GENMASK(23, 16)
2831 #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 GENMASK(31, 24)
2832 #define RTW89_H2C_SCANOFLD_BE_OPCH_W4_DURATION_V1 GENMASK(15, 0)
2833
2834 struct rtw89_h2c_scanofld_be {
2835 __le32 w0;
2836 __le32 w1;
2837 __le32 w2;
2838 __le32 w3;
2839 __le32 w4;
2840 __le32 w5;
2841 __le32 w6;
2842 __le32 w7;
2843 __le32 w8;
2844 __le32 w9; /* Added after SCAN_OFFLOAD_BE_V1 */
2845 /* struct rtw89_h2c_scanofld_be_macc_role (flexible number) */
2846 /* struct rtw89_h2c_scanofld_be_opch (flexible number) */
2847 } __packed;
2848
2849 #define RTW89_H2C_SCANOFLD_BE_W0_OP GENMASK(1, 0)
2850 #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE GENMASK(3, 2)
2851 #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT GENMASK(5, 4)
2852 #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END BIT(6)
2853 #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH BIT(7)
2854 #define RTW89_H2C_SCANOFLD_BE_W0_MACID GENMASK(23, 8)
2855 #define RTW89_H2C_SCANOFLD_BE_W0_PORT GENMASK(26, 24)
2856 #define RTW89_H2C_SCANOFLD_BE_W0_BAND GENMASK(28, 27)
2857 #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE BIT(29)
2858 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE GENMASK(7, 0)
2859 #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP GENMASK(15, 8)
2860 #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD GENMASK(31, 16)
2861 #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD GENMASK(15, 0)
2862 #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY GENMASK(23, 16)
2863 #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END GENMASK(31, 24)
2864 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID GENMASK(7, 0)
2865 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID GENMASK(15, 8)
2866 #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID GENMASK(23, 16)
2867 #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID GENMASK(31, 24)
2868 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G GENMASK(7, 0)
2869 #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G GENMASK(15, 8)
2870 #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START GENMASK(31, 16)
2871 #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE GENMASK(31, 0)
2872 #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW GENMASK(31, 0)
2873 #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH GENMASK(31, 0)
2874 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ GENMASK(7, 0)
2875 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ GENMASK(15, 8)
2876 #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ GENMASK(23, 16)
2877 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG GENMASK(7, 0)
2878 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC GENMASK(15, 8)
2879 #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP GENMASK(23, 16)
2880
2881 struct rtw89_h2c_fwips {
2882 __le32 w0;
2883 } __packed;
2884
2885 #define RTW89_H2C_FW_IPS_W0_MACID GENMASK(7, 0)
2886 #define RTW89_H2C_FW_IPS_W0_ENABLE BIT(8)
2887
2888 struct rtw89_h2c_mlo_link_cfg {
2889 __le32 w0;
2890 };
2891
2892 #define RTW89_H2C_MLO_LINK_CFG_W0_MACID GENMASK(15, 0)
2893 #define RTW89_H2C_MLO_LINK_CFG_W0_OPTION GENMASK(19, 16)
2894
RTW89_SET_FWCMD_P2P_MACID(void * cmd,u32 val)2895 static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val)
2896 {
2897 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
2898 }
2899
RTW89_SET_FWCMD_P2P_P2PID(void * cmd,u32 val)2900 static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val)
2901 {
2902 le32p_replace_bits((__le32 *)cmd, val, GENMASK(11, 8));
2903 }
2904
RTW89_SET_FWCMD_P2P_NOAID(void * cmd,u32 val)2905 static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val)
2906 {
2907 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 12));
2908 }
2909
RTW89_SET_FWCMD_P2P_ACT(void * cmd,u32 val)2910 static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val)
2911 {
2912 le32p_replace_bits((__le32 *)cmd, val, GENMASK(19, 16));
2913 }
2914
RTW89_SET_FWCMD_P2P_TYPE(void * cmd,u32 val)2915 static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val)
2916 {
2917 le32p_replace_bits((__le32 *)cmd, val, BIT(20));
2918 }
2919
RTW89_SET_FWCMD_P2P_ALL_SLEP(void * cmd,u32 val)2920 static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val)
2921 {
2922 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
2923 }
2924
RTW89_SET_FWCMD_NOA_START_TIME(void * cmd,__le32 val)2925 static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val)
2926 {
2927 *((__le32 *)cmd + 1) = val;
2928 }
2929
RTW89_SET_FWCMD_NOA_INTERVAL(void * cmd,__le32 val)2930 static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val)
2931 {
2932 *((__le32 *)cmd + 2) = val;
2933 }
2934
RTW89_SET_FWCMD_NOA_DURATION(void * cmd,__le32 val)2935 static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val)
2936 {
2937 *((__le32 *)cmd + 3) = val;
2938 }
2939
RTW89_SET_FWCMD_NOA_COUNT(void * cmd,u32 val)2940 static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val)
2941 {
2942 le32p_replace_bits((__le32 *)(cmd) + 4, val, GENMASK(7, 0));
2943 }
2944
RTW89_SET_FWCMD_NOA_CTWINDOW(void * cmd,u32 val)2945 static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val)
2946 {
2947 u8 ctwnd;
2948
2949 if (!(val & IEEE80211_P2P_OPPPS_ENABLE_BIT))
2950 return;
2951 ctwnd = FIELD_GET(IEEE80211_P2P_OPPPS_CTWINDOW_MASK, val);
2952 le32p_replace_bits((__le32 *)(cmd) + 4, ctwnd, GENMASK(23, 8));
2953 }
2954
RTW89_SET_FWCMD_TSF32_TOGL_BAND(void * cmd,u32 val)2955 static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val)
2956 {
2957 le32p_replace_bits((__le32 *)cmd, val, BIT(0));
2958 }
2959
RTW89_SET_FWCMD_TSF32_TOGL_EN(void * cmd,u32 val)2960 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val)
2961 {
2962 le32p_replace_bits((__le32 *)cmd, val, BIT(1));
2963 }
2964
RTW89_SET_FWCMD_TSF32_TOGL_PORT(void * cmd,u32 val)2965 static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val)
2966 {
2967 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 2));
2968 }
2969
RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void * cmd,u32 val)2970 static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val)
2971 {
2972 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 16));
2973 }
2974
2975 enum rtw89_fw_mcc_c2h_rpt_cfg {
2976 RTW89_FW_MCC_C2H_RPT_OFF = 0,
2977 RTW89_FW_MCC_C2H_RPT_FAIL_ONLY = 1,
2978 RTW89_FW_MCC_C2H_RPT_ALL = 2,
2979 };
2980
2981 struct rtw89_fw_mcc_add_req {
2982 u8 macid;
2983 u8 central_ch_seg0;
2984 u8 central_ch_seg1;
2985 u8 primary_ch;
2986 enum rtw89_bandwidth bandwidth: 4;
2987 u32 group: 2;
2988 u32 c2h_rpt: 2;
2989 u32 dis_tx_null: 1;
2990 u32 dis_sw_retry: 1;
2991 u32 in_curr_ch: 1;
2992 u32 sw_retry_count: 3;
2993 u32 tx_null_early: 4;
2994 u32 btc_in_2g: 1;
2995 u32 pta_en: 1;
2996 u32 rfk_by_pass: 1;
2997 u32 ch_band_type: 2;
2998 u32 rsvd0: 9;
2999 u32 duration;
3000 u8 courtesy_en;
3001 u8 courtesy_num;
3002 u8 courtesy_target;
3003 u8 rsvd1;
3004 };
3005
RTW89_SET_FWCMD_ADD_MCC_MACID(void * cmd,u32 val)3006 static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val)
3007 {
3008 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3009 }
3010
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void * cmd,u32 val)3011 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val)
3012 {
3013 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3014 }
3015
RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void * cmd,u32 val)3016 static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val)
3017 {
3018 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3019 }
3020
RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void * cmd,u32 val)3021 static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val)
3022 {
3023 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3024 }
3025
RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void * cmd,u32 val)3026 static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val)
3027 {
3028 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(3, 0));
3029 }
3030
RTW89_SET_FWCMD_ADD_MCC_GROUP(void * cmd,u32 val)3031 static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val)
3032 {
3033 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(5, 4));
3034 }
3035
RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void * cmd,u32 val)3036 static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val)
3037 {
3038 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(7, 6));
3039 }
3040
RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void * cmd,u32 val)3041 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val)
3042 {
3043 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(8));
3044 }
3045
RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void * cmd,u32 val)3046 static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val)
3047 {
3048 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(9));
3049 }
3050
RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void * cmd,u32 val)3051 static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val)
3052 {
3053 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(10));
3054 }
3055
RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void * cmd,u32 val)3056 static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val)
3057 {
3058 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(13, 11));
3059 }
3060
RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void * cmd,u32 val)3061 static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val)
3062 {
3063 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(17, 14));
3064 }
3065
RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void * cmd,u32 val)3066 static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val)
3067 {
3068 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(18));
3069 }
3070
RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void * cmd,u32 val)3071 static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val)
3072 {
3073 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(19));
3074 }
3075
RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void * cmd,u32 val)3076 static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val)
3077 {
3078 le32p_replace_bits((__le32 *)cmd + 1, val, BIT(20));
3079 }
3080
RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void * cmd,u32 val)3081 static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val)
3082 {
3083 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(22, 21));
3084 }
3085
RTW89_SET_FWCMD_ADD_MCC_DURATION(void * cmd,u32 val)3086 static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val)
3087 {
3088 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3089 }
3090
RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void * cmd,u32 val)3091 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val)
3092 {
3093 le32p_replace_bits((__le32 *)cmd + 3, val, BIT(0));
3094 }
3095
RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void * cmd,u32 val)3096 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val)
3097 {
3098 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(15, 8));
3099 }
3100
RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void * cmd,u32 val)3101 static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val)
3102 {
3103 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(23, 16));
3104 }
3105
3106 enum rtw89_fw_mcc_old_group_actions {
3107 RTW89_FW_MCC_OLD_GROUP_ACT_NONE = 0,
3108 RTW89_FW_MCC_OLD_GROUP_ACT_REPLACE = 1,
3109 };
3110
3111 struct rtw89_fw_mcc_start_req {
3112 u32 group: 2;
3113 u32 btc_in_group: 1;
3114 u32 old_group_action: 2;
3115 u32 old_group: 2;
3116 u32 rsvd0: 9;
3117 u32 notify_cnt: 3;
3118 u32 rsvd1: 2;
3119 u32 notify_rxdbg_en: 1;
3120 u32 rsvd2: 2;
3121 u32 macid: 8;
3122 u32 tsf_low;
3123 u32 tsf_high;
3124 };
3125
RTW89_SET_FWCMD_START_MCC_GROUP(void * cmd,u32 val)3126 static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val)
3127 {
3128 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3129 }
3130
RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void * cmd,u32 val)3131 static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val)
3132 {
3133 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3134 }
3135
RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void * cmd,u32 val)3136 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val)
3137 {
3138 le32p_replace_bits((__le32 *)cmd, val, GENMASK(4, 3));
3139 }
3140
RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void * cmd,u32 val)3141 static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val)
3142 {
3143 le32p_replace_bits((__le32 *)cmd, val, GENMASK(6, 5));
3144 }
3145
RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void * cmd,u32 val)3146 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val)
3147 {
3148 le32p_replace_bits((__le32 *)cmd, val, GENMASK(18, 16));
3149 }
3150
RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void * cmd,u32 val)3151 static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val)
3152 {
3153 le32p_replace_bits((__le32 *)cmd, val, BIT(21));
3154 }
3155
RTW89_SET_FWCMD_START_MCC_MACID(void * cmd,u32 val)3156 static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val)
3157 {
3158 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3159 }
3160
RTW89_SET_FWCMD_START_MCC_TSF_LOW(void * cmd,u32 val)3161 static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val)
3162 {
3163 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3164 }
3165
RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void * cmd,u32 val)3166 static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val)
3167 {
3168 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3169 }
3170
RTW89_SET_FWCMD_STOP_MCC_MACID(void * cmd,u32 val)3171 static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val)
3172 {
3173 le32p_replace_bits((__le32 *)cmd, val, GENMASK(7, 0));
3174 }
3175
RTW89_SET_FWCMD_STOP_MCC_GROUP(void * cmd,u32 val)3176 static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val)
3177 {
3178 le32p_replace_bits((__le32 *)cmd, val, GENMASK(9, 8));
3179 }
3180
RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void * cmd,u32 val)3181 static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val)
3182 {
3183 le32p_replace_bits((__le32 *)cmd, val, BIT(10));
3184 }
3185
RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void * cmd,u32 val)3186 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val)
3187 {
3188 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3189 }
3190
RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void * cmd,u32 val)3191 static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val)
3192 {
3193 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3194 }
3195
RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void * cmd,u32 val)3196 static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val)
3197 {
3198 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3199 }
3200
3201 struct rtw89_fw_mcc_tsf_req {
3202 u8 group: 2;
3203 u8 rsvd0: 6;
3204 u8 macid_x;
3205 u8 macid_y;
3206 u8 rsvd1;
3207 };
3208
RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void * cmd,u32 val)3209 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val)
3210 {
3211 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3212 }
3213
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void * cmd,u32 val)3214 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val)
3215 {
3216 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3217 }
3218
RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void * cmd,u32 val)3219 static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val)
3220 {
3221 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3222 }
3223
RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void * cmd,u32 val)3224 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val)
3225 {
3226 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3227 }
3228
RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void * cmd,u32 val)3229 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val)
3230 {
3231 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3232 }
3233
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void * cmd,u32 val)3234 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val)
3235 {
3236 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3237 }
3238
RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void * cmd,u8 * bitmap,u8 len)3239 static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd,
3240 u8 *bitmap, u8 len)
3241 {
3242 memcpy((__le32 *)cmd + 1, bitmap, len);
3243 }
3244
RTW89_SET_FWCMD_MCC_SYNC_GROUP(void * cmd,u32 val)3245 static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val)
3246 {
3247 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3248 }
3249
RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void * cmd,u32 val)3250 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val)
3251 {
3252 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3253 }
3254
RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void * cmd,u32 val)3255 static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val)
3256 {
3257 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3258 }
3259
RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void * cmd,u32 val)3260 static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val)
3261 {
3262 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3263 }
3264
3265 struct rtw89_fw_mcc_duration {
3266 u32 group: 2;
3267 u32 btc_in_group: 1;
3268 u32 rsvd0: 5;
3269 u32 start_macid: 8;
3270 u32 macid_x: 8;
3271 u32 macid_y: 8;
3272 u32 start_tsf_low;
3273 u32 start_tsf_high;
3274 u32 duration_x;
3275 u32 duration_y;
3276 };
3277
RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void * cmd,u32 val)3278 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val)
3279 {
3280 le32p_replace_bits((__le32 *)cmd, val, GENMASK(1, 0));
3281 }
3282
3283 static
RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void * cmd,u32 val)3284 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val)
3285 {
3286 le32p_replace_bits((__le32 *)cmd, val, BIT(2));
3287 }
3288
3289 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void * cmd,u32 val)3290 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val)
3291 {
3292 le32p_replace_bits((__le32 *)cmd, val, GENMASK(15, 8));
3293 }
3294
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void * cmd,u32 val)3295 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val)
3296 {
3297 le32p_replace_bits((__le32 *)cmd, val, GENMASK(23, 16));
3298 }
3299
RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void * cmd,u32 val)3300 static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val)
3301 {
3302 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 24));
3303 }
3304
3305 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void * cmd,u32 val)3306 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val)
3307 {
3308 le32p_replace_bits((__le32 *)cmd + 1, val, GENMASK(31, 0));
3309 }
3310
3311 static
RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void * cmd,u32 val)3312 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val)
3313 {
3314 le32p_replace_bits((__le32 *)cmd + 2, val, GENMASK(31, 0));
3315 }
3316
3317 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void * cmd,u32 val)3318 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val)
3319 {
3320 le32p_replace_bits((__le32 *)cmd + 3, val, GENMASK(31, 0));
3321 }
3322
3323 static
RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void * cmd,u32 val)3324 inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val)
3325 {
3326 le32p_replace_bits((__le32 *)cmd + 4, val, GENMASK(31, 0));
3327 }
3328
3329 enum rtw89_h2c_mrc_sch_types {
3330 RTW89_H2C_MRC_SCH_BAND0_ONLY = 0,
3331 RTW89_H2C_MRC_SCH_BAND1_ONLY = 1,
3332 RTW89_H2C_MRC_SCH_DUAL_BAND = 2,
3333 };
3334
3335 enum rtw89_h2c_mrc_role_types {
3336 RTW89_H2C_MRC_ROLE_WIFI = 0,
3337 RTW89_H2C_MRC_ROLE_BT = 1,
3338 RTW89_H2C_MRC_ROLE_EMPTY = 2,
3339 };
3340
3341 #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM 3
3342 #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT 1 /* before MLO */
3343
3344 struct rtw89_fw_mrc_add_slot_arg {
3345 u16 duration; /* unit: TU */
3346 bool courtesy_en;
3347 u8 courtesy_period;
3348 u8 courtesy_target; /* slot idx */
3349
3350 unsigned int role_num;
3351 struct {
3352 enum rtw89_h2c_mrc_role_types role_type;
3353 bool is_master;
3354 bool en_tx_null;
3355 enum rtw89_band band;
3356 enum rtw89_bandwidth bw;
3357 u8 macid;
3358 u8 central_ch;
3359 u8 primary_ch;
3360 u8 null_early; /* unit: TU */
3361
3362 /* if MLD, for macid: [0, chip::support_mld_num)
3363 * otherwise, for macid: [0, 32)
3364 */
3365 u32 macid_main_bitmap;
3366 /* for MLD, bit X maps to macid: X + chip::support_mld_num */
3367 u32 macid_paired_bitmap;
3368 } roles[RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT];
3369 };
3370
3371 struct rtw89_fw_mrc_add_arg {
3372 u8 sch_idx;
3373 enum rtw89_h2c_mrc_sch_types sch_type;
3374 bool btc_in_sch;
3375
3376 unsigned int slot_num;
3377 struct rtw89_fw_mrc_add_slot_arg slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3378 };
3379
3380 struct rtw89_h2c_mrc_add_role {
3381 __le32 w0;
3382 __le32 w1;
3383 __le32 w2;
3384 __le32 macid_main_bitmap;
3385 __le32 macid_paired_bitmap;
3386 } __packed;
3387
3388 #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID GENMASK(15, 0)
3389 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE GENMASK(23, 16)
3390 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER BIT(24)
3391 #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE BIT(25)
3392 #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN BIT(26)
3393 #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN BIT(27)
3394 #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG GENMASK(7, 0)
3395 #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH GENMASK(15, 8)
3396 #define RTW89_H2C_MRC_ADD_ROLE_W1_BW GENMASK(19, 16)
3397 #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE GENMASK(21, 20)
3398 #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS BIT(22)
3399 #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC BIT(23)
3400 #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY GENMASK(31, 24)
3401 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD GENMASK(7, 0)
3402 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE GENMASK(15, 8)
3403 #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID GENMASK(23, 16)
3404
3405 struct rtw89_h2c_mrc_add_slot {
3406 __le32 w0;
3407 __le32 w1;
3408 struct rtw89_h2c_mrc_add_role roles[];
3409 } __packed;
3410
3411 #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION GENMASK(15, 0)
3412 #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN BIT(17)
3413 #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM GENMASK(31, 24)
3414 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD GENMASK(7, 0)
3415 #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET GENMASK(15, 8)
3416
3417 struct rtw89_h2c_mrc_add {
3418 __le32 w0;
3419 /* Logically append flexible struct rtw89_h2c_mrc_add_slot, but there
3420 * are other flexible array inside it. We cannot access them correctly
3421 * through this struct. So, in case misusing, we don't really declare
3422 * it here.
3423 */
3424 } __packed;
3425
3426 #define RTW89_H2C_MRC_ADD_W0_SCH_IDX GENMASK(3, 0)
3427 #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE GENMASK(7, 4)
3428 #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM GENMASK(15, 8)
3429 #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH BIT(16)
3430
3431 enum rtw89_h2c_mrc_start_actions {
3432 RTW89_H2C_MRC_START_ACTION_START_NEW = 0,
3433 RTW89_H2C_MRC_START_ACTION_REPLACE_OLD = 1,
3434 };
3435
3436 struct rtw89_fw_mrc_start_arg {
3437 u8 sch_idx;
3438 u8 old_sch_idx;
3439 u64 start_tsf;
3440 enum rtw89_h2c_mrc_start_actions action;
3441 };
3442
3443 struct rtw89_h2c_mrc_start {
3444 __le32 w0;
3445 __le32 start_tsf_low;
3446 __le32 start_tsf_high;
3447 } __packed;
3448
3449 #define RTW89_H2C_MRC_START_W0_SCH_IDX GENMASK(3, 0)
3450 #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX GENMASK(7, 4)
3451 #define RTW89_H2C_MRC_START_W0_ACTION GENMASK(15, 8)
3452
3453 struct rtw89_h2c_mrc_del {
3454 __le32 w0;
3455 } __packed;
3456
3457 #define RTW89_H2C_MRC_DEL_W0_SCH_IDX GENMASK(3, 0)
3458 #define RTW89_H2C_MRC_DEL_W0_DEL_ALL BIT(4)
3459 #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY BIT(5)
3460 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN BIT(6)
3461 #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX GENMASK(15, 8)
3462 #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID GENMASK(31, 16)
3463
3464 #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM 2
3465
3466 struct rtw89_fw_mrc_req_tsf_arg {
3467 unsigned int num;
3468 struct {
3469 u8 band;
3470 u8 port;
3471 } infos[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3472 };
3473
3474 struct rtw89_h2c_mrc_req_tsf {
3475 u8 req_tsf_num;
3476 u8 infos[] __counted_by(req_tsf_num);
3477 } __packed;
3478
3479 #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND GENMASK(3, 0)
3480 #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT GENMASK(7, 4)
3481
3482 enum rtw89_h2c_mrc_upd_bitmap_actions {
3483 RTW89_H2C_MRC_UPD_BITMAP_ACTION_DEL = 0,
3484 RTW89_H2C_MRC_UPD_BITMAP_ACTION_ADD = 1,
3485 };
3486
3487 struct rtw89_fw_mrc_upd_bitmap_arg {
3488 u8 sch_idx;
3489 u8 macid;
3490 u8 client_macid;
3491 enum rtw89_h2c_mrc_upd_bitmap_actions action;
3492 };
3493
3494 struct rtw89_h2c_mrc_upd_bitmap {
3495 __le32 w0;
3496 __le32 w1;
3497 } __packed;
3498
3499 #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX GENMASK(3, 0)
3500 #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION BIT(4)
3501 #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID GENMASK(31, 16)
3502 #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID GENMASK(15, 0)
3503
3504 struct rtw89_fw_mrc_sync_arg {
3505 u8 offset; /* unit: TU */
3506 struct {
3507 u8 band;
3508 u8 port;
3509 } src, dest;
3510 };
3511
3512 struct rtw89_h2c_mrc_sync {
3513 __le32 w0;
3514 __le32 w1;
3515 } __packed;
3516
3517 #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN BIT(0)
3518 #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT GENMASK(11, 8)
3519 #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND GENMASK(15, 12)
3520 #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT GENMASK(19, 16)
3521 #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND GENMASK(23, 20)
3522 #define RTW89_H2C_MRC_SYNC_W1_OFFSET GENMASK(15, 0)
3523
3524 struct rtw89_fw_mrc_upd_duration_arg {
3525 u8 sch_idx;
3526 u64 start_tsf;
3527
3528 unsigned int slot_num;
3529 struct {
3530 u8 slot_idx;
3531 u16 duration; /* unit: TU */
3532 } slots[RTW89_MAC_MRC_MAX_ADD_SLOT_NUM];
3533 };
3534
3535 struct rtw89_h2c_mrc_upd_duration {
3536 __le32 w0;
3537 __le32 start_tsf_low;
3538 __le32 start_tsf_high;
3539 __le32 slots[];
3540 } __packed;
3541
3542 #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX GENMASK(3, 0)
3543 #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM GENMASK(15, 8)
3544 #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH BIT(16)
3545 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX GENMASK(7, 0)
3546 #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION GENMASK(31, 16)
3547
3548 struct rtw89_h2c_wow_aoac {
3549 __le32 w0;
3550 } __packed;
3551
3552 struct rtw89_h2c_ap_info {
3553 __le32 w0;
3554 } __packed;
3555
3556 #define RTW89_H2C_AP_INFO_W0_PWR_INT_EN BIT(0)
3557
3558 #define RTW89_C2H_HEADER_LEN 8
3559
3560 struct rtw89_c2h_hdr {
3561 __le32 w0;
3562 __le32 w1;
3563 } __packed;
3564
3565 #define RTW89_C2H_HDR_W0_CATEGORY GENMASK(1, 0)
3566 #define RTW89_C2H_HDR_W0_CLASS GENMASK(7, 2)
3567 #define RTW89_C2H_HDR_W0_FUNC GENMASK(15, 8)
3568 #define RTW89_C2H_HDR_W1_LEN GENMASK(13, 0)
3569
3570 struct rtw89_fw_c2h_attr {
3571 u8 category;
3572 u8 class;
3573 u8 func;
3574 u16 len;
3575 u8 is_scan_event: 1;
3576 u8 scan_seq: 2;
3577 };
3578
RTW89_SKB_C2H_CB(struct sk_buff * skb)3579 static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb)
3580 {
3581 #if defined(__linux__)
3582 static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3583 #elif defined(__FreeBSD__)
3584 rtw89_static_assert(sizeof(skb->cb) >= sizeof(struct rtw89_fw_c2h_attr));
3585 #endif
3586
3587 return (struct rtw89_fw_c2h_attr *)skb->cb;
3588 }
3589
3590 struct rtw89_c2h_done_ack {
3591 __le32 w0;
3592 __le32 w1;
3593 __le32 w2;
3594 } __packed;
3595
3596 #define RTW89_C2H_DONE_ACK_W2_CAT GENMASK(1, 0)
3597 #define RTW89_C2H_DONE_ACK_W2_CLASS GENMASK(7, 2)
3598 #define RTW89_C2H_DONE_ACK_W2_FUNC GENMASK(15, 8)
3599 #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN GENMASK(23, 16)
3600 #define RTW89_C2H_SCAN_DONE_ACK_RETURN GENMASK(5, 0)
3601 #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ GENMASK(31, 24)
3602
3603 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \
3604 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3605 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \
3606 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3607 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \
3608 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3609 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \
3610 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16))
3611
3612 struct rtw89_fw_c2h_log_fmt {
3613 __le16 signature;
3614 u8 feature;
3615 u8 syntax;
3616 __le32 fmt_id;
3617 u8 file_num;
3618 __le16 line_num;
3619 u8 argc;
3620 union {
3621 DECLARE_FLEX_ARRAY(u8, raw);
3622 DECLARE_FLEX_ARRAY(__le32, argv);
3623 } __packed u;
3624 } __packed;
3625
3626 #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN 11
3627 #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT BIT(2)
3628 #define RTW89_C2H_FW_LOG_MAX_PARA_NUM 16
3629 #define RTW89_C2H_FW_LOG_SIGNATURE 0xA5A5
3630 #define RTW89_C2H_FW_LOG_STR_BUF_SIZE 512
3631
3632 struct rtw89_c2h_mac_bcnfltr_rpt {
3633 __le32 w0;
3634 __le32 w1;
3635 __le32 w2;
3636 } __packed;
3637
3638 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID GENMASK(7, 0)
3639 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE GENMASK(9, 8)
3640 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT GENMASK(11, 10)
3641 #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA GENMASK(23, 16)
3642
3643 struct rtw89_c2h_ra_rpt {
3644 struct rtw89_c2h_hdr hdr;
3645 __le32 w2;
3646 __le32 w3;
3647 } __packed;
3648
3649 #define RTW89_C2H_RA_RPT_W2_MACID GENMASK(15, 0)
3650 #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO GENMASK(23, 16)
3651 #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 BIT(31)
3652 #define RTW89_C2H_RA_RPT_W3_MCSNSS GENMASK(6, 0)
3653 #define RTW89_C2H_RA_RPT_W3_MD_SEL GENMASK(9, 8)
3654 #define RTW89_C2H_RA_RPT_W3_GILTF GENMASK(12, 10)
3655 #define RTW89_C2H_RA_RPT_W3_BW GENMASK(14, 13)
3656 #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 BIT(15)
3657 #define RTW89_C2H_RA_RPT_W3_BW_B2 BIT(16)
3658
3659 struct rtw89_c2h_fw_scan_rpt {
3660 struct rtw89_c2h_hdr hdr;
3661 u8 phy_idx;
3662 u8 band;
3663 u8 center_ch;
3664 u8 ofdm_pd_idx; /* in unit of 2 dBm */
3665 #define PD_LOWER_BOUND_BASE 102
3666 s8 cck_pd_idx;
3667 u8 rsvd0;
3668 u8 rsvd1;
3669 u8 rsvd2;
3670 } __packed;
3671
3672 /* For WiFi 6 chips:
3673 * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS
3674 * HT-new: [6:5]: NA, [4:0]: MCS
3675 * For WiFi 7 chips (V1):
3676 * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS
3677 */
3678 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4)
3679 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0)
3680 #define RTW89_RA_RATE_MASK_NSS_V1 GENMASK(7, 5)
3681 #define RTW89_RA_RATE_MASK_MCS_V1 GENMASK(4, 0)
3682 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0)
3683 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \
3684 FIELD_PREP(GENMASK(2, 0), mcs))
3685
3686 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \
3687 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3688 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \
3689 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8))
3690 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \
3691 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16))
3692
3693 struct rtw89_c2h_scanofld {
3694 __le32 w0;
3695 __le32 w1;
3696 __le32 w2;
3697 __le32 w3;
3698 __le32 w4;
3699 __le32 w5;
3700 __le32 w6;
3701 __le32 w7;
3702 __le32 w8;
3703 } __packed;
3704
3705 #define RTW89_C2H_SCANOFLD_W2_PRI_CH GENMASK(7, 0)
3706 #define RTW89_C2H_SCANOFLD_W2_RSN GENMASK(19, 16)
3707 #define RTW89_C2H_SCANOFLD_W2_STATUS GENMASK(23, 20)
3708 #define RTW89_C2H_SCANOFLD_W2_PERIOD GENMASK(31, 24)
3709 #define RTW89_C2H_SCANOFLD_W5_TX_FAIL GENMASK(3, 0)
3710 #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY GENMASK(7, 4)
3711 #define RTW89_C2H_SCANOFLD_W5_BAND GENMASK(25, 24)
3712 #define RTW89_C2H_SCANOFLD_W5_MAC_IDX BIT(26)
3713 #define RTW89_C2H_SCANOFLD_W6_SW_DEF GENMASK(7, 0)
3714 #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD GENMASK(15, 8)
3715 #define RTW89_C2H_SCANOFLD_W6_FW_DEF GENMASK(23, 16)
3716 #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF GENMASK(31, 0)
3717 #define RTW89_C2H_SCANOFLD_W8_PERIOD_V1 GENMASK(15, 0)
3718 #define RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1 GENMASK(31, 16)
3719
3720 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) \
3721 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3722 #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) \
3723 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3724
3725 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) \
3726 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0))
3727 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) \
3728 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2))
3729 #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) \
3730 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3731
3732 struct rtw89_mac_mcc_tsf_rpt {
3733 u32 macid_x;
3734 u32 macid_y;
3735 u32 tsf_x_low;
3736 u32 tsf_x_high;
3737 u32 tsf_y_low;
3738 u32 tsf_y_high;
3739 };
3740
3741 #if defined(__linux__)
3742 static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3743 #elif defined(__FreeBSD__)
3744 rtw89_static_assert(sizeof(struct rtw89_mac_mcc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3745 #endif
3746
3747 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) \
3748 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0))
3749 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) \
3750 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3751 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) \
3752 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(17, 16))
3753 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) \
3754 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3755 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) \
3756 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3757 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) \
3758 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(31, 0))
3759 #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) \
3760 le32_get_bits(*((const __le32 *)(c2h) + 6), GENMASK(31, 0))
3761
3762 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) \
3763 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(5, 0))
3764 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) \
3765 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 6))
3766 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) \
3767 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8))
3768 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) \
3769 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(31, 0))
3770 #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) \
3771 le32_get_bits(*((const __le32 *)(c2h) + 4), GENMASK(31, 0))
3772
3773 struct rtw89_c2h_mlo_link_cfg_rpt {
3774 struct rtw89_c2h_hdr hdr;
3775 __le32 w2;
3776 } __packed;
3777
3778 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID GENMASK(15, 0)
3779 #define RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS GENMASK(19, 16)
3780
3781 enum rtw89_c2h_mlo_link_status {
3782 RTW89_C2H_MLO_LINK_CFG_IDLE = 0,
3783 RTW89_C2H_MLO_LINK_CFG_DONE = 1,
3784 RTW89_C2H_MLO_LINK_CFG_ISSUE_NULL_FAIL = 2,
3785 RTW89_C2H_MLO_LINK_CFG_TX_NULL_FAIL = 3,
3786 RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST = 4,
3787 RTW89_C2H_MLO_LINK_CFG_NULL_1_TIMEOUT = 5,
3788 RTW89_C2H_MLO_LINK_CFG_NULL_0_TIMEOUT = 6,
3789 RTW89_C2H_MLO_LINK_CFG_RUNNING = 0xff,
3790 };
3791
3792 struct rtw89_mac_mrc_tsf_rpt {
3793 unsigned int num;
3794 u64 tsfs[RTW89_MAC_MRC_MAX_REQ_TSF_NUM];
3795 };
3796
3797 static_assert(sizeof(struct rtw89_mac_mrc_tsf_rpt) <= RTW89_COMPLETION_BUF_SIZE);
3798
3799 struct rtw89_c2h_mrc_tsf_rpt_info {
3800 __le32 tsf_low;
3801 __le32 tsf_high;
3802 } __packed;
3803
3804 struct rtw89_c2h_mrc_tsf_rpt {
3805 struct rtw89_c2h_hdr hdr;
3806 __le32 w2;
3807 struct rtw89_c2h_mrc_tsf_rpt_info infos[];
3808 } __packed;
3809
3810 #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM GENMASK(7, 0)
3811
3812 struct rtw89_c2h_mrc_status_rpt {
3813 struct rtw89_c2h_hdr hdr;
3814 __le32 w2;
3815 __le32 tsf_low;
3816 __le32 tsf_high;
3817 } __packed;
3818
3819 #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS GENMASK(5, 0)
3820 #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX GENMASK(7, 6)
3821
3822 struct rtw89_c2h_pkt_ofld_rsp {
3823 __le32 w0;
3824 __le32 w1;
3825 __le32 w2;
3826 } __packed;
3827
3828 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID GENMASK(7, 0)
3829 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP GENMASK(10, 8)
3830 #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN GENMASK(31, 16)
3831
3832 struct rtw89_c2h_tx_duty_rpt {
3833 struct rtw89_c2h_hdr c2h_hdr;
3834 __le32 w2;
3835 } __packed;
3836
3837 #define RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR GENMASK(2, 0)
3838
3839 struct rtw89_c2h_wow_aoac_report {
3840 struct rtw89_c2h_hdr c2h_hdr;
3841 u8 rpt_ver;
3842 u8 sec_type;
3843 u8 key_idx;
3844 u8 pattern_idx;
3845 u8 rekey_ok;
3846 u8 rsvd1[3];
3847 u8 ptk_tx_iv[8];
3848 u8 eapol_key_replay_count[8];
3849 u8 gtk[32];
3850 u8 ptk_rx_iv[8];
3851 u8 gtk_rx_iv[4][8];
3852 __le64 igtk_key_id;
3853 __le64 igtk_ipn;
3854 u8 igtk[32];
3855 u8 csa_pri_ch;
3856 u8 csa_bw_ch_offset;
3857 u8 csa_ch_band_chsw_failed;
3858 u8 csa_rsvd1;
3859 } __packed;
3860
3861 #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX BIT(0)
3862
3863 struct rtw89_c2h_pwr_int_notify {
3864 struct rtw89_c2h_hdr hdr;
3865 __le32 w2;
3866 } __packed;
3867
3868 #define RTW89_C2H_PWR_INT_NOTIFY_W2_MACID GENMASK(15, 0)
3869 #define RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS BIT(16)
3870
3871 struct rtw89_h2c_tx_duty {
3872 __le32 w0;
3873 __le32 w1;
3874 } __packed;
3875
3876 #define RTW89_H2C_TX_DUTY_W0_PAUSE_INTVL_MASK GENMASK(15, 0)
3877 #define RTW89_H2C_TX_DUTY_W0_TX_INTVL_MASK GENMASK(31, 16)
3878 #define RTW89_H2C_TX_DUTY_W1_STOP BIT(0)
3879
3880 struct rtw89_h2c_bcnfltr {
3881 __le32 w0;
3882 } __packed;
3883
3884 #define RTW89_H2C_BCNFLTR_W0_MON_RSSI BIT(0)
3885 #define RTW89_H2C_BCNFLTR_W0_MON_BCN BIT(1)
3886 #define RTW89_H2C_BCNFLTR_W0_MON_EN BIT(2)
3887 #define RTW89_H2C_BCNFLTR_W0_MODE GENMASK(4, 3)
3888 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_H3 GENMASK(7, 5)
3889 #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT_L4 GENMASK(11, 8)
3890 #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST GENMASK(15, 12)
3891 #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD GENMASK(23, 16)
3892 #define RTW89_H2C_BCNFLTR_W0_MAC_ID GENMASK(31, 24)
3893
3894 struct rtw89_h2c_ofld_rssi {
3895 __le32 w0;
3896 __le32 w1;
3897 } __packed;
3898
3899 #define RTW89_H2C_OFLD_RSSI_W0_MACID GENMASK(7, 0)
3900 #define RTW89_H2C_OFLD_RSSI_W0_NUM GENMASK(15, 8)
3901 #define RTW89_H2C_OFLD_RSSI_W1_VAL GENMASK(7, 0)
3902
3903 struct rtw89_h2c_ofld {
3904 __le32 w0;
3905 } __packed;
3906
3907 #define RTW89_H2C_OFLD_W0_MAC_ID GENMASK(7, 0)
3908 #define RTW89_H2C_OFLD_W0_TX_TP GENMASK(17, 8)
3909 #define RTW89_H2C_OFLD_W0_RX_TP GENMASK(27, 18)
3910
3911 #define RTW89_MFW_SIG 0xFF
3912
3913 struct rtw89_mfw_info {
3914 u8 cv;
3915 u8 type; /* enum rtw89_fw_type */
3916 u8 mp;
3917 u8 rsvd;
3918 __le32 shift;
3919 __le32 size;
3920 u8 rsvd2[4];
3921 } __packed;
3922
3923 struct rtw89_mfw_hdr {
3924 u8 sig; /* RTW89_MFW_SIG */
3925 u8 fw_nr;
3926 u8 rsvd0[2];
3927 struct {
3928 u8 major;
3929 u8 minor;
3930 u8 sub;
3931 u8 idx;
3932 } ver;
3933 u8 rsvd1[8];
3934 struct rtw89_mfw_info info[];
3935 } __packed;
3936
3937 struct rtw89_fw_logsuit_hdr {
3938 __le32 rsvd;
3939 __le32 count;
3940 __le32 ids[];
3941 } __packed;
3942
3943 #define RTW89_FW_ELEMENT_ALIGN 16
3944
3945 enum rtw89_fw_element_id {
3946 RTW89_FW_ELEMENT_ID_BBMCU0 = 0,
3947 RTW89_FW_ELEMENT_ID_BBMCU1 = 1,
3948 RTW89_FW_ELEMENT_ID_BB_REG = 2,
3949 RTW89_FW_ELEMENT_ID_BB_GAIN = 3,
3950 RTW89_FW_ELEMENT_ID_RADIO_A = 4,
3951 RTW89_FW_ELEMENT_ID_RADIO_B = 5,
3952 RTW89_FW_ELEMENT_ID_RADIO_C = 6,
3953 RTW89_FW_ELEMENT_ID_RADIO_D = 7,
3954 RTW89_FW_ELEMENT_ID_RF_NCTL = 8,
3955 RTW89_FW_ELEMENT_ID_TXPWR_BYRATE = 9,
3956 RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ = 10,
3957 RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ = 11,
3958 RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ = 12,
3959 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ = 13,
3960 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ = 14,
3961 RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ = 15,
3962 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT = 16,
3963 RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU = 17,
3964 RTW89_FW_ELEMENT_ID_TXPWR_TRK = 18,
3965 RTW89_FW_ELEMENT_ID_RFKLOG_FMT = 19,
3966 RTW89_FW_ELEMENT_ID_REGD = 20,
3967 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_2GHZ = 21,
3968 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_5GHZ = 22,
3969 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_6GHZ = 23,
3970 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_2GHZ = 24,
3971 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_5GHZ = 25,
3972 RTW89_FW_ELEMENT_ID_TXPWR_DA_LMT_RU_6GHZ = 26,
3973
3974 RTW89_FW_ELEMENT_ID_NUM,
3975 };
3976
3977 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ \
3978 (BIT(RTW89_FW_ELEMENT_ID_TXPWR_BYRATE) | \
3979 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_2GHZ) | \
3980 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_5GHZ) | \
3981 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_2GHZ) | \
3982 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_5GHZ) | \
3983 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT) | \
3984 BIT(RTW89_FW_ELEMENT_ID_TX_SHAPE_LMT_RU))
3985
3986 #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS \
3987 (BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ | \
3988 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_6GHZ) | \
3989 BIT(RTW89_FW_ELEMENT_ID_TXPWR_LMT_RU_6GHZ))
3990
3991 #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ \
3992 (BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
3993 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
3994 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
3995 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
3996 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
3997 BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ)
3998
3999 #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS (BIT(RTW89_FW_ELEMENT_ID_BBMCU0) | \
4000 BIT(RTW89_FW_ELEMENT_ID_BB_REG) | \
4001 BIT(RTW89_FW_ELEMENT_ID_RADIO_A) | \
4002 BIT(RTW89_FW_ELEMENT_ID_RADIO_B) | \
4003 BIT(RTW89_FW_ELEMENT_ID_RF_NCTL) | \
4004 BIT(RTW89_FW_ELEMENT_ID_TXPWR_TRK) | \
4005 BITS_OF_RTW89_TXPWR_FW_ELEMENTS)
4006
4007 struct __rtw89_fw_txpwr_element {
4008 u8 rsvd0;
4009 u8 rsvd1;
4010 u8 rfe_type;
4011 u8 ent_sz;
4012 __le32 num_ents;
4013 u8 content[];
4014 } __packed;
4015
4016 struct __rtw89_fw_regd_element {
4017 u8 rsvd0;
4018 u8 rsvd1;
4019 u8 rsvd2;
4020 u8 ent_sz;
4021 __le32 num_ents;
4022 u8 content[];
4023 } __packed;
4024
4025 enum rtw89_fw_txpwr_trk_type {
4026 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_START = 0,
4027 RTW89_FW_TXPWR_TRK_TYPE_6GB_N = 0,
4028 RTW89_FW_TXPWR_TRK_TYPE_6GB_P = 1,
4029 RTW89_FW_TXPWR_TRK_TYPE_6GA_N = 2,
4030 RTW89_FW_TXPWR_TRK_TYPE_6GA_P = 3,
4031 __RTW89_FW_TXPWR_TRK_TYPE_6GHZ_MAX = 3,
4032
4033 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_START = 4,
4034 RTW89_FW_TXPWR_TRK_TYPE_5GB_N = 4,
4035 RTW89_FW_TXPWR_TRK_TYPE_5GB_P = 5,
4036 RTW89_FW_TXPWR_TRK_TYPE_5GA_N = 6,
4037 RTW89_FW_TXPWR_TRK_TYPE_5GA_P = 7,
4038 __RTW89_FW_TXPWR_TRK_TYPE_5GHZ_MAX = 7,
4039
4040 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_START = 8,
4041 RTW89_FW_TXPWR_TRK_TYPE_2GB_N = 8,
4042 RTW89_FW_TXPWR_TRK_TYPE_2GB_P = 9,
4043 RTW89_FW_TXPWR_TRK_TYPE_2GA_N = 10,
4044 RTW89_FW_TXPWR_TRK_TYPE_2GA_P = 11,
4045 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N = 12,
4046 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P = 13,
4047 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N = 14,
4048 RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P = 15,
4049 __RTW89_FW_TXPWR_TRK_TYPE_2GHZ_MAX = 15,
4050
4051 RTW89_FW_TXPWR_TRK_TYPE_NR,
4052 };
4053
4054 struct rtw89_fw_txpwr_track_cfg {
4055 const s8 (*delta[RTW89_FW_TXPWR_TRK_TYPE_NR])[DELTA_SWINGIDX_SIZE];
4056 };
4057
4058 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ \
4059 (BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_N) | \
4060 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GB_P) | \
4061 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_N) | \
4062 BIT(RTW89_FW_TXPWR_TRK_TYPE_6GA_P))
4063 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ \
4064 (BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_N) | \
4065 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GB_P) | \
4066 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_N) | \
4067 BIT(RTW89_FW_TXPWR_TRK_TYPE_5GA_P))
4068 #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ \
4069 (BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_N) | \
4070 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GB_P) | \
4071 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_N) | \
4072 BIT(RTW89_FW_TXPWR_TRK_TYPE_2GA_P) | \
4073 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_N) | \
4074 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_B_P) | \
4075 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_N) | \
4076 BIT(RTW89_FW_TXPWR_TRK_TYPE_2G_CCK_A_P))
4077
4078 struct rtw89_fw_element_hdr {
4079 __le32 id; /* enum rtw89_fw_element_id */
4080 __le32 size; /* exclude header size */
4081 u8 ver[4];
4082 __le32 rsvd0;
4083 __le32 rsvd1;
4084 __le32 rsvd2;
4085 union {
4086 struct {
4087 u8 priv[8];
4088 u8 contents[];
4089 } __packed common;
4090 struct {
4091 u8 idx;
4092 u8 rsvd[7];
4093 struct {
4094 __le32 addr;
4095 __le32 data;
4096 } __packed regs[];
4097 } __packed reg2;
4098 struct {
4099 u8 cv;
4100 u8 priv[7];
4101 u8 contents[];
4102 } __packed bbmcu;
4103 struct {
4104 __le32 bitmap; /* bitmap of enum rtw89_fw_txpwr_trk_type */
4105 __le32 rsvd;
4106 s8 contents[][DELTA_SWINGIDX_SIZE];
4107 } __packed txpwr_trk;
4108 struct {
4109 u8 nr;
4110 u8 rsvd[3];
4111 u8 rfk_id; /* enum rtw89_phy_c2h_rfk_log_func */
4112 u8 rsvd1[3];
4113 __le16 offset[];
4114 } __packed rfk_log_fmt;
4115 struct __rtw89_fw_txpwr_element txpwr;
4116 struct __rtw89_fw_regd_element regd;
4117 } __packed u;
4118 } __packed;
4119
4120 struct fwcmd_hdr {
4121 __le32 hdr0;
4122 __le32 hdr1;
4123 };
4124
4125 union rtw89_compat_fw_hdr {
4126 struct rtw89_mfw_hdr mfw_hdr;
4127 struct rtw89_fw_hdr fw_hdr;
4128 };
4129
rtw89_compat_fw_hdr_ver_code(const void * fw_buf)4130 static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf)
4131 {
4132 const union rtw89_compat_fw_hdr *compat = (typeof(compat))fw_buf;
4133
4134 if (compat->mfw_hdr.sig == RTW89_MFW_SIG)
4135 return RTW89_MFW_HDR_VER_CODE(&compat->mfw_hdr);
4136 else
4137 return RTW89_FW_HDR_VER_CODE(&compat->fw_hdr);
4138 }
4139
rtw89_fw_get_filename(char * buf,size_t size,const char * fw_basename,int fw_format)4140 static inline void rtw89_fw_get_filename(char *buf, size_t size,
4141 const char *fw_basename, int fw_format)
4142 {
4143 if (fw_format <= 0)
4144 snprintf(buf, size, "%s.bin", fw_basename);
4145 else
4146 snprintf(buf, size, "%s-%d.bin", fw_basename, fw_format);
4147 }
4148
4149 #define RTW89_H2C_RF_PAGE_SIZE 500
4150 #define RTW89_H2C_RF_PAGE_NUM 3
4151 struct rtw89_fw_h2c_rf_reg_info {
4152 enum rtw89_rf_path rf_path;
4153 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];
4154 u16 curr_idx;
4155 };
4156
4157 #define H2C_SEC_CAM_LEN 24
4158
4159 #define H2C_HEADER_LEN 8
4160 #define H2C_HDR_CAT GENMASK(1, 0)
4161 #define H2C_HDR_CLASS GENMASK(7, 2)
4162 #define H2C_HDR_FUNC GENMASK(15, 8)
4163 #define H2C_HDR_DEL_TYPE GENMASK(19, 16)
4164 #define H2C_HDR_H2C_SEQ GENMASK(31, 24)
4165 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0)
4166 #define H2C_HDR_REC_ACK BIT(14)
4167 #define H2C_HDR_DONE_ACK BIT(15)
4168
4169 #define FWCMD_TYPE_H2C 0
4170
4171 #define H2C_CAT_TEST 0x0
4172
4173 /* CLASS 5 - FW STATUS TEST */
4174 #define H2C_CL_FW_STATUS_TEST 0x5
4175 #define H2C_FUNC_CPU_EXCEPTION 0x1
4176
4177 #define H2C_CAT_MAC 0x1
4178
4179 /* CLASS 0 - FW INFO */
4180 #define H2C_CL_FW_INFO 0x0
4181 #define H2C_FUNC_LOG_CFG 0x0
4182 #define H2C_FUNC_MAC_GENERAL_PKT 0x1
4183
4184 /* CLASS 1 - WOW */
4185 #define H2C_CL_MAC_WOW 0x1
4186 enum rtw89_wow_h2c_func {
4187 H2C_FUNC_KEEP_ALIVE = 0x0,
4188 H2C_FUNC_DISCONNECT_DETECT = 0x1,
4189 H2C_FUNC_WOW_GLOBAL = 0x2,
4190 H2C_FUNC_GTK_OFLD = 0x3,
4191 H2C_FUNC_ARP_OFLD = 0x4,
4192 H2C_FUNC_NLO = 0x7,
4193 H2C_FUNC_WAKEUP_CTRL = 0x8,
4194 H2C_FUNC_WOW_CAM_UPD = 0xC,
4195 H2C_FUNC_AOAC_REPORT_REQ = 0xD,
4196
4197 NUM_OF_RTW89_WOW_H2C_FUNC,
4198 };
4199
4200 #define RTW89_WOW_WAIT_COND(tag, func) \
4201 ((tag) * NUM_OF_RTW89_WOW_H2C_FUNC + (func))
4202
4203 #define RTW89_WOW_WAIT_COND_AOAC \
4204 RTW89_WOW_WAIT_COND(0 /* don't care */, H2C_FUNC_AOAC_REPORT_REQ)
4205
4206 /* CLASS 2 - PS */
4207 #define H2C_CL_MAC_PS 0x2
4208 enum rtw89_ps_h2c_func {
4209 H2C_FUNC_MAC_LPS_PARM = 0x0,
4210 H2C_FUNC_P2P_ACT = 0x1,
4211 H2C_FUNC_IPS_CFG = 0x3,
4212
4213 NUM_OF_RTW89_PS_H2C_FUNC,
4214 };
4215
4216 #define RTW89_PS_WAIT_COND(tag, func) \
4217 ((tag) * NUM_OF_RTW89_PS_H2C_FUNC + (func))
4218
4219 #define RTW89_PS_WAIT_COND_IPS_CFG \
4220 RTW89_PS_WAIT_COND(0 /* don't care */, H2C_FUNC_IPS_CFG)
4221
4222 /* CLASS 3 - FW download */
4223 #define H2C_CL_MAC_FWDL 0x3
4224 #define H2C_FUNC_MAC_FWHDR_DL 0x0
4225
4226 /* CLASS 5 - Frame Exchange */
4227 #define H2C_CL_MAC_FR_EXCHG 0x5
4228 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2
4229 #define H2C_FUNC_MAC_BCN_UPD 0x5
4230 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9
4231 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa
4232 #define H2C_FUNC_MAC_DCTLINFO_UD_V2 0xc
4233 #define H2C_FUNC_MAC_BCN_UPD_BE 0xd
4234 #define H2C_FUNC_MAC_CCTLINFO_UD_G7 0x11
4235
4236 /* CLASS 6 - Address CAM */
4237 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6
4238 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0
4239
4240 /* CLASS 8 - Media Status Report */
4241 #define H2C_CL_MAC_MEDIA_RPT 0x8
4242 #define H2C_FUNC_MAC_JOININFO 0x0
4243 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4
4244 #define H2C_FUNC_NOTIFY_DBCC 0x5
4245
4246 /* CLASS 9 - FW offload */
4247 #define H2C_CL_MAC_FW_OFLD 0x9
4248 enum rtw89_fw_ofld_h2c_func {
4249 H2C_FUNC_PACKET_OFLD = 0x1,
4250 H2C_FUNC_MAC_MACID_PAUSE = 0x8,
4251 H2C_FUNC_USR_EDCA = 0xF,
4252 H2C_FUNC_TSF32_TOGL = 0x10,
4253 H2C_FUNC_OFLD_CFG = 0x14,
4254 H2C_FUNC_ADD_SCANOFLD_CH = 0x16,
4255 H2C_FUNC_SCANOFLD = 0x17,
4256 H2C_FUNC_TX_DUTY = 0x18,
4257 H2C_FUNC_PKT_DROP = 0x1b,
4258 H2C_FUNC_CFG_BCNFLTR = 0x1e,
4259 H2C_FUNC_OFLD_RSSI = 0x1f,
4260 H2C_FUNC_OFLD_TP = 0x20,
4261 H2C_FUNC_MAC_MACID_PAUSE_SLEEP = 0x28,
4262 H2C_FUNC_SCANOFLD_BE = 0x2c,
4263
4264 NUM_OF_RTW89_FW_OFLD_H2C_FUNC,
4265 };
4266
4267 #define RTW89_FW_OFLD_WAIT_COND(tag, func) \
4268 ((tag) * NUM_OF_RTW89_FW_OFLD_H2C_FUNC + (func))
4269
4270 #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) \
4271 RTW89_FW_OFLD_WAIT_COND(RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op), \
4272 H2C_FUNC_PACKET_OFLD)
4273
4274 #define RTW89_SCANOFLD_WAIT_COND_ADD_CH RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_ADD_SCANOFLD_CH)
4275
4276 #define RTW89_SCANOFLD_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD)
4277 #define RTW89_SCANOFLD_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD)
4278 #define RTW89_SCANOFLD_BE_WAIT_COND_START RTW89_FW_OFLD_WAIT_COND(0, H2C_FUNC_SCANOFLD_BE)
4279 #define RTW89_SCANOFLD_BE_WAIT_COND_STOP RTW89_FW_OFLD_WAIT_COND(1, H2C_FUNC_SCANOFLD_BE)
4280
4281
4282 /* CLASS 10 - Security CAM */
4283 #define H2C_CL_MAC_SEC_CAM 0xa
4284 #define H2C_FUNC_MAC_SEC_UPD 0x1
4285
4286 /* CLASS 12 - BA CAM */
4287 #define H2C_CL_BA_CAM 0xc
4288 #define H2C_FUNC_MAC_BA_CAM 0x0
4289 #define H2C_FUNC_MAC_BA_CAM_V1 0x1
4290 #define H2C_FUNC_MAC_BA_CAM_INIT 0x2
4291
4292 /* CLASS 14 - MCC */
4293 #define H2C_CL_MCC 0xe
4294 enum rtw89_mcc_h2c_func {
4295 H2C_FUNC_ADD_MCC = 0x0,
4296 H2C_FUNC_START_MCC = 0x1,
4297 H2C_FUNC_STOP_MCC = 0x2,
4298 H2C_FUNC_DEL_MCC_GROUP = 0x3,
4299 H2C_FUNC_RESET_MCC_GROUP = 0x4,
4300 H2C_FUNC_MCC_REQ_TSF = 0x5,
4301 H2C_FUNC_MCC_MACID_BITMAP = 0x6,
4302 H2C_FUNC_MCC_SYNC = 0x7,
4303 H2C_FUNC_MCC_SET_DURATION = 0x8,
4304
4305 NUM_OF_RTW89_MCC_H2C_FUNC,
4306 };
4307
4308 #define RTW89_MCC_WAIT_COND(group, func) \
4309 ((group) * NUM_OF_RTW89_MCC_H2C_FUNC + (func))
4310
4311 /* CLASS 20 - MLO */
4312 #define H2C_CL_MLO 0x14
4313 enum rtw89_mlo_h2c_func {
4314 H2C_FUNC_MLO_TBL_CFG = 0x0,
4315 H2C_FUNC_MLO_STA_CFG = 0x1,
4316 H2C_FUNC_MLO_TTLM = 0x2,
4317 H2C_FUNC_MLO_DM_CFG = 0x3,
4318 H2C_FUNC_MLO_EMLSR_STA_CFG = 0x4,
4319 H2C_FUNC_MLO_MCMLO_RELINK_DROP = 0x5,
4320 H2C_FUNC_MLO_MCMLO_SN_SYNC = 0x6,
4321 H2C_FUNC_MLO_RELINK = 0x7,
4322 H2C_FUNC_MLO_LINK_CFG = 0x8,
4323 H2C_FUNC_MLO_DM_DBG = 0x9,
4324
4325 NUM_OF_RTW89_MLO_H2C_FUNC,
4326 };
4327
4328 #define RTW89_MLO_WAIT_COND(macid, func) \
4329 ((macid) * NUM_OF_RTW89_MLO_H2C_FUNC + (func))
4330
4331 /* CLASS 24 - MRC */
4332 #define H2C_CL_MRC 0x18
4333 enum rtw89_mrc_h2c_func {
4334 H2C_FUNC_MRC_REQ_TSF = 0x0,
4335 H2C_FUNC_ADD_MRC = 0x1,
4336 H2C_FUNC_START_MRC = 0x2,
4337 H2C_FUNC_DEL_MRC = 0x3,
4338 H2C_FUNC_MRC_SYNC = 0x4,
4339 H2C_FUNC_MRC_UPD_DURATION = 0x5,
4340 H2C_FUNC_MRC_UPD_BITMAP = 0x6,
4341
4342 NUM_OF_RTW89_MRC_H2C_FUNC,
4343 };
4344
4345 /* can consider MRC's sch_idx as MCC's group */
4346 #define RTW89_MRC_WAIT_COND(sch_idx, func) \
4347 ((sch_idx) * NUM_OF_RTW89_MRC_H2C_FUNC + (func))
4348
4349 #define RTW89_MRC_WAIT_COND_REQ_TSF \
4350 RTW89_MRC_WAIT_COND(0 /* don't care */, H2C_FUNC_MRC_REQ_TSF)
4351
4352 /* CLASS 36 - AP */
4353 #define H2C_CL_AP 0x24
4354 #define H2C_FUNC_AP_INFO 0x0
4355
4356 #define H2C_CAT_OUTSRC 0x2
4357
4358 #define H2C_CL_OUTSRC_RA 0x1
4359 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
4360
4361 #define H2C_CL_OUTSRC_DM 0x2
4362 #define H2C_FUNC_FW_MCC_DIG 0x6
4363 #define H2C_FUNC_FW_LPS_CH_INFO 0xb
4364 #define H2C_FUNC_FW_LPS_ML_CMN_INFO 0xe
4365
4366 #define H2C_CL_OUTSRC_RF_REG_A 0x8
4367 #define H2C_CL_OUTSRC_RF_REG_B 0x9
4368 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa
4369 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2
4370 #define H2C_FUNC_OUTSRC_RF_PS_INFO 0x10
4371 #define H2C_CL_OUTSRC_RF_FW_RFK 0xb
4372
4373 enum rtw89_rfk_offload_h2c_func {
4374 H2C_FUNC_RFK_TSSI_OFFLOAD = 0x0,
4375 H2C_FUNC_RFK_IQK_OFFLOAD = 0x1,
4376 H2C_FUNC_RFK_DPK_OFFLOAD = 0x3,
4377 H2C_FUNC_RFK_TXGAPK_OFFLOAD = 0x4,
4378 H2C_FUNC_RFK_DACK_OFFLOAD = 0x5,
4379 H2C_FUNC_RFK_RXDCK_OFFLOAD = 0x6,
4380 H2C_FUNC_RFK_PRE_NOTIFY = 0x8,
4381 };
4382
4383 struct rtw89_fw_h2c_rf_get_mccch {
4384 __le32 ch_0_0;
4385 __le32 ch_0_1;
4386 __le32 ch_1_0;
4387 __le32 ch_1_1;
4388 __le32 current_channel;
4389 } __packed;
4390
4391 struct rtw89_fw_h2c_rf_get_mccch_v0 {
4392 __le32 ch_0;
4393 __le32 ch_1;
4394 __le32 band_0;
4395 __le32 band_1;
4396 __le32 current_channel;
4397 __le32 current_band_type;
4398 } __packed;
4399
4400 struct rtw89_h2c_mcc_dig {
4401 __le32 w0;
4402 __le32 w1;
4403 __le32 w2;
4404 } __packed;
4405
4406 #define RTW89_H2C_MCC_DIG_W0_REG_CNT GENMASK(7, 0)
4407 #define RTW89_H2C_MCC_DIG_W0_DM_EN BIT(8)
4408 #define RTW89_H2C_MCC_DIG_W0_IDX GENMASK(10, 9)
4409 #define RTW89_H2C_MCC_DIG_W0_SET BIT(11)
4410 #define RTW89_H2C_MCC_DIG_W0_PHY0_EN BIT(12)
4411 #define RTW89_H2C_MCC_DIG_W0_PHY1_EN BIT(13)
4412 #define RTW89_H2C_MCC_DIG_W0_CENTER_CH GENMASK(23, 16)
4413 #define RTW89_H2C_MCC_DIG_W0_BAND_TYPE GENMASK(31, 24)
4414 #define RTW89_H2C_MCC_DIG_W1_ADDR_LSB GENMASK(7, 0)
4415 #define RTW89_H2C_MCC_DIG_W1_ADDR_MSB GENMASK(15, 8)
4416 #define RTW89_H2C_MCC_DIG_W1_BMASK_LSB GENMASK(23, 16)
4417 #define RTW89_H2C_MCC_DIG_W1_BMASK_MSB GENMASK(31, 24)
4418 #define RTW89_H2C_MCC_DIG_W2_VAL_LSB GENMASK(7, 0)
4419 #define RTW89_H2C_MCC_DIG_W2_VAL_MSB GENMASK(15, 8)
4420
4421 #define NUM_OF_RTW89_FW_RFK_PATH 2
4422 #define NUM_OF_RTW89_FW_RFK_TBL 3
4423
4424 struct rtw89_h2c_rf_ps_info {
4425 __le32 rf18[NUM_OF_RTW89_FW_RFK_PATH];
4426 __le32 mlo_mode;
4427 u8 pri_ch[NUM_OF_RTW89_FW_RFK_PATH];
4428 } __packed;
4429
4430 struct rtw89_fw_h2c_rfk_pre_info_common {
4431 struct {
4432 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4433 __le32 band[NUM_OF_RTW89_FW_RFK_PATH][NUM_OF_RTW89_FW_RFK_TBL];
4434 } __packed dbcc;
4435
4436 __le32 mlo_mode;
4437 struct {
4438 __le32 cur_ch[NUM_OF_RTW89_FW_RFK_PATH];
4439 __le32 cur_band[NUM_OF_RTW89_FW_RFK_PATH];
4440 } __packed tbl;
4441
4442 __le32 phy_idx;
4443 } __packed;
4444
4445 struct rtw89_fw_h2c_rfk_pre_info_v0 {
4446 struct rtw89_fw_h2c_rfk_pre_info_common common;
4447
4448 __le32 cur_band;
4449 __le32 cur_bw;
4450 __le32 cur_center_ch;
4451
4452 __le32 ktbl_sel0;
4453 __le32 ktbl_sel1;
4454 __le32 rfmod0;
4455 __le32 rfmod1;
4456
4457 __le32 mlo_1_1;
4458 __le32 rfe_type;
4459 __le32 drv_mode;
4460
4461 struct {
4462 __le32 ch[NUM_OF_RTW89_FW_RFK_PATH];
4463 __le32 band[NUM_OF_RTW89_FW_RFK_PATH];
4464 } __packed mlo;
4465 } __packed;
4466
4467 struct rtw89_fw_h2c_rfk_pre_info_v1 {
4468 struct rtw89_fw_h2c_rfk_pre_info_common common;
4469 __le32 mlo_1_1;
4470 } __packed;
4471
4472 struct rtw89_fw_h2c_rfk_pre_info {
4473 struct rtw89_fw_h2c_rfk_pre_info_v1 base_v1;
4474 __le32 cur_bandwidth[NUM_OF_RTW89_FW_RFK_PATH];
4475 } __packed;
4476
4477 struct rtw89_h2c_rf_tssi {
4478 __le16 len;
4479 u8 phy;
4480 u8 ch;
4481 u8 bw;
4482 u8 band;
4483 u8 hwtx_en;
4484 u8 cv;
4485 s8 curr_tssi_cck_de[2];
4486 s8 curr_tssi_cck_de_20m[2];
4487 s8 curr_tssi_cck_de_40m[2];
4488 s8 curr_tssi_efuse_cck_de[2];
4489 s8 curr_tssi_ofdm_de[2];
4490 s8 curr_tssi_ofdm_de_20m[2];
4491 s8 curr_tssi_ofdm_de_40m[2];
4492 s8 curr_tssi_ofdm_de_80m[2];
4493 s8 curr_tssi_ofdm_de_160m[2];
4494 s8 curr_tssi_ofdm_de_320m[2];
4495 s8 curr_tssi_efuse_ofdm_de[2];
4496 s8 curr_tssi_ofdm_de_diff_20m[2];
4497 s8 curr_tssi_ofdm_de_diff_80m[2];
4498 s8 curr_tssi_ofdm_de_diff_160m[2];
4499 s8 curr_tssi_ofdm_de_diff_320m[2];
4500 s8 curr_tssi_trim_de[2];
4501 u8 pg_thermal[2];
4502 u8 ftable[2][128];
4503 u8 tssi_mode;
4504 u8 rfe_type;
4505 } __packed;
4506
4507 struct rtw89_h2c_rf_iqk_v0 {
4508 __le32 phy_idx;
4509 __le32 dbcc;
4510 } __packed;
4511
4512 struct rtw89_h2c_rf_iqk {
4513 u8 len;
4514 u8 ktype;
4515 u8 phy;
4516 u8 kpath;
4517 u8 band;
4518 u8 bw;
4519 u8 ch;
4520 u8 cv;
4521 } __packed;
4522
4523 struct rtw89_h2c_rf_dpk {
4524 u8 len;
4525 u8 phy;
4526 u8 dpk_enable;
4527 u8 kpath;
4528 u8 cur_band;
4529 u8 cur_bw;
4530 u8 cur_ch;
4531 u8 dpk_dbg_en;
4532 } __packed;
4533
4534 struct rtw89_h2c_rf_txgapk {
4535 u8 len;
4536 u8 ktype;
4537 u8 phy;
4538 u8 kpath;
4539 u8 band;
4540 u8 bw;
4541 u8 ch;
4542 u8 cv;
4543 } __packed;
4544
4545 struct rtw89_h2c_rf_dack {
4546 __le32 len;
4547 __le32 phy;
4548 __le32 type;
4549 } __packed;
4550
4551 struct rtw89_h2c_rf_rxdck_v0 {
4552 u8 len;
4553 u8 phy;
4554 u8 is_afe;
4555 u8 kpath;
4556 u8 cur_band;
4557 u8 cur_bw;
4558 u8 cur_ch;
4559 u8 rxdck_dbg_en;
4560 } __packed;
4561
4562 struct rtw89_h2c_rf_rxdck {
4563 struct rtw89_h2c_rf_rxdck_v0 v0;
4564 u8 is_chl_k;
4565 } __packed;
4566
4567 enum rtw89_rf_log_type {
4568 RTW89_RF_RUN_LOG = 0,
4569 RTW89_RF_RPT_LOG = 1,
4570 };
4571
4572 struct rtw89_c2h_rf_log_hdr {
4573 u8 type; /* enum rtw89_rf_log_type */
4574 __le16 len;
4575 u8 content[];
4576 } __packed;
4577
4578 struct rtw89_c2h_rf_run_log {
4579 __le32 fmt_idx;
4580 __le32 arg[4];
4581 } __packed;
4582
4583 struct rtw89_c2h_rf_iqk_rpt_log {
4584 bool iqk_tx_fail[2];
4585 bool iqk_rx_fail[2];
4586 bool is_iqk_init;
4587 bool is_reload;
4588 bool is_wb_txiqk[2];
4589 bool is_wb_rxiqk[2];
4590 bool is_nbiqk;
4591 bool txiqk_en;
4592 bool rxiqk_en;
4593 bool lok_en;
4594 bool iqk_xym_en;
4595 bool iqk_sram_en;
4596 bool iqk_fft_en;
4597 bool is_fw_iqk;
4598 bool is_iqk_enable;
4599 bool iqk_cfir_en;
4600 bool thermal_rek_en;
4601 u8 iqk_band[2];
4602 u8 iqk_ch[2];
4603 u8 iqk_bw[2];
4604 u8 iqk_times;
4605 u8 version;
4606 u8 phy;
4607 u8 fwk_status;
4608 u8 rsvd;
4609 __le32 reload_cnt;
4610 __le32 iqk_fail_cnt;
4611 __le32 lok_idac[2];
4612 __le32 lok_vbuf[2];
4613 __le32 rftxgain[2][4];
4614 __le32 rfrxgain[2][4];
4615 __le32 tx_xym[2][4];
4616 __le32 rx_xym[2][4];
4617 } __packed;
4618
4619 struct rtw89_c2h_rf_dpk_rpt_log {
4620 u8 ver;
4621 u8 idx[2];
4622 u8 band[2];
4623 u8 bw[2];
4624 u8 ch[2];
4625 u8 path_ok[2];
4626 u8 txagc[2];
4627 u8 ther[2];
4628 u8 gs[2];
4629 u8 dc_i[4];
4630 u8 dc_q[4];
4631 u8 corr_val[2];
4632 u8 corr_idx[2];
4633 u8 is_timeout[2];
4634 u8 rxbb_ov[2];
4635 u8 rsvd;
4636 } __packed;
4637
4638 struct rtw89_c2h_rf_dack_rpt_log {
4639 u8 fwdack_ver;
4640 u8 fwdack_info_ver;
4641 u8 msbk_d[2][2][16];
4642 u8 dadck_d[2][2];
4643 u8 cdack_d[2][2][2];
4644 u8 addck2_hd[2][2][2];
4645 u8 addck2_ld[2][2][2];
4646 u8 adgaink_d[2][2];
4647 u8 biask_hd[2][2];
4648 u8 biask_ld[2][2];
4649 u8 addck_timeout;
4650 u8 cdack_timeout;
4651 u8 dadck_timeout;
4652 u8 msbk_timeout;
4653 u8 adgaink_timeout;
4654 u8 wbadcdck_timeout;
4655 u8 drck_timeout;
4656 u8 dack_fail;
4657 u8 wbdck_d[2];
4658 u8 rck_d;
4659 } __packed;
4660
4661 struct rtw89_c2h_rf_rxdck_rpt_log {
4662 u8 ver;
4663 u8 band[2];
4664 u8 bw[2];
4665 u8 ch[2];
4666 u8 timeout[2];
4667 } __packed;
4668
4669 struct rtw89_c2h_rf_tssi_rpt_log {
4670 s8 alignment_power[2][2][4];
4671 u8 alignment_power_cw_h[2][2][4];
4672 u8 alignment_power_cw_l[2][2][4];
4673 u8 tssi_alimk_state[2][2];
4674 u8 default_txagc_offset[2][2];
4675 } __packed;
4676
4677 struct rtw89_c2h_rf_txgapk_rpt_log {
4678 __le32 r0x8010[2];
4679 __le32 chk_cnt;
4680 u8 track_d[2][17];
4681 u8 power_d[2][17];
4682 u8 is_txgapk_ok;
4683 u8 chk_id;
4684 u8 ver;
4685 u8 rsv1;
4686 } __packed;
4687
4688 struct rtw89_c2h_rfk_report {
4689 struct rtw89_c2h_hdr hdr;
4690 u8 state; /* enum rtw89_rfk_report_state */
4691 u8 version;
4692 } __packed;
4693
4694 struct rtw89_c2h_rf_tas_info {
4695 struct rtw89_c2h_hdr hdr;
4696 __le32 cur_idx;
4697 __le16 txpwr_history[20];
4698 } __packed;
4699
4700 #define RTW89_FW_RSVD_PLE_SIZE 0x800
4701
4702 #define RTW89_FW_BACKTRACE_INFO_SIZE 8
4703 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \
4704 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0)
4705
4706 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */
4707 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE
4708
4709 #define FWDL_WAIT_CNT 400000
4710 #define FWDL_WAIT_CNT_USB 3200
4711
4712 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type);
4713 int rtw89_fw_recognize(struct rtw89_dev *rtwdev);
4714 int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev);
4715 const struct firmware *
4716 rtw89_early_fw_feature_recognize(struct device *device,
4717 const struct rtw89_chip_info *chip,
4718 struct rtw89_fw_info *early_fw,
4719 int *used_fw_format);
4720 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,
4721 bool include_bb);
4722 void rtw89_load_firmware_work(struct work_struct *work);
4723 void rtw89_unload_firmware(struct rtw89_dev *rtwdev);
4724 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev);
4725 int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev);
4726 void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len);
4727 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4728 u8 type, u8 cat, u8 class, u8 func,
4729 bool rack, bool dack, u32 len);
4730 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4731 struct rtw89_vif_link *rtwvif_link,
4732 struct rtw89_sta_link *rtwsta_link);
4733 int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4734 struct rtw89_vif_link *rtwvif_link,
4735 struct rtw89_sta_link *rtwsta_link);
4736 int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev,
4737 struct rtw89_vif_link *rtwvif_link,
4738 struct rtw89_sta_link *rtwsta_link);
4739 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
4740 struct rtw89_vif_link *rtwvif_link,
4741 struct rtw89_sta_link *rtwsta_link);
4742 int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4743 struct rtw89_vif_link *rtwvif_link,
4744 struct rtw89_sta_link *rtwsta_link);
4745 int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4746 struct rtw89_vif_link *rtwvif_link,
4747 struct rtw89_sta_link *rtwsta_link);
4748 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
4749 struct rtw89_sta_link *rtwsta_link);
4750 int rtw89_fw_h2c_txtime_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4751 struct rtw89_sta_link *rtwsta_link);
4752 int rtw89_fw_h2c_punctured_cmac_tbl_g7(struct rtw89_dev *rtwdev,
4753 struct rtw89_vif_link *rtwvif_link,
4754 u16 punctured);
4755 int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev,
4756 struct rtw89_sta_link *rtwsta_link);
4757 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev,
4758 struct rtw89_vif_link *rtwvif_link);
4759 int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev,
4760 struct rtw89_vif_link *rtwvif_link);
4761 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif,
4762 struct rtw89_sta_link *rtwsta_link, const u8 *scan_mac_addr);
4763 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev,
4764 struct rtw89_vif_link *rtwvif_link,
4765 struct rtw89_sta_link *rtwsta_link);
4766 int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev,
4767 struct rtw89_vif_link *rtwvif_link,
4768 struct rtw89_sta_link *rtwsta_link);
4769 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h);
4770 void rtw89_fw_c2h_work(struct wiphy *wiphy, struct wiphy_work *work);
4771 void rtw89_fw_c2h_purge_obsoleted_scan_events(struct rtw89_dev *rtwdev);
4772 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev,
4773 struct rtw89_vif_link *rtwvif_link,
4774 struct rtw89_sta_link *rtwsta_link,
4775 enum rtw89_upd_mode upd_mode);
4776 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4777 struct rtw89_sta_link *rtwsta_link, bool dis_conn);
4778 int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en);
4779 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,
4780 bool pause);
4781 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4782 u8 ac, u32 val);
4783 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev);
4784 int rtw89_fw_h2c_tx_duty(struct rtw89_dev *rtwdev, u8 lv);
4785 int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev,
4786 struct rtw89_vif_link *rtwvif_link,
4787 bool connect);
4788 int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
4789 struct rtw89_rx_phy_ppdu *phy_ppdu);
4790 int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
4791 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
4792 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
4793 int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
4794 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
4795 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type);
4796 int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type);
4797 int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type);
4798 int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type);
4799 int rtw89_fw_h2c_cxdrv_osi_info(struct rtw89_dev *rtwdev, u8 type);
4800 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type);
4801 int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type);
4802 int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type);
4803 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type);
4804 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id);
4805 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id,
4806 struct sk_buff *skb_ofld);
4807 int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev,
4808 struct rtw89_scan_option *opt,
4809 struct rtw89_vif_link *vif,
4810 bool wowlan);
4811 int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev,
4812 struct rtw89_scan_option *opt,
4813 struct rtw89_vif_link *vif,
4814 bool wowlan);
4815 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,
4816 struct rtw89_fw_h2c_rf_reg_info *info,
4817 u16 len, u8 page);
4818 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev);
4819 int rtw89_fw_h2c_rf_ps_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4820 int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev,
4821 enum rtw89_phy_idx phy_idx);
4822 int rtw89_fw_h2c_mcc_dig(struct rtw89_dev *rtwdev,
4823 enum rtw89_chanctx_idx chanctx_idx,
4824 u8 mcc_role_idx, u8 pd_val, bool en);
4825 int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4826 const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode);
4827 int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4828 const struct rtw89_chan *chan);
4829 int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4830 const struct rtw89_chan *chan);
4831 int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4832 const struct rtw89_chan *chan);
4833 int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4834 const struct rtw89_chan *chan);
4835 int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
4836 const struct rtw89_chan *chan, bool is_chl_k);
4837 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,
4838 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len,
4839 bool rack, bool dack);
4840 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len);
4841 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev);
4842 void __rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4843 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev);
4844 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4845 u8 macid);
4846 void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev,
4847 struct rtw89_vif_link *rtwvif_link,
4848 bool notify_fw);
4849 void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw);
4850 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev,
4851 struct rtw89_vif_link *rtwvif_link,
4852 struct rtw89_sta_link *rtwsta_link,
4853 bool valid, struct ieee80211_ampdu_params *params);
4854 int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev,
4855 struct rtw89_vif_link *rtwvif_link,
4856 struct rtw89_sta_link *rtwsta_link,
4857 bool valid, struct ieee80211_ampdu_params *params);
4858 void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev);
4859 int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users,
4860 u8 offset, u8 mac_idx);
4861
4862 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,
4863 struct rtw89_lps_parm *lps_param);
4864 int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
4865 int rtw89_fw_h2c_lps_ml_cmn_info(struct rtw89_dev *rtwdev,
4866 struct rtw89_vif *rtwvif);
4867 int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4868 bool enable);
4869 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len);
4870 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len);
4871 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,
4872 struct rtw89_mac_h2c_info *h2c_info,
4873 struct rtw89_mac_c2h_info *c2h_info);
4874 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable);
4875 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev);
4876 int rtw89_hw_scan_start(struct rtw89_dev *rtwdev,
4877 struct rtw89_vif_link *rtwvif_link,
4878 struct ieee80211_scan_request *scan_req);
4879 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev,
4880 struct rtw89_vif_link *rtwvif_link,
4881 bool aborted);
4882 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev,
4883 struct rtw89_vif_link *rtwvif_link,
4884 bool enable);
4885 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev,
4886 struct rtw89_vif_link *rtwvif_link);
4887 int rtw89_hw_scan_prep_chan_list_ax(struct rtw89_dev *rtwdev,
4888 struct rtw89_vif_link *rtwvif_link);
4889 void rtw89_hw_scan_free_chan_list_ax(struct rtw89_dev *rtwdev);
4890 int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4891 struct rtw89_vif_link *rtwvif_link);
4892 int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev,
4893 struct rtw89_vif_link *rtwvif_link);
4894 int rtw89_hw_scan_prep_chan_list_be(struct rtw89_dev *rtwdev,
4895 struct rtw89_vif_link *rtwvif_link);
4896 void rtw89_hw_scan_free_chan_list_be(struct rtw89_dev *rtwdev);
4897 int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4898 struct rtw89_vif_link *rtwvif_link);
4899 int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev,
4900 struct rtw89_vif_link *rtwvif_link);
4901 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev);
4902 int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev,
4903 const struct rtw89_pkt_drop_params *params);
4904 int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev,
4905 struct rtw89_vif_link *rtwvif_link,
4906 struct ieee80211_p2p_noa_desc *desc,
4907 u8 act, u8 noa_id, u8 ctwindow_oppps);
4908 int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev,
4909 struct rtw89_vif_link *rtwvif_link,
4910 bool en);
4911 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4912 bool enable);
4913 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4914 struct rtw89_vif_link *rtwvif_link, bool enable);
4915 int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4916 bool enable);
4917 int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4918 bool enable);
4919 int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev,
4920 struct rtw89_vif_link *rtwvif_link, bool enable);
4921 int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev,
4922 struct rtw89_vif_link *rtwvif_link, bool enable);
4923 int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4924 bool enable);
4925 int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev,
4926 struct rtw89_vif_link *rtwvif_link, bool enable);
4927 int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev,
4928 struct rtw89_wow_cam_info *cam_info);
4929 int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev,
4930 struct rtw89_vif_link *rtwvif_link,
4931 bool enable);
4932 int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev);
4933 int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev,
4934 const struct rtw89_fw_mcc_add_req *p);
4935 int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev,
4936 const struct rtw89_fw_mcc_start_req *p);
4937 int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4938 bool prev_groups);
4939 int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group,
4940 bool prev_groups);
4941 int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group);
4942 int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev,
4943 const struct rtw89_fw_mcc_tsf_req *req,
4944 struct rtw89_mac_mcc_tsf_rpt *rpt);
4945 int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid,
4946 u8 *bitmap);
4947 int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source,
4948 u8 target, u8 offset);
4949 int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev,
4950 const struct rtw89_fw_mcc_duration *p);
4951 int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev,
4952 const struct rtw89_fw_mrc_add_arg *arg);
4953 int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev,
4954 const struct rtw89_fw_mrc_start_arg *arg);
4955 int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx);
4956 int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev,
4957 const struct rtw89_fw_mrc_req_tsf_arg *arg,
4958 struct rtw89_mac_mrc_tsf_rpt *rpt);
4959 int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev,
4960 const struct rtw89_fw_mrc_upd_bitmap_arg *arg);
4961 int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev,
4962 const struct rtw89_fw_mrc_sync_arg *arg);
4963 int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev,
4964 const struct rtw89_fw_mrc_upd_duration_arg *arg);
4965 int rtw89_fw_h2c_ap_info_refcount(struct rtw89_dev *rtwdev, bool en);
4966 int rtw89_fw_h2c_mlo_link_cfg(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4967 bool enable);
4968
rtw89_fw_h2c_init_ba_cam(struct rtw89_dev * rtwdev)4969 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev)
4970 {
4971 const struct rtw89_chip_info *chip = rtwdev->chip;
4972
4973 if (chip->bacam_ver == RTW89_BACAM_V0_EXT)
4974 rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(rtwdev);
4975 }
4976
rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4977 static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev,
4978 struct rtw89_vif_link *rtwvif_link,
4979 struct rtw89_sta_link *rtwsta_link)
4980 {
4981 const struct rtw89_chip_info *chip = rtwdev->chip;
4982
4983 return chip->ops->h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4984 }
4985
rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4986 static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev,
4987 struct rtw89_vif_link *rtwvif_link,
4988 struct rtw89_sta_link *rtwsta_link)
4989 {
4990 const struct rtw89_chip_info *chip = rtwdev->chip;
4991
4992 if (chip->ops->h2c_default_dmac_tbl)
4993 return chip->ops->h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4994
4995 return 0;
4996 }
4997
rtw89_chip_h2c_update_beacon(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4998 static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev,
4999 struct rtw89_vif_link *rtwvif_link)
5000 {
5001 const struct rtw89_chip_info *chip = rtwdev->chip;
5002
5003 return chip->ops->h2c_update_beacon(rtwdev, rtwvif_link);
5004 }
5005
rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5006 static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,
5007 struct rtw89_vif_link *rtwvif_link,
5008 struct rtw89_sta_link *rtwsta_link)
5009 {
5010 const struct rtw89_chip_info *chip = rtwdev->chip;
5011
5012 return chip->ops->h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5013 }
5014
5015 static inline
rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5016 int rtw89_chip_h2c_ampdu_link_cmac_tbl(struct rtw89_dev *rtwdev,
5017 struct rtw89_vif_link *rtwvif_link,
5018 struct rtw89_sta_link *rtwsta_link)
5019 {
5020 const struct rtw89_chip_info *chip = rtwdev->chip;
5021
5022 if (chip->ops->h2c_ampdu_cmac_tbl)
5023 return chip->ops->h2c_ampdu_cmac_tbl(rtwdev, rtwvif_link,
5024 rtwsta_link);
5025
5026 return 0;
5027 }
5028
rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta)5029 static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev,
5030 struct rtw89_vif *rtwvif,
5031 struct rtw89_sta *rtwsta)
5032 {
5033 struct rtw89_vif_link *rtwvif_link;
5034 struct rtw89_sta_link *rtwsta_link;
5035 unsigned int link_id;
5036 int ret;
5037
5038 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5039 rtwvif_link = rtwsta_link->rtwvif_link;
5040 ret = rtw89_chip_h2c_ampdu_link_cmac_tbl(rtwdev, rtwvif_link,
5041 rtwsta_link);
5042 if (ret)
5043 return ret;
5044 }
5045
5046 return 0;
5047 }
5048
5049 static inline
rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)5050 int rtw89_chip_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,
5051 struct rtw89_sta_link *rtwsta_link)
5052 {
5053 const struct rtw89_chip_info *chip = rtwdev->chip;
5054
5055 return chip->ops->h2c_txtime_cmac_tbl(rtwdev, rtwsta_link);
5056 }
5057
5058 static inline
rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,u16 punctured)5059 int rtw89_chip_h2c_punctured_cmac_tbl(struct rtw89_dev *rtwdev,
5060 struct rtw89_vif_link *rtwvif_link,
5061 u16 punctured)
5062 {
5063 const struct rtw89_chip_info *chip = rtwdev->chip;
5064
5065 if (!chip->ops->h2c_punctured_cmac_tbl)
5066 return 0;
5067
5068 return chip->ops->h2c_punctured_cmac_tbl(rtwdev, rtwvif_link, punctured);
5069 }
5070
5071 static inline
rtw89_chip_h2c_ba_cam(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool valid,struct ieee80211_ampdu_params * params)5072 int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5073 bool valid, struct ieee80211_ampdu_params *params)
5074 {
5075 const struct rtw89_chip_info *chip = rtwdev->chip;
5076 struct rtw89_vif_link *rtwvif_link;
5077 struct rtw89_sta_link *rtwsta_link;
5078 unsigned int link_id;
5079 int ret;
5080
5081 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
5082 rtwvif_link = rtwsta_link->rtwvif_link;
5083 ret = chip->ops->h2c_ba_cam(rtwdev, rtwvif_link, rtwsta_link,
5084 valid, params);
5085 if (ret)
5086 return ret;
5087 }
5088
5089 return 0;
5090 }
5091
5092 /* Must consider compatibility; don't insert new in the mid.
5093 * Fill each field's default value in rtw89_regd_entcpy().
5094 */
5095 struct rtw89_fw_regd_entry {
5096 u8 alpha2_0;
5097 u8 alpha2_1;
5098 u8 rule_2ghz;
5099 u8 rule_5ghz;
5100 u8 rule_6ghz;
5101 __le32 fmap;
5102 } __packed;
5103
5104 /* must consider compatibility; don't insert new in the mid */
5105 struct rtw89_fw_txpwr_byrate_entry {
5106 u8 band;
5107 u8 nss;
5108 u8 rs;
5109 u8 shf;
5110 u8 len;
5111 __le32 data;
5112 u8 bw;
5113 u8 ofdma;
5114 } __packed;
5115
5116 /* must consider compatibility; don't insert new in the mid */
5117 struct rtw89_fw_txpwr_lmt_2ghz_entry {
5118 u8 bw;
5119 u8 nt;
5120 u8 rs;
5121 u8 bf;
5122 u8 regd;
5123 u8 ch_idx;
5124 s8 v;
5125 } __packed;
5126
5127 /* must consider compatibility; don't insert new in the mid */
5128 struct rtw89_fw_txpwr_lmt_5ghz_entry {
5129 u8 bw;
5130 u8 nt;
5131 u8 rs;
5132 u8 bf;
5133 u8 regd;
5134 u8 ch_idx;
5135 s8 v;
5136 } __packed;
5137
5138 /* must consider compatibility; don't insert new in the mid */
5139 struct rtw89_fw_txpwr_lmt_6ghz_entry {
5140 u8 bw;
5141 u8 nt;
5142 u8 rs;
5143 u8 bf;
5144 u8 regd;
5145 u8 reg_6ghz_power;
5146 u8 ch_idx;
5147 s8 v;
5148 } __packed;
5149
5150 /* must consider compatibility; don't insert new in the mid */
5151 struct rtw89_fw_txpwr_lmt_ru_2ghz_entry {
5152 u8 ru;
5153 u8 nt;
5154 u8 regd;
5155 u8 ch_idx;
5156 s8 v;
5157 } __packed;
5158
5159 /* must consider compatibility; don't insert new in the mid */
5160 struct rtw89_fw_txpwr_lmt_ru_5ghz_entry {
5161 u8 ru;
5162 u8 nt;
5163 u8 regd;
5164 u8 ch_idx;
5165 s8 v;
5166 } __packed;
5167
5168 /* must consider compatibility; don't insert new in the mid */
5169 struct rtw89_fw_txpwr_lmt_ru_6ghz_entry {
5170 u8 ru;
5171 u8 nt;
5172 u8 regd;
5173 u8 reg_6ghz_power;
5174 u8 ch_idx;
5175 s8 v;
5176 } __packed;
5177
5178 /* must consider compatibility; don't insert new in the mid */
5179 struct rtw89_fw_tx_shape_lmt_entry {
5180 u8 band;
5181 u8 tx_shape_rs;
5182 u8 regd;
5183 u8 v;
5184 } __packed;
5185
5186 /* must consider compatibility; don't insert new in the mid */
5187 struct rtw89_fw_tx_shape_lmt_ru_entry {
5188 u8 band;
5189 u8 regd;
5190 u8 v;
5191 } __packed;
5192
5193 const struct rtw89_rfe_parms *
5194 rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev,
5195 const struct rtw89_rfe_parms *init);
5196
5197 enum rtw89_wow_wakeup_ver {
5198 RTW89_WOW_REASON_V0,
5199 RTW89_WOW_REASON_V1,
5200 RTW89_WOW_REASON_NUM,
5201 };
5202
5203 #endif
5204