1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - Single-link to LVDS Channel A tested 15 * - Single-link to LVDS Channel B tested 16 * - 2x Single-link LVDS mode unsupported 17 * (should be easy to add by someone who has the HW) 18 * - SN65DSI85 19 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 20 * - Unsupported 21 * (should be easy to add by someone who has the HW) 22 * 23 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 24 * 25 * Based on previous work of: 26 * Valentin Raevsky <valentin@compulab.co.il> 27 * Philippe Schenker <philippe.schenker@toradex.com> 28 */ 29 30 #include <linux/bits.h> 31 #include <linux/clk.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/i2c.h> 34 #include <linux/media-bus-format.h> 35 #include <linux/module.h> 36 #include <linux/of.h> 37 #include <linux/of_graph.h> 38 #include <linux/regmap.h> 39 #include <linux/regulator/consumer.h> 40 #include <linux/timer.h> 41 #include <linux/workqueue.h> 42 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_bridge.h> 45 #include <drm/drm_bridge_helper.h> 46 #include <drm/drm_mipi_dsi.h> 47 #include <drm/drm_of.h> 48 #include <drm/drm_print.h> 49 #include <drm/drm_probe_helper.h> 50 51 /* ID registers */ 52 #define REG_ID(n) (0x00 + (n)) 53 /* Reset and clock registers */ 54 #define REG_RC_RESET 0x09 55 #define REG_RC_RESET_SOFT_RESET BIT(0) 56 #define REG_RC_LVDS_PLL 0x0a 57 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 58 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 59 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 60 #define REG_RC_DSI_CLK 0x0b 61 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 62 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 63 #define REG_RC_PLL_EN 0x0d 64 #define REG_RC_PLL_EN_PLL_EN BIT(0) 65 /* DSI registers */ 66 #define REG_DSI_LANE 0x10 67 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 68 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 69 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 70 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 71 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 72 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 73 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 74 #define REG_DSI_EQ 0x11 75 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 76 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 77 #define REG_DSI_CLK 0x12 78 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 79 /* LVDS registers */ 80 #define REG_LVDS_FMT 0x18 81 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 82 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 83 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 84 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 85 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 86 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 87 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 88 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 89 #define REG_LVDS_VCOM 0x19 90 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 91 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 92 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 93 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 94 #define REG_LVDS_LANE 0x1a 95 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 96 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 97 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 98 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 99 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 100 #define REG_LVDS_CM 0x1b 101 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 102 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 103 /* Video registers */ 104 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 105 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 106 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 107 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 108 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28 109 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 110 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 111 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 112 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 113 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 114 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 115 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 116 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 117 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 118 #define REG_VID_CHA_TEST_PATTERN 0x3c 119 #define REG_VID_CHA_TEST_PATTERN_EN BIT(4) 120 /* IRQ registers */ 121 #define REG_IRQ_GLOBAL 0xe0 122 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 123 #define REG_IRQ_EN 0xe1 124 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 125 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 126 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 127 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 128 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 129 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 130 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 131 #define REG_IRQ_STAT 0xe5 132 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 133 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 134 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 135 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 136 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 137 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 138 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 139 140 static bool sn65dsi83_test_pattern; 141 module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644); 142 143 enum sn65dsi83_channel { 144 CHANNEL_A, 145 CHANNEL_B 146 }; 147 148 enum sn65dsi83_lvds_term { 149 OHM_100, 150 OHM_200 151 }; 152 153 enum sn65dsi83_model { 154 MODEL_SN65DSI83, 155 MODEL_SN65DSI84, 156 }; 157 158 struct sn65dsi83 { 159 struct drm_bridge bridge; 160 struct device *dev; 161 struct regmap *regmap; 162 struct mipi_dsi_device *dsi; 163 struct drm_bridge *panel_bridge; 164 struct gpio_desc *enable_gpio; 165 struct regulator *vcc; 166 bool lvds_dual_link; 167 bool lvds_channel_swap; 168 int lvds_vod_swing_conf[2]; 169 int lvds_term_conf[2]; 170 int irq; 171 struct delayed_work monitor_work; 172 struct work_struct reset_work; 173 }; 174 175 static const struct regmap_range sn65dsi83_readable_ranges[] = { 176 regmap_reg_range(REG_ID(0), REG_ID(8)), 177 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 178 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 179 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 180 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 181 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 182 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 183 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 184 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 185 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 186 REG_VID_CHA_SYNC_DELAY_HIGH), 187 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 188 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 189 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 190 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 191 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 192 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 193 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 194 REG_VID_CHA_VERTICAL_BACK_PORCH), 195 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 196 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 197 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 198 REG_VID_CHA_VERTICAL_FRONT_PORCH), 199 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 200 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 201 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 202 }; 203 204 static const struct regmap_access_table sn65dsi83_readable_table = { 205 .yes_ranges = sn65dsi83_readable_ranges, 206 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 207 }; 208 209 static const struct regmap_range sn65dsi83_writeable_ranges[] = { 210 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 211 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 212 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 213 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 214 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 215 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 216 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 217 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 218 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 219 REG_VID_CHA_SYNC_DELAY_HIGH), 220 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 221 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 222 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 223 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 224 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 225 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 226 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 227 REG_VID_CHA_VERTICAL_BACK_PORCH), 228 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 229 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 230 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 231 REG_VID_CHA_VERTICAL_FRONT_PORCH), 232 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 233 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 234 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 235 }; 236 237 static const struct regmap_access_table sn65dsi83_writeable_table = { 238 .yes_ranges = sn65dsi83_writeable_ranges, 239 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 240 }; 241 242 static const struct regmap_range sn65dsi83_volatile_ranges[] = { 243 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 244 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 245 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 246 }; 247 248 static const struct regmap_access_table sn65dsi83_volatile_table = { 249 .yes_ranges = sn65dsi83_volatile_ranges, 250 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 251 }; 252 253 static const struct regmap_config sn65dsi83_regmap_config = { 254 .reg_bits = 8, 255 .val_bits = 8, 256 .rd_table = &sn65dsi83_readable_table, 257 .wr_table = &sn65dsi83_writeable_table, 258 .volatile_table = &sn65dsi83_volatile_table, 259 .cache_type = REGCACHE_MAPLE, 260 .max_register = REG_IRQ_STAT, 261 }; 262 263 static const int lvds_vod_swing_data_table[2][4][2] = { 264 { /* 100 Ohm */ 265 { 180000, 313000 }, 266 { 215000, 372000 }, 267 { 250000, 430000 }, 268 { 290000, 488000 }, 269 }, 270 { /* 200 Ohm */ 271 { 150000, 261000 }, 272 { 200000, 346000 }, 273 { 250000, 428000 }, 274 { 300000, 511000 }, 275 }, 276 }; 277 278 static const int lvds_vod_swing_clock_table[2][4][2] = { 279 { /* 100 Ohm */ 280 { 140000, 244000 }, 281 { 168000, 290000 }, 282 { 195000, 335000 }, 283 { 226000, 381000 }, 284 }, 285 { /* 200 Ohm */ 286 { 117000, 204000 }, 287 { 156000, 270000 }, 288 { 195000, 334000 }, 289 { 234000, 399000 }, 290 }, 291 }; 292 293 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 294 { 295 return container_of(bridge, struct sn65dsi83, bridge); 296 } 297 298 static int sn65dsi83_attach(struct drm_bridge *bridge, 299 struct drm_encoder *encoder, 300 enum drm_bridge_attach_flags flags) 301 { 302 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 303 304 return drm_bridge_attach(encoder, ctx->panel_bridge, 305 &ctx->bridge, flags); 306 } 307 308 static void sn65dsi83_detach(struct drm_bridge *bridge) 309 { 310 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 311 312 if (!ctx->dsi) 313 return; 314 315 ctx->dsi = NULL; 316 } 317 318 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx, 319 const struct drm_display_mode *mode) 320 { 321 /* 322 * The encoding of the LVDS_CLK_RANGE is as follows: 323 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 324 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 325 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 326 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 327 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 328 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 329 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 330 * the ends of the ranges are clamped to the supported range. Since 331 * sn65dsi83_mode_valid() already filters the valid modes and limits 332 * the clock to 25..154 MHz, the range calculation can be simplified 333 * as follows: 334 */ 335 int mode_clock = mode->clock; 336 337 if (ctx->lvds_dual_link) 338 mode_clock /= 2; 339 340 return (mode_clock - 12500) / 25000; 341 } 342 343 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 344 const struct drm_display_mode *mode) 345 { 346 /* 347 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 348 * 0x00 through 0x07 - Reserved 349 * 0x08 - 40 <= DSI_CLK < 45 MHz 350 * 0x09 - 45 <= DSI_CLK < 50 MHz 351 * ... 352 * 0x63 - 495 <= DSI_CLK < 500 MHz 353 * 0x64 - 500 MHz 354 * 0x65 through 0xFF - Reserved 355 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 356 * The DSI clock are calculated as: 357 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 358 * the 2 is there because the bus is DDR. 359 */ 360 return clamp((unsigned int)mode->clock * 361 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 362 ctx->dsi->lanes / 2, 40000U, 500000U) / 5000U; 363 } 364 365 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 366 { 367 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 368 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 369 370 dsi_div /= ctx->dsi->lanes; 371 372 if (!ctx->lvds_dual_link) 373 dsi_div /= 2; 374 375 return dsi_div - 1; 376 } 377 378 static int sn65dsi83_reset_pipe(struct sn65dsi83 *sn65dsi83) 379 { 380 struct drm_modeset_acquire_ctx ctx; 381 int err; 382 383 /* 384 * Reset active outputs of the related CRTC. 385 * 386 * This way, drm core will reconfigure each components in the CRTC 387 * outputs path. In our case, this will force the previous component to 388 * go back in LP11 mode and so allow the reconfiguration of SN65DSI83 389 * bridge. 390 * 391 * Keep the lock during the whole operation to be atomic. 392 */ 393 394 drm_modeset_acquire_init(&ctx, 0); 395 396 dev_warn(sn65dsi83->dev, "reset the pipe\n"); 397 398 retry: 399 err = drm_bridge_helper_reset_crtc(&sn65dsi83->bridge, &ctx); 400 if (err == -EDEADLK) { 401 drm_modeset_backoff(&ctx); 402 goto retry; 403 } 404 405 drm_modeset_drop_locks(&ctx); 406 drm_modeset_acquire_fini(&ctx); 407 408 return err; 409 } 410 411 static void sn65dsi83_reset_work(struct work_struct *ws) 412 { 413 struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work); 414 int ret; 415 int idx; 416 417 if (!drm_bridge_enter(&ctx->bridge, &idx)) 418 return; 419 420 /* Reset the pipe */ 421 ret = sn65dsi83_reset_pipe(ctx); 422 if (ret) { 423 dev_err(ctx->dev, "reset pipe failed %pe\n", ERR_PTR(ret)); 424 goto bridge_exit; 425 } 426 427 if (ctx->irq) 428 enable_irq(ctx->irq); 429 430 bridge_exit: 431 drm_bridge_exit(idx); 432 } 433 434 static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx) 435 { 436 unsigned int irq_stat; 437 int ret; 438 int idx; 439 440 if (!drm_bridge_enter(&ctx->bridge, &idx)) 441 return; 442 443 /* 444 * Schedule a reset in case of: 445 * - the bridge doesn't answer 446 * - the bridge signals an error 447 */ 448 449 ret = regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat); 450 451 /* 452 * Some hardware (Toradex Verdin AM62) is known to report the 453 * PLL_UNLOCK error interrupt while working without visible 454 * problems. In lack of a reliable way to discriminate such cases 455 * from user-visible PLL_UNLOCK cases, ignore that bit entirely. 456 */ 457 if (ret || irq_stat & ~REG_IRQ_STAT_CHA_PLL_UNLOCK) { 458 /* 459 * IRQ acknowledged is not always possible (the bridge can be in 460 * a state where it doesn't answer anymore). To prevent an 461 * interrupt storm, disable interrupt. The interrupt will be 462 * after the reset. 463 */ 464 if (ctx->irq) 465 disable_irq_nosync(ctx->irq); 466 467 schedule_work(&ctx->reset_work); 468 } 469 470 drm_bridge_exit(idx); 471 } 472 473 static void sn65dsi83_monitor_work(struct work_struct *work) 474 { 475 struct sn65dsi83 *ctx = container_of(to_delayed_work(work), 476 struct sn65dsi83, monitor_work); 477 478 sn65dsi83_handle_errors(ctx); 479 480 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000)); 481 } 482 483 static void sn65dsi83_monitor_start(struct sn65dsi83 *ctx) 484 { 485 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000)); 486 } 487 488 static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx) 489 { 490 cancel_delayed_work_sync(&ctx->monitor_work); 491 } 492 493 /* 494 * Release resources taken by sn65dsi83_atomic_pre_enable(). 495 * 496 * Invoked by sn65dsi83_atomic_disable() normally, or by devres after 497 * sn65dsi83_remove() in case this happens befora atomic_disable. 498 */ 499 static void sn65dsi83_release_resources(void *data) 500 { 501 struct sn65dsi83 *ctx = (struct sn65dsi83 *)data; 502 int ret; 503 504 if (ctx->irq) { 505 /* Disable irq */ 506 regmap_write(ctx->regmap, REG_IRQ_EN, 0x0); 507 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0); 508 } else { 509 /* Stop the polling task */ 510 sn65dsi83_monitor_stop(ctx); 511 } 512 513 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 514 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 515 usleep_range(10000, 11000); 516 517 ret = regulator_disable(ctx->vcc); 518 if (ret) 519 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret); 520 521 regcache_mark_dirty(ctx->regmap); 522 } 523 524 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, 525 struct drm_atomic_commit *state) 526 { 527 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 528 const unsigned int dual_factor = ctx->lvds_dual_link ? 2 : 1; 529 const struct drm_bridge_state *bridge_state; 530 const struct drm_crtc_state *crtc_state; 531 const struct drm_display_mode *mode; 532 struct drm_connector *connector; 533 struct drm_crtc *crtc; 534 bool test_pattern = sn65dsi83_test_pattern; 535 bool lvds_format_24bpp; 536 bool lvds_format_jeida; 537 unsigned int pval; 538 __le16 le16val; 539 u16 val; 540 int ret; 541 int idx; 542 543 if (!drm_bridge_enter(bridge, &idx)) 544 return; 545 546 ret = regulator_enable(ctx->vcc); 547 if (ret) { 548 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret); 549 goto err_exit; 550 } 551 552 /* Deassert reset */ 553 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 554 usleep_range(10000, 11000); 555 556 /* Get the LVDS format from the bridge state. */ 557 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 558 559 switch (bridge_state->output_bus_cfg.format) { 560 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 561 lvds_format_24bpp = false; 562 lvds_format_jeida = true; 563 break; 564 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 565 lvds_format_24bpp = true; 566 lvds_format_jeida = true; 567 break; 568 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 569 lvds_format_24bpp = true; 570 lvds_format_jeida = false; 571 break; 572 default: 573 /* 574 * Some bridges still don't set the correct 575 * LVDS bus pixel format, use SPWG24 default 576 * format until those are fixed. 577 */ 578 lvds_format_24bpp = true; 579 lvds_format_jeida = false; 580 dev_warn(ctx->dev, 581 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 582 bridge_state->output_bus_cfg.format); 583 break; 584 } 585 586 /* 587 * Retrieve the CRTC adjusted mode. This requires a little dance to go 588 * from the bridge to the encoder, to the connector and to the CRTC. 589 */ 590 connector = drm_atomic_get_new_connector_for_encoder(state, 591 bridge->encoder); 592 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 593 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 594 mode = &crtc_state->adjusted_mode; 595 596 /* Clear reset, disable PLL */ 597 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 598 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 599 600 /* Reference clock derived from DSI link clock. */ 601 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 602 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) | 603 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 604 regmap_write(ctx->regmap, REG_DSI_CLK, 605 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode))); 606 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 607 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 608 609 /* Set number of DSI lanes and LVDS link config. */ 610 regmap_write(ctx->regmap, REG_DSI_LANE, 611 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 612 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) | 613 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 614 REG_DSI_LANE_CHB_DSI_LANES(3)); 615 /* No equalization. */ 616 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 617 618 /* Set up sync signal polarity. */ 619 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 620 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 621 (mode->flags & DRM_MODE_FLAG_NVSYNC ? 622 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 623 val |= bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW ? 624 REG_LVDS_FMT_DE_NEG_POLARITY : 0; 625 626 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 627 if (lvds_format_24bpp) { 628 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 629 if (ctx->lvds_dual_link) 630 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 631 } 632 633 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 634 if (lvds_format_jeida) { 635 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 636 if (ctx->lvds_dual_link) 637 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 638 } 639 640 /* Set up LVDS output config (DSI84,DSI85) */ 641 if (!ctx->lvds_dual_link) 642 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 643 644 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 645 regmap_write(ctx->regmap, REG_LVDS_VCOM, 646 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) | 647 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B])); 648 regmap_write(ctx->regmap, REG_LVDS_LANE, 649 (ctx->lvds_channel_swap ? 650 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 651 (ctx->lvds_term_conf[CHANNEL_A] ? 652 REG_LVDS_LANE_CHA_LVDS_TERM : 0) | 653 (ctx->lvds_term_conf[CHANNEL_B] ? 654 REG_LVDS_LANE_CHB_LVDS_TERM : 0)); 655 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 656 657 /* 658 * Active line length needs to be halved for test pattern 659 * generation in dual LVDS output. 660 */ 661 le16val = cpu_to_le16(mode->hdisplay / (test_pattern ? dual_factor : 1)); 662 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 663 &le16val, 2); 664 le16val = cpu_to_le16(mode->vdisplay); 665 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 666 &le16val, 2); 667 /* 32 + 1 pixel clock to ensure proper operation */ 668 le16val = cpu_to_le16(32 + 1); 669 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); 670 le16val = cpu_to_le16((mode->hsync_end - mode->hsync_start) / dual_factor); 671 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 672 &le16val, 2); 673 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start); 674 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 675 &le16val, 2); 676 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 677 (mode->htotal - mode->hsync_end) / dual_factor); 678 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 679 mode->vtotal - mode->vsync_end); 680 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 681 (mode->hsync_start - mode->hdisplay) / dual_factor); 682 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 683 mode->vsync_start - mode->vdisplay); 684 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 685 test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0); 686 687 /* Enable PLL */ 688 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 689 usleep_range(3000, 4000); 690 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 691 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 692 1000, 100000); 693 if (ret) { 694 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 695 /* On failure, disable PLL again and exit. */ 696 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 697 goto err_add_action; 698 } 699 700 /* Trigger reset after CSR register update. */ 701 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 702 703 /* Wait for 10ms after soft reset as specified in datasheet */ 704 usleep_range(10000, 12000); 705 706 err_add_action: 707 devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx); 708 err_exit: 709 drm_bridge_exit(idx); 710 } 711 712 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, 713 struct drm_atomic_commit *state) 714 { 715 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 716 unsigned int pval; 717 int idx; 718 719 if (!drm_bridge_enter(bridge, &idx)) 720 return; 721 722 /* Clear all errors that got asserted during initialization. */ 723 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 724 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 725 726 /* Wait for 1ms and check for errors in status register */ 727 usleep_range(1000, 1100); 728 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 729 if (pval) 730 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval); 731 732 if (ctx->irq) { 733 /* Enable irq to detect errors */ 734 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, REG_IRQ_GLOBAL_IRQ_EN); 735 regmap_write(ctx->regmap, REG_IRQ_EN, 0xff & ~REG_IRQ_EN_CHA_PLL_UNLOCK_EN); 736 } else { 737 /* Use the polling task */ 738 sn65dsi83_monitor_start(ctx); 739 } 740 741 drm_bridge_exit(idx); 742 } 743 744 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, 745 struct drm_atomic_commit *state) 746 { 747 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 748 int idx; 749 750 if (!drm_bridge_enter(bridge, &idx)) 751 return; 752 753 devm_release_action(ctx->dev, sn65dsi83_release_resources, ctx); 754 755 drm_bridge_exit(idx); 756 } 757 758 static enum drm_mode_status 759 sn65dsi83_mode_valid(struct drm_bridge *bridge, 760 const struct drm_display_info *info, 761 const struct drm_display_mode *mode) 762 { 763 /* LVDS output clock range 25..154 MHz */ 764 if (mode->clock < 25000) 765 return MODE_CLOCK_LOW; 766 if (mode->clock > 154000) 767 return MODE_CLOCK_HIGH; 768 769 return MODE_OK; 770 } 771 772 #define MAX_INPUT_SEL_FORMATS 1 773 774 static u32 * 775 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 776 struct drm_bridge_state *bridge_state, 777 struct drm_crtc_state *crtc_state, 778 struct drm_connector_state *conn_state, 779 u32 output_fmt, 780 unsigned int *num_input_fmts) 781 { 782 u32 *input_fmts; 783 784 *num_input_fmts = 0; 785 786 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 787 GFP_KERNEL); 788 if (!input_fmts) 789 return NULL; 790 791 /* This is the DSI-end bus format */ 792 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 793 *num_input_fmts = 1; 794 795 return input_fmts; 796 } 797 798 static const struct drm_bridge_funcs sn65dsi83_funcs = { 799 .attach = sn65dsi83_attach, 800 .detach = sn65dsi83_detach, 801 .atomic_enable = sn65dsi83_atomic_enable, 802 .atomic_pre_enable = sn65dsi83_atomic_pre_enable, 803 .atomic_disable = sn65dsi83_atomic_disable, 804 .mode_valid = sn65dsi83_mode_valid, 805 806 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 807 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 808 .atomic_create_state = drm_atomic_helper_bridge_create_state, 809 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, 810 }; 811 812 static int sn65dsi83_select_lvds_vod_swing(struct device *dev, 813 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term) 814 { 815 int i; 816 817 for (i = 0; i <= 3; i++) { 818 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] && 819 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] && 820 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] && 821 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1]) 822 return i; 823 } 824 825 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n"); 826 return -EINVAL; 827 } 828 829 static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel) 830 { 831 struct device *dev = ctx->dev; 832 int endpoint_reg = (channel == CHANNEL_A) ? 2 : 3; 833 struct device_node *endpoint __free(device_node) = 834 of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1); 835 /* Set so the property can be freely selected if not defined */ 836 u32 lvds_vod_swing_data[2] = { 0, 1000000 }; 837 u32 lvds_vod_swing_clk[2] = { 0, 1000000 }; 838 /* Set default near end terminataion to 200 Ohm */ 839 u32 lvds_term = 200; 840 int lvds_vod_swing_conf; 841 int ret_data; 842 int ret_clock; 843 844 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term); 845 if (lvds_term == 100) 846 ctx->lvds_term_conf[channel] = OHM_100; 847 else if (lvds_term == 200) 848 ctx->lvds_term_conf[channel] = OHM_200; 849 else 850 return -EINVAL; 851 852 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt", 853 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data)); 854 if (ret_data != 0 && ret_data != -EINVAL) 855 return ret_data; 856 857 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt", 858 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk)); 859 if (ret_clock != 0 && ret_clock != -EINVAL) 860 return ret_clock; 861 862 /* Use default value if both properties are NOT defined. */ 863 if (ret_data == -EINVAL && ret_clock == -EINVAL) 864 lvds_vod_swing_conf = 0x1; 865 866 /* Use lookup table if any of the two properties is defined. */ 867 if (!ret_data || !ret_clock) { 868 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data, 869 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]); 870 if (lvds_vod_swing_conf < 0) 871 return lvds_vod_swing_conf; 872 } 873 874 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf; 875 876 return 0; 877 } 878 879 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 880 { 881 struct drm_bridge *panel_bridge; 882 struct device *dev = ctx->dev; 883 u32 output_port = 2; 884 int ret; 885 886 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A); 887 if (ret < 0) 888 return ret; 889 890 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B); 891 if (ret < 0) 892 return ret; 893 894 ctx->lvds_dual_link = false; 895 ctx->lvds_channel_swap = false; 896 if (model != MODEL_SN65DSI83) { 897 struct device_node *port0, *port1, *port2, *port3; 898 int dual_link; 899 900 port0 = of_graph_get_port_by_id(dev->of_node, 0); 901 port1 = of_graph_get_port_by_id(dev->of_node, 1); 902 port2 = of_graph_get_port_by_id(dev->of_node, 2); 903 port3 = of_graph_get_port_by_id(dev->of_node, 3); 904 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 905 906 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 907 /* Odd pixels to LVDS Channel A, even pixels to B */ 908 ctx->lvds_dual_link = true; 909 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 910 /* Even pixels to LVDS Channel A, odd pixels to B */ 911 ctx->lvds_dual_link = true; 912 ctx->lvds_channel_swap = true; 913 } else if (port0 && !port1 && port2 && !port3) { 914 /* DSI Channel A to LVDS Channel A */ 915 } else if (port0 && !port1 && !port2 && port3) { 916 /* DSI Channel A to LVDS Channel B */ 917 ctx->lvds_channel_swap = true; 918 output_port = 3; 919 } 920 of_node_put(port0); 921 of_node_put(port1); 922 of_node_put(port2); 923 of_node_put(port3); 924 } 925 926 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, output_port, 0); 927 if (IS_ERR(panel_bridge)) 928 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n"); 929 930 ctx->panel_bridge = panel_bridge; 931 932 ctx->vcc = devm_regulator_get(dev, "vcc"); 933 if (IS_ERR(ctx->vcc)) 934 return dev_err_probe(dev, PTR_ERR(ctx->vcc), 935 "Failed to get supply 'vcc'\n"); 936 937 return 0; 938 } 939 940 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) 941 { 942 struct device *dev = ctx->dev; 943 struct device_node *host_node; 944 struct device_node *endpoint; 945 struct mipi_dsi_device *dsi; 946 struct mipi_dsi_host *host; 947 const struct mipi_dsi_device_info info = { 948 .type = "sn65dsi83", 949 .channel = 0, 950 .node = NULL, 951 }; 952 int dsi_lanes, ret; 953 954 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 955 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); 956 host_node = of_graph_get_remote_port_parent(endpoint); 957 host = of_find_mipi_dsi_host_by_node(host_node); 958 of_node_put(host_node); 959 of_node_put(endpoint); 960 961 if (!host) 962 return -EPROBE_DEFER; 963 964 if (dsi_lanes < 0) 965 return dsi_lanes; 966 967 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 968 if (IS_ERR(dsi)) 969 return dev_err_probe(dev, PTR_ERR(dsi), 970 "failed to create dsi device\n"); 971 972 ctx->dsi = dsi; 973 974 dsi->lanes = dsi_lanes; 975 dsi->format = MIPI_DSI_FMT_RGB888; 976 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 977 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET; 978 979 ret = devm_mipi_dsi_attach(dev, dsi); 980 if (ret < 0) { 981 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 982 return ret; 983 } 984 985 return 0; 986 } 987 988 static irqreturn_t sn65dsi83_irq(int irq, void *data) 989 { 990 struct sn65dsi83 *ctx = data; 991 992 sn65dsi83_handle_errors(ctx); 993 return IRQ_HANDLED; 994 } 995 996 static int sn65dsi83_probe(struct i2c_client *client) 997 { 998 const struct i2c_device_id *id = i2c_client_get_device_id(client); 999 struct device *dev = &client->dev; 1000 enum sn65dsi83_model model; 1001 struct sn65dsi83 *ctx; 1002 int ret; 1003 1004 ctx = devm_drm_bridge_alloc(dev, struct sn65dsi83, bridge, &sn65dsi83_funcs); 1005 if (IS_ERR(ctx)) 1006 return PTR_ERR(ctx); 1007 1008 ctx->dev = dev; 1009 INIT_WORK(&ctx->reset_work, sn65dsi83_reset_work); 1010 INIT_DELAYED_WORK(&ctx->monitor_work, sn65dsi83_monitor_work); 1011 1012 if (dev->of_node) { 1013 model = (enum sn65dsi83_model)(uintptr_t) 1014 of_device_get_match_data(dev); 1015 } else { 1016 model = id->driver_data; 1017 } 1018 1019 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 1020 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable", 1021 GPIOD_OUT_LOW); 1022 if (IS_ERR(ctx->enable_gpio)) 1023 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n"); 1024 1025 usleep_range(10000, 11000); 1026 1027 ret = sn65dsi83_parse_dt(ctx, model); 1028 if (ret) 1029 return ret; 1030 1031 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 1032 if (IS_ERR(ctx->regmap)) 1033 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n"); 1034 1035 if (client->irq) { 1036 ctx->irq = client->irq; 1037 ret = devm_request_threaded_irq(ctx->dev, ctx->irq, NULL, sn65dsi83_irq, 1038 IRQF_ONESHOT, dev_name(ctx->dev), ctx); 1039 if (ret) 1040 return ret; 1041 } 1042 1043 dev_set_drvdata(dev, ctx); 1044 i2c_set_clientdata(client, ctx); 1045 1046 ctx->bridge.of_node = dev->of_node; 1047 ctx->bridge.pre_enable_prev_first = true; 1048 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS; 1049 drm_bridge_add(&ctx->bridge); 1050 1051 ret = sn65dsi83_host_attach(ctx); 1052 if (ret) { 1053 dev_err_probe(dev, ret, "failed to attach DSI host\n"); 1054 goto err_remove_bridge; 1055 } 1056 1057 return 0; 1058 1059 err_remove_bridge: 1060 drm_bridge_remove(&ctx->bridge); 1061 return ret; 1062 } 1063 1064 static void sn65dsi83_remove(struct i2c_client *client) 1065 { 1066 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 1067 1068 drm_bridge_unplug(&ctx->bridge); 1069 } 1070 1071 static const struct i2c_device_id sn65dsi83_id[] = { 1072 { .name = "ti,sn65dsi83", .driver_data = MODEL_SN65DSI83 }, 1073 { .name = "ti,sn65dsi84", .driver_data = MODEL_SN65DSI84 }, 1074 { } 1075 }; 1076 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 1077 1078 static const struct of_device_id sn65dsi83_match_table[] = { 1079 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 1080 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 1081 {}, 1082 }; 1083 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 1084 1085 static struct i2c_driver sn65dsi83_driver = { 1086 .probe = sn65dsi83_probe, 1087 .remove = sn65dsi83_remove, 1088 .id_table = sn65dsi83_id, 1089 .driver = { 1090 .name = "sn65dsi83", 1091 .of_match_table = sn65dsi83_match_table, 1092 }, 1093 }; 1094 module_i2c_driver(sn65dsi83_driver); 1095 1096 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 1097 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 1098 MODULE_LICENSE("GPL v2"); 1099