xref: /linux/arch/sparc/include/asm/trap_block.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _SPARC_TRAP_BLOCK_H
3 #define _SPARC_TRAP_BLOCK_H
4 
5 #include <linux/threads.h>
6 
7 #include <asm/hypervisor.h>
8 #include <asm/asi.h>
9 
10 #ifndef __ASSEMBLY__
11 
12 /* Trap handling code needs to get at a few critical values upon
13  * trap entry and to process TSB misses.  These cannot be in the
14  * per_cpu() area as we really need to lock them into the TLB and
15  * thus make them part of the main kernel image.  As a result we
16  * try to make this as small as possible.
17  *
18  * This is padded out and aligned to 64-bytes to avoid false sharing
19  * on SMP.
20  */
21 
22 /* If you modify the size of this structure, please update
23  * TRAP_BLOCK_SZ_SHIFT below.
24  */
25 struct thread_info;
26 struct trap_per_cpu {
27 /* D-cache line 1: Basic thread information, cpu and device mondo queues */
28 	struct thread_info	*thread;
29 	unsigned long		pgd_paddr;
30 	unsigned long		cpu_mondo_pa;
31 	unsigned long		dev_mondo_pa;
32 
33 /* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
34 	unsigned long		resum_mondo_pa;
35 	unsigned long		resum_kernel_buf_pa;
36 	unsigned long		nonresum_mondo_pa;
37 	unsigned long		nonresum_kernel_buf_pa;
38 
39 /* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
40 	struct hv_fault_status	fault_info;
41 
42 /* Dcache line 7: Physical addresses of CPU send mondo block and CPU list.  */
43 	unsigned long		cpu_mondo_block_pa;
44 	unsigned long		cpu_list_pa;
45 	unsigned long		tsb_huge;
46 	unsigned long		tsb_huge_temp;
47 
48 /* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
49 	unsigned long		irq_worklist_pa;
50 	unsigned int		cpu_mondo_qmask;
51 	unsigned int		dev_mondo_qmask;
52 	unsigned int		resum_qmask;
53 	unsigned int		nonresum_qmask;
54 	unsigned long		__per_cpu_base;
55 } __attribute__((aligned(64)));
56 extern struct trap_per_cpu trap_block[NR_CPUS];
57 void init_cur_cpu_trap(struct thread_info *);
58 void setup_tba(void);
59 extern int ncpus_probed;
60 extern u64 cpu_mondo_counter[NR_CPUS];
61 
62 unsigned long real_hard_smp_processor_id(void);
63 
64 struct cpuid_patch_entry {
65 	unsigned int	addr;
66 	unsigned int	cheetah_safari[4];
67 	unsigned int	cheetah_jbus[4];
68 	unsigned int	starfire[4];
69 	unsigned int	sun4v[4];
70 };
71 extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
72 
73 struct sun4v_1insn_patch_entry {
74 	unsigned int	addr;
75 	unsigned int	insn;
76 };
77 extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
78 	__sun4v_1insn_patch_end;
79 extern struct sun4v_1insn_patch_entry __fast_win_ctrl_1insn_patch,
80 	__fast_win_ctrl_1insn_patch_end;
81 extern struct sun4v_1insn_patch_entry __sun_m7_1insn_patch,
82 	__sun_m7_1insn_patch_end;
83 
84 struct sun4v_2insn_patch_entry {
85 	unsigned int	addr;
86 	unsigned int	insns[2];
87 };
88 extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
89 	__sun4v_2insn_patch_end;
90 extern struct sun4v_2insn_patch_entry __sun_m7_2insn_patch,
91 	__sun_m7_2insn_patch_end;
92 
93 
94 #endif /* !(__ASSEMBLY__) */
95 
96 #define TRAP_PER_CPU_THREAD		0x00
97 #define TRAP_PER_CPU_PGD_PADDR		0x08
98 #define TRAP_PER_CPU_CPU_MONDO_PA	0x10
99 #define TRAP_PER_CPU_DEV_MONDO_PA	0x18
100 #define TRAP_PER_CPU_RESUM_MONDO_PA	0x20
101 #define TRAP_PER_CPU_RESUM_KBUF_PA	0x28
102 #define TRAP_PER_CPU_NONRESUM_MONDO_PA	0x30
103 #define TRAP_PER_CPU_NONRESUM_KBUF_PA	0x38
104 #define TRAP_PER_CPU_FAULT_INFO		0x40
105 #define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA	0xc0
106 #define TRAP_PER_CPU_CPU_LIST_PA	0xc8
107 #define TRAP_PER_CPU_TSB_HUGE		0xd0
108 #define TRAP_PER_CPU_TSB_HUGE_TEMP	0xd8
109 #define TRAP_PER_CPU_IRQ_WORKLIST_PA	0xe0
110 #define TRAP_PER_CPU_CPU_MONDO_QMASK	0xe8
111 #define TRAP_PER_CPU_DEV_MONDO_QMASK	0xec
112 #define TRAP_PER_CPU_RESUM_QMASK	0xf0
113 #define TRAP_PER_CPU_NONRESUM_QMASK	0xf4
114 #define TRAP_PER_CPU_PER_CPU_BASE	0xf8
115 
116 #define TRAP_BLOCK_SZ_SHIFT		8
117 
118 #include <asm/scratchpad.h>
119 
120 #define __GET_CPUID(REG)				\
121 	/* Spitfire implementation (default). */	\
122 661:	ldxa		[%g0] ASI_UPA_CONFIG, REG;	\
123 	srlx		REG, 17, REG;			\
124 	 and		REG, 0x1f, REG;			\
125 	nop;						\
126 	.section	.cpuid_patch, "ax";		\
127 	/* Instruction location. */			\
128 	.word		661b;				\
129 	/* Cheetah Safari implementation. */		\
130 	ldxa		[%g0] ASI_SAFARI_CONFIG, REG;	\
131 	srlx		REG, 17, REG;			\
132 	and		REG, 0x3ff, REG;		\
133 	nop;						\
134 	/* Cheetah JBUS implementation. */		\
135 	ldxa		[%g0] ASI_JBUS_CONFIG, REG;	\
136 	srlx		REG, 17, REG;			\
137 	and		REG, 0x1f, REG;			\
138 	nop;						\
139 	/* Starfire implementation. */			\
140 	sethi		%hi(0x1fff40000d0 >> 9), REG;	\
141 	sllx		REG, 9, REG;			\
142 	or		REG, 0xd0, REG;			\
143 	lduwa		[REG] ASI_PHYS_BYPASS_EC_E, REG;\
144 	/* sun4v implementation. */			\
145 	mov		SCRATCHPAD_CPUID, REG;		\
146 	ldxa		[REG] ASI_SCRATCHPAD, REG;	\
147 	nop;						\
148 	nop;						\
149 	.previous;
150 
151 #ifdef CONFIG_SMP
152 
153 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
154 	__GET_CPUID(TMP)			\
155 	sethi	%hi(trap_block), DEST;		\
156 	sllx	TMP, TRAP_BLOCK_SZ_SHIFT, TMP;	\
157 	or	DEST, %lo(trap_block), DEST;	\
158 	add	DEST, TMP, DEST;		\
159 
160 /* Clobbers TMP, current address space PGD phys address into DEST.  */
161 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)		\
162 	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
163 	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
164 
165 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
166 #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)	\
167 	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
168 	add	DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
169 
170 /* Clobbers TMP, loads DEST with current thread info pointer.  */
171 #define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
172 	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
173 	ldx	[DEST + TRAP_PER_CPU_THREAD], DEST;
174 
175 /* Given the current thread info pointer in THR, load the per-cpu
176  * area base of the current processor into DEST.  REG1, REG2, and REG3 are
177  * clobbered.
178  *
179  * You absolutely cannot use DEST as a temporary in this code.  The
180  * reason is that traps can happen during execution, and return from
181  * trap will load the fully resolved DEST per-cpu base.  This can corrupt
182  * the calculations done by the macro mid-stream.
183  */
184 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)	\
185 	lduh	[THR + TI_CPU], REG1;			\
186 	sethi	%hi(trap_block), REG2;			\
187 	sllx	REG1, TRAP_BLOCK_SZ_SHIFT, REG1;	\
188 	or	REG2, %lo(trap_block), REG2;		\
189 	add	REG2, REG1, REG2;			\
190 	ldx	[REG2 + TRAP_PER_CPU_PER_CPU_BASE], DEST;
191 
192 #else
193 
194 #define TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
195 	sethi	%hi(trap_block), DEST;		\
196 	or	DEST, %lo(trap_block), DEST;	\
197 
198 /* Uniprocessor versions, we know the cpuid is zero.  */
199 #define TRAP_LOAD_PGD_PHYS(DEST, TMP)		\
200 	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
201 	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
202 
203 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
204 #define TRAP_LOAD_IRQ_WORK_PA(DEST, TMP)	\
205 	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
206 	add	DEST, TRAP_PER_CPU_IRQ_WORKLIST_PA, DEST;
207 
208 #define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
209 	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
210 	ldx	[DEST + TRAP_PER_CPU_THREAD], DEST;
211 
212 /* No per-cpu areas on uniprocessor, so no need to load DEST.  */
213 #define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
214 
215 #endif /* !(CONFIG_SMP) */
216 
217 #endif /* _SPARC_TRAP_BLOCK_H */
218