1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin (yanmin.zhang@intel.com) 12 * Shaohua Li (shaohua.li@intel.com) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 #include <linux/args.h> 27 #include <linux/device-id/pci.h> 28 29 #include <linux/types.h> 30 #include <linux/sizes.h> 31 #include <linux/init.h> 32 #include <linux/ioport.h> 33 #include <linux/list.h> 34 #include <linux/compiler.h> 35 #include <linux/errno.h> 36 #include <linux/kobject.h> 37 #include <linux/atomic.h> 38 #include <linux/device.h> 39 #include <linux/interrupt.h> 40 #include <linux/io.h> 41 #include <linux/resource_ext.h> 42 #include <linux/msi_api.h> 43 #include <uapi/linux/pci.h> 44 45 #include <linux/pci_ids.h> 46 47 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 48 PCI_STATUS_SIG_SYSTEM_ERROR | \ 49 PCI_STATUS_REC_MASTER_ABORT | \ 50 PCI_STATUS_REC_TARGET_ABORT | \ 51 PCI_STATUS_SIG_TARGET_ABORT | \ 52 PCI_STATUS_PARITY) 53 54 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 55 #define PCI_NUM_RESET_METHODS 8 56 57 #define PCI_RESET_PROBE true 58 #define PCI_RESET_DO_RESET false 59 60 /* 61 * The PCI interface treats multi-function devices as independent 62 * devices. The slot/function address of each device is encoded 63 * in a single byte as follows: 64 * 65 * 7:3 = slot 66 * 2:0 = function 67 * 68 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 69 * In the interest of not exposing interfaces to user-space unnecessarily, 70 * the following kernel-only defines are being added here. 71 */ 72 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 73 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 74 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 75 76 /* 77 * PCI_SLOT_ALL_DEVICES indicates a slot that covers all devices on the bus. 78 * Used for PCIe hotplug where the physical slot is the entire secondary bus, 79 * and, if ARI Forwarding is enabled, functions may appear to be on multiple 80 * devices. 81 */ 82 #define PCI_SLOT_ALL_DEVICES 0xfeff 83 84 /* Used to identify a slot as a placeholder */ 85 #define PCI_SLOT_PLACEHOLDER 0xffff 86 87 /* pci_slot represents a physical slot */ 88 struct pci_slot { 89 struct pci_bus *bus; /* Bus this slot is on */ 90 struct list_head list; /* Node in list of slots */ 91 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 92 u16 number; /* Device nr, or PCI_SLOT_ALL_DEVICES */ 93 unsigned int per_func_slot:1; /* Allow per function slot */ 94 struct kobject kobj; 95 }; 96 97 static inline const char *pci_slot_name(const struct pci_slot *slot) 98 { 99 return kobject_name(&slot->kobj); 100 } 101 102 /* File state for mmap()s on /proc/bus/pci/X/Y */ 103 enum pci_mmap_state { 104 pci_mmap_io, 105 pci_mmap_mem 106 }; 107 108 /* For PCI devices, the region numbers are assigned this way: */ 109 enum { 110 /* #0-5: standard PCI resources */ 111 PCI_STD_RESOURCES, 112 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 113 114 /* #6: expansion ROM resource */ 115 PCI_ROM_RESOURCE, 116 117 /* Device-specific resources */ 118 #ifdef CONFIG_PCI_IOV 119 PCI_IOV_RESOURCES, 120 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 121 #endif 122 123 /* PCI-to-PCI (P2P) bridge windows */ 124 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 125 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 126 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 127 128 /* CardBus bridge windows */ 129 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 130 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 131 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 132 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 133 134 /* Total number of bridge resources for P2P and CardBus */ 135 #define PCI_P2P_BRIDGE_RESOURCE_NUM 3 136 #define PCI_BRIDGE_RESOURCE_NUM 4 137 138 /* Resources assigned to buses behind the bridge */ 139 PCI_BRIDGE_RESOURCES, 140 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 141 PCI_BRIDGE_RESOURCE_NUM - 1, 142 143 /* Total resources associated with a PCI device */ 144 PCI_NUM_RESOURCES, 145 146 /* Preserve this for compatibility */ 147 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 148 }; 149 150 /** 151 * enum pci_interrupt_pin - PCI INTx interrupt values 152 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 153 * @PCI_INTERRUPT_INTA: PCI INTA pin 154 * @PCI_INTERRUPT_INTB: PCI INTB pin 155 * @PCI_INTERRUPT_INTC: PCI INTC pin 156 * @PCI_INTERRUPT_INTD: PCI INTD pin 157 * 158 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 159 * PCI_INTERRUPT_PIN register. 160 */ 161 enum pci_interrupt_pin { 162 PCI_INTERRUPT_UNKNOWN, 163 PCI_INTERRUPT_INTA, 164 PCI_INTERRUPT_INTB, 165 PCI_INTERRUPT_INTC, 166 PCI_INTERRUPT_INTD, 167 }; 168 169 /* The number of legacy PCI INTx interrupts */ 170 #define PCI_NUM_INTX 4 171 172 /* 173 * Reading from a device that doesn't respond typically returns ~0. A 174 * successful read from a device may also return ~0, so you need additional 175 * information to reliably identify errors. 176 */ 177 #define PCI_ERROR_RESPONSE (~0ULL) 178 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 179 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 180 181 /* 182 * pci_power_t values must match the bits in the Capabilities PME_Support 183 * and Control/Status PowerState fields in the Power Management capability. 184 */ 185 typedef int __bitwise pci_power_t; 186 187 #define PCI_D0 ((pci_power_t __force) 0) 188 #define PCI_D1 ((pci_power_t __force) 1) 189 #define PCI_D2 ((pci_power_t __force) 2) 190 #define PCI_D3hot ((pci_power_t __force) 3) 191 #define PCI_D3cold ((pci_power_t __force) 4) 192 #define PCI_UNKNOWN ((pci_power_t __force) 5) 193 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 194 195 /* Remember to update this when the list above changes! */ 196 extern const char *pci_power_names[]; 197 198 static inline const char *pci_power_name(pci_power_t state) 199 { 200 return pci_power_names[1 + (__force int) state]; 201 } 202 203 /** 204 * typedef pci_channel_state_t 205 * 206 * The pci_channel state describes connectivity between the CPU and 207 * the PCI device. If some PCI bus between here and the PCI device 208 * has crashed or locked up, this info is reflected here. 209 */ 210 typedef unsigned int __bitwise pci_channel_state_t; 211 212 enum { 213 /* I/O channel is in normal state */ 214 pci_channel_io_normal = (__force pci_channel_state_t) 1, 215 216 /* I/O to channel is blocked */ 217 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 218 219 /* PCI card is dead */ 220 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 221 }; 222 223 typedef unsigned int __bitwise pcie_reset_state_t; 224 225 enum pcie_reset_state { 226 /* Reset is NOT asserted (Use to deassert reset) */ 227 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 228 229 /* Use #PERST to reset PCIe device */ 230 pcie_warm_reset = (__force pcie_reset_state_t) 2, 231 232 /* Use PCIe Hot Reset to reset device */ 233 pcie_hot_reset = (__force pcie_reset_state_t) 3 234 }; 235 236 typedef unsigned short __bitwise pci_dev_flags_t; 237 enum pci_dev_flags { 238 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 239 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 240 /* Device configuration is irrevocably lost if disabled into D3 */ 241 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 242 /* Provide indication device is assigned by a Virtual Machine Manager */ 243 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 244 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 245 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 246 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 247 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 248 /* Do not use bus resets for device */ 249 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 250 /* Do not use PM reset even if device advertises NoSoftRst- */ 251 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 252 /* Get VPD from function 0 VPD */ 253 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 254 /* A non-root bridge where translation occurs, stop alias search here */ 255 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 256 /* Do not use FLR even if device advertises PCI_AF_CAP */ 257 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 258 /* Don't use Relaxed Ordering for TLPs directed at this device */ 259 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 260 /* Device does honor MSI masking despite saying otherwise */ 261 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 262 /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */ 263 PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13), 264 /* 265 * PCIe to PCI bridge does not create RID aliases because the bridge is 266 * integrated with the downstream devices and doesn't use real PCI. 267 */ 268 PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), 269 }; 270 271 enum pci_irq_reroute_variant { 272 INTEL_IRQ_REROUTE_VARIANT = 1, 273 MAX_IRQ_REROUTE_VARIANTS = 3 274 }; 275 276 typedef unsigned short __bitwise pci_bus_flags_t; 277 enum pci_bus_flags { 278 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 279 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 280 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 281 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 282 }; 283 284 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 285 enum pcie_link_width { 286 PCIE_LNK_WIDTH_RESRV = 0x00, 287 PCIE_LNK_X1 = 0x01, 288 PCIE_LNK_X2 = 0x02, 289 PCIE_LNK_X4 = 0x04, 290 PCIE_LNK_X8 = 0x08, 291 PCIE_LNK_X12 = 0x0c, 292 PCIE_LNK_X16 = 0x10, 293 PCIE_LNK_X32 = 0x20, 294 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 295 }; 296 297 /* See matching string table in pci_speed_string() */ 298 enum pci_bus_speed { 299 PCI_SPEED_33MHz = 0x00, 300 PCI_SPEED_66MHz = 0x01, 301 PCI_SPEED_66MHz_PCIX = 0x02, 302 PCI_SPEED_100MHz_PCIX = 0x03, 303 PCI_SPEED_133MHz_PCIX = 0x04, 304 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 305 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 306 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 307 PCI_SPEED_66MHz_PCIX_266 = 0x09, 308 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 309 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 310 AGP_UNKNOWN = 0x0c, 311 AGP_1X = 0x0d, 312 AGP_2X = 0x0e, 313 AGP_4X = 0x0f, 314 AGP_8X = 0x10, 315 PCI_SPEED_66MHz_PCIX_533 = 0x11, 316 PCI_SPEED_100MHz_PCIX_533 = 0x12, 317 PCI_SPEED_133MHz_PCIX_533 = 0x13, 318 PCIE_SPEED_2_5GT = 0x14, 319 PCIE_SPEED_5_0GT = 0x15, 320 PCIE_SPEED_8_0GT = 0x16, 321 PCIE_SPEED_16_0GT = 0x17, 322 PCIE_SPEED_32_0GT = 0x18, 323 PCIE_SPEED_64_0GT = 0x19, 324 PCI_SPEED_UNKNOWN = 0xff, 325 }; 326 327 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 328 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 329 330 struct pci_vpd { 331 struct mutex lock; 332 unsigned int len; 333 u8 cap; 334 }; 335 336 struct irq_affinity; 337 struct pcie_bwctrl_data; 338 struct pcie_link_state; 339 struct pci_sriov; 340 struct pci_p2pdma; 341 struct rcec_ea; 342 343 /* struct pci_dev - describes a PCI device 344 * 345 * @supported_speeds: PCIe Supported Link Speeds Vector (+ reserved 0 at 346 * LSB). 0 when the supported speeds cannot be 347 * determined (e.g., for Root Complex Integrated 348 * Endpoints without the relevant Capability 349 * Registers). 350 * @is_hotplug_bridge: Hotplug bridge of any kind (e.g. PCIe Hot-Plug Capable, 351 * Conventional PCI Hot-Plug, ACPI slot). 352 * Such bridges are allocated additional MMIO and bus 353 * number resources to allow for hierarchy expansion. 354 * @is_pciehp: PCIe Hot-Plug Capable bridge. 355 */ 356 struct pci_dev { 357 struct list_head bus_list; /* Node in per-bus list */ 358 struct pci_bus *bus; /* Bus this device is on */ 359 struct pci_bus *subordinate; /* Bus this device bridges to */ 360 361 void *sysdata; /* Hook for sys-specific extension */ 362 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 363 struct pci_slot *slot; /* Physical slot this device is in */ 364 365 unsigned int devfn; /* Encoded device & function index */ 366 unsigned short vendor; 367 unsigned short device; 368 unsigned short subsystem_vendor; 369 unsigned short subsystem_device; 370 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 371 u8 revision; /* PCI revision, low byte of class word */ 372 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 373 #ifdef CONFIG_PCIEAER 374 u16 aer_cap; /* AER capability offset */ 375 struct aer_info *aer_info; /* AER info for this device */ 376 #endif 377 #ifdef CONFIG_PCIEPORTBUS 378 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 379 struct pci_dev *rcec; /* Associated RCEC device */ 380 #endif 381 u32 devcap; /* PCIe Device Capabilities */ 382 u16 rebar_cap; /* Resizable BAR capability offset */ 383 u8 pcie_cap; /* PCIe capability offset */ 384 u8 msi_cap; /* MSI capability offset */ 385 u8 msix_cap; /* MSI-X capability offset */ 386 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 387 u8 rom_base_reg; /* Config register controlling ROM */ 388 u8 pin; /* Interrupt pin this device uses */ 389 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 390 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 391 392 struct pci_driver *driver; /* Driver bound to this device */ 393 u64 dma_mask; /* Mask of the bits of bus address this 394 device implements. Normally this is 395 0xffffffff. You only need to change 396 this if your device has broken DMA 397 or supports 64-bit transfers. */ 398 u64 msi_addr_mask; /* Mask of the bits of bus address for 399 MSI that this device implements. 400 Normally set based on device 401 capabilities. You only need to 402 change this if your device claims 403 to support 64-bit MSI but implements 404 fewer than 64 address bits. */ 405 406 struct device_dma_parameters dma_parms; 407 408 pci_power_t current_state; /* Current operating state. In ACPI, 409 this is D0-D3, D0 being fully 410 functional, and D3 being off. */ 411 u8 pm_cap; /* PM capability offset */ 412 unsigned int pme_support:5; /* Bitmask of states from which PME# 413 can be generated */ 414 unsigned int pme_poll:1; /* Poll device's PME status bit */ 415 unsigned int pinned:1; /* Whether this dev is pinned */ 416 unsigned int config_rrs_sv:1; /* Config RRS software visibility */ 417 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 418 unsigned int d1_support:1; /* Low power state D1 is supported */ 419 unsigned int d2_support:1; /* Low power state D2 is supported */ 420 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 421 unsigned int no_d3cold:1; /* D3cold is forbidden */ 422 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 423 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 424 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 425 decoding during BAR sizing */ 426 unsigned int wakeup_prepared:1; 427 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 428 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 429 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 430 controlled exclusively by 431 user sysfs */ 432 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 433 bit manually */ 434 unsigned int no_bw_notif:1; /* BW notifications may cause issues */ 435 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 436 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 437 438 u16 l1ss; /* L1SS Capability pointer */ 439 #ifdef CONFIG_PCIEASPM 440 struct pcie_link_state *link_state; /* ASPM link state */ 441 unsigned int aspm_l0s_support:1; /* ASPM L0s support */ 442 unsigned int aspm_l1_support:1; /* ASPM L1 support */ 443 unsigned int ltr_path:1; /* Latency Tolerance Reporting 444 supported from root to here */ 445 #endif 446 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 447 unsigned int eetlp_prefix_max:3; /* Max # of End-End TLP Prefixes, 0=not supported */ 448 449 pci_channel_state_t error_state; /* Current connectivity state */ 450 struct device dev; /* Generic device interface */ 451 452 int cfg_size; /* Size of config space */ 453 454 /* 455 * Instead of touching interrupt line and base address registers 456 * directly, use the values stored here. They might be different! 457 */ 458 unsigned int irq; 459 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 460 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 461 462 unsigned int transparent:1; /* Subtractive decode bridge */ 463 unsigned int io_window:1; /* Bridge has I/O window */ 464 unsigned int pref_window:1; /* Bridge has pref mem window */ 465 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 466 unsigned int multifunction:1; /* Multi-function device */ 467 468 unsigned int is_busmaster:1; /* Is busmaster */ 469 unsigned int no_msi:1; /* May not use MSI */ 470 unsigned int no_aer_anfe:1; /* Do not unmask ANFE */ 471 unsigned int block_cfg_access:1; /* Config space access blocked */ 472 unsigned int broken_parity_status:1; /* Generates false positive parity */ 473 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 474 unsigned int msi_enabled:1; 475 unsigned int msix_enabled:1; 476 unsigned int ari_enabled:1; /* ARI forwarding */ 477 unsigned int ats_enabled:1; /* Address Translation Svc */ 478 unsigned int pasid_enabled:1; /* Process Address Space ID */ 479 unsigned int pri_enabled:1; /* Page Request Interface */ 480 unsigned int tph_enabled:1; /* TLP Processing Hints */ 481 unsigned int fm_enabled:1; /* Flit Mode (segment captured) */ 482 unsigned int is_managed:1; /* Managed via devres */ 483 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 484 unsigned int needs_freset:1; /* Requires fundamental reset */ 485 unsigned int state_saved:1; 486 unsigned int is_physfn:1; 487 unsigned int is_virtfn:1; 488 unsigned int is_hotplug_bridge:1; 489 unsigned int is_pciehp:1; 490 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 491 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 492 unsigned int is_cxl:1; /* Compute Express Link (CXL) */ 493 /* 494 * Devices marked being untrusted are the ones that can potentially 495 * execute DMA attacks and similar. They are typically connected 496 * through external ports such as Thunderbolt but not limited to 497 * that. When an IOMMU is enabled they should be getting full 498 * mappings to make sure they cannot access arbitrary memory. 499 */ 500 unsigned int untrusted:1; 501 /* 502 * Info from the platform, e.g., ACPI or device tree, may mark a 503 * device as "external-facing". An external-facing device is 504 * itself internal but devices downstream from it are external. 505 */ 506 unsigned int external_facing:1; 507 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 508 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 509 unsigned int irq_managed:1; 510 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 511 unsigned int is_probed:1; /* Device probing in progress */ 512 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 513 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 514 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 515 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 516 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ 517 unsigned int non_mappable_bars:1; /* BARs can't be mapped by CPU or peers */ 518 pci_dev_flags_t dev_flags; 519 atomic_t enable_cnt; /* pci_enable_device has been called */ 520 521 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */ 522 u32 saved_config_space[16]; /* Config space saved at suspend time */ 523 struct hlist_head saved_cap_space; 524 525 #ifdef CONFIG_HOTPLUG_PCI_PCIE 526 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 527 #endif 528 #ifdef CONFIG_PCIE_PTM 529 u16 ptm_cap; /* PTM Capability */ 530 unsigned int ptm_root:1; 531 unsigned int ptm_responder:1; 532 unsigned int ptm_requester:1; 533 atomic_t ptm_enable_cnt; 534 u8 ptm_granularity; 535 #endif 536 #ifdef CONFIG_PCI_MSI 537 void __iomem *msix_base; 538 raw_spinlock_t msi_lock; 539 #endif 540 struct pci_vpd vpd; 541 #ifdef CONFIG_PCIE_DPC 542 u16 dpc_cap; 543 unsigned int dpc_rp_extensions:1; 544 u8 dpc_rp_log_size; 545 #endif 546 struct pcie_bwctrl_data *link_bwctrl; 547 #ifdef CONFIG_PCI_ATS 548 union { 549 struct pci_sriov *sriov; /* PF: SR-IOV info */ 550 struct pci_dev *physfn; /* VF: related PF */ 551 }; 552 u16 ats_cap; /* ATS Capability offset */ 553 u8 ats_stu; /* ATS Smallest Translation Unit */ 554 #endif 555 #ifdef CONFIG_PCI_PRI 556 u16 pri_cap; /* PRI Capability offset */ 557 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 558 unsigned int pasid_required:1; /* PRG Response PASID Required */ 559 #endif 560 #ifdef CONFIG_PCI_PASID 561 u16 pasid_cap; /* PASID Capability offset */ 562 u16 pasid_features; 563 #endif 564 #ifdef CONFIG_PCI_P2PDMA 565 struct pci_p2pdma __rcu *p2pdma; 566 #endif 567 #ifdef CONFIG_PCI_DOE 568 struct xarray doe_mbs; /* Data Object Exchange mailboxes */ 569 #endif 570 #ifdef CONFIG_PCI_NPEM 571 struct npem *npem; /* Native PCIe Enclosure Management */ 572 #endif 573 #ifdef CONFIG_PCI_IDE 574 u16 ide_cap; /* Link Integrity & Data Encryption */ 575 u8 nr_ide_mem; /* Address association resources for streams */ 576 u8 nr_link_ide; /* Link Stream count (Selective Stream offset) */ 577 u16 nr_sel_ide; /* Selective Stream count (register block allocator) */ 578 struct ida ide_stream_ida; 579 unsigned int ide_cfg:1; /* Config cycles over IDE */ 580 unsigned int ide_tee_limit:1; /* Disallow T=0 traffic over IDE */ 581 #endif 582 #ifdef CONFIG_PCI_TSM 583 struct pci_tsm *tsm; /* TSM operation state */ 584 #endif 585 u16 acs_cap; /* ACS Capability offset */ 586 u16 acs_capabilities; /* ACS Capabilities */ 587 u8 supported_speeds; /* Supported Link Speeds Vector */ 588 phys_addr_t rom; /* Physical address if not from BAR */ 589 size_t romlen; /* Length if not from BAR */ 590 unsigned long priv_flags; /* Private flags for the PCI driver */ 591 592 /* These methods index pci_reset_fn_methods[] */ 593 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 594 595 struct gpio_desc *wake; /* WAKE# GPIO */ 596 597 #ifdef CONFIG_PCIE_TPH 598 u16 tph_cap; /* TPH capability offset */ 599 u8 tph_mode; /* TPH mode */ 600 u8 tph_req_type; /* TPH requester type */ 601 #endif 602 }; 603 604 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 605 { 606 #ifdef CONFIG_PCI_IOV 607 if (dev->is_virtfn) 608 dev = dev->physfn; 609 #endif 610 return dev; 611 } 612 613 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 614 615 static inline struct pci_dev *to_pci_dev(const struct device *dev) 616 { 617 return container_of(dev, struct pci_dev, dev); 618 } 619 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 620 #define for_each_pci_dev_reverse(d) \ 621 while ((d = pci_get_device_reverse(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 622 623 static inline int pci_channel_offline(struct pci_dev *pdev) 624 { 625 return (pdev->error_state != pci_channel_io_normal); 626 } 627 628 /* 629 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 630 * Group number is limited to a 16-bit value, therefore (int)-1 is 631 * not a valid PCI domain number, and can be used as a sentinel 632 * value indicating ->domain_nr is not set by the driver (and 633 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 634 * pci_bus_find_domain_nr()). 635 */ 636 #define PCI_DOMAIN_NR_NOT_SET (-1) 637 638 struct pci_host_bridge { 639 struct device dev; 640 struct pci_bus *bus; /* Root bus */ 641 struct pci_ops *ops; 642 struct pci_ops *child_ops; 643 void *sysdata; 644 int busnr; 645 int domain_nr; 646 struct list_head windows; /* resource_entry */ 647 struct list_head dma_ranges; /* dma ranges resource list */ 648 struct list_head ports; /* Root Port list (pci_host_port) */ 649 #ifdef CONFIG_PCI_IDE 650 u16 nr_ide_streams; /* Max streams possibly active in @ide_stream_ida */ 651 struct ida ide_stream_ida; 652 struct ida ide_stream_ids_ida; /* track unique ids per domain */ 653 #endif 654 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 655 int (*map_irq)(const struct pci_dev *, u8, u8); 656 void (*release_fn)(struct pci_host_bridge *); 657 int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); 658 void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); 659 int (*reset_root_port)(struct pci_host_bridge *bridge, struct pci_dev *dev); 660 void *release_data; 661 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 662 unsigned int no_ext_tags:1; /* No Extended Tags */ 663 unsigned int no_inc_mrrs:1; /* No Increase MRRS */ 664 unsigned int native_aer:1; /* OS may use PCIe AER */ 665 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 666 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 667 unsigned int native_pme:1; /* OS may use PCIe PME */ 668 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 669 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 670 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ 671 unsigned int preserve_config:1; /* Preserve FW resource setup */ 672 unsigned int size_windows:1; /* Enable root bus sizing */ 673 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 674 unsigned int broken_l1ss_resume:1; /* Resuming from L1SS during 675 system suspend is broken */ 676 677 /* Resource alignment requirements */ 678 resource_size_t (*align_resource)(struct pci_dev *dev, 679 const struct resource *res, 680 resource_size_t start, 681 resource_size_t size, 682 resource_size_t align); 683 unsigned long private[] ____cacheline_aligned; 684 }; 685 686 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 687 688 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 689 { 690 return (void *)bridge->private; 691 } 692 693 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 694 { 695 return container_of(priv, struct pci_host_bridge, private); 696 } 697 698 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 699 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 700 size_t priv); 701 void pci_free_host_bridge(struct pci_host_bridge *bridge); 702 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 703 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 704 705 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 706 void (*release_fn)(struct pci_host_bridge *), 707 void *release_data); 708 709 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 710 711 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 712 713 struct pci_bus { 714 struct list_head node; /* Node in list of buses */ 715 struct pci_bus *parent; /* Parent bus this bridge is on */ 716 struct list_head children; /* List of child buses */ 717 struct list_head devices; /* List of devices on this bus */ 718 struct pci_dev *self; /* Bridge device as seen by parent */ 719 struct list_head slots; /* List of slots on this bus; 720 protected by pci_slot_mutex */ 721 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 722 struct list_head resources; /* Address space routed to this bus */ 723 struct resource busn_res; /* Bus numbers routed to this bus */ 724 725 struct pci_ops *ops; /* Configuration access functions */ 726 void *sysdata; /* Hook for sys-specific extension */ 727 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 728 729 unsigned char number; /* Bus number */ 730 unsigned char primary; /* Number of primary bridge */ 731 unsigned char max_bus_speed; /* enum pci_bus_speed */ 732 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 733 #ifdef CONFIG_PCI_DOMAINS_GENERIC 734 int domain_nr; 735 #endif 736 737 char name[48]; 738 739 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 740 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 741 struct device *bridge; 742 struct device dev; 743 unsigned int is_added:1; 744 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 745 unsigned int flit_mode:1; /* Link in Flit mode */ 746 }; 747 748 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 749 750 static inline u16 pci_dev_id(struct pci_dev *dev) 751 { 752 return PCI_DEVID(dev->bus->number, dev->devfn); 753 } 754 755 /* 756 * Returns true if the PCI bus is root (behind host-PCI bridge), 757 * false otherwise 758 * 759 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 760 * This is incorrect because "virtual" buses added for SR-IOV (via 761 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 762 */ 763 static inline bool pci_is_root_bus(struct pci_bus *pbus) 764 { 765 return !(pbus->parent); 766 } 767 768 /** 769 * pci_is_bridge - check if the PCI device is a bridge 770 * @dev: PCI device 771 * 772 * Return true if the PCI device is bridge whether it has subordinate 773 * or not. 774 */ 775 static inline bool pci_is_bridge(struct pci_dev *dev) 776 { 777 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 778 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 779 } 780 781 /** 782 * pci_is_vga - check if the PCI device is a VGA device 783 * @pdev: PCI device 784 * 785 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define 786 * VGA Base Class and Sub-Classes: 787 * 788 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible 789 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code) 790 * 791 * Return true if the PCI device is a VGA device and uses the legacy VGA 792 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and 793 * aliases). 794 */ 795 static inline bool pci_is_vga(struct pci_dev *pdev) 796 { 797 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) 798 return true; 799 800 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA) 801 return true; 802 803 return false; 804 } 805 806 /** 807 * pci_is_display - check if the PCI device is a display controller 808 * @pdev: PCI device 809 * 810 * Determine whether the given PCI device corresponds to a display 811 * controller. Display controllers are typically used for graphical output 812 * and are identified based on their class code. 813 * 814 * Return: true if the PCI device is a display controller, false otherwise. 815 */ 816 static inline bool pci_is_display(struct pci_dev *pdev) 817 { 818 return (pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY; 819 } 820 821 static inline bool pcie_is_cxl(struct pci_dev *pci_dev) 822 { 823 return pci_dev->is_cxl; 824 } 825 826 #define for_each_pci_bridge(dev, bus) \ 827 list_for_each_entry(dev, &bus->devices, bus_list) \ 828 if (!pci_is_bridge(dev)) {} else 829 830 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 831 { 832 dev = pci_physfn(dev); 833 if (pci_is_root_bus(dev->bus)) 834 return NULL; 835 836 return dev->bus->self; 837 } 838 839 #ifdef CONFIG_PCI_MSI 840 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 841 { 842 return pci_dev->msi_enabled || pci_dev->msix_enabled; 843 } 844 #else 845 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 846 #endif 847 848 /* Error values that may be returned by PCI functions */ 849 #define PCIBIOS_SUCCESSFUL 0x00 850 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 851 #define PCIBIOS_BAD_VENDOR_ID 0x83 852 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 853 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 854 #define PCIBIOS_SET_FAILED 0x88 855 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 856 857 /* Translate above to generic errno for passing back through non-PCI code */ 858 static inline int pcibios_err_to_errno(int err) 859 { 860 if (err <= PCIBIOS_SUCCESSFUL) 861 return err; /* Assume already errno */ 862 863 switch (err) { 864 case PCIBIOS_FUNC_NOT_SUPPORTED: 865 return -ENOENT; 866 case PCIBIOS_BAD_VENDOR_ID: 867 return -ENOTTY; 868 case PCIBIOS_DEVICE_NOT_FOUND: 869 return -ENODEV; 870 case PCIBIOS_BAD_REGISTER_NUMBER: 871 return -EFAULT; 872 case PCIBIOS_SET_FAILED: 873 return -EIO; 874 case PCIBIOS_BUFFER_TOO_SMALL: 875 return -ENOSPC; 876 } 877 878 return -ERANGE; 879 } 880 881 /* Low-level architecture-dependent routines */ 882 883 struct pci_ops { 884 int (*add_bus)(struct pci_bus *bus); 885 void (*remove_bus)(struct pci_bus *bus); 886 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 887 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 888 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 889 }; 890 891 /* 892 * ACPI needs to be able to access PCI config space before we've done a 893 * PCI bus scan and created pci_bus structures. 894 */ 895 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 896 int reg, int len, u32 *val); 897 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 898 int reg, int len, u32 val); 899 900 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 901 typedef u64 pci_bus_addr_t; 902 #else 903 typedef u32 pci_bus_addr_t; 904 #endif 905 906 struct pci_bus_region { 907 pci_bus_addr_t start; 908 pci_bus_addr_t end; 909 }; 910 911 static inline pci_bus_addr_t pci_bus_region_size(const struct pci_bus_region *region) 912 { 913 return region->end - region->start + 1; 914 } 915 916 struct pci_dynids { 917 spinlock_t lock; /* Protects list, index */ 918 struct list_head list; /* For IDs added at runtime */ 919 }; 920 921 922 /* 923 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 924 * a set of callbacks in struct pci_error_handlers, that device driver 925 * will be notified of PCI bus errors, and will be driven to recovery 926 * when an error occurs. 927 */ 928 929 typedef unsigned int __bitwise pci_ers_result_t; 930 931 enum pci_ers_result { 932 /* No result/none/not supported in device driver */ 933 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 934 935 /* Device driver can recover without slot reset */ 936 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 937 938 /* Device driver wants slot to be reset */ 939 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 940 941 /* Device has completely failed, is unrecoverable */ 942 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 943 944 /* Device driver is fully recovered and operational */ 945 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 946 947 /* No AER capabilities registered for the driver */ 948 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 949 }; 950 951 /* PCI bus error event callbacks */ 952 struct pci_error_handlers { 953 /* PCI bus error detected on this device */ 954 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 955 pci_channel_state_t error); 956 957 /* MMIO has been re-enabled, but not DMA */ 958 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 959 960 /* PCI slot has been reset */ 961 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 962 963 /* PCI function reset prepare or completed */ 964 void (*reset_prepare)(struct pci_dev *dev); 965 void (*reset_done)(struct pci_dev *dev); 966 967 /* Device driver may resume normal operations */ 968 void (*resume)(struct pci_dev *dev); 969 970 /* Allow device driver to record more details of a correctable error */ 971 void (*cor_error_detected)(struct pci_dev *dev); 972 }; 973 974 975 struct module; 976 977 /** 978 * struct pci_driver - PCI driver structure 979 * @name: Driver name. 980 * @id_table: Pointer to table of device IDs the driver is 981 * interested in. Most drivers should export this 982 * table using MODULE_DEVICE_TABLE(pci,...). 983 * @probe: This probing function gets called (during execution 984 * of pci_register_driver() for already existing 985 * devices or later if a new device gets inserted) for 986 * all PCI devices which match the ID table and are not 987 * "owned" by the other drivers yet. This function gets 988 * passed a "struct pci_dev \*" for each device whose 989 * entry in the ID table matches the device. The probe 990 * function returns zero when the driver chooses to 991 * take "ownership" of the device or an error code 992 * (negative number) otherwise. 993 * The pci_device_id parameter is only valid during probe. 994 * The probe function always gets called from process 995 * context, so it can sleep. 996 * @remove: The remove() function gets called whenever a device 997 * being handled by this driver is removed (either during 998 * deregistration of the driver or when it's manually 999 * pulled out of a hot-pluggable slot). 1000 * The remove function always gets called from process 1001 * context, so it can sleep. 1002 * @suspend: Put device into low power state. 1003 * @resume: Wake device from low power state. 1004 * (Please see Documentation/power/pci.rst for descriptions 1005 * of PCI Power Management and the related functions.) 1006 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 1007 * Intended to stop any idling DMA operations. 1008 * Useful for enabling wake-on-lan (NIC) or changing 1009 * the power state of a device before reboot. 1010 * e.g. drivers/net/e100.c. 1011 * @sriov_configure: Optional driver callback to allow configuration of 1012 * number of VFs to enable via sysfs "sriov_numvfs" file. 1013 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 1014 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 1015 * This will change MSI-X Table Size in the VF Message Control 1016 * registers. 1017 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 1018 * MSI-X vectors available for distribution to the VFs. 1019 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 1020 * @groups: Sysfs attribute groups. 1021 * @dev_groups: Attributes attached to the device that will be 1022 * created once it is bound to the driver. 1023 * @driver: Driver model structure. 1024 * @dynids: List of dynamically added device IDs. 1025 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 1026 * For most device drivers, no need to care about this flag 1027 * as long as all DMAs are handled through the kernel DMA API. 1028 * For some special ones, for example VFIO drivers, they know 1029 * how to manage the DMA themselves and set this flag so that 1030 * the IOMMU layer will allow them to setup and manage their 1031 * own I/O address space. 1032 */ 1033 struct pci_driver { 1034 const char *name; 1035 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 1036 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 1037 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 1038 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 1039 int (*resume)(struct pci_dev *dev); /* Device woken up */ 1040 void (*shutdown)(struct pci_dev *dev); 1041 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 1042 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 1043 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 1044 const struct pci_error_handlers *err_handler; 1045 const struct attribute_group **groups; 1046 const struct attribute_group **dev_groups; 1047 struct device_driver driver; 1048 struct pci_dynids dynids; 1049 bool driver_managed_dma; 1050 }; 1051 1052 #define to_pci_driver(__drv) \ 1053 ( __drv ? container_of_const(__drv, struct pci_driver, driver) : NULL ) 1054 1055 /** 1056 * PCI_DEVICE - macro used to describe a specific PCI device 1057 * @vend: the 16 bit PCI Vendor ID 1058 * @dev: the 16 bit PCI Device ID 1059 * 1060 * This macro is used to create a struct pci_device_id that matches a 1061 * specific device. The subvendor and subdevice fields will be set to 1062 * PCI_ANY_ID. 1063 */ 1064 #define PCI_DEVICE(vend,dev) \ 1065 .vendor = (vend), .device = (dev), \ 1066 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1067 1068 /** 1069 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 1070 * override_only flags. 1071 * @vend: the 16 bit PCI Vendor ID 1072 * @dev: the 16 bit PCI Device ID 1073 * @driver_override: the 32 bit PCI Device override_only 1074 * 1075 * This macro is used to create a struct pci_device_id that matches only a 1076 * driver_override device. The subvendor and subdevice fields will be set to 1077 * PCI_ANY_ID. 1078 */ 1079 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 1080 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 1081 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 1082 1083 /** 1084 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 1085 * "driver_override" PCI device. 1086 * @vend: the 16 bit PCI Vendor ID 1087 * @dev: the 16 bit PCI Device ID 1088 * 1089 * This macro is used to create a struct pci_device_id that matches a 1090 * specific device. The subvendor and subdevice fields will be set to 1091 * PCI_ANY_ID and the driver_override will be set to 1092 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 1093 */ 1094 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 1095 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 1096 1097 /** 1098 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 1099 * @vend: the 16 bit PCI Vendor ID 1100 * @dev: the 16 bit PCI Device ID 1101 * @subvend: the 16 bit PCI Subvendor ID 1102 * @subdev: the 16 bit PCI Subdevice ID 1103 * 1104 * This macro is used to create a struct pci_device_id that matches a 1105 * specific device with subsystem information. 1106 */ 1107 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1108 .vendor = (vend), .device = (dev), \ 1109 .subvendor = (subvend), .subdevice = (subdev) 1110 1111 /** 1112 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 1113 * @dev_class: the class, subclass, prog-if triple for this device 1114 * @dev_class_mask: the class mask for this device 1115 * 1116 * This macro is used to create a struct pci_device_id that matches a 1117 * specific PCI class. The vendor, device, subvendor, and subdevice 1118 * fields will be set to PCI_ANY_ID. 1119 */ 1120 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1121 .class = (dev_class), .class_mask = (dev_class_mask), \ 1122 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1123 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1124 1125 /** 1126 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1127 * @vend: the vendor name 1128 * @dev: the 16 bit PCI Device ID 1129 * 1130 * This macro is used to create a struct pci_device_id that matches a 1131 * specific PCI device. The subvendor, and subdevice fields will be set 1132 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1133 * private data. 1134 */ 1135 #define PCI_VDEVICE(vend, dev) \ 1136 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1137 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1138 1139 /** 1140 * PCI_VDEVICE_SUB - describe a specific PCI device/subdevice in a short form 1141 * @vend: the vendor name 1142 * @dev: the 16 bit PCI Device ID 1143 * @subvend: the 16 bit PCI Subvendor ID 1144 * @subdev: the 16 bit PCI Subdevice ID 1145 * 1146 * Generate the pci_device_id struct layout for the specific PCI 1147 * device/subdevice. Private data may follow the output. 1148 */ 1149 #define PCI_VDEVICE_SUB(vend, dev, subvend, subdev) \ 1150 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1151 .subvendor = (subvend), .subdevice = (subdev), 0, 0 1152 1153 /** 1154 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1155 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1156 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1157 * @data: the driver data to be filled 1158 * 1159 * This macro is used to create a struct pci_device_id that matches a 1160 * specific PCI device. The subvendor, and subdevice fields will be set 1161 * to PCI_ANY_ID. 1162 */ 1163 #define PCI_DEVICE_DATA(vend, dev, data) \ 1164 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1165 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1166 .driver_data = (kernel_ulong_t)(data) 1167 1168 enum { 1169 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1170 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1171 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1172 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1173 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1174 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1175 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1176 }; 1177 1178 #define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */ 1179 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1180 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1181 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1182 1183 /* These external functions are only available when PCI support is enabled */ 1184 #ifdef CONFIG_PCI 1185 1186 /* PCI legacy I/O port and memory address space sizes. */ 1187 #define PCI_LEGACY_IO_SIZE (SZ_64K - 1) 1188 #define PCI_LEGACY_MEM_SIZE SZ_1M 1189 1190 extern unsigned int pci_flags; 1191 1192 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1193 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1194 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1195 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1196 1197 void pcie_bus_configure_settings(struct pci_bus *bus); 1198 1199 enum pcie_bus_config_types { 1200 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1201 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1202 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1203 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1204 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1205 }; 1206 1207 extern enum pcie_bus_config_types pcie_bus_config; 1208 1209 extern const struct bus_type pci_bus_type; 1210 1211 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1212 * code, or PCI core code. */ 1213 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1214 1215 void pcibios_resource_survey_bus(struct pci_bus *bus); 1216 void pcibios_bus_add_device(struct pci_dev *pdev); 1217 void pcibios_add_bus(struct pci_bus *bus); 1218 void pcibios_remove_bus(struct pci_bus *bus); 1219 void pcibios_fixup_bus(struct pci_bus *); 1220 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1221 /* Architecture-specific versions may override this (weak) */ 1222 char *pcibios_setup(char *str); 1223 1224 /* Used only when drivers/pci/setup.c is used */ 1225 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1226 const struct resource *empty_res, 1227 resource_size_t size, 1228 resource_size_t align); 1229 resource_size_t pci_align_resource(struct pci_dev *dev, 1230 const struct resource *res, 1231 const struct resource *empty_res, 1232 resource_size_t size, 1233 resource_size_t align); 1234 1235 /* Generic PCI functions used internally */ 1236 1237 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1238 struct resource *res); 1239 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1240 struct pci_bus_region *region); 1241 void pcibios_scan_specific_bus(int busn); 1242 struct pci_bus *pci_find_bus(int domain, int busnr); 1243 void pci_bus_add_devices(const struct pci_bus *bus); 1244 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1245 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1246 struct pci_ops *ops, void *sysdata, 1247 struct list_head *resources); 1248 int pci_host_probe(struct pci_host_bridge *bridge); 1249 void pci_probe_flush_workqueue(void); 1250 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1251 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1252 void pci_bus_release_busn_res(struct pci_bus *b); 1253 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1254 struct pci_ops *ops, void *sysdata, 1255 struct list_head *resources); 1256 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1257 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1258 int busnr); 1259 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1260 const char *name, 1261 struct hotplug_slot *hotplug); 1262 void pci_destroy_slot(struct pci_slot *slot); 1263 #ifdef CONFIG_SYSFS 1264 void pci_dev_assign_slot(struct pci_dev *dev); 1265 #else 1266 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1267 #endif 1268 int pci_scan_slot(struct pci_bus *bus, int devfn); 1269 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1270 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1271 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1272 void pci_bus_add_device(struct pci_dev *dev); 1273 void pci_read_bridge_bases(struct pci_bus *child); 1274 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1275 struct resource *res); 1276 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1277 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1278 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1279 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1280 void pci_dev_put(struct pci_dev *dev); 1281 DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T)) 1282 void pci_remove_bus(struct pci_bus *b); 1283 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1284 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1285 void pci_stop_root_bus(struct pci_bus *bus); 1286 void pci_remove_root_bus(struct pci_bus *bus); 1287 #ifdef CONFIG_CARDBUS 1288 void pci_setup_cardbus_bridge(struct pci_bus *bus); 1289 #else 1290 static inline void pci_setup_cardbus_bridge(struct pci_bus *bus) { } 1291 #endif 1292 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1293 void pci_sort_breadthfirst(void); 1294 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1295 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1296 1297 /* Generic PCI functions exported to card drivers */ 1298 1299 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1300 u8 pci_find_capability(struct pci_dev *dev, int cap); 1301 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1302 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1303 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1304 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1305 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1306 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1307 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1308 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1309 1310 u64 pci_get_dsn(struct pci_dev *dev); 1311 1312 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1313 struct pci_dev *from); 1314 struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device, 1315 struct pci_dev *from); 1316 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1317 unsigned int ss_vendor, unsigned int ss_device, 1318 struct pci_dev *from); 1319 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1320 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1321 unsigned int devfn); 1322 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1323 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); 1324 1325 int pci_dev_present(const struct pci_device_id *ids); 1326 1327 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1328 int where, u8 *val); 1329 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1330 int where, u16 *val); 1331 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1332 int where, u32 *val); 1333 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1334 int where, u8 val); 1335 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1336 int where, u16 val); 1337 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1338 int where, u32 val); 1339 1340 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1341 int where, int size, u32 *val); 1342 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1343 int where, int size, u32 val); 1344 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1345 int where, int size, u32 *val); 1346 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1347 int where, int size, u32 val); 1348 1349 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1350 1351 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1352 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1353 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1354 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1355 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1356 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1357 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos, 1358 u32 clear, u32 set); 1359 1360 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1361 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1362 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1363 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1364 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, 1365 u16 clear, u16 set); 1366 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos, 1367 u16 clear, u16 set); 1368 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1369 u32 clear, u32 set); 1370 1371 /** 1372 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers 1373 * @dev: PCI device structure of the PCI Express device 1374 * @pos: PCI Express Capability Register 1375 * @clear: Clear bitmask 1376 * @set: Set bitmask 1377 * 1378 * Perform a Read-Modify-Write (RMW) operation using @clear and @set 1379 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express 1380 * Capability Registers are accessed concurrently in RMW fashion, hence 1381 * require locking which is handled transparently to the caller. 1382 */ 1383 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, 1384 int pos, 1385 u16 clear, u16 set) 1386 { 1387 switch (pos) { 1388 case PCI_EXP_LNKCTL: 1389 case PCI_EXP_LNKCTL2: 1390 case PCI_EXP_RTCTL: 1391 return pcie_capability_clear_and_set_word_locked(dev, pos, 1392 clear, set); 1393 default: 1394 return pcie_capability_clear_and_set_word_unlocked(dev, pos, 1395 clear, set); 1396 } 1397 } 1398 1399 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1400 u16 set) 1401 { 1402 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1403 } 1404 1405 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1406 u32 set) 1407 { 1408 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1409 } 1410 1411 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1412 u16 clear) 1413 { 1414 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1415 } 1416 1417 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1418 u32 clear) 1419 { 1420 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1421 } 1422 1423 /* User-space driven config access */ 1424 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1425 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1426 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1427 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1428 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1429 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1430 1431 int __must_check pci_enable_device(struct pci_dev *dev); 1432 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1433 int __must_check pci_reenable_device(struct pci_dev *); 1434 int __must_check pcim_enable_device(struct pci_dev *pdev); 1435 void pcim_pin_device(struct pci_dev *pdev); 1436 1437 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1438 { 1439 /* 1440 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1441 * writable and no quirk has marked the feature broken. 1442 */ 1443 return !pdev->broken_intx_masking; 1444 } 1445 1446 static inline int pci_is_enabled(struct pci_dev *pdev) 1447 { 1448 return (atomic_read(&pdev->enable_cnt) > 0); 1449 } 1450 1451 static inline int pci_is_managed(struct pci_dev *pdev) 1452 { 1453 return pdev->is_managed; 1454 } 1455 1456 void pci_disable_device(struct pci_dev *dev); 1457 1458 extern unsigned int pcibios_max_latency; 1459 void pci_set_master(struct pci_dev *dev); 1460 void pci_clear_master(struct pci_dev *dev); 1461 1462 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1463 int pci_set_cacheline_size(struct pci_dev *dev); 1464 int __must_check pci_set_mwi(struct pci_dev *dev); 1465 int __must_check pcim_set_mwi(struct pci_dev *dev); 1466 int pci_try_set_mwi(struct pci_dev *dev); 1467 void pci_clear_mwi(struct pci_dev *dev); 1468 void pci_disable_parity(struct pci_dev *dev); 1469 void pci_intx(struct pci_dev *dev, int enable); 1470 bool pci_check_and_mask_intx(struct pci_dev *dev); 1471 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1472 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1473 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1474 int pcix_get_max_mmrbc(struct pci_dev *dev); 1475 int pcix_get_mmrbc(struct pci_dev *dev); 1476 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1477 int pcie_get_readrq(struct pci_dev *dev); 1478 int pcie_set_readrq(struct pci_dev *dev, int rq); 1479 int pcie_get_mps(struct pci_dev *dev); 1480 int pcie_set_mps(struct pci_dev *dev, int mps); 1481 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1482 enum pci_bus_speed *speed, 1483 enum pcie_link_width *width); 1484 int pcie_link_bandwidth_mbps(struct pci_dev *pdev); 1485 void pcie_print_link_status(struct pci_dev *dev); 1486 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1487 int pcie_flr(struct pci_dev *dev); 1488 int __pci_reset_function_locked(struct pci_dev *dev); 1489 int pci_reset_function(struct pci_dev *dev); 1490 int pci_reset_function_locked(struct pci_dev *dev); 1491 int pci_try_reset_function(struct pci_dev *dev); 1492 int pci_probe_reset_slot(struct pci_slot *slot); 1493 int pci_probe_reset_bus(struct pci_bus *bus); 1494 int pci_reset_bus(struct pci_dev *dev); 1495 void pci_reset_secondary_bus(struct pci_dev *dev); 1496 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1497 void pci_update_resource(struct pci_dev *dev, int resno); 1498 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1499 int pci_release_resource(struct pci_dev *dev, int resno); 1500 1501 /* Resizable BAR related routines */ 1502 int pci_rebar_bytes_to_size(u64 bytes); 1503 resource_size_t pci_rebar_size_to_bytes(int size); 1504 u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1505 bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); 1506 int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); 1507 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size, 1508 int exclude_bars); 1509 1510 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1511 bool pci_device_is_present(struct pci_dev *pdev); 1512 void pci_ignore_hotplug(struct pci_dev *dev); 1513 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1514 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1515 1516 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1517 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1518 const char *fmt, ...); 1519 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1520 1521 /* ROM control related routines */ 1522 int pci_enable_rom(struct pci_dev *pdev); 1523 void pci_disable_rom(struct pci_dev *pdev); 1524 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1525 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1526 1527 /* Power management related routines */ 1528 int pci_save_state(struct pci_dev *dev); 1529 void pci_restore_state(struct pci_dev *dev); 1530 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1531 int pci_load_saved_state(struct pci_dev *dev, 1532 struct pci_saved_state *state); 1533 int pci_load_and_free_saved_state(struct pci_dev *dev, 1534 struct pci_saved_state **state); 1535 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1536 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1537 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state); 1538 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1539 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1540 void pci_pme_active(struct pci_dev *dev, bool enable); 1541 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1542 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1543 int pci_prepare_to_sleep(struct pci_dev *dev); 1544 int pci_back_from_sleep(struct pci_dev *dev); 1545 bool pci_dev_run_wake(struct pci_dev *dev); 1546 void pci_d3cold_enable(struct pci_dev *dev); 1547 void pci_d3cold_disable(struct pci_dev *dev); 1548 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1549 void pci_resume_bus(struct pci_bus *bus); 1550 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1551 1552 /* For use by arch with custom probe code */ 1553 void set_pcie_port_type(struct pci_dev *pdev); 1554 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1555 1556 /* Functions for PCI Hotplug drivers to use */ 1557 unsigned int pci_rescan_bus(struct pci_bus *bus); 1558 void pci_lock_rescan_remove(void); 1559 void pci_unlock_rescan_remove(void); 1560 1561 /* Vital Product Data routines */ 1562 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1563 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1564 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1565 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1566 1567 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1568 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1569 void pci_bus_assign_resources(const struct pci_bus *bus); 1570 void pci_bus_claim_resources(struct pci_bus *bus); 1571 void pci_bus_size_bridges(struct pci_bus *bus); 1572 int pci_claim_resource(struct pci_dev *, int); 1573 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1574 void pci_assign_unassigned_resources(void); 1575 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1576 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1577 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1578 int pci_enable_resources(struct pci_dev *, int mask); 1579 void pci_assign_irq(struct pci_dev *dev); 1580 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1581 #define HAVE_PCI_REQ_REGIONS 2 1582 int __must_check pci_request_regions(struct pci_dev *, const char *); 1583 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1584 void pci_release_regions(struct pci_dev *); 1585 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1586 void pci_release_region(struct pci_dev *, int); 1587 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1588 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1589 void pci_release_selected_regions(struct pci_dev *, int); 1590 1591 static inline __must_check struct resource * 1592 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1593 unsigned int len, const char *name) 1594 { 1595 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1596 name, IORESOURCE_EXCLUSIVE); 1597 } 1598 1599 static inline void pci_release_config_region(struct pci_dev *pdev, 1600 unsigned int offset, 1601 unsigned int len) 1602 { 1603 __release_region(&pdev->driver_exclusive_resource, offset, len); 1604 } 1605 1606 /* drivers/pci/bus.c */ 1607 void pci_add_resource(struct list_head *resources, struct resource *res); 1608 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1609 resource_size_t offset); 1610 void pci_free_resource_list(struct list_head *resources); 1611 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res); 1612 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1613 void pci_bus_remove_resources(struct pci_bus *bus); 1614 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); 1615 int devm_request_pci_bus_resources(struct device *dev, 1616 struct list_head *resources); 1617 1618 /* Temporary until new and working PCI SBR API in place */ 1619 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1620 1621 #define __pci_bus_for_each_res0(bus, res, ...) \ 1622 for (unsigned int __b = 0; \ 1623 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1624 __b++) 1625 1626 #define __pci_bus_for_each_res1(bus, res, __b) \ 1627 for (__b = 0; \ 1628 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1629 __b++) 1630 1631 /** 1632 * pci_bus_for_each_resource - iterate over PCI bus resources 1633 * @bus: the PCI bus 1634 * @res: pointer to the current resource 1635 * @...: optional index of the current resource 1636 * 1637 * Iterate over PCI bus resources. The first part is to go over PCI bus 1638 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries. 1639 * After that continue with the separate list of the additional resources, 1640 * if not empty. That's why the Logical OR is being used. 1641 * 1642 * Possible usage: 1643 * 1644 * struct pci_bus *bus = ...; 1645 * struct resource *res; 1646 * unsigned int i; 1647 * 1648 * // With optional index 1649 * pci_bus_for_each_resource(bus, res, i) 1650 * pr_info("PCI bus resource[%u]: %pR\n", i, res); 1651 * 1652 * // Without index 1653 * pci_bus_for_each_resource(bus, res) 1654 * _do_something_(res); 1655 */ 1656 #define pci_bus_for_each_resource(bus, res, ...) \ 1657 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 1658 (bus, res, __VA_ARGS__) 1659 1660 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1661 struct resource *res, resource_size_t size, 1662 resource_size_t align, resource_size_t min, 1663 unsigned long type_mask, 1664 resource_alignf alignf, 1665 void *alignf_data); 1666 1667 1668 int pci_register_io_range(const struct fwnode_handle *fwnode, phys_addr_t addr, 1669 resource_size_t size); 1670 unsigned long pci_address_to_pio(phys_addr_t addr); 1671 phys_addr_t pci_pio_to_address(unsigned long pio); 1672 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1673 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1674 phys_addr_t phys_addr); 1675 void pci_unmap_iospace(struct resource *res); 1676 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1677 resource_size_t offset, 1678 resource_size_t size); 1679 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1680 struct resource *res); 1681 1682 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1683 { 1684 struct pci_bus_region region; 1685 1686 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1687 return region.start; 1688 } 1689 1690 /* Proper probing supporting hot-pluggable devices */ 1691 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1692 const char *mod_name); 1693 1694 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1695 #define pci_register_driver(driver) \ 1696 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1697 1698 void pci_unregister_driver(struct pci_driver *dev); 1699 1700 /** 1701 * module_pci_driver() - Helper macro for registering a PCI driver 1702 * @__pci_driver: pci_driver struct 1703 * 1704 * Helper macro for PCI drivers which do not do anything special in module 1705 * init/exit. This eliminates a lot of boilerplate. Each module may only 1706 * use this macro once, and calling it replaces module_init() and module_exit() 1707 */ 1708 #define module_pci_driver(__pci_driver) \ 1709 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1710 1711 /** 1712 * builtin_pci_driver() - Helper macro for registering a PCI driver 1713 * @__pci_driver: pci_driver struct 1714 * 1715 * Helper macro for PCI drivers which do not do anything special in their 1716 * init code. This eliminates a lot of boilerplate. Each driver may only 1717 * use this macro once, and calling it replaces device_initcall(...) 1718 */ 1719 #define builtin_pci_driver(__pci_driver) \ 1720 builtin_driver(__pci_driver, pci_register_driver) 1721 1722 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1723 int pci_add_dynid(struct pci_driver *drv, 1724 unsigned int vendor, unsigned int device, 1725 unsigned int subvendor, unsigned int subdevice, 1726 unsigned int class, unsigned int class_mask, 1727 unsigned long driver_data); 1728 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1729 struct pci_dev *dev); 1730 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1731 int pass); 1732 1733 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1734 void *userdata); 1735 void pci_walk_bus_reverse(struct pci_bus *top, 1736 int (*cb)(struct pci_dev *, void *), void *userdata); 1737 int pci_cfg_space_size(struct pci_dev *dev); 1738 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1739 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1740 unsigned long type); 1741 1742 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1743 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1744 1745 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1746 unsigned int command_bits, u32 flags); 1747 1748 /* 1749 * Virtual interrupts allow for more interrupts to be allocated 1750 * than the device has interrupts for. These are not programmed 1751 * into the device's MSI-X table and must be handled by some 1752 * other driver means. 1753 */ 1754 #define PCI_IRQ_VIRTUAL (1 << 4) 1755 1756 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1757 1758 #include <linux/dmapool.h> 1759 1760 struct msix_entry { 1761 u32 vector; /* Kernel uses to write allocated vector */ 1762 u16 entry; /* Driver uses to specify entry, OS writes */ 1763 }; 1764 1765 #ifdef CONFIG_PCI_MSI 1766 int pci_msi_vec_count(struct pci_dev *dev); 1767 void pci_disable_msi(struct pci_dev *dev); 1768 int pci_msix_vec_count(struct pci_dev *dev); 1769 void pci_disable_msix(struct pci_dev *dev); 1770 void pci_restore_msi_state(struct pci_dev *dev); 1771 bool pci_msi_enabled(void); 1772 int pci_enable_msi(struct pci_dev *dev); 1773 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1774 int minvec, int maxvec); 1775 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1776 struct msix_entry *entries, int nvec) 1777 { 1778 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1779 if (rc < 0) 1780 return rc; 1781 return 0; 1782 } 1783 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1784 unsigned int max_vecs, unsigned int flags); 1785 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1786 unsigned int max_vecs, unsigned int flags, 1787 struct irq_affinity *affd); 1788 1789 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1790 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1791 const struct irq_affinity_desc *affdesc); 1792 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1793 1794 void pci_free_irq_vectors(struct pci_dev *dev); 1795 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1796 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1797 1798 /** 1799 * pci_irq_type - Get the interrupt type of a PCI device 1800 * @pdev: the PCI device to operate on 1801 * 1802 * Discriminate the interrupt type the PCI core selected for this device 1803 * after a successful pci_alloc_irq_vectors() call. 1804 * 1805 * Return: %PCI_IRQ_MSIX, %PCI_IRQ_MSI, or %PCI_IRQ_INTX. 1806 */ 1807 static inline unsigned int pci_irq_type(struct pci_dev *pdev) 1808 { 1809 if (pdev->msix_enabled) 1810 return PCI_IRQ_MSIX; 1811 1812 if (pdev->msi_enabled) 1813 return PCI_IRQ_MSI; 1814 1815 return PCI_IRQ_INTX; 1816 } 1817 1818 #else 1819 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1820 static inline void pci_disable_msi(struct pci_dev *dev) { } 1821 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1822 static inline void pci_disable_msix(struct pci_dev *dev) { } 1823 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1824 static inline bool pci_msi_enabled(void) { return false; } 1825 static inline int pci_enable_msi(struct pci_dev *dev) 1826 { return -ENOSYS; } 1827 static inline int pci_enable_msix_range(struct pci_dev *dev, 1828 struct msix_entry *entries, int minvec, int maxvec) 1829 { return -ENOSYS; } 1830 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1831 struct msix_entry *entries, int nvec) 1832 { return -ENOSYS; } 1833 1834 static inline int 1835 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1836 unsigned int max_vecs, unsigned int flags, 1837 struct irq_affinity *aff_desc) 1838 { 1839 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq) 1840 return 1; 1841 return -ENOSPC; 1842 } 1843 static inline int 1844 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1845 unsigned int max_vecs, unsigned int flags) 1846 { 1847 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1848 flags, NULL); 1849 } 1850 1851 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) 1852 { return false; } 1853 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1854 const struct irq_affinity_desc *affdesc) 1855 { 1856 struct msi_map map = { .index = -ENOSYS, }; 1857 1858 return map; 1859 } 1860 1861 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) 1862 { 1863 } 1864 1865 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1866 { 1867 } 1868 1869 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1870 { 1871 if (WARN_ON_ONCE(nr > 0)) 1872 return -EINVAL; 1873 return dev->irq; 1874 } 1875 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1876 int vec) 1877 { 1878 return cpu_possible_mask; 1879 } 1880 1881 static inline unsigned int pci_irq_type(struct pci_dev *pdev) 1882 { 1883 return PCI_IRQ_INTX; 1884 } 1885 #endif 1886 1887 /** 1888 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1889 * @d: the INTx IRQ domain 1890 * @node: the DT node for the device whose interrupt we're translating 1891 * @intspec: the interrupt specifier data from the DT 1892 * @intsize: the number of entries in @intspec 1893 * @out_hwirq: pointer at which to write the hwirq number 1894 * @out_type: pointer at which to write the interrupt type 1895 * 1896 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1897 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1898 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1899 * INTx value to obtain the hwirq number. 1900 * 1901 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1902 */ 1903 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1904 struct device_node *node, 1905 const u32 *intspec, 1906 unsigned int intsize, 1907 unsigned long *out_hwirq, 1908 unsigned int *out_type) 1909 { 1910 const u32 intx = intspec[0]; 1911 1912 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1913 return -EINVAL; 1914 1915 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1916 return 0; 1917 } 1918 1919 #ifdef CONFIG_PCIEPORTBUS 1920 extern bool pcie_ports_disabled; 1921 extern bool pcie_ports_native; 1922 extern bool pcie_ports_dpc_native; 1923 1924 int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_req, 1925 bool use_lt); 1926 #else 1927 #define pcie_ports_disabled true 1928 #define pcie_ports_native false 1929 #define pcie_ports_dpc_native false 1930 1931 static inline int pcie_set_target_speed(struct pci_dev *port, 1932 enum pci_bus_speed speed_req, 1933 bool use_lt) 1934 { 1935 return -EOPNOTSUPP; 1936 } 1937 #endif 1938 1939 #define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */ 1940 #define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */ 1941 #define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */ 1942 #define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */ 1943 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */ 1944 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */ 1945 #define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\ 1946 PCIE_LINK_STATE_L1 |\ 1947 PCIE_LINK_STATE_L1_1 |\ 1948 PCIE_LINK_STATE_L1_2 |\ 1949 PCIE_LINK_STATE_L1_1_PCIPM |\ 1950 PCIE_LINK_STATE_L1_2_PCIPM) 1951 #define PCIE_LINK_STATE_CLKPM BIT(7) 1952 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\ 1953 PCIE_LINK_STATE_CLKPM) 1954 1955 #ifdef CONFIG_PCIEASPM 1956 int pci_disable_link_state(struct pci_dev *pdev, int state); 1957 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1958 int pci_enable_link_state(struct pci_dev *pdev, int state); 1959 int pci_enable_link_state_locked(struct pci_dev *pdev, int state); 1960 void pcie_no_aspm(void); 1961 bool pcie_aspm_support_enabled(void); 1962 bool pcie_aspm_enabled(struct pci_dev *pdev); 1963 #else 1964 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1965 { return 0; } 1966 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1967 { return 0; } 1968 static inline int pci_enable_link_state(struct pci_dev *pdev, int state) 1969 { return 0; } 1970 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) 1971 { return 0; } 1972 static inline void pcie_no_aspm(void) { } 1973 static inline bool pcie_aspm_support_enabled(void) { return false; } 1974 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1975 #endif 1976 1977 #ifdef CONFIG_HOTPLUG_PCI 1978 void pci_hp_ignore_link_change(struct pci_dev *pdev); 1979 void pci_hp_unignore_link_change(struct pci_dev *pdev); 1980 #else 1981 static inline void pci_hp_ignore_link_change(struct pci_dev *pdev) { } 1982 static inline void pci_hp_unignore_link_change(struct pci_dev *pdev) { } 1983 #endif 1984 1985 #ifdef CONFIG_PCIEAER 1986 bool pci_aer_available(void); 1987 #else 1988 static inline bool pci_aer_available(void) { return false; } 1989 #endif 1990 1991 bool pci_ats_disabled(void); 1992 1993 #define PCIE_PTM_CONTEXT_UPDATE_AUTO 0 1994 #define PCIE_PTM_CONTEXT_UPDATE_MANUAL 1 1995 1996 struct pcie_ptm_ops { 1997 int (*check_capability)(void *drvdata); 1998 int (*context_update_write)(void *drvdata, u8 mode); 1999 int (*context_update_read)(void *drvdata, u8 *mode); 2000 int (*context_valid_write)(void *drvdata, bool valid); 2001 int (*context_valid_read)(void *drvdata, bool *valid); 2002 int (*local_clock_read)(void *drvdata, u64 *clock); 2003 int (*master_clock_read)(void *drvdata, u64 *clock); 2004 int (*t1_read)(void *drvdata, u64 *clock); 2005 int (*t2_read)(void *drvdata, u64 *clock); 2006 int (*t3_read)(void *drvdata, u64 *clock); 2007 int (*t4_read)(void *drvdata, u64 *clock); 2008 2009 bool (*context_update_visible)(void *drvdata); 2010 bool (*context_valid_visible)(void *drvdata); 2011 bool (*local_clock_visible)(void *drvdata); 2012 bool (*master_clock_visible)(void *drvdata); 2013 bool (*t1_visible)(void *drvdata); 2014 bool (*t2_visible)(void *drvdata); 2015 bool (*t3_visible)(void *drvdata); 2016 bool (*t4_visible)(void *drvdata); 2017 }; 2018 2019 struct pci_ptm_debugfs { 2020 struct dentry *debugfs; 2021 const struct pcie_ptm_ops *ops; 2022 struct mutex lock; 2023 void *pdata; 2024 }; 2025 2026 #ifdef CONFIG_PCIE_PTM 2027 int pci_enable_ptm(struct pci_dev *dev); 2028 void pci_disable_ptm(struct pci_dev *dev); 2029 bool pcie_ptm_enabled(struct pci_dev *dev); 2030 #else 2031 static inline int pci_enable_ptm(struct pci_dev *dev) 2032 { return -EINVAL; } 2033 static inline void pci_disable_ptm(struct pci_dev *dev) { } 2034 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 2035 { return false; } 2036 #endif 2037 2038 #if IS_ENABLED(CONFIG_DEBUG_FS) && IS_ENABLED(CONFIG_PCIE_PTM) 2039 struct pci_ptm_debugfs *pcie_ptm_create_debugfs(struct device *dev, void *pdata, 2040 const struct pcie_ptm_ops *ops); 2041 void pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs); 2042 #else 2043 static inline struct pci_ptm_debugfs 2044 *pcie_ptm_create_debugfs(struct device *dev, void *pdata, 2045 const struct pcie_ptm_ops *ops) { return NULL; } 2046 static inline void 2047 pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs) { } 2048 #endif 2049 2050 void pci_cfg_access_lock(struct pci_dev *dev); 2051 bool pci_cfg_access_trylock(struct pci_dev *dev); 2052 void pci_cfg_access_unlock(struct pci_dev *dev); 2053 2054 void pci_dev_lock(struct pci_dev *dev); 2055 int pci_dev_trylock(struct pci_dev *dev); 2056 void pci_dev_unlock(struct pci_dev *dev); 2057 DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T)) 2058 2059 /* 2060 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 2061 * a PCI domain is defined to be a set of PCI buses which share 2062 * configuration space. 2063 */ 2064 #ifdef CONFIG_PCI_DOMAINS 2065 extern int pci_domains_supported; 2066 int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max); 2067 void pci_bus_release_emul_domain_nr(int domain_nr); 2068 #else 2069 enum { pci_domains_supported = 0 }; 2070 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2071 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 2072 static inline int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max) 2073 { 2074 return 0; 2075 } 2076 static inline void pci_bus_release_emul_domain_nr(int domain_nr) { } 2077 #endif /* CONFIG_PCI_DOMAINS */ 2078 2079 /* 2080 * Generic implementation for PCI domain support. If your 2081 * architecture does not need custom management of PCI 2082 * domains then this implementation will be used 2083 */ 2084 #ifdef CONFIG_PCI_DOMAINS_GENERIC 2085 static inline int pci_domain_nr(struct pci_bus *bus) 2086 { 2087 return bus->domain_nr; 2088 } 2089 #ifdef CONFIG_ACPI 2090 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 2091 #else 2092 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 2093 { return 0; } 2094 #endif 2095 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 2096 void pci_bus_release_domain_nr(struct device *parent, int domain_nr); 2097 #endif 2098 2099 /* Some architectures require additional setup to direct VGA traffic */ 2100 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 2101 unsigned int command_bits, u32 flags); 2102 void pci_register_set_vga_state(arch_set_vga_state_t func); 2103 2104 static inline int 2105 pci_request_io_regions(struct pci_dev *pdev, const char *name) 2106 { 2107 return pci_request_selected_regions(pdev, 2108 pci_select_bars(pdev, IORESOURCE_IO), name); 2109 } 2110 2111 static inline void 2112 pci_release_io_regions(struct pci_dev *pdev) 2113 { 2114 return pci_release_selected_regions(pdev, 2115 pci_select_bars(pdev, IORESOURCE_IO)); 2116 } 2117 2118 static inline int 2119 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 2120 { 2121 return pci_request_selected_regions(pdev, 2122 pci_select_bars(pdev, IORESOURCE_MEM), name); 2123 } 2124 2125 static inline void 2126 pci_release_mem_regions(struct pci_dev *pdev) 2127 { 2128 return pci_release_selected_regions(pdev, 2129 pci_select_bars(pdev, IORESOURCE_MEM)); 2130 } 2131 2132 bool pci_suspend_retains_context(struct pci_dev *pdev); 2133 2134 #else /* CONFIG_PCI is not enabled */ 2135 2136 static inline void pci_set_flags(int flags) { } 2137 static inline void pci_add_flags(int flags) { } 2138 static inline void pci_clear_flags(int flags) { } 2139 static inline int pci_has_flag(int flag) { return 0; } 2140 2141 /* 2142 * If the system does not have PCI, clearly these return errors. Define 2143 * these as simple inline functions to avoid hair in drivers. 2144 */ 2145 #define _PCI_NOP(o, s, t) \ 2146 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 2147 int where, t val) \ 2148 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 2149 2150 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 2151 _PCI_NOP(o, word, u16 x) \ 2152 _PCI_NOP(o, dword, u32 x) 2153 _PCI_NOP_ALL(read, *) 2154 _PCI_NOP_ALL(write,) 2155 2156 static inline void pci_probe_flush_workqueue(void) { } 2157 2158 static inline struct pci_dev *pci_get_device(unsigned int vendor, 2159 unsigned int device, 2160 struct pci_dev *from) 2161 { return NULL; } 2162 2163 static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor, 2164 unsigned int device, 2165 struct pci_dev *from) 2166 { return NULL; } 2167 2168 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 2169 unsigned int device, 2170 unsigned int ss_vendor, 2171 unsigned int ss_device, 2172 struct pci_dev *from) 2173 { return NULL; } 2174 2175 static inline struct pci_dev *pci_get_class(unsigned int class, 2176 struct pci_dev *from) 2177 { return NULL; } 2178 2179 static inline struct pci_dev *pci_get_base_class(unsigned int class, 2180 struct pci_dev *from) 2181 { return NULL; } 2182 2183 static inline int pci_dev_present(const struct pci_device_id *ids) 2184 { return 0; } 2185 2186 #define pci_dev_put(dev) do { } while (0) 2187 2188 static inline void pci_set_master(struct pci_dev *dev) { } 2189 static inline void pci_clear_master(struct pci_dev *dev) { } 2190 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 2191 static inline void pci_disable_device(struct pci_dev *dev) { } 2192 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 2193 static inline int pci_assign_resource(struct pci_dev *dev, int i) 2194 { return -EBUSY; } 2195 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 2196 struct module *owner, 2197 const char *mod_name) 2198 { return 0; } 2199 static inline int pci_register_driver(struct pci_driver *drv) 2200 { return 0; } 2201 static inline void pci_unregister_driver(struct pci_driver *drv) { } 2202 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 2203 { return 0; } 2204 static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap) 2205 { return 0; } 2206 static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap) 2207 { return 0; } 2208 2209 static inline u64 pci_get_dsn(struct pci_dev *dev) 2210 { return 0; } 2211 2212 /* Power management related routines */ 2213 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 2214 static inline void pci_restore_state(struct pci_dev *dev) { } 2215 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 2216 { return 0; } 2217 static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state) 2218 { return 0; } 2219 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 2220 { return 0; } 2221 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 2222 pm_message_t state) 2223 { return PCI_D0; } 2224 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 2225 int enable) 2226 { return 0; } 2227 2228 static inline struct resource *pci_find_resource(struct pci_dev *dev, 2229 struct resource *res) 2230 { return NULL; } 2231 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 2232 { return -EIO; } 2233 static inline void pci_release_regions(struct pci_dev *dev) { } 2234 2235 static inline int pci_register_io_range(const struct fwnode_handle *fwnode, 2236 phys_addr_t addr, resource_size_t size) 2237 { return -EINVAL; } 2238 2239 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 2240 2241 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 2242 { return NULL; } 2243 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 2244 unsigned int devfn) 2245 { return NULL; } 2246 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 2247 unsigned int bus, unsigned int devfn) 2248 { return NULL; } 2249 2250 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2251 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 2252 2253 #define dev_is_pci(d) (false) 2254 #define dev_is_pf(d) (false) 2255 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2256 { return false; } 2257 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 2258 struct device_node *node, 2259 const u32 *intspec, 2260 unsigned int intsize, 2261 unsigned long *out_hwirq, 2262 unsigned int *out_type) 2263 { return -EINVAL; } 2264 2265 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 2266 struct pci_dev *dev) 2267 { return NULL; } 2268 static inline bool pci_ats_disabled(void) { return true; } 2269 2270 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 2271 { 2272 return -EINVAL; 2273 } 2274 2275 static inline int 2276 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 2277 unsigned int max_vecs, unsigned int flags, 2278 struct irq_affinity *aff_desc) 2279 { 2280 return -ENOSPC; 2281 } 2282 static inline int 2283 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 2284 unsigned int max_vecs, unsigned int flags) 2285 { 2286 return -ENOSPC; 2287 } 2288 2289 static inline void pci_free_irq_vectors(struct pci_dev *dev) 2290 { 2291 } 2292 2293 static inline bool pci_suspend_retains_context(struct pci_dev *pdev) 2294 { 2295 return true; 2296 } 2297 2298 static inline unsigned int pci_irq_type(struct pci_dev *pdev) 2299 { 2300 return 0; 2301 } 2302 #endif /* CONFIG_PCI */ 2303 2304 /* Include architecture-dependent settings and functions */ 2305 2306 #include <asm/pci.h> 2307 2308 /* 2309 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 2310 * is expected to be an offset within that region. 2311 * 2312 */ 2313 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 2314 struct vm_area_struct *vma, 2315 enum pci_mmap_state mmap_state, int write_combine); 2316 2317 #ifndef arch_can_pci_mmap_wc 2318 #define arch_can_pci_mmap_wc() 0 2319 #endif 2320 2321 #ifndef arch_can_pci_mmap_io 2322 #define arch_can_pci_mmap_io() 0 2323 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 2324 #else 2325 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 2326 #endif 2327 2328 #ifndef pci_root_bus_fwnode 2329 #define pci_root_bus_fwnode(bus) NULL 2330 #endif 2331 2332 /* 2333 * These helpers provide future and backwards compatibility 2334 * for accessing popular PCI BAR info 2335 */ 2336 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)]) 2337 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start) 2338 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end) 2339 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags) 2340 #define pci_resource_len(dev,bar) \ 2341 (pci_resource_end((dev), (bar)) ? \ 2342 resource_size(pci_resource_n((dev), (bar))) : 0) 2343 2344 #define __pci_dev_for_each_res0(dev, res, ...) \ 2345 for (unsigned int __b = 0; \ 2346 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2347 __b++) 2348 2349 #define __pci_dev_for_each_res1(dev, res, __b) \ 2350 for (__b = 0; \ 2351 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2352 __b++) 2353 2354 #define pci_dev_for_each_resource(dev, res, ...) \ 2355 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 2356 (dev, res, __VA_ARGS__) 2357 2358 /** 2359 * pci_resource_is_io - check if a PCI resource is of I/O port type. 2360 * @dev: PCI device to check. 2361 * @resno: The resource number (BAR index) to check. 2362 * 2363 * Returns true if the resource type is I/O port. 2364 */ 2365 static inline bool pci_resource_is_io(const struct pci_dev *dev, int resno) 2366 { 2367 return resource_type(pci_resource_n(dev, resno)) == IORESOURCE_IO; 2368 } 2369 2370 /** 2371 * pci_resource_is_mem - check if a PCI resource is of memory type. 2372 * @dev: PCI device to check. 2373 * @resno: The resource number (BAR index) to check. 2374 * 2375 * Returns true if the resource type is memory, including 2376 * prefetchable memory. 2377 */ 2378 static inline bool pci_resource_is_mem(const struct pci_dev *dev, int resno) 2379 { 2380 return resource_type(pci_resource_n(dev, resno)) == IORESOURCE_MEM; 2381 } 2382 2383 /* 2384 * Similar to the helpers above, these manipulate per-pci_dev 2385 * driver-specific data. They are really just a wrapper around 2386 * the generic device structure functions of these calls. 2387 */ 2388 static inline void *pci_get_drvdata(struct pci_dev *pdev) 2389 { 2390 return dev_get_drvdata(&pdev->dev); 2391 } 2392 2393 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 2394 { 2395 dev_set_drvdata(&pdev->dev, data); 2396 } 2397 2398 static inline const char *pci_name(const struct pci_dev *pdev) 2399 { 2400 return dev_name(&pdev->dev); 2401 } 2402 2403 void pci_resource_to_user(const struct pci_dev *dev, int bar, 2404 const struct resource *rsrc, 2405 resource_size_t *start, resource_size_t *end); 2406 2407 /* 2408 * The world is not perfect and supplies us with broken PCI devices. 2409 * For at least a part of these bugs we need a work-around, so both 2410 * generic (drivers/pci/quirks.c) and per-architecture code can define 2411 * fixup hooks to be called for particular buggy devices. 2412 */ 2413 2414 struct pci_fixup { 2415 u16 vendor; /* Or PCI_ANY_ID */ 2416 u16 device; /* Or PCI_ANY_ID */ 2417 u32 class; /* Or PCI_ANY_ID */ 2418 unsigned int class_shift; /* should be 0, 8, 16 */ 2419 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2420 int hook_offset; 2421 #else 2422 void (*hook)(struct pci_dev *dev); 2423 #endif 2424 }; 2425 2426 enum pci_fixup_pass { 2427 pci_fixup_early, /* Before probing BARs */ 2428 pci_fixup_header, /* After reading configuration header */ 2429 pci_fixup_final, /* Final phase of device fixups */ 2430 pci_fixup_enable, /* pci_enable_device() time */ 2431 pci_fixup_resume, /* pci_device_resume() */ 2432 pci_fixup_suspend, /* pci_device_suspend() */ 2433 pci_fixup_resume_early, /* pci_device_resume_early() */ 2434 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2435 }; 2436 2437 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2438 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2439 class_shift, hook) \ 2440 __ADDRESSABLE(hook) \ 2441 asm(".section " #sec ", \"a\" \n" \ 2442 ".balign 16 \n" \ 2443 ".short " #vendor ", " #device " \n" \ 2444 ".long " #class ", " #class_shift " \n" \ 2445 ".long " #hook " - . \n" \ 2446 ".previous \n"); 2447 2448 /* 2449 * Clang's LTO may rename static functions in C, but has no way to 2450 * handle such renamings when referenced from inline asm. To work 2451 * around this, create global C stubs for these cases. 2452 */ 2453 #ifdef CONFIG_LTO_CLANG 2454 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2455 class_shift, hook, stub) \ 2456 void stub(struct pci_dev *dev); \ 2457 void stub(struct pci_dev *dev) \ 2458 { \ 2459 hook(dev); \ 2460 } \ 2461 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2462 class_shift, stub) 2463 #else 2464 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2465 class_shift, hook, stub) \ 2466 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2467 class_shift, hook) 2468 #endif 2469 2470 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2471 class_shift, hook) \ 2472 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2473 class_shift, hook, __UNIQUE_ID(hook)) 2474 #else 2475 /* Anonymous variables would be nice... */ 2476 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2477 class_shift, hook) \ 2478 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2479 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2480 = { vendor, device, class, class_shift, hook }; 2481 #endif 2482 2483 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2484 class_shift, hook) \ 2485 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2486 hook, vendor, device, class, class_shift, hook) 2487 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2488 class_shift, hook) \ 2489 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2490 hook, vendor, device, class, class_shift, hook) 2491 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2492 class_shift, hook) \ 2493 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2494 hook, vendor, device, class, class_shift, hook) 2495 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2496 class_shift, hook) \ 2497 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2498 hook, vendor, device, class, class_shift, hook) 2499 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2500 class_shift, hook) \ 2501 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2502 resume##hook, vendor, device, class, class_shift, hook) 2503 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2504 class_shift, hook) \ 2505 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2506 resume_early##hook, vendor, device, class, class_shift, hook) 2507 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2508 class_shift, hook) \ 2509 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2510 suspend##hook, vendor, device, class, class_shift, hook) 2511 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2512 class_shift, hook) \ 2513 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2514 suspend_late##hook, vendor, device, class, class_shift, hook) 2515 2516 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2517 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2518 hook, vendor, device, PCI_ANY_ID, 0, hook) 2519 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2520 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2521 hook, vendor, device, PCI_ANY_ID, 0, hook) 2522 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2523 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2524 hook, vendor, device, PCI_ANY_ID, 0, hook) 2525 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2526 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2527 hook, vendor, device, PCI_ANY_ID, 0, hook) 2528 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2529 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2530 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2531 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2532 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2533 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2534 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2535 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2536 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2537 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2538 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2539 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2540 2541 #ifdef CONFIG_PCI_QUIRKS 2542 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2543 #else 2544 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2545 struct pci_dev *dev) { } 2546 #endif 2547 2548 int pcim_intx(struct pci_dev *pdev, int enabled); 2549 int pcim_request_all_regions(struct pci_dev *pdev, const char *name); 2550 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2551 void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar, 2552 const char *name); 2553 void pcim_iounmap_region(struct pci_dev *pdev, int bar); 2554 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2555 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2556 int pcim_request_region(struct pci_dev *pdev, int bar, const char *name); 2557 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2558 void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar, 2559 unsigned long offset, unsigned long len); 2560 2561 extern int pci_pci_problems; 2562 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2563 #define PCIPCI_TRITON 2 2564 #define PCIPCI_NATOMA 4 2565 #define PCIPCI_VIAETBF 8 2566 #define PCIPCI_VSFX 16 2567 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2568 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2569 2570 extern u8 pci_dfl_cache_line_size; 2571 extern u8 pci_cache_line_size; 2572 2573 /* Architecture-specific versions may override these (weak) */ 2574 void pcibios_disable_device(struct pci_dev *dev); 2575 void pcibios_set_master(struct pci_dev *dev); 2576 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2577 enum pcie_reset_state state); 2578 int pcibios_device_add(struct pci_dev *dev); 2579 void pcibios_release_device(struct pci_dev *dev); 2580 #ifdef CONFIG_PCI 2581 void pcibios_penalize_isa_irq(int irq, int active); 2582 #else 2583 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2584 #endif 2585 int pcibios_alloc_irq(struct pci_dev *dev); 2586 void pcibios_free_irq(struct pci_dev *dev); 2587 resource_size_t pcibios_default_alignment(void); 2588 2589 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2590 void __init pci_mmcfg_early_init(void); 2591 void __init pci_mmcfg_late_init(void); 2592 #else 2593 static inline void pci_mmcfg_early_init(void) { } 2594 static inline void pci_mmcfg_late_init(void) { } 2595 #endif 2596 2597 int pci_ext_cfg_avail(void); 2598 2599 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2600 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2601 2602 #ifdef CONFIG_PCI_IOV 2603 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2604 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2605 int pci_iov_vf_id(struct pci_dev *dev); 2606 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2607 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2608 void pci_disable_sriov(struct pci_dev *dev); 2609 2610 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2611 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2612 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2613 int pci_num_vf(struct pci_dev *dev); 2614 int pci_vfs_assigned(struct pci_dev *dev); 2615 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2616 unsigned int pci_sriov_get_totalvfs(struct pci_dev *dev); 2617 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2618 resource_size_t pci_iov_resource_size(const struct pci_dev *dev, int resno); 2619 int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size); 2620 u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs); 2621 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2622 2623 /* Arch may override these (weak) */ 2624 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2625 int pcibios_sriov_disable(struct pci_dev *pdev); 2626 resource_size_t pcibios_iov_resource_alignment(const struct pci_dev *dev, 2627 int resno); 2628 #else 2629 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2630 { 2631 return -ENOSYS; 2632 } 2633 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2634 { 2635 return -ENOSYS; 2636 } 2637 2638 static inline int pci_iov_vf_id(struct pci_dev *dev) 2639 { 2640 return -ENOSYS; 2641 } 2642 2643 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2644 struct pci_driver *pf_driver) 2645 { 2646 return ERR_PTR(-EINVAL); 2647 } 2648 2649 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2650 { return -ENODEV; } 2651 2652 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2653 struct pci_dev *virtfn, int id) 2654 { 2655 return -ENODEV; 2656 } 2657 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2658 { 2659 return -ENOSYS; 2660 } 2661 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2662 int id) { } 2663 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2664 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2665 static inline int pci_vfs_assigned(struct pci_dev *dev) 2666 { return 0; } 2667 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2668 { return 0; } 2669 static inline unsigned int pci_sriov_get_totalvfs(struct pci_dev *dev) 2670 { return 0; } 2671 #define pci_sriov_configure_simple NULL 2672 static inline resource_size_t pci_iov_resource_size(const struct pci_dev *dev, 2673 int resno) 2674 { return 0; } 2675 static inline int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) 2676 { return -ENODEV; } 2677 static inline u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) 2678 { return 0; } 2679 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2680 #endif 2681 2682 /** 2683 * pci_pcie_cap - get the saved PCIe capability offset 2684 * @dev: PCI device 2685 * 2686 * PCIe capability offset is calculated at PCI device initialization 2687 * time and saved in the data structure. This function returns saved 2688 * PCIe capability offset. Using this instead of pci_find_capability() 2689 * reduces unnecessary search in the PCI configuration space. If you 2690 * need to calculate PCIe capability offset from raw device for some 2691 * reasons, please use pci_find_capability() instead. 2692 */ 2693 static inline int pci_pcie_cap(struct pci_dev *dev) 2694 { 2695 return dev->pcie_cap; 2696 } 2697 2698 /** 2699 * pci_is_pcie - check if the PCI device is PCI Express capable 2700 * @dev: PCI device 2701 * 2702 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2703 */ 2704 static inline bool pci_is_pcie(struct pci_dev *dev) 2705 { 2706 return pci_pcie_cap(dev); 2707 } 2708 2709 /** 2710 * pcie_caps_reg - get the PCIe Capabilities Register 2711 * @dev: PCI device 2712 */ 2713 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2714 { 2715 return dev->pcie_flags_reg; 2716 } 2717 2718 /** 2719 * pci_pcie_type - get the PCIe device/port type 2720 * @dev: PCI device 2721 */ 2722 static inline int pci_pcie_type(const struct pci_dev *dev) 2723 { 2724 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2725 } 2726 2727 /** 2728 * pcie_find_root_port - Get the PCIe root port device 2729 * @dev: PCI device 2730 * 2731 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2732 * for a given PCI/PCIe Device. 2733 */ 2734 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2735 { 2736 while (dev) { 2737 if (pci_is_pcie(dev) && 2738 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2739 return dev; 2740 dev = pci_upstream_bridge(dev); 2741 } 2742 2743 return NULL; 2744 } 2745 2746 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 2747 { 2748 /* 2749 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg() 2750 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache 2751 * the value (e.g. inside the loop in pci_dev_wait()). 2752 */ 2753 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure; 2754 } 2755 2756 void pci_request_acs(void); 2757 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2758 bool pci_acs_path_enabled(struct pci_dev *start, 2759 struct pci_dev *end, u16 acs_flags); 2760 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2761 2762 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2763 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2764 2765 /* Large Resource Data Type Tag Item Names */ 2766 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2767 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2768 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2769 2770 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2771 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2772 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2773 2774 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2775 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2776 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2777 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2778 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2779 2780 /** 2781 * pci_vpd_alloc - Allocate buffer and read VPD into it 2782 * @dev: PCI device 2783 * @size: pointer to field where VPD length is returned 2784 * 2785 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2786 */ 2787 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2788 2789 /** 2790 * pci_vpd_find_id_string - Locate id string in VPD 2791 * @buf: Pointer to buffered VPD data 2792 * @len: The length of the buffer area in which to search 2793 * @size: Pointer to field where length of id string is returned 2794 * 2795 * Returns the index of the id string or -ENOENT if not found. 2796 */ 2797 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2798 2799 /** 2800 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2801 * @buf: Pointer to buffered VPD data 2802 * @len: The length of the buffer area in which to search 2803 * @kw: The keyword to search for 2804 * @size: Pointer to field where length of found keyword data is returned 2805 * 2806 * Returns the index of the information field keyword data or -ENOENT if 2807 * not found. 2808 */ 2809 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2810 const char *kw, unsigned int *size); 2811 2812 /** 2813 * pci_vpd_check_csum - Check VPD checksum 2814 * @buf: Pointer to buffered VPD data 2815 * @len: VPD size 2816 * 2817 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2818 */ 2819 int pci_vpd_check_csum(const void *buf, unsigned int len); 2820 2821 /* PCI <-> OF binding helpers */ 2822 #ifdef CONFIG_OF 2823 struct device_node; 2824 struct irq_domain; 2825 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2826 bool pci_host_of_has_msi_map(struct device *dev); 2827 2828 /* Arch may override this (weak) */ 2829 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2830 2831 #else /* CONFIG_OF */ 2832 static inline struct irq_domain * 2833 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2834 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2835 #endif /* CONFIG_OF */ 2836 2837 static inline struct device_node * 2838 pci_device_to_OF_node(const struct pci_dev *pdev) 2839 { 2840 return pdev ? pdev->dev.of_node : NULL; 2841 } 2842 2843 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2844 { 2845 return bus ? bus->dev.of_node : NULL; 2846 } 2847 2848 #ifdef CONFIG_ACPI 2849 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2850 2851 void 2852 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2853 bool pci_pr3_present(struct pci_dev *pdev); 2854 #else 2855 static inline struct irq_domain * 2856 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2857 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2858 #endif 2859 2860 #if defined(CONFIG_X86) && defined(CONFIG_ACPI) 2861 bool arch_pci_dev_is_removable(struct pci_dev *pdev); 2862 #else 2863 static inline bool arch_pci_dev_is_removable(struct pci_dev *pdev) { return false; } 2864 #endif 2865 2866 #ifdef CONFIG_EEH 2867 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2868 { 2869 return pdev->dev.archdata.edev; 2870 } 2871 #endif 2872 2873 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2874 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2875 int pci_for_each_dma_alias(struct pci_dev *pdev, 2876 int (*fn)(struct pci_dev *pdev, 2877 u16 alias, void *data), void *data); 2878 2879 /* Helper functions for operation of device flag */ 2880 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2881 { 2882 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2883 } 2884 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2885 { 2886 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2887 } 2888 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2889 { 2890 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2891 } 2892 2893 /** 2894 * pci_ari_enabled - query ARI forwarding status 2895 * @bus: the PCI bus 2896 * 2897 * Returns true if ARI forwarding is enabled. 2898 */ 2899 static inline bool pci_ari_enabled(struct pci_bus *bus) 2900 { 2901 return bus->self && bus->self->ari_enabled; 2902 } 2903 2904 /** 2905 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2906 * @pdev: PCI device to check 2907 * 2908 * Walk upwards from @pdev and check for each encountered bridge if it's part 2909 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2910 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2911 */ 2912 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2913 { 2914 struct pci_dev *parent = pdev; 2915 2916 if (pdev->is_thunderbolt) 2917 return true; 2918 2919 while ((parent = pci_upstream_bridge(parent))) 2920 if (parent->is_thunderbolt) 2921 return true; 2922 2923 return false; 2924 } 2925 2926 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) || defined(CONFIG_S390) 2927 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2928 #endif 2929 2930 #include <linux/dma-mapping.h> 2931 2932 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2933 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2934 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2935 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2936 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2937 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2938 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2939 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2940 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2941 2942 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2943 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2944 2945 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2946 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2947 2948 #define pci_WARN(pdev, condition, fmt, arg...) \ 2949 WARN(condition, "%s %s: " fmt, \ 2950 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2951 2952 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2953 WARN_ONCE(condition, "%s %s: " fmt, \ 2954 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2955 2956 #endif /* LINUX_PCI_H */ 2957