1 /*
2 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
30
31 #include "dm_services.h"
32
33 #include "link_encoder.h"
34 #include "stream_encoder.h"
35
36 #include "resource.h"
37 #include "clk_mgr.h"
38 #include "include/irq_service_interface.h"
39 #include "irq/dce60/irq_service_dce60.h"
40 #include "dce110/dce110_timing_generator.h"
41 #include "dce110/dce110_resource.h"
42 #include "dce60/dce60_timing_generator.h"
43 #include "dce/dce_mem_input.h"
44 #include "dce/dce_link_encoder.h"
45 #include "dce/dce_stream_encoder.h"
46 #include "dce/dce_ipp.h"
47 #include "dce/dce_transform.h"
48 #include "dce/dce_opp.h"
49 #include "dce/dce_clock_source.h"
50 #include "dce/dce_audio.h"
51 #include "dce/dce_hwseq.h"
52 #include "dce60/dce60_hwseq.h"
53 #include "dce100/dce100_resource.h"
54 #include "dce/dce_panel_cntl.h"
55
56 #include "reg_helper.h"
57
58 #include "dce/dce_dmcu.h"
59 #include "dce/dce_aux.h"
60 #include "dce/dce_abm.h"
61 #include "dce/dce_i2c.h"
62 /* TODO remove this include */
63
64 #include "dce60_resource.h"
65
66 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
67 #include "gmc/gmc_6_0_d.h"
68 #include "gmc/gmc_6_0_sh_mask.h"
69 #endif
70
71 #ifndef mmDP_DPHY_INTERNAL_CTRL
72 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
73 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
74 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
75 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
76 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
77 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
78 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
79 #endif
80
81
82 #ifndef mmBIOS_SCRATCH_2
83 #define mmBIOS_SCRATCH_2 0x05CB
84 #define mmBIOS_SCRATCH_3 0x05CC
85 #define mmBIOS_SCRATCH_6 0x05CF
86 #endif
87
88 #ifndef mmDP_DPHY_FAST_TRAINING
89 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
90 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
91 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
92 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
93 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
94 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
95 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
96 #endif
97
98
99 #ifndef mmHPD_DC_HPD_CONTROL
100 #define mmHPD_DC_HPD_CONTROL 0x189A
101 #define mmHPD0_DC_HPD_CONTROL 0x189A
102 #define mmHPD1_DC_HPD_CONTROL 0x18A2
103 #define mmHPD2_DC_HPD_CONTROL 0x18AA
104 #define mmHPD3_DC_HPD_CONTROL 0x18B2
105 #define mmHPD4_DC_HPD_CONTROL 0x18BA
106 #define mmHPD5_DC_HPD_CONTROL 0x18C2
107 #endif
108
109 #define DCE11_DIG_FE_CNTL 0x4a00
110 #define DCE11_DIG_BE_CNTL 0x4a47
111 #define DCE11_DP_SEC 0x4ac3
112
113 static const struct dce110_timing_generator_offsets dce60_tg_offsets[] = {
114 {
115 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
116 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
117 .dmif = (mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3
118 - mmDPG_PIPE_ARBITRATION_CONTROL3),
119 },
120 {
121 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
123 .dmif = (mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3
124 - mmDPG_PIPE_ARBITRATION_CONTROL3),
125 },
126 {
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
129 .dmif = (mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3
130 - mmDPG_PIPE_ARBITRATION_CONTROL3),
131 },
132 {
133 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
134 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
135 .dmif = (mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3
136 - mmDPG_PIPE_ARBITRATION_CONTROL3),
137 },
138 {
139 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
140 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
141 .dmif = (mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3
142 - mmDPG_PIPE_ARBITRATION_CONTROL3),
143 },
144 {
145 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
146 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
147 .dmif = (mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3
148 - mmDPG_PIPE_ARBITRATION_CONTROL3),
149 }
150 };
151
152 /* set register offset */
153 #define SR(reg_name)\
154 .reg_name = mm ## reg_name
155
156 /* set register offset with instance */
157 #define SRI(reg_name, block, id)\
158 .reg_name = mm ## block ## id ## _ ## reg_name
159
160 #define ipp_regs(id)\
161 [id] = {\
162 IPP_COMMON_REG_LIST_DCE_BASE(id)\
163 }
164
165 static const struct dce_ipp_registers ipp_regs[] = {
166 ipp_regs(0),
167 ipp_regs(1),
168 ipp_regs(2),
169 ipp_regs(3),
170 ipp_regs(4),
171 ipp_regs(5)
172 };
173
174 static const struct dce_ipp_shift ipp_shift = {
175 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
176 };
177
178 static const struct dce_ipp_mask ipp_mask = {
179 IPP_DCE60_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
180 };
181
182 #define transform_regs(id)\
183 [id] = {\
184 XFM_COMMON_REG_LIST_DCE60(id)\
185 }
186
187 static const struct dce_transform_registers xfm_regs[] = {
188 transform_regs(0),
189 transform_regs(1),
190 transform_regs(2),
191 transform_regs(3),
192 transform_regs(4),
193 transform_regs(5)
194 };
195
196 static const struct dce_transform_shift xfm_shift = {
197 XFM_COMMON_MASK_SH_LIST_DCE60(__SHIFT)
198 };
199
200 static const struct dce_transform_mask xfm_mask = {
201 XFM_COMMON_MASK_SH_LIST_DCE60(_MASK)
202 };
203
204 #define aux_regs(id)\
205 [id] = {\
206 AUX_REG_LIST(id)\
207 }
208
209 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
210 aux_regs(0),
211 aux_regs(1),
212 aux_regs(2),
213 aux_regs(3),
214 aux_regs(4),
215 aux_regs(5)
216 };
217
218 #define hpd_regs(id)\
219 [id] = {\
220 HPD_REG_LIST(id)\
221 }
222
223 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
224 hpd_regs(0),
225 hpd_regs(1),
226 hpd_regs(2),
227 hpd_regs(3),
228 hpd_regs(4),
229 hpd_regs(5)
230 };
231
232 #define link_regs(id)\
233 [id] = {\
234 LE_DCE60_REG_LIST(id)\
235 }
236
237 static const struct dce110_link_enc_registers link_enc_regs[] = {
238 link_regs(0),
239 link_regs(1),
240 link_regs(2),
241 link_regs(3),
242 link_regs(4),
243 link_regs(5)
244 };
245
246 #define stream_enc_regs(id)\
247 [id] = {\
248 SE_COMMON_REG_LIST_DCE_BASE(id),\
249 .AFMT_CNTL = 0,\
250 }
251
252 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
253 stream_enc_regs(0),
254 stream_enc_regs(1),
255 stream_enc_regs(2),
256 stream_enc_regs(3),
257 stream_enc_regs(4),
258 stream_enc_regs(5)
259 };
260
261 static const struct dce_stream_encoder_shift se_shift = {
262 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
263 };
264
265 static const struct dce_stream_encoder_mask se_mask = {
266 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
267 };
268
269 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
270 { DCE_PANEL_CNTL_REG_LIST() }
271 };
272
273 static const struct dce_panel_cntl_shift panel_cntl_shift = {
274 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
275 };
276
277 static const struct dce_panel_cntl_mask panel_cntl_mask = {
278 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
279 };
280
281 #define opp_regs(id)\
282 [id] = {\
283 OPP_DCE_60_REG_LIST(id),\
284 }
285
286 static const struct dce_opp_registers opp_regs[] = {
287 opp_regs(0),
288 opp_regs(1),
289 opp_regs(2),
290 opp_regs(3),
291 opp_regs(4),
292 opp_regs(5)
293 };
294
295 static const struct dce_opp_shift opp_shift = {
296 OPP_COMMON_MASK_SH_LIST_DCE_60(__SHIFT)
297 };
298
299 static const struct dce_opp_mask opp_mask = {
300 OPP_COMMON_MASK_SH_LIST_DCE_60(_MASK)
301 };
302
303 static const struct dce110_aux_registers_shift aux_shift = {
304 DCE10_AUX_MASK_SH_LIST(__SHIFT)
305 };
306
307 static const struct dce110_aux_registers_mask aux_mask = {
308 DCE10_AUX_MASK_SH_LIST(_MASK)
309 };
310
311 #define aux_engine_regs(id)\
312 [id] = {\
313 AUX_COMMON_REG_LIST(id), \
314 .AUX_RESET_MASK = 0 \
315 }
316
317 static const struct dce110_aux_registers aux_engine_regs[] = {
318 aux_engine_regs(0),
319 aux_engine_regs(1),
320 aux_engine_regs(2),
321 aux_engine_regs(3),
322 aux_engine_regs(4),
323 aux_engine_regs(5)
324 };
325
326 #define audio_regs(id)\
327 [id] = {\
328 AUD_COMMON_REG_LIST(id)\
329 }
330
331 static const struct dce_audio_registers audio_regs[] = {
332 audio_regs(0),
333 audio_regs(1),
334 audio_regs(2),
335 audio_regs(3),
336 audio_regs(4),
337 audio_regs(5),
338 };
339
340 static const struct dce_audio_shift audio_shift = {
341 AUD_DCE60_MASK_SH_LIST(__SHIFT)
342 };
343
344 static const struct dce_audio_mask audio_mask = {
345 AUD_DCE60_MASK_SH_LIST(_MASK)
346 };
347
348 #define clk_src_regs(id)\
349 [id] = {\
350 CS_COMMON_REG_LIST_DCE_80(id),\
351 }
352
353
354 static const struct dce110_clk_src_regs clk_src_regs[] = {
355 clk_src_regs(0),
356 clk_src_regs(1),
357 clk_src_regs(2)
358 };
359
360 static const struct dce110_clk_src_shift cs_shift = {
361 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
362 };
363
364 static const struct dce110_clk_src_mask cs_mask = {
365 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
366 };
367
368 static const struct bios_registers bios_regs = {
369 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
370 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
371 };
372
373 static const struct resource_caps res_cap = {
374 .num_timing_generator = 6,
375 .num_audio = 6,
376 .num_stream_encoder = 6,
377 .num_pll = 3,
378 .num_ddc = 6,
379 };
380
381 static const struct resource_caps res_cap_61 = {
382 .num_timing_generator = 4,
383 .num_audio = 6,
384 .num_stream_encoder = 6,
385 .num_pll = 3,
386 .num_ddc = 6,
387 };
388
389 static const struct resource_caps res_cap_64 = {
390 .num_timing_generator = 2,
391 .num_audio = 2,
392 .num_stream_encoder = 2,
393 .num_pll = 3,
394 .num_ddc = 2,
395 };
396
397 static const struct dc_plane_cap plane_cap = {
398 .type = DC_PLANE_TYPE_DCE_RGB,
399
400 .pixel_format_support = {
401 .argb8888 = true,
402 .nv12 = false,
403 .fp16 = false
404 },
405
406 .max_upscale_factor = {
407 .argb8888 = 1,
408 .nv12 = 1,
409 .fp16 = 1
410 },
411
412 .max_downscale_factor = {
413 .argb8888 = 1,
414 .nv12 = 1,
415 .fp16 = 1
416 }
417 };
418
419 static const struct dce_dmcu_registers dmcu_regs = {
420 DMCU_DCE60_REG_LIST()
421 };
422
423 static const struct dce_dmcu_shift dmcu_shift = {
424 DMCU_MASK_SH_LIST_DCE60(__SHIFT)
425 };
426
427 static const struct dce_dmcu_mask dmcu_mask = {
428 DMCU_MASK_SH_LIST_DCE60(_MASK)
429 };
430 static const struct dce_abm_registers abm_regs = {
431 ABM_DCE110_COMMON_REG_LIST()
432 };
433
434 static const struct dce_abm_shift abm_shift = {
435 ABM_MASK_SH_LIST_DCE110(__SHIFT)
436 };
437
438 static const struct dce_abm_mask abm_mask = {
439 ABM_MASK_SH_LIST_DCE110(_MASK)
440 };
441
442 #define CTX ctx
443 #define REG(reg) mm ## reg
444
445 #ifndef mmCC_DC_HDMI_STRAPS
446 #define mmCC_DC_HDMI_STRAPS 0x1918
447 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
448 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
449 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
450 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
451 #endif
452
map_transmitter_id_to_phy_instance(enum transmitter transmitter)453 static int map_transmitter_id_to_phy_instance(
454 enum transmitter transmitter)
455 {
456 switch (transmitter) {
457 case TRANSMITTER_UNIPHY_A:
458 return 0;
459 case TRANSMITTER_UNIPHY_B:
460 return 1;
461 case TRANSMITTER_UNIPHY_C:
462 return 2;
463 case TRANSMITTER_UNIPHY_D:
464 return 3;
465 case TRANSMITTER_UNIPHY_E:
466 return 4;
467 case TRANSMITTER_UNIPHY_F:
468 return 5;
469 case TRANSMITTER_UNIPHY_G:
470 return 6;
471 default:
472 ASSERT(0);
473 return 0;
474 }
475 }
476
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)477 static void read_dce_straps(
478 struct dc_context *ctx,
479 struct resource_straps *straps)
480 {
481 REG_GET_2(CC_DC_HDMI_STRAPS,
482 HDMI_DISABLE, &straps->hdmi_disable,
483 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
484
485 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
486 }
487
create_audio(struct dc_context * ctx,unsigned int inst)488 static struct audio *create_audio(
489 struct dc_context *ctx, unsigned int inst)
490 {
491 return dce60_audio_create(ctx, inst,
492 &audio_regs[inst], &audio_shift, &audio_mask);
493 }
494
dce60_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)495 static struct timing_generator *dce60_timing_generator_create(
496 struct dc_context *ctx,
497 uint32_t instance,
498 const struct dce110_timing_generator_offsets *offsets)
499 {
500 struct dce110_timing_generator *tg110 =
501 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
502
503 if (!tg110)
504 return NULL;
505
506 dce60_timing_generator_construct(tg110, ctx, instance, offsets);
507 return &tg110->base;
508 }
509
dce60_opp_create(struct dc_context * ctx,uint32_t inst)510 static struct output_pixel_processor *dce60_opp_create(
511 struct dc_context *ctx,
512 uint32_t inst)
513 {
514 struct dce110_opp *opp =
515 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
516
517 if (!opp)
518 return NULL;
519
520 dce60_opp_construct(opp,
521 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
522 return &opp->base;
523 }
524
dce60_aux_engine_create(struct dc_context * ctx,uint32_t inst)525 static struct dce_aux *dce60_aux_engine_create(
526 struct dc_context *ctx,
527 uint32_t inst)
528 {
529 struct aux_engine_dce110 *aux_engine =
530 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
531
532 if (!aux_engine)
533 return NULL;
534
535 dce110_aux_engine_construct(aux_engine, ctx, inst,
536 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
537 &aux_engine_regs[inst],
538 &aux_mask,
539 &aux_shift,
540 ctx->dc->caps.extended_aux_timeout_support);
541
542 return &aux_engine->base;
543 }
544 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
545
546 static const struct dce_i2c_registers i2c_hw_regs[] = {
547 i2c_inst_regs(1),
548 i2c_inst_regs(2),
549 i2c_inst_regs(3),
550 i2c_inst_regs(4),
551 i2c_inst_regs(5),
552 i2c_inst_regs(6),
553 };
554
555 static const struct dce_i2c_shift i2c_shifts = {
556 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
557 };
558
559 static const struct dce_i2c_mask i2c_masks = {
560 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
561 };
562
dce60_i2c_hw_create(struct dc_context * ctx,uint32_t inst)563 static struct dce_i2c_hw *dce60_i2c_hw_create(
564 struct dc_context *ctx,
565 uint32_t inst)
566 {
567 struct dce_i2c_hw *dce_i2c_hw =
568 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
569
570 if (!dce_i2c_hw)
571 return NULL;
572
573 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
574 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
575
576 return dce_i2c_hw;
577 }
578
dce60_i2c_sw_create(struct dc_context * ctx)579 static struct dce_i2c_sw *dce60_i2c_sw_create(
580 struct dc_context *ctx)
581 {
582 struct dce_i2c_sw *dce_i2c_sw =
583 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
584
585 if (!dce_i2c_sw)
586 return NULL;
587
588 dce_i2c_sw_construct(dce_i2c_sw, ctx);
589
590 return dce_i2c_sw;
591 }
dce60_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)592 static struct stream_encoder *dce60_stream_encoder_create(
593 enum engine_id eng_id,
594 struct dc_context *ctx)
595 {
596 struct dce110_stream_encoder *enc110 =
597 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
598
599 if (!enc110)
600 return NULL;
601
602 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
603 &stream_enc_regs[eng_id],
604 &se_shift, &se_mask);
605 return &enc110->base;
606 }
607
608 #define SRII(reg_name, block, id)\
609 .reg_name[id] = mm ## block ## id ## _ ## reg_name
610
611 static const struct dce_hwseq_registers hwseq_reg = {
612 HWSEQ_DCE6_REG_LIST()
613 };
614
615 static const struct dce_hwseq_shift hwseq_shift = {
616 HWSEQ_DCE6_MASK_SH_LIST(__SHIFT)
617 };
618
619 static const struct dce_hwseq_mask hwseq_mask = {
620 HWSEQ_DCE6_MASK_SH_LIST(_MASK)
621 };
622
dce60_hwseq_create(struct dc_context * ctx)623 static struct dce_hwseq *dce60_hwseq_create(
624 struct dc_context *ctx)
625 {
626 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
627
628 if (hws) {
629 hws->ctx = ctx;
630 hws->regs = &hwseq_reg;
631 hws->shifts = &hwseq_shift;
632 hws->masks = &hwseq_mask;
633 }
634 return hws;
635 }
636
637 static const struct resource_create_funcs res_create_funcs = {
638 .read_dce_straps = read_dce_straps,
639 .create_audio = create_audio,
640 .create_stream_encoder = dce60_stream_encoder_create,
641 .create_hwseq = dce60_hwseq_create,
642 };
643
644 #define mi_inst_regs(id) { \
645 MI_DCE6_REG_LIST(id), \
646 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
647 }
648 static const struct dce_mem_input_registers mi_regs[] = {
649 mi_inst_regs(0),
650 mi_inst_regs(1),
651 mi_inst_regs(2),
652 mi_inst_regs(3),
653 mi_inst_regs(4),
654 mi_inst_regs(5),
655 };
656
657 static const struct dce_mem_input_shift mi_shifts = {
658 MI_DCE6_MASK_SH_LIST(__SHIFT),
659 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
660 };
661
662 static const struct dce_mem_input_mask mi_masks = {
663 MI_DCE6_MASK_SH_LIST(_MASK),
664 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
665 };
666
dce60_mem_input_create(struct dc_context * ctx,uint32_t inst)667 static struct mem_input *dce60_mem_input_create(
668 struct dc_context *ctx,
669 uint32_t inst)
670 {
671 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
672 GFP_KERNEL);
673
674 if (!dce_mi) {
675 BREAK_TO_DEBUGGER();
676 return NULL;
677 }
678
679 dce60_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
680 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
681 return &dce_mi->base;
682 }
683
dce60_transform_destroy(struct transform ** xfm)684 static void dce60_transform_destroy(struct transform **xfm)
685 {
686 kfree(TO_DCE_TRANSFORM(*xfm));
687 *xfm = NULL;
688 }
689
dce60_transform_create(struct dc_context * ctx,uint32_t inst)690 static struct transform *dce60_transform_create(
691 struct dc_context *ctx,
692 uint32_t inst)
693 {
694 struct dce_transform *transform =
695 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
696
697 if (!transform)
698 return NULL;
699
700 dce60_transform_construct(transform, ctx, inst,
701 &xfm_regs[inst], &xfm_shift, &xfm_mask);
702 transform->prescaler_on = false;
703 return &transform->base;
704 }
705
706 static const struct encoder_feature_support link_enc_feature = {
707 .max_hdmi_deep_color = COLOR_DEPTH_121212,
708 .max_hdmi_pixel_clock = 297000,
709 .flags.bits.IS_HBR2_CAPABLE = true,
710 .flags.bits.IS_TPS3_CAPABLE = true
711 };
712
dce60_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)713 static struct link_encoder *dce60_link_encoder_create(
714 struct dc_context *ctx,
715 const struct encoder_init_data *enc_init_data)
716 {
717 struct dce110_link_encoder *enc110 =
718 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
719 int link_regs_id;
720
721 if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
722 return NULL;
723
724 link_regs_id =
725 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
726
727 dce60_link_encoder_construct(enc110,
728 enc_init_data,
729 &link_enc_feature,
730 &link_enc_regs[link_regs_id],
731 &link_enc_aux_regs[enc_init_data->channel - 1],
732 &link_enc_hpd_regs[enc_init_data->hpd_source]);
733 return &enc110->base;
734 }
735
dce60_panel_cntl_create(const struct panel_cntl_init_data * init_data)736 static struct panel_cntl *dce60_panel_cntl_create(const struct panel_cntl_init_data *init_data)
737 {
738 struct dce_panel_cntl *panel_cntl =
739 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
740
741 if (!panel_cntl)
742 return NULL;
743
744 dce_panel_cntl_construct(panel_cntl,
745 init_data,
746 &panel_cntl_regs[init_data->inst],
747 &panel_cntl_shift,
748 &panel_cntl_mask);
749
750 return &panel_cntl->base;
751 }
752
dce60_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)753 static struct clock_source *dce60_clock_source_create(
754 struct dc_context *ctx,
755 struct dc_bios *bios,
756 enum clock_source_id id,
757 const struct dce110_clk_src_regs *regs,
758 bool dp_clk_src)
759 {
760 struct dce110_clk_src *clk_src =
761 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
762
763 if (!clk_src)
764 return NULL;
765
766 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
767 regs, &cs_shift, &cs_mask)) {
768 clk_src->base.dp_clk_src = dp_clk_src;
769 return &clk_src->base;
770 }
771
772 kfree(clk_src);
773 BREAK_TO_DEBUGGER();
774 return NULL;
775 }
776
dce60_clock_source_destroy(struct clock_source ** clk_src)777 static void dce60_clock_source_destroy(struct clock_source **clk_src)
778 {
779 kfree(TO_DCE110_CLK_SRC(*clk_src));
780 *clk_src = NULL;
781 }
782
dce60_ipp_create(struct dc_context * ctx,uint32_t inst)783 static struct input_pixel_processor *dce60_ipp_create(
784 struct dc_context *ctx, uint32_t inst)
785 {
786 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
787
788 if (!ipp) {
789 BREAK_TO_DEBUGGER();
790 return NULL;
791 }
792
793 dce60_ipp_construct(ipp, ctx, inst,
794 &ipp_regs[inst], &ipp_shift, &ipp_mask);
795 return &ipp->base;
796 }
797
dce60_resource_destruct(struct dce110_resource_pool * pool)798 static void dce60_resource_destruct(struct dce110_resource_pool *pool)
799 {
800 unsigned int i;
801
802 for (i = 0; i < pool->base.pipe_count; i++) {
803 if (pool->base.opps[i] != NULL)
804 dce110_opp_destroy(&pool->base.opps[i]);
805
806 if (pool->base.transforms[i] != NULL)
807 dce60_transform_destroy(&pool->base.transforms[i]);
808
809 if (pool->base.ipps[i] != NULL)
810 dce_ipp_destroy(&pool->base.ipps[i]);
811
812 if (pool->base.mis[i] != NULL) {
813 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
814 pool->base.mis[i] = NULL;
815 }
816
817 if (pool->base.timing_generators[i] != NULL) {
818 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
819 pool->base.timing_generators[i] = NULL;
820 }
821 }
822
823 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
824 if (pool->base.engines[i] != NULL)
825 dce110_engine_destroy(&pool->base.engines[i]);
826 if (pool->base.hw_i2cs[i] != NULL) {
827 kfree(pool->base.hw_i2cs[i]);
828 pool->base.hw_i2cs[i] = NULL;
829 }
830 if (pool->base.sw_i2cs[i] != NULL) {
831 kfree(pool->base.sw_i2cs[i]);
832 pool->base.sw_i2cs[i] = NULL;
833 }
834 }
835
836 for (i = 0; i < pool->base.stream_enc_count; i++) {
837 if (pool->base.stream_enc[i] != NULL)
838 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
839 }
840
841 for (i = 0; i < pool->base.clk_src_count; i++) {
842 if (pool->base.clock_sources[i] != NULL) {
843 dce60_clock_source_destroy(&pool->base.clock_sources[i]);
844 }
845 }
846
847 if (pool->base.abm != NULL)
848 dce_abm_destroy(&pool->base.abm);
849
850 if (pool->base.dmcu != NULL)
851 dce_dmcu_destroy(&pool->base.dmcu);
852
853 if (pool->base.dp_clock_source != NULL)
854 dce60_clock_source_destroy(&pool->base.dp_clock_source);
855
856 for (i = 0; i < pool->base.audio_count; i++) {
857 if (pool->base.audios[i] != NULL) {
858 dce_aud_destroy(&pool->base.audios[i]);
859 }
860 }
861
862 if (pool->base.irqs != NULL) {
863 dal_irq_service_destroy(&pool->base.irqs);
864 }
865 }
866
dce60_destroy_resource_pool(struct resource_pool ** pool)867 static void dce60_destroy_resource_pool(struct resource_pool **pool)
868 {
869 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
870
871 dce60_resource_destruct(dce110_pool);
872 kfree(dce110_pool);
873 *pool = NULL;
874 }
875
876 static const struct resource_funcs dce60_res_pool_funcs = {
877 .destroy = dce60_destroy_resource_pool,
878 .link_enc_create = dce60_link_encoder_create,
879 .panel_cntl_create = dce60_panel_cntl_create,
880 .validate_bandwidth = dce100_validate_bandwidth,
881 .validate_plane = dce100_validate_plane,
882 .add_stream_to_ctx = dce100_add_stream_to_ctx,
883 .validate_global = dce100_validate_global,
884 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
885 };
886
dce60_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)887 static bool dce60_construct(
888 uint8_t num_virtual_links,
889 struct dc *dc,
890 struct dce110_resource_pool *pool)
891 {
892 unsigned int i;
893 struct dc_context *ctx = dc->ctx;
894 struct dc_bios *bp;
895
896 ctx->dc_bios->regs = &bios_regs;
897
898 pool->base.res_cap = &res_cap;
899 pool->base.funcs = &dce60_res_pool_funcs;
900
901
902 /*************************************************
903 * Resource + asic cap harcoding *
904 *************************************************/
905 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
906 pool->base.pipe_count = res_cap.num_timing_generator;
907 pool->base.timing_generator_count = res_cap.num_timing_generator;
908 dc->caps.max_downscale_ratio = 200;
909 dc->caps.i2c_speed_in_khz = 40;
910 dc->caps.max_cursor_size = 64;
911 dc->caps.dual_link_dvi = true;
912 dc->caps.extended_aux_timeout_support = false;
913
914 /*************************************************
915 * Create resources *
916 *************************************************/
917
918 bp = ctx->dc_bios;
919
920 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
921 pool->base.dp_clock_source =
922 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
923
924 /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
925 pool->base.clock_sources[0] =
926 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
927 pool->base.clock_sources[1] =
928 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
929 pool->base.clk_src_count = 2;
930
931 } else {
932 pool->base.dp_clock_source =
933 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
934
935 pool->base.clock_sources[0] =
936 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
937 pool->base.clock_sources[1] =
938 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
939 pool->base.clk_src_count = 2;
940 }
941
942 if (pool->base.dp_clock_source == NULL) {
943 dm_error("DC: failed to create dp clock source!\n");
944 BREAK_TO_DEBUGGER();
945 goto res_create_fail;
946 }
947
948 for (i = 0; i < pool->base.clk_src_count; i++) {
949 if (pool->base.clock_sources[i] == NULL) {
950 dm_error("DC: failed to create clock sources!\n");
951 BREAK_TO_DEBUGGER();
952 goto res_create_fail;
953 }
954 }
955
956 pool->base.dmcu = dce_dmcu_create(ctx,
957 &dmcu_regs,
958 &dmcu_shift,
959 &dmcu_mask);
960 if (pool->base.dmcu == NULL) {
961 dm_error("DC: failed to create dmcu!\n");
962 BREAK_TO_DEBUGGER();
963 goto res_create_fail;
964 }
965
966 pool->base.abm = dce_abm_create(ctx,
967 &abm_regs,
968 &abm_shift,
969 &abm_mask);
970 if (pool->base.abm == NULL) {
971 dm_error("DC: failed to create abm!\n");
972 BREAK_TO_DEBUGGER();
973 goto res_create_fail;
974 }
975
976 {
977 struct irq_service_init_data init_data;
978 init_data.ctx = dc->ctx;
979 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
980 if (!pool->base.irqs)
981 goto res_create_fail;
982 }
983
984 for (i = 0; i < pool->base.pipe_count; i++) {
985 pool->base.timing_generators[i] = dce60_timing_generator_create(
986 ctx, i, &dce60_tg_offsets[i]);
987 if (pool->base.timing_generators[i] == NULL) {
988 BREAK_TO_DEBUGGER();
989 dm_error("DC: failed to create tg!\n");
990 goto res_create_fail;
991 }
992
993 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
994 if (pool->base.mis[i] == NULL) {
995 BREAK_TO_DEBUGGER();
996 dm_error("DC: failed to create memory input!\n");
997 goto res_create_fail;
998 }
999
1000 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1001 if (pool->base.ipps[i] == NULL) {
1002 BREAK_TO_DEBUGGER();
1003 dm_error("DC: failed to create input pixel processor!\n");
1004 goto res_create_fail;
1005 }
1006
1007 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1008 if (pool->base.transforms[i] == NULL) {
1009 BREAK_TO_DEBUGGER();
1010 dm_error("DC: failed to create transform!\n");
1011 goto res_create_fail;
1012 }
1013
1014 pool->base.opps[i] = dce60_opp_create(ctx, i);
1015 if (pool->base.opps[i] == NULL) {
1016 BREAK_TO_DEBUGGER();
1017 dm_error("DC: failed to create output pixel processor!\n");
1018 goto res_create_fail;
1019 }
1020 }
1021
1022 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1023 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1024 if (pool->base.engines[i] == NULL) {
1025 BREAK_TO_DEBUGGER();
1026 dm_error(
1027 "DC:failed to create aux engine!!\n");
1028 goto res_create_fail;
1029 }
1030 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1031 if (pool->base.hw_i2cs[i] == NULL) {
1032 BREAK_TO_DEBUGGER();
1033 dm_error(
1034 "DC:failed to create i2c engine!!\n");
1035 goto res_create_fail;
1036 }
1037 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1038 if (pool->base.sw_i2cs[i] == NULL) {
1039 BREAK_TO_DEBUGGER();
1040 dm_error(
1041 "DC:failed to create sw i2c!!\n");
1042 goto res_create_fail;
1043 }
1044 }
1045
1046 dc->caps.max_planes = pool->base.pipe_count;
1047
1048 for (i = 0; i < dc->caps.max_planes; ++i)
1049 dc->caps.planes[i] = plane_cap;
1050
1051 dc->caps.disable_dp_clk_share = true;
1052
1053 if (!resource_construct(num_virtual_links, dc, &pool->base,
1054 &res_create_funcs))
1055 goto res_create_fail;
1056
1057 /* Create hardware sequencer */
1058 dce60_hw_sequencer_construct(dc);
1059
1060 return true;
1061
1062 res_create_fail:
1063 dce60_resource_destruct(pool);
1064 return false;
1065 }
1066
dce60_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1067 struct resource_pool *dce60_create_resource_pool(
1068 uint8_t num_virtual_links,
1069 struct dc *dc)
1070 {
1071 struct dce110_resource_pool *pool =
1072 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1073
1074 if (!pool)
1075 return NULL;
1076
1077 if (dce60_construct(num_virtual_links, dc, pool))
1078 return &pool->base;
1079
1080 kfree(pool);
1081 BREAK_TO_DEBUGGER();
1082 return NULL;
1083 }
1084
dce61_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1085 static bool dce61_construct(
1086 uint8_t num_virtual_links,
1087 struct dc *dc,
1088 struct dce110_resource_pool *pool)
1089 {
1090 unsigned int i;
1091 struct dc_context *ctx = dc->ctx;
1092 struct dc_bios *bp;
1093
1094 ctx->dc_bios->regs = &bios_regs;
1095
1096 pool->base.res_cap = &res_cap_61;
1097 pool->base.funcs = &dce60_res_pool_funcs;
1098
1099
1100 /*************************************************
1101 * Resource + asic cap harcoding *
1102 *************************************************/
1103 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1104 pool->base.pipe_count = res_cap_61.num_timing_generator;
1105 pool->base.timing_generator_count = res_cap_61.num_timing_generator;
1106 dc->caps.max_downscale_ratio = 200;
1107 dc->caps.i2c_speed_in_khz = 40;
1108 dc->caps.max_cursor_size = 64;
1109 dc->caps.is_apu = true;
1110
1111 /*************************************************
1112 * Create resources *
1113 *************************************************/
1114
1115 bp = ctx->dc_bios;
1116
1117 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1118 pool->base.dp_clock_source =
1119 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1120
1121 pool->base.clock_sources[0] =
1122 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1123 pool->base.clock_sources[1] =
1124 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1125 pool->base.clock_sources[2] =
1126 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1127 pool->base.clk_src_count = 3;
1128
1129 } else {
1130 pool->base.dp_clock_source =
1131 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1132
1133 pool->base.clock_sources[0] =
1134 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1135 pool->base.clock_sources[1] =
1136 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1137 pool->base.clk_src_count = 2;
1138 }
1139
1140 if (pool->base.dp_clock_source == NULL) {
1141 dm_error("DC: failed to create dp clock source!\n");
1142 BREAK_TO_DEBUGGER();
1143 goto res_create_fail;
1144 }
1145
1146 for (i = 0; i < pool->base.clk_src_count; i++) {
1147 if (pool->base.clock_sources[i] == NULL) {
1148 dm_error("DC: failed to create clock sources!\n");
1149 BREAK_TO_DEBUGGER();
1150 goto res_create_fail;
1151 }
1152 }
1153
1154 pool->base.dmcu = dce_dmcu_create(ctx,
1155 &dmcu_regs,
1156 &dmcu_shift,
1157 &dmcu_mask);
1158 if (pool->base.dmcu == NULL) {
1159 dm_error("DC: failed to create dmcu!\n");
1160 BREAK_TO_DEBUGGER();
1161 goto res_create_fail;
1162 }
1163
1164 pool->base.abm = dce_abm_create(ctx,
1165 &abm_regs,
1166 &abm_shift,
1167 &abm_mask);
1168 if (pool->base.abm == NULL) {
1169 dm_error("DC: failed to create abm!\n");
1170 BREAK_TO_DEBUGGER();
1171 goto res_create_fail;
1172 }
1173
1174 {
1175 struct irq_service_init_data init_data;
1176 init_data.ctx = dc->ctx;
1177 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1178 if (!pool->base.irqs)
1179 goto res_create_fail;
1180 }
1181
1182 for (i = 0; i < pool->base.pipe_count; i++) {
1183 pool->base.timing_generators[i] = dce60_timing_generator_create(
1184 ctx, i, &dce60_tg_offsets[i]);
1185 if (pool->base.timing_generators[i] == NULL) {
1186 BREAK_TO_DEBUGGER();
1187 dm_error("DC: failed to create tg!\n");
1188 goto res_create_fail;
1189 }
1190
1191 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1192 if (pool->base.mis[i] == NULL) {
1193 BREAK_TO_DEBUGGER();
1194 dm_error("DC: failed to create memory input!\n");
1195 goto res_create_fail;
1196 }
1197
1198 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1199 if (pool->base.ipps[i] == NULL) {
1200 BREAK_TO_DEBUGGER();
1201 dm_error("DC: failed to create input pixel processor!\n");
1202 goto res_create_fail;
1203 }
1204
1205 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1206 if (pool->base.transforms[i] == NULL) {
1207 BREAK_TO_DEBUGGER();
1208 dm_error("DC: failed to create transform!\n");
1209 goto res_create_fail;
1210 }
1211
1212 pool->base.opps[i] = dce60_opp_create(ctx, i);
1213 if (pool->base.opps[i] == NULL) {
1214 BREAK_TO_DEBUGGER();
1215 dm_error("DC: failed to create output pixel processor!\n");
1216 goto res_create_fail;
1217 }
1218 }
1219
1220 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1221 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1222 if (pool->base.engines[i] == NULL) {
1223 BREAK_TO_DEBUGGER();
1224 dm_error(
1225 "DC:failed to create aux engine!!\n");
1226 goto res_create_fail;
1227 }
1228 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1229 if (pool->base.hw_i2cs[i] == NULL) {
1230 BREAK_TO_DEBUGGER();
1231 dm_error(
1232 "DC:failed to create i2c engine!!\n");
1233 goto res_create_fail;
1234 }
1235 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1236 if (pool->base.sw_i2cs[i] == NULL) {
1237 BREAK_TO_DEBUGGER();
1238 dm_error(
1239 "DC:failed to create sw i2c!!\n");
1240 goto res_create_fail;
1241 }
1242 }
1243
1244 dc->caps.max_planes = pool->base.pipe_count;
1245
1246 for (i = 0; i < dc->caps.max_planes; ++i)
1247 dc->caps.planes[i] = plane_cap;
1248
1249 dc->caps.disable_dp_clk_share = true;
1250
1251 if (!resource_construct(num_virtual_links, dc, &pool->base,
1252 &res_create_funcs))
1253 goto res_create_fail;
1254
1255 /* Create hardware sequencer */
1256 dce60_hw_sequencer_construct(dc);
1257
1258 return true;
1259
1260 res_create_fail:
1261 dce60_resource_destruct(pool);
1262 return false;
1263 }
1264
dce61_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1265 struct resource_pool *dce61_create_resource_pool(
1266 uint8_t num_virtual_links,
1267 struct dc *dc)
1268 {
1269 struct dce110_resource_pool *pool =
1270 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1271
1272 if (!pool)
1273 return NULL;
1274
1275 if (dce61_construct(num_virtual_links, dc, pool))
1276 return &pool->base;
1277
1278 kfree(pool);
1279 BREAK_TO_DEBUGGER();
1280 return NULL;
1281 }
1282
dce64_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1283 static bool dce64_construct(
1284 uint8_t num_virtual_links,
1285 struct dc *dc,
1286 struct dce110_resource_pool *pool)
1287 {
1288 unsigned int i;
1289 struct dc_context *ctx = dc->ctx;
1290 struct dc_bios *bp;
1291
1292 ctx->dc_bios->regs = &bios_regs;
1293
1294 pool->base.res_cap = &res_cap_64;
1295 pool->base.funcs = &dce60_res_pool_funcs;
1296
1297
1298 /*************************************************
1299 * Resource + asic cap harcoding *
1300 *************************************************/
1301 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1302 pool->base.pipe_count = res_cap_64.num_timing_generator;
1303 pool->base.timing_generator_count = res_cap_64.num_timing_generator;
1304 dc->caps.max_downscale_ratio = 200;
1305 dc->caps.i2c_speed_in_khz = 40;
1306 dc->caps.max_cursor_size = 64;
1307 dc->caps.is_apu = true;
1308
1309 /*************************************************
1310 * Create resources *
1311 *************************************************/
1312
1313 bp = ctx->dc_bios;
1314
1315 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1316 pool->base.dp_clock_source =
1317 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1318
1319 /* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
1320 pool->base.clock_sources[0] =
1321 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1322 pool->base.clock_sources[1] =
1323 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1324 pool->base.clk_src_count = 2;
1325
1326 } else {
1327 pool->base.dp_clock_source =
1328 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1329
1330 pool->base.clock_sources[0] =
1331 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1332 pool->base.clock_sources[1] =
1333 dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1334 pool->base.clk_src_count = 2;
1335 }
1336
1337 if (pool->base.dp_clock_source == NULL) {
1338 dm_error("DC: failed to create dp clock source!\n");
1339 BREAK_TO_DEBUGGER();
1340 goto res_create_fail;
1341 }
1342
1343 for (i = 0; i < pool->base.clk_src_count; i++) {
1344 if (pool->base.clock_sources[i] == NULL) {
1345 dm_error("DC: failed to create clock sources!\n");
1346 BREAK_TO_DEBUGGER();
1347 goto res_create_fail;
1348 }
1349 }
1350
1351 pool->base.dmcu = dce_dmcu_create(ctx,
1352 &dmcu_regs,
1353 &dmcu_shift,
1354 &dmcu_mask);
1355 if (pool->base.dmcu == NULL) {
1356 dm_error("DC: failed to create dmcu!\n");
1357 BREAK_TO_DEBUGGER();
1358 goto res_create_fail;
1359 }
1360
1361 pool->base.abm = dce_abm_create(ctx,
1362 &abm_regs,
1363 &abm_shift,
1364 &abm_mask);
1365 if (pool->base.abm == NULL) {
1366 dm_error("DC: failed to create abm!\n");
1367 BREAK_TO_DEBUGGER();
1368 goto res_create_fail;
1369 }
1370
1371 {
1372 struct irq_service_init_data init_data;
1373 init_data.ctx = dc->ctx;
1374 pool->base.irqs = dal_irq_service_dce60_create(&init_data);
1375 if (!pool->base.irqs)
1376 goto res_create_fail;
1377 }
1378
1379 for (i = 0; i < pool->base.pipe_count; i++) {
1380 pool->base.timing_generators[i] = dce60_timing_generator_create(
1381 ctx, i, &dce60_tg_offsets[i]);
1382 if (pool->base.timing_generators[i] == NULL) {
1383 BREAK_TO_DEBUGGER();
1384 dm_error("DC: failed to create tg!\n");
1385 goto res_create_fail;
1386 }
1387
1388 pool->base.mis[i] = dce60_mem_input_create(ctx, i);
1389 if (pool->base.mis[i] == NULL) {
1390 BREAK_TO_DEBUGGER();
1391 dm_error("DC: failed to create memory input!\n");
1392 goto res_create_fail;
1393 }
1394
1395 pool->base.ipps[i] = dce60_ipp_create(ctx, i);
1396 if (pool->base.ipps[i] == NULL) {
1397 BREAK_TO_DEBUGGER();
1398 dm_error("DC: failed to create input pixel processor!\n");
1399 goto res_create_fail;
1400 }
1401
1402 pool->base.transforms[i] = dce60_transform_create(ctx, i);
1403 if (pool->base.transforms[i] == NULL) {
1404 BREAK_TO_DEBUGGER();
1405 dm_error("DC: failed to create transform!\n");
1406 goto res_create_fail;
1407 }
1408
1409 pool->base.opps[i] = dce60_opp_create(ctx, i);
1410 if (pool->base.opps[i] == NULL) {
1411 BREAK_TO_DEBUGGER();
1412 dm_error("DC: failed to create output pixel processor!\n");
1413 goto res_create_fail;
1414 }
1415 }
1416
1417 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1418 pool->base.engines[i] = dce60_aux_engine_create(ctx, i);
1419 if (pool->base.engines[i] == NULL) {
1420 BREAK_TO_DEBUGGER();
1421 dm_error(
1422 "DC:failed to create aux engine!!\n");
1423 goto res_create_fail;
1424 }
1425 pool->base.hw_i2cs[i] = dce60_i2c_hw_create(ctx, i);
1426 if (pool->base.hw_i2cs[i] == NULL) {
1427 BREAK_TO_DEBUGGER();
1428 dm_error(
1429 "DC:failed to create i2c engine!!\n");
1430 goto res_create_fail;
1431 }
1432 pool->base.sw_i2cs[i] = dce60_i2c_sw_create(ctx);
1433 if (pool->base.sw_i2cs[i] == NULL) {
1434 BREAK_TO_DEBUGGER();
1435 dm_error(
1436 "DC:failed to create sw i2c!!\n");
1437 goto res_create_fail;
1438 }
1439 }
1440
1441 dc->caps.max_planes = pool->base.pipe_count;
1442
1443 for (i = 0; i < dc->caps.max_planes; ++i)
1444 dc->caps.planes[i] = plane_cap;
1445
1446 dc->caps.disable_dp_clk_share = true;
1447
1448 if (!resource_construct(num_virtual_links, dc, &pool->base,
1449 &res_create_funcs))
1450 goto res_create_fail;
1451
1452 /* Create hardware sequencer */
1453 dce60_hw_sequencer_construct(dc);
1454
1455 return true;
1456
1457 res_create_fail:
1458 dce60_resource_destruct(pool);
1459 return false;
1460 }
1461
dce64_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1462 struct resource_pool *dce64_create_resource_pool(
1463 uint8_t num_virtual_links,
1464 struct dc *dc)
1465 {
1466 struct dce110_resource_pool *pool =
1467 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1468
1469 if (!pool)
1470 return NULL;
1471
1472 if (dce64_construct(num_virtual_links, dc, pool))
1473 return &pool->base;
1474
1475 kfree(pool);
1476 BREAK_TO_DEBUGGER();
1477 return NULL;
1478 }
1479