1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/slab.h> 28 #include <asm/div64.h> 29 #if IS_ENABLED(CONFIG_X86_64) 30 #include <asm/intel-family.h> 31 #endif 32 #include <drm/amdgpu_drm.h> 33 #include "ppatomctrl.h" 34 #include "atombios.h" 35 #include "pptable_v1_0.h" 36 #include "pppcielanes.h" 37 #include "amd_pcie_helpers.h" 38 #include "hardwaremanager.h" 39 #include "process_pptables_v1_0.h" 40 #include "cgs_common.h" 41 42 #include "smu7_common.h" 43 44 #include "hwmgr.h" 45 #include "smu7_hwmgr.h" 46 #include "smu_ucode_xfer_vi.h" 47 #include "smu7_powertune.h" 48 #include "smu7_dyn_defaults.h" 49 #include "smu7_thermal.h" 50 #include "smu7_clockpowergating.h" 51 #include "processpptables.h" 52 #include "pp_thermal.h" 53 #include "smu7_baco.h" 54 #include "smu7_smumgr.h" 55 #include "polaris10_smumgr.h" 56 57 #include "ivsrcid/ivsrcid_vislands30.h" 58 59 #define MC_CG_ARB_FREQ_F0 0x0a 60 #define MC_CG_ARB_FREQ_F1 0x0b 61 #define MC_CG_ARB_FREQ_F2 0x0c 62 #define MC_CG_ARB_FREQ_F3 0x0d 63 64 #define MC_CG_SEQ_DRAMCONF_S0 0x05 65 #define MC_CG_SEQ_DRAMCONF_S1 0x06 66 #define MC_CG_SEQ_YCLK_SUSPEND 0x04 67 #define MC_CG_SEQ_YCLK_RESUME 0x0a 68 69 #define SMC_CG_IND_START 0xc0030000 70 #define SMC_CG_IND_END 0xc0040000 71 72 #define MEM_FREQ_LOW_LATENCY 25000 73 #define MEM_FREQ_HIGH_LATENCY 80000 74 75 #define MEM_LATENCY_HIGH 45 76 #define MEM_LATENCY_LOW 35 77 #define MEM_LATENCY_ERR 0xFFFF 78 79 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 80 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 81 #define MC_SEQ_MISC0_GDDR5_VALUE 5 82 83 #define PCIE_BUS_CLK 10000 84 #define TCLK (PCIE_BUS_CLK / 10) 85 86 static struct profile_mode_setting smu7_profiling[7] = { 87 {0, 0, 0, 0, 0, 0, 0, 0}, 88 {1, 0, 100, 30, 1, 0, 100, 10}, 89 {1, 10, 0, 30, 0, 0, 0, 0}, 90 {0, 0, 0, 0, 1, 10, 16, 31}, 91 {1, 0, 11, 50, 1, 0, 100, 10}, 92 {1, 0, 5, 30, 0, 0, 0, 0}, 93 {0, 0, 0, 0, 0, 0, 0, 0}, 94 }; 95 96 #define PPSMC_MSG_SetVBITimeout_VEGAM ((uint16_t) 0x310) 97 98 #define ixPWR_SVI2_PLANE1_LOAD 0xC0200280 99 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK 0x00000020L 100 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK 0x00000040L 101 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT 0x00000005 102 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT 0x00000006 103 104 #define STRAP_EVV_REVISION_MSB 2211 105 #define STRAP_EVV_REVISION_LSB 2208 106 107 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ 108 enum DPM_EVENT_SRC { 109 DPM_EVENT_SRC_ANALOG = 0, 110 DPM_EVENT_SRC_EXTERNAL = 1, 111 DPM_EVENT_SRC_DIGITAL = 2, 112 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 113 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 114 }; 115 116 #define ixDIDT_SQ_EDC_CTRL 0x0013 117 #define ixDIDT_SQ_EDC_THRESHOLD 0x0014 118 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 119 #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 120 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 121 #define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 122 123 #define ixDIDT_TD_EDC_CTRL 0x0053 124 #define ixDIDT_TD_EDC_THRESHOLD 0x0054 125 #define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 126 #define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 127 #define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 128 #define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 129 130 #define ixDIDT_TCP_EDC_CTRL 0x0073 131 #define ixDIDT_TCP_EDC_THRESHOLD 0x0074 132 #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 133 #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 134 #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 135 #define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 136 137 #define ixDIDT_DB_EDC_CTRL 0x0033 138 #define ixDIDT_DB_EDC_THRESHOLD 0x0034 139 #define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 140 #define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 141 #define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 142 #define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 143 144 uint32_t DIDTEDCConfig_P12[] = { 145 ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 146 ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 147 ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 148 ixDIDT_SQ_EDC_STALL_PATTERN_7, 149 ixDIDT_SQ_EDC_THRESHOLD, 150 ixDIDT_SQ_EDC_CTRL, 151 ixDIDT_TD_EDC_STALL_PATTERN_1_2, 152 ixDIDT_TD_EDC_STALL_PATTERN_3_4, 153 ixDIDT_TD_EDC_STALL_PATTERN_5_6, 154 ixDIDT_TD_EDC_STALL_PATTERN_7, 155 ixDIDT_TD_EDC_THRESHOLD, 156 ixDIDT_TD_EDC_CTRL, 157 ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 158 ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 159 ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 160 ixDIDT_TCP_EDC_STALL_PATTERN_7, 161 ixDIDT_TCP_EDC_THRESHOLD, 162 ixDIDT_TCP_EDC_CTRL, 163 ixDIDT_DB_EDC_STALL_PATTERN_1_2, 164 ixDIDT_DB_EDC_STALL_PATTERN_3_4, 165 ixDIDT_DB_EDC_STALL_PATTERN_5_6, 166 ixDIDT_DB_EDC_STALL_PATTERN_7, 167 ixDIDT_DB_EDC_THRESHOLD, 168 ixDIDT_DB_EDC_CTRL, 169 0xFFFFFFFF // End of list 170 }; 171 172 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic); 173 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 174 enum pp_clock_type type, uint32_t mask); 175 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr); 176 177 static struct smu7_power_state *cast_phw_smu7_power_state( 178 struct pp_hw_power_state *hw_ps) 179 { 180 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), 181 "Invalid Powerstate Type!", 182 return NULL); 183 184 return (struct smu7_power_state *)hw_ps; 185 } 186 187 static const struct smu7_power_state *cast_const_phw_smu7_power_state( 188 const struct pp_hw_power_state *hw_ps) 189 { 190 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), 191 "Invalid Powerstate Type!", 192 return NULL); 193 194 return (const struct smu7_power_state *)hw_ps; 195 } 196 197 /** 198 * smu7_get_mc_microcode_version - Find the MC microcode version and store it in the HwMgr struct 199 * 200 * @hwmgr: the address of the powerplay hardware manager. 201 * Return: always 0 202 */ 203 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) 204 { 205 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); 206 207 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); 208 209 return 0; 210 } 211 212 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) 213 { 214 uint32_t speedCntl = 0; 215 216 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ 217 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, 218 ixPCIE_LC_SPEED_CNTL); 219 return((uint16_t)PHM_GET_FIELD(speedCntl, 220 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); 221 } 222 223 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) 224 { 225 uint32_t link_width; 226 227 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ 228 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 229 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); 230 231 PP_ASSERT_WITH_CODE((7 >= link_width), 232 "Invalid PCIe lane width!", return 0); 233 234 return decode_pcie_lane_width(link_width); 235 } 236 237 /** 238 * smu7_enable_smc_voltage_controller - Enable voltage control 239 * 240 * @hwmgr: the address of the powerplay hardware manager. 241 * Return: always PP_Result_OK 242 */ 243 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) 244 { 245 if (hwmgr->chip_id >= CHIP_POLARIS10 && 246 hwmgr->chip_id <= CHIP_VEGAM) { 247 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 248 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0); 249 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 250 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0); 251 } 252 253 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) 254 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL); 255 256 return 0; 257 } 258 259 /** 260 * smu7_voltage_control - Checks if we want to support voltage control 261 * 262 * @hwmgr: the address of the powerplay hardware manager. 263 */ 264 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr) 265 { 266 const struct smu7_hwmgr *data = 267 (const struct smu7_hwmgr *)(hwmgr->backend); 268 269 return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control); 270 } 271 272 /** 273 * smu7_enable_voltage_control - Enable voltage control 274 * 275 * @hwmgr: the address of the powerplay hardware manager. 276 * Return: always 0 277 */ 278 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr) 279 { 280 /* enable voltage control */ 281 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 282 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); 283 284 return 0; 285 } 286 287 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table, 288 struct phm_clock_voltage_dependency_table *voltage_dependency_table 289 ) 290 { 291 uint32_t i; 292 293 PP_ASSERT_WITH_CODE((NULL != voltage_table), 294 "Voltage Dependency Table empty.", return -EINVAL;); 295 296 voltage_table->mask_low = 0; 297 voltage_table->phase_delay = 0; 298 voltage_table->count = voltage_dependency_table->count; 299 300 for (i = 0; i < voltage_dependency_table->count; i++) { 301 voltage_table->entries[i].value = 302 voltage_dependency_table->entries[i].v; 303 voltage_table->entries[i].smio_low = 0; 304 } 305 306 return 0; 307 } 308 309 310 /** 311 * smu7_construct_voltage_tables - Create Voltage Tables. 312 * 313 * @hwmgr: the address of the powerplay hardware manager. 314 * Return: always 0 315 */ 316 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) 317 { 318 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 319 struct phm_ppt_v1_information *table_info = 320 (struct phm_ppt_v1_information *)hwmgr->pptable; 321 int result = 0; 322 uint32_t tmp; 323 324 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 325 result = atomctrl_get_voltage_table_v3(hwmgr, 326 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, 327 &(data->mvdd_voltage_table)); 328 PP_ASSERT_WITH_CODE((0 == result), 329 "Failed to retrieve MVDD table.", 330 return result); 331 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { 332 if (hwmgr->pp_table_version == PP_TABLE_V1) 333 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), 334 table_info->vdd_dep_on_mclk); 335 else if (hwmgr->pp_table_version == PP_TABLE_V0) 336 result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table), 337 hwmgr->dyn_state.mvdd_dependency_on_mclk); 338 339 PP_ASSERT_WITH_CODE((0 == result), 340 "Failed to retrieve SVI2 MVDD table from dependency table.", 341 return result;); 342 } 343 344 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 345 result = atomctrl_get_voltage_table_v3(hwmgr, 346 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, 347 &(data->vddci_voltage_table)); 348 PP_ASSERT_WITH_CODE((0 == result), 349 "Failed to retrieve VDDCI table.", 350 return result); 351 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { 352 if (hwmgr->pp_table_version == PP_TABLE_V1) 353 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), 354 table_info->vdd_dep_on_mclk); 355 else if (hwmgr->pp_table_version == PP_TABLE_V0) 356 result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table), 357 hwmgr->dyn_state.vddci_dependency_on_mclk); 358 PP_ASSERT_WITH_CODE((0 == result), 359 "Failed to retrieve SVI2 VDDCI table from dependency table.", 360 return result); 361 } 362 363 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { 364 /* VDDGFX has only SVI2 voltage control */ 365 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table), 366 table_info->vddgfx_lookup_table); 367 PP_ASSERT_WITH_CODE((0 == result), 368 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;); 369 } 370 371 372 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) { 373 result = atomctrl_get_voltage_table_v3(hwmgr, 374 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT, 375 &data->vddc_voltage_table); 376 PP_ASSERT_WITH_CODE((0 == result), 377 "Failed to retrieve VDDC table.", return result;); 378 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 379 380 if (hwmgr->pp_table_version == PP_TABLE_V0) 381 result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table, 382 hwmgr->dyn_state.vddc_dependency_on_mclk); 383 else if (hwmgr->pp_table_version == PP_TABLE_V1) 384 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), 385 table_info->vddc_lookup_table); 386 387 PP_ASSERT_WITH_CODE((0 == result), 388 "Failed to retrieve SVI2 VDDC table from dependency table.", return result;); 389 } 390 391 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC); 392 PP_ASSERT_WITH_CODE( 393 (data->vddc_voltage_table.count <= tmp), 394 "Too many voltage values for VDDC. Trimming to fit state table.", 395 phm_trim_voltage_table_to_fit_state_table(tmp, 396 &(data->vddc_voltage_table))); 397 398 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); 399 PP_ASSERT_WITH_CODE( 400 (data->vddgfx_voltage_table.count <= tmp), 401 "Too many voltage values for VDDC. Trimming to fit state table.", 402 phm_trim_voltage_table_to_fit_state_table(tmp, 403 &(data->vddgfx_voltage_table))); 404 405 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI); 406 PP_ASSERT_WITH_CODE( 407 (data->vddci_voltage_table.count <= tmp), 408 "Too many voltage values for VDDCI. Trimming to fit state table.", 409 phm_trim_voltage_table_to_fit_state_table(tmp, 410 &(data->vddci_voltage_table))); 411 412 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD); 413 PP_ASSERT_WITH_CODE( 414 (data->mvdd_voltage_table.count <= tmp), 415 "Too many voltage values for MVDD. Trimming to fit state table.", 416 phm_trim_voltage_table_to_fit_state_table(tmp, 417 &(data->mvdd_voltage_table))); 418 419 return 0; 420 } 421 422 /** 423 * smu7_program_static_screen_threshold_parameters - Programs static screed detection parameters 424 * 425 * @hwmgr: the address of the powerplay hardware manager. 426 * Return: always 0 427 */ 428 static int smu7_program_static_screen_threshold_parameters( 429 struct pp_hwmgr *hwmgr) 430 { 431 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 432 433 /* Set static screen threshold unit */ 434 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 435 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, 436 data->static_screen_threshold_unit); 437 /* Set static screen threshold */ 438 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 439 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, 440 data->static_screen_threshold); 441 442 return 0; 443 } 444 445 /** 446 * smu7_enable_display_gap - Setup display gap for glitch free memory clock switching. 447 * 448 * @hwmgr: the address of the powerplay hardware manager. 449 * Return: always 0 450 */ 451 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr) 452 { 453 uint32_t display_gap = 454 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 455 ixCG_DISPLAY_GAP_CNTL); 456 457 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, 458 DISP_GAP, DISPLAY_GAP_IGNORE); 459 460 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, 461 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); 462 463 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 464 ixCG_DISPLAY_GAP_CNTL, display_gap); 465 466 return 0; 467 } 468 469 /** 470 * smu7_program_voting_clients - Programs activity state transition voting clients 471 * 472 * @hwmgr: the address of the powerplay hardware manager. 473 * Return: always 0 474 */ 475 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) 476 { 477 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 478 int i; 479 480 /* Clear reset for voting clients before enabling DPM */ 481 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 482 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); 483 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 484 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); 485 486 for (i = 0; i < 8; i++) 487 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 488 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 489 data->voting_rights_clients[i]); 490 return 0; 491 } 492 493 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) 494 { 495 int i; 496 497 /* Reset voting clients before disabling DPM */ 498 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 499 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); 500 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 501 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); 502 503 for (i = 0; i < 8; i++) 504 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 505 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0); 506 507 return 0; 508 } 509 510 /* Copy one arb setting to another and then switch the active set. 511 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. 512 */ 513 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, 514 uint32_t arb_src, uint32_t arb_dest) 515 { 516 uint32_t mc_arb_dram_timing; 517 uint32_t mc_arb_dram_timing2; 518 uint32_t burst_time; 519 uint32_t mc_cg_config; 520 521 switch (arb_src) { 522 case MC_CG_ARB_FREQ_F0: 523 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); 524 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); 525 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); 526 break; 527 case MC_CG_ARB_FREQ_F1: 528 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); 529 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); 530 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 switch (arb_dest) { 537 case MC_CG_ARB_FREQ_F0: 538 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); 539 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 540 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); 541 break; 542 case MC_CG_ARB_FREQ_F1: 543 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 544 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 545 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); 546 break; 547 default: 548 return -EINVAL; 549 } 550 551 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); 552 mc_cg_config |= 0x0000000F; 553 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); 554 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); 555 556 return 0; 557 } 558 559 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) 560 { 561 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL); 562 } 563 564 /** 565 * smu7_initial_switch_from_arbf0_to_f1 - Initial switch from ARB F0->F1 566 * 567 * @hwmgr: the address of the powerplay hardware manager. 568 * Return: always 0 569 * This function is to be called from the SetPowerState table. 570 */ 571 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) 572 { 573 return smu7_copy_and_switch_arb_sets(hwmgr, 574 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 575 } 576 577 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) 578 { 579 uint32_t tmp; 580 581 tmp = (cgs_read_ind_register(hwmgr->device, 582 CGS_IND_REG__SMC, ixSMC_SCRATCH9) & 583 0x0000ff00) >> 8; 584 585 if (tmp == MC_CG_ARB_FREQ_F0) 586 return 0; 587 588 return smu7_copy_and_switch_arb_sets(hwmgr, 589 tmp, MC_CG_ARB_FREQ_F0); 590 } 591 592 static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr) 593 { 594 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 595 uint16_t pcie_gen = 0; 596 597 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 && 598 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4) 599 pcie_gen = 3; 600 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 && 601 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) 602 pcie_gen = 2; 603 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 && 604 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2) 605 pcie_gen = 1; 606 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 && 607 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1) 608 pcie_gen = 0; 609 610 return pcie_gen; 611 } 612 613 static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr) 614 { 615 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 616 uint16_t pcie_width = 0; 617 618 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 619 pcie_width = 16; 620 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 621 pcie_width = 12; 622 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 623 pcie_width = 8; 624 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 625 pcie_width = 4; 626 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 627 pcie_width = 2; 628 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 629 pcie_width = 1; 630 631 return pcie_width; 632 } 633 634 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 635 { 636 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 637 638 struct phm_ppt_v1_information *table_info = 639 (struct phm_ppt_v1_information *)(hwmgr->pptable); 640 struct phm_ppt_v1_pcie_table *pcie_table = NULL; 641 642 uint32_t i, max_entry; 643 uint32_t tmp; 644 645 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || 646 data->use_pcie_power_saving_levels), "No pcie performance levels!", 647 return -EINVAL); 648 649 if (table_info != NULL) 650 pcie_table = table_info->pcie_table; 651 652 if (data->use_pcie_performance_levels && 653 !data->use_pcie_power_saving_levels) { 654 data->pcie_gen_power_saving = data->pcie_gen_performance; 655 data->pcie_lane_power_saving = data->pcie_lane_performance; 656 } else if (!data->use_pcie_performance_levels && 657 data->use_pcie_power_saving_levels) { 658 data->pcie_gen_performance = data->pcie_gen_power_saving; 659 data->pcie_lane_performance = data->pcie_lane_power_saving; 660 } 661 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK); 662 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, 663 tmp, 664 MAX_REGULAR_DPM_NUMBER); 665 666 if (pcie_table != NULL) { 667 /* max_entry is used to make sure we reserve one PCIE level 668 * for boot level (fix for A+A PSPP issue). 669 * If PCIE table from PPTable have ULV entry + 8 entries, 670 * then ignore the last entry.*/ 671 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count; 672 for (i = 1; i < max_entry; i++) { 673 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, 674 get_pcie_gen_support(data->pcie_gen_cap, 675 pcie_table->entries[i].gen_speed), 676 get_pcie_lane_support(data->pcie_lane_cap, 677 pcie_table->entries[i].lane_width)); 678 } 679 data->dpm_table.pcie_speed_table.count = max_entry - 1; 680 smum_update_smc_table(hwmgr, SMU_BIF_TABLE); 681 } else { 682 /* Hardcode Pcie Table */ 683 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, 684 get_pcie_gen_support(data->pcie_gen_cap, 685 PP_Min_PCIEGen), 686 get_pcie_lane_support(data->pcie_lane_cap, 687 PP_Max_PCIELane)); 688 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, 689 get_pcie_gen_support(data->pcie_gen_cap, 690 PP_Min_PCIEGen), 691 get_pcie_lane_support(data->pcie_lane_cap, 692 PP_Max_PCIELane)); 693 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, 694 get_pcie_gen_support(data->pcie_gen_cap, 695 PP_Max_PCIEGen), 696 get_pcie_lane_support(data->pcie_lane_cap, 697 PP_Max_PCIELane)); 698 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, 699 get_pcie_gen_support(data->pcie_gen_cap, 700 PP_Max_PCIEGen), 701 get_pcie_lane_support(data->pcie_lane_cap, 702 PP_Max_PCIELane)); 703 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, 704 get_pcie_gen_support(data->pcie_gen_cap, 705 PP_Max_PCIEGen), 706 get_pcie_lane_support(data->pcie_lane_cap, 707 PP_Max_PCIELane)); 708 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, 709 get_pcie_gen_support(data->pcie_gen_cap, 710 PP_Max_PCIEGen), 711 get_pcie_lane_support(data->pcie_lane_cap, 712 PP_Max_PCIELane)); 713 714 data->dpm_table.pcie_speed_table.count = 6; 715 } 716 /* Populate last level for boot PCIE level, but do not increment count. */ 717 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 718 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) 719 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i, 720 get_pcie_gen_support(data->pcie_gen_cap, 721 PP_Max_PCIEGen), 722 data->vbios_boot_state.pcie_lane_bootup_value); 723 } else { 724 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 725 data->dpm_table.pcie_speed_table.count, 726 get_pcie_gen_support(data->pcie_gen_cap, 727 PP_Min_PCIEGen), 728 get_pcie_lane_support(data->pcie_lane_cap, 729 PP_Max_PCIELane)); 730 731 if (data->pcie_dpm_key_disabled) 732 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 733 data->dpm_table.pcie_speed_table.count, 734 smu7_override_pcie_speed(hwmgr), smu7_override_pcie_width(hwmgr)); 735 } 736 return 0; 737 } 738 739 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) 740 { 741 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 742 743 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); 744 745 phm_reset_single_dpm_table( 746 &data->dpm_table.sclk_table, 747 smum_get_mac_definition(hwmgr, 748 SMU_MAX_LEVELS_GRAPHICS), 749 MAX_REGULAR_DPM_NUMBER); 750 phm_reset_single_dpm_table( 751 &data->dpm_table.mclk_table, 752 smum_get_mac_definition(hwmgr, 753 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); 754 755 phm_reset_single_dpm_table( 756 &data->dpm_table.vddc_table, 757 smum_get_mac_definition(hwmgr, 758 SMU_MAX_LEVELS_VDDC), 759 MAX_REGULAR_DPM_NUMBER); 760 phm_reset_single_dpm_table( 761 &data->dpm_table.vddci_table, 762 smum_get_mac_definition(hwmgr, 763 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); 764 765 phm_reset_single_dpm_table( 766 &data->dpm_table.mvdd_table, 767 smum_get_mac_definition(hwmgr, 768 SMU_MAX_LEVELS_MVDD), 769 MAX_REGULAR_DPM_NUMBER); 770 return 0; 771 } 772 /* 773 * This function is to initialize all DPM state tables 774 * for SMU7 based on the dependency table. 775 * Dynamic state patching function will then trim these 776 * state tables to the allowed range based 777 * on the power policy or external client requests, 778 * such as UVD request, etc. 779 */ 780 781 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) 782 { 783 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 784 struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table = 785 hwmgr->dyn_state.vddc_dependency_on_sclk; 786 struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table = 787 hwmgr->dyn_state.vddc_dependency_on_mclk; 788 struct phm_cac_leakage_table *std_voltage_table = 789 hwmgr->dyn_state.cac_leakage_table; 790 uint32_t i, clk; 791 792 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, 793 "SCLK dependency table is missing. This table is mandatory", return -EINVAL); 794 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, 795 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); 796 797 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, 798 "MCLK dependency table is missing. This table is mandatory", return -EINVAL); 799 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, 800 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); 801 802 803 /* Initialize Sclk DPM table based on allow Sclk values*/ 804 data->dpm_table.sclk_table.count = 0; 805 806 for (i = 0; i < allowed_vdd_sclk_table->count; i++) { 807 clk = min(allowed_vdd_sclk_table->entries[i].clk, data->sclk_cap); 808 809 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != 810 clk) { 811 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 812 clk; 813 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; 814 data->dpm_table.sclk_table.count++; 815 } 816 } 817 818 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, 819 "MCLK dependency table is missing. This table is mandatory", return -EINVAL); 820 /* Initialize Mclk DPM table based on allow Mclk values */ 821 data->dpm_table.mclk_table.count = 0; 822 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 823 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != 824 allowed_vdd_mclk_table->entries[i].clk) { 825 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 826 allowed_vdd_mclk_table->entries[i].clk; 827 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; 828 data->dpm_table.mclk_table.count++; 829 } 830 } 831 832 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */ 833 for (i = 0; i < allowed_vdd_sclk_table->count; i++) { 834 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 835 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; 836 /* param1 is for corresponding std voltage */ 837 data->dpm_table.vddc_table.dpm_levels[i].enabled = true; 838 } 839 840 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count; 841 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; 842 843 if (NULL != allowed_vdd_mclk_table) { 844 /* Initialize Vddci DPM table based on allow Mclk values */ 845 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 846 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 847 data->dpm_table.vddci_table.dpm_levels[i].enabled = true; 848 } 849 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count; 850 } 851 852 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; 853 854 if (NULL != allowed_vdd_mclk_table) { 855 /* 856 * Initialize MVDD DPM table based on allow Mclk 857 * values 858 */ 859 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 860 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 861 data->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 862 } 863 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count; 864 } 865 866 return 0; 867 } 868 869 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr) 870 { 871 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 872 struct phm_ppt_v1_information *table_info = 873 (struct phm_ppt_v1_information *)(hwmgr->pptable); 874 uint32_t i; 875 876 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 877 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 878 879 if (table_info == NULL) 880 return -EINVAL; 881 882 dep_sclk_table = table_info->vdd_dep_on_sclk; 883 dep_mclk_table = table_info->vdd_dep_on_mclk; 884 885 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, 886 "SCLK dependency table is missing.", 887 return -EINVAL); 888 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, 889 "SCLK dependency table count is 0.", 890 return -EINVAL); 891 892 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, 893 "MCLK dependency table is missing.", 894 return -EINVAL); 895 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, 896 "MCLK dependency table count is 0", 897 return -EINVAL); 898 899 /* Initialize Sclk DPM table based on allow Sclk values */ 900 data->dpm_table.sclk_table.count = 0; 901 for (i = 0; i < dep_sclk_table->count; i++) { 902 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != 903 dep_sclk_table->entries[i].clk) { 904 905 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 906 dep_sclk_table->entries[i].clk; 907 908 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 909 i == 0; 910 data->dpm_table.sclk_table.count++; 911 } 912 } 913 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) 914 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; 915 /* Initialize Mclk DPM table based on allow Mclk values */ 916 data->dpm_table.mclk_table.count = 0; 917 for (i = 0; i < dep_mclk_table->count; i++) { 918 if (i == 0 || data->dpm_table.mclk_table.dpm_levels 919 [data->dpm_table.mclk_table.count - 1].value != 920 dep_mclk_table->entries[i].clk) { 921 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 922 dep_mclk_table->entries[i].clk; 923 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 924 i == 0; 925 data->dpm_table.mclk_table.count++; 926 } 927 } 928 929 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) 930 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk; 931 return 0; 932 } 933 934 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr) 935 { 936 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 937 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 938 struct phm_ppt_v1_information *table_info = 939 (struct phm_ppt_v1_information *)(hwmgr->pptable); 940 uint32_t i; 941 942 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 943 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 944 struct phm_odn_performance_level *entries; 945 946 if (table_info == NULL) 947 return -EINVAL; 948 949 dep_sclk_table = table_info->vdd_dep_on_sclk; 950 dep_mclk_table = table_info->vdd_dep_on_mclk; 951 952 odn_table->odn_core_clock_dpm_levels.num_of_pl = 953 data->golden_dpm_table.sclk_table.count; 954 entries = odn_table->odn_core_clock_dpm_levels.entries; 955 for (i = 0; i < data->golden_dpm_table.sclk_table.count; i++) { 956 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value; 957 entries[i].enabled = true; 958 entries[i].vddc = dep_sclk_table->entries[i].vddc; 959 } 960 961 smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table, 962 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk)); 963 964 odn_table->odn_memory_clock_dpm_levels.num_of_pl = 965 data->golden_dpm_table.mclk_table.count; 966 entries = odn_table->odn_memory_clock_dpm_levels.entries; 967 for (i = 0; i < data->golden_dpm_table.mclk_table.count; i++) { 968 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value; 969 entries[i].enabled = true; 970 entries[i].vddc = dep_mclk_table->entries[i].vddc; 971 } 972 973 smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table, 974 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk)); 975 976 return 0; 977 } 978 979 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr) 980 { 981 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 982 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 983 struct phm_ppt_v1_information *table_info = 984 (struct phm_ppt_v1_information *)(hwmgr->pptable); 985 uint32_t min_vddc = 0; 986 uint32_t max_vddc = 0; 987 988 if (!table_info) 989 return; 990 991 dep_sclk_table = table_info->vdd_dep_on_sclk; 992 993 atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc); 994 995 if (min_vddc == 0 || min_vddc > 2000 996 || min_vddc > dep_sclk_table->entries[0].vddc) 997 min_vddc = dep_sclk_table->entries[0].vddc; 998 999 if (max_vddc == 0 || max_vddc > 2000 1000 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc) 1001 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc; 1002 1003 data->odn_dpm_table.min_vddc = min_vddc; 1004 data->odn_dpm_table.max_vddc = max_vddc; 1005 } 1006 1007 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) 1008 { 1009 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1010 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 1011 struct phm_ppt_v1_information *table_info = 1012 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1013 uint32_t i; 1014 1015 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 1016 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; 1017 1018 if (table_info == NULL) 1019 return; 1020 1021 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { 1022 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock != 1023 data->dpm_table.sclk_table.dpm_levels[i].value) { 1024 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 1025 break; 1026 } 1027 } 1028 1029 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { 1030 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock != 1031 data->dpm_table.mclk_table.dpm_levels[i].value) { 1032 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 1033 break; 1034 } 1035 } 1036 1037 dep_table = table_info->vdd_dep_on_mclk; 1038 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk); 1039 1040 for (i = 0; i < dep_table->count; i++) { 1041 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 1042 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; 1043 return; 1044 } 1045 } 1046 1047 dep_table = table_info->vdd_dep_on_sclk; 1048 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); 1049 for (i = 0; i < dep_table->count; i++) { 1050 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 1051 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; 1052 return; 1053 } 1054 } 1055 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 1056 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; 1057 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; 1058 } 1059 } 1060 1061 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 1062 { 1063 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1064 1065 smu7_reset_dpm_tables(hwmgr); 1066 1067 if (hwmgr->pp_table_version == PP_TABLE_V1) 1068 smu7_setup_dpm_tables_v1(hwmgr); 1069 else if (hwmgr->pp_table_version == PP_TABLE_V0) 1070 smu7_setup_dpm_tables_v0(hwmgr); 1071 1072 smu7_setup_default_pcie_table(hwmgr); 1073 1074 /* save a copy of the default DPM table */ 1075 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 1076 sizeof(struct smu7_dpm_table)); 1077 1078 /* initialize ODN table */ 1079 if (hwmgr->od_enabled) { 1080 if (data->odn_dpm_table.max_vddc) { 1081 smu7_check_dpm_table_updated(hwmgr); 1082 } else { 1083 smu7_setup_voltage_range_from_vbios(hwmgr); 1084 smu7_odn_initial_default_setting(hwmgr); 1085 } 1086 } 1087 return 0; 1088 } 1089 1090 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) 1091 { 1092 1093 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1094 PHM_PlatformCaps_RegulatorHot)) 1095 return smum_send_msg_to_smc(hwmgr, 1096 PPSMC_MSG_EnableVRHotGPIOInterrupt, 1097 NULL); 1098 1099 return 0; 1100 } 1101 1102 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr) 1103 { 1104 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1105 SCLK_PWRMGT_OFF, 0); 1106 return 0; 1107 } 1108 1109 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) 1110 { 1111 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1112 1113 if (data->ulv_supported) 1114 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL); 1115 1116 return 0; 1117 } 1118 1119 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) 1120 { 1121 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1122 1123 if (data->ulv_supported) 1124 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL); 1125 1126 return 0; 1127 } 1128 1129 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 1130 { 1131 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1132 PHM_PlatformCaps_SclkDeepSleep)) { 1133 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL)) 1134 PP_ASSERT_WITH_CODE(false, 1135 "Attempt to enable Master Deep Sleep switch failed!", 1136 return -EINVAL); 1137 } else { 1138 if (smum_send_msg_to_smc(hwmgr, 1139 PPSMC_MSG_MASTER_DeepSleep_OFF, 1140 NULL)) { 1141 PP_ASSERT_WITH_CODE(false, 1142 "Attempt to disable Master Deep Sleep switch failed!", 1143 return -EINVAL); 1144 } 1145 } 1146 1147 return 0; 1148 } 1149 1150 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 1151 { 1152 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1153 PHM_PlatformCaps_SclkDeepSleep)) { 1154 if (smum_send_msg_to_smc(hwmgr, 1155 PPSMC_MSG_MASTER_DeepSleep_OFF, 1156 NULL)) { 1157 PP_ASSERT_WITH_CODE(false, 1158 "Attempt to disable Master Deep Sleep switch failed!", 1159 return -EINVAL); 1160 } 1161 } 1162 1163 return 0; 1164 } 1165 1166 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr) 1167 { 1168 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1169 uint32_t soft_register_value = 0; 1170 uint32_t handshake_disables_offset = data->soft_regs_start 1171 + smum_get_offsetof(hwmgr, 1172 SMU_SoftRegisters, HandshakeDisables); 1173 1174 soft_register_value = cgs_read_ind_register(hwmgr->device, 1175 CGS_IND_REG__SMC, handshake_disables_offset); 1176 soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE; 1177 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1178 handshake_disables_offset, soft_register_value); 1179 return 0; 1180 } 1181 1182 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) 1183 { 1184 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1185 uint32_t soft_register_value = 0; 1186 uint32_t handshake_disables_offset = data->soft_regs_start 1187 + smum_get_offsetof(hwmgr, 1188 SMU_SoftRegisters, HandshakeDisables); 1189 1190 soft_register_value = cgs_read_ind_register(hwmgr->device, 1191 CGS_IND_REG__SMC, handshake_disables_offset); 1192 soft_register_value |= smum_get_mac_definition(hwmgr, 1193 SMU_UVD_MCLK_HANDSHAKE_DISABLE); 1194 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1195 handshake_disables_offset, soft_register_value); 1196 return 0; 1197 } 1198 1199 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 1200 { 1201 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1202 1203 /* enable SCLK dpm */ 1204 if (!data->sclk_dpm_key_disabled) { 1205 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1206 hwmgr->chip_id <= CHIP_VEGAM) 1207 smu7_disable_sclk_vce_handshake(hwmgr); 1208 1209 PP_ASSERT_WITH_CODE( 1210 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)), 1211 "Failed to enable SCLK DPM during DPM Start Function!", 1212 return -EINVAL); 1213 } 1214 1215 /* enable MCLK dpm */ 1216 if (0 == data->mclk_dpm_key_disabled) { 1217 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) 1218 smu7_disable_handshake_uvd(hwmgr); 1219 1220 PP_ASSERT_WITH_CODE( 1221 (0 == smum_send_msg_to_smc(hwmgr, 1222 PPSMC_MSG_MCLKDPM_Enable, 1223 NULL)), 1224 "Failed to enable MCLK DPM during DPM Start Function!", 1225 return -EINVAL); 1226 1227 if ((hwmgr->chip_family == AMDGPU_FAMILY_CI) || 1228 (hwmgr->chip_id == CHIP_POLARIS10) || 1229 (hwmgr->chip_id == CHIP_POLARIS11) || 1230 (hwmgr->chip_id == CHIP_POLARIS12) || 1231 (hwmgr->chip_id == CHIP_TONGA) || 1232 (hwmgr->chip_id == CHIP_TOPAZ)) 1233 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); 1234 1235 1236 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 1237 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5); 1238 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5); 1239 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005); 1240 udelay(10); 1241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005); 1242 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005); 1243 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005); 1244 } else { 1245 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); 1246 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); 1247 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); 1248 udelay(10); 1249 if (hwmgr->chip_id == CHIP_VEGAM) { 1250 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009); 1251 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009); 1252 } else { 1253 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); 1254 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); 1255 } 1256 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); 1257 } 1258 } 1259 1260 return 0; 1261 } 1262 1263 static int smu7_start_dpm(struct pp_hwmgr *hwmgr) 1264 { 1265 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1266 1267 /*enable general power management */ 1268 1269 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1270 GLOBAL_PWRMGT_EN, 1); 1271 1272 /* enable sclk deep sleep */ 1273 1274 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1275 DYNAMIC_PM_EN, 1); 1276 1277 /* prepare for PCIE DPM */ 1278 1279 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1280 data->soft_regs_start + 1281 smum_get_offsetof(hwmgr, SMU_SoftRegisters, 1282 VoltageChangeTimeout), 0x1000); 1283 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 1284 SWRST_COMMAND_1, RESETLC, 0x0); 1285 1286 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) 1287 cgs_write_register(hwmgr->device, 0x1488, 1288 (cgs_read_register(hwmgr->device, 0x1488) & ~0x1)); 1289 1290 if (smu7_enable_sclk_mclk_dpm(hwmgr)) { 1291 pr_err("Failed to enable Sclk DPM and Mclk DPM!"); 1292 return -EINVAL; 1293 } 1294 1295 /* enable PCIE dpm */ 1296 if (0 == data->pcie_dpm_key_disabled) { 1297 PP_ASSERT_WITH_CODE( 1298 (0 == smum_send_msg_to_smc(hwmgr, 1299 PPSMC_MSG_PCIeDPM_Enable, 1300 NULL)), 1301 "Failed to enable pcie DPM during DPM Start Function!", 1302 return -EINVAL); 1303 } else { 1304 PP_ASSERT_WITH_CODE( 1305 (0 == smum_send_msg_to_smc(hwmgr, 1306 PPSMC_MSG_PCIeDPM_Disable, 1307 NULL)), 1308 "Failed to disable pcie DPM during DPM Start Function!", 1309 return -EINVAL); 1310 } 1311 1312 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1313 PHM_PlatformCaps_Falcon_QuickTransition)) { 1314 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr, 1315 PPSMC_MSG_EnableACDCGPIOInterrupt, 1316 NULL)), 1317 "Failed to enable AC DC GPIO Interrupt!", 1318 ); 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 1325 { 1326 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1327 1328 /* disable SCLK dpm */ 1329 if (!data->sclk_dpm_key_disabled) { 1330 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1331 "Trying to disable SCLK DPM when DPM is disabled", 1332 return 0); 1333 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL); 1334 } 1335 1336 /* disable MCLK dpm */ 1337 if (!data->mclk_dpm_key_disabled) { 1338 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1339 "Trying to disable MCLK DPM when DPM is disabled", 1340 return 0); 1341 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL); 1342 } 1343 1344 return 0; 1345 } 1346 1347 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) 1348 { 1349 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1350 1351 /* disable general power management */ 1352 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1353 GLOBAL_PWRMGT_EN, 0); 1354 /* disable sclk deep sleep */ 1355 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1356 DYNAMIC_PM_EN, 0); 1357 1358 /* disable PCIE dpm */ 1359 if (!data->pcie_dpm_key_disabled) { 1360 PP_ASSERT_WITH_CODE( 1361 (smum_send_msg_to_smc(hwmgr, 1362 PPSMC_MSG_PCIeDPM_Disable, 1363 NULL) == 0), 1364 "Failed to disable pcie DPM during DPM Stop Function!", 1365 return -EINVAL); 1366 } 1367 1368 smu7_disable_sclk_mclk_dpm(hwmgr); 1369 1370 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1371 "Trying to disable voltage DPM when DPM is disabled", 1372 return 0); 1373 1374 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL); 1375 1376 return 0; 1377 } 1378 1379 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) 1380 { 1381 bool protection; 1382 enum DPM_EVENT_SRC src; 1383 1384 switch (sources) { 1385 default: 1386 pr_err("Unknown throttling event sources."); 1387 fallthrough; 1388 case 0: 1389 protection = false; 1390 /* src is unused */ 1391 break; 1392 case (1 << PHM_AutoThrottleSource_Thermal): 1393 protection = true; 1394 src = DPM_EVENT_SRC_DIGITAL; 1395 break; 1396 case (1 << PHM_AutoThrottleSource_External): 1397 protection = true; 1398 src = DPM_EVENT_SRC_EXTERNAL; 1399 break; 1400 case (1 << PHM_AutoThrottleSource_External) | 1401 (1 << PHM_AutoThrottleSource_Thermal): 1402 protection = true; 1403 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; 1404 break; 1405 } 1406 /* Order matters - don't enable thermal protection for the wrong source. */ 1407 if (protection) { 1408 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, 1409 DPM_EVENT_SRC, src); 1410 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1411 THERMAL_PROTECTION_DIS, 1412 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1413 PHM_PlatformCaps_ThermalController)); 1414 } else 1415 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1416 THERMAL_PROTECTION_DIS, 1); 1417 } 1418 1419 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, 1420 PHM_AutoThrottleSource source) 1421 { 1422 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1423 1424 if (!(data->active_auto_throttle_sources & (1 << source))) { 1425 data->active_auto_throttle_sources |= 1 << source; 1426 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); 1427 } 1428 return 0; 1429 } 1430 1431 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) 1432 { 1433 return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); 1434 } 1435 1436 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr, 1437 PHM_AutoThrottleSource source) 1438 { 1439 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1440 1441 if (data->active_auto_throttle_sources & (1 << source)) { 1442 data->active_auto_throttle_sources &= ~(1 << source); 1443 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); 1444 } 1445 return 0; 1446 } 1447 1448 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) 1449 { 1450 return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); 1451 } 1452 1453 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) 1454 { 1455 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1456 data->pcie_performance_request = true; 1457 1458 return 0; 1459 } 1460 1461 static int smu7_program_edc_didt_registers(struct pp_hwmgr *hwmgr, 1462 uint32_t *cac_config_regs, 1463 AtomCtrl_EDCLeakgeTable *edc_leakage_table) 1464 { 1465 uint32_t data, i = 0; 1466 1467 while (cac_config_regs[i] != 0xFFFFFFFF) { 1468 data = edc_leakage_table->DIDT_REG[i]; 1469 cgs_write_ind_register(hwmgr->device, 1470 CGS_IND_REG__DIDT, 1471 cac_config_regs[i], 1472 data); 1473 i++; 1474 } 1475 1476 return 0; 1477 } 1478 1479 static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr) 1480 { 1481 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1482 int ret = 0; 1483 1484 if (!data->disable_edc_leakage_controller && 1485 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset && 1486 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) { 1487 ret = smu7_program_edc_didt_registers(hwmgr, 1488 DIDTEDCConfig_P12, 1489 &data->edc_leakage_table); 1490 if (ret) 1491 return ret; 1492 1493 ret = smum_send_msg_to_smc(hwmgr, 1494 (PPSMC_Msg)PPSMC_MSG_EnableEDCController, 1495 NULL); 1496 } else { 1497 ret = smum_send_msg_to_smc(hwmgr, 1498 (PPSMC_Msg)PPSMC_MSG_DisableEDCController, 1499 NULL); 1500 } 1501 1502 return ret; 1503 } 1504 1505 static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1506 { 1507 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1508 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; 1509 int32_t tmp_sclk, count, percentage; 1510 1511 if (golden_dpm_table->mclk_table.count == 1) { 1512 percentage = 70; 1513 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[0].value; 1514 } else { 1515 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / 1516 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 1517 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; 1518 } 1519 1520 tmp_sclk = hwmgr->pstate_mclk * percentage / 100; 1521 1522 if (hwmgr->pp_table_version == PP_TABLE_V0) { 1523 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk = 1524 hwmgr->dyn_state.vddc_dependency_on_sclk; 1525 1526 for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) { 1527 if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) { 1528 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk; 1529 break; 1530 } 1531 } 1532 if (count < 0) 1533 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk; 1534 1535 hwmgr->pstate_sclk_peak = 1536 vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk; 1537 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 1538 struct phm_ppt_v1_information *table_info = 1539 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1540 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk = 1541 table_info->vdd_dep_on_sclk; 1542 1543 for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) { 1544 if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) { 1545 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk; 1546 break; 1547 } 1548 } 1549 if (count < 0) 1550 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk; 1551 1552 hwmgr->pstate_sclk_peak = 1553 vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk; 1554 } 1555 1556 hwmgr->pstate_mclk_peak = 1557 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 1558 1559 /* make sure the output is in Mhz */ 1560 hwmgr->pstate_sclk /= 100; 1561 hwmgr->pstate_mclk /= 100; 1562 hwmgr->pstate_sclk_peak /= 100; 1563 hwmgr->pstate_mclk_peak /= 100; 1564 } 1565 1566 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1567 { 1568 int tmp_result = 0; 1569 int result = 0; 1570 1571 if (smu7_voltage_control(hwmgr)) { 1572 tmp_result = smu7_enable_voltage_control(hwmgr); 1573 PP_ASSERT_WITH_CODE(tmp_result == 0, 1574 "Failed to enable voltage control!", 1575 result = tmp_result); 1576 1577 tmp_result = smu7_construct_voltage_tables(hwmgr); 1578 PP_ASSERT_WITH_CODE((0 == tmp_result), 1579 "Failed to construct voltage tables!", 1580 result = tmp_result); 1581 } 1582 smum_initialize_mc_reg_table(hwmgr); 1583 1584 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1585 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) 1586 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1587 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); 1588 1589 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1590 PHM_PlatformCaps_ThermalController)) 1591 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1592 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); 1593 1594 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr); 1595 PP_ASSERT_WITH_CODE((0 == tmp_result), 1596 "Failed to program static screen threshold parameters!", 1597 result = tmp_result); 1598 1599 tmp_result = smu7_enable_display_gap(hwmgr); 1600 PP_ASSERT_WITH_CODE((0 == tmp_result), 1601 "Failed to enable display gap!", result = tmp_result); 1602 1603 tmp_result = smu7_program_voting_clients(hwmgr); 1604 PP_ASSERT_WITH_CODE((0 == tmp_result), 1605 "Failed to program voting clients!", result = tmp_result); 1606 1607 tmp_result = smum_process_firmware_header(hwmgr); 1608 PP_ASSERT_WITH_CODE((0 == tmp_result), 1609 "Failed to process firmware header!", result = tmp_result); 1610 1611 if (hwmgr->chip_id != CHIP_VEGAM) { 1612 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr); 1613 PP_ASSERT_WITH_CODE((0 == tmp_result), 1614 "Failed to initialize switch from ArbF0 to F1!", 1615 result = tmp_result); 1616 } 1617 1618 result = smu7_setup_default_dpm_tables(hwmgr); 1619 PP_ASSERT_WITH_CODE(0 == result, 1620 "Failed to setup default DPM tables!", return result); 1621 1622 tmp_result = smum_init_smc_table(hwmgr); 1623 PP_ASSERT_WITH_CODE((0 == tmp_result), 1624 "Failed to initialize SMC table!", result = tmp_result); 1625 1626 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr); 1627 PP_ASSERT_WITH_CODE((0 == tmp_result), 1628 "Failed to enable VR hot GPIO interrupt!", result = tmp_result); 1629 1630 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1631 hwmgr->chip_id <= CHIP_VEGAM) { 1632 tmp_result = smu7_notify_has_display(hwmgr); 1633 PP_ASSERT_WITH_CODE((0 == tmp_result), 1634 "Failed to enable display setting!", result = tmp_result); 1635 } else { 1636 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL); 1637 } 1638 1639 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1640 hwmgr->chip_id <= CHIP_VEGAM) { 1641 tmp_result = smu7_populate_edc_leakage_registers(hwmgr); 1642 PP_ASSERT_WITH_CODE((0 == tmp_result), 1643 "Failed to populate edc leakage registers!", result = tmp_result); 1644 } 1645 1646 tmp_result = smu7_enable_sclk_control(hwmgr); 1647 PP_ASSERT_WITH_CODE((0 == tmp_result), 1648 "Failed to enable SCLK control!", result = tmp_result); 1649 1650 tmp_result = smu7_enable_smc_voltage_controller(hwmgr); 1651 PP_ASSERT_WITH_CODE((0 == tmp_result), 1652 "Failed to enable voltage control!", result = tmp_result); 1653 1654 tmp_result = smu7_enable_ulv(hwmgr); 1655 PP_ASSERT_WITH_CODE((0 == tmp_result), 1656 "Failed to enable ULV!", result = tmp_result); 1657 1658 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr); 1659 PP_ASSERT_WITH_CODE((0 == tmp_result), 1660 "Failed to enable deep sleep master switch!", result = tmp_result); 1661 1662 tmp_result = smu7_enable_didt_config(hwmgr); 1663 PP_ASSERT_WITH_CODE((tmp_result == 0), 1664 "Failed to enable deep sleep master switch!", result = tmp_result); 1665 1666 tmp_result = smu7_start_dpm(hwmgr); 1667 PP_ASSERT_WITH_CODE((0 == tmp_result), 1668 "Failed to start DPM!", result = tmp_result); 1669 1670 tmp_result = smu7_enable_smc_cac(hwmgr); 1671 PP_ASSERT_WITH_CODE((0 == tmp_result), 1672 "Failed to enable SMC CAC!", result = tmp_result); 1673 1674 tmp_result = smu7_enable_power_containment(hwmgr); 1675 PP_ASSERT_WITH_CODE((0 == tmp_result), 1676 "Failed to enable power containment!", result = tmp_result); 1677 1678 tmp_result = smu7_power_control_set_level(hwmgr); 1679 PP_ASSERT_WITH_CODE((0 == tmp_result), 1680 "Failed to power control set level!", result = tmp_result); 1681 1682 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr); 1683 PP_ASSERT_WITH_CODE((0 == tmp_result), 1684 "Failed to enable thermal auto throttle!", result = tmp_result); 1685 1686 tmp_result = smu7_pcie_performance_request(hwmgr); 1687 PP_ASSERT_WITH_CODE((0 == tmp_result), 1688 "pcie performance request failed!", result = tmp_result); 1689 1690 smu7_populate_umdpstate_clocks(hwmgr); 1691 1692 return 0; 1693 } 1694 1695 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) 1696 { 1697 if (!hwmgr->avfs_supported) 1698 return 0; 1699 1700 if (enable) { 1701 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 1702 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { 1703 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 1704 hwmgr, PPSMC_MSG_EnableAvfs, NULL), 1705 "Failed to enable AVFS!", 1706 return -EINVAL); 1707 } 1708 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 1709 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { 1710 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 1711 hwmgr, PPSMC_MSG_DisableAvfs, NULL), 1712 "Failed to disable AVFS!", 1713 return -EINVAL); 1714 } 1715 1716 return 0; 1717 } 1718 1719 static int smu7_update_avfs(struct pp_hwmgr *hwmgr) 1720 { 1721 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1722 1723 if (!hwmgr->avfs_supported) 1724 return 0; 1725 1726 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 1727 smu7_avfs_control(hwmgr, false); 1728 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 1729 smu7_avfs_control(hwmgr, false); 1730 smu7_avfs_control(hwmgr, true); 1731 } else { 1732 smu7_avfs_control(hwmgr, true); 1733 } 1734 1735 return 0; 1736 } 1737 1738 static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 1739 { 1740 int tmp_result, result = 0; 1741 1742 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1743 PHM_PlatformCaps_ThermalController)) 1744 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1745 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1); 1746 1747 tmp_result = smu7_disable_power_containment(hwmgr); 1748 PP_ASSERT_WITH_CODE((tmp_result == 0), 1749 "Failed to disable power containment!", result = tmp_result); 1750 1751 tmp_result = smu7_disable_smc_cac(hwmgr); 1752 PP_ASSERT_WITH_CODE((tmp_result == 0), 1753 "Failed to disable SMC CAC!", result = tmp_result); 1754 1755 tmp_result = smu7_disable_didt_config(hwmgr); 1756 PP_ASSERT_WITH_CODE((tmp_result == 0), 1757 "Failed to disable DIDT!", result = tmp_result); 1758 1759 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1760 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0); 1761 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1762 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0); 1763 1764 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr); 1765 PP_ASSERT_WITH_CODE((tmp_result == 0), 1766 "Failed to disable thermal auto throttle!", result = tmp_result); 1767 1768 tmp_result = smu7_avfs_control(hwmgr, false); 1769 PP_ASSERT_WITH_CODE((tmp_result == 0), 1770 "Failed to disable AVFS!", result = tmp_result); 1771 1772 tmp_result = smu7_stop_dpm(hwmgr); 1773 PP_ASSERT_WITH_CODE((tmp_result == 0), 1774 "Failed to stop DPM!", result = tmp_result); 1775 1776 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr); 1777 PP_ASSERT_WITH_CODE((tmp_result == 0), 1778 "Failed to disable deep sleep master switch!", result = tmp_result); 1779 1780 tmp_result = smu7_disable_ulv(hwmgr); 1781 PP_ASSERT_WITH_CODE((tmp_result == 0), 1782 "Failed to disable ULV!", result = tmp_result); 1783 1784 tmp_result = smu7_clear_voting_clients(hwmgr); 1785 PP_ASSERT_WITH_CODE((tmp_result == 0), 1786 "Failed to clear voting clients!", result = tmp_result); 1787 1788 tmp_result = smu7_reset_to_default(hwmgr); 1789 PP_ASSERT_WITH_CODE((tmp_result == 0), 1790 "Failed to reset to default!", result = tmp_result); 1791 1792 tmp_result = smum_stop_smc(hwmgr); 1793 PP_ASSERT_WITH_CODE((tmp_result == 0), 1794 "Failed to stop smc!", result = tmp_result); 1795 1796 tmp_result = smu7_force_switch_to_arbf0(hwmgr); 1797 PP_ASSERT_WITH_CODE((tmp_result == 0), 1798 "Failed to force to switch arbf0!", result = tmp_result); 1799 1800 return result; 1801 } 1802 1803 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 1804 { 1805 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1806 struct phm_ppt_v1_information *table_info = 1807 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1808 struct amdgpu_device *adev = hwmgr->adev; 1809 uint8_t tmp1, tmp2; 1810 uint16_t tmp3 = 0; 1811 1812 data->dll_default_on = false; 1813 data->mclk_dpm0_activity_target = 0xa; 1814 data->vddc_vddgfx_delta = 300; 1815 data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT; 1816 data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT; 1817 data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0; 1818 data->voting_rights_clients[1] = SMU7_VOTINGRIGHTSCLIENTS_DFLT1; 1819 data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2; 1820 data->voting_rights_clients[3] = SMU7_VOTINGRIGHTSCLIENTS_DFLT3; 1821 data->voting_rights_clients[4] = SMU7_VOTINGRIGHTSCLIENTS_DFLT4; 1822 data->voting_rights_clients[5] = SMU7_VOTINGRIGHTSCLIENTS_DFLT5; 1823 data->voting_rights_clients[6] = SMU7_VOTINGRIGHTSCLIENTS_DFLT6; 1824 data->voting_rights_clients[7] = SMU7_VOTINGRIGHTSCLIENTS_DFLT7; 1825 1826 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 1827 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 1828 data->pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 1829 /* need to set voltage control types before EVV patching */ 1830 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE; 1831 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE; 1832 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE; 1833 data->enable_tdc_limit_feature = true; 1834 data->enable_pkg_pwr_tracking_feature = true; 1835 data->force_pcie_gen = PP_PCIEGenInvalid; 1836 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; 1837 data->current_profile_setting.bupdate_sclk = 1; 1838 data->current_profile_setting.sclk_up_hyst = 0; 1839 data->current_profile_setting.sclk_down_hyst = 100; 1840 data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT; 1841 data->current_profile_setting.bupdate_mclk = 1; 1842 if (hwmgr->chip_id >= CHIP_POLARIS10) { 1843 if (adev->gmc.vram_width == 256) { 1844 data->current_profile_setting.mclk_up_hyst = 10; 1845 data->current_profile_setting.mclk_down_hyst = 60; 1846 data->current_profile_setting.mclk_activity = 25; 1847 } else if (adev->gmc.vram_width == 128) { 1848 data->current_profile_setting.mclk_up_hyst = 5; 1849 data->current_profile_setting.mclk_down_hyst = 16; 1850 data->current_profile_setting.mclk_activity = 20; 1851 } else if (adev->gmc.vram_width == 64) { 1852 data->current_profile_setting.mclk_up_hyst = 3; 1853 data->current_profile_setting.mclk_down_hyst = 16; 1854 data->current_profile_setting.mclk_activity = 20; 1855 } 1856 } else { 1857 data->current_profile_setting.mclk_up_hyst = 0; 1858 data->current_profile_setting.mclk_down_hyst = 100; 1859 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT; 1860 } 1861 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1862 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1863 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1864 1865 if (hwmgr->chip_id == CHIP_HAWAII) { 1866 data->thermal_temp_setting.temperature_low = 94500; 1867 data->thermal_temp_setting.temperature_high = 95000; 1868 data->thermal_temp_setting.temperature_shutdown = 104000; 1869 } else { 1870 data->thermal_temp_setting.temperature_low = 99500; 1871 data->thermal_temp_setting.temperature_high = 100000; 1872 data->thermal_temp_setting.temperature_shutdown = 104000; 1873 } 1874 1875 data->fast_watermark_threshold = 100; 1876 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1877 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 1878 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1879 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1880 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 1881 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1882 1883 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1884 PHM_PlatformCaps_ControlVDDGFX)) { 1885 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1886 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { 1887 data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1888 } 1889 } 1890 1891 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1892 PHM_PlatformCaps_EnableMVDDControl)) { 1893 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1894 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 1895 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1896 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1897 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 1898 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1899 } 1900 1901 if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) 1902 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1903 PHM_PlatformCaps_ControlVDDGFX); 1904 1905 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1906 PHM_PlatformCaps_ControlVDDCI)) { 1907 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1908 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 1909 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1910 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1911 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 1912 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1913 } 1914 1915 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) 1916 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1917 PHM_PlatformCaps_EnableMVDDControl); 1918 1919 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) 1920 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1921 PHM_PlatformCaps_ControlVDDCI); 1922 1923 data->vddc_phase_shed_control = 1; 1924 if ((hwmgr->chip_id == CHIP_POLARIS12) || 1925 ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) || 1926 ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 1927 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) || 1928 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) { 1929 if (data->voltage_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 1930 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2, 1931 &tmp3); 1932 tmp3 = (tmp3 >> 5) & 0x3; 1933 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3; 1934 } 1935 } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 1936 data->vddc_phase_shed_control = 1; 1937 } 1938 1939 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) 1940 && (table_info->cac_dtp_table->usClockStretchAmount != 0)) 1941 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1942 PHM_PlatformCaps_ClockStretcher); 1943 1944 data->pcie_gen_performance.max = PP_PCIEGen1; 1945 data->pcie_gen_performance.min = PP_PCIEGen3; 1946 data->pcie_gen_power_saving.max = PP_PCIEGen1; 1947 data->pcie_gen_power_saving.min = PP_PCIEGen3; 1948 data->pcie_lane_performance.max = 0; 1949 data->pcie_lane_performance.min = 16; 1950 data->pcie_lane_power_saving.max = 0; 1951 data->pcie_lane_power_saving.min = 16; 1952 1953 1954 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 1955 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1956 PHM_PlatformCaps_UVDPowerGating); 1957 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 1958 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1959 PHM_PlatformCaps_VCEPowerGating); 1960 1961 data->disable_edc_leakage_controller = true; 1962 if (((adev->asic_type == CHIP_POLARIS10) && hwmgr->is_kicker) || 1963 ((adev->asic_type == CHIP_POLARIS11) && hwmgr->is_kicker) || 1964 (adev->asic_type == CHIP_POLARIS12) || 1965 (adev->asic_type == CHIP_VEGAM)) 1966 data->disable_edc_leakage_controller = false; 1967 1968 if (!atomctrl_is_asic_internal_ss_supported(hwmgr)) { 1969 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1970 PHM_PlatformCaps_MemorySpreadSpectrumSupport); 1971 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1972 PHM_PlatformCaps_EngineSpreadSpectrumSupport); 1973 } 1974 1975 if ((adev->pdev->device == 0x699F) && 1976 (adev->pdev->revision == 0xCF)) { 1977 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1978 PHM_PlatformCaps_PowerContainment); 1979 data->enable_tdc_limit_feature = false; 1980 data->enable_pkg_pwr_tracking_feature = false; 1981 data->disable_edc_leakage_controller = true; 1982 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1983 PHM_PlatformCaps_ClockStretcher); 1984 } 1985 } 1986 1987 static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr) 1988 { 1989 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1990 struct amdgpu_device *adev = hwmgr->adev; 1991 uint32_t asicrev1, evv_revision, max = 0, min = 0; 1992 1993 atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB, STRAP_EVV_REVISION_MSB, 1994 &evv_revision); 1995 1996 atomctrl_read_efuse(hwmgr, 568, 579, &asicrev1); 1997 1998 if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) || 1999 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) { 2000 min = 1200; 2001 max = 2500; 2002 } else if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 2003 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) { 2004 min = 900; 2005 max = 2100; 2006 } else if (hwmgr->chip_id == CHIP_POLARIS10) { 2007 if (adev->pdev->subsystem_vendor == 0x106B) { 2008 min = 1000; 2009 max = 2300; 2010 } else { 2011 if (evv_revision == 0) { 2012 min = 1000; 2013 max = 2300; 2014 } else if (evv_revision == 1) { 2015 if (asicrev1 == 326) { 2016 min = 1200; 2017 max = 2500; 2018 /* TODO: PATCH RO in VBIOS */ 2019 } else { 2020 min = 1200; 2021 max = 2000; 2022 } 2023 } else if (evv_revision == 2) { 2024 min = 1200; 2025 max = 2500; 2026 } 2027 } 2028 } else { 2029 min = 1100; 2030 max = 2100; 2031 } 2032 2033 data->ro_range_minimum = min; 2034 data->ro_range_maximum = max; 2035 2036 /* TODO: PATCH RO in VBIOS here */ 2037 2038 return 0; 2039 } 2040 2041 /** 2042 * smu7_get_evv_voltages - Get Leakage VDDC based on leakage ID. 2043 * 2044 * @hwmgr: the address of the powerplay hardware manager. 2045 * Return: always 0 2046 */ 2047 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) 2048 { 2049 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2050 uint16_t vv_id; 2051 uint16_t vddc = 0; 2052 uint16_t vddgfx = 0; 2053 uint16_t i, j; 2054 uint32_t sclk = 0; 2055 struct phm_ppt_v1_information *table_info = 2056 (struct phm_ppt_v1_information *)hwmgr->pptable; 2057 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; 2058 2059 if (hwmgr->chip_id == CHIP_POLARIS10 || 2060 hwmgr->chip_id == CHIP_POLARIS11 || 2061 hwmgr->chip_id == CHIP_POLARIS12) 2062 smu7_calculate_ro_range(hwmgr); 2063 2064 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 2065 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 2066 2067 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2068 if ((hwmgr->pp_table_version == PP_TABLE_V1) 2069 && !phm_get_sclk_for_voltage_evv(hwmgr, 2070 table_info->vddgfx_lookup_table, vv_id, &sclk)) { 2071 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2072 PHM_PlatformCaps_ClockStretcher)) { 2073 sclk_table = table_info->vdd_dep_on_sclk; 2074 2075 for (j = 1; j < sclk_table->count; j++) { 2076 if (sclk_table->entries[j].clk == sclk && 2077 sclk_table->entries[j].cks_enable == 0) { 2078 sclk += 5000; 2079 break; 2080 } 2081 } 2082 } 2083 if (0 == atomctrl_get_voltage_evv_on_sclk 2084 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, 2085 vv_id, &vddgfx)) { 2086 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ 2087 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL); 2088 2089 /* the voltage should not be zero nor equal to leakage ID */ 2090 if (vddgfx != 0 && vddgfx != vv_id) { 2091 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; 2092 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id; 2093 data->vddcgfx_leakage.count++; 2094 } 2095 } else { 2096 pr_info("Error retrieving EVV voltage value!\n"); 2097 } 2098 } 2099 } else { 2100 if ((hwmgr->pp_table_version == PP_TABLE_V0) 2101 || !phm_get_sclk_for_voltage_evv(hwmgr, 2102 table_info->vddc_lookup_table, vv_id, &sclk)) { 2103 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2104 PHM_PlatformCaps_ClockStretcher)) { 2105 if (table_info == NULL) 2106 return -EINVAL; 2107 sclk_table = table_info->vdd_dep_on_sclk; 2108 2109 for (j = 1; j < sclk_table->count; j++) { 2110 if (sclk_table->entries[j].clk == sclk && 2111 sclk_table->entries[j].cks_enable == 0) { 2112 sclk += 5000; 2113 break; 2114 } 2115 } 2116 } 2117 2118 if (phm_get_voltage_evv_on_sclk(hwmgr, 2119 VOLTAGE_TYPE_VDDC, 2120 sclk, vv_id, &vddc) == 0) { 2121 if (vddc >= 2000 || vddc == 0) 2122 return -EINVAL; 2123 } else { 2124 pr_debug("failed to retrieving EVV voltage!\n"); 2125 continue; 2126 } 2127 2128 /* the voltage should not be zero nor equal to leakage ID */ 2129 if (vddc != 0 && vddc != vv_id) { 2130 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc); 2131 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; 2132 data->vddc_leakage.count++; 2133 } 2134 } 2135 } 2136 } 2137 2138 return 0; 2139 } 2140 2141 /** 2142 * smu7_patch_ppt_v1_with_vdd_leakage - Change virtual leakage voltage to actual value. 2143 * 2144 * @hwmgr: the address of the powerplay hardware manager. 2145 * @voltage: pointer to changing voltage 2146 * @leakage_table: pointer to leakage table 2147 */ 2148 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr, 2149 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table) 2150 { 2151 uint32_t index; 2152 2153 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 2154 for (index = 0; index < leakage_table->count; index++) { 2155 /* if this voltage matches a leakage voltage ID */ 2156 /* patch with actual leakage voltage */ 2157 if (leakage_table->leakage_id[index] == *voltage) { 2158 *voltage = leakage_table->actual_voltage[index]; 2159 break; 2160 } 2161 } 2162 2163 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 2164 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 2165 } 2166 2167 /** 2168 * smu7_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. 2169 * 2170 * @hwmgr: the address of the powerplay hardware manager. 2171 * @lookup_table: pointer to voltage lookup table 2172 * @leakage_table: pointer to leakage table 2173 * Return: always 0 2174 */ 2175 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, 2176 phm_ppt_v1_voltage_lookup_table *lookup_table, 2177 struct smu7_leakage_voltage *leakage_table) 2178 { 2179 uint32_t i; 2180 2181 for (i = 0; i < lookup_table->count; i++) 2182 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, 2183 &lookup_table->entries[i].us_vdd, leakage_table); 2184 2185 return 0; 2186 } 2187 2188 static int smu7_patch_clock_voltage_limits_with_vddc_leakage( 2189 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table, 2190 uint16_t *vddc) 2191 { 2192 struct phm_ppt_v1_information *table_info = 2193 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2194 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); 2195 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = 2196 table_info->max_clock_voltage_on_dc.vddc; 2197 return 0; 2198 } 2199 2200 static int smu7_patch_voltage_dependency_tables_with_lookup_table( 2201 struct pp_hwmgr *hwmgr) 2202 { 2203 uint8_t entry_id; 2204 uint8_t voltage_id; 2205 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2206 struct phm_ppt_v1_information *table_info = 2207 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2208 2209 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 2210 table_info->vdd_dep_on_sclk; 2211 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = 2212 table_info->vdd_dep_on_mclk; 2213 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 2214 table_info->mm_dep_table; 2215 2216 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2217 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2218 voltage_id = sclk_table->entries[entry_id].vddInd; 2219 sclk_table->entries[entry_id].vddgfx = 2220 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd; 2221 } 2222 } else { 2223 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2224 voltage_id = sclk_table->entries[entry_id].vddInd; 2225 sclk_table->entries[entry_id].vddc = 2226 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2227 } 2228 } 2229 2230 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 2231 voltage_id = mclk_table->entries[entry_id].vddInd; 2232 mclk_table->entries[entry_id].vddc = 2233 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2234 } 2235 2236 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { 2237 voltage_id = mm_table->entries[entry_id].vddcInd; 2238 mm_table->entries[entry_id].vddc = 2239 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2240 } 2241 2242 return 0; 2243 2244 } 2245 2246 static int phm_add_voltage(struct pp_hwmgr *hwmgr, 2247 phm_ppt_v1_voltage_lookup_table *look_up_table, 2248 phm_ppt_v1_voltage_lookup_record *record) 2249 { 2250 uint32_t i; 2251 2252 PP_ASSERT_WITH_CODE((NULL != look_up_table), 2253 "Lookup Table empty.", return -EINVAL); 2254 PP_ASSERT_WITH_CODE((0 != look_up_table->count), 2255 "Lookup Table empty.", return -EINVAL); 2256 2257 i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); 2258 PP_ASSERT_WITH_CODE((i >= look_up_table->count), 2259 "Lookup Table is full.", return -EINVAL); 2260 2261 /* This is to avoid entering duplicate calculated records. */ 2262 for (i = 0; i < look_up_table->count; i++) { 2263 if (look_up_table->entries[i].us_vdd == record->us_vdd) { 2264 if (look_up_table->entries[i].us_calculated == 1) 2265 return 0; 2266 break; 2267 } 2268 } 2269 2270 look_up_table->entries[i].us_calculated = 1; 2271 look_up_table->entries[i].us_vdd = record->us_vdd; 2272 look_up_table->entries[i].us_cac_low = record->us_cac_low; 2273 look_up_table->entries[i].us_cac_mid = record->us_cac_mid; 2274 look_up_table->entries[i].us_cac_high = record->us_cac_high; 2275 /* Only increment the count when we're appending, not replacing duplicate entry. */ 2276 if (i == look_up_table->count) 2277 look_up_table->count++; 2278 2279 return 0; 2280 } 2281 2282 2283 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) 2284 { 2285 uint8_t entry_id; 2286 struct phm_ppt_v1_voltage_lookup_record v_record; 2287 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2288 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 2289 2290 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; 2291 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; 2292 2293 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2294 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2295 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15)) 2296 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + 2297 sclk_table->entries[entry_id].vdd_offset - 0xFFFF; 2298 else 2299 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + 2300 sclk_table->entries[entry_id].vdd_offset; 2301 2302 sclk_table->entries[entry_id].vddc = 2303 v_record.us_cac_low = v_record.us_cac_mid = 2304 v_record.us_cac_high = v_record.us_vdd; 2305 2306 phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); 2307 } 2308 2309 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 2310 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15)) 2311 v_record.us_vdd = mclk_table->entries[entry_id].vddc + 2312 mclk_table->entries[entry_id].vdd_offset - 0xFFFF; 2313 else 2314 v_record.us_vdd = mclk_table->entries[entry_id].vddc + 2315 mclk_table->entries[entry_id].vdd_offset; 2316 2317 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low = 2318 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; 2319 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); 2320 } 2321 } 2322 return 0; 2323 } 2324 2325 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) 2326 { 2327 uint8_t entry_id; 2328 struct phm_ppt_v1_voltage_lookup_record v_record; 2329 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2330 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 2331 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; 2332 2333 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2334 for (entry_id = 0; entry_id < mm_table->count; entry_id++) { 2335 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15)) 2336 v_record.us_vdd = mm_table->entries[entry_id].vddc + 2337 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF; 2338 else 2339 v_record.us_vdd = mm_table->entries[entry_id].vddc + 2340 mm_table->entries[entry_id].vddgfx_offset; 2341 2342 /* Add the calculated VDDGFX to the VDDGFX lookup table */ 2343 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low = 2344 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; 2345 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); 2346 } 2347 } 2348 return 0; 2349 } 2350 2351 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, 2352 struct phm_ppt_v1_voltage_lookup_table *lookup_table) 2353 { 2354 uint32_t table_size, i, j; 2355 table_size = lookup_table->count; 2356 2357 PP_ASSERT_WITH_CODE(0 != lookup_table->count, 2358 "Lookup table is empty", return -EINVAL); 2359 2360 /* Sorting voltages */ 2361 for (i = 0; i < table_size - 1; i++) { 2362 for (j = i + 1; j > 0; j--) { 2363 if (lookup_table->entries[j].us_vdd < 2364 lookup_table->entries[j - 1].us_vdd) { 2365 swap(lookup_table->entries[j - 1], 2366 lookup_table->entries[j]); 2367 } 2368 } 2369 } 2370 2371 return 0; 2372 } 2373 2374 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr) 2375 { 2376 int result = 0; 2377 int tmp_result; 2378 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2379 struct phm_ppt_v1_information *table_info = 2380 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2381 2382 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2383 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, 2384 table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage)); 2385 if (tmp_result != 0) 2386 result = tmp_result; 2387 2388 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, 2389 &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage)); 2390 } else { 2391 2392 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, 2393 table_info->vddc_lookup_table, &(data->vddc_leakage)); 2394 if (tmp_result) 2395 result = tmp_result; 2396 2397 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, 2398 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); 2399 if (tmp_result) 2400 result = tmp_result; 2401 } 2402 2403 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr); 2404 if (tmp_result) 2405 result = tmp_result; 2406 2407 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr); 2408 if (tmp_result) 2409 result = tmp_result; 2410 2411 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr); 2412 if (tmp_result) 2413 result = tmp_result; 2414 2415 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table); 2416 if (tmp_result) 2417 result = tmp_result; 2418 2419 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); 2420 if (tmp_result) 2421 result = tmp_result; 2422 2423 return result; 2424 } 2425 2426 static int smu7_find_highest_vddc(struct pp_hwmgr *hwmgr) 2427 { 2428 struct phm_ppt_v1_information *table_info = 2429 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2430 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 2431 table_info->vdd_dep_on_sclk; 2432 struct phm_ppt_v1_voltage_lookup_table *lookup_table = 2433 table_info->vddc_lookup_table; 2434 uint16_t highest_voltage; 2435 uint32_t i; 2436 2437 highest_voltage = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 2438 2439 for (i = 0; i < lookup_table->count; i++) { 2440 if (lookup_table->entries[i].us_vdd < ATOM_VIRTUAL_VOLTAGE_ID0 && 2441 lookup_table->entries[i].us_vdd > highest_voltage) 2442 highest_voltage = lookup_table->entries[i].us_vdd; 2443 } 2444 2445 return highest_voltage; 2446 } 2447 2448 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr) 2449 { 2450 struct phm_ppt_v1_information *table_info = 2451 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2452 2453 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 2454 table_info->vdd_dep_on_sclk; 2455 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = 2456 table_info->vdd_dep_on_mclk; 2457 2458 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, 2459 "VDD dependency on SCLK table is missing.", 2460 return -EINVAL); 2461 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, 2462 "VDD dependency on SCLK table has to have is missing.", 2463 return -EINVAL); 2464 2465 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, 2466 "VDD dependency on MCLK table is missing", 2467 return -EINVAL); 2468 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 2469 "VDD dependency on MCLK table has to have is missing.", 2470 return -EINVAL); 2471 2472 table_info->max_clock_voltage_on_ac.sclk = 2473 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; 2474 table_info->max_clock_voltage_on_ac.mclk = 2475 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 2476 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) 2477 table_info->max_clock_voltage_on_ac.vddc = 2478 smu7_find_highest_vddc(hwmgr); 2479 else 2480 table_info->max_clock_voltage_on_ac.vddc = 2481 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 2482 table_info->max_clock_voltage_on_ac.vddci = 2483 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; 2484 2485 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; 2486 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; 2487 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc; 2488 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci; 2489 2490 return 0; 2491 } 2492 2493 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) 2494 { 2495 struct phm_ppt_v1_information *table_info = 2496 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2497 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 2498 struct phm_ppt_v1_voltage_lookup_table *lookup_table; 2499 uint32_t i; 2500 uint32_t hw_revision, sub_vendor_id, sub_sys_id; 2501 struct amdgpu_device *adev = hwmgr->adev; 2502 2503 if (table_info != NULL) { 2504 dep_mclk_table = table_info->vdd_dep_on_mclk; 2505 lookup_table = table_info->vddc_lookup_table; 2506 } else 2507 return 0; 2508 2509 hw_revision = adev->pdev->revision; 2510 sub_sys_id = adev->pdev->subsystem_device; 2511 sub_vendor_id = adev->pdev->subsystem_vendor; 2512 2513 if (adev->pdev->device == 0x67DF && hw_revision == 0xC7 && 2514 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) || 2515 (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) || 2516 (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) { 2517 2518 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 2519 CGS_IND_REG__SMC, 2520 PWR_CKS_CNTL, 2521 CKS_STRETCH_AMOUNT, 2522 0x3); 2523 2524 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000) 2525 return 0; 2526 2527 for (i = 0; i < lookup_table->count; i++) { 2528 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) { 2529 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i; 2530 return 0; 2531 } 2532 } 2533 } 2534 return 0; 2535 } 2536 2537 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) 2538 { 2539 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; 2540 uint32_t temp_reg; 2541 struct phm_ppt_v1_information *table_info = 2542 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2543 2544 2545 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { 2546 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); 2547 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { 2548 case 0: 2549 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); 2550 break; 2551 case 1: 2552 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); 2553 break; 2554 case 2: 2555 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); 2556 break; 2557 case 3: 2558 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); 2559 break; 2560 case 4: 2561 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); 2562 break; 2563 default: 2564 break; 2565 } 2566 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); 2567 } 2568 2569 if (table_info == NULL) 2570 return 0; 2571 2572 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 && 2573 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) { 2574 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit = 2575 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; 2576 2577 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit = 2578 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; 2579 2580 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1; 2581 2582 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100; 2583 2584 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit = 2585 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; 2586 2587 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1; 2588 2589 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ? 2590 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0; 2591 2592 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp; 2593 table_info->cac_dtp_table->usOperatingTempStep = 1; 2594 table_info->cac_dtp_table->usOperatingTempHyst = 1; 2595 2596 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = 2597 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; 2598 2599 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = 2600 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM; 2601 2602 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit = 2603 table_info->cac_dtp_table->usOperatingTempMinLimit; 2604 2605 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit = 2606 table_info->cac_dtp_table->usOperatingTempMaxLimit; 2607 2608 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = 2609 table_info->cac_dtp_table->usDefaultTargetOperatingTemp; 2610 2611 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep = 2612 table_info->cac_dtp_table->usOperatingTempStep; 2613 2614 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = 2615 table_info->cac_dtp_table->usTargetOperatingTemp; 2616 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK) 2617 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2618 PHM_PlatformCaps_ODFuzzyFanControlSupport); 2619 } 2620 2621 return 0; 2622 } 2623 2624 /** 2625 * smu7_patch_ppt_v0_with_vdd_leakage - Change virtual leakage voltage to actual value. 2626 * 2627 * @hwmgr: the address of the powerplay hardware manager. 2628 * @voltage: pointer to changing voltage 2629 * @leakage_table: pointer to leakage table 2630 */ 2631 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr, 2632 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table) 2633 { 2634 uint32_t index; 2635 2636 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 2637 for (index = 0; index < leakage_table->count; index++) { 2638 /* if this voltage matches a leakage voltage ID */ 2639 /* patch with actual leakage voltage */ 2640 if (leakage_table->leakage_id[index] == *voltage) { 2641 *voltage = leakage_table->actual_voltage[index]; 2642 break; 2643 } 2644 } 2645 2646 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 2647 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 2648 } 2649 2650 2651 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr, 2652 struct phm_clock_voltage_dependency_table *tab) 2653 { 2654 uint16_t i; 2655 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2656 2657 if (tab) 2658 for (i = 0; i < tab->count; i++) 2659 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2660 &data->vddc_leakage); 2661 2662 return 0; 2663 } 2664 2665 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr, 2666 struct phm_clock_voltage_dependency_table *tab) 2667 { 2668 uint16_t i; 2669 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2670 2671 if (tab) 2672 for (i = 0; i < tab->count; i++) 2673 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2674 &data->vddci_leakage); 2675 2676 return 0; 2677 } 2678 2679 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr, 2680 struct phm_vce_clock_voltage_dependency_table *tab) 2681 { 2682 uint16_t i; 2683 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2684 2685 if (tab) 2686 for (i = 0; i < tab->count; i++) 2687 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2688 &data->vddc_leakage); 2689 2690 return 0; 2691 } 2692 2693 2694 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr, 2695 struct phm_uvd_clock_voltage_dependency_table *tab) 2696 { 2697 uint16_t i; 2698 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2699 2700 if (tab) 2701 for (i = 0; i < tab->count; i++) 2702 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2703 &data->vddc_leakage); 2704 2705 return 0; 2706 } 2707 2708 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr, 2709 struct phm_phase_shedding_limits_table *tab) 2710 { 2711 uint16_t i; 2712 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2713 2714 if (tab) 2715 for (i = 0; i < tab->count; i++) 2716 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage, 2717 &data->vddc_leakage); 2718 2719 return 0; 2720 } 2721 2722 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr, 2723 struct phm_samu_clock_voltage_dependency_table *tab) 2724 { 2725 uint16_t i; 2726 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2727 2728 if (tab) 2729 for (i = 0; i < tab->count; i++) 2730 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2731 &data->vddc_leakage); 2732 2733 return 0; 2734 } 2735 2736 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr, 2737 struct phm_acp_clock_voltage_dependency_table *tab) 2738 { 2739 uint16_t i; 2740 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2741 2742 if (tab) 2743 for (i = 0; i < tab->count; i++) 2744 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2745 &data->vddc_leakage); 2746 2747 return 0; 2748 } 2749 2750 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, 2751 struct phm_clock_and_voltage_limits *tab) 2752 { 2753 uint32_t vddc, vddci; 2754 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2755 2756 if (tab) { 2757 vddc = tab->vddc; 2758 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, 2759 &data->vddc_leakage); 2760 tab->vddc = vddc; 2761 vddci = tab->vddci; 2762 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, 2763 &data->vddci_leakage); 2764 tab->vddci = vddci; 2765 } 2766 2767 return 0; 2768 } 2769 2770 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab) 2771 { 2772 uint32_t i; 2773 uint32_t vddc; 2774 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2775 2776 if (tab) { 2777 for (i = 0; i < tab->count; i++) { 2778 vddc = (uint32_t)(tab->entries[i].Vddc); 2779 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage); 2780 tab->entries[i].Vddc = (uint16_t)vddc; 2781 } 2782 } 2783 2784 return 0; 2785 } 2786 2787 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr) 2788 { 2789 int tmp; 2790 2791 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); 2792 if (tmp) 2793 return -EINVAL; 2794 2795 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); 2796 if (tmp) 2797 return -EINVAL; 2798 2799 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); 2800 if (tmp) 2801 return -EINVAL; 2802 2803 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_display_clock); 2804 if (tmp) 2805 return -EINVAL; 2806 2807 tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table); 2808 if (tmp) 2809 return -EINVAL; 2810 2811 tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table); 2812 if (tmp) 2813 return -EINVAL; 2814 2815 tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table); 2816 if (tmp) 2817 return -EINVAL; 2818 2819 tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table); 2820 if (tmp) 2821 return -EINVAL; 2822 2823 tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table); 2824 if (tmp) 2825 return -EINVAL; 2826 2827 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac); 2828 if (tmp) 2829 return -EINVAL; 2830 2831 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); 2832 if (tmp) 2833 return -EINVAL; 2834 2835 tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table); 2836 if (tmp) 2837 return -EINVAL; 2838 2839 return 0; 2840 } 2841 2842 2843 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) 2844 { 2845 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2846 2847 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 2848 struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 2849 struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk; 2850 2851 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, 2852 "VDDC dependency on SCLK table is missing. This table is mandatory", 2853 return -EINVAL); 2854 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, 2855 "VDDC dependency on SCLK table has to have is missing. This table is mandatory", 2856 return -EINVAL); 2857 2858 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL, 2859 "VDDC dependency on MCLK table is missing. This table is mandatory", 2860 return -EINVAL); 2861 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1, 2862 "VDD dependency on MCLK table has to have is missing. This table is mandatory", 2863 return -EINVAL); 2864 2865 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v; 2866 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 2867 2868 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = 2869 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 2870 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = 2871 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk; 2872 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = 2873 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 2874 2875 if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) { 2876 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v; 2877 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 2878 } 2879 2880 if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1) 2881 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v; 2882 2883 return 0; 2884 } 2885 2886 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 2887 { 2888 kfree(hwmgr->dyn_state.vddc_dependency_on_display_clock); 2889 hwmgr->dyn_state.vddc_dependency_on_display_clock = NULL; 2890 kfree(hwmgr->backend); 2891 hwmgr->backend = NULL; 2892 2893 return 0; 2894 } 2895 2896 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr) 2897 { 2898 uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id; 2899 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2900 int i; 2901 2902 if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) { 2903 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 2904 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 2905 if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci, 2906 virtual_voltage_id, 2907 efuse_voltage_id) == 0) { 2908 if (vddc != 0 && vddc != virtual_voltage_id) { 2909 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; 2910 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; 2911 data->vddc_leakage.count++; 2912 } 2913 if (vddci != 0 && vddci != virtual_voltage_id) { 2914 data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci; 2915 data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id; 2916 data->vddci_leakage.count++; 2917 } 2918 } 2919 } 2920 } 2921 return 0; 2922 } 2923 2924 #define LEAKAGE_ID_MSB 463 2925 #define LEAKAGE_ID_LSB 454 2926 2927 static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr) 2928 { 2929 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2930 uint32_t efuse; 2931 uint16_t offset; 2932 int ret = 0; 2933 2934 if (data->disable_edc_leakage_controller) 2935 return 0; 2936 2937 ret = atomctrl_get_edc_hilo_leakage_offset_table(hwmgr, 2938 &data->edc_hilo_leakage_offset_from_vbios); 2939 if (ret) 2940 return ret; 2941 2942 if (data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset && 2943 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) { 2944 atomctrl_read_efuse(hwmgr, LEAKAGE_ID_LSB, LEAKAGE_ID_MSB, &efuse); 2945 if (efuse < data->edc_hilo_leakage_offset_from_vbios.usHiLoLeakageThreshold) 2946 offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset; 2947 else 2948 offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset; 2949 2950 ret = atomctrl_get_edc_leakage_table(hwmgr, 2951 &data->edc_leakage_table, 2952 offset); 2953 if (ret) 2954 return ret; 2955 } 2956 2957 return ret; 2958 } 2959 2960 static int smu7_init_voltage_dependency_on_display_clock_table(struct pp_hwmgr *hwmgr) 2961 { 2962 struct phm_clock_voltage_dependency_table *table; 2963 2964 if (!amdgpu_device_ip_get_ip_block(hwmgr->adev, AMD_IP_BLOCK_TYPE_DCE)) 2965 return 0; 2966 2967 table = kzalloc(struct_size(table, entries, 4), GFP_KERNEL); 2968 if (!table) 2969 return -ENOMEM; 2970 2971 if (hwmgr->chip_id >= CHIP_POLARIS10) { 2972 table->entries[0].clk = 38918; 2973 table->entries[1].clk = 45900; 2974 table->entries[2].clk = 66700; 2975 table->entries[3].clk = 113200; 2976 2977 table->entries[0].v = 700; 2978 table->entries[1].v = 740; 2979 table->entries[2].v = 800; 2980 table->entries[3].v = 900; 2981 } else { 2982 if (hwmgr->chip_family == AMDGPU_FAMILY_CZ) { 2983 table->entries[0].clk = 35200; 2984 table->entries[1].clk = 35200; 2985 table->entries[2].clk = 46700; 2986 table->entries[3].clk = 64300; 2987 } else { 2988 table->entries[0].clk = 0; 2989 table->entries[1].clk = 35200; 2990 table->entries[2].clk = 54000; 2991 table->entries[3].clk = 62500; 2992 } 2993 2994 table->entries[0].v = 0; 2995 table->entries[1].v = 720; 2996 table->entries[2].v = 810; 2997 table->entries[3].v = 900; 2998 } 2999 3000 table->count = 4; 3001 hwmgr->dyn_state.vddc_dependency_on_display_clock = table; 3002 return 0; 3003 } 3004 3005 static void smu7_set_sclk_cap(struct pp_hwmgr *hwmgr) 3006 { 3007 struct amdgpu_device *adev = hwmgr->adev; 3008 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3009 3010 data->sclk_cap = 0xffffffff; 3011 3012 if (hwmgr->od_enabled) 3013 return; 3014 3015 /* R9 390X board: last sclk dpm level is unstable, use lower sclk */ 3016 if (adev->pdev->device == 0x67B0 && 3017 adev->pdev->subsystem_vendor == 0x1043) 3018 data->sclk_cap = 104000; /* 1040 MHz */ 3019 3020 if (data->sclk_cap != 0xffffffff) 3021 dev_info(adev->dev, "sclk cap: %u kHz on quirky ASIC\n", data->sclk_cap * 10); 3022 } 3023 3024 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 3025 { 3026 struct amdgpu_device *adev = hwmgr->adev; 3027 struct smu7_hwmgr *data; 3028 int result = 0; 3029 3030 data = kzalloc_obj(struct smu7_hwmgr); 3031 if (data == NULL) 3032 return -ENOMEM; 3033 3034 hwmgr->backend = data; 3035 smu7_set_sclk_cap(hwmgr); 3036 smu7_patch_voltage_workaround(hwmgr); 3037 smu7_init_dpm_defaults(hwmgr); 3038 3039 /* Get leakage voltage based on leakage ID. */ 3040 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3041 PHM_PlatformCaps_EVV)) { 3042 result = smu7_get_evv_voltages(hwmgr); 3043 if (result) { 3044 pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); 3045 kfree(hwmgr->backend); 3046 hwmgr->backend = NULL; 3047 return -EINVAL; 3048 } 3049 } else { 3050 smu7_get_elb_voltages(hwmgr); 3051 } 3052 3053 result = smu7_init_voltage_dependency_on_display_clock_table(hwmgr); 3054 if (result) 3055 goto fail; 3056 3057 if (hwmgr->pp_table_version == PP_TABLE_V1) { 3058 smu7_complete_dependency_tables(hwmgr); 3059 smu7_set_private_data_based_on_pptable_v1(hwmgr); 3060 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 3061 smu7_patch_dependency_tables_with_leakage(hwmgr); 3062 smu7_set_private_data_based_on_pptable_v0(hwmgr); 3063 } 3064 3065 data->is_tlu_enabled = false; 3066 3067 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 3068 SMU7_MAX_HARDWARE_POWERLEVELS; 3069 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 3070 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 3071 3072 data->pcie_gen_cap = adev->pm.pcie_gen_mask; 3073 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 3074 data->pcie_spc_cap = 20; 3075 else 3076 data->pcie_spc_cap = 16; 3077 data->pcie_lane_cap = adev->pm.pcie_mlw_mask; 3078 3079 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 3080 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 3081 hwmgr->platform_descriptor.clockStep.engineClock = 500; 3082 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 3083 smu7_thermal_parameter_init(hwmgr); 3084 3085 result = smu7_update_edc_leakage_table(hwmgr); 3086 if (result) 3087 goto fail; 3088 3089 return 0; 3090 fail: 3091 smu7_hwmgr_backend_fini(hwmgr); 3092 return result; 3093 } 3094 3095 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) 3096 { 3097 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3098 uint32_t level, tmp; 3099 3100 if (!data->pcie_dpm_key_disabled) { 3101 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3102 level = 0; 3103 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; 3104 while (tmp >>= 1) 3105 level++; 3106 3107 if (level) 3108 smum_send_msg_to_smc_with_parameter(hwmgr, 3109 PPSMC_MSG_PCIeDPM_ForceLevel, level, 3110 NULL); 3111 } 3112 } 3113 3114 if (!data->sclk_dpm_key_disabled) { 3115 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3116 level = 0; 3117 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; 3118 while (tmp >>= 1) 3119 level++; 3120 3121 if (level) 3122 smum_send_msg_to_smc_with_parameter(hwmgr, 3123 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3124 (1 << level), 3125 NULL); 3126 } 3127 } 3128 3129 if (!data->mclk_dpm_key_disabled) { 3130 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3131 level = 0; 3132 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; 3133 while (tmp >>= 1) 3134 level++; 3135 3136 if (level) 3137 smum_send_msg_to_smc_with_parameter(hwmgr, 3138 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3139 (1 << level), 3140 NULL); 3141 } 3142 } 3143 3144 return 0; 3145 } 3146 3147 static uint32_t smu7_lookup_vddc_from_dispclk(struct pp_hwmgr *hwmgr) 3148 { 3149 const struct amd_pp_display_configuration *cfg = hwmgr->display_config; 3150 const struct phm_clock_voltage_dependency_table *vddc_dep_on_dispclk = 3151 hwmgr->dyn_state.vddc_dependency_on_display_clock; 3152 uint32_t i; 3153 3154 if (!vddc_dep_on_dispclk || !vddc_dep_on_dispclk->count || 3155 !cfg || !cfg->num_display || !cfg->display_clk) 3156 return 0; 3157 3158 /* Start from 1 because ClocksStateUltraLow should not be used according to DC. */ 3159 for (i = 1; i < vddc_dep_on_dispclk->count; ++i) 3160 if (vddc_dep_on_dispclk->entries[i].clk >= cfg->display_clk) 3161 return vddc_dep_on_dispclk->entries[i].v; 3162 3163 return vddc_dep_on_dispclk->entries[vddc_dep_on_dispclk->count - 1].v; 3164 } 3165 3166 static void smu7_apply_minimum_dce_voltage_request(struct pp_hwmgr *hwmgr) 3167 { 3168 uint32_t req_vddc = smu7_lookup_vddc_from_dispclk(hwmgr); 3169 3170 smum_send_msg_to_smc_with_parameter(hwmgr, 3171 PPSMC_MSG_VddC_Request, 3172 req_vddc * VOLTAGE_SCALE, 3173 NULL); 3174 } 3175 3176 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) 3177 { 3178 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3179 3180 smu7_apply_minimum_dce_voltage_request(hwmgr); 3181 3182 if (!data->sclk_dpm_key_disabled) { 3183 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) 3184 smum_send_msg_to_smc_with_parameter(hwmgr, 3185 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3186 data->dpm_level_enable_mask.sclk_dpm_enable_mask, 3187 NULL); 3188 } 3189 3190 if (!data->mclk_dpm_key_disabled) { 3191 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) 3192 smum_send_msg_to_smc_with_parameter(hwmgr, 3193 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3194 data->dpm_level_enable_mask.mclk_dpm_enable_mask, 3195 NULL); 3196 } 3197 3198 return 0; 3199 } 3200 3201 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 3202 { 3203 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3204 3205 if (!smum_is_dpm_running(hwmgr)) 3206 return -EINVAL; 3207 3208 if (!data->pcie_dpm_key_disabled) { 3209 smum_send_msg_to_smc(hwmgr, 3210 PPSMC_MSG_PCIeDPM_UnForceLevel, 3211 NULL); 3212 } 3213 3214 return smu7_upload_dpm_level_enable_mask(hwmgr); 3215 } 3216 3217 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) 3218 { 3219 struct smu7_hwmgr *data = 3220 (struct smu7_hwmgr *)(hwmgr->backend); 3221 uint32_t level; 3222 3223 if (!data->sclk_dpm_key_disabled) 3224 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3225 level = phm_get_lowest_enabled_level(hwmgr, 3226 data->dpm_level_enable_mask.sclk_dpm_enable_mask); 3227 smum_send_msg_to_smc_with_parameter(hwmgr, 3228 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3229 (1 << level), 3230 NULL); 3231 3232 } 3233 3234 if (!data->mclk_dpm_key_disabled) { 3235 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3236 level = phm_get_lowest_enabled_level(hwmgr, 3237 data->dpm_level_enable_mask.mclk_dpm_enable_mask); 3238 smum_send_msg_to_smc_with_parameter(hwmgr, 3239 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3240 (1 << level), 3241 NULL); 3242 } 3243 } 3244 3245 if (!data->pcie_dpm_key_disabled) { 3246 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3247 level = phm_get_lowest_enabled_level(hwmgr, 3248 data->dpm_level_enable_mask.pcie_dpm_enable_mask); 3249 smum_send_msg_to_smc_with_parameter(hwmgr, 3250 PPSMC_MSG_PCIeDPM_ForceLevel, 3251 (level), 3252 NULL); 3253 } 3254 } 3255 3256 return 0; 3257 } 3258 3259 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 3260 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) 3261 { 3262 uint32_t percentage; 3263 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3264 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; 3265 int32_t tmp_mclk; 3266 int32_t tmp_sclk; 3267 int32_t count; 3268 3269 if (golden_dpm_table->mclk_table.count < 1) 3270 return -EINVAL; 3271 3272 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / 3273 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 3274 3275 if (golden_dpm_table->mclk_table.count == 1) { 3276 percentage = 70; 3277 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 3278 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 3279 } else { 3280 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; 3281 *mclk_mask = golden_dpm_table->mclk_table.count - 2; 3282 } 3283 3284 tmp_sclk = tmp_mclk * percentage / 100; 3285 3286 if (hwmgr->pp_table_version == PP_TABLE_V0) { 3287 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 3288 count >= 0; count--) { 3289 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { 3290 *sclk_mask = count; 3291 break; 3292 } 3293 } 3294 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 3295 *sclk_mask = 0; 3296 3297 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3298 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 3299 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 3300 struct phm_ppt_v1_information *table_info = 3301 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3302 3303 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { 3304 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) { 3305 *sclk_mask = count; 3306 break; 3307 } 3308 } 3309 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 3310 *sclk_mask = 0; 3311 3312 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3313 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 3314 } 3315 3316 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) 3317 *mclk_mask = 0; 3318 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3319 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 3320 3321 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1; 3322 3323 return 0; 3324 } 3325 3326 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, 3327 enum amd_dpm_forced_level level) 3328 { 3329 int ret = 0; 3330 uint32_t sclk_mask = 0; 3331 uint32_t mclk_mask = 0; 3332 uint32_t pcie_mask = 0; 3333 3334 switch (level) { 3335 case AMD_DPM_FORCED_LEVEL_HIGH: 3336 ret = smu7_force_dpm_highest(hwmgr); 3337 break; 3338 case AMD_DPM_FORCED_LEVEL_LOW: 3339 ret = smu7_force_dpm_lowest(hwmgr); 3340 break; 3341 case AMD_DPM_FORCED_LEVEL_AUTO: 3342 ret = smu7_unforce_dpm_levels(hwmgr); 3343 break; 3344 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 3345 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 3346 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 3347 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 3348 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); 3349 if (ret) 3350 return ret; 3351 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 3352 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 3353 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); 3354 break; 3355 case AMD_DPM_FORCED_LEVEL_MANUAL: 3356 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 3357 default: 3358 break; 3359 } 3360 3361 if (!ret) { 3362 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3363 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 3364 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3365 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); 3366 } 3367 return ret; 3368 } 3369 3370 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) 3371 { 3372 return sizeof(struct smu7_power_state); 3373 } 3374 3375 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr, 3376 uint32_t vblank_time_us) 3377 { 3378 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3379 uint32_t switch_limit_us; 3380 3381 switch (hwmgr->chip_id) { 3382 case CHIP_POLARIS10: 3383 case CHIP_POLARIS11: 3384 case CHIP_POLARIS12: 3385 if (hwmgr->is_kicker || (hwmgr->chip_id == CHIP_POLARIS12)) 3386 switch_limit_us = data->is_memory_gddr5 ? 450 : 150; 3387 else 3388 switch_limit_us = data->is_memory_gddr5 ? 200 : 150; 3389 break; 3390 case CHIP_VEGAM: 3391 switch_limit_us = 30; 3392 break; 3393 default: 3394 switch_limit_us = data->is_memory_gddr5 ? 450 : 150; 3395 break; 3396 } 3397 3398 if (vblank_time_us < switch_limit_us) 3399 return true; 3400 else 3401 return false; 3402 } 3403 3404 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 3405 struct pp_power_state *request_ps, 3406 const struct pp_power_state *current_ps) 3407 { 3408 struct amdgpu_device *adev = hwmgr->adev; 3409 struct smu7_power_state *smu7_ps; 3410 uint32_t sclk; 3411 uint32_t mclk; 3412 struct PP_Clocks minimum_clocks = {0}; 3413 bool disable_mclk_switching; 3414 bool disable_mclk_switching_for_frame_lock; 3415 bool disable_mclk_switching_for_display; 3416 const struct phm_clock_and_voltage_limits *max_limits; 3417 uint32_t i; 3418 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3419 struct phm_ppt_v1_information *table_info = 3420 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3421 int32_t count; 3422 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; 3423 uint32_t latency; 3424 bool latency_allowed = false; 3425 3426 smu7_ps = cast_phw_smu7_power_state(&request_ps->hardware); 3427 if (!smu7_ps) 3428 return -EINVAL; 3429 3430 data->battery_state = (PP_StateUILabel_Battery == 3431 request_ps->classification.ui_label); 3432 data->mclk_ignore_signal = false; 3433 3434 max_limits = adev->pm.ac_power ? 3435 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : 3436 &(hwmgr->dyn_state.max_clock_voltage_on_dc); 3437 3438 /* Cap clock DPM tables at DC MAX if it is in DC. */ 3439 if (!adev->pm.ac_power) { 3440 for (i = 0; i < smu7_ps->performance_level_count; i++) { 3441 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) 3442 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; 3443 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) 3444 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; 3445 } 3446 } 3447 3448 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; 3449 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 3450 3451 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3452 PHM_PlatformCaps_StablePState)) { 3453 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); 3454 stable_pstate_sclk = (max_limits->sclk * 75) / 100; 3455 3456 for (count = table_info->vdd_dep_on_sclk->count - 1; 3457 count >= 0; count--) { 3458 if (stable_pstate_sclk >= 3459 table_info->vdd_dep_on_sclk->entries[count].clk) { 3460 stable_pstate_sclk = 3461 table_info->vdd_dep_on_sclk->entries[count].clk; 3462 break; 3463 } 3464 } 3465 3466 if (count < 0) 3467 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3468 3469 stable_pstate_mclk = max_limits->mclk; 3470 3471 minimum_clocks.engineClock = stable_pstate_sclk; 3472 minimum_clocks.memoryClock = stable_pstate_mclk; 3473 } 3474 3475 disable_mclk_switching_for_frame_lock = phm_cap_enabled( 3476 hwmgr->platform_descriptor.platformCaps, 3477 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 3478 3479 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && 3480 !hwmgr->display_config->multi_monitor_in_sync) || 3481 (hwmgr->display_config->num_display && 3482 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); 3483 3484 disable_mclk_switching = disable_mclk_switching_for_frame_lock || 3485 disable_mclk_switching_for_display; 3486 3487 if (hwmgr->display_config->num_display == 0) { 3488 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) 3489 data->mclk_ignore_signal = true; 3490 else 3491 disable_mclk_switching = false; 3492 } 3493 3494 sclk = smu7_ps->performance_levels[0].engine_clock; 3495 mclk = smu7_ps->performance_levels[0].memory_clock; 3496 3497 if (disable_mclk_switching && 3498 (!(hwmgr->chip_id >= CHIP_POLARIS10 && 3499 hwmgr->chip_id <= CHIP_VEGAM))) 3500 mclk = smu7_ps->performance_levels 3501 [smu7_ps->performance_level_count - 1].memory_clock; 3502 3503 if (sclk < minimum_clocks.engineClock) 3504 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? 3505 max_limits->sclk : minimum_clocks.engineClock; 3506 3507 if (mclk < minimum_clocks.memoryClock) 3508 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? 3509 max_limits->mclk : minimum_clocks.memoryClock; 3510 3511 smu7_ps->performance_levels[0].engine_clock = sclk; 3512 smu7_ps->performance_levels[0].memory_clock = mclk; 3513 3514 smu7_ps->performance_levels[1].engine_clock = 3515 (smu7_ps->performance_levels[1].engine_clock >= 3516 smu7_ps->performance_levels[0].engine_clock) ? 3517 smu7_ps->performance_levels[1].engine_clock : 3518 smu7_ps->performance_levels[0].engine_clock; 3519 3520 if (disable_mclk_switching) { 3521 if (mclk < smu7_ps->performance_levels[1].memory_clock) 3522 mclk = smu7_ps->performance_levels[1].memory_clock; 3523 3524 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) { 3525 if (disable_mclk_switching_for_display) { 3526 /* Find the lowest MCLK frequency that is within 3527 * the tolerable latency defined in DAL 3528 */ 3529 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3530 for (i = 0; i < data->mclk_latency_table.count; i++) { 3531 if (data->mclk_latency_table.entries[i].latency <= latency) { 3532 latency_allowed = true; 3533 3534 if ((data->mclk_latency_table.entries[i].frequency >= 3535 smu7_ps->performance_levels[0].memory_clock) && 3536 (data->mclk_latency_table.entries[i].frequency <= 3537 smu7_ps->performance_levels[1].memory_clock)) { 3538 mclk = data->mclk_latency_table.entries[i].frequency; 3539 break; 3540 } 3541 } 3542 } 3543 if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) { 3544 data->mclk_ignore_signal = true; 3545 } else { 3546 data->mclk_ignore_signal = false; 3547 } 3548 } 3549 3550 if (disable_mclk_switching_for_frame_lock) 3551 mclk = smu7_ps->performance_levels[1].memory_clock; 3552 } 3553 3554 smu7_ps->performance_levels[0].memory_clock = mclk; 3555 3556 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 3557 hwmgr->chip_id <= CHIP_VEGAM)) 3558 smu7_ps->performance_levels[1].memory_clock = mclk; 3559 } else { 3560 if (smu7_ps->performance_levels[1].memory_clock < 3561 smu7_ps->performance_levels[0].memory_clock) 3562 smu7_ps->performance_levels[1].memory_clock = 3563 smu7_ps->performance_levels[0].memory_clock; 3564 } 3565 3566 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3567 PHM_PlatformCaps_StablePState)) { 3568 for (i = 0; i < smu7_ps->performance_level_count; i++) { 3569 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk; 3570 smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk; 3571 smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; 3572 smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; 3573 } 3574 } 3575 return 0; 3576 } 3577 3578 3579 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 3580 { 3581 struct pp_power_state *ps; 3582 struct smu7_power_state *smu7_ps; 3583 3584 if (hwmgr == NULL) 3585 return -EINVAL; 3586 3587 ps = hwmgr->request_ps; 3588 3589 if (ps == NULL) 3590 return -EINVAL; 3591 3592 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3593 3594 if (low) 3595 return smu7_ps->performance_levels[0].memory_clock; 3596 else 3597 return smu7_ps->performance_levels 3598 [smu7_ps->performance_level_count-1].memory_clock; 3599 } 3600 3601 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 3602 { 3603 struct pp_power_state *ps; 3604 struct smu7_power_state *smu7_ps; 3605 3606 if (hwmgr == NULL) 3607 return -EINVAL; 3608 3609 ps = hwmgr->request_ps; 3610 3611 if (ps == NULL) 3612 return -EINVAL; 3613 3614 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3615 3616 if (low) 3617 return smu7_ps->performance_levels[0].engine_clock; 3618 else 3619 return smu7_ps->performance_levels 3620 [smu7_ps->performance_level_count-1].engine_clock; 3621 } 3622 3623 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, 3624 struct pp_hw_power_state *hw_ps) 3625 { 3626 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3627 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps; 3628 ATOM_FIRMWARE_INFO_V2_2 *fw_info; 3629 uint16_t size; 3630 uint8_t frev, crev; 3631 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 3632 3633 /* First retrieve the Boot clocks and VDDC from the firmware info table. 3634 * We assume here that fw_info is unchanged if this call fails. 3635 */ 3636 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index, 3637 &size, &frev, &crev); 3638 if (!fw_info) 3639 /* During a test, there is no firmware info table. */ 3640 return 0; 3641 3642 /* Patch the state. */ 3643 data->vbios_boot_state.sclk_bootup_value = 3644 le32_to_cpu(fw_info->ulDefaultEngineClock); 3645 data->vbios_boot_state.mclk_bootup_value = 3646 le32_to_cpu(fw_info->ulDefaultMemoryClock); 3647 data->vbios_boot_state.mvdd_bootup_value = 3648 le16_to_cpu(fw_info->usBootUpMVDDCVoltage); 3649 data->vbios_boot_state.vddc_bootup_value = 3650 le16_to_cpu(fw_info->usBootUpVDDCVoltage); 3651 data->vbios_boot_state.vddci_bootup_value = 3652 le16_to_cpu(fw_info->usBootUpVDDCIVoltage); 3653 data->vbios_boot_state.pcie_gen_bootup_value = 3654 smu7_get_current_pcie_speed(hwmgr); 3655 3656 data->vbios_boot_state.pcie_lane_bootup_value = 3657 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr); 3658 3659 /* set boot power state */ 3660 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; 3661 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; 3662 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; 3663 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; 3664 3665 return 0; 3666 } 3667 3668 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) 3669 { 3670 int result; 3671 unsigned long ret = 0; 3672 3673 if (hwmgr->pp_table_version == PP_TABLE_V0) { 3674 result = pp_tables_get_num_of_entries(hwmgr, &ret); 3675 return result ? 0 : ret; 3676 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 3677 result = get_number_of_powerplay_table_entries_v1_0(hwmgr); 3678 return result; 3679 } 3680 return 0; 3681 } 3682 3683 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, 3684 void *state, struct pp_power_state *power_state, 3685 void *pp_table, uint32_t classification_flag) 3686 { 3687 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3688 struct smu7_power_state *smu7_power_state = 3689 (struct smu7_power_state *)(&(power_state->hardware)); 3690 struct smu7_performance_level *performance_level; 3691 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; 3692 ATOM_Tonga_POWERPLAYTABLE *powerplay_table = 3693 (ATOM_Tonga_POWERPLAYTABLE *)pp_table; 3694 PPTable_Generic_SubTable_Header *sclk_dep_table = 3695 (PPTable_Generic_SubTable_Header *) 3696 (((unsigned long)powerplay_table) + 3697 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); 3698 3699 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = 3700 (ATOM_Tonga_MCLK_Dependency_Table *) 3701 (((unsigned long)powerplay_table) + 3702 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 3703 3704 /* The following fields are not initialized here: id orderedList allStatesList */ 3705 power_state->classification.ui_label = 3706 (le16_to_cpu(state_entry->usClassification) & 3707 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> 3708 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; 3709 power_state->classification.flags = classification_flag; 3710 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ 3711 3712 power_state->classification.temporary_state = false; 3713 power_state->classification.to_be_deleted = false; 3714 3715 power_state->validation.disallowOnDC = 3716 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & 3717 ATOM_Tonga_DISALLOW_ON_DC)); 3718 3719 power_state->pcie.lanes = 0; 3720 3721 power_state->display.disableFrameModulation = false; 3722 power_state->display.limitRefreshrate = false; 3723 power_state->display.enableVariBright = 3724 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & 3725 ATOM_Tonga_ENABLE_VARIBRIGHT)); 3726 3727 power_state->validation.supportedPowerLevels = 0; 3728 power_state->uvd_clocks.VCLK = 0; 3729 power_state->uvd_clocks.DCLK = 0; 3730 power_state->temperatures.min = 0; 3731 power_state->temperatures.max = 0; 3732 3733 performance_level = &(smu7_power_state->performance_levels 3734 [smu7_power_state->performance_level_count++]); 3735 3736 PP_ASSERT_WITH_CODE( 3737 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), 3738 "Performance levels exceeds SMC limit!", 3739 return -EINVAL); 3740 3741 PP_ASSERT_WITH_CODE( 3742 (smu7_power_state->performance_level_count < 3743 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3744 "Performance levels exceeds Driver limit!", 3745 return -EINVAL); 3746 3747 /* Performance levels are arranged from low to high. */ 3748 performance_level->memory_clock = mclk_dep_table->entries 3749 [state_entry->ucMemoryClockIndexLow].ulMclk; 3750 if (sclk_dep_table->ucRevId == 0) 3751 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries 3752 [state_entry->ucEngineClockIndexLow].ulSclk; 3753 else if (sclk_dep_table->ucRevId == 1) 3754 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries 3755 [state_entry->ucEngineClockIndexLow].ulSclk; 3756 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3757 state_entry->ucPCIEGenLow); 3758 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3759 state_entry->ucPCIELaneLow); 3760 3761 performance_level = &(smu7_power_state->performance_levels 3762 [smu7_power_state->performance_level_count++]); 3763 performance_level->memory_clock = mclk_dep_table->entries 3764 [state_entry->ucMemoryClockIndexHigh].ulMclk; 3765 3766 if (sclk_dep_table->ucRevId == 0) 3767 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries 3768 [state_entry->ucEngineClockIndexHigh].ulSclk; 3769 else if (sclk_dep_table->ucRevId == 1) 3770 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries 3771 [state_entry->ucEngineClockIndexHigh].ulSclk; 3772 3773 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3774 state_entry->ucPCIEGenHigh); 3775 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3776 state_entry->ucPCIELaneHigh); 3777 3778 return 0; 3779 } 3780 3781 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr, 3782 unsigned long entry_index, struct pp_power_state *state) 3783 { 3784 int result; 3785 struct smu7_power_state *ps; 3786 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3787 struct phm_ppt_v1_information *table_info = 3788 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3789 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 3790 table_info->vdd_dep_on_mclk; 3791 3792 state->hardware.magic = PHM_VIslands_Magic; 3793 3794 ps = (struct smu7_power_state *)(&state->hardware); 3795 3796 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state, 3797 smu7_get_pp_table_entry_callback_func_v1); 3798 3799 /* This is the earliest time we have all the dependency table and the VBIOS boot state 3800 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state 3801 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state 3802 */ 3803 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { 3804 if (dep_mclk_table->entries[0].clk != 3805 data->vbios_boot_state.mclk_bootup_value) 3806 pr_debug("Single MCLK entry VDDCI/MCLK dependency table " 3807 "does not match VBIOS boot MCLK level"); 3808 if (dep_mclk_table->entries[0].vddci != 3809 data->vbios_boot_state.vddci_bootup_value) 3810 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " 3811 "does not match VBIOS boot VDDCI level"); 3812 } 3813 3814 /* set DC compatible flag if this state supports DC */ 3815 if (!state->validation.disallowOnDC) 3816 ps->dc_compatible = true; 3817 3818 if (state->classification.flags & PP_StateClassificationFlag_ACPI) 3819 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; 3820 3821 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3822 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3823 3824 if (!result) { 3825 uint32_t i; 3826 3827 switch (state->classification.ui_label) { 3828 case PP_StateUILabel_Performance: 3829 data->use_pcie_performance_levels = true; 3830 for (i = 0; i < ps->performance_level_count; i++) { 3831 if (data->pcie_gen_performance.max < 3832 ps->performance_levels[i].pcie_gen) 3833 data->pcie_gen_performance.max = 3834 ps->performance_levels[i].pcie_gen; 3835 3836 if (data->pcie_gen_performance.min > 3837 ps->performance_levels[i].pcie_gen) 3838 data->pcie_gen_performance.min = 3839 ps->performance_levels[i].pcie_gen; 3840 3841 if (data->pcie_lane_performance.max < 3842 ps->performance_levels[i].pcie_lane) 3843 data->pcie_lane_performance.max = 3844 ps->performance_levels[i].pcie_lane; 3845 if (data->pcie_lane_performance.min > 3846 ps->performance_levels[i].pcie_lane) 3847 data->pcie_lane_performance.min = 3848 ps->performance_levels[i].pcie_lane; 3849 } 3850 break; 3851 case PP_StateUILabel_Battery: 3852 data->use_pcie_power_saving_levels = true; 3853 3854 for (i = 0; i < ps->performance_level_count; i++) { 3855 if (data->pcie_gen_power_saving.max < 3856 ps->performance_levels[i].pcie_gen) 3857 data->pcie_gen_power_saving.max = 3858 ps->performance_levels[i].pcie_gen; 3859 3860 if (data->pcie_gen_power_saving.min > 3861 ps->performance_levels[i].pcie_gen) 3862 data->pcie_gen_power_saving.min = 3863 ps->performance_levels[i].pcie_gen; 3864 3865 if (data->pcie_lane_power_saving.max < 3866 ps->performance_levels[i].pcie_lane) 3867 data->pcie_lane_power_saving.max = 3868 ps->performance_levels[i].pcie_lane; 3869 3870 if (data->pcie_lane_power_saving.min > 3871 ps->performance_levels[i].pcie_lane) 3872 data->pcie_lane_power_saving.min = 3873 ps->performance_levels[i].pcie_lane; 3874 } 3875 break; 3876 default: 3877 break; 3878 } 3879 } 3880 return 0; 3881 } 3882 3883 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, 3884 struct pp_hw_power_state *power_state, 3885 unsigned int index, const void *clock_info) 3886 { 3887 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3888 struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state); 3889 const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info; 3890 struct smu7_performance_level *performance_level; 3891 uint32_t engine_clock, memory_clock; 3892 uint16_t pcie_gen_from_bios; 3893 3894 engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow; 3895 memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow; 3896 3897 if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk) 3898 data->highest_mclk = memory_clock; 3899 3900 PP_ASSERT_WITH_CODE( 3901 (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), 3902 "Performance levels exceeds SMC limit!", 3903 return -EINVAL); 3904 3905 PP_ASSERT_WITH_CODE( 3906 (ps->performance_level_count < 3907 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3908 "Performance levels exceeds Driver limit, Skip!", 3909 return 0); 3910 3911 performance_level = &(ps->performance_levels 3912 [ps->performance_level_count++]); 3913 3914 /* Performance levels are arranged from low to high. */ 3915 performance_level->memory_clock = memory_clock; 3916 performance_level->engine_clock = min(engine_clock, data->sclk_cap); 3917 3918 pcie_gen_from_bios = visland_clk_info->ucPCIEGen; 3919 3920 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios); 3921 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane); 3922 3923 return 0; 3924 } 3925 3926 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr, 3927 unsigned long entry_index, struct pp_power_state *state) 3928 { 3929 int result; 3930 struct smu7_power_state *ps; 3931 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3932 struct phm_clock_voltage_dependency_table *dep_mclk_table = 3933 hwmgr->dyn_state.vddci_dependency_on_mclk; 3934 3935 memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state)); 3936 3937 state->hardware.magic = PHM_VIslands_Magic; 3938 3939 ps = (struct smu7_power_state *)(&state->hardware); 3940 3941 result = pp_tables_get_entry(hwmgr, entry_index, state, 3942 smu7_get_pp_table_entry_callback_func_v0); 3943 3944 /* 3945 * This is the earliest time we have all the dependency table 3946 * and the VBIOS boot state as 3947 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot 3948 * state if there is only one VDDCI/MCLK level, check if it's 3949 * the same as VBIOS boot state 3950 */ 3951 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { 3952 if (dep_mclk_table->entries[0].clk != 3953 data->vbios_boot_state.mclk_bootup_value) 3954 pr_debug("Single MCLK entry VDDCI/MCLK dependency table " 3955 "does not match VBIOS boot MCLK level"); 3956 if (dep_mclk_table->entries[0].v != 3957 data->vbios_boot_state.vddci_bootup_value) 3958 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " 3959 "does not match VBIOS boot VDDCI level"); 3960 } 3961 3962 /* set DC compatible flag if this state supports DC */ 3963 if (!state->validation.disallowOnDC) 3964 ps->dc_compatible = true; 3965 3966 if (state->classification.flags & PP_StateClassificationFlag_ACPI) 3967 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; 3968 3969 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3970 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3971 3972 if (!result) { 3973 uint32_t i; 3974 3975 switch (state->classification.ui_label) { 3976 case PP_StateUILabel_Performance: 3977 data->use_pcie_performance_levels = true; 3978 3979 for (i = 0; i < ps->performance_level_count; i++) { 3980 if (data->pcie_gen_performance.max < 3981 ps->performance_levels[i].pcie_gen) 3982 data->pcie_gen_performance.max = 3983 ps->performance_levels[i].pcie_gen; 3984 3985 if (data->pcie_gen_performance.min > 3986 ps->performance_levels[i].pcie_gen) 3987 data->pcie_gen_performance.min = 3988 ps->performance_levels[i].pcie_gen; 3989 3990 if (data->pcie_lane_performance.max < 3991 ps->performance_levels[i].pcie_lane) 3992 data->pcie_lane_performance.max = 3993 ps->performance_levels[i].pcie_lane; 3994 3995 if (data->pcie_lane_performance.min > 3996 ps->performance_levels[i].pcie_lane) 3997 data->pcie_lane_performance.min = 3998 ps->performance_levels[i].pcie_lane; 3999 } 4000 break; 4001 case PP_StateUILabel_Battery: 4002 data->use_pcie_power_saving_levels = true; 4003 4004 for (i = 0; i < ps->performance_level_count; i++) { 4005 if (data->pcie_gen_power_saving.max < 4006 ps->performance_levels[i].pcie_gen) 4007 data->pcie_gen_power_saving.max = 4008 ps->performance_levels[i].pcie_gen; 4009 4010 if (data->pcie_gen_power_saving.min > 4011 ps->performance_levels[i].pcie_gen) 4012 data->pcie_gen_power_saving.min = 4013 ps->performance_levels[i].pcie_gen; 4014 4015 if (data->pcie_lane_power_saving.max < 4016 ps->performance_levels[i].pcie_lane) 4017 data->pcie_lane_power_saving.max = 4018 ps->performance_levels[i].pcie_lane; 4019 4020 if (data->pcie_lane_power_saving.min > 4021 ps->performance_levels[i].pcie_lane) 4022 data->pcie_lane_power_saving.min = 4023 ps->performance_levels[i].pcie_lane; 4024 } 4025 break; 4026 default: 4027 break; 4028 } 4029 } 4030 return 0; 4031 } 4032 4033 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, 4034 unsigned long entry_index, struct pp_power_state *state) 4035 { 4036 if (hwmgr->pp_table_version == PP_TABLE_V0) 4037 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state); 4038 else if (hwmgr->pp_table_version == PP_TABLE_V1) 4039 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state); 4040 4041 return 0; 4042 } 4043 4044 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query) 4045 { 4046 struct amdgpu_device *adev = hwmgr->adev; 4047 int i; 4048 u32 tmp = 0; 4049 4050 if (!query) 4051 return -EINVAL; 4052 4053 /* 4054 * PPSMC_MSG_GetCurrPkgPwr is not supported on: 4055 * - Hawaii 4056 * - Bonaire 4057 * - Fiji 4058 * - Tonga 4059 */ 4060 if ((adev->asic_type != CHIP_HAWAII) && 4061 (adev->asic_type != CHIP_BONAIRE) && 4062 (adev->asic_type != CHIP_FIJI) && 4063 (adev->asic_type != CHIP_TONGA)) { 4064 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp); 4065 *query = tmp; 4066 4067 if (tmp != 0) 4068 return 0; 4069 } 4070 4071 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL); 4072 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4073 ixSMU_PM_STATUS_95, 0); 4074 4075 for (i = 0; i < 10; i++) { 4076 msleep(500); 4077 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL); 4078 tmp = cgs_read_ind_register(hwmgr->device, 4079 CGS_IND_REG__SMC, 4080 ixSMU_PM_STATUS_95); 4081 if (tmp != 0) 4082 break; 4083 } 4084 *query = tmp; 4085 4086 return 0; 4087 } 4088 4089 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, 4090 void *value, int *size) 4091 { 4092 uint32_t sclk, mclk, activity_percent; 4093 uint32_t offset, val_vid; 4094 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4095 struct amdgpu_device *adev = hwmgr->adev; 4096 int ret = 0; 4097 4098 /* size must be at least 4 bytes for all sensors */ 4099 if (*size < 4) 4100 return -EINVAL; 4101 4102 switch (idx) { 4103 case AMDGPU_PP_SENSOR_GFX_SCLK: 4104 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &sclk); 4105 if (ret) 4106 return ret; 4107 *((uint32_t *)value) = sclk; 4108 *size = 4; 4109 return 0; 4110 case AMDGPU_PP_SENSOR_GFX_MCLK: 4111 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &mclk); 4112 if (ret) 4113 return ret; 4114 *((uint32_t *)value) = mclk; 4115 *size = 4; 4116 return 0; 4117 case AMDGPU_PP_SENSOR_GPU_LOAD: 4118 case AMDGPU_PP_SENSOR_MEM_LOAD: 4119 offset = data->soft_regs_start + smum_get_offsetof(hwmgr, 4120 SMU_SoftRegisters, 4121 (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ? 4122 AverageGraphicsActivity : 4123 AverageMemoryActivity); 4124 4125 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); 4126 activity_percent += 0x80; 4127 activity_percent >>= 8; 4128 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 4129 *size = 4; 4130 return 0; 4131 case AMDGPU_PP_SENSOR_GPU_TEMP: 4132 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr); 4133 *size = 4; 4134 return 0; 4135 case AMDGPU_PP_SENSOR_UVD_POWER: 4136 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 4137 *size = 4; 4138 return 0; 4139 case AMDGPU_PP_SENSOR_VCE_POWER: 4140 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 4141 *size = 4; 4142 return 0; 4143 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 4144 if ((adev->asic_type != CHIP_HAWAII) && 4145 (adev->asic_type != CHIP_BONAIRE) && 4146 (adev->asic_type != CHIP_FIJI) && 4147 (adev->asic_type != CHIP_TONGA)) 4148 return smu7_get_gpu_power(hwmgr, (uint32_t *)value); 4149 else 4150 return -EOPNOTSUPP; 4151 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 4152 if ((adev->asic_type != CHIP_HAWAII) && 4153 (adev->asic_type != CHIP_BONAIRE) && 4154 (adev->asic_type != CHIP_FIJI) && 4155 (adev->asic_type != CHIP_TONGA)) 4156 return -EOPNOTSUPP; 4157 else 4158 return smu7_get_gpu_power(hwmgr, (uint32_t *)value); 4159 case AMDGPU_PP_SENSOR_VDDGFX: 4160 if ((data->vr_config & VRCONF_VDDGFX_MASK) == 4161 (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT)) 4162 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, 4163 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID); 4164 else 4165 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, 4166 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID); 4167 4168 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid); 4169 return 0; 4170 default: 4171 return -EOPNOTSUPP; 4172 } 4173 } 4174 4175 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) 4176 { 4177 const struct phm_set_power_state_input *states = 4178 (const struct phm_set_power_state_input *)input; 4179 const struct smu7_power_state *smu7_ps = 4180 cast_const_phw_smu7_power_state(states->pnew_state); 4181 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4182 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4183 uint32_t sclk = smu7_ps->performance_levels 4184 [smu7_ps->performance_level_count - 1].engine_clock; 4185 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4186 uint32_t mclk = smu7_ps->performance_levels 4187 [smu7_ps->performance_level_count - 1].memory_clock; 4188 struct PP_Clocks min_clocks = {0}; 4189 uint32_t i; 4190 4191 for (i = 0; i < sclk_table->count; i++) { 4192 if (sclk == sclk_table->dpm_levels[i].value) 4193 break; 4194 } 4195 4196 if (i >= sclk_table->count) { 4197 if (sclk > sclk_table->dpm_levels[i-1].value) { 4198 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 4199 sclk_table->dpm_levels[i-1].value = sclk; 4200 } 4201 } else { 4202 /* TODO: Check SCLK in DAL's minimum clocks 4203 * in case DeepSleep divider update is required. 4204 */ 4205 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && 4206 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || 4207 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) 4208 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 4209 } 4210 4211 for (i = 0; i < mclk_table->count; i++) { 4212 if (mclk == mclk_table->dpm_levels[i].value) 4213 break; 4214 } 4215 4216 if (i >= mclk_table->count) { 4217 if (mclk > mclk_table->dpm_levels[i-1].value) { 4218 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 4219 mclk_table->dpm_levels[i-1].value = mclk; 4220 } 4221 } 4222 4223 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 4224 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 4225 4226 return 0; 4227 } 4228 4229 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr, 4230 const struct smu7_power_state *smu7_ps) 4231 { 4232 uint32_t i; 4233 uint32_t sclk, max_sclk = 0; 4234 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4235 struct smu7_dpm_table *dpm_table = &data->dpm_table; 4236 4237 for (i = 0; i < smu7_ps->performance_level_count; i++) { 4238 sclk = smu7_ps->performance_levels[i].engine_clock; 4239 if (max_sclk < sclk) 4240 max_sclk = sclk; 4241 } 4242 4243 for (i = 0; i < dpm_table->sclk_table.count; i++) { 4244 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) 4245 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? 4246 dpm_table->pcie_speed_table.dpm_levels 4247 [dpm_table->pcie_speed_table.count - 1].value : 4248 dpm_table->pcie_speed_table.dpm_levels[i].value); 4249 } 4250 4251 return 0; 4252 } 4253 4254 static int smu7_request_link_speed_change_before_state_change( 4255 struct pp_hwmgr *hwmgr, const void *input) 4256 { 4257 const struct phm_set_power_state_input *states = 4258 (const struct phm_set_power_state_input *)input; 4259 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4260 const struct smu7_power_state *smu7_nps = 4261 cast_const_phw_smu7_power_state(states->pnew_state); 4262 const struct smu7_power_state *polaris10_cps = 4263 cast_const_phw_smu7_power_state(states->pcurrent_state); 4264 4265 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps); 4266 uint16_t current_link_speed; 4267 4268 if (data->force_pcie_gen == PP_PCIEGenInvalid) 4269 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps); 4270 else 4271 current_link_speed = data->force_pcie_gen; 4272 4273 data->force_pcie_gen = PP_PCIEGenInvalid; 4274 data->pspp_notify_required = false; 4275 4276 if (target_link_speed > current_link_speed) { 4277 switch (target_link_speed) { 4278 #ifdef CONFIG_ACPI 4279 case PP_PCIEGen3: 4280 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false)) 4281 break; 4282 data->force_pcie_gen = PP_PCIEGen2; 4283 if (current_link_speed == PP_PCIEGen2) 4284 break; 4285 fallthrough; 4286 case PP_PCIEGen2: 4287 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false)) 4288 break; 4289 fallthrough; 4290 #endif 4291 default: 4292 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr); 4293 break; 4294 } 4295 } else { 4296 if (target_link_speed < current_link_speed) 4297 data->pspp_notify_required = true; 4298 } 4299 4300 return 0; 4301 } 4302 4303 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 4304 { 4305 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4306 4307 if (0 == data->need_update_smu7_dpm_table) 4308 return 0; 4309 4310 if ((0 == data->sclk_dpm_key_disabled) && 4311 (data->need_update_smu7_dpm_table & 4312 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 4313 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4314 "Trying to freeze SCLK DPM when DPM is disabled", 4315 ); 4316 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4317 PPSMC_MSG_SCLKDPM_FreezeLevel, 4318 NULL), 4319 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", 4320 return -EINVAL); 4321 } 4322 4323 if ((0 == data->mclk_dpm_key_disabled) && 4324 !data->mclk_ignore_signal && 4325 (data->need_update_smu7_dpm_table & 4326 DPMTABLE_OD_UPDATE_MCLK)) { 4327 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4328 "Trying to freeze MCLK DPM when DPM is disabled", 4329 ); 4330 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4331 PPSMC_MSG_MCLKDPM_FreezeLevel, 4332 NULL), 4333 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", 4334 return -EINVAL); 4335 } 4336 4337 return 0; 4338 } 4339 4340 static int smu7_populate_and_upload_sclk_mclk_dpm_levels( 4341 struct pp_hwmgr *hwmgr, const void *input) 4342 { 4343 int result = 0; 4344 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4345 struct smu7_dpm_table *dpm_table = &data->dpm_table; 4346 uint32_t count; 4347 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 4348 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); 4349 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); 4350 4351 if (0 == data->need_update_smu7_dpm_table) 4352 return 0; 4353 4354 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 4355 for (count = 0; count < dpm_table->sclk_table.count; count++) { 4356 dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled; 4357 dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock; 4358 } 4359 } 4360 4361 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 4362 for (count = 0; count < dpm_table->mclk_table.count; count++) { 4363 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; 4364 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; 4365 } 4366 } 4367 4368 if (data->need_update_smu7_dpm_table & 4369 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 4370 result = smum_populate_all_graphic_levels(hwmgr); 4371 PP_ASSERT_WITH_CODE((0 == result), 4372 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", 4373 return result); 4374 } 4375 4376 if (data->need_update_smu7_dpm_table & 4377 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 4378 /*populate MCLK dpm table to SMU7 */ 4379 result = smum_populate_all_memory_levels(hwmgr); 4380 PP_ASSERT_WITH_CODE((0 == result), 4381 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", 4382 return result); 4383 } 4384 4385 return result; 4386 } 4387 4388 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, 4389 struct smu7_single_dpm_table *dpm_table, 4390 uint32_t low_limit, uint32_t high_limit) 4391 { 4392 uint32_t i; 4393 4394 /* force the trim if mclk_switching is disabled to prevent flicker */ 4395 bool force_trim = (low_limit == high_limit); 4396 for (i = 0; i < dpm_table->count; i++) { 4397 /*skip the trim if od is enabled*/ 4398 if ((!hwmgr->od_enabled || force_trim) 4399 && (dpm_table->dpm_levels[i].value < low_limit 4400 || dpm_table->dpm_levels[i].value > high_limit)) 4401 dpm_table->dpm_levels[i].enabled = false; 4402 else 4403 dpm_table->dpm_levels[i].enabled = true; 4404 } 4405 4406 return 0; 4407 } 4408 4409 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr, 4410 const struct smu7_power_state *smu7_ps) 4411 { 4412 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4413 uint32_t high_limit_count; 4414 4415 PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1), 4416 "power state did not have any performance level", 4417 return -EINVAL); 4418 4419 high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1; 4420 4421 smu7_trim_single_dpm_states(hwmgr, 4422 &(data->dpm_table.sclk_table), 4423 smu7_ps->performance_levels[0].engine_clock, 4424 smu7_ps->performance_levels[high_limit_count].engine_clock); 4425 4426 smu7_trim_single_dpm_states(hwmgr, 4427 &(data->dpm_table.mclk_table), 4428 smu7_ps->performance_levels[0].memory_clock, 4429 smu7_ps->performance_levels[high_limit_count].memory_clock); 4430 4431 return 0; 4432 } 4433 4434 static int smu7_generate_dpm_level_enable_mask( 4435 struct pp_hwmgr *hwmgr, const void *input) 4436 { 4437 int result = 0; 4438 const struct phm_set_power_state_input *states = 4439 (const struct phm_set_power_state_input *)input; 4440 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4441 const struct smu7_power_state *smu7_ps = 4442 cast_const_phw_smu7_power_state(states->pnew_state); 4443 4444 4445 result = smu7_trim_dpm_states(hwmgr, smu7_ps); 4446 if (result) 4447 return result; 4448 4449 data->dpm_level_enable_mask.sclk_dpm_enable_mask = 4450 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); 4451 data->dpm_level_enable_mask.mclk_dpm_enable_mask = 4452 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); 4453 data->dpm_level_enable_mask.pcie_dpm_enable_mask = 4454 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); 4455 4456 return 0; 4457 } 4458 4459 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 4460 { 4461 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4462 4463 if (0 == data->need_update_smu7_dpm_table) 4464 return 0; 4465 4466 if ((0 == data->sclk_dpm_key_disabled) && 4467 (data->need_update_smu7_dpm_table & 4468 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 4469 4470 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4471 "Trying to Unfreeze SCLK DPM when DPM is disabled", 4472 ); 4473 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4474 PPSMC_MSG_SCLKDPM_UnfreezeLevel, 4475 NULL), 4476 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", 4477 return -EINVAL); 4478 } 4479 4480 if ((0 == data->mclk_dpm_key_disabled) && 4481 !data->mclk_ignore_signal && 4482 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 4483 4484 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4485 "Trying to Unfreeze MCLK DPM when DPM is disabled", 4486 ); 4487 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4488 PPSMC_MSG_MCLKDPM_UnfreezeLevel, 4489 NULL), 4490 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", 4491 return -EINVAL); 4492 } 4493 4494 data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; 4495 4496 return 0; 4497 } 4498 4499 static int smu7_notify_link_speed_change_after_state_change( 4500 struct pp_hwmgr *hwmgr, const void *input) 4501 { 4502 const struct phm_set_power_state_input *states = 4503 (const struct phm_set_power_state_input *)input; 4504 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4505 const struct smu7_power_state *smu7_ps = 4506 cast_const_phw_smu7_power_state(states->pnew_state); 4507 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps); 4508 uint8_t request; 4509 4510 if (data->pspp_notify_required) { 4511 if (target_link_speed == PP_PCIEGen3) 4512 request = PCIE_PERF_REQ_GEN3; 4513 else if (target_link_speed == PP_PCIEGen2) 4514 request = PCIE_PERF_REQ_GEN2; 4515 else 4516 request = PCIE_PERF_REQ_GEN1; 4517 4518 if (request == PCIE_PERF_REQ_GEN1 && 4519 smu7_get_current_pcie_speed(hwmgr) > 0) 4520 return 0; 4521 4522 #ifdef CONFIG_ACPI 4523 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) { 4524 if (PP_PCIEGen2 == target_link_speed) 4525 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!"); 4526 else 4527 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!"); 4528 } 4529 #endif 4530 } 4531 4532 return 0; 4533 } 4534 4535 static int smu7_notify_no_display(struct pp_hwmgr *hwmgr) 4536 { 4537 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL) == 0) ? 0 : -EINVAL; 4538 } 4539 4540 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr) 4541 { 4542 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4543 4544 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { 4545 if (hwmgr->chip_id == CHIP_VEGAM) 4546 smum_send_msg_to_smc_with_parameter(hwmgr, 4547 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2, 4548 NULL); 4549 else 4550 smum_send_msg_to_smc_with_parameter(hwmgr, 4551 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2, 4552 NULL); 4553 data->last_sent_vbi_timeout = data->frame_time_x2; 4554 } 4555 4556 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ? 0 : -EINVAL; 4557 } 4558 4559 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) 4560 { 4561 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4562 int result = 0; 4563 4564 if (data->mclk_ignore_signal) 4565 result = smu7_notify_no_display(hwmgr); 4566 else 4567 result = smu7_notify_has_display(hwmgr); 4568 4569 return result; 4570 } 4571 4572 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) 4573 { 4574 int tmp_result, result = 0; 4575 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4576 4577 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input); 4578 PP_ASSERT_WITH_CODE((0 == tmp_result), 4579 "Failed to find DPM states clocks in DPM table!", 4580 result = tmp_result); 4581 4582 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 4583 PHM_PlatformCaps_PCIEPerformanceRequest)) { 4584 tmp_result = 4585 smu7_request_link_speed_change_before_state_change(hwmgr, input); 4586 PP_ASSERT_WITH_CODE((0 == tmp_result), 4587 "Failed to request link speed change before state change!", 4588 result = tmp_result); 4589 } 4590 4591 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr); 4592 PP_ASSERT_WITH_CODE((0 == tmp_result), 4593 "Failed to freeze SCLK MCLK DPM!", result = tmp_result); 4594 4595 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); 4596 PP_ASSERT_WITH_CODE((0 == tmp_result), 4597 "Failed to populate and upload SCLK MCLK DPM levels!", 4598 result = tmp_result); 4599 4600 /* 4601 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. 4602 * That effectively disables AVFS feature. 4603 */ 4604 if (hwmgr->hardcode_pp_table != NULL) 4605 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 4606 4607 tmp_result = smu7_update_avfs(hwmgr); 4608 PP_ASSERT_WITH_CODE((0 == tmp_result), 4609 "Failed to update avfs voltages!", 4610 result = tmp_result); 4611 4612 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input); 4613 PP_ASSERT_WITH_CODE((0 == tmp_result), 4614 "Failed to generate DPM level enabled mask!", 4615 result = tmp_result); 4616 4617 tmp_result = smum_update_sclk_threshold(hwmgr); 4618 PP_ASSERT_WITH_CODE((0 == tmp_result), 4619 "Failed to update SCLK threshold!", 4620 result = tmp_result); 4621 4622 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr); 4623 PP_ASSERT_WITH_CODE((0 == tmp_result), 4624 "Failed to unfreeze SCLK MCLK DPM!", 4625 result = tmp_result); 4626 4627 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr); 4628 PP_ASSERT_WITH_CODE((0 == tmp_result), 4629 "Failed to upload DPM level enabled mask!", 4630 result = tmp_result); 4631 4632 tmp_result = smu7_notify_smc_display(hwmgr); 4633 PP_ASSERT_WITH_CODE((0 == tmp_result), 4634 "Failed to notify smc display settings!", 4635 result = tmp_result); 4636 4637 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 4638 PHM_PlatformCaps_PCIEPerformanceRequest)) { 4639 tmp_result = 4640 smu7_notify_link_speed_change_after_state_change(hwmgr, input); 4641 PP_ASSERT_WITH_CODE((0 == tmp_result), 4642 "Failed to notify link speed change after state change!", 4643 result = tmp_result); 4644 } 4645 data->apply_optimized_settings = false; 4646 return result; 4647 } 4648 4649 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) 4650 { 4651 hwmgr->thermal_controller. 4652 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; 4653 4654 return smum_send_msg_to_smc_with_parameter(hwmgr, 4655 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm, 4656 NULL); 4657 } 4658 4659 static int 4660 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) 4661 { 4662 return 0; 4663 } 4664 4665 /** 4666 * smu7_program_display_gap - Programs the display gap 4667 * 4668 * @hwmgr: the address of the powerplay hardware manager. 4669 * Return: always OK 4670 */ 4671 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) 4672 { 4673 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4674 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); 4675 uint32_t display_gap2; 4676 uint32_t pre_vbi_time_in_us; 4677 uint32_t frame_time_in_us; 4678 uint32_t ref_clock, refresh_rate; 4679 4680 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); 4681 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); 4682 4683 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 4684 refresh_rate = hwmgr->display_config->vrefresh; 4685 4686 if (0 == refresh_rate) 4687 refresh_rate = 60; 4688 4689 frame_time_in_us = 1000000 / refresh_rate; 4690 4691 pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time; 4692 4693 data->frame_time_x2 = frame_time_in_us * 2 / 100; 4694 4695 if (data->frame_time_x2 < 280) { 4696 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2); 4697 data->frame_time_x2 = 280; 4698 } 4699 4700 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); 4701 4702 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); 4703 4704 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4705 data->soft_regs_start + smum_get_offsetof(hwmgr, 4706 SMU_SoftRegisters, 4707 PreVBlankGap), 0x64); 4708 4709 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4710 data->soft_regs_start + smum_get_offsetof(hwmgr, 4711 SMU_SoftRegisters, 4712 VBlankTimeout), 4713 (frame_time_in_us - pre_vbi_time_in_us)); 4714 4715 return 0; 4716 } 4717 4718 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 4719 { 4720 return smu7_program_display_gap(hwmgr); 4721 } 4722 4723 /** 4724 * smu7_set_max_fan_rpm_output - Set maximum target operating fan output RPM 4725 * 4726 * @hwmgr: the address of the powerplay hardware manager. 4727 * @us_max_fan_rpm: max operating fan RPM value. 4728 * Return: The response that came from the SMC. 4729 */ 4730 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) 4731 { 4732 hwmgr->thermal_controller. 4733 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; 4734 4735 return smum_send_msg_to_smc_with_parameter(hwmgr, 4736 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm, 4737 NULL); 4738 } 4739 4740 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = { 4741 .process = phm_irq_process, 4742 }; 4743 4744 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr) 4745 { 4746 struct amdgpu_irq_src *source = 4747 kzalloc_obj(struct amdgpu_irq_src); 4748 4749 if (!source) 4750 return -ENOMEM; 4751 4752 source->funcs = &smu7_irq_funcs; 4753 4754 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4755 AMDGPU_IRQ_CLIENTID_LEGACY, 4756 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH, 4757 source); 4758 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4759 AMDGPU_IRQ_CLIENTID_LEGACY, 4760 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW, 4761 source); 4762 4763 /* Register CTF(GPIO_19) interrupt */ 4764 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4765 AMDGPU_IRQ_CLIENTID_LEGACY, 4766 VISLANDS30_IV_SRCID_GPIO_19, 4767 source); 4768 4769 return 0; 4770 } 4771 4772 static bool 4773 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 4774 { 4775 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4776 bool is_update_required = false; 4777 4778 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 4779 is_update_required = true; 4780 4781 if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh) 4782 is_update_required = true; 4783 4784 if (hwmgr->chip_id >= CHIP_POLARIS10 && 4785 hwmgr->chip_id <= CHIP_VEGAM && 4786 data->last_sent_vbi_timeout != data->frame_time_x2) 4787 is_update_required = true; 4788 4789 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { 4790 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr && 4791 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK || 4792 hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) 4793 is_update_required = true; 4794 } 4795 return is_update_required; 4796 } 4797 4798 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1, 4799 const struct smu7_performance_level *pl2) 4800 { 4801 return ((pl1->memory_clock == pl2->memory_clock) && 4802 (pl1->engine_clock == pl2->engine_clock) && 4803 (pl1->pcie_gen == pl2->pcie_gen) && 4804 (pl1->pcie_lane == pl2->pcie_lane)); 4805 } 4806 4807 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr, 4808 const struct pp_hw_power_state *pstate1, 4809 const struct pp_hw_power_state *pstate2, bool *equal) 4810 { 4811 const struct smu7_power_state *psa; 4812 const struct smu7_power_state *psb; 4813 int i; 4814 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4815 4816 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 4817 return -EINVAL; 4818 4819 psa = cast_const_phw_smu7_power_state(pstate1); 4820 psb = cast_const_phw_smu7_power_state(pstate2); 4821 /* If the two states don't even have the same number of performance levels they cannot be the same state. */ 4822 if (psa->performance_level_count != psb->performance_level_count) { 4823 *equal = false; 4824 return 0; 4825 } 4826 4827 for (i = 0; i < psa->performance_level_count; i++) { 4828 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { 4829 /* If we have found even one performance level pair that is different the states are different. */ 4830 *equal = false; 4831 return 0; 4832 } 4833 } 4834 4835 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 4836 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); 4837 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); 4838 *equal &= (psa->sclk_threshold == psb->sclk_threshold); 4839 /* For OD call, set value based on flag */ 4840 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | 4841 DPMTABLE_OD_UPDATE_MCLK | 4842 DPMTABLE_OD_UPDATE_VDDC)); 4843 4844 return 0; 4845 } 4846 4847 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr) 4848 { 4849 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4850 4851 uint32_t tmp; 4852 4853 /* Read MC indirect register offset 0x9F bits [3:0] to see 4854 * if VBIOS has already loaded a full version of MC ucode 4855 * or not. 4856 */ 4857 4858 smu7_get_mc_microcode_version(hwmgr); 4859 4860 data->need_long_memory_training = false; 4861 4862 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 4863 ixMC_IO_DEBUG_UP_13); 4864 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); 4865 4866 if (tmp & (1 << 23)) { 4867 data->mem_latency_high = MEM_LATENCY_HIGH; 4868 data->mem_latency_low = MEM_LATENCY_LOW; 4869 if ((hwmgr->chip_id == CHIP_POLARIS10) || 4870 (hwmgr->chip_id == CHIP_POLARIS11) || 4871 (hwmgr->chip_id == CHIP_POLARIS12)) 4872 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL); 4873 } else { 4874 data->mem_latency_high = 330; 4875 data->mem_latency_low = 330; 4876 if ((hwmgr->chip_id == CHIP_POLARIS10) || 4877 (hwmgr->chip_id == CHIP_POLARIS11) || 4878 (hwmgr->chip_id == CHIP_POLARIS12)) 4879 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL); 4880 } 4881 4882 return 0; 4883 } 4884 4885 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr) 4886 { 4887 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4888 4889 data->clock_registers.vCG_SPLL_FUNC_CNTL = 4890 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); 4891 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = 4892 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); 4893 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = 4894 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); 4895 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = 4896 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); 4897 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = 4898 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); 4899 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = 4900 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); 4901 data->clock_registers.vDLL_CNTL = 4902 cgs_read_register(hwmgr->device, mmDLL_CNTL); 4903 data->clock_registers.vMCLK_PWRMGT_CNTL = 4904 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); 4905 data->clock_registers.vMPLL_AD_FUNC_CNTL = 4906 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); 4907 data->clock_registers.vMPLL_DQ_FUNC_CNTL = 4908 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); 4909 data->clock_registers.vMPLL_FUNC_CNTL = 4910 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); 4911 data->clock_registers.vMPLL_FUNC_CNTL_1 = 4912 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); 4913 data->clock_registers.vMPLL_FUNC_CNTL_2 = 4914 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); 4915 data->clock_registers.vMPLL_SS1 = 4916 cgs_read_register(hwmgr->device, mmMPLL_SS1); 4917 data->clock_registers.vMPLL_SS2 = 4918 cgs_read_register(hwmgr->device, mmMPLL_SS2); 4919 return 0; 4920 4921 } 4922 4923 /** 4924 * smu7_get_memory_type - Find out if memory is GDDR5. 4925 * 4926 * @hwmgr: the address of the powerplay hardware manager. 4927 * Return: always 0 4928 */ 4929 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr) 4930 { 4931 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4932 struct amdgpu_device *adev = hwmgr->adev; 4933 4934 data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5); 4935 4936 return 0; 4937 } 4938 4939 /** 4940 * smu7_enable_acpi_power_management - Enables Dynamic Power Management by SMC 4941 * 4942 * @hwmgr: the address of the powerplay hardware manager. 4943 * Return: always 0 4944 */ 4945 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr) 4946 { 4947 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 4948 GENERAL_PWRMGT, STATIC_PM_EN, 1); 4949 4950 return 0; 4951 } 4952 4953 /** 4954 * smu7_init_power_gate_state - Initialize PowerGating States for different engines 4955 * 4956 * @hwmgr: the address of the powerplay hardware manager. 4957 * Return: always 0 4958 */ 4959 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr) 4960 { 4961 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4962 4963 data->uvd_power_gated = false; 4964 data->vce_power_gated = false; 4965 4966 return 0; 4967 } 4968 4969 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr) 4970 { 4971 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4972 4973 data->low_sclk_interrupt_threshold = 0; 4974 return 0; 4975 } 4976 4977 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) 4978 { 4979 int tmp_result, result = 0; 4980 4981 smu7_check_mc_firmware(hwmgr); 4982 4983 tmp_result = smu7_read_clock_registers(hwmgr); 4984 PP_ASSERT_WITH_CODE((0 == tmp_result), 4985 "Failed to read clock registers!", result = tmp_result); 4986 4987 tmp_result = smu7_get_memory_type(hwmgr); 4988 PP_ASSERT_WITH_CODE((0 == tmp_result), 4989 "Failed to get memory type!", result = tmp_result); 4990 4991 tmp_result = smu7_enable_acpi_power_management(hwmgr); 4992 PP_ASSERT_WITH_CODE((0 == tmp_result), 4993 "Failed to enable ACPI power management!", result = tmp_result); 4994 4995 tmp_result = smu7_init_power_gate_state(hwmgr); 4996 PP_ASSERT_WITH_CODE((0 == tmp_result), 4997 "Failed to init power gate state!", result = tmp_result); 4998 4999 tmp_result = smu7_get_mc_microcode_version(hwmgr); 5000 PP_ASSERT_WITH_CODE((0 == tmp_result), 5001 "Failed to get MC microcode version!", result = tmp_result); 5002 5003 tmp_result = smu7_init_sclk_threshold(hwmgr); 5004 PP_ASSERT_WITH_CODE((0 == tmp_result), 5005 "Failed to init sclk threshold!", result = tmp_result); 5006 5007 return result; 5008 } 5009 5010 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 5011 enum pp_clock_type type, uint32_t mask) 5012 { 5013 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5014 5015 if (mask == 0) 5016 return -EINVAL; 5017 5018 switch (type) { 5019 case PP_SCLK: 5020 if (!data->sclk_dpm_key_disabled) 5021 smum_send_msg_to_smc_with_parameter(hwmgr, 5022 PPSMC_MSG_SCLKDPM_SetEnabledMask, 5023 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask, 5024 NULL); 5025 break; 5026 case PP_MCLK: 5027 if (!data->mclk_dpm_key_disabled) 5028 smum_send_msg_to_smc_with_parameter(hwmgr, 5029 PPSMC_MSG_MCLKDPM_SetEnabledMask, 5030 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask, 5031 NULL); 5032 break; 5033 case PP_PCIE: 5034 { 5035 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; 5036 5037 if (!data->pcie_dpm_key_disabled) { 5038 if (fls(tmp) != ffs(tmp)) 5039 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel, 5040 NULL); 5041 else 5042 smum_send_msg_to_smc_with_parameter(hwmgr, 5043 PPSMC_MSG_PCIeDPM_ForceLevel, 5044 fls(tmp) - 1, 5045 NULL); 5046 } 5047 break; 5048 } 5049 default: 5050 break; 5051 } 5052 5053 return 0; 5054 } 5055 5056 static int smu7_emit_clock_levels(struct pp_hwmgr *hwmgr, 5057 enum pp_clock_type type, char *buf, 5058 int *offset) 5059 { 5060 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5061 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 5062 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 5063 struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); 5064 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 5065 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); 5066 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); 5067 int size = *offset, ret = 0; 5068 uint32_t i, now, clock, pcie_speed; 5069 5070 switch (type) { 5071 case PP_SCLK: 5072 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock); 5073 if (ret) 5074 return ret; 5075 for (i = 0; i < sclk_table->count; i++) { 5076 if (clock > sclk_table->dpm_levels[i].value) 5077 continue; 5078 break; 5079 } 5080 now = i; 5081 5082 for (i = 0; i < sclk_table->count; i++) 5083 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 5084 sclk_table->dpm_levels[i].value / 5085 100, 5086 (i == now) ? "*" : ""); 5087 break; 5088 case PP_MCLK: 5089 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock); 5090 if (ret) 5091 return ret; 5092 for (i = 0; i < mclk_table->count; i++) { 5093 if (clock > mclk_table->dpm_levels[i].value) 5094 continue; 5095 break; 5096 } 5097 now = i; 5098 5099 for (i = 0; i < mclk_table->count; i++) 5100 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, 5101 mclk_table->dpm_levels[i].value / 5102 100, 5103 (i == now) ? "*" : ""); 5104 break; 5105 case PP_PCIE: 5106 pcie_speed = smu7_get_current_pcie_speed(hwmgr); 5107 for (i = 0; i < pcie_table->count; i++) { 5108 if (pcie_speed != pcie_table->dpm_levels[i].value) 5109 continue; 5110 break; 5111 } 5112 now = i; 5113 5114 for (i = 0; i < pcie_table->count; i++) 5115 size += sysfs_emit_at( 5116 buf, size, "%d: %s %s\n", i, 5117 (pcie_table->dpm_levels[i].value == 0) ? 5118 "2.5GT/s, x8" : 5119 (pcie_table->dpm_levels[i].value == 1) ? 5120 "5.0GT/s, x16" : 5121 (pcie_table->dpm_levels[i].value == 2) ? 5122 "8.0GT/s, x16" : 5123 "", 5124 (i == now) ? "*" : ""); 5125 break; 5126 case OD_SCLK: 5127 if (hwmgr->od_enabled) { 5128 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 5129 for (i = 0; i < odn_sclk_table->num_of_pl; i++) 5130 size += sysfs_emit_at( 5131 buf, size, "%d: %10uMHz %10umV\n", i, 5132 odn_sclk_table->entries[i].clock / 100, 5133 odn_sclk_table->entries[i].vddc); 5134 } 5135 break; 5136 case OD_MCLK: 5137 if (hwmgr->od_enabled) { 5138 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); 5139 for (i = 0; i < odn_mclk_table->num_of_pl; i++) 5140 size += sysfs_emit_at( 5141 buf, size, "%d: %10uMHz %10umV\n", i, 5142 odn_mclk_table->entries[i].clock / 100, 5143 odn_mclk_table->entries[i].vddc); 5144 } 5145 break; 5146 case OD_RANGE: 5147 if (hwmgr->od_enabled) { 5148 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 5149 size += sysfs_emit_at( 5150 buf, size, "SCLK: %7uMHz %10uMHz\n", 5151 data->golden_dpm_table.sclk_table.dpm_levels[0] 5152 .value / 5153 100, 5154 hwmgr->platform_descriptor.overdriveLimit 5155 .engineClock / 5156 100); 5157 size += sysfs_emit_at( 5158 buf, size, "MCLK: %7uMHz %10uMHz\n", 5159 data->golden_dpm_table.mclk_table.dpm_levels[0] 5160 .value / 5161 100, 5162 hwmgr->platform_descriptor.overdriveLimit 5163 .memoryClock / 5164 100); 5165 size += sysfs_emit_at(buf, size, "VDDC: %7umV %11umV\n", 5166 data->odn_dpm_table.min_vddc, 5167 data->odn_dpm_table.max_vddc); 5168 } 5169 break; 5170 default: 5171 break; 5172 } 5173 5174 *offset = size; 5175 5176 return 0; 5177 } 5178 5179 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 5180 { 5181 switch (mode) { 5182 case AMD_FAN_CTRL_NONE: 5183 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 5184 break; 5185 case AMD_FAN_CTRL_MANUAL: 5186 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 5187 PHM_PlatformCaps_MicrocodeFanControl)) 5188 smu7_fan_ctrl_stop_smc_fan_control(hwmgr); 5189 break; 5190 case AMD_FAN_CTRL_AUTO: 5191 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode)) 5192 smu7_fan_ctrl_start_smc_fan_control(hwmgr); 5193 break; 5194 default: 5195 break; 5196 } 5197 } 5198 5199 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) 5200 { 5201 return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL; 5202 } 5203 5204 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr) 5205 { 5206 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5207 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 5208 struct smu7_single_dpm_table *golden_sclk_table = 5209 &(data->golden_dpm_table.sclk_table); 5210 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 5211 int golden_value = golden_sclk_table->dpm_levels 5212 [golden_sclk_table->count - 1].value; 5213 5214 value -= golden_value; 5215 value = DIV_ROUND_UP(value * 100, golden_value); 5216 5217 return value; 5218 } 5219 5220 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5221 { 5222 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5223 struct smu7_single_dpm_table *golden_sclk_table = 5224 &(data->golden_dpm_table.sclk_table); 5225 struct pp_power_state *ps; 5226 struct smu7_power_state *smu7_ps; 5227 5228 if (value > 20) 5229 value = 20; 5230 5231 ps = hwmgr->request_ps; 5232 5233 if (ps == NULL) 5234 return -EINVAL; 5235 5236 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 5237 5238 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock = 5239 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * 5240 value / 100 + 5241 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; 5242 5243 return 0; 5244 } 5245 5246 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr) 5247 { 5248 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5249 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 5250 struct smu7_single_dpm_table *golden_mclk_table = 5251 &(data->golden_dpm_table.mclk_table); 5252 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 5253 int golden_value = golden_mclk_table->dpm_levels 5254 [golden_mclk_table->count - 1].value; 5255 5256 value -= golden_value; 5257 value = DIV_ROUND_UP(value * 100, golden_value); 5258 5259 return value; 5260 } 5261 5262 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5263 { 5264 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5265 struct smu7_single_dpm_table *golden_mclk_table = 5266 &(data->golden_dpm_table.mclk_table); 5267 struct pp_power_state *ps; 5268 struct smu7_power_state *smu7_ps; 5269 5270 if (value > 20) 5271 value = 20; 5272 5273 ps = hwmgr->request_ps; 5274 5275 if (ps == NULL) 5276 return -EINVAL; 5277 5278 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 5279 5280 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock = 5281 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * 5282 value / 100 + 5283 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; 5284 5285 return 0; 5286 } 5287 5288 5289 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 5290 { 5291 struct phm_ppt_v1_information *table_info = 5292 (struct phm_ppt_v1_information *)hwmgr->pptable; 5293 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; 5294 struct phm_clock_voltage_dependency_table *sclk_table; 5295 int i; 5296 5297 if (hwmgr->pp_table_version == PP_TABLE_V1) { 5298 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) 5299 return -EINVAL; 5300 dep_sclk_table = table_info->vdd_dep_on_sclk; 5301 for (i = 0; i < dep_sclk_table->count; i++) 5302 clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; 5303 clocks->count = dep_sclk_table->count; 5304 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 5305 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 5306 for (i = 0; i < sclk_table->count; i++) 5307 clocks->clock[i] = sclk_table->entries[i].clk * 10; 5308 clocks->count = sclk_table->count; 5309 } 5310 5311 return 0; 5312 } 5313 5314 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk) 5315 { 5316 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5317 5318 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY) 5319 return data->mem_latency_high; 5320 else if (clk >= MEM_FREQ_HIGH_LATENCY) 5321 return data->mem_latency_low; 5322 else 5323 return MEM_LATENCY_ERR; 5324 } 5325 5326 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 5327 { 5328 struct phm_ppt_v1_information *table_info = 5329 (struct phm_ppt_v1_information *)hwmgr->pptable; 5330 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 5331 int i; 5332 struct phm_clock_voltage_dependency_table *mclk_table; 5333 5334 if (hwmgr->pp_table_version == PP_TABLE_V1) { 5335 if (table_info == NULL) 5336 return -EINVAL; 5337 dep_mclk_table = table_info->vdd_dep_on_mclk; 5338 for (i = 0; i < dep_mclk_table->count; i++) { 5339 clocks->clock[i] = dep_mclk_table->entries[i].clk * 10; 5340 clocks->latency[i] = smu7_get_mem_latency(hwmgr, 5341 dep_mclk_table->entries[i].clk); 5342 } 5343 clocks->count = dep_mclk_table->count; 5344 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 5345 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 5346 for (i = 0; i < mclk_table->count; i++) 5347 clocks->clock[i] = mclk_table->entries[i].clk * 10; 5348 clocks->count = mclk_table->count; 5349 } 5350 return 0; 5351 } 5352 5353 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, 5354 struct amd_pp_clocks *clocks) 5355 { 5356 switch (type) { 5357 case amd_pp_sys_clock: 5358 smu7_get_sclks(hwmgr, clocks); 5359 break; 5360 case amd_pp_mem_clock: 5361 smu7_get_mclks(hwmgr, clocks); 5362 break; 5363 default: 5364 return -EINVAL; 5365 } 5366 5367 return 0; 5368 } 5369 5370 static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr, 5371 struct pp_clock_levels_with_latency *clocks) 5372 { 5373 struct phm_ppt_v1_information *table_info = 5374 (struct phm_ppt_v1_information *)hwmgr->pptable; 5375 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = 5376 table_info->vdd_dep_on_sclk; 5377 int i; 5378 5379 clocks->num_levels = 0; 5380 for (i = 0; i < dep_sclk_table->count; i++) { 5381 if (dep_sclk_table->entries[i].clk) { 5382 clocks->data[clocks->num_levels].clocks_in_khz = 5383 dep_sclk_table->entries[i].clk * 10; 5384 clocks->num_levels++; 5385 } 5386 } 5387 5388 return 0; 5389 } 5390 5391 static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr, 5392 struct pp_clock_levels_with_latency *clocks) 5393 { 5394 struct phm_ppt_v1_information *table_info = 5395 (struct phm_ppt_v1_information *)hwmgr->pptable; 5396 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 5397 table_info->vdd_dep_on_mclk; 5398 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5399 int i; 5400 5401 clocks->num_levels = 0; 5402 data->mclk_latency_table.count = 0; 5403 for (i = 0; i < dep_mclk_table->count; i++) { 5404 if (dep_mclk_table->entries[i].clk) { 5405 clocks->data[clocks->num_levels].clocks_in_khz = 5406 dep_mclk_table->entries[i].clk * 10; 5407 data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency = 5408 dep_mclk_table->entries[i].clk; 5409 clocks->data[clocks->num_levels].latency_in_us = 5410 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency = 5411 smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk); 5412 clocks->num_levels++; 5413 data->mclk_latency_table.count++; 5414 } 5415 } 5416 5417 return 0; 5418 } 5419 5420 static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 5421 enum amd_pp_clock_type type, 5422 struct pp_clock_levels_with_latency *clocks) 5423 { 5424 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 5425 hwmgr->chip_id <= CHIP_VEGAM)) 5426 return -EINVAL; 5427 5428 switch (type) { 5429 case amd_pp_sys_clock: 5430 smu7_get_sclks_with_latency(hwmgr, clocks); 5431 break; 5432 case amd_pp_mem_clock: 5433 smu7_get_mclks_with_latency(hwmgr, clocks); 5434 break; 5435 default: 5436 return -EINVAL; 5437 } 5438 5439 return 0; 5440 } 5441 5442 static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 5443 void *clock_range) 5444 { 5445 struct phm_ppt_v1_information *table_info = 5446 (struct phm_ppt_v1_information *)hwmgr->pptable; 5447 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 5448 table_info->vdd_dep_on_mclk; 5449 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = 5450 table_info->vdd_dep_on_sclk; 5451 struct polaris10_smumgr *smu_data = 5452 (struct polaris10_smumgr *)(hwmgr->smu_backend); 5453 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 5454 struct dm_pp_wm_sets_with_clock_ranges *watermarks = 5455 (struct dm_pp_wm_sets_with_clock_ranges *)clock_range; 5456 uint32_t i, j, k; 5457 bool valid_entry; 5458 5459 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 5460 hwmgr->chip_id <= CHIP_VEGAM)) 5461 return -EINVAL; 5462 5463 for (i = 0; i < dep_mclk_table->count; i++) { 5464 for (j = 0; j < dep_sclk_table->count; j++) { 5465 valid_entry = false; 5466 for (k = 0; k < watermarks->num_wm_sets; k++) { 5467 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && 5468 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && 5469 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && 5470 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { 5471 valid_entry = true; 5472 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id; 5473 break; 5474 } 5475 } 5476 PP_ASSERT_WITH_CODE(valid_entry, 5477 "Clock is not in range of specified clock range for watermark from DAL! Using highest water mark set.", 5478 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id); 5479 } 5480 } 5481 5482 return smu7_copy_bytes_to_smc(hwmgr, 5483 smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, DisplayWatermark), 5484 (uint8_t *)table->DisplayWatermark, 5485 sizeof(uint8_t) * SMU74_MAX_LEVELS_MEMORY * SMU74_MAX_LEVELS_GRAPHICS, 5486 SMC_RAM_END); 5487 } 5488 5489 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 5490 uint32_t virtual_addr_low, 5491 uint32_t virtual_addr_hi, 5492 uint32_t mc_addr_low, 5493 uint32_t mc_addr_hi, 5494 uint32_t size) 5495 { 5496 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5497 5498 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5499 data->soft_regs_start + 5500 smum_get_offsetof(hwmgr, 5501 SMU_SoftRegisters, DRAM_LOG_ADDR_H), 5502 mc_addr_hi); 5503 5504 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5505 data->soft_regs_start + 5506 smum_get_offsetof(hwmgr, 5507 SMU_SoftRegisters, DRAM_LOG_ADDR_L), 5508 mc_addr_low); 5509 5510 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5511 data->soft_regs_start + 5512 smum_get_offsetof(hwmgr, 5513 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H), 5514 virtual_addr_hi); 5515 5516 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5517 data->soft_regs_start + 5518 smum_get_offsetof(hwmgr, 5519 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L), 5520 virtual_addr_low); 5521 5522 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5523 data->soft_regs_start + 5524 smum_get_offsetof(hwmgr, 5525 SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE), 5526 size); 5527 return 0; 5528 } 5529 5530 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr, 5531 struct amd_pp_simple_clock_info *clocks) 5532 { 5533 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5534 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 5535 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 5536 5537 if (clocks == NULL) 5538 return -EINVAL; 5539 5540 clocks->memory_max_clock = mclk_table->count > 1 ? 5541 mclk_table->dpm_levels[mclk_table->count-1].value : 5542 mclk_table->dpm_levels[0].value; 5543 clocks->engine_max_clock = sclk_table->count > 1 ? 5544 sclk_table->dpm_levels[sclk_table->count-1].value : 5545 sclk_table->dpm_levels[0].value; 5546 return 0; 5547 } 5548 5549 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 5550 struct PP_TemperatureRange *thermal_data) 5551 { 5552 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5553 struct phm_ppt_v1_information *table_info = 5554 (struct phm_ppt_v1_information *)hwmgr->pptable; 5555 5556 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange)); 5557 5558 if (hwmgr->pp_table_version == PP_TABLE_V1) 5559 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp * 5560 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5561 else if (hwmgr->pp_table_version == PP_TABLE_V0) 5562 thermal_data->max = data->thermal_temp_setting.temperature_shutdown; 5563 5564 thermal_data->sw_ctf_threshold = thermal_data->max; 5565 5566 return 0; 5567 } 5568 5569 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, 5570 enum PP_OD_DPM_TABLE_COMMAND type, 5571 uint32_t clk, 5572 uint32_t voltage) 5573 { 5574 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5575 5576 if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) { 5577 pr_info("OD voltage is out of range [%d - %d] mV\n", 5578 data->odn_dpm_table.min_vddc, 5579 data->odn_dpm_table.max_vddc); 5580 return false; 5581 } 5582 5583 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5584 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk || 5585 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { 5586 pr_info("OD engine clock is out of range [%d - %d] MHz\n", 5587 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, 5588 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5589 return false; 5590 } 5591 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5592 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk || 5593 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { 5594 pr_info("OD memory clock is out of range [%d - %d] MHz\n", 5595 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, 5596 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5597 return false; 5598 } 5599 } else { 5600 return false; 5601 } 5602 5603 return true; 5604 } 5605 5606 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 5607 enum PP_OD_DPM_TABLE_COMMAND type, 5608 long *input, uint32_t size) 5609 { 5610 uint32_t i; 5611 struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL; 5612 struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL; 5613 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5614 5615 uint32_t input_clk; 5616 uint32_t input_vol; 5617 uint32_t input_level; 5618 5619 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 5620 return -EINVAL); 5621 5622 if (!hwmgr->od_enabled) { 5623 pr_info("OverDrive feature not enabled\n"); 5624 return -EINVAL; 5625 } 5626 5627 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { 5628 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels; 5629 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk; 5630 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), 5631 "Failed to get ODN SCLK and Voltage tables", 5632 return -EINVAL); 5633 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { 5634 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels; 5635 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk; 5636 5637 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), 5638 "Failed to get ODN MCLK and Voltage tables", 5639 return -EINVAL); 5640 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { 5641 smu7_odn_initial_default_setting(hwmgr); 5642 return 0; 5643 } else if (PP_OD_COMMIT_DPM_TABLE == type) { 5644 smu7_check_dpm_table_updated(hwmgr); 5645 return 0; 5646 } else { 5647 return -EINVAL; 5648 } 5649 5650 for (i = 0; i < size; i += 3) { 5651 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) { 5652 pr_info("invalid clock voltage input \n"); 5653 return 0; 5654 } 5655 input_level = input[i]; 5656 input_clk = input[i+1] * 100; 5657 input_vol = input[i+2]; 5658 5659 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { 5660 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; 5661 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; 5662 podn_dpm_table_in_backend->entries[input_level].vddc = input_vol; 5663 podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol; 5664 podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol; 5665 } else { 5666 return -EINVAL; 5667 } 5668 } 5669 5670 return 0; 5671 } 5672 5673 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 5674 { 5675 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5676 uint32_t i, size = 0; 5677 uint32_t len; 5678 5679 static const char *title[8] = {"NUM", 5680 "MODE_NAME", 5681 "SCLK_UP_HYST", 5682 "SCLK_DOWN_HYST", 5683 "SCLK_ACTIVE_LEVEL", 5684 "MCLK_UP_HYST", 5685 "MCLK_DOWN_HYST", 5686 "MCLK_ACTIVE_LEVEL"}; 5687 5688 if (!buf) 5689 return -EINVAL; 5690 5691 phm_get_sysfs_buf(&buf, &size); 5692 5693 size += sysfs_emit_at(buf, size, "%s %16s %16s %16s %16s %16s %16s %16s\n", 5694 title[0], title[1], title[2], title[3], 5695 title[4], title[5], title[6], title[7]); 5696 5697 len = ARRAY_SIZE(smu7_profiling); 5698 5699 for (i = 0; i < len; i++) { 5700 if (i == hwmgr->power_profile_mode) { 5701 size += sysfs_emit_at(buf, size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n", 5702 i, amdgpu_pp_profile_name[i], "*", 5703 data->current_profile_setting.sclk_up_hyst, 5704 data->current_profile_setting.sclk_down_hyst, 5705 data->current_profile_setting.sclk_activity, 5706 data->current_profile_setting.mclk_up_hyst, 5707 data->current_profile_setting.mclk_down_hyst, 5708 data->current_profile_setting.mclk_activity); 5709 continue; 5710 } 5711 if (smu7_profiling[i].bupdate_sclk) 5712 size += sysfs_emit_at(buf, size, "%3d %16s: %8d %16d %16d ", 5713 i, amdgpu_pp_profile_name[i], smu7_profiling[i].sclk_up_hyst, 5714 smu7_profiling[i].sclk_down_hyst, 5715 smu7_profiling[i].sclk_activity); 5716 else 5717 size += sysfs_emit_at(buf, size, "%3d %16s: %8s %16s %16s ", 5718 i, amdgpu_pp_profile_name[i], "-", "-", "-"); 5719 5720 if (smu7_profiling[i].bupdate_mclk) 5721 size += sysfs_emit_at(buf, size, "%16d %16d %16d\n", 5722 smu7_profiling[i].mclk_up_hyst, 5723 smu7_profiling[i].mclk_down_hyst, 5724 smu7_profiling[i].mclk_activity); 5725 else 5726 size += sysfs_emit_at(buf, size, "%16s %16s %16s\n", 5727 "-", "-", "-"); 5728 } 5729 5730 return size; 5731 } 5732 5733 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr, 5734 enum PP_SMC_POWER_PROFILE requst) 5735 { 5736 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5737 uint32_t tmp, level; 5738 5739 if (requst == PP_SMC_POWER_PROFILE_COMPUTE) { 5740 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 5741 level = 0; 5742 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; 5743 while (tmp >>= 1) 5744 level++; 5745 if (level > 0) 5746 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); 5747 } 5748 } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) { 5749 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); 5750 } 5751 } 5752 5753 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 5754 { 5755 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5756 struct profile_mode_setting tmp; 5757 enum PP_SMC_POWER_PROFILE mode; 5758 5759 if (input == NULL) 5760 return -EINVAL; 5761 5762 mode = input[size]; 5763 switch (mode) { 5764 case PP_SMC_POWER_PROFILE_CUSTOM: 5765 if (size != 8 && size != 0) 5766 return -EINVAL; 5767 /* If only CUSTOM is passed in, use the saved values. Check 5768 * that we actually have a CUSTOM profile by ensuring that 5769 * the "use sclk" or the "use mclk" bits are set 5770 */ 5771 tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM]; 5772 if (size == 0) { 5773 if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0) 5774 return -EINVAL; 5775 } else { 5776 tmp.bupdate_sclk = input[0]; 5777 tmp.sclk_up_hyst = input[1]; 5778 tmp.sclk_down_hyst = input[2]; 5779 tmp.sclk_activity = input[3]; 5780 tmp.bupdate_mclk = input[4]; 5781 tmp.mclk_up_hyst = input[5]; 5782 tmp.mclk_down_hyst = input[6]; 5783 tmp.mclk_activity = input[7]; 5784 smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp; 5785 } 5786 if (!smum_update_dpm_settings(hwmgr, &tmp)) { 5787 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting)); 5788 hwmgr->power_profile_mode = mode; 5789 } 5790 break; 5791 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 5792 case PP_SMC_POWER_PROFILE_POWERSAVING: 5793 case PP_SMC_POWER_PROFILE_VIDEO: 5794 case PP_SMC_POWER_PROFILE_VR: 5795 case PP_SMC_POWER_PROFILE_COMPUTE: 5796 if (mode == hwmgr->power_profile_mode) 5797 return 0; 5798 5799 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting)); 5800 if (!smum_update_dpm_settings(hwmgr, &tmp)) { 5801 if (tmp.bupdate_sclk) { 5802 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk; 5803 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst; 5804 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst; 5805 data->current_profile_setting.sclk_activity = tmp.sclk_activity; 5806 } 5807 if (tmp.bupdate_mclk) { 5808 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk; 5809 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst; 5810 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst; 5811 data->current_profile_setting.mclk_activity = tmp.mclk_activity; 5812 } 5813 smu7_patch_compute_profile_mode(hwmgr, mode); 5814 hwmgr->power_profile_mode = mode; 5815 } 5816 break; 5817 default: 5818 return -EINVAL; 5819 } 5820 5821 return 0; 5822 } 5823 5824 static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 5825 PHM_PerformanceLevelDesignation designation, uint32_t index, 5826 PHM_PerformanceLevel *level) 5827 { 5828 const struct smu7_power_state *ps; 5829 uint32_t i; 5830 5831 if (level == NULL || hwmgr == NULL || state == NULL) 5832 return -EINVAL; 5833 5834 ps = cast_const_phw_smu7_power_state(state); 5835 5836 i = index > ps->performance_level_count - 1 ? 5837 ps->performance_level_count - 1 : index; 5838 5839 level->coreClock = ps->performance_levels[i].engine_clock; 5840 level->memory_clock = ps->performance_levels[i].memory_clock; 5841 5842 return 0; 5843 } 5844 5845 static int smu7_power_off_asic(struct pp_hwmgr *hwmgr) 5846 { 5847 int result; 5848 5849 result = smu7_disable_dpm_tasks(hwmgr); 5850 PP_ASSERT_WITH_CODE((0 == result), 5851 "[disable_dpm_tasks] Failed to disable DPM!", 5852 ); 5853 5854 return result; 5855 } 5856 5857 static void smu7_notify_ac_dc(struct pp_hwmgr *hwmgr) 5858 { 5859 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 5860 5861 /* Check if the platform already manages the AC/DC switch via dedicated GPIO. */ 5862 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 5863 PHM_PlatformCaps_AutomaticDCTransition)) 5864 return; 5865 5866 /* The SMU automatically notices DC, but needs to be notified when switching to AC. */ 5867 if (adev->pm.ac_power) 5868 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunningOnAC, NULL); 5869 } 5870 5871 static const struct pp_hwmgr_func smu7_hwmgr_funcs = { 5872 .backend_init = &smu7_hwmgr_backend_init, 5873 .backend_fini = &smu7_hwmgr_backend_fini, 5874 .asic_setup = &smu7_setup_asic_task, 5875 .dynamic_state_management_enable = &smu7_enable_dpm_tasks, 5876 .apply_state_adjust_rules = smu7_apply_state_adjust_rules, 5877 .force_dpm_level = &smu7_force_dpm_level, 5878 .power_state_set = smu7_set_power_state_tasks, 5879 .get_power_state_size = smu7_get_power_state_size, 5880 .get_mclk = smu7_dpm_get_mclk, 5881 .get_sclk = smu7_dpm_get_sclk, 5882 .patch_boot_state = smu7_dpm_patch_boot_state, 5883 .get_pp_table_entry = smu7_get_pp_table_entry, 5884 .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries, 5885 .powergate_uvd = smu7_powergate_uvd, 5886 .powergate_vce = smu7_powergate_vce, 5887 .disable_clock_power_gating = smu7_disable_clock_power_gating, 5888 .update_clock_gatings = smu7_update_clock_gatings, 5889 .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment, 5890 .display_config_changed = smu7_display_configuration_changed_task, 5891 .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output, 5892 .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output, 5893 .stop_thermal_controller = smu7_thermal_stop_thermal_controller, 5894 .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info, 5895 .get_fan_speed_pwm = smu7_fan_ctrl_get_fan_speed_pwm, 5896 .set_fan_speed_pwm = smu7_fan_ctrl_set_fan_speed_pwm, 5897 .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default, 5898 .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm, 5899 .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm, 5900 .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller, 5901 .register_irq_handlers = smu7_register_irq_handlers, 5902 .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration, 5903 .check_states_equal = smu7_check_states_equal, 5904 .set_fan_control_mode = smu7_set_fan_control_mode, 5905 .get_fan_control_mode = smu7_get_fan_control_mode, 5906 .force_clock_level = smu7_force_clock_level, 5907 .emit_clock_levels = smu7_emit_clock_levels, 5908 .powergate_gfx = smu7_powergate_gfx, 5909 .get_sclk_od = smu7_get_sclk_od, 5910 .set_sclk_od = smu7_set_sclk_od, 5911 .get_mclk_od = smu7_get_mclk_od, 5912 .set_mclk_od = smu7_set_mclk_od, 5913 .get_clock_by_type = smu7_get_clock_by_type, 5914 .get_clock_by_type_with_latency = smu7_get_clock_by_type_with_latency, 5915 .set_watermarks_for_clocks_ranges = smu7_set_watermarks_for_clocks_ranges, 5916 .read_sensor = smu7_read_sensor, 5917 .dynamic_state_management_disable = smu7_disable_dpm_tasks, 5918 .avfs_control = smu7_avfs_control, 5919 .disable_smc_firmware_ctf = smu7_thermal_disable_alert, 5920 .start_thermal_controller = smu7_start_thermal_controller, 5921 .notify_cac_buffer_info = smu7_notify_cac_buffer_info, 5922 .get_max_high_clocks = smu7_get_max_high_clocks, 5923 .get_thermal_temperature_range = smu7_get_thermal_temperature_range, 5924 .odn_edit_dpm_table = smu7_odn_edit_dpm_table, 5925 .set_power_limit = smu7_set_power_limit, 5926 .get_power_profile_mode = smu7_get_power_profile_mode, 5927 .set_power_profile_mode = smu7_set_power_profile_mode, 5928 .get_performance_level = smu7_get_performance_level, 5929 .get_bamaco_support = smu7_get_bamaco_support, 5930 .get_asic_baco_state = smu7_baco_get_state, 5931 .set_asic_baco_state = smu7_baco_set_state, 5932 .power_off_asic = smu7_power_off_asic, 5933 .notify_ac_dc = smu7_notify_ac_dc, 5934 }; 5935 5936 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 5937 uint32_t clock_insr) 5938 { 5939 uint8_t i; 5940 uint32_t temp; 5941 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK); 5942 5943 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0); 5944 for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 5945 temp = clock >> i; 5946 5947 if (temp >= min || i == 0) 5948 break; 5949 } 5950 return i; 5951 } 5952 5953 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr) 5954 { 5955 hwmgr->hwmgr_func = &smu7_hwmgr_funcs; 5956 if (hwmgr->pp_table_version == PP_TABLE_V0) 5957 hwmgr->pptable_func = &pptable_funcs; 5958 else if (hwmgr->pp_table_version == PP_TABLE_V1) 5959 hwmgr->pptable_func = &pptable_v1_0_funcs; 5960 5961 return 0; 5962 } 5963