1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3 * Copyright (c) 2020, MIPI Alliance, Inc.
4 *
5 * Author: Nicolas Pitre <npitre@baylibre.com>
6 *
7 * Common HCI stuff
8 */
9
10 #ifndef HCI_H
11 #define HCI_H
12
13 #include <linux/io.h>
14
15 /* 32-bit word aware bit and mask macros */
16 #define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0)
17 #define W1_MASK(h, l) GENMASK((h) - 32, (l) - 32)
18 #define W2_MASK(h, l) GENMASK((h) - 64, (l) - 64)
19 #define W3_MASK(h, l) GENMASK((h) - 96, (l) - 96)
20
21 /* Same for single bit macros (trailing _ to align with W*_MASK width) */
22 #define W0_BIT_(x) BIT((x) - 0)
23 #define W1_BIT_(x) BIT((x) - 32)
24 #define W2_BIT_(x) BIT((x) - 64)
25 #define W3_BIT_(x) BIT((x) - 96)
26
27 #define reg_read(r) readl(hci->base_regs + (r))
28 #define reg_write(r, v) writel(v, hci->base_regs + (r))
29 #define reg_set(r, v) reg_write(r, reg_read(r) | (v))
30 #define reg_clear(r, v) reg_write(r, reg_read(r) & ~(v))
31
32 struct hci_cmd_ops;
33
34 struct dat_words {
35 u32 w0;
36 u32 w1;
37 };
38
39 /* Our main structure */
40 struct i3c_hci {
41 struct i3c_master_controller master;
42 void __iomem *base_regs;
43 void __iomem *DAT_regs;
44 void __iomem *DCT_regs;
45 void __iomem *RHS_regs;
46 void __iomem *PIO_regs;
47 void __iomem *EXTCAPS_regs;
48 void __iomem *AUTOCMD_regs;
49 void __iomem *DEBUG_regs;
50 const struct hci_io_ops *io;
51 void *io_data;
52 const struct hci_cmd_ops *cmd;
53 atomic_t next_cmd_tid;
54 bool irq_inactive;
55 u32 caps;
56 unsigned int quirks;
57 unsigned int DAT_entries;
58 unsigned int DAT_entry_size;
59 void *DAT_data;
60 struct dat_words *DAT;
61 unsigned int DCT_entries;
62 unsigned int DCT_entry_size;
63 u8 version_major;
64 u8 version_minor;
65 u8 revision;
66 u8 dyn_addr;
67 u32 vendor_mipi_id;
68 u32 vendor_version_id;
69 u32 vendor_product_id;
70 void *vendor_data;
71 };
72
73 /*
74 * Structure to represent a master initiated transfer.
75 * The rnw, data and data_len fields must be initialized before calling any
76 * hci->cmd->*() method. The cmd method will initialize cmd_desc[] and
77 * possibly modify (clear) the data field. Then xfer->cmd_desc[0] can
78 * be augmented with CMD_0_ROC and/or CMD_0_TOC.
79 * The completion field needs to be initialized before queueing with
80 * hci->io->queue_xfer(), and requires CMD_0_ROC to be set.
81 */
82 struct hci_xfer {
83 u32 cmd_desc[4];
84 u32 response;
85 bool rnw;
86 void *data;
87 unsigned int data_len;
88 unsigned int cmd_tid;
89 struct completion *completion;
90 union {
91 struct {
92 /* PIO specific */
93 struct hci_xfer *next_xfer;
94 struct hci_xfer *next_data;
95 struct hci_xfer *next_resp;
96 unsigned int data_left;
97 u32 data_word_before_partial;
98 };
99 struct {
100 /* DMA specific */
101 struct i3c_dma *dma;
102 int ring_number;
103 int ring_entry;
104 };
105 };
106 };
107
hci_alloc_xfer(unsigned int n)108 static inline struct hci_xfer *hci_alloc_xfer(unsigned int n)
109 {
110 return kzalloc_objs(struct hci_xfer, n);
111 }
112
hci_free_xfer(struct hci_xfer * xfer,unsigned int n)113 static inline void hci_free_xfer(struct hci_xfer *xfer, unsigned int n)
114 {
115 kfree(xfer);
116 }
117
118 /* This abstracts PIO vs DMA operations */
119 struct hci_io_ops {
120 bool (*irq_handler)(struct i3c_hci *hci);
121 int (*queue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
122 bool (*dequeue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
123 int (*request_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
124 const struct i3c_ibi_setup *req);
125 void (*free_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev);
126 void (*recycle_ibi_slot)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
127 struct i3c_ibi_slot *slot);
128 int (*init)(struct i3c_hci *hci);
129 void (*cleanup)(struct i3c_hci *hci);
130 void (*suspend)(struct i3c_hci *hci);
131 void (*resume)(struct i3c_hci *hci);
132 };
133
134 extern const struct hci_io_ops mipi_i3c_hci_pio;
135 extern const struct hci_io_ops mipi_i3c_hci_dma;
136
137 /* Our per device master private data */
138 struct i3c_hci_dev_data {
139 int dat_idx;
140 void *ibi_data;
141 };
142
143 /* list of quirks */
144 #define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */
145 #define HCI_QUIRK_PIO_MODE BIT(2) /* Set PIO mode for AMD platforms */
146 #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD platforms */
147 #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD platforms */
148 #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */
149
150 /* global functions */
151 void mipi_i3c_hci_resume(struct i3c_hci *hci);
152 void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
153 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
154 void amd_set_od_pp_timing(struct i3c_hci *hci);
155 void amd_set_resp_buf_thld(struct i3c_hci *hci);
156 void i3c_hci_sync_irq_inactive(struct i3c_hci *hci);
157
158 #endif
159