1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2017 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/ctype.h>
13 #include <linux/stringify.h>
14 #include <linux/ethtool.h>
15 #include <linux/ethtool_netlink.h>
16 #include <linux/linkmode.h>
17 #include <linux/interrupt.h>
18 #include <linux/pci.h>
19 #include <linux/etherdevice.h>
20 #include <linux/crc32.h>
21 #include <linux/firmware.h>
22 #include <linux/utsname.h>
23 #include <linux/time.h>
24 #include <linux/ptp_clock_kernel.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/timecounter.h>
27 #include <net/netdev_queues.h>
28 #include <net/netlink.h>
29 #include <linux/bnxt/hsi.h>
30 #include <linux/bnxt/ulp.h>
31 #include "bnxt.h"
32 #include "bnxt_hwrm.h"
33 #include "bnxt_xdp.h"
34 #include "bnxt_ptp.h"
35 #include "bnxt_ethtool.h"
36 #include "bnxt_gso.h"
37 #include "bnxt_nvm_defs.h" /* NVRAM content constant and structure defs */
38 #include "bnxt_fw_hdr.h" /* Firmware hdr constant and structure defs */
39 #include "bnxt_coredump.h"
40
41 #define BNXT_NVM_ERR_MSG(dev, extack, msg) \
42 do { \
43 if (extack) \
44 NL_SET_ERR_MSG_MOD(extack, msg); \
45 netdev_err(dev, "%s\n", msg); \
46 } while (0)
47
bnxt_get_msglevel(struct net_device * dev)48 static u32 bnxt_get_msglevel(struct net_device *dev)
49 {
50 struct bnxt *bp = netdev_priv(dev);
51
52 return bp->msg_enable;
53 }
54
bnxt_set_msglevel(struct net_device * dev,u32 value)55 static void bnxt_set_msglevel(struct net_device *dev, u32 value)
56 {
57 struct bnxt *bp = netdev_priv(dev);
58
59 bp->msg_enable = value;
60 }
61
bnxt_get_coalesce(struct net_device * dev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)62 static int bnxt_get_coalesce(struct net_device *dev,
63 struct ethtool_coalesce *coal,
64 struct kernel_ethtool_coalesce *kernel_coal,
65 struct netlink_ext_ack *extack)
66 {
67 struct bnxt *bp = netdev_priv(dev);
68 struct bnxt_coal *hw_coal;
69 u16 mult;
70
71 memset(coal, 0, sizeof(*coal));
72
73 coal->use_adaptive_rx_coalesce = bp->flags & BNXT_FLAG_DIM;
74
75 hw_coal = &bp->rx_coal;
76 mult = hw_coal->bufs_per_record;
77 coal->rx_coalesce_usecs = hw_coal->coal_ticks;
78 coal->rx_max_coalesced_frames = hw_coal->coal_bufs / mult;
79 coal->rx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
80 coal->rx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
81 if (hw_coal->flags &
82 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
83 kernel_coal->use_cqe_mode_rx = true;
84
85 hw_coal = &bp->tx_coal;
86 mult = hw_coal->bufs_per_record;
87 coal->tx_coalesce_usecs = hw_coal->coal_ticks;
88 coal->tx_max_coalesced_frames = hw_coal->coal_bufs / mult;
89 coal->tx_coalesce_usecs_irq = hw_coal->coal_ticks_irq;
90 coal->tx_max_coalesced_frames_irq = hw_coal->coal_bufs_irq / mult;
91 if (hw_coal->flags &
92 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET)
93 kernel_coal->use_cqe_mode_tx = true;
94
95 coal->stats_block_coalesce_usecs = bp->stats_coal_ticks;
96
97 return 0;
98 }
99
bnxt_set_coalesce(struct net_device * dev,struct ethtool_coalesce * coal,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)100 static int bnxt_set_coalesce(struct net_device *dev,
101 struct ethtool_coalesce *coal,
102 struct kernel_ethtool_coalesce *kernel_coal,
103 struct netlink_ext_ack *extack)
104 {
105 struct bnxt *bp = netdev_priv(dev);
106 bool update_stats = false;
107 struct bnxt_coal *hw_coal;
108 int rc = 0;
109 u16 mult;
110
111 if (coal->use_adaptive_rx_coalesce) {
112 bp->flags |= BNXT_FLAG_DIM;
113 } else {
114 if (bp->flags & BNXT_FLAG_DIM) {
115 bp->flags &= ~(BNXT_FLAG_DIM);
116 goto reset_coalesce;
117 }
118 }
119
120 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) &&
121 !(bp->coal_cap.cmpl_params &
122 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET))
123 return -EOPNOTSUPP;
124
125 hw_coal = &bp->rx_coal;
126 mult = hw_coal->bufs_per_record;
127 hw_coal->coal_ticks = coal->rx_coalesce_usecs;
128 hw_coal->coal_bufs = coal->rx_max_coalesced_frames * mult;
129 hw_coal->coal_ticks_irq = coal->rx_coalesce_usecs_irq;
130 hw_coal->coal_bufs_irq = coal->rx_max_coalesced_frames_irq * mult;
131 hw_coal->flags &=
132 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
133 if (kernel_coal->use_cqe_mode_rx)
134 hw_coal->flags |=
135 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
136
137 hw_coal = &bp->tx_coal;
138 mult = hw_coal->bufs_per_record;
139 hw_coal->coal_ticks = coal->tx_coalesce_usecs;
140 hw_coal->coal_bufs = coal->tx_max_coalesced_frames * mult;
141 hw_coal->coal_ticks_irq = coal->tx_coalesce_usecs_irq;
142 hw_coal->coal_bufs_irq = coal->tx_max_coalesced_frames_irq * mult;
143 hw_coal->flags &=
144 ~RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
145 if (kernel_coal->use_cqe_mode_tx)
146 hw_coal->flags |=
147 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
148
149 if (bp->stats_coal_ticks != coal->stats_block_coalesce_usecs) {
150 u32 stats_ticks = coal->stats_block_coalesce_usecs;
151
152 /* Allow 0, which means disable. */
153 if (stats_ticks)
154 stats_ticks = clamp_t(u32, stats_ticks,
155 BNXT_MIN_STATS_COAL_TICKS,
156 BNXT_MAX_STATS_COAL_TICKS);
157 stats_ticks = rounddown(stats_ticks, BNXT_MIN_STATS_COAL_TICKS);
158 bp->stats_coal_ticks = stats_ticks;
159 if (bp->stats_coal_ticks)
160 bp->current_interval =
161 bp->stats_coal_ticks * HZ / 1000000;
162 else
163 bp->current_interval = BNXT_TIMER_INTERVAL;
164 update_stats = true;
165 }
166
167 reset_coalesce:
168 if (test_bit(BNXT_STATE_OPEN, &bp->state)) {
169 if (update_stats) {
170 bnxt_close_nic(bp, true, false);
171 rc = bnxt_open_nic(bp, true, false);
172 } else {
173 rc = bnxt_hwrm_set_coal(bp);
174 }
175 }
176
177 return rc;
178 }
179
180 static const char * const bnxt_ring_rx_stats_str[] = {
181 "rx_ucast_packets",
182 "rx_mcast_packets",
183 "rx_bcast_packets",
184 "rx_discards",
185 "rx_errors",
186 "rx_ucast_bytes",
187 "rx_mcast_bytes",
188 "rx_bcast_bytes",
189 };
190
191 static const char * const bnxt_ring_tx_stats_str[] = {
192 "tx_ucast_packets",
193 "tx_mcast_packets",
194 "tx_bcast_packets",
195 "tx_errors",
196 "tx_discards",
197 "tx_ucast_bytes",
198 "tx_mcast_bytes",
199 "tx_bcast_bytes",
200 };
201
202 static const char * const bnxt_ring_tpa_stats_str[] = {
203 "tpa_packets",
204 "tpa_bytes",
205 "tpa_events",
206 "tpa_aborts",
207 };
208
209 static const char * const bnxt_ring_tpa2_stats_str[] = {
210 "rx_tpa_eligible_pkt",
211 "rx_tpa_eligible_bytes",
212 "rx_tpa_pkt",
213 "rx_tpa_bytes",
214 "rx_tpa_errors",
215 "rx_tpa_events",
216 };
217
218 static const char * const bnxt_rx_sw_stats_str[] = {
219 "rx_l4_csum_errors",
220 "rx_resets",
221 "rx_buf_errors",
222 };
223
224 static const char * const bnxt_cmn_sw_stats_str[] = {
225 "missed_irqs",
226 };
227
228 #define BNXT_RX_STATS_ENTRY(counter) \
229 { BNXT_RX_STATS_OFFSET(counter), __stringify(counter) }
230
231 #define BNXT_TX_STATS_ENTRY(counter) \
232 { BNXT_TX_STATS_OFFSET(counter), __stringify(counter) }
233
234 #define BNXT_RX_STATS_EXT_ENTRY(counter) \
235 { BNXT_RX_STATS_EXT_OFFSET(counter), __stringify(counter) }
236
237 #define BNXT_TX_STATS_EXT_ENTRY(counter) \
238 { BNXT_TX_STATS_EXT_OFFSET(counter), __stringify(counter) }
239
240 #define BNXT_RX_STATS_EXT_PFC_ENTRY(n) \
241 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_duration_us), \
242 BNXT_RX_STATS_EXT_ENTRY(pfc_pri##n##_rx_transitions)
243
244 #define BNXT_TX_STATS_EXT_PFC_ENTRY(n) \
245 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_duration_us), \
246 BNXT_TX_STATS_EXT_ENTRY(pfc_pri##n##_tx_transitions)
247
248 #define BNXT_RX_STATS_EXT_PFC_ENTRIES \
249 BNXT_RX_STATS_EXT_PFC_ENTRY(0), \
250 BNXT_RX_STATS_EXT_PFC_ENTRY(1), \
251 BNXT_RX_STATS_EXT_PFC_ENTRY(2), \
252 BNXT_RX_STATS_EXT_PFC_ENTRY(3), \
253 BNXT_RX_STATS_EXT_PFC_ENTRY(4), \
254 BNXT_RX_STATS_EXT_PFC_ENTRY(5), \
255 BNXT_RX_STATS_EXT_PFC_ENTRY(6), \
256 BNXT_RX_STATS_EXT_PFC_ENTRY(7)
257
258 #define BNXT_TX_STATS_EXT_PFC_ENTRIES \
259 BNXT_TX_STATS_EXT_PFC_ENTRY(0), \
260 BNXT_TX_STATS_EXT_PFC_ENTRY(1), \
261 BNXT_TX_STATS_EXT_PFC_ENTRY(2), \
262 BNXT_TX_STATS_EXT_PFC_ENTRY(3), \
263 BNXT_TX_STATS_EXT_PFC_ENTRY(4), \
264 BNXT_TX_STATS_EXT_PFC_ENTRY(5), \
265 BNXT_TX_STATS_EXT_PFC_ENTRY(6), \
266 BNXT_TX_STATS_EXT_PFC_ENTRY(7)
267
268 #define BNXT_RX_STATS_EXT_COS_ENTRY(n) \
269 BNXT_RX_STATS_EXT_ENTRY(rx_bytes_cos##n), \
270 BNXT_RX_STATS_EXT_ENTRY(rx_packets_cos##n)
271
272 #define BNXT_TX_STATS_EXT_COS_ENTRY(n) \
273 BNXT_TX_STATS_EXT_ENTRY(tx_bytes_cos##n), \
274 BNXT_TX_STATS_EXT_ENTRY(tx_packets_cos##n)
275
276 #define BNXT_RX_STATS_EXT_COS_ENTRIES \
277 BNXT_RX_STATS_EXT_COS_ENTRY(0), \
278 BNXT_RX_STATS_EXT_COS_ENTRY(1), \
279 BNXT_RX_STATS_EXT_COS_ENTRY(2), \
280 BNXT_RX_STATS_EXT_COS_ENTRY(3), \
281 BNXT_RX_STATS_EXT_COS_ENTRY(4), \
282 BNXT_RX_STATS_EXT_COS_ENTRY(5), \
283 BNXT_RX_STATS_EXT_COS_ENTRY(6), \
284 BNXT_RX_STATS_EXT_COS_ENTRY(7) \
285
286 #define BNXT_TX_STATS_EXT_COS_ENTRIES \
287 BNXT_TX_STATS_EXT_COS_ENTRY(0), \
288 BNXT_TX_STATS_EXT_COS_ENTRY(1), \
289 BNXT_TX_STATS_EXT_COS_ENTRY(2), \
290 BNXT_TX_STATS_EXT_COS_ENTRY(3), \
291 BNXT_TX_STATS_EXT_COS_ENTRY(4), \
292 BNXT_TX_STATS_EXT_COS_ENTRY(5), \
293 BNXT_TX_STATS_EXT_COS_ENTRY(6), \
294 BNXT_TX_STATS_EXT_COS_ENTRY(7) \
295
296 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(n) \
297 BNXT_RX_STATS_EXT_ENTRY(rx_discard_bytes_cos##n), \
298 BNXT_RX_STATS_EXT_ENTRY(rx_discard_packets_cos##n)
299
300 #define BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES \
301 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(0), \
302 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(1), \
303 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(2), \
304 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(3), \
305 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(4), \
306 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(5), \
307 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(6), \
308 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRY(7)
309
310 #define BNXT_RX_STATS_PRI_ENTRY(counter, n) \
311 { BNXT_RX_STATS_EXT_OFFSET(counter##_cos0), \
312 __stringify(counter##_pri##n) }
313
314 #define BNXT_TX_STATS_PRI_ENTRY(counter, n) \
315 { BNXT_TX_STATS_EXT_OFFSET(counter##_cos0), \
316 __stringify(counter##_pri##n) }
317
318 #define BNXT_RX_STATS_PRI_ENTRIES(counter) \
319 BNXT_RX_STATS_PRI_ENTRY(counter, 0), \
320 BNXT_RX_STATS_PRI_ENTRY(counter, 1), \
321 BNXT_RX_STATS_PRI_ENTRY(counter, 2), \
322 BNXT_RX_STATS_PRI_ENTRY(counter, 3), \
323 BNXT_RX_STATS_PRI_ENTRY(counter, 4), \
324 BNXT_RX_STATS_PRI_ENTRY(counter, 5), \
325 BNXT_RX_STATS_PRI_ENTRY(counter, 6), \
326 BNXT_RX_STATS_PRI_ENTRY(counter, 7)
327
328 #define BNXT_TX_STATS_PRI_ENTRIES(counter) \
329 BNXT_TX_STATS_PRI_ENTRY(counter, 0), \
330 BNXT_TX_STATS_PRI_ENTRY(counter, 1), \
331 BNXT_TX_STATS_PRI_ENTRY(counter, 2), \
332 BNXT_TX_STATS_PRI_ENTRY(counter, 3), \
333 BNXT_TX_STATS_PRI_ENTRY(counter, 4), \
334 BNXT_TX_STATS_PRI_ENTRY(counter, 5), \
335 BNXT_TX_STATS_PRI_ENTRY(counter, 6), \
336 BNXT_TX_STATS_PRI_ENTRY(counter, 7)
337
338 enum {
339 RX_TOTAL_DISCARDS,
340 TX_TOTAL_DISCARDS,
341 RX_NETPOLL_DISCARDS,
342 };
343
344 static const char *const bnxt_ring_drv_stats_arr[] = {
345 "rx_total_l4_csum_errors",
346 "rx_total_resets",
347 "rx_total_buf_errors",
348 "rx_total_oom_discards",
349 "rx_total_netpoll_discards",
350 "rx_total_ring_discards",
351 "tx_total_resets",
352 "tx_total_ring_discards",
353 "total_missed_irqs",
354 };
355
356 #define NUM_RING_RX_SW_STATS ARRAY_SIZE(bnxt_rx_sw_stats_str)
357 #define NUM_RING_CMN_SW_STATS ARRAY_SIZE(bnxt_cmn_sw_stats_str)
358 #define NUM_RING_RX_HW_STATS ARRAY_SIZE(bnxt_ring_rx_stats_str)
359 #define NUM_RING_TX_HW_STATS ARRAY_SIZE(bnxt_ring_tx_stats_str)
360
361 static const struct {
362 long offset;
363 char string[ETH_GSTRING_LEN];
364 } bnxt_port_stats_arr[] = {
365 BNXT_RX_STATS_ENTRY(rx_64b_frames),
366 BNXT_RX_STATS_ENTRY(rx_65b_127b_frames),
367 BNXT_RX_STATS_ENTRY(rx_128b_255b_frames),
368 BNXT_RX_STATS_ENTRY(rx_256b_511b_frames),
369 BNXT_RX_STATS_ENTRY(rx_512b_1023b_frames),
370 BNXT_RX_STATS_ENTRY(rx_1024b_1518b_frames),
371 BNXT_RX_STATS_ENTRY(rx_good_vlan_frames),
372 BNXT_RX_STATS_ENTRY(rx_1519b_2047b_frames),
373 BNXT_RX_STATS_ENTRY(rx_2048b_4095b_frames),
374 BNXT_RX_STATS_ENTRY(rx_4096b_9216b_frames),
375 BNXT_RX_STATS_ENTRY(rx_9217b_16383b_frames),
376 BNXT_RX_STATS_ENTRY(rx_total_frames),
377 BNXT_RX_STATS_ENTRY(rx_ucast_frames),
378 BNXT_RX_STATS_ENTRY(rx_mcast_frames),
379 BNXT_RX_STATS_ENTRY(rx_bcast_frames),
380 BNXT_RX_STATS_ENTRY(rx_fcs_err_frames),
381 BNXT_RX_STATS_ENTRY(rx_ctrl_frames),
382 BNXT_RX_STATS_ENTRY(rx_pause_frames),
383 BNXT_RX_STATS_ENTRY(rx_pfc_frames),
384 BNXT_RX_STATS_ENTRY(rx_align_err_frames),
385 BNXT_RX_STATS_ENTRY(rx_ovrsz_frames),
386 BNXT_RX_STATS_ENTRY(rx_jbr_frames),
387 BNXT_RX_STATS_ENTRY(rx_mtu_err_frames),
388 BNXT_RX_STATS_ENTRY(rx_tagged_frames),
389 BNXT_RX_STATS_ENTRY(rx_double_tagged_frames),
390 BNXT_RX_STATS_ENTRY(rx_good_frames),
391 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri0),
392 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri1),
393 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri2),
394 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri3),
395 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri4),
396 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri5),
397 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri6),
398 BNXT_RX_STATS_ENTRY(rx_pfc_ena_frames_pri7),
399 BNXT_RX_STATS_ENTRY(rx_undrsz_frames),
400 BNXT_RX_STATS_ENTRY(rx_eee_lpi_events),
401 BNXT_RX_STATS_ENTRY(rx_eee_lpi_duration),
402 BNXT_RX_STATS_ENTRY(rx_bytes),
403 BNXT_RX_STATS_ENTRY(rx_runt_bytes),
404 BNXT_RX_STATS_ENTRY(rx_runt_frames),
405 BNXT_RX_STATS_ENTRY(rx_stat_discard),
406 BNXT_RX_STATS_ENTRY(rx_stat_err),
407
408 BNXT_TX_STATS_ENTRY(tx_64b_frames),
409 BNXT_TX_STATS_ENTRY(tx_65b_127b_frames),
410 BNXT_TX_STATS_ENTRY(tx_128b_255b_frames),
411 BNXT_TX_STATS_ENTRY(tx_256b_511b_frames),
412 BNXT_TX_STATS_ENTRY(tx_512b_1023b_frames),
413 BNXT_TX_STATS_ENTRY(tx_1024b_1518b_frames),
414 BNXT_TX_STATS_ENTRY(tx_good_vlan_frames),
415 BNXT_TX_STATS_ENTRY(tx_1519b_2047b_frames),
416 BNXT_TX_STATS_ENTRY(tx_2048b_4095b_frames),
417 BNXT_TX_STATS_ENTRY(tx_4096b_9216b_frames),
418 BNXT_TX_STATS_ENTRY(tx_9217b_16383b_frames),
419 BNXT_TX_STATS_ENTRY(tx_good_frames),
420 BNXT_TX_STATS_ENTRY(tx_total_frames),
421 BNXT_TX_STATS_ENTRY(tx_ucast_frames),
422 BNXT_TX_STATS_ENTRY(tx_mcast_frames),
423 BNXT_TX_STATS_ENTRY(tx_bcast_frames),
424 BNXT_TX_STATS_ENTRY(tx_pause_frames),
425 BNXT_TX_STATS_ENTRY(tx_pfc_frames),
426 BNXT_TX_STATS_ENTRY(tx_jabber_frames),
427 BNXT_TX_STATS_ENTRY(tx_fcs_err_frames),
428 BNXT_TX_STATS_ENTRY(tx_err),
429 BNXT_TX_STATS_ENTRY(tx_fifo_underruns),
430 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri0),
431 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri1),
432 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri2),
433 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri3),
434 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri4),
435 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri5),
436 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri6),
437 BNXT_TX_STATS_ENTRY(tx_pfc_ena_frames_pri7),
438 BNXT_TX_STATS_ENTRY(tx_eee_lpi_events),
439 BNXT_TX_STATS_ENTRY(tx_eee_lpi_duration),
440 BNXT_TX_STATS_ENTRY(tx_total_collisions),
441 BNXT_TX_STATS_ENTRY(tx_bytes),
442 BNXT_TX_STATS_ENTRY(tx_xthol_frames),
443 BNXT_TX_STATS_ENTRY(tx_stat_discard),
444 BNXT_TX_STATS_ENTRY(tx_stat_error),
445 };
446
447 static const struct {
448 long offset;
449 char string[ETH_GSTRING_LEN];
450 } bnxt_port_stats_ext_arr[] = {
451 BNXT_RX_STATS_EXT_ENTRY(link_down_events),
452 BNXT_RX_STATS_EXT_ENTRY(continuous_pause_events),
453 BNXT_RX_STATS_EXT_ENTRY(resume_pause_events),
454 BNXT_RX_STATS_EXT_ENTRY(continuous_roce_pause_events),
455 BNXT_RX_STATS_EXT_ENTRY(resume_roce_pause_events),
456 BNXT_RX_STATS_EXT_COS_ENTRIES,
457 BNXT_RX_STATS_EXT_PFC_ENTRIES,
458 BNXT_RX_STATS_EXT_ENTRY(rx_bits),
459 BNXT_RX_STATS_EXT_ENTRY(rx_buffer_passed_threshold),
460 BNXT_RX_STATS_EXT_ENTRY(rx_pcs_symbol_err),
461 BNXT_RX_STATS_EXT_ENTRY(rx_corrected_bits),
462 BNXT_RX_STATS_EXT_DISCARD_COS_ENTRIES,
463 BNXT_RX_STATS_EXT_ENTRY(rx_fec_corrected_blocks),
464 BNXT_RX_STATS_EXT_ENTRY(rx_fec_uncorrectable_blocks),
465 BNXT_RX_STATS_EXT_ENTRY(rx_filter_miss),
466 };
467
468 static const struct {
469 long offset;
470 char string[ETH_GSTRING_LEN];
471 } bnxt_tx_port_stats_ext_arr[] = {
472 BNXT_TX_STATS_EXT_COS_ENTRIES,
473 BNXT_TX_STATS_EXT_PFC_ENTRIES,
474 };
475
476 static const struct {
477 long base_off;
478 char string[ETH_GSTRING_LEN];
479 } bnxt_rx_bytes_pri_arr[] = {
480 BNXT_RX_STATS_PRI_ENTRIES(rx_bytes),
481 };
482
483 static const struct {
484 long base_off;
485 char string[ETH_GSTRING_LEN];
486 } bnxt_rx_pkts_pri_arr[] = {
487 BNXT_RX_STATS_PRI_ENTRIES(rx_packets),
488 };
489
490 static const struct {
491 long base_off;
492 char string[ETH_GSTRING_LEN];
493 } bnxt_tx_bytes_pri_arr[] = {
494 BNXT_TX_STATS_PRI_ENTRIES(tx_bytes),
495 };
496
497 static const struct {
498 long base_off;
499 char string[ETH_GSTRING_LEN];
500 } bnxt_tx_pkts_pri_arr[] = {
501 BNXT_TX_STATS_PRI_ENTRIES(tx_packets),
502 };
503
504 #define BNXT_NUM_RING_DRV_STATS ARRAY_SIZE(bnxt_ring_drv_stats_arr)
505 #define BNXT_NUM_PORT_STATS ARRAY_SIZE(bnxt_port_stats_arr)
506 #define BNXT_NUM_STATS_PRI \
507 (ARRAY_SIZE(bnxt_rx_bytes_pri_arr) + \
508 ARRAY_SIZE(bnxt_rx_pkts_pri_arr) + \
509 ARRAY_SIZE(bnxt_tx_bytes_pri_arr) + \
510 ARRAY_SIZE(bnxt_tx_pkts_pri_arr))
511
bnxt_get_num_tpa_ring_stats(struct bnxt * bp)512 static int bnxt_get_num_tpa_ring_stats(struct bnxt *bp)
513 {
514 if (BNXT_SUPPORTS_TPA(bp)) {
515 if (bp->max_tpa_v2) {
516 if (BNXT_CHIP_P5(bp))
517 return BNXT_NUM_TPA_RING_STATS_P5;
518 return BNXT_NUM_TPA_RING_STATS_P7;
519 }
520 return BNXT_NUM_TPA_RING_STATS;
521 }
522 return 0;
523 }
524
bnxt_get_num_ring_stats(struct bnxt * bp)525 static int bnxt_get_num_ring_stats(struct bnxt *bp)
526 {
527 int rx, tx, cmn;
528
529 rx = NUM_RING_RX_HW_STATS + NUM_RING_RX_SW_STATS +
530 bnxt_get_num_tpa_ring_stats(bp);
531 tx = NUM_RING_TX_HW_STATS;
532 cmn = NUM_RING_CMN_SW_STATS;
533 return rx * bp->rx_nr_rings +
534 tx * (bp->tx_nr_rings_xdp + bp->tx_nr_rings_per_tc) +
535 cmn * bp->cp_nr_rings;
536 }
537
bnxt_get_num_stats(struct bnxt * bp)538 static int bnxt_get_num_stats(struct bnxt *bp)
539 {
540 int num_stats = bnxt_get_num_ring_stats(bp);
541 int len;
542
543 num_stats += BNXT_NUM_RING_DRV_STATS;
544
545 if (bp->flags & BNXT_FLAG_PORT_STATS)
546 num_stats += BNXT_NUM_PORT_STATS;
547
548 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
549 len = min_t(int, bp->fw_rx_stats_ext_size,
550 ARRAY_SIZE(bnxt_port_stats_ext_arr));
551 num_stats += len;
552 len = min_t(int, bp->fw_tx_stats_ext_size,
553 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
554 num_stats += len;
555 if (bp->pri2cos_valid)
556 num_stats += BNXT_NUM_STATS_PRI;
557 }
558
559 return num_stats;
560 }
561
bnxt_get_sset_count(struct net_device * dev,int sset)562 static int bnxt_get_sset_count(struct net_device *dev, int sset)
563 {
564 struct bnxt *bp = netdev_priv(dev);
565
566 switch (sset) {
567 case ETH_SS_STATS:
568 return bnxt_get_num_stats(bp);
569 case ETH_SS_TEST:
570 if (!bp->num_tests)
571 return -EOPNOTSUPP;
572 return bp->num_tests;
573 default:
574 return -EOPNOTSUPP;
575 }
576 }
577
is_rx_ring(struct bnxt * bp,int ring_num)578 static bool is_rx_ring(struct bnxt *bp, int ring_num)
579 {
580 return ring_num < bp->rx_nr_rings;
581 }
582
is_tx_ring(struct bnxt * bp,int ring_num)583 static bool is_tx_ring(struct bnxt *bp, int ring_num)
584 {
585 int tx_base = 0;
586
587 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
588 tx_base = bp->rx_nr_rings;
589
590 if (ring_num >= tx_base && ring_num < (tx_base + bp->tx_nr_rings))
591 return true;
592 return false;
593 }
594
bnxt_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * buf)595 static void bnxt_get_ethtool_stats(struct net_device *dev,
596 struct ethtool_stats *stats, u64 *buf)
597 {
598 struct bnxt_total_ring_drv_stats ring_drv_stats = {0};
599 struct bnxt *bp = netdev_priv(dev);
600 u64 *curr, *prev;
601 u32 tpa_stats;
602 u32 i, j = 0;
603
604 if (!bp->bnapi) {
605 j += bnxt_get_num_ring_stats(bp);
606 goto skip_ring_stats;
607 }
608
609 bnxt_sync_ring_stats(bp);
610 tpa_stats = bnxt_get_num_tpa_ring_stats(bp);
611 for (i = 0; i < bp->cp_nr_rings; i++) {
612 struct bnxt_napi *bnapi = bp->bnapi[i];
613 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
614 u64 *sw_stats = cpr->stats.sw_stats;
615 u64 *sw;
616 int k;
617
618 if (is_rx_ring(bp, i)) {
619 for (k = 0; k < NUM_RING_RX_HW_STATS; j++, k++)
620 buf[j] = sw_stats[k];
621 }
622 if (is_tx_ring(bp, i)) {
623 k = NUM_RING_RX_HW_STATS;
624 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
625 j++, k++)
626 buf[j] = sw_stats[k];
627 }
628 if (!tpa_stats || !is_rx_ring(bp, i))
629 goto skip_tpa_ring_stats;
630
631 k = NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS;
632 for (; k < NUM_RING_RX_HW_STATS + NUM_RING_TX_HW_STATS +
633 tpa_stats; j++, k++)
634 buf[j] = sw_stats[k];
635
636 skip_tpa_ring_stats:
637 sw = (u64 *)&cpr->sw_stats->rx;
638 if (is_rx_ring(bp, i)) {
639 for (k = 0; k < NUM_RING_RX_SW_STATS; j++, k++)
640 buf[j] = sw[k];
641 }
642
643 sw = (u64 *)&cpr->sw_stats->cmn;
644 for (k = 0; k < NUM_RING_CMN_SW_STATS; j++, k++)
645 buf[j] = sw[k];
646 }
647
648 bnxt_get_ring_drv_stats(bp, &ring_drv_stats);
649
650 skip_ring_stats:
651 curr = &ring_drv_stats.rx_total_l4_csum_errors;
652 prev = &bp->ring_drv_stats_prev.rx_total_l4_csum_errors;
653 for (i = 0; i < BNXT_NUM_RING_DRV_STATS; i++, j++, curr++, prev++)
654 buf[j] = *curr + *prev;
655
656 if (bp->flags & BNXT_FLAG_PORT_STATS) {
657 u64 *port_stats = bp->port_stats.sw_stats;
658
659 for (i = 0; i < BNXT_NUM_PORT_STATS; i++, j++)
660 buf[j] = *(port_stats + bnxt_port_stats_arr[i].offset);
661 }
662 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
663 u64 *rx_port_stats_ext = bp->rx_port_stats_ext.sw_stats;
664 u64 *tx_port_stats_ext = bp->tx_port_stats_ext.sw_stats;
665 u32 len;
666
667 len = min_t(u32, bp->fw_rx_stats_ext_size,
668 ARRAY_SIZE(bnxt_port_stats_ext_arr));
669 for (i = 0; i < len; i++, j++) {
670 buf[j] = *(rx_port_stats_ext +
671 bnxt_port_stats_ext_arr[i].offset);
672 }
673 len = min_t(u32, bp->fw_tx_stats_ext_size,
674 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
675 for (i = 0; i < len; i++, j++) {
676 buf[j] = *(tx_port_stats_ext +
677 bnxt_tx_port_stats_ext_arr[i].offset);
678 }
679 if (bp->pri2cos_valid) {
680 for (i = 0; i < 8; i++, j++) {
681 long n = bnxt_rx_bytes_pri_arr[i].base_off +
682 bp->pri2cos_idx[i];
683
684 buf[j] = *(rx_port_stats_ext + n);
685 }
686 for (i = 0; i < 8; i++, j++) {
687 long n = bnxt_rx_pkts_pri_arr[i].base_off +
688 bp->pri2cos_idx[i];
689
690 buf[j] = *(rx_port_stats_ext + n);
691 }
692 for (i = 0; i < 8; i++, j++) {
693 u8 cos_idx = bp->pri2cos_idx[i];
694 long n;
695
696 n = bnxt_tx_bytes_pri_arr[i].base_off + cos_idx;
697 buf[j] = *(tx_port_stats_ext + n);
698 if (bp->cos0_cos1_shared && !cos_idx)
699 buf[j] += *(tx_port_stats_ext + n + 1);
700 }
701 for (i = 0; i < 8; i++, j++) {
702 u8 cos_idx = bp->pri2cos_idx[i];
703 long n;
704
705 n = bnxt_tx_pkts_pri_arr[i].base_off + cos_idx;
706 buf[j] = *(tx_port_stats_ext + n);
707 if (bp->cos0_cos1_shared && !cos_idx)
708 buf[j] += *(tx_port_stats_ext + n + 1);
709 }
710 }
711 }
712 }
713
bnxt_get_strings(struct net_device * dev,u32 stringset,u8 * buf)714 static void bnxt_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
715 {
716 struct bnxt *bp = netdev_priv(dev);
717 u32 i, j, num_str;
718 const char *str;
719
720 switch (stringset) {
721 case ETH_SS_STATS:
722 for (i = 0; i < bp->cp_nr_rings; i++) {
723 if (is_rx_ring(bp, i))
724 for (j = 0; j < NUM_RING_RX_HW_STATS; j++) {
725 str = bnxt_ring_rx_stats_str[j];
726 ethtool_sprintf(&buf, "[%d]: %s", i,
727 str);
728 }
729 if (is_tx_ring(bp, i))
730 for (j = 0; j < NUM_RING_TX_HW_STATS; j++) {
731 str = bnxt_ring_tx_stats_str[j];
732 ethtool_sprintf(&buf, "[%d]: %s", i,
733 str);
734 }
735 num_str = bnxt_get_num_tpa_ring_stats(bp);
736 if (!num_str || !is_rx_ring(bp, i))
737 goto skip_tpa_stats;
738
739 if (bp->max_tpa_v2)
740 for (j = 0; j < num_str; j++) {
741 str = bnxt_ring_tpa2_stats_str[j];
742 ethtool_sprintf(&buf, "[%d]: %s", i,
743 str);
744 }
745 else
746 for (j = 0; j < num_str; j++) {
747 str = bnxt_ring_tpa_stats_str[j];
748 ethtool_sprintf(&buf, "[%d]: %s", i,
749 str);
750 }
751 skip_tpa_stats:
752 if (is_rx_ring(bp, i))
753 for (j = 0; j < NUM_RING_RX_SW_STATS; j++) {
754 str = bnxt_rx_sw_stats_str[j];
755 ethtool_sprintf(&buf, "[%d]: %s", i,
756 str);
757 }
758 for (j = 0; j < NUM_RING_CMN_SW_STATS; j++) {
759 str = bnxt_cmn_sw_stats_str[j];
760 ethtool_sprintf(&buf, "[%d]: %s", i, str);
761 }
762 }
763 for (i = 0; i < BNXT_NUM_RING_DRV_STATS; i++)
764 ethtool_puts(&buf, bnxt_ring_drv_stats_arr[i]);
765
766 if (bp->flags & BNXT_FLAG_PORT_STATS)
767 for (i = 0; i < BNXT_NUM_PORT_STATS; i++) {
768 str = bnxt_port_stats_arr[i].string;
769 ethtool_puts(&buf, str);
770 }
771
772 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
773 u32 len;
774
775 len = min_t(u32, bp->fw_rx_stats_ext_size,
776 ARRAY_SIZE(bnxt_port_stats_ext_arr));
777 for (i = 0; i < len; i++) {
778 str = bnxt_port_stats_ext_arr[i].string;
779 ethtool_puts(&buf, str);
780 }
781
782 len = min_t(u32, bp->fw_tx_stats_ext_size,
783 ARRAY_SIZE(bnxt_tx_port_stats_ext_arr));
784 for (i = 0; i < len; i++) {
785 str = bnxt_tx_port_stats_ext_arr[i].string;
786 ethtool_puts(&buf, str);
787 }
788
789 if (bp->pri2cos_valid) {
790 for (i = 0; i < 8; i++) {
791 str = bnxt_rx_bytes_pri_arr[i].string;
792 ethtool_puts(&buf, str);
793 }
794
795 for (i = 0; i < 8; i++) {
796 str = bnxt_rx_pkts_pri_arr[i].string;
797 ethtool_puts(&buf, str);
798 }
799
800 for (i = 0; i < 8; i++) {
801 str = bnxt_tx_bytes_pri_arr[i].string;
802 ethtool_puts(&buf, str);
803 }
804
805 for (i = 0; i < 8; i++) {
806 str = bnxt_tx_pkts_pri_arr[i].string;
807 ethtool_puts(&buf, str);
808 }
809 }
810 }
811 break;
812 case ETH_SS_TEST:
813 if (bp->num_tests)
814 for (i = 0; i < bp->num_tests; i++)
815 ethtool_puts(&buf, bp->test_info->string[i]);
816 break;
817 default:
818 netdev_err(bp->dev, "bnxt_get_strings invalid request %x\n",
819 stringset);
820 break;
821 }
822 }
823
bnxt_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)824 static void bnxt_get_ringparam(struct net_device *dev,
825 struct ethtool_ringparam *ering,
826 struct kernel_ethtool_ringparam *kernel_ering,
827 struct netlink_ext_ack *extack)
828 {
829 struct bnxt *bp = netdev_priv(dev);
830
831 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
832 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT_JUM_ENA;
833 ering->rx_jumbo_max_pending = BNXT_MAX_RX_JUM_DESC_CNT;
834 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_ENABLED;
835 } else {
836 ering->rx_max_pending = BNXT_MAX_RX_DESC_CNT;
837 ering->rx_jumbo_max_pending = 0;
838 kernel_ering->tcp_data_split = ETHTOOL_TCP_DATA_SPLIT_DISABLED;
839 }
840 ering->tx_max_pending = BNXT_MAX_TX_DESC_CNT;
841
842 ering->rx_pending = bp->rx_ring_size;
843 ering->rx_jumbo_pending = bp->rx_agg_ring_size;
844 ering->tx_pending = bp->tx_ring_size;
845
846 kernel_ering->hds_thresh_max = BNXT_HDS_THRESHOLD_MAX;
847 }
848
bnxt_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)849 static int bnxt_set_ringparam(struct net_device *dev,
850 struct ethtool_ringparam *ering,
851 struct kernel_ethtool_ringparam *kernel_ering,
852 struct netlink_ext_ack *extack)
853 {
854 u8 tcp_data_split = kernel_ering->tcp_data_split;
855 struct bnxt *bp = netdev_priv(dev);
856 u8 hds_config_mod;
857 int rc;
858
859 if ((ering->rx_pending > BNXT_MAX_RX_DESC_CNT) ||
860 (ering->tx_pending > BNXT_MAX_TX_DESC_CNT) ||
861 (ering->tx_pending < BNXT_MIN_TX_DESC_CNT))
862 return -EINVAL;
863
864 if ((dev->features & NETIF_F_GSO_UDP_L4) &&
865 !(bp->flags & BNXT_FLAG_UDP_GSO_CAP) &&
866 ering->tx_pending < 2 * BNXT_SW_USO_MAX_DESCS)
867 return -EINVAL;
868
869 hds_config_mod = tcp_data_split != dev->cfg->hds_config;
870 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_DISABLED && hds_config_mod)
871 return -EINVAL;
872
873 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED &&
874 hds_config_mod && BNXT_RX_PAGE_MODE(bp)) {
875 NL_SET_ERR_MSG_MOD(extack, "tcp-data-split is disallowed when XDP is attached");
876 return -EINVAL;
877 }
878
879 if (netif_running(dev))
880 bnxt_close_nic(bp, false, false);
881
882 if (hds_config_mod) {
883 if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_ENABLED)
884 bp->flags |= BNXT_FLAG_HDS;
885 else if (tcp_data_split == ETHTOOL_TCP_DATA_SPLIT_UNKNOWN)
886 bp->flags &= ~BNXT_FLAG_HDS;
887 }
888
889 bp->rx_ring_size = ering->rx_pending;
890 bp->tx_ring_size = ering->tx_pending;
891 bnxt_set_ring_params(bp);
892
893 if (netif_running(dev)) {
894 rc = bnxt_open_nic(bp, false, false);
895 if (rc)
896 return rc;
897 }
898
899 /* ring size changes may affect features (SW USO requires a minimum
900 * ring size), so recalculate features to ensure the correct features
901 * are blocked/available.
902 */
903 netdev_update_features(dev);
904 return 0;
905 }
906
bnxt_get_channels(struct net_device * dev,struct ethtool_channels * channel)907 static void bnxt_get_channels(struct net_device *dev,
908 struct ethtool_channels *channel)
909 {
910 struct bnxt *bp = netdev_priv(dev);
911 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
912 int max_rx_rings, max_tx_rings, tcs;
913 int max_tx_sch_inputs, tx_grps;
914
915 /* Get the most up-to-date max_tx_sch_inputs. */
916 if (netif_running(dev) && BNXT_NEW_RM(bp))
917 bnxt_hwrm_func_resc_qcaps(bp, false);
918 max_tx_sch_inputs = hw_resc->max_tx_sch_inputs;
919
920 bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
921 if (max_tx_sch_inputs)
922 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
923
924 tcs = bp->num_tc;
925 tx_grps = max(tcs, 1);
926 if (bp->tx_nr_rings_xdp)
927 tx_grps++;
928 max_tx_rings /= tx_grps;
929 channel->max_combined = min_t(int, max_rx_rings, max_tx_rings);
930
931 if (bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, false)) {
932 max_rx_rings = 0;
933 max_tx_rings = 0;
934 }
935 if (max_tx_sch_inputs)
936 max_tx_rings = min_t(int, max_tx_rings, max_tx_sch_inputs);
937
938 if (tcs > 1)
939 max_tx_rings /= tcs;
940
941 channel->max_rx = max_rx_rings;
942 channel->max_tx = max_tx_rings;
943 channel->max_other = 0;
944 if (bp->flags & BNXT_FLAG_SHARED_RINGS) {
945 channel->combined_count = bp->rx_nr_rings;
946 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
947 channel->combined_count--;
948 } else {
949 if (!BNXT_CHIP_TYPE_NITRO_A0(bp)) {
950 channel->rx_count = bp->rx_nr_rings;
951 channel->tx_count = bp->tx_nr_rings_per_tc;
952 }
953 }
954 }
955
bnxt_set_channels(struct net_device * dev,struct ethtool_channels * channel)956 static int bnxt_set_channels(struct net_device *dev,
957 struct ethtool_channels *channel)
958 {
959 struct bnxt *bp = netdev_priv(dev);
960 int req_tx_rings, req_rx_rings, tcs;
961 u32 new_tbl_size = 0, old_tbl_size;
962 bool sh = false;
963 int tx_xdp = 0;
964 int rc = 0;
965
966 if (channel->other_count)
967 return -EINVAL;
968
969 if (!channel->combined_count &&
970 (!channel->rx_count || !channel->tx_count))
971 return -EINVAL;
972
973 if (channel->combined_count &&
974 (channel->rx_count || channel->tx_count))
975 return -EINVAL;
976
977 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && (channel->rx_count ||
978 channel->tx_count))
979 return -EINVAL;
980
981 if (channel->combined_count)
982 sh = true;
983
984 tcs = bp->num_tc;
985
986 req_tx_rings = sh ? channel->combined_count : channel->tx_count;
987 req_rx_rings = sh ? channel->combined_count : channel->rx_count;
988 if (bp->tx_nr_rings_xdp) {
989 if (!sh) {
990 netdev_err(dev, "Only combined mode supported when XDP is enabled.\n");
991 return -EINVAL;
992 }
993 tx_xdp = req_rx_rings;
994 }
995
996 rc = bnxt_check_rings(bp, req_tx_rings, req_rx_rings, sh, tcs, tx_xdp);
997 if (rc) {
998 netdev_warn(dev, "Unable to allocate the requested rings\n");
999 return rc;
1000 }
1001
1002 /* RSS table size only changes on P5 chips with older firmware;
1003 * newer firmware always uses the largest table size.
1004 */
1005 if (bnxt_get_nr_rss_ctxs(bp, req_rx_rings) !=
1006 bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings)) {
1007 new_tbl_size = bnxt_get_nr_rss_ctxs(bp, req_rx_rings) *
1008 BNXT_RSS_TABLE_ENTRIES_P5;
1009 old_tbl_size = bnxt_get_rxfh_indir_size(dev);
1010
1011 if (!ethtool_rxfh_indir_can_resize(dev, bp->rss_indir_tbl,
1012 old_tbl_size,
1013 new_tbl_size)) {
1014 netdev_warn(dev, "RSS table resize not possible\n");
1015 return -EINVAL;
1016 }
1017
1018 rc = ethtool_rxfh_ctxs_can_resize(dev, new_tbl_size);
1019 if (rc)
1020 return rc;
1021 }
1022
1023 if (netif_running(dev)) {
1024 if (BNXT_PF(bp)) {
1025 /* TODO CHIMP_FW: Send message to all VF's
1026 * before PF unload
1027 */
1028 }
1029 bnxt_close_nic(bp, true, false);
1030 }
1031
1032 if (new_tbl_size) {
1033 ethtool_rxfh_indir_resize(dev, bp->rss_indir_tbl,
1034 old_tbl_size, new_tbl_size);
1035 ethtool_rxfh_ctxs_resize(dev, new_tbl_size);
1036 }
1037
1038 if (sh) {
1039 bp->flags |= BNXT_FLAG_SHARED_RINGS;
1040 bp->rx_nr_rings = channel->combined_count;
1041 bp->tx_nr_rings_per_tc = channel->combined_count;
1042 } else {
1043 bp->flags &= ~BNXT_FLAG_SHARED_RINGS;
1044 bp->rx_nr_rings = channel->rx_count;
1045 bp->tx_nr_rings_per_tc = channel->tx_count;
1046 }
1047 bp->tx_nr_rings_xdp = tx_xdp;
1048 bp->tx_nr_rings = bp->tx_nr_rings_per_tc + tx_xdp;
1049 if (tcs > 1)
1050 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs + tx_xdp;
1051
1052 bnxt_set_cp_rings(bp, sh);
1053
1054 /* After changing number of rx channels, update NTUPLE feature. */
1055 netdev_update_features(dev);
1056 if (netif_running(dev)) {
1057 rc = bnxt_open_nic(bp, true, false);
1058 if ((!rc) && BNXT_PF(bp)) {
1059 /* TODO CHIMP_FW: Send message to all VF's
1060 * to renable
1061 */
1062 }
1063 } else {
1064 rc = bnxt_reserve_rings(bp, true);
1065 }
1066
1067 return rc;
1068 }
1069
bnxt_get_all_fltr_ids_rcu(struct bnxt * bp,struct hlist_head tbl[],int tbl_size,u32 * ids,u32 start,u32 id_cnt)1070 static u32 bnxt_get_all_fltr_ids_rcu(struct bnxt *bp, struct hlist_head tbl[],
1071 int tbl_size, u32 *ids, u32 start,
1072 u32 id_cnt)
1073 {
1074 int i, j = start;
1075
1076 if (j >= id_cnt)
1077 return j;
1078 for (i = 0; i < tbl_size; i++) {
1079 struct hlist_head *head;
1080 struct bnxt_filter_base *fltr;
1081
1082 head = &tbl[i];
1083 hlist_for_each_entry_rcu(fltr, head, hash) {
1084 if (!fltr->flags ||
1085 test_bit(BNXT_FLTR_FW_DELETED, &fltr->state))
1086 continue;
1087 ids[j++] = fltr->sw_id;
1088 if (j == id_cnt)
1089 return j;
1090 }
1091 }
1092 return j;
1093 }
1094
bnxt_get_one_fltr_rcu(struct bnxt * bp,struct hlist_head tbl[],int tbl_size,u32 id)1095 static struct bnxt_filter_base *bnxt_get_one_fltr_rcu(struct bnxt *bp,
1096 struct hlist_head tbl[],
1097 int tbl_size, u32 id)
1098 {
1099 int i;
1100
1101 for (i = 0; i < tbl_size; i++) {
1102 struct hlist_head *head;
1103 struct bnxt_filter_base *fltr;
1104
1105 head = &tbl[i];
1106 hlist_for_each_entry_rcu(fltr, head, hash) {
1107 if (fltr->flags && fltr->sw_id == id)
1108 return fltr;
1109 }
1110 }
1111 return NULL;
1112 }
1113
bnxt_grxclsrlall(struct bnxt * bp,struct ethtool_rxnfc * cmd,u32 * rule_locs)1114 static int bnxt_grxclsrlall(struct bnxt *bp, struct ethtool_rxnfc *cmd,
1115 u32 *rule_locs)
1116 {
1117 u32 count;
1118
1119 cmd->data = bp->ntp_fltr_count;
1120 rcu_read_lock();
1121 count = bnxt_get_all_fltr_ids_rcu(bp, bp->l2_fltr_hash_tbl,
1122 BNXT_L2_FLTR_HASH_SIZE, rule_locs, 0,
1123 cmd->rule_cnt);
1124 cmd->rule_cnt = bnxt_get_all_fltr_ids_rcu(bp, bp->ntp_fltr_hash_tbl,
1125 BNXT_NTP_FLTR_HASH_SIZE,
1126 rule_locs, count,
1127 cmd->rule_cnt);
1128 rcu_read_unlock();
1129
1130 return 0;
1131 }
1132
bnxt_grxclsrule(struct bnxt * bp,struct ethtool_rxnfc * cmd)1133 static int bnxt_grxclsrule(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1134 {
1135 struct ethtool_rx_flow_spec *fs =
1136 (struct ethtool_rx_flow_spec *)&cmd->fs;
1137 struct bnxt_filter_base *fltr_base;
1138 struct bnxt_ntuple_filter *fltr;
1139 struct bnxt_flow_masks *fmasks;
1140 struct flow_keys *fkeys;
1141 int rc = -EINVAL;
1142
1143 if (fs->location >= bp->max_fltr)
1144 return rc;
1145
1146 rcu_read_lock();
1147 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl,
1148 BNXT_L2_FLTR_HASH_SIZE,
1149 fs->location);
1150 if (fltr_base) {
1151 struct ethhdr *h_ether = &fs->h_u.ether_spec;
1152 struct ethhdr *m_ether = &fs->m_u.ether_spec;
1153 struct bnxt_l2_filter *l2_fltr;
1154 struct bnxt_l2_key *l2_key;
1155
1156 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base);
1157 l2_key = &l2_fltr->l2_key;
1158 fs->flow_type = ETHER_FLOW;
1159 ether_addr_copy(h_ether->h_dest, l2_key->dst_mac_addr);
1160 eth_broadcast_addr(m_ether->h_dest);
1161 if (l2_key->vlan) {
1162 struct ethtool_flow_ext *m_ext = &fs->m_ext;
1163 struct ethtool_flow_ext *h_ext = &fs->h_ext;
1164
1165 fs->flow_type |= FLOW_EXT;
1166 m_ext->vlan_tci = htons(0xfff);
1167 h_ext->vlan_tci = htons(l2_key->vlan);
1168 }
1169 if (fltr_base->flags & BNXT_ACT_RING_DST)
1170 fs->ring_cookie = fltr_base->rxq;
1171 if (fltr_base->flags & BNXT_ACT_FUNC_DST)
1172 fs->ring_cookie = (u64)(fltr_base->vf_idx + 1) <<
1173 ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
1174 rcu_read_unlock();
1175 return 0;
1176 }
1177 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1178 BNXT_NTP_FLTR_HASH_SIZE,
1179 fs->location);
1180 if (!fltr_base) {
1181 rcu_read_unlock();
1182 return rc;
1183 }
1184 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1185
1186 fkeys = &fltr->fkeys;
1187 fmasks = &fltr->fmasks;
1188 if (fkeys->basic.n_proto == htons(ETH_P_IP)) {
1189 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) {
1190 fs->flow_type = IP_USER_FLOW;
1191 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
1192 fs->h_u.usr_ip4_spec.proto = BNXT_IP_PROTO_WILDCARD;
1193 fs->m_u.usr_ip4_spec.proto = 0;
1194 } else if (fkeys->basic.ip_proto == IPPROTO_ICMP) {
1195 fs->flow_type = IP_USER_FLOW;
1196 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
1197 fs->h_u.usr_ip4_spec.proto = IPPROTO_ICMP;
1198 fs->m_u.usr_ip4_spec.proto = BNXT_IP_PROTO_FULL_MASK;
1199 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) {
1200 fs->flow_type = TCP_V4_FLOW;
1201 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) {
1202 fs->flow_type = UDP_V4_FLOW;
1203 } else {
1204 goto fltr_err;
1205 }
1206
1207 fs->h_u.tcp_ip4_spec.ip4src = fkeys->addrs.v4addrs.src;
1208 fs->m_u.tcp_ip4_spec.ip4src = fmasks->addrs.v4addrs.src;
1209 fs->h_u.tcp_ip4_spec.ip4dst = fkeys->addrs.v4addrs.dst;
1210 fs->m_u.tcp_ip4_spec.ip4dst = fmasks->addrs.v4addrs.dst;
1211 if (fs->flow_type == TCP_V4_FLOW ||
1212 fs->flow_type == UDP_V4_FLOW) {
1213 fs->h_u.tcp_ip4_spec.psrc = fkeys->ports.src;
1214 fs->m_u.tcp_ip4_spec.psrc = fmasks->ports.src;
1215 fs->h_u.tcp_ip4_spec.pdst = fkeys->ports.dst;
1216 fs->m_u.tcp_ip4_spec.pdst = fmasks->ports.dst;
1217 }
1218 } else {
1219 if (fkeys->basic.ip_proto == BNXT_IP_PROTO_WILDCARD) {
1220 fs->flow_type = IPV6_USER_FLOW;
1221 fs->h_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_WILDCARD;
1222 fs->m_u.usr_ip6_spec.l4_proto = 0;
1223 } else if (fkeys->basic.ip_proto == IPPROTO_ICMPV6) {
1224 fs->flow_type = IPV6_USER_FLOW;
1225 fs->h_u.usr_ip6_spec.l4_proto = IPPROTO_ICMPV6;
1226 fs->m_u.usr_ip6_spec.l4_proto = BNXT_IP_PROTO_FULL_MASK;
1227 } else if (fkeys->basic.ip_proto == IPPROTO_TCP) {
1228 fs->flow_type = TCP_V6_FLOW;
1229 } else if (fkeys->basic.ip_proto == IPPROTO_UDP) {
1230 fs->flow_type = UDP_V6_FLOW;
1231 } else {
1232 goto fltr_err;
1233 }
1234
1235 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6src[0] =
1236 fkeys->addrs.v6addrs.src;
1237 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6src[0] =
1238 fmasks->addrs.v6addrs.src;
1239 *(struct in6_addr *)&fs->h_u.tcp_ip6_spec.ip6dst[0] =
1240 fkeys->addrs.v6addrs.dst;
1241 *(struct in6_addr *)&fs->m_u.tcp_ip6_spec.ip6dst[0] =
1242 fmasks->addrs.v6addrs.dst;
1243 if (fs->flow_type == TCP_V6_FLOW ||
1244 fs->flow_type == UDP_V6_FLOW) {
1245 fs->h_u.tcp_ip6_spec.psrc = fkeys->ports.src;
1246 fs->m_u.tcp_ip6_spec.psrc = fmasks->ports.src;
1247 fs->h_u.tcp_ip6_spec.pdst = fkeys->ports.dst;
1248 fs->m_u.tcp_ip6_spec.pdst = fmasks->ports.dst;
1249 }
1250 }
1251
1252 if (fltr->base.flags & BNXT_ACT_DROP) {
1253 fs->ring_cookie = RX_CLS_FLOW_DISC;
1254 } else if (fltr->base.flags & BNXT_ACT_RSS_CTX) {
1255 fs->flow_type |= FLOW_RSS;
1256 cmd->rss_context = fltr->base.fw_vnic_id;
1257 } else {
1258 fs->ring_cookie = fltr->base.rxq;
1259 }
1260 rc = 0;
1261
1262 fltr_err:
1263 rcu_read_unlock();
1264
1265 return rc;
1266 }
1267
bnxt_get_rss_ctx_from_index(struct bnxt * bp,u32 index)1268 static struct bnxt_rss_ctx *bnxt_get_rss_ctx_from_index(struct bnxt *bp,
1269 u32 index)
1270 {
1271 struct ethtool_rxfh_context *ctx;
1272
1273 ctx = xa_load(&bp->dev->ethtool->rss_ctx, index);
1274 if (!ctx)
1275 return NULL;
1276 return ethtool_rxfh_context_priv(ctx);
1277 }
1278
bnxt_alloc_vnic_rss_table(struct bnxt * bp,struct bnxt_vnic_info * vnic)1279 static int bnxt_alloc_vnic_rss_table(struct bnxt *bp,
1280 struct bnxt_vnic_info *vnic)
1281 {
1282 int size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
1283
1284 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
1285 vnic->rss_table = dma_alloc_coherent(&bp->pdev->dev,
1286 vnic->rss_table_size,
1287 &vnic->rss_table_dma_addr,
1288 GFP_KERNEL);
1289 if (!vnic->rss_table)
1290 return -ENOMEM;
1291
1292 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
1293 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
1294 return 0;
1295 }
1296
bnxt_add_l2_cls_rule(struct bnxt * bp,struct ethtool_rx_flow_spec * fs)1297 static int bnxt_add_l2_cls_rule(struct bnxt *bp,
1298 struct ethtool_rx_flow_spec *fs)
1299 {
1300 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1301 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1302 struct ethhdr *h_ether = &fs->h_u.ether_spec;
1303 struct ethhdr *m_ether = &fs->m_u.ether_spec;
1304 struct bnxt_l2_filter *fltr;
1305 struct bnxt_l2_key key;
1306 u16 vnic_id;
1307 u8 flags;
1308 int rc;
1309
1310 if (BNXT_CHIP_P5_PLUS(bp))
1311 return -EOPNOTSUPP;
1312
1313 if (!is_broadcast_ether_addr(m_ether->h_dest))
1314 return -EINVAL;
1315 ether_addr_copy(key.dst_mac_addr, h_ether->h_dest);
1316 key.vlan = 0;
1317 if (fs->flow_type & FLOW_EXT) {
1318 struct ethtool_flow_ext *m_ext = &fs->m_ext;
1319 struct ethtool_flow_ext *h_ext = &fs->h_ext;
1320
1321 if (m_ext->vlan_tci != htons(0xfff) || !h_ext->vlan_tci)
1322 return -EINVAL;
1323 key.vlan = ntohs(h_ext->vlan_tci);
1324 }
1325
1326 if (vf) {
1327 flags = BNXT_ACT_FUNC_DST;
1328 vnic_id = 0xffff;
1329 vf--;
1330 } else {
1331 flags = BNXT_ACT_RING_DST;
1332 vnic_id = bp->vnic_info[ring + 1].fw_vnic_id;
1333 }
1334 fltr = bnxt_alloc_new_l2_filter(bp, &key, flags);
1335 if (IS_ERR(fltr))
1336 return PTR_ERR(fltr);
1337
1338 fltr->base.fw_vnic_id = vnic_id;
1339 fltr->base.rxq = ring;
1340 fltr->base.vf_idx = vf;
1341 rc = bnxt_hwrm_l2_filter_alloc(bp, fltr);
1342 if (rc)
1343 bnxt_del_l2_filter(bp, fltr);
1344 else
1345 fs->location = fltr->base.sw_id;
1346 return rc;
1347 }
1348
bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec * ip_spec,struct ethtool_usrip4_spec * ip_mask)1349 static bool bnxt_verify_ntuple_ip4_flow(struct ethtool_usrip4_spec *ip_spec,
1350 struct ethtool_usrip4_spec *ip_mask)
1351 {
1352 u8 mproto = ip_mask->proto;
1353 u8 sproto = ip_spec->proto;
1354
1355 if (ip_mask->l4_4_bytes || ip_mask->tos ||
1356 ip_spec->ip_ver != ETH_RX_NFC_IP4 ||
1357 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMP)))
1358 return false;
1359 return true;
1360 }
1361
bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec * ip_spec,struct ethtool_usrip6_spec * ip_mask)1362 static bool bnxt_verify_ntuple_ip6_flow(struct ethtool_usrip6_spec *ip_spec,
1363 struct ethtool_usrip6_spec *ip_mask)
1364 {
1365 u8 mproto = ip_mask->l4_proto;
1366 u8 sproto = ip_spec->l4_proto;
1367
1368 if (ip_mask->l4_4_bytes || ip_mask->tclass ||
1369 (mproto && (mproto != BNXT_IP_PROTO_FULL_MASK || sproto != IPPROTO_ICMPV6)))
1370 return false;
1371 return true;
1372 }
1373
bnxt_add_ntuple_cls_rule(struct bnxt * bp,struct ethtool_rxnfc * cmd)1374 static int bnxt_add_ntuple_cls_rule(struct bnxt *bp,
1375 struct ethtool_rxnfc *cmd)
1376 {
1377 struct ethtool_rx_flow_spec *fs = &cmd->fs;
1378 struct bnxt_ntuple_filter *new_fltr, *fltr;
1379 u32 flow_type = fs->flow_type & 0xff;
1380 struct bnxt_l2_filter *l2_fltr;
1381 struct bnxt_flow_masks *fmasks;
1382 struct flow_keys *fkeys;
1383 u32 idx;
1384 int rc;
1385
1386 if (!bp->vnic_info)
1387 return -EAGAIN;
1388
1389 if (fs->flow_type & (FLOW_MAC_EXT | FLOW_EXT))
1390 return -EOPNOTSUPP;
1391
1392 if (fs->ring_cookie != RX_CLS_FLOW_DISC &&
1393 ethtool_get_flow_spec_ring_vf(fs->ring_cookie))
1394 return -EOPNOTSUPP;
1395
1396 if (flow_type == IP_USER_FLOW) {
1397 if (!bnxt_verify_ntuple_ip4_flow(&fs->h_u.usr_ip4_spec,
1398 &fs->m_u.usr_ip4_spec))
1399 return -EOPNOTSUPP;
1400 }
1401
1402 if (flow_type == IPV6_USER_FLOW) {
1403 if (!bnxt_verify_ntuple_ip6_flow(&fs->h_u.usr_ip6_spec,
1404 &fs->m_u.usr_ip6_spec))
1405 return -EOPNOTSUPP;
1406 }
1407
1408 new_fltr = kzalloc_obj(*new_fltr);
1409 if (!new_fltr)
1410 return -ENOMEM;
1411
1412 l2_fltr = bp->vnic_info[BNXT_VNIC_DEFAULT].l2_filters[0];
1413 atomic_inc(&l2_fltr->refcnt);
1414 new_fltr->l2_fltr = l2_fltr;
1415 fmasks = &new_fltr->fmasks;
1416 fkeys = &new_fltr->fkeys;
1417
1418 rc = -EOPNOTSUPP;
1419 switch (flow_type) {
1420 case IP_USER_FLOW: {
1421 struct ethtool_usrip4_spec *ip_spec = &fs->h_u.usr_ip4_spec;
1422 struct ethtool_usrip4_spec *ip_mask = &fs->m_u.usr_ip4_spec;
1423
1424 fkeys->basic.ip_proto = ip_mask->proto ? ip_spec->proto
1425 : BNXT_IP_PROTO_WILDCARD;
1426 fkeys->basic.n_proto = htons(ETH_P_IP);
1427 fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1428 fmasks->addrs.v4addrs.src = ip_mask->ip4src;
1429 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1430 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst;
1431 break;
1432 }
1433 case TCP_V4_FLOW:
1434 case UDP_V4_FLOW: {
1435 struct ethtool_tcpip4_spec *ip_spec = &fs->h_u.tcp_ip4_spec;
1436 struct ethtool_tcpip4_spec *ip_mask = &fs->m_u.tcp_ip4_spec;
1437
1438 fkeys->basic.ip_proto = IPPROTO_TCP;
1439 if (flow_type == UDP_V4_FLOW)
1440 fkeys->basic.ip_proto = IPPROTO_UDP;
1441 fkeys->basic.n_proto = htons(ETH_P_IP);
1442 fkeys->addrs.v4addrs.src = ip_spec->ip4src;
1443 fmasks->addrs.v4addrs.src = ip_mask->ip4src;
1444 fkeys->addrs.v4addrs.dst = ip_spec->ip4dst;
1445 fmasks->addrs.v4addrs.dst = ip_mask->ip4dst;
1446 fkeys->ports.src = ip_spec->psrc;
1447 fmasks->ports.src = ip_mask->psrc;
1448 fkeys->ports.dst = ip_spec->pdst;
1449 fmasks->ports.dst = ip_mask->pdst;
1450 break;
1451 }
1452 case IPV6_USER_FLOW: {
1453 struct ethtool_usrip6_spec *ip_spec = &fs->h_u.usr_ip6_spec;
1454 struct ethtool_usrip6_spec *ip_mask = &fs->m_u.usr_ip6_spec;
1455
1456 fkeys->basic.ip_proto = ip_mask->l4_proto ? ip_spec->l4_proto
1457 : BNXT_IP_PROTO_WILDCARD;
1458 fkeys->basic.n_proto = htons(ETH_P_IPV6);
1459 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src;
1460 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src;
1461 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst;
1462 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst;
1463 break;
1464 }
1465 case TCP_V6_FLOW:
1466 case UDP_V6_FLOW: {
1467 struct ethtool_tcpip6_spec *ip_spec = &fs->h_u.tcp_ip6_spec;
1468 struct ethtool_tcpip6_spec *ip_mask = &fs->m_u.tcp_ip6_spec;
1469
1470 fkeys->basic.ip_proto = IPPROTO_TCP;
1471 if (flow_type == UDP_V6_FLOW)
1472 fkeys->basic.ip_proto = IPPROTO_UDP;
1473 fkeys->basic.n_proto = htons(ETH_P_IPV6);
1474
1475 fkeys->addrs.v6addrs.src = *(struct in6_addr *)&ip_spec->ip6src;
1476 fmasks->addrs.v6addrs.src = *(struct in6_addr *)&ip_mask->ip6src;
1477 fkeys->addrs.v6addrs.dst = *(struct in6_addr *)&ip_spec->ip6dst;
1478 fmasks->addrs.v6addrs.dst = *(struct in6_addr *)&ip_mask->ip6dst;
1479 fkeys->ports.src = ip_spec->psrc;
1480 fmasks->ports.src = ip_mask->psrc;
1481 fkeys->ports.dst = ip_spec->pdst;
1482 fmasks->ports.dst = ip_mask->pdst;
1483 break;
1484 }
1485 default:
1486 rc = -EOPNOTSUPP;
1487 goto ntuple_err;
1488 }
1489 if (!memcmp(&BNXT_FLOW_MASK_NONE, fmasks, sizeof(*fmasks)))
1490 goto ntuple_err;
1491
1492 idx = bnxt_get_ntp_filter_idx(bp, fkeys, NULL);
1493 rcu_read_lock();
1494 fltr = bnxt_lookup_ntp_filter_from_idx(bp, new_fltr, idx);
1495 if (fltr) {
1496 rcu_read_unlock();
1497 rc = -EEXIST;
1498 goto ntuple_err;
1499 }
1500 rcu_read_unlock();
1501
1502 new_fltr->base.flags = BNXT_ACT_NO_AGING;
1503 if (fs->flow_type & FLOW_RSS) {
1504 struct bnxt_rss_ctx *rss_ctx;
1505
1506 new_fltr->base.fw_vnic_id = 0;
1507 new_fltr->base.flags |= BNXT_ACT_RSS_CTX;
1508 rss_ctx = bnxt_get_rss_ctx_from_index(bp, cmd->rss_context);
1509 if (rss_ctx) {
1510 new_fltr->base.fw_vnic_id = rss_ctx->index;
1511 } else {
1512 rc = -EINVAL;
1513 goto ntuple_err;
1514 }
1515 }
1516 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1517 new_fltr->base.flags |= BNXT_ACT_DROP;
1518 else
1519 new_fltr->base.rxq = ethtool_get_flow_spec_ring(fs->ring_cookie);
1520 __set_bit(BNXT_FLTR_VALID, &new_fltr->base.state);
1521 rc = bnxt_insert_ntp_filter(bp, new_fltr, idx);
1522 if (!rc) {
1523 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, new_fltr);
1524 if (rc) {
1525 bnxt_del_ntp_filter(bp, new_fltr);
1526 return rc;
1527 }
1528 fs->location = new_fltr->base.sw_id;
1529 return 0;
1530 }
1531
1532 ntuple_err:
1533 atomic_dec(&l2_fltr->refcnt);
1534 kfree(new_fltr);
1535 return rc;
1536 }
1537
bnxt_srxclsrlins(struct bnxt * bp,struct ethtool_rxnfc * cmd)1538 static int bnxt_srxclsrlins(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1539 {
1540 struct ethtool_rx_flow_spec *fs = &cmd->fs;
1541 u32 ring, flow_type;
1542 int rc;
1543 u8 vf;
1544
1545 if (!netif_running(bp->dev))
1546 return -EAGAIN;
1547 if (!(bp->flags & BNXT_FLAG_RFS))
1548 return -EPERM;
1549 if (fs->location != RX_CLS_LOC_ANY)
1550 return -EINVAL;
1551
1552 flow_type = fs->flow_type;
1553 if ((flow_type == IP_USER_FLOW ||
1554 flow_type == IPV6_USER_FLOW) &&
1555 !(bp->fw_cap & BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO))
1556 return -EOPNOTSUPP;
1557 if (flow_type & FLOW_MAC_EXT)
1558 return -EINVAL;
1559 flow_type &= ~FLOW_EXT;
1560
1561 if (fs->ring_cookie == RX_CLS_FLOW_DISC && flow_type != ETHER_FLOW)
1562 return bnxt_add_ntuple_cls_rule(bp, cmd);
1563
1564 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
1565 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
1566 if (BNXT_VF(bp) && vf)
1567 return -EINVAL;
1568 if (BNXT_PF(bp) && vf > bp->pf.active_vfs)
1569 return -EINVAL;
1570 if (!vf && ring >= bp->rx_nr_rings)
1571 return -EINVAL;
1572
1573 if (flow_type == ETHER_FLOW)
1574 rc = bnxt_add_l2_cls_rule(bp, fs);
1575 else
1576 rc = bnxt_add_ntuple_cls_rule(bp, cmd);
1577 return rc;
1578 }
1579
bnxt_srxclsrldel(struct bnxt * bp,struct ethtool_rxnfc * cmd)1580 static int bnxt_srxclsrldel(struct bnxt *bp, struct ethtool_rxnfc *cmd)
1581 {
1582 struct ethtool_rx_flow_spec *fs = &cmd->fs;
1583 struct bnxt_filter_base *fltr_base;
1584 struct bnxt_ntuple_filter *fltr;
1585 u32 id = fs->location;
1586
1587 rcu_read_lock();
1588 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->l2_fltr_hash_tbl,
1589 BNXT_L2_FLTR_HASH_SIZE, id);
1590 if (fltr_base) {
1591 struct bnxt_l2_filter *l2_fltr;
1592
1593 l2_fltr = container_of(fltr_base, struct bnxt_l2_filter, base);
1594 rcu_read_unlock();
1595 bnxt_hwrm_l2_filter_free(bp, l2_fltr);
1596 bnxt_del_l2_filter(bp, l2_fltr);
1597 return 0;
1598 }
1599 fltr_base = bnxt_get_one_fltr_rcu(bp, bp->ntp_fltr_hash_tbl,
1600 BNXT_NTP_FLTR_HASH_SIZE, id);
1601 if (!fltr_base) {
1602 rcu_read_unlock();
1603 return -ENOENT;
1604 }
1605
1606 fltr = container_of(fltr_base, struct bnxt_ntuple_filter, base);
1607 if (!(fltr->base.flags & BNXT_ACT_NO_AGING)) {
1608 rcu_read_unlock();
1609 return -EINVAL;
1610 }
1611 rcu_read_unlock();
1612 bnxt_hwrm_cfa_ntuple_filter_free(bp, fltr);
1613 bnxt_del_ntp_filter(bp, fltr);
1614 return 0;
1615 }
1616
get_ethtool_ipv4_rss(struct bnxt * bp)1617 static u64 get_ethtool_ipv4_rss(struct bnxt *bp)
1618 {
1619 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4)
1620 return RXH_IP_SRC | RXH_IP_DST;
1621 return 0;
1622 }
1623
get_ethtool_ipv6_rss(struct bnxt * bp)1624 static u64 get_ethtool_ipv6_rss(struct bnxt *bp)
1625 {
1626 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6)
1627 return RXH_IP_SRC | RXH_IP_DST;
1628 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL)
1629 return RXH_IP_SRC | RXH_IP_DST | RXH_IP6_FL;
1630 return 0;
1631 }
1632
bnxt_get_rxfh_fields(struct net_device * dev,struct ethtool_rxfh_fields * cmd)1633 static int bnxt_get_rxfh_fields(struct net_device *dev,
1634 struct ethtool_rxfh_fields *cmd)
1635 {
1636 struct bnxt *bp = netdev_priv(dev);
1637
1638 cmd->data = 0;
1639 switch (cmd->flow_type) {
1640 case TCP_V4_FLOW:
1641 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4)
1642 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1643 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1644 cmd->data |= get_ethtool_ipv4_rss(bp);
1645 break;
1646 case UDP_V4_FLOW:
1647 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4)
1648 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1649 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1650 fallthrough;
1651 case AH_ESP_V4_FLOW:
1652 if (bp->rss_hash_cfg &
1653 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1654 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4))
1655 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1656 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1657 fallthrough;
1658 case SCTP_V4_FLOW:
1659 case AH_V4_FLOW:
1660 case ESP_V4_FLOW:
1661 case IPV4_FLOW:
1662 cmd->data |= get_ethtool_ipv4_rss(bp);
1663 break;
1664
1665 case TCP_V6_FLOW:
1666 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6)
1667 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1668 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1669 cmd->data |= get_ethtool_ipv6_rss(bp);
1670 break;
1671 case UDP_V6_FLOW:
1672 if (bp->rss_hash_cfg & VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6)
1673 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1674 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1675 fallthrough;
1676 case AH_ESP_V6_FLOW:
1677 if (bp->rss_hash_cfg &
1678 (VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1679 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6))
1680 cmd->data |= RXH_IP_SRC | RXH_IP_DST |
1681 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1682 fallthrough;
1683 case SCTP_V6_FLOW:
1684 case AH_V6_FLOW:
1685 case ESP_V6_FLOW:
1686 case IPV6_FLOW:
1687 cmd->data |= get_ethtool_ipv6_rss(bp);
1688 break;
1689 }
1690 return 0;
1691 }
1692
1693 #define RXH_4TUPLE (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)
1694 #define RXH_2TUPLE (RXH_IP_SRC | RXH_IP_DST)
1695
bnxt_set_rxfh_fields(struct net_device * dev,const struct ethtool_rxfh_fields * cmd,struct netlink_ext_ack * extack)1696 static int bnxt_set_rxfh_fields(struct net_device *dev,
1697 const struct ethtool_rxfh_fields *cmd,
1698 struct netlink_ext_ack *extack)
1699 {
1700 struct bnxt *bp = netdev_priv(dev);
1701 int tuple, rc = 0;
1702 u32 rss_hash_cfg;
1703
1704 rss_hash_cfg = bp->rss_hash_cfg;
1705
1706 if (cmd->data == RXH_4TUPLE)
1707 tuple = 4;
1708 else if (cmd->data == RXH_2TUPLE ||
1709 cmd->data == (RXH_2TUPLE | RXH_IP6_FL))
1710 tuple = 2;
1711 else if (!cmd->data)
1712 tuple = 0;
1713 else
1714 return -EINVAL;
1715
1716 if (cmd->data & RXH_IP6_FL &&
1717 !(bp->rss_cap & BNXT_RSS_CAP_IPV6_FLOW_LABEL_RSS_CAP))
1718 return -EINVAL;
1719
1720 if (cmd->flow_type == TCP_V4_FLOW) {
1721 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1722 if (tuple == 4)
1723 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4;
1724 } else if (cmd->flow_type == UDP_V4_FLOW) {
1725 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1726 return -EINVAL;
1727 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1728 if (tuple == 4)
1729 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4;
1730 } else if (cmd->flow_type == TCP_V6_FLOW) {
1731 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1732 if (tuple == 4)
1733 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
1734 } else if (cmd->flow_type == UDP_V6_FLOW) {
1735 if (tuple == 4 && !(bp->rss_cap & BNXT_RSS_CAP_UDP_RSS_CAP))
1736 return -EINVAL;
1737 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1738 if (tuple == 4)
1739 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
1740 } else if (cmd->flow_type == AH_ESP_V4_FLOW) {
1741 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V4_RSS_CAP) ||
1742 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V4_RSS_CAP)))
1743 return -EINVAL;
1744 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1745 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4);
1746 if (tuple == 4)
1747 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 |
1748 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4;
1749 } else if (cmd->flow_type == AH_ESP_V6_FLOW) {
1750 if (tuple == 4 && (!(bp->rss_cap & BNXT_RSS_CAP_AH_V6_RSS_CAP) ||
1751 !(bp->rss_cap & BNXT_RSS_CAP_ESP_V6_RSS_CAP)))
1752 return -EINVAL;
1753 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1754 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6);
1755 if (tuple == 4)
1756 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 |
1757 VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6;
1758 } else if (tuple == 4) {
1759 return -EINVAL;
1760 }
1761
1762 switch (cmd->flow_type) {
1763 case TCP_V4_FLOW:
1764 case UDP_V4_FLOW:
1765 case SCTP_V4_FLOW:
1766 case AH_ESP_V4_FLOW:
1767 case AH_V4_FLOW:
1768 case ESP_V4_FLOW:
1769 case IPV4_FLOW:
1770 if (tuple == 2)
1771 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1772 else if (!tuple)
1773 rss_hash_cfg &= ~VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4;
1774 break;
1775
1776 case TCP_V6_FLOW:
1777 case UDP_V6_FLOW:
1778 case SCTP_V6_FLOW:
1779 case AH_ESP_V6_FLOW:
1780 case AH_V6_FLOW:
1781 case ESP_V6_FLOW:
1782 case IPV6_FLOW:
1783 rss_hash_cfg &= ~(VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
1784 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL);
1785 if (!tuple)
1786 break;
1787 if (cmd->data & RXH_IP6_FL)
1788 rss_hash_cfg |=
1789 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL;
1790 else if (tuple == 2)
1791 rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6;
1792 break;
1793 }
1794
1795 if (bp->rss_hash_cfg == rss_hash_cfg)
1796 return 0;
1797
1798 if (bp->rss_cap & BNXT_RSS_CAP_RSS_HASH_TYPE_DELTA)
1799 bp->rss_hash_delta = bp->rss_hash_cfg ^ rss_hash_cfg;
1800 bp->rss_hash_cfg = rss_hash_cfg;
1801 if (netif_running(bp->dev)) {
1802 bnxt_close_nic(bp, false, false);
1803 rc = bnxt_open_nic(bp, false, false);
1804 }
1805 return rc;
1806 }
1807
bnxt_get_rx_ring_count(struct net_device * dev)1808 static u32 bnxt_get_rx_ring_count(struct net_device *dev)
1809 {
1810 struct bnxt *bp = netdev_priv(dev);
1811
1812 return bp->rx_nr_rings;
1813 }
1814
bnxt_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)1815 static int bnxt_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1816 u32 *rule_locs)
1817 {
1818 struct bnxt *bp = netdev_priv(dev);
1819 int rc = 0;
1820
1821 switch (cmd->cmd) {
1822 case ETHTOOL_GRXCLSRLCNT:
1823 cmd->rule_cnt = bp->ntp_fltr_count;
1824 cmd->data = bp->max_fltr | RX_CLS_LOC_SPECIAL;
1825 break;
1826
1827 case ETHTOOL_GRXCLSRLALL:
1828 rc = bnxt_grxclsrlall(bp, cmd, (u32 *)rule_locs);
1829 break;
1830
1831 case ETHTOOL_GRXCLSRULE:
1832 rc = bnxt_grxclsrule(bp, cmd);
1833 break;
1834
1835 default:
1836 rc = -EOPNOTSUPP;
1837 break;
1838 }
1839
1840 return rc;
1841 }
1842
bnxt_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)1843 static int bnxt_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1844 {
1845 struct bnxt *bp = netdev_priv(dev);
1846 int rc;
1847
1848 switch (cmd->cmd) {
1849 case ETHTOOL_SRXCLSRLINS:
1850 rc = bnxt_srxclsrlins(bp, cmd);
1851 break;
1852
1853 case ETHTOOL_SRXCLSRLDEL:
1854 rc = bnxt_srxclsrldel(bp, cmd);
1855 break;
1856
1857 default:
1858 rc = -EOPNOTSUPP;
1859 break;
1860 }
1861 return rc;
1862 }
1863
bnxt_get_rxfh_indir_size(struct net_device * dev)1864 u32 bnxt_get_rxfh_indir_size(struct net_device *dev)
1865 {
1866 struct bnxt *bp = netdev_priv(dev);
1867
1868 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
1869 return bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) *
1870 BNXT_RSS_TABLE_ENTRIES_P5;
1871 return HW_HASH_INDEX_SIZE;
1872 }
1873
bnxt_get_rxfh_key_size(struct net_device * dev)1874 static u32 bnxt_get_rxfh_key_size(struct net_device *dev)
1875 {
1876 return HW_HASH_KEY_SIZE;
1877 }
1878
bnxt_get_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh)1879 static int bnxt_get_rxfh(struct net_device *dev,
1880 struct ethtool_rxfh_param *rxfh)
1881 {
1882 struct bnxt_rss_ctx *rss_ctx = NULL;
1883 struct bnxt *bp = netdev_priv(dev);
1884 u32 *indir_tbl = bp->rss_indir_tbl;
1885 struct bnxt_vnic_info *vnic;
1886 u32 i, tbl_size;
1887
1888 rxfh->hfunc = ETH_RSS_HASH_TOP;
1889
1890 if (!bp->vnic_info)
1891 return 0;
1892
1893 vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
1894 if (rxfh->rss_context) {
1895 struct ethtool_rxfh_context *ctx;
1896
1897 ctx = xa_load(&bp->dev->ethtool->rss_ctx, rxfh->rss_context);
1898 if (!ctx)
1899 return -EINVAL;
1900 indir_tbl = ethtool_rxfh_context_indir(ctx);
1901 rss_ctx = ethtool_rxfh_context_priv(ctx);
1902 vnic = &rss_ctx->vnic;
1903 }
1904
1905 if (rxfh->indir && indir_tbl) {
1906 tbl_size = bnxt_get_rxfh_indir_size(dev);
1907 for (i = 0; i < tbl_size; i++)
1908 rxfh->indir[i] = indir_tbl[i];
1909 }
1910
1911 if (rxfh->key && vnic->rss_hash_key)
1912 memcpy(rxfh->key, vnic->rss_hash_key, HW_HASH_KEY_SIZE);
1913
1914 return 0;
1915 }
1916
bnxt_modify_rss(struct bnxt * bp,struct ethtool_rxfh_context * ctx,struct bnxt_rss_ctx * rss_ctx,const struct ethtool_rxfh_param * rxfh)1917 static void bnxt_modify_rss(struct bnxt *bp, struct ethtool_rxfh_context *ctx,
1918 struct bnxt_rss_ctx *rss_ctx,
1919 const struct ethtool_rxfh_param *rxfh)
1920 {
1921 if (rxfh->key) {
1922 if (rss_ctx) {
1923 memcpy(rss_ctx->vnic.rss_hash_key, rxfh->key,
1924 HW_HASH_KEY_SIZE);
1925 } else {
1926 memcpy(bp->rss_hash_key, rxfh->key, HW_HASH_KEY_SIZE);
1927 bp->rss_hash_key_updated = true;
1928 }
1929 }
1930 if (rxfh->indir) {
1931 u32 i, pad, tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
1932 u32 *indir_tbl = bp->rss_indir_tbl;
1933
1934 if (rss_ctx)
1935 indir_tbl = ethtool_rxfh_context_indir(ctx);
1936 for (i = 0; i < tbl_size; i++)
1937 indir_tbl[i] = rxfh->indir[i];
1938 pad = bp->rss_indir_tbl_entries - tbl_size;
1939 if (pad)
1940 memset(&indir_tbl[i], 0, pad * sizeof(*indir_tbl));
1941 }
1942 }
1943
bnxt_rxfh_context_check(struct bnxt * bp,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1944 static int bnxt_rxfh_context_check(struct bnxt *bp,
1945 const struct ethtool_rxfh_param *rxfh,
1946 struct netlink_ext_ack *extack)
1947 {
1948 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP) {
1949 NL_SET_ERR_MSG_MOD(extack, "RSS hash function not supported");
1950 return -EOPNOTSUPP;
1951 }
1952
1953 if (!BNXT_SUPPORTS_MULTI_RSS_CTX(bp)) {
1954 NL_SET_ERR_MSG_MOD(extack, "RSS contexts not supported");
1955 return -EOPNOTSUPP;
1956 }
1957
1958 if (!netif_running(bp->dev)) {
1959 NL_SET_ERR_MSG_MOD(extack, "Unable to set RSS contexts when interface is down");
1960 return -EAGAIN;
1961 }
1962
1963 return 0;
1964 }
1965
bnxt_create_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)1966 static int bnxt_create_rxfh_context(struct net_device *dev,
1967 struct ethtool_rxfh_context *ctx,
1968 const struct ethtool_rxfh_param *rxfh,
1969 struct netlink_ext_ack *extack)
1970 {
1971 struct bnxt *bp = netdev_priv(dev);
1972 struct bnxt_rss_ctx *rss_ctx;
1973 struct bnxt_vnic_info *vnic;
1974 int rc;
1975
1976 rc = bnxt_rxfh_context_check(bp, rxfh, extack);
1977 if (rc)
1978 return rc;
1979
1980 if (bp->num_rss_ctx >= BNXT_MAX_ETH_RSS_CTX) {
1981 NL_SET_ERR_MSG_FMT_MOD(extack, "Out of RSS contexts, maximum %u",
1982 BNXT_MAX_ETH_RSS_CTX);
1983 return -EINVAL;
1984 }
1985
1986 if (!bnxt_rfs_capable(bp, true)) {
1987 NL_SET_ERR_MSG_MOD(extack, "Out hardware resources");
1988 return -ENOMEM;
1989 }
1990
1991 rss_ctx = ethtool_rxfh_context_priv(ctx);
1992
1993 bp->num_rss_ctx++;
1994
1995 vnic = &rss_ctx->vnic;
1996 vnic->rss_ctx = ctx;
1997 vnic->flags |= BNXT_VNIC_RSSCTX_FLAG;
1998 vnic->vnic_id = BNXT_VNIC_ID_INVALID;
1999 rc = bnxt_alloc_vnic_rss_table(bp, vnic);
2000 if (rc)
2001 goto out;
2002
2003 /* Populate defaults in the context */
2004 bnxt_set_dflt_rss_indir_tbl(bp, ctx);
2005 ctx->hfunc = ETH_RSS_HASH_TOP;
2006 memcpy(vnic->rss_hash_key, bp->rss_hash_key, HW_HASH_KEY_SIZE);
2007 memcpy(ethtool_rxfh_context_key(ctx),
2008 bp->rss_hash_key, HW_HASH_KEY_SIZE);
2009
2010 rc = bnxt_hwrm_vnic_alloc(bp, vnic, 0, bp->rx_nr_rings);
2011 if (rc) {
2012 NL_SET_ERR_MSG_MOD(extack, "Unable to allocate VNIC");
2013 goto out;
2014 }
2015
2016 rc = bnxt_hwrm_vnic_set_tpa(bp, vnic, bp->flags & BNXT_FLAG_TPA);
2017 if (rc) {
2018 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA");
2019 goto out;
2020 }
2021 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh);
2022
2023 rc = __bnxt_setup_vnic_p5(bp, vnic);
2024 if (rc) {
2025 NL_SET_ERR_MSG_MOD(extack, "Unable to setup TPA");
2026 goto out;
2027 }
2028
2029 rss_ctx->index = rxfh->rss_context;
2030 return 0;
2031 out:
2032 bnxt_del_one_rss_ctx(bp, rss_ctx, true);
2033 return rc;
2034 }
2035
bnxt_modify_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,const struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)2036 static int bnxt_modify_rxfh_context(struct net_device *dev,
2037 struct ethtool_rxfh_context *ctx,
2038 const struct ethtool_rxfh_param *rxfh,
2039 struct netlink_ext_ack *extack)
2040 {
2041 struct bnxt *bp = netdev_priv(dev);
2042 struct bnxt_rss_ctx *rss_ctx;
2043 int rc;
2044
2045 rc = bnxt_rxfh_context_check(bp, rxfh, extack);
2046 if (rc)
2047 return rc;
2048
2049 rss_ctx = ethtool_rxfh_context_priv(ctx);
2050
2051 bnxt_modify_rss(bp, ctx, rss_ctx, rxfh);
2052
2053 return bnxt_hwrm_vnic_rss_cfg_p5(bp, &rss_ctx->vnic);
2054 }
2055
bnxt_remove_rxfh_context(struct net_device * dev,struct ethtool_rxfh_context * ctx,u32 rss_context,struct netlink_ext_ack * extack)2056 static int bnxt_remove_rxfh_context(struct net_device *dev,
2057 struct ethtool_rxfh_context *ctx,
2058 u32 rss_context,
2059 struct netlink_ext_ack *extack)
2060 {
2061 struct bnxt *bp = netdev_priv(dev);
2062 struct bnxt_rss_ctx *rss_ctx;
2063
2064 rss_ctx = ethtool_rxfh_context_priv(ctx);
2065
2066 bnxt_del_one_rss_ctx(bp, rss_ctx, true);
2067 return 0;
2068 }
2069
bnxt_set_rxfh(struct net_device * dev,struct ethtool_rxfh_param * rxfh,struct netlink_ext_ack * extack)2070 static int bnxt_set_rxfh(struct net_device *dev,
2071 struct ethtool_rxfh_param *rxfh,
2072 struct netlink_ext_ack *extack)
2073 {
2074 struct bnxt *bp = netdev_priv(dev);
2075 int rc = 0;
2076
2077 if (rxfh->hfunc && rxfh->hfunc != ETH_RSS_HASH_TOP)
2078 return -EOPNOTSUPP;
2079
2080 bnxt_modify_rss(bp, NULL, NULL, rxfh);
2081
2082 if (netif_running(bp->dev)) {
2083 bnxt_close_nic(bp, false, false);
2084 rc = bnxt_open_nic(bp, false, false);
2085 }
2086 return rc;
2087 }
2088
bnxt_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)2089 static void bnxt_get_drvinfo(struct net_device *dev,
2090 struct ethtool_drvinfo *info)
2091 {
2092 struct bnxt *bp = netdev_priv(dev);
2093
2094 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
2095 strscpy(info->fw_version, bp->fw_ver_str, sizeof(info->fw_version));
2096 strscpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
2097 info->n_stats = bnxt_get_num_stats(bp);
2098 info->testinfo_len = bp->num_tests;
2099 /* TODO CHIMP_FW: eeprom dump details */
2100 info->eedump_len = 0;
2101 /* TODO CHIMP FW: reg dump details */
2102 info->regdump_len = 0;
2103 }
2104
bnxt_get_regs_len(struct net_device * dev)2105 static int bnxt_get_regs_len(struct net_device *dev)
2106 {
2107 struct bnxt *bp = netdev_priv(dev);
2108
2109 if (!BNXT_PF(bp))
2110 return -EOPNOTSUPP;
2111
2112 return BNXT_PXP_REG_LEN + bp->pcie_stat_len;
2113 }
2114
2115 static void *
__bnxt_hwrm_pcie_qstats(struct bnxt * bp,struct hwrm_pcie_qstats_input * req)2116 __bnxt_hwrm_pcie_qstats(struct bnxt *bp, struct hwrm_pcie_qstats_input *req)
2117 {
2118 struct pcie_ctx_hw_stats_v2 *hw_pcie_stats;
2119 dma_addr_t hw_pcie_stats_addr;
2120 int rc;
2121
2122 hw_pcie_stats = hwrm_req_dma_slice(bp, req, sizeof(*hw_pcie_stats),
2123 &hw_pcie_stats_addr);
2124 if (!hw_pcie_stats)
2125 return NULL;
2126
2127 req->pcie_stat_size = cpu_to_le16(sizeof(*hw_pcie_stats));
2128 req->pcie_stat_host_addr = cpu_to_le64(hw_pcie_stats_addr);
2129 rc = hwrm_req_send(bp, req);
2130
2131 return rc ? NULL : hw_pcie_stats;
2132 }
2133
2134 #define BNXT_PCIE_32B_ENTRY(start, end) \
2135 { offsetof(struct pcie_ctx_hw_stats_v2, start),\
2136 offsetof(struct pcie_ctx_hw_stats_v2, end) }
2137
2138 static const struct {
2139 u16 start;
2140 u16 end;
2141 } bnxt_pcie_32b_entries[] = {
2142 BNXT_PCIE_32B_ENTRY(pcie_ltssm_histogram[0], pcie_ltssm_histogram[3]),
2143 BNXT_PCIE_32B_ENTRY(pcie_tl_credit_nph_histogram[0], unused_1),
2144 BNXT_PCIE_32B_ENTRY(pcie_rd_latency_histogram[0], unused_2),
2145 };
2146
bnxt_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * _p)2147 static void bnxt_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2148 void *_p)
2149 {
2150 struct hwrm_pcie_qstats_output *resp;
2151 struct hwrm_pcie_qstats_input *req;
2152 struct bnxt *bp = netdev_priv(dev);
2153 u8 *src;
2154
2155 regs->version = 0;
2156 if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED))
2157 bnxt_dbg_hwrm_rd_reg(bp, 0, BNXT_PXP_REG_LEN / 4, _p);
2158
2159 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
2160 return;
2161
2162 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
2163 return;
2164
2165 resp = hwrm_req_hold(bp, req);
2166 src = __bnxt_hwrm_pcie_qstats(bp, req);
2167 if (src) {
2168 u8 *dst = (u8 *)(_p + BNXT_PXP_REG_LEN);
2169 int i, j, len;
2170
2171 len = min(bp->pcie_stat_len, le16_to_cpu(resp->pcie_stat_size));
2172 if (len <= sizeof(struct pcie_ctx_hw_stats))
2173 regs->version = 1;
2174 else if (len < sizeof(struct pcie_ctx_hw_stats_v2))
2175 regs->version = 2;
2176 else
2177 regs->version = 3;
2178
2179 for (i = 0, j = 0; i < len; ) {
2180 if (i >= bnxt_pcie_32b_entries[j].start &&
2181 i <= bnxt_pcie_32b_entries[j].end) {
2182 u32 *dst32 = (u32 *)(dst + i);
2183
2184 *dst32 = le32_to_cpu(*(__le32 *)(src + i));
2185 i += 4;
2186 if (i > bnxt_pcie_32b_entries[j].end &&
2187 j < ARRAY_SIZE(bnxt_pcie_32b_entries) - 1)
2188 j++;
2189 } else {
2190 u64 *dst64 = (u64 *)(dst + i);
2191
2192 *dst64 = le64_to_cpu(*(__le64 *)(src + i));
2193 i += 8;
2194 }
2195 }
2196 }
2197 hwrm_req_drop(bp, req);
2198 }
2199
bnxt_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)2200 static void bnxt_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2201 {
2202 struct bnxt *bp = netdev_priv(dev);
2203
2204 wol->supported = 0;
2205 wol->wolopts = 0;
2206 memset(&wol->sopass, 0, sizeof(wol->sopass));
2207 if (bp->flags & BNXT_FLAG_WOL_CAP) {
2208 wol->supported = WAKE_MAGIC;
2209 if (bp->wol)
2210 wol->wolopts = WAKE_MAGIC;
2211 }
2212 }
2213
bnxt_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)2214 static int bnxt_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2215 {
2216 struct bnxt *bp = netdev_priv(dev);
2217
2218 if (wol->wolopts & ~WAKE_MAGIC)
2219 return -EINVAL;
2220
2221 if (wol->wolopts & WAKE_MAGIC) {
2222 if (!(bp->flags & BNXT_FLAG_WOL_CAP))
2223 return -EINVAL;
2224 if (!bp->wol) {
2225 if (bnxt_hwrm_alloc_wol_fltr(bp))
2226 return -EBUSY;
2227 bp->wol = 1;
2228 }
2229 } else {
2230 if (bp->wol) {
2231 if (bnxt_hwrm_free_wol_fltr(bp))
2232 return -EBUSY;
2233 bp->wol = 0;
2234 }
2235 }
2236 return 0;
2237 }
2238
2239 /* TODO: support 25GB, 40GB, 50GB with different cable type */
_bnxt_fw_to_linkmode(unsigned long * mode,u16 fw_speeds)2240 void _bnxt_fw_to_linkmode(unsigned long *mode, u16 fw_speeds)
2241 {
2242 linkmode_zero(mode);
2243
2244 if (fw_speeds & BNXT_LINK_SPEED_MSK_100MB)
2245 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode);
2246 if (fw_speeds & BNXT_LINK_SPEED_MSK_1GB)
2247 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode);
2248 if (fw_speeds & BNXT_LINK_SPEED_MSK_2_5GB)
2249 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, mode);
2250 if (fw_speeds & BNXT_LINK_SPEED_MSK_10GB)
2251 linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode);
2252 if (fw_speeds & BNXT_LINK_SPEED_MSK_40GB)
2253 linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode);
2254 }
2255
2256 enum bnxt_media_type {
2257 BNXT_MEDIA_UNKNOWN = 0,
2258 BNXT_MEDIA_TP,
2259 BNXT_MEDIA_CR,
2260 BNXT_MEDIA_SR,
2261 BNXT_MEDIA_LR_ER_FR,
2262 BNXT_MEDIA_KR,
2263 BNXT_MEDIA_KX,
2264 BNXT_MEDIA_X,
2265 __BNXT_MEDIA_END,
2266 };
2267
2268 static const enum bnxt_media_type bnxt_phy_types[] = {
2269 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR] = BNXT_MEDIA_CR,
2270 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4] = BNXT_MEDIA_KR,
2271 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR] = BNXT_MEDIA_LR_ER_FR,
2272 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR] = BNXT_MEDIA_SR,
2273 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2] = BNXT_MEDIA_KR,
2274 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX] = BNXT_MEDIA_KX,
2275 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR] = BNXT_MEDIA_KR,
2276 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASET] = BNXT_MEDIA_TP,
2277 [PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE] = BNXT_MEDIA_TP,
2278 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L] = BNXT_MEDIA_CR,
2279 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S] = BNXT_MEDIA_CR,
2280 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N] = BNXT_MEDIA_CR,
2281 [PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR] = BNXT_MEDIA_SR,
2282 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4] = BNXT_MEDIA_CR,
2283 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4] = BNXT_MEDIA_SR,
2284 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2285 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2286 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10] = BNXT_MEDIA_SR,
2287 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4] = BNXT_MEDIA_CR,
2288 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4] = BNXT_MEDIA_SR,
2289 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2290 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2291 [PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE] = BNXT_MEDIA_SR,
2292 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET] = BNXT_MEDIA_TP,
2293 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX] = BNXT_MEDIA_X,
2294 [PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX] = BNXT_MEDIA_X,
2295 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4] = BNXT_MEDIA_CR,
2296 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4] = BNXT_MEDIA_SR,
2297 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2298 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2299 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR] = BNXT_MEDIA_CR,
2300 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR] = BNXT_MEDIA_SR,
2301 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR] = BNXT_MEDIA_LR_ER_FR,
2302 [PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER] = BNXT_MEDIA_LR_ER_FR,
2303 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2] = BNXT_MEDIA_CR,
2304 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2] = BNXT_MEDIA_SR,
2305 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
2306 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
2307 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR] = BNXT_MEDIA_CR,
2308 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR] = BNXT_MEDIA_SR,
2309 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR] = BNXT_MEDIA_LR_ER_FR,
2310 [PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER] = BNXT_MEDIA_LR_ER_FR,
2311 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2] = BNXT_MEDIA_CR,
2312 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2] = BNXT_MEDIA_SR,
2313 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2] = BNXT_MEDIA_LR_ER_FR,
2314 [PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2] = BNXT_MEDIA_LR_ER_FR,
2315 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8] = BNXT_MEDIA_CR,
2316 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8] = BNXT_MEDIA_SR,
2317 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8] = BNXT_MEDIA_LR_ER_FR,
2318 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8] = BNXT_MEDIA_LR_ER_FR,
2319 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4] = BNXT_MEDIA_CR,
2320 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4] = BNXT_MEDIA_SR,
2321 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4] = BNXT_MEDIA_LR_ER_FR,
2322 [PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4] = BNXT_MEDIA_LR_ER_FR,
2323 };
2324
2325 static enum bnxt_media_type
bnxt_get_media(struct bnxt_link_info * link_info)2326 bnxt_get_media(struct bnxt_link_info *link_info)
2327 {
2328 switch (link_info->media_type) {
2329 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP:
2330 return BNXT_MEDIA_TP;
2331 case PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC:
2332 return BNXT_MEDIA_CR;
2333 default:
2334 if (link_info->phy_type < ARRAY_SIZE(bnxt_phy_types))
2335 return bnxt_phy_types[link_info->phy_type];
2336 return BNXT_MEDIA_UNKNOWN;
2337 }
2338 }
2339
2340 enum bnxt_link_speed_indices {
2341 BNXT_LINK_SPEED_UNKNOWN = 0,
2342 BNXT_LINK_SPEED_100MB_IDX,
2343 BNXT_LINK_SPEED_1GB_IDX,
2344 BNXT_LINK_SPEED_10GB_IDX,
2345 BNXT_LINK_SPEED_25GB_IDX,
2346 BNXT_LINK_SPEED_40GB_IDX,
2347 BNXT_LINK_SPEED_50GB_IDX,
2348 BNXT_LINK_SPEED_100GB_IDX,
2349 BNXT_LINK_SPEED_200GB_IDX,
2350 BNXT_LINK_SPEED_400GB_IDX,
2351 __BNXT_LINK_SPEED_END
2352 };
2353
bnxt_fw_speed_idx(u16 speed)2354 static enum bnxt_link_speed_indices bnxt_fw_speed_idx(u16 speed)
2355 {
2356 switch (speed) {
2357 case BNXT_LINK_SPEED_100MB: return BNXT_LINK_SPEED_100MB_IDX;
2358 case BNXT_LINK_SPEED_1GB: return BNXT_LINK_SPEED_1GB_IDX;
2359 case BNXT_LINK_SPEED_10GB: return BNXT_LINK_SPEED_10GB_IDX;
2360 case BNXT_LINK_SPEED_25GB: return BNXT_LINK_SPEED_25GB_IDX;
2361 case BNXT_LINK_SPEED_40GB: return BNXT_LINK_SPEED_40GB_IDX;
2362 case BNXT_LINK_SPEED_50GB:
2363 case BNXT_LINK_SPEED_50GB_PAM4:
2364 return BNXT_LINK_SPEED_50GB_IDX;
2365 case BNXT_LINK_SPEED_100GB:
2366 case BNXT_LINK_SPEED_100GB_PAM4:
2367 case BNXT_LINK_SPEED_100GB_PAM4_112:
2368 return BNXT_LINK_SPEED_100GB_IDX;
2369 case BNXT_LINK_SPEED_200GB:
2370 case BNXT_LINK_SPEED_200GB_PAM4:
2371 case BNXT_LINK_SPEED_200GB_PAM4_112:
2372 return BNXT_LINK_SPEED_200GB_IDX;
2373 case BNXT_LINK_SPEED_400GB:
2374 case BNXT_LINK_SPEED_400GB_PAM4:
2375 case BNXT_LINK_SPEED_400GB_PAM4_112:
2376 return BNXT_LINK_SPEED_400GB_IDX;
2377 default: return BNXT_LINK_SPEED_UNKNOWN;
2378 }
2379 }
2380
2381 static const enum ethtool_link_mode_bit_indices
2382 bnxt_link_modes[__BNXT_LINK_SPEED_END][BNXT_SIG_MODE_MAX][__BNXT_MEDIA_END] = {
2383 [BNXT_LINK_SPEED_100MB_IDX] = {
2384 {
2385 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2386 },
2387 },
2388 [BNXT_LINK_SPEED_1GB_IDX] = {
2389 {
2390 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2391 /* historically baseT, but DAC is more correctly baseX */
2392 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2393 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2394 [BNXT_MEDIA_X] = ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
2395 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2396 },
2397 },
2398 [BNXT_LINK_SPEED_10GB_IDX] = {
2399 {
2400 [BNXT_MEDIA_TP] = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2401 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2402 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2403 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2404 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2405 [BNXT_MEDIA_KX] = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2406 },
2407 },
2408 [BNXT_LINK_SPEED_25GB_IDX] = {
2409 {
2410 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2411 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2412 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2413 },
2414 },
2415 [BNXT_LINK_SPEED_40GB_IDX] = {
2416 {
2417 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2418 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2419 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2420 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2421 },
2422 },
2423 [BNXT_LINK_SPEED_50GB_IDX] = {
2424 [BNXT_SIG_MODE_NRZ] = {
2425 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2426 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2427 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2428 },
2429 [BNXT_SIG_MODE_PAM4] = {
2430 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2431 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2432 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2433 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2434 },
2435 },
2436 [BNXT_LINK_SPEED_100GB_IDX] = {
2437 [BNXT_SIG_MODE_NRZ] = {
2438 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2439 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2440 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2441 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2442 },
2443 [BNXT_SIG_MODE_PAM4] = {
2444 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2445 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2446 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2447 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2448 },
2449 [BNXT_SIG_MODE_PAM4_112] = {
2450 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_100000baseCR_Full_BIT,
2451 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
2452 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
2453 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
2454 },
2455 },
2456 [BNXT_LINK_SPEED_200GB_IDX] = {
2457 [BNXT_SIG_MODE_PAM4] = {
2458 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2459 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2460 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2461 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2462 },
2463 [BNXT_SIG_MODE_PAM4_112] = {
2464 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT,
2465 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
2466 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
2467 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
2468 },
2469 },
2470 [BNXT_LINK_SPEED_400GB_IDX] = {
2471 [BNXT_SIG_MODE_PAM4] = {
2472 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
2473 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
2474 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
2475 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
2476 },
2477 [BNXT_SIG_MODE_PAM4_112] = {
2478 [BNXT_MEDIA_CR] = ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT,
2479 [BNXT_MEDIA_KR] = ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
2480 [BNXT_MEDIA_SR] = ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
2481 [BNXT_MEDIA_LR_ER_FR] = ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
2482 },
2483 },
2484 };
2485
2486 #define BNXT_LINK_MODE_UNKNOWN -1
2487
2488 static enum ethtool_link_mode_bit_indices
bnxt_get_link_mode(struct bnxt_link_info * link_info)2489 bnxt_get_link_mode(struct bnxt_link_info *link_info)
2490 {
2491 enum ethtool_link_mode_bit_indices link_mode;
2492 enum bnxt_link_speed_indices speed;
2493 enum bnxt_media_type media;
2494 u8 sig_mode;
2495
2496 if (link_info->phy_link_status != BNXT_LINK_LINK)
2497 return BNXT_LINK_MODE_UNKNOWN;
2498
2499 media = bnxt_get_media(link_info);
2500 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
2501 speed = bnxt_fw_speed_idx(link_info->link_speed);
2502 sig_mode = link_info->active_fec_sig_mode &
2503 PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK;
2504 } else {
2505 speed = bnxt_fw_speed_idx(link_info->req_link_speed);
2506 sig_mode = link_info->req_signal_mode;
2507 }
2508 if (sig_mode >= BNXT_SIG_MODE_MAX)
2509 return BNXT_LINK_MODE_UNKNOWN;
2510
2511 /* Note ETHTOOL_LINK_MODE_10baseT_Half_BIT == 0 is a legal Linux
2512 * link mode, but since no such devices exist, the zeroes in the
2513 * map can be conveniently used to represent unknown link modes.
2514 */
2515 link_mode = bnxt_link_modes[speed][sig_mode][media];
2516 if (!link_mode)
2517 return BNXT_LINK_MODE_UNKNOWN;
2518
2519 switch (link_mode) {
2520 case ETHTOOL_LINK_MODE_100baseT_Full_BIT:
2521 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2522 link_mode = ETHTOOL_LINK_MODE_100baseT_Half_BIT;
2523 break;
2524 case ETHTOOL_LINK_MODE_1000baseT_Full_BIT:
2525 if (~link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2526 link_mode = ETHTOOL_LINK_MODE_1000baseT_Half_BIT;
2527 break;
2528 default:
2529 break;
2530 }
2531
2532 return link_mode;
2533 }
2534
bnxt_get_ethtool_modes(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)2535 static void bnxt_get_ethtool_modes(struct bnxt_link_info *link_info,
2536 struct ethtool_link_ksettings *lk_ksettings)
2537 {
2538 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2539
2540 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE)) {
2541 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2542 lk_ksettings->link_modes.supported);
2543 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2544 lk_ksettings->link_modes.supported);
2545 }
2546
2547 if (link_info->support_auto_speeds || link_info->support_auto_speeds2 ||
2548 link_info->support_pam4_auto_speeds)
2549 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2550 lk_ksettings->link_modes.supported);
2551
2552 if (~link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
2553 return;
2554
2555 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_RX)
2556 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2557 lk_ksettings->link_modes.advertising);
2558 if (hweight8(link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) == 1)
2559 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2560 lk_ksettings->link_modes.advertising);
2561 if (link_info->lp_pause & BNXT_LINK_PAUSE_RX)
2562 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2563 lk_ksettings->link_modes.lp_advertising);
2564 if (hweight8(link_info->lp_pause & BNXT_LINK_PAUSE_BOTH) == 1)
2565 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2566 lk_ksettings->link_modes.lp_advertising);
2567 }
2568
2569 static const u16 bnxt_nrz_speed_masks[] = {
2570 [BNXT_LINK_SPEED_100MB_IDX] = BNXT_LINK_SPEED_MSK_100MB,
2571 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEED_MSK_1GB,
2572 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEED_MSK_10GB,
2573 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEED_MSK_25GB,
2574 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEED_MSK_40GB,
2575 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEED_MSK_50GB,
2576 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEED_MSK_100GB,
2577 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2578 };
2579
2580 static const u16 bnxt_pam4_speed_masks[] = {
2581 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_50GB,
2582 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_100GB,
2583 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_PAM4_SPEED_MSK_200GB,
2584 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2585 };
2586
2587 static const u16 bnxt_nrz_speeds2_masks[] = {
2588 [BNXT_LINK_SPEED_1GB_IDX] = BNXT_LINK_SPEEDS2_MSK_1GB,
2589 [BNXT_LINK_SPEED_10GB_IDX] = BNXT_LINK_SPEEDS2_MSK_10GB,
2590 [BNXT_LINK_SPEED_25GB_IDX] = BNXT_LINK_SPEEDS2_MSK_25GB,
2591 [BNXT_LINK_SPEED_40GB_IDX] = BNXT_LINK_SPEEDS2_MSK_40GB,
2592 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB,
2593 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB,
2594 [__BNXT_LINK_SPEED_END - 1] = 0 /* make any legal speed a valid index */
2595 };
2596
2597 static const u16 bnxt_pam4_speeds2_masks[] = {
2598 [BNXT_LINK_SPEED_50GB_IDX] = BNXT_LINK_SPEEDS2_MSK_50GB_PAM4,
2599 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4,
2600 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4,
2601 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4,
2602 };
2603
2604 static const u16 bnxt_pam4_112_speeds2_masks[] = {
2605 [BNXT_LINK_SPEED_100GB_IDX] = BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112,
2606 [BNXT_LINK_SPEED_200GB_IDX] = BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112,
2607 [BNXT_LINK_SPEED_400GB_IDX] = BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112,
2608 };
2609
2610 static enum bnxt_link_speed_indices
bnxt_encoding_speed_idx(u8 sig_mode,u16 phy_flags,u16 speed_msk)2611 bnxt_encoding_speed_idx(u8 sig_mode, u16 phy_flags, u16 speed_msk)
2612 {
2613 const u16 *speeds;
2614 int idx, len;
2615
2616 switch (sig_mode) {
2617 case BNXT_SIG_MODE_NRZ:
2618 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2619 speeds = bnxt_nrz_speeds2_masks;
2620 len = ARRAY_SIZE(bnxt_nrz_speeds2_masks);
2621 } else {
2622 speeds = bnxt_nrz_speed_masks;
2623 len = ARRAY_SIZE(bnxt_nrz_speed_masks);
2624 }
2625 break;
2626 case BNXT_SIG_MODE_PAM4:
2627 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2628 speeds = bnxt_pam4_speeds2_masks;
2629 len = ARRAY_SIZE(bnxt_pam4_speeds2_masks);
2630 } else {
2631 speeds = bnxt_pam4_speed_masks;
2632 len = ARRAY_SIZE(bnxt_pam4_speed_masks);
2633 }
2634 break;
2635 case BNXT_SIG_MODE_PAM4_112:
2636 speeds = bnxt_pam4_112_speeds2_masks;
2637 len = ARRAY_SIZE(bnxt_pam4_112_speeds2_masks);
2638 break;
2639 default:
2640 return BNXT_LINK_SPEED_UNKNOWN;
2641 }
2642
2643 for (idx = 0; idx < len; idx++) {
2644 if (speeds[idx] == speed_msk)
2645 return idx;
2646 }
2647
2648 return BNXT_LINK_SPEED_UNKNOWN;
2649 }
2650
2651 #define BNXT_FW_SPEED_MSK_BITS 16
2652
2653 static void
__bnxt_get_ethtool_speeds(unsigned long fw_mask,enum bnxt_media_type media,u8 sig_mode,u16 phy_flags,unsigned long * et_mask)2654 __bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2655 u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2656 {
2657 enum ethtool_link_mode_bit_indices link_mode;
2658 enum bnxt_link_speed_indices speed;
2659 u8 bit;
2660
2661 for_each_set_bit(bit, &fw_mask, BNXT_FW_SPEED_MSK_BITS) {
2662 speed = bnxt_encoding_speed_idx(sig_mode, phy_flags, 1 << bit);
2663 if (!speed)
2664 continue;
2665
2666 link_mode = bnxt_link_modes[speed][sig_mode][media];
2667 if (!link_mode)
2668 continue;
2669
2670 linkmode_set_bit(link_mode, et_mask);
2671 }
2672 }
2673
2674 static void
bnxt_get_ethtool_speeds(unsigned long fw_mask,enum bnxt_media_type media,u8 sig_mode,u16 phy_flags,unsigned long * et_mask)2675 bnxt_get_ethtool_speeds(unsigned long fw_mask, enum bnxt_media_type media,
2676 u8 sig_mode, u16 phy_flags, unsigned long *et_mask)
2677 {
2678 if (media) {
2679 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2680 et_mask);
2681 return;
2682 }
2683
2684 /* list speeds for all media if unknown */
2685 for (media = 1; media < __BNXT_MEDIA_END; media++)
2686 __bnxt_get_ethtool_speeds(fw_mask, media, sig_mode, phy_flags,
2687 et_mask);
2688 }
2689
2690 static void
bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info * link_info,enum bnxt_media_type media,struct ethtool_link_ksettings * lk_ksettings)2691 bnxt_get_all_ethtool_support_speeds(struct bnxt_link_info *link_info,
2692 enum bnxt_media_type media,
2693 struct ethtool_link_ksettings *lk_ksettings)
2694 {
2695 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2696 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2697 u16 phy_flags = bp->phy_flags;
2698
2699 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2700 sp_nrz = link_info->support_speeds2;
2701 sp_pam4 = link_info->support_speeds2;
2702 sp_pam4_112 = link_info->support_speeds2;
2703 } else {
2704 sp_nrz = link_info->support_speeds;
2705 sp_pam4 = link_info->support_pam4_speeds;
2706 }
2707 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2708 lk_ksettings->link_modes.supported);
2709 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2710 lk_ksettings->link_modes.supported);
2711 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2712 phy_flags, lk_ksettings->link_modes.supported);
2713 }
2714
2715 static void
bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info * link_info,enum bnxt_media_type media,struct ethtool_link_ksettings * lk_ksettings)2716 bnxt_get_all_ethtool_adv_speeds(struct bnxt_link_info *link_info,
2717 enum bnxt_media_type media,
2718 struct ethtool_link_ksettings *lk_ksettings)
2719 {
2720 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2721 u16 sp_nrz, sp_pam4, sp_pam4_112 = 0;
2722 u16 phy_flags = bp->phy_flags;
2723
2724 sp_nrz = link_info->advertising;
2725 if (phy_flags & BNXT_PHY_FL_SPEEDS2) {
2726 sp_pam4 = link_info->advertising;
2727 sp_pam4_112 = link_info->advertising;
2728 } else {
2729 sp_pam4 = link_info->advertising_pam4;
2730 }
2731 bnxt_get_ethtool_speeds(sp_nrz, media, BNXT_SIG_MODE_NRZ, phy_flags,
2732 lk_ksettings->link_modes.advertising);
2733 bnxt_get_ethtool_speeds(sp_pam4, media, BNXT_SIG_MODE_PAM4, phy_flags,
2734 lk_ksettings->link_modes.advertising);
2735 bnxt_get_ethtool_speeds(sp_pam4_112, media, BNXT_SIG_MODE_PAM4_112,
2736 phy_flags, lk_ksettings->link_modes.advertising);
2737 }
2738
2739 static void
bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info * link_info,enum bnxt_media_type media,struct ethtool_link_ksettings * lk_ksettings)2740 bnxt_get_all_ethtool_lp_speeds(struct bnxt_link_info *link_info,
2741 enum bnxt_media_type media,
2742 struct ethtool_link_ksettings *lk_ksettings)
2743 {
2744 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2745 u16 phy_flags = bp->phy_flags;
2746
2747 bnxt_get_ethtool_speeds(link_info->lp_auto_link_speeds, media,
2748 BNXT_SIG_MODE_NRZ, phy_flags,
2749 lk_ksettings->link_modes.lp_advertising);
2750 bnxt_get_ethtool_speeds(link_info->lp_auto_pam4_link_speeds, media,
2751 BNXT_SIG_MODE_PAM4, phy_flags,
2752 lk_ksettings->link_modes.lp_advertising);
2753 }
2754
bnxt_update_speed(u32 * delta,bool installed_media,u16 * speeds,u16 speed_msk,const unsigned long * et_mask,enum ethtool_link_mode_bit_indices mode)2755 static void bnxt_update_speed(u32 *delta, bool installed_media, u16 *speeds,
2756 u16 speed_msk, const unsigned long *et_mask,
2757 enum ethtool_link_mode_bit_indices mode)
2758 {
2759 bool mode_desired = linkmode_test_bit(mode, et_mask);
2760
2761 if (!mode)
2762 return;
2763
2764 /* enabled speeds for installed media should override */
2765 if (installed_media && mode_desired) {
2766 *speeds |= speed_msk;
2767 *delta |= speed_msk;
2768 return;
2769 }
2770
2771 /* many to one mapping, only allow one change per fw_speed bit */
2772 if (!(*delta & speed_msk) && (mode_desired == !(*speeds & speed_msk))) {
2773 *speeds ^= speed_msk;
2774 *delta |= speed_msk;
2775 }
2776 }
2777
bnxt_set_ethtool_speeds(struct bnxt_link_info * link_info,const unsigned long * et_mask)2778 static void bnxt_set_ethtool_speeds(struct bnxt_link_info *link_info,
2779 const unsigned long *et_mask)
2780 {
2781 struct bnxt *bp = container_of(link_info, struct bnxt, link_info);
2782 u16 const *sp_msks, *sp_pam4_msks, *sp_pam4_112_msks;
2783 enum bnxt_media_type media = bnxt_get_media(link_info);
2784 u16 *adv, *adv_pam4, *adv_pam4_112 = NULL;
2785 u32 delta_pam4_112 = 0;
2786 u32 delta_pam4 = 0;
2787 u32 delta_nrz = 0;
2788 int i, m;
2789
2790 adv = &link_info->advertising;
2791 if (bp->phy_flags & BNXT_PHY_FL_SPEEDS2) {
2792 adv_pam4 = &link_info->advertising;
2793 adv_pam4_112 = &link_info->advertising;
2794 sp_msks = bnxt_nrz_speeds2_masks;
2795 sp_pam4_msks = bnxt_pam4_speeds2_masks;
2796 sp_pam4_112_msks = bnxt_pam4_112_speeds2_masks;
2797 } else {
2798 adv_pam4 = &link_info->advertising_pam4;
2799 sp_msks = bnxt_nrz_speed_masks;
2800 sp_pam4_msks = bnxt_pam4_speed_masks;
2801 }
2802 for (i = 1; i < __BNXT_LINK_SPEED_END; i++) {
2803 /* accept any legal media from user */
2804 for (m = 1; m < __BNXT_MEDIA_END; m++) {
2805 bnxt_update_speed(&delta_nrz, m == media,
2806 adv, sp_msks[i], et_mask,
2807 bnxt_link_modes[i][BNXT_SIG_MODE_NRZ][m]);
2808 bnxt_update_speed(&delta_pam4, m == media,
2809 adv_pam4, sp_pam4_msks[i], et_mask,
2810 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4][m]);
2811 if (!adv_pam4_112)
2812 continue;
2813
2814 bnxt_update_speed(&delta_pam4_112, m == media,
2815 adv_pam4_112, sp_pam4_112_msks[i], et_mask,
2816 bnxt_link_modes[i][BNXT_SIG_MODE_PAM4_112][m]);
2817 }
2818 }
2819 }
2820
bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)2821 static void bnxt_fw_to_ethtool_advertised_fec(struct bnxt_link_info *link_info,
2822 struct ethtool_link_ksettings *lk_ksettings)
2823 {
2824 u16 fec_cfg = link_info->fec_cfg;
2825
2826 if ((fec_cfg & BNXT_FEC_NONE) || !(fec_cfg & BNXT_FEC_AUTONEG)) {
2827 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2828 lk_ksettings->link_modes.advertising);
2829 return;
2830 }
2831 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
2832 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2833 lk_ksettings->link_modes.advertising);
2834 if (fec_cfg & BNXT_FEC_ENC_RS)
2835 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2836 lk_ksettings->link_modes.advertising);
2837 if (fec_cfg & BNXT_FEC_ENC_LLRS)
2838 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2839 lk_ksettings->link_modes.advertising);
2840 }
2841
bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info * link_info,struct ethtool_link_ksettings * lk_ksettings)2842 static void bnxt_fw_to_ethtool_support_fec(struct bnxt_link_info *link_info,
2843 struct ethtool_link_ksettings *lk_ksettings)
2844 {
2845 u16 fec_cfg = link_info->fec_cfg;
2846
2847 if (fec_cfg & BNXT_FEC_NONE) {
2848 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
2849 lk_ksettings->link_modes.supported);
2850 return;
2851 }
2852 if (fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)
2853 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
2854 lk_ksettings->link_modes.supported);
2855 if (fec_cfg & BNXT_FEC_ENC_RS_CAP)
2856 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
2857 lk_ksettings->link_modes.supported);
2858 if (fec_cfg & BNXT_FEC_ENC_LLRS_CAP)
2859 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
2860 lk_ksettings->link_modes.supported);
2861 }
2862
bnxt_fw_to_ethtool_speed(u16 fw_link_speed)2863 u32 bnxt_fw_to_ethtool_speed(u16 fw_link_speed)
2864 {
2865 switch (fw_link_speed) {
2866 case BNXT_LINK_SPEED_100MB:
2867 return SPEED_100;
2868 case BNXT_LINK_SPEED_1GB:
2869 return SPEED_1000;
2870 case BNXT_LINK_SPEED_2_5GB:
2871 return SPEED_2500;
2872 case BNXT_LINK_SPEED_10GB:
2873 return SPEED_10000;
2874 case BNXT_LINK_SPEED_20GB:
2875 return SPEED_20000;
2876 case BNXT_LINK_SPEED_25GB:
2877 return SPEED_25000;
2878 case BNXT_LINK_SPEED_40GB:
2879 return SPEED_40000;
2880 case BNXT_LINK_SPEED_50GB:
2881 case BNXT_LINK_SPEED_50GB_PAM4:
2882 return SPEED_50000;
2883 case BNXT_LINK_SPEED_100GB:
2884 case BNXT_LINK_SPEED_100GB_PAM4:
2885 case BNXT_LINK_SPEED_100GB_PAM4_112:
2886 return SPEED_100000;
2887 case BNXT_LINK_SPEED_200GB:
2888 case BNXT_LINK_SPEED_200GB_PAM4:
2889 case BNXT_LINK_SPEED_200GB_PAM4_112:
2890 return SPEED_200000;
2891 case BNXT_LINK_SPEED_400GB:
2892 case BNXT_LINK_SPEED_400GB_PAM4:
2893 case BNXT_LINK_SPEED_400GB_PAM4_112:
2894 return SPEED_400000;
2895 default:
2896 return SPEED_UNKNOWN;
2897 }
2898 }
2899
bnxt_get_default_speeds(struct ethtool_link_ksettings * lk_ksettings,struct bnxt_link_info * link_info)2900 static void bnxt_get_default_speeds(struct ethtool_link_ksettings *lk_ksettings,
2901 struct bnxt_link_info *link_info)
2902 {
2903 struct ethtool_link_settings *base = &lk_ksettings->base;
2904
2905 if (link_info->link_state == BNXT_LINK_STATE_UP) {
2906 base->speed = bnxt_fw_to_ethtool_speed(link_info->link_speed);
2907 base->duplex = DUPLEX_HALF;
2908 if (link_info->duplex & BNXT_LINK_DUPLEX_FULL)
2909 base->duplex = DUPLEX_FULL;
2910 lk_ksettings->lanes = link_info->active_lanes;
2911 } else if (!link_info->autoneg) {
2912 base->speed = bnxt_fw_to_ethtool_speed(link_info->req_link_speed);
2913 base->duplex = DUPLEX_HALF;
2914 if (link_info->req_duplex == BNXT_LINK_DUPLEX_FULL)
2915 base->duplex = DUPLEX_FULL;
2916 }
2917 }
2918
bnxt_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * lk_ksettings)2919 static int bnxt_get_link_ksettings(struct net_device *dev,
2920 struct ethtool_link_ksettings *lk_ksettings)
2921 {
2922 struct ethtool_link_settings *base = &lk_ksettings->base;
2923 enum ethtool_link_mode_bit_indices link_mode;
2924 struct bnxt *bp = netdev_priv(dev);
2925 struct bnxt_link_info *link_info;
2926 enum bnxt_media_type media;
2927
2928 ethtool_link_ksettings_zero_link_mode(lk_ksettings, lp_advertising);
2929 ethtool_link_ksettings_zero_link_mode(lk_ksettings, advertising);
2930 ethtool_link_ksettings_zero_link_mode(lk_ksettings, supported);
2931 base->duplex = DUPLEX_UNKNOWN;
2932 base->speed = SPEED_UNKNOWN;
2933 link_info = &bp->link_info;
2934
2935 mutex_lock(&bp->link_lock);
2936 bnxt_get_ethtool_modes(link_info, lk_ksettings);
2937 media = bnxt_get_media(link_info);
2938 bnxt_get_all_ethtool_support_speeds(link_info, media, lk_ksettings);
2939 bnxt_fw_to_ethtool_support_fec(link_info, lk_ksettings);
2940 link_mode = bnxt_get_link_mode(link_info);
2941 if (link_mode != BNXT_LINK_MODE_UNKNOWN)
2942 ethtool_params_from_link_mode(lk_ksettings, link_mode);
2943 else
2944 bnxt_get_default_speeds(lk_ksettings, link_info);
2945
2946 if (link_info->autoneg) {
2947 bnxt_fw_to_ethtool_advertised_fec(link_info, lk_ksettings);
2948 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
2949 lk_ksettings->link_modes.advertising);
2950 base->autoneg = AUTONEG_ENABLE;
2951 bnxt_get_all_ethtool_adv_speeds(link_info, media, lk_ksettings);
2952 if (link_info->phy_link_status == BNXT_LINK_LINK)
2953 bnxt_get_all_ethtool_lp_speeds(link_info, media,
2954 lk_ksettings);
2955 } else {
2956 base->autoneg = AUTONEG_DISABLE;
2957 }
2958
2959 base->port = PORT_NONE;
2960 if (media == BNXT_MEDIA_TP) {
2961 base->port = PORT_TP;
2962 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2963 lk_ksettings->link_modes.supported);
2964 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2965 lk_ksettings->link_modes.advertising);
2966 } else if (media == BNXT_MEDIA_KR) {
2967 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT,
2968 lk_ksettings->link_modes.supported);
2969 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT,
2970 lk_ksettings->link_modes.advertising);
2971 } else {
2972 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2973 lk_ksettings->link_modes.supported);
2974 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
2975 lk_ksettings->link_modes.advertising);
2976
2977 if (media == BNXT_MEDIA_CR)
2978 base->port = PORT_DA;
2979 else
2980 base->port = PORT_FIBRE;
2981 }
2982 base->phy_address = link_info->phy_addr;
2983 mutex_unlock(&bp->link_lock);
2984
2985 return 0;
2986 }
2987
2988 static int
bnxt_force_link_speed(struct net_device * dev,u32 ethtool_speed,u32 lanes)2989 bnxt_force_link_speed(struct net_device *dev, u32 ethtool_speed, u32 lanes)
2990 {
2991 struct bnxt *bp = netdev_priv(dev);
2992 struct bnxt_link_info *link_info = &bp->link_info;
2993 u16 support_pam4_spds = link_info->support_pam4_speeds;
2994 u16 support_spds2 = link_info->support_speeds2;
2995 u16 support_spds = link_info->support_speeds;
2996 u8 sig_mode = BNXT_SIG_MODE_NRZ;
2997 u32 lanes_needed = 1;
2998 u16 fw_speed = 0;
2999
3000 switch (ethtool_speed) {
3001 case SPEED_100:
3002 if (support_spds & BNXT_LINK_SPEED_MSK_100MB)
3003 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB;
3004 break;
3005 case SPEED_1000:
3006 if ((support_spds & BNXT_LINK_SPEED_MSK_1GB) ||
3007 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_1GB))
3008 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
3009 break;
3010 case SPEED_2500:
3011 if (support_spds & BNXT_LINK_SPEED_MSK_2_5GB)
3012 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB;
3013 break;
3014 case SPEED_10000:
3015 if ((support_spds & BNXT_LINK_SPEED_MSK_10GB) ||
3016 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_10GB))
3017 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
3018 break;
3019 case SPEED_20000:
3020 if (support_spds & BNXT_LINK_SPEED_MSK_20GB) {
3021 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB;
3022 lanes_needed = 2;
3023 }
3024 break;
3025 case SPEED_25000:
3026 if ((support_spds & BNXT_LINK_SPEED_MSK_25GB) ||
3027 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_25GB))
3028 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
3029 break;
3030 case SPEED_40000:
3031 if ((support_spds & BNXT_LINK_SPEED_MSK_40GB) ||
3032 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_40GB)) {
3033 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
3034 lanes_needed = 4;
3035 }
3036 break;
3037 case SPEED_50000:
3038 if (((support_spds & BNXT_LINK_SPEED_MSK_50GB) ||
3039 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB)) &&
3040 lanes != 1) {
3041 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
3042 lanes_needed = 2;
3043 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_50GB) {
3044 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB;
3045 sig_mode = BNXT_SIG_MODE_PAM4;
3046 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_50GB_PAM4) {
3047 fw_speed = BNXT_LINK_SPEED_50GB_PAM4;
3048 sig_mode = BNXT_SIG_MODE_PAM4;
3049 }
3050 break;
3051 case SPEED_100000:
3052 if (((support_spds & BNXT_LINK_SPEED_MSK_100GB) ||
3053 (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB)) &&
3054 lanes != 2 && lanes != 1) {
3055 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB;
3056 lanes_needed = 4;
3057 } else if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_100GB) {
3058 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB;
3059 sig_mode = BNXT_SIG_MODE_PAM4;
3060 lanes_needed = 2;
3061 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4) &&
3062 lanes != 1) {
3063 fw_speed = BNXT_LINK_SPEED_100GB_PAM4;
3064 sig_mode = BNXT_SIG_MODE_PAM4;
3065 lanes_needed = 2;
3066 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_100GB_PAM4_112) {
3067 fw_speed = BNXT_LINK_SPEED_100GB_PAM4_112;
3068 sig_mode = BNXT_SIG_MODE_PAM4_112;
3069 }
3070 break;
3071 case SPEED_200000:
3072 if (support_pam4_spds & BNXT_LINK_PAM4_SPEED_MSK_200GB) {
3073 fw_speed = PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB;
3074 sig_mode = BNXT_SIG_MODE_PAM4;
3075 lanes_needed = 4;
3076 } else if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4) &&
3077 lanes != 2) {
3078 fw_speed = BNXT_LINK_SPEED_200GB_PAM4;
3079 sig_mode = BNXT_SIG_MODE_PAM4;
3080 lanes_needed = 4;
3081 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_200GB_PAM4_112) {
3082 fw_speed = BNXT_LINK_SPEED_200GB_PAM4_112;
3083 sig_mode = BNXT_SIG_MODE_PAM4_112;
3084 lanes_needed = 2;
3085 }
3086 break;
3087 case SPEED_400000:
3088 if ((support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4) &&
3089 lanes != 4) {
3090 fw_speed = BNXT_LINK_SPEED_400GB_PAM4;
3091 sig_mode = BNXT_SIG_MODE_PAM4;
3092 lanes_needed = 8;
3093 } else if (support_spds2 & BNXT_LINK_SPEEDS2_MSK_400GB_PAM4_112) {
3094 fw_speed = BNXT_LINK_SPEED_400GB_PAM4_112;
3095 sig_mode = BNXT_SIG_MODE_PAM4_112;
3096 lanes_needed = 4;
3097 }
3098 break;
3099 }
3100
3101 if (!fw_speed) {
3102 netdev_err(dev, "unsupported speed!\n");
3103 return -EINVAL;
3104 }
3105
3106 if (lanes && lanes != lanes_needed) {
3107 netdev_err(dev, "unsupported number of lanes for speed\n");
3108 return -EINVAL;
3109 }
3110
3111 if (link_info->req_link_speed == fw_speed &&
3112 link_info->req_signal_mode == sig_mode &&
3113 link_info->autoneg == 0)
3114 return -EALREADY;
3115
3116 link_info->req_link_speed = fw_speed;
3117 link_info->req_signal_mode = sig_mode;
3118 link_info->req_duplex = BNXT_LINK_DUPLEX_FULL;
3119 link_info->autoneg = 0;
3120 link_info->advertising = 0;
3121 link_info->advertising_pam4 = 0;
3122
3123 return 0;
3124 }
3125
bnxt_get_fw_auto_link_speeds(const unsigned long * mode)3126 u16 bnxt_get_fw_auto_link_speeds(const unsigned long *mode)
3127 {
3128 u16 fw_speed_mask = 0;
3129
3130 if (linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mode) ||
3131 linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mode))
3132 fw_speed_mask |= BNXT_LINK_SPEED_MSK_100MB;
3133
3134 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mode) ||
3135 linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, mode))
3136 fw_speed_mask |= BNXT_LINK_SPEED_MSK_1GB;
3137
3138 if (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, mode))
3139 fw_speed_mask |= BNXT_LINK_SPEED_MSK_10GB;
3140
3141 if (linkmode_test_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, mode))
3142 fw_speed_mask |= BNXT_LINK_SPEED_MSK_40GB;
3143
3144 return fw_speed_mask;
3145 }
3146
bnxt_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * lk_ksettings)3147 static int bnxt_set_link_ksettings(struct net_device *dev,
3148 const struct ethtool_link_ksettings *lk_ksettings)
3149 {
3150 struct bnxt *bp = netdev_priv(dev);
3151 struct bnxt_link_info *link_info = &bp->link_info;
3152 const struct ethtool_link_settings *base = &lk_ksettings->base;
3153 bool set_pause = false;
3154 u32 speed, lanes = 0;
3155 int rc = 0;
3156
3157 if (!BNXT_PHY_CFG_ABLE(bp))
3158 return -EOPNOTSUPP;
3159
3160 mutex_lock(&bp->link_lock);
3161 if (base->autoneg == AUTONEG_ENABLE) {
3162 bnxt_set_ethtool_speeds(link_info,
3163 lk_ksettings->link_modes.advertising);
3164 link_info->autoneg |= BNXT_AUTONEG_SPEED;
3165 if (!link_info->advertising && !link_info->advertising_pam4) {
3166 link_info->advertising = link_info->support_auto_speeds;
3167 link_info->advertising_pam4 =
3168 link_info->support_pam4_auto_speeds;
3169 }
3170 /* any change to autoneg will cause link change, therefore the
3171 * driver should put back the original pause setting in autoneg
3172 */
3173 if (!(bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
3174 set_pause = true;
3175 } else {
3176 u8 phy_type = link_info->phy_type;
3177
3178 if (phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
3179 phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE ||
3180 link_info->media_type == PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP) {
3181 netdev_err(dev, "10GBase-T devices must autoneg\n");
3182 rc = -EINVAL;
3183 goto set_setting_exit;
3184 }
3185 if (base->duplex == DUPLEX_HALF) {
3186 netdev_err(dev, "HALF DUPLEX is not supported!\n");
3187 rc = -EINVAL;
3188 goto set_setting_exit;
3189 }
3190 speed = base->speed;
3191 lanes = lk_ksettings->lanes;
3192 rc = bnxt_force_link_speed(dev, speed, lanes);
3193 if (rc) {
3194 if (rc == -EALREADY)
3195 rc = 0;
3196 goto set_setting_exit;
3197 }
3198 }
3199
3200 if (netif_running(dev))
3201 rc = bnxt_hwrm_set_link_setting(bp, set_pause, false);
3202
3203 set_setting_exit:
3204 mutex_unlock(&bp->link_lock);
3205 return rc;
3206 }
3207
bnxt_get_fecparam(struct net_device * dev,struct ethtool_fecparam * fec)3208 static int bnxt_get_fecparam(struct net_device *dev,
3209 struct ethtool_fecparam *fec)
3210 {
3211 struct bnxt *bp = netdev_priv(dev);
3212 struct bnxt_link_info *link_info;
3213 u8 active_fec;
3214 u16 fec_cfg;
3215
3216 link_info = &bp->link_info;
3217 fec_cfg = link_info->fec_cfg;
3218 active_fec = link_info->active_fec_sig_mode &
3219 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
3220 if (fec_cfg & BNXT_FEC_NONE) {
3221 fec->fec = ETHTOOL_FEC_NONE;
3222 fec->active_fec = ETHTOOL_FEC_NONE;
3223 return 0;
3224 }
3225 if (fec_cfg & BNXT_FEC_AUTONEG)
3226 fec->fec |= ETHTOOL_FEC_AUTO;
3227 if (fec_cfg & BNXT_FEC_ENC_BASE_R)
3228 fec->fec |= ETHTOOL_FEC_BASER;
3229 if (fec_cfg & BNXT_FEC_ENC_RS)
3230 fec->fec |= ETHTOOL_FEC_RS;
3231 if (fec_cfg & BNXT_FEC_ENC_LLRS)
3232 fec->fec |= ETHTOOL_FEC_LLRS;
3233
3234 switch (active_fec) {
3235 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
3236 fec->active_fec |= ETHTOOL_FEC_BASER;
3237 break;
3238 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
3239 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
3240 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
3241 fec->active_fec |= ETHTOOL_FEC_RS;
3242 break;
3243 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
3244 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
3245 fec->active_fec |= ETHTOOL_FEC_LLRS;
3246 break;
3247 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
3248 fec->active_fec |= ETHTOOL_FEC_OFF;
3249 break;
3250 }
3251 return 0;
3252 }
3253
3254 static const struct ethtool_fec_hist_range bnxt_fec_ranges[] = {
3255 { 0, 0},
3256 { 1, 1},
3257 { 2, 2},
3258 { 3, 3},
3259 { 4, 4},
3260 { 5, 5},
3261 { 6, 6},
3262 { 7, 7},
3263 { 8, 8},
3264 { 9, 9},
3265 { 10, 10},
3266 { 11, 11},
3267 { 12, 12},
3268 { 13, 13},
3269 { 14, 14},
3270 { 15, 15},
3271 { 0, 0},
3272 };
3273
bnxt_hwrm_port_phy_fdrstat(struct bnxt * bp,struct ethtool_fec_hist * hist)3274 static void bnxt_hwrm_port_phy_fdrstat(struct bnxt *bp,
3275 struct ethtool_fec_hist *hist)
3276 {
3277 struct ethtool_fec_hist_value *values = hist->values;
3278 struct hwrm_port_phy_fdrstat_output *resp;
3279 struct hwrm_port_phy_fdrstat_input *req;
3280 int rc, i;
3281
3282 if (!(bp->phy_flags & BNXT_PHY_FL_FDRSTATS))
3283 return;
3284
3285 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_FDRSTAT);
3286 if (rc)
3287 return;
3288
3289 req->port_id = cpu_to_le16(bp->pf.port_id);
3290 req->ops = cpu_to_le16(PORT_PHY_FDRSTAT_REQ_OPS_COUNTER);
3291 resp = hwrm_req_hold(bp, req);
3292 rc = hwrm_req_send(bp, req);
3293 if (!rc) {
3294 hist->ranges = bnxt_fec_ranges;
3295 for (i = 0; i <= 15; i++) {
3296 __le64 sum = resp->accumulated_codewords_err_s[i];
3297
3298 values[i].sum = le64_to_cpu(sum);
3299 }
3300 }
3301 hwrm_req_drop(bp, req);
3302 }
3303
bnxt_get_fec_stats(struct net_device * dev,struct ethtool_fec_stats * fec_stats,struct ethtool_fec_hist * hist)3304 static void bnxt_get_fec_stats(struct net_device *dev,
3305 struct ethtool_fec_stats *fec_stats,
3306 struct ethtool_fec_hist *hist)
3307 {
3308 struct bnxt *bp = netdev_priv(dev);
3309 u64 *rx;
3310
3311 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
3312 return;
3313
3314 rx = bp->rx_port_stats_ext.sw_stats;
3315 fec_stats->corrected_bits.total =
3316 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_corrected_bits));
3317
3318 if (bp->fw_rx_stats_ext_size <= BNXT_RX_STATS_EXT_NUM_LEGACY)
3319 return;
3320
3321 fec_stats->corrected_blocks.total =
3322 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks));
3323 fec_stats->uncorrectable_blocks.total =
3324 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_fec_uncorrectable_blocks));
3325 bnxt_hwrm_port_phy_fdrstat(bp, hist);
3326 }
3327
bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info * link_info,u32 fec)3328 static u32 bnxt_ethtool_forced_fec_to_fw(struct bnxt_link_info *link_info,
3329 u32 fec)
3330 {
3331 u32 fw_fec = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE;
3332
3333 if (fec & ETHTOOL_FEC_BASER)
3334 fw_fec |= BNXT_FEC_BASE_R_ON(link_info);
3335 else if (fec & ETHTOOL_FEC_RS)
3336 fw_fec |= BNXT_FEC_RS_ON(link_info);
3337 else if (fec & ETHTOOL_FEC_LLRS)
3338 fw_fec |= BNXT_FEC_LLRS_ON;
3339 return fw_fec;
3340 }
3341
bnxt_set_fecparam(struct net_device * dev,struct ethtool_fecparam * fecparam)3342 static int bnxt_set_fecparam(struct net_device *dev,
3343 struct ethtool_fecparam *fecparam)
3344 {
3345 struct hwrm_port_phy_cfg_input *req;
3346 struct bnxt *bp = netdev_priv(dev);
3347 struct bnxt_link_info *link_info;
3348 u32 new_cfg, fec = fecparam->fec;
3349 u16 fec_cfg;
3350 int rc;
3351
3352 link_info = &bp->link_info;
3353 fec_cfg = link_info->fec_cfg;
3354 if (fec_cfg & BNXT_FEC_NONE)
3355 return -EOPNOTSUPP;
3356
3357 if (fec & ETHTOOL_FEC_OFF) {
3358 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE |
3359 BNXT_FEC_ALL_OFF(link_info);
3360 goto apply_fec;
3361 }
3362 if (((fec & ETHTOOL_FEC_AUTO) && !(fec_cfg & BNXT_FEC_AUTONEG_CAP)) ||
3363 ((fec & ETHTOOL_FEC_RS) && !(fec_cfg & BNXT_FEC_ENC_RS_CAP)) ||
3364 ((fec & ETHTOOL_FEC_LLRS) && !(fec_cfg & BNXT_FEC_ENC_LLRS_CAP)) ||
3365 ((fec & ETHTOOL_FEC_BASER) && !(fec_cfg & BNXT_FEC_ENC_BASE_R_CAP)))
3366 return -EINVAL;
3367
3368 if (fec & ETHTOOL_FEC_AUTO) {
3369 if (!link_info->autoneg)
3370 return -EINVAL;
3371 new_cfg = PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE;
3372 } else {
3373 new_cfg = bnxt_ethtool_forced_fec_to_fw(link_info, fec);
3374 }
3375
3376 apply_fec:
3377 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
3378 if (rc)
3379 return rc;
3380 req->flags = cpu_to_le32(new_cfg | PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
3381 rc = hwrm_req_send(bp, req);
3382 /* update current settings */
3383 if (!rc) {
3384 mutex_lock(&bp->link_lock);
3385 bnxt_update_link(bp, false);
3386 mutex_unlock(&bp->link_lock);
3387 }
3388 return rc;
3389 }
3390
bnxt_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)3391 static void bnxt_get_pauseparam(struct net_device *dev,
3392 struct ethtool_pauseparam *epause)
3393 {
3394 struct bnxt *bp = netdev_priv(dev);
3395 struct bnxt_link_info *link_info = &bp->link_info;
3396
3397 if (BNXT_VF(bp))
3398 return;
3399 epause->autoneg = !!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL);
3400 epause->rx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_RX);
3401 epause->tx_pause = !!(link_info->req_flow_ctrl & BNXT_LINK_PAUSE_TX);
3402 }
3403
bnxt_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * epstat)3404 static void bnxt_get_pause_stats(struct net_device *dev,
3405 struct ethtool_pause_stats *epstat)
3406 {
3407 struct bnxt *bp = netdev_priv(dev);
3408 u64 *rx, *tx;
3409
3410 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
3411 return;
3412
3413 rx = bp->port_stats.sw_stats;
3414 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3415
3416 epstat->rx_pause_frames = BNXT_GET_RX_PORT_STATS64(rx, rx_pause_frames);
3417 epstat->tx_pause_frames = BNXT_GET_TX_PORT_STATS64(tx, tx_pause_frames);
3418 }
3419
bnxt_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * epause)3420 static int bnxt_set_pauseparam(struct net_device *dev,
3421 struct ethtool_pauseparam *epause)
3422 {
3423 int rc = 0;
3424 struct bnxt *bp = netdev_priv(dev);
3425 struct bnxt_link_info *link_info = &bp->link_info;
3426
3427 if (!BNXT_PHY_CFG_ABLE(bp) || (bp->phy_flags & BNXT_PHY_FL_NO_PAUSE))
3428 return -EOPNOTSUPP;
3429
3430 mutex_lock(&bp->link_lock);
3431 if (epause->autoneg) {
3432 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
3433 rc = -EINVAL;
3434 goto pause_exit;
3435 }
3436
3437 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
3438 link_info->req_flow_ctrl = 0;
3439 } else {
3440 /* when transition from auto pause to force pause,
3441 * force a link change
3442 */
3443 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
3444 link_info->force_link_chng = true;
3445 link_info->autoneg &= ~BNXT_AUTONEG_FLOW_CTRL;
3446 link_info->req_flow_ctrl = 0;
3447 }
3448 if (epause->rx_pause)
3449 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_RX;
3450
3451 if (epause->tx_pause)
3452 link_info->req_flow_ctrl |= BNXT_LINK_PAUSE_TX;
3453
3454 if (netif_running(dev))
3455 rc = bnxt_hwrm_set_pause(bp);
3456
3457 pause_exit:
3458 mutex_unlock(&bp->link_lock);
3459 return rc;
3460 }
3461
bnxt_get_link(struct net_device * dev)3462 static u32 bnxt_get_link(struct net_device *dev)
3463 {
3464 struct bnxt *bp = netdev_priv(dev);
3465
3466 /* TODO: handle MF, VF, driver close case */
3467 return BNXT_LINK_IS_UP(bp);
3468 }
3469
bnxt_get_link_ext_state(struct net_device * dev,struct ethtool_link_ext_state_info * info)3470 static int bnxt_get_link_ext_state(struct net_device *dev,
3471 struct ethtool_link_ext_state_info *info)
3472 {
3473 struct bnxt *bp = netdev_priv(dev);
3474 u8 reason;
3475
3476 if (BNXT_LINK_IS_UP(bp))
3477 return -ENODATA;
3478
3479 reason = bp->link_info.link_down_reason;
3480 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF) {
3481 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE;
3482 info->link_training = ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT;
3483 return 0;
3484 }
3485 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED) {
3486 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_NO_CABLE;
3487 return 0;
3488 }
3489 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION) {
3490 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_OTP_SPEED_VIOLATION;
3491 return 0;
3492 }
3493 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT) {
3494 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_MODULE;
3495 return 0;
3496 }
3497 if (reason & PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST) {
3498 info->link_ext_state = ETHTOOL_LINK_EXT_STATE_BMC_REQUEST_DOWN;
3499 return 0;
3500 }
3501 return -ENODATA;
3502 }
3503
bnxt_hwrm_nvm_get_dev_info(struct bnxt * bp,struct hwrm_nvm_get_dev_info_output * nvm_dev_info)3504 int bnxt_hwrm_nvm_get_dev_info(struct bnxt *bp,
3505 struct hwrm_nvm_get_dev_info_output *nvm_dev_info)
3506 {
3507 struct hwrm_nvm_get_dev_info_output *resp;
3508 struct hwrm_nvm_get_dev_info_input *req;
3509 int rc;
3510
3511 if (BNXT_VF(bp))
3512 return -EOPNOTSUPP;
3513
3514 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DEV_INFO);
3515 if (rc)
3516 return rc;
3517
3518 resp = hwrm_req_hold(bp, req);
3519 rc = hwrm_req_send(bp, req);
3520 if (!rc)
3521 memcpy(nvm_dev_info, resp, sizeof(*resp));
3522 hwrm_req_drop(bp, req);
3523 return rc;
3524 }
3525
bnxt_print_admin_err(struct bnxt * bp)3526 static void bnxt_print_admin_err(struct bnxt *bp)
3527 {
3528 netdev_info(bp->dev, "PF does not have admin privileges to flash or reset the device\n");
3529 }
3530
3531 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
3532 u16 ext, u16 *index, u32 *item_length,
3533 u32 *data_length);
3534
bnxt_flash_nvram(struct net_device * dev,u16 dir_type,u16 dir_ordinal,u16 dir_ext,u16 dir_attr,u32 dir_item_len,const u8 * data,size_t data_len)3535 int bnxt_flash_nvram(struct net_device *dev, u16 dir_type,
3536 u16 dir_ordinal, u16 dir_ext, u16 dir_attr,
3537 u32 dir_item_len, const u8 *data,
3538 size_t data_len)
3539 {
3540 struct bnxt *bp = netdev_priv(dev);
3541 struct hwrm_nvm_write_input *req;
3542 int rc;
3543
3544 rc = hwrm_req_init(bp, req, HWRM_NVM_WRITE);
3545 if (rc)
3546 return rc;
3547
3548 if (data_len && data) {
3549 dma_addr_t dma_handle;
3550 u8 *kmem;
3551
3552 kmem = hwrm_req_dma_slice(bp, req, data_len, &dma_handle);
3553 if (!kmem) {
3554 hwrm_req_drop(bp, req);
3555 return -ENOMEM;
3556 }
3557
3558 req->dir_data_length = cpu_to_le32(data_len);
3559
3560 memcpy(kmem, data, data_len);
3561 req->host_src_addr = cpu_to_le64(dma_handle);
3562 }
3563
3564 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
3565 req->dir_type = cpu_to_le16(dir_type);
3566 req->dir_ordinal = cpu_to_le16(dir_ordinal);
3567 req->dir_ext = cpu_to_le16(dir_ext);
3568 req->dir_attr = cpu_to_le16(dir_attr);
3569 req->dir_item_length = cpu_to_le32(dir_item_len);
3570 rc = hwrm_req_send(bp, req);
3571
3572 if (rc == -EACCES)
3573 bnxt_print_admin_err(bp);
3574 return rc;
3575 }
3576
bnxt_hwrm_firmware_reset(struct net_device * dev,u8 proc_type,u8 self_reset,u8 flags)3577 int bnxt_hwrm_firmware_reset(struct net_device *dev, u8 proc_type,
3578 u8 self_reset, u8 flags)
3579 {
3580 struct bnxt *bp = netdev_priv(dev);
3581 struct hwrm_fw_reset_input *req;
3582 int rc;
3583
3584 if (!bnxt_hwrm_reset_permitted(bp)) {
3585 netdev_warn(bp->dev, "Reset denied by firmware, it may be inhibited by remote driver");
3586 return -EPERM;
3587 }
3588
3589 rc = hwrm_req_init(bp, req, HWRM_FW_RESET);
3590 if (rc)
3591 return rc;
3592
3593 req->embedded_proc_type = proc_type;
3594 req->selfrst_status = self_reset;
3595 req->flags = flags;
3596
3597 if (proc_type == FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP) {
3598 rc = hwrm_req_send_silent(bp, req);
3599 } else {
3600 rc = hwrm_req_send(bp, req);
3601 if (rc == -EACCES)
3602 bnxt_print_admin_err(bp);
3603 }
3604 return rc;
3605 }
3606
bnxt_firmware_reset(struct net_device * dev,enum bnxt_nvm_directory_type dir_type)3607 static int bnxt_firmware_reset(struct net_device *dev,
3608 enum bnxt_nvm_directory_type dir_type)
3609 {
3610 u8 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE;
3611 u8 proc_type, flags = 0;
3612
3613 /* TODO: Address self-reset of APE/KONG/BONO/TANG or ungraceful reset */
3614 /* (e.g. when firmware isn't already running) */
3615 switch (dir_type) {
3616 case BNX_DIR_TYPE_CHIMP_PATCH:
3617 case BNX_DIR_TYPE_BOOTCODE:
3618 case BNX_DIR_TYPE_BOOTCODE_2:
3619 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT;
3620 /* Self-reset ChiMP upon next PCIe reset: */
3621 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3622 break;
3623 case BNX_DIR_TYPE_APE_FW:
3624 case BNX_DIR_TYPE_APE_PATCH:
3625 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT;
3626 /* Self-reset APE upon next PCIe reset: */
3627 self_reset = FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST;
3628 break;
3629 case BNX_DIR_TYPE_KONG_FW:
3630 case BNX_DIR_TYPE_KONG_PATCH:
3631 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL;
3632 break;
3633 case BNX_DIR_TYPE_BONO_FW:
3634 case BNX_DIR_TYPE_BONO_PATCH:
3635 proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE;
3636 break;
3637 default:
3638 return -EINVAL;
3639 }
3640
3641 return bnxt_hwrm_firmware_reset(dev, proc_type, self_reset, flags);
3642 }
3643
bnxt_firmware_reset_chip(struct net_device * dev)3644 static int bnxt_firmware_reset_chip(struct net_device *dev)
3645 {
3646 struct bnxt *bp = netdev_priv(dev);
3647 u8 flags = 0;
3648
3649 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
3650 flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
3651
3652 return bnxt_hwrm_firmware_reset(dev,
3653 FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP,
3654 FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP,
3655 flags);
3656 }
3657
bnxt_firmware_reset_ap(struct net_device * dev)3658 static int bnxt_firmware_reset_ap(struct net_device *dev)
3659 {
3660 return bnxt_hwrm_firmware_reset(dev, FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP,
3661 FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE,
3662 0);
3663 }
3664
bnxt_flash_firmware(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)3665 static int bnxt_flash_firmware(struct net_device *dev,
3666 u16 dir_type,
3667 const u8 *fw_data,
3668 size_t fw_size)
3669 {
3670 int rc = 0;
3671 u16 code_type;
3672 u32 stored_crc;
3673 u32 calculated_crc;
3674 struct bnxt_fw_header *header = (struct bnxt_fw_header *)fw_data;
3675
3676 switch (dir_type) {
3677 case BNX_DIR_TYPE_BOOTCODE:
3678 case BNX_DIR_TYPE_BOOTCODE_2:
3679 code_type = CODE_BOOT;
3680 break;
3681 case BNX_DIR_TYPE_CHIMP_PATCH:
3682 code_type = CODE_CHIMP_PATCH;
3683 break;
3684 case BNX_DIR_TYPE_APE_FW:
3685 code_type = CODE_MCTP_PASSTHRU;
3686 break;
3687 case BNX_DIR_TYPE_APE_PATCH:
3688 code_type = CODE_APE_PATCH;
3689 break;
3690 case BNX_DIR_TYPE_KONG_FW:
3691 code_type = CODE_KONG_FW;
3692 break;
3693 case BNX_DIR_TYPE_KONG_PATCH:
3694 code_type = CODE_KONG_PATCH;
3695 break;
3696 case BNX_DIR_TYPE_BONO_FW:
3697 code_type = CODE_BONO_FW;
3698 break;
3699 case BNX_DIR_TYPE_BONO_PATCH:
3700 code_type = CODE_BONO_PATCH;
3701 break;
3702 default:
3703 netdev_err(dev, "Unsupported directory entry type: %u\n",
3704 dir_type);
3705 return -EINVAL;
3706 }
3707 if (fw_size < sizeof(struct bnxt_fw_header)) {
3708 netdev_err(dev, "Invalid firmware file size: %u\n",
3709 (unsigned int)fw_size);
3710 return -EINVAL;
3711 }
3712 if (header->signature != cpu_to_le32(BNXT_FIRMWARE_BIN_SIGNATURE)) {
3713 netdev_err(dev, "Invalid firmware signature: %08X\n",
3714 le32_to_cpu(header->signature));
3715 return -EINVAL;
3716 }
3717 if (header->code_type != code_type) {
3718 netdev_err(dev, "Expected firmware type: %d, read: %d\n",
3719 code_type, header->code_type);
3720 return -EINVAL;
3721 }
3722 if (header->device != DEVICE_CUMULUS_FAMILY) {
3723 netdev_err(dev, "Expected firmware device family %d, read: %d\n",
3724 DEVICE_CUMULUS_FAMILY, header->device);
3725 return -EINVAL;
3726 }
3727 /* Confirm the CRC32 checksum of the file: */
3728 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3729 sizeof(stored_crc)));
3730 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3731 if (calculated_crc != stored_crc) {
3732 netdev_err(dev, "Firmware file CRC32 checksum (%08lX) does not match calculated checksum (%08lX)\n",
3733 (unsigned long)stored_crc,
3734 (unsigned long)calculated_crc);
3735 return -EINVAL;
3736 }
3737 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3738 0, 0, 0, fw_data, fw_size);
3739 if (rc == 0) /* Firmware update successful */
3740 rc = bnxt_firmware_reset(dev, dir_type);
3741
3742 return rc;
3743 }
3744
bnxt_flash_microcode(struct net_device * dev,u16 dir_type,const u8 * fw_data,size_t fw_size)3745 static int bnxt_flash_microcode(struct net_device *dev,
3746 u16 dir_type,
3747 const u8 *fw_data,
3748 size_t fw_size)
3749 {
3750 struct bnxt_ucode_trailer *trailer;
3751 u32 calculated_crc;
3752 u32 stored_crc;
3753 int rc = 0;
3754
3755 if (fw_size < sizeof(struct bnxt_ucode_trailer)) {
3756 netdev_err(dev, "Invalid microcode file size: %u\n",
3757 (unsigned int)fw_size);
3758 return -EINVAL;
3759 }
3760 trailer = (struct bnxt_ucode_trailer *)(fw_data + (fw_size -
3761 sizeof(*trailer)));
3762 if (trailer->sig != cpu_to_le32(BNXT_UCODE_TRAILER_SIGNATURE)) {
3763 netdev_err(dev, "Invalid microcode trailer signature: %08X\n",
3764 le32_to_cpu(trailer->sig));
3765 return -EINVAL;
3766 }
3767 if (le16_to_cpu(trailer->dir_type) != dir_type) {
3768 netdev_err(dev, "Expected microcode type: %d, read: %d\n",
3769 dir_type, le16_to_cpu(trailer->dir_type));
3770 return -EINVAL;
3771 }
3772 if (le16_to_cpu(trailer->trailer_length) <
3773 sizeof(struct bnxt_ucode_trailer)) {
3774 netdev_err(dev, "Invalid microcode trailer length: %d\n",
3775 le16_to_cpu(trailer->trailer_length));
3776 return -EINVAL;
3777 }
3778
3779 /* Confirm the CRC32 checksum of the file: */
3780 stored_crc = le32_to_cpu(*(__le32 *)(fw_data + fw_size -
3781 sizeof(stored_crc)));
3782 calculated_crc = ~crc32(~0, fw_data, fw_size - sizeof(stored_crc));
3783 if (calculated_crc != stored_crc) {
3784 netdev_err(dev,
3785 "CRC32 (%08lX) does not match calculated: %08lX\n",
3786 (unsigned long)stored_crc,
3787 (unsigned long)calculated_crc);
3788 return -EINVAL;
3789 }
3790 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3791 0, 0, 0, fw_data, fw_size);
3792
3793 return rc;
3794 }
3795
bnxt_dir_type_is_ape_bin_format(u16 dir_type)3796 static bool bnxt_dir_type_is_ape_bin_format(u16 dir_type)
3797 {
3798 switch (dir_type) {
3799 case BNX_DIR_TYPE_CHIMP_PATCH:
3800 case BNX_DIR_TYPE_BOOTCODE:
3801 case BNX_DIR_TYPE_BOOTCODE_2:
3802 case BNX_DIR_TYPE_APE_FW:
3803 case BNX_DIR_TYPE_APE_PATCH:
3804 case BNX_DIR_TYPE_KONG_FW:
3805 case BNX_DIR_TYPE_KONG_PATCH:
3806 case BNX_DIR_TYPE_BONO_FW:
3807 case BNX_DIR_TYPE_BONO_PATCH:
3808 return true;
3809 }
3810
3811 return false;
3812 }
3813
bnxt_dir_type_is_other_exec_format(u16 dir_type)3814 static bool bnxt_dir_type_is_other_exec_format(u16 dir_type)
3815 {
3816 switch (dir_type) {
3817 case BNX_DIR_TYPE_AVS:
3818 case BNX_DIR_TYPE_EXP_ROM_MBA:
3819 case BNX_DIR_TYPE_PCIE:
3820 case BNX_DIR_TYPE_TSCF_UCODE:
3821 case BNX_DIR_TYPE_EXT_PHY:
3822 case BNX_DIR_TYPE_CCM:
3823 case BNX_DIR_TYPE_ISCSI_BOOT:
3824 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3825 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3826 return true;
3827 }
3828
3829 return false;
3830 }
3831
bnxt_dir_type_is_executable(u16 dir_type)3832 static bool bnxt_dir_type_is_executable(u16 dir_type)
3833 {
3834 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3835 bnxt_dir_type_is_other_exec_format(dir_type);
3836 }
3837
bnxt_flash_firmware_from_file(struct net_device * dev,u16 dir_type,const char * filename)3838 static int bnxt_flash_firmware_from_file(struct net_device *dev,
3839 u16 dir_type,
3840 const char *filename)
3841 {
3842 const struct firmware *fw;
3843 int rc;
3844
3845 rc = request_firmware(&fw, filename, &dev->dev);
3846 if (rc != 0) {
3847 netdev_err(dev, "Error %d requesting firmware file: %s\n",
3848 rc, filename);
3849 return rc;
3850 }
3851 if (bnxt_dir_type_is_ape_bin_format(dir_type))
3852 rc = bnxt_flash_firmware(dev, dir_type, fw->data, fw->size);
3853 else if (bnxt_dir_type_is_other_exec_format(dir_type))
3854 rc = bnxt_flash_microcode(dev, dir_type, fw->data, fw->size);
3855 else
3856 rc = bnxt_flash_nvram(dev, dir_type, BNX_DIR_ORDINAL_FIRST,
3857 0, 0, 0, fw->data, fw->size);
3858 release_firmware(fw);
3859 return rc;
3860 }
3861
3862 #define MSG_INTEGRITY_ERR "PKG install error : Data integrity on NVM"
3863 #define MSG_INVALID_PKG "PKG install error : Invalid package"
3864 #define MSG_AUTHENTICATION_ERR "PKG install error : Authentication error"
3865 #define MSG_INVALID_DEV "PKG install error : Invalid device"
3866 #define MSG_INTERNAL_ERR "PKG install error : Internal error"
3867 #define MSG_NO_PKG_UPDATE_AREA_ERR "PKG update area not created in nvram"
3868 #define MSG_NO_SPACE_ERR "PKG insufficient update area in nvram"
3869 #define MSG_RESIZE_UPDATE_ERR "Resize UPDATE entry error"
3870 #define MSG_ANTI_ROLLBACK_ERR "HWRM_NVM_INSTALL_UPDATE failure due to Anti-rollback detected"
3871 #define MSG_GENERIC_FAILURE_ERR "HWRM_NVM_INSTALL_UPDATE failure"
3872
nvm_update_err_to_stderr(struct net_device * dev,u8 result,struct netlink_ext_ack * extack)3873 static int nvm_update_err_to_stderr(struct net_device *dev, u8 result,
3874 struct netlink_ext_ack *extack)
3875 {
3876 switch (result) {
3877 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER:
3878 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER:
3879 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR:
3880 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR:
3881 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND:
3882 case NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED:
3883 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTEGRITY_ERR);
3884 return -EINVAL;
3885 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE:
3886 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER:
3887 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE:
3888 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM:
3889 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH:
3890 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST:
3891 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER:
3892 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM:
3893 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM:
3894 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH:
3895 case NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE:
3896 case NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM:
3897 case NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM:
3898 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_PKG);
3899 return -ENOPKG;
3900 case NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR:
3901 BNXT_NVM_ERR_MSG(dev, extack, MSG_AUTHENTICATION_ERR);
3902 return -EPERM;
3903 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV:
3904 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID:
3905 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR:
3906 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID:
3907 case NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM:
3908 BNXT_NVM_ERR_MSG(dev, extack, MSG_INVALID_DEV);
3909 return -EOPNOTSUPP;
3910 default:
3911 BNXT_NVM_ERR_MSG(dev, extack, MSG_INTERNAL_ERR);
3912 return -EIO;
3913 }
3914 }
3915
3916 #define BNXT_PKG_DMA_SIZE 0x40000
3917 #define BNXT_NVM_MORE_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_MODE))
3918 #define BNXT_NVM_LAST_FLAG (cpu_to_le16(NVM_MODIFY_REQ_FLAGS_BATCH_LAST))
3919
bnxt_hwrm_nvm_defrag(struct bnxt * bp)3920 static int bnxt_hwrm_nvm_defrag(struct bnxt *bp)
3921 {
3922 struct hwrm_nvm_defrag_input *req;
3923 int rc;
3924
3925 rc = hwrm_req_init(bp, req, HWRM_NVM_DEFRAG);
3926 if (rc)
3927 return rc;
3928 req->flags = cpu_to_le32(NVM_DEFRAG_REQ_FLAGS_DEFRAG);
3929 hwrm_req_timeout(bp, req, bp->hwrm_cmd_max_timeout);
3930
3931 return hwrm_req_send(bp, req);
3932 }
3933
bnxt_resize_update_entry(struct net_device * dev,size_t fw_size,struct netlink_ext_ack * extack)3934 static int bnxt_resize_update_entry(struct net_device *dev, size_t fw_size,
3935 struct netlink_ext_ack *extack)
3936 {
3937 struct bnxt *bp = netdev_priv(dev);
3938 bool retry = false;
3939 u32 item_len;
3940 int rc;
3941
3942 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
3943 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE, NULL,
3944 &item_len, NULL);
3945 if (rc) {
3946 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
3947 return rc;
3948 }
3949
3950 if (fw_size > item_len) {
3951 do {
3952 rc = bnxt_flash_nvram(dev, BNX_DIR_TYPE_UPDATE,
3953 BNX_DIR_ORDINAL_FIRST, 0, 1,
3954 round_up(fw_size, 4096), NULL,
3955 0);
3956
3957 if (rc == -ENOSPC) {
3958 if (retry || bnxt_hwrm_nvm_defrag(bp))
3959 break;
3960 retry = true;
3961 }
3962 } while (rc == -ENOSPC);
3963
3964 if (rc) {
3965 BNXT_NVM_ERR_MSG(dev, extack, MSG_RESIZE_UPDATE_ERR);
3966 return rc;
3967 }
3968 }
3969 return 0;
3970 }
3971
bnxt_flash_package_from_fw_obj(struct net_device * dev,const struct firmware * fw,u32 install_type,struct netlink_ext_ack * extack)3972 int bnxt_flash_package_from_fw_obj(struct net_device *dev, const struct firmware *fw,
3973 u32 install_type, struct netlink_ext_ack *extack)
3974 {
3975 struct hwrm_nvm_install_update_input *install;
3976 struct hwrm_nvm_install_update_output *resp;
3977 struct hwrm_nvm_modify_input *modify;
3978 struct bnxt *bp = netdev_priv(dev);
3979 bool defrag_attempted = false;
3980 dma_addr_t dma_handle;
3981 u8 *kmem = NULL;
3982 u32 modify_len;
3983 u32 item_len;
3984 u8 cmd_err;
3985 u16 index;
3986 int rc;
3987
3988 /* resize before flashing larger image than available space */
3989 rc = bnxt_resize_update_entry(dev, fw->size, extack);
3990 if (rc)
3991 return rc;
3992
3993 bnxt_hwrm_fw_set_time(bp);
3994
3995 rc = hwrm_req_init(bp, modify, HWRM_NVM_MODIFY);
3996 if (rc)
3997 return rc;
3998
3999 /* Try allocating a large DMA buffer first. Older fw will
4000 * cause excessive NVRAM erases when using small blocks.
4001 */
4002 modify_len = roundup_pow_of_two(fw->size);
4003 modify_len = min_t(u32, modify_len, BNXT_PKG_DMA_SIZE);
4004 while (1) {
4005 kmem = hwrm_req_dma_slice(bp, modify, modify_len, &dma_handle);
4006 if (!kmem && modify_len > PAGE_SIZE)
4007 modify_len /= 2;
4008 else
4009 break;
4010 }
4011 if (!kmem) {
4012 hwrm_req_drop(bp, modify);
4013 return -ENOMEM;
4014 }
4015
4016 rc = hwrm_req_init(bp, install, HWRM_NVM_INSTALL_UPDATE);
4017 if (rc) {
4018 hwrm_req_drop(bp, modify);
4019 return rc;
4020 }
4021
4022 hwrm_req_timeout(bp, modify, bp->hwrm_cmd_max_timeout);
4023 hwrm_req_timeout(bp, install, bp->hwrm_cmd_max_timeout);
4024
4025 hwrm_req_hold(bp, modify);
4026 modify->host_src_addr = cpu_to_le64(dma_handle);
4027
4028 resp = hwrm_req_hold(bp, install);
4029 if ((install_type & 0xffff) == 0)
4030 install_type >>= 16;
4031 install->install_type = cpu_to_le32(install_type);
4032
4033 do {
4034 u32 copied = 0, len = modify_len;
4035
4036 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_UPDATE,
4037 BNX_DIR_ORDINAL_FIRST,
4038 BNX_DIR_EXT_NONE,
4039 &index, &item_len, NULL);
4040 if (rc) {
4041 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_PKG_UPDATE_AREA_ERR);
4042 break;
4043 }
4044 if (fw->size > item_len) {
4045 BNXT_NVM_ERR_MSG(dev, extack, MSG_NO_SPACE_ERR);
4046 rc = -EFBIG;
4047 break;
4048 }
4049
4050 modify->dir_idx = cpu_to_le16(index);
4051
4052 if (fw->size > modify_len)
4053 modify->flags = BNXT_NVM_MORE_FLAG;
4054 while (copied < fw->size) {
4055 u32 balance = fw->size - copied;
4056
4057 if (balance <= modify_len) {
4058 len = balance;
4059 if (copied)
4060 modify->flags |= BNXT_NVM_LAST_FLAG;
4061 }
4062 memcpy(kmem, fw->data + copied, len);
4063 modify->len = cpu_to_le32(len);
4064 modify->offset = cpu_to_le32(copied);
4065 rc = hwrm_req_send(bp, modify);
4066 if (rc)
4067 goto pkg_abort;
4068 copied += len;
4069 }
4070
4071 rc = hwrm_req_send_silent(bp, install);
4072 if (!rc)
4073 break;
4074
4075 if (defrag_attempted) {
4076 /* We have tried to defragment already in the previous
4077 * iteration. Return with the result for INSTALL_UPDATE
4078 */
4079 break;
4080 }
4081
4082 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
4083
4084 switch (cmd_err) {
4085 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK:
4086 BNXT_NVM_ERR_MSG(dev, extack, MSG_ANTI_ROLLBACK_ERR);
4087 rc = -EALREADY;
4088 break;
4089 case NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR:
4090 install->flags =
4091 cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
4092
4093 rc = hwrm_req_send_silent(bp, install);
4094 if (!rc)
4095 break;
4096
4097 cmd_err = ((struct hwrm_err_output *)resp)->cmd_err;
4098
4099 if (cmd_err == NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE) {
4100 /* FW has cleared NVM area, driver will create
4101 * UPDATE directory and try the flash again
4102 */
4103 defrag_attempted = true;
4104 install->flags = 0;
4105 rc = bnxt_flash_nvram(bp->dev,
4106 BNX_DIR_TYPE_UPDATE,
4107 BNX_DIR_ORDINAL_FIRST,
4108 0, 0, item_len, NULL, 0);
4109 if (!rc)
4110 break;
4111 }
4112 fallthrough;
4113 default:
4114 BNXT_NVM_ERR_MSG(dev, extack, MSG_GENERIC_FAILURE_ERR);
4115 }
4116 } while (defrag_attempted && !rc);
4117
4118 pkg_abort:
4119 hwrm_req_drop(bp, modify);
4120 hwrm_req_drop(bp, install);
4121
4122 if (resp->result) {
4123 netdev_err(dev, "PKG install error = %d, problem_item = %d\n",
4124 (s8)resp->result, (int)resp->problem_item);
4125 rc = nvm_update_err_to_stderr(dev, resp->result, extack);
4126 }
4127 if (rc == -EACCES)
4128 bnxt_print_admin_err(bp);
4129 return rc;
4130 }
4131
bnxt_flash_package_from_file(struct net_device * dev,const char * filename,u32 install_type,struct netlink_ext_ack * extack)4132 static int bnxt_flash_package_from_file(struct net_device *dev, const char *filename,
4133 u32 install_type, struct netlink_ext_ack *extack)
4134 {
4135 const struct firmware *fw;
4136 int rc;
4137
4138 rc = request_firmware(&fw, filename, &dev->dev);
4139 if (rc != 0) {
4140 netdev_err(dev, "PKG error %d requesting file: %s\n",
4141 rc, filename);
4142 return rc;
4143 }
4144
4145 rc = bnxt_flash_package_from_fw_obj(dev, fw, install_type, extack);
4146
4147 release_firmware(fw);
4148
4149 return rc;
4150 }
4151
bnxt_flash_device(struct net_device * dev,struct ethtool_flash * flash)4152 static int bnxt_flash_device(struct net_device *dev,
4153 struct ethtool_flash *flash)
4154 {
4155 if (!BNXT_PF((struct bnxt *)netdev_priv(dev))) {
4156 netdev_err(dev, "flashdev not supported from a virtual function\n");
4157 return -EINVAL;
4158 }
4159
4160 if (flash->region == ETHTOOL_FLASH_ALL_REGIONS ||
4161 flash->region > 0xffff)
4162 return bnxt_flash_package_from_file(dev, flash->data,
4163 flash->region, NULL);
4164
4165 return bnxt_flash_firmware_from_file(dev, flash->region, flash->data);
4166 }
4167
nvm_get_dir_info(struct net_device * dev,u32 * entries,u32 * length)4168 static int nvm_get_dir_info(struct net_device *dev, u32 *entries, u32 *length)
4169 {
4170 struct hwrm_nvm_get_dir_info_output *output;
4171 struct hwrm_nvm_get_dir_info_input *req;
4172 struct bnxt *bp = netdev_priv(dev);
4173 int rc;
4174
4175 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_INFO);
4176 if (rc)
4177 return rc;
4178
4179 output = hwrm_req_hold(bp, req);
4180 rc = hwrm_req_send(bp, req);
4181 if (!rc) {
4182 *entries = le32_to_cpu(output->entries);
4183 *length = le32_to_cpu(output->entry_length);
4184 }
4185 hwrm_req_drop(bp, req);
4186 return rc;
4187 }
4188
bnxt_get_eeprom_len(struct net_device * dev)4189 static int bnxt_get_eeprom_len(struct net_device *dev)
4190 {
4191 struct bnxt *bp = netdev_priv(dev);
4192
4193 if (BNXT_VF(bp))
4194 return 0;
4195
4196 /* The -1 return value allows the entire 32-bit range of offsets to be
4197 * passed via the ethtool command-line utility.
4198 */
4199 return -1;
4200 }
4201
bnxt_get_nvram_directory(struct net_device * dev,u32 len,u8 * data)4202 static int bnxt_get_nvram_directory(struct net_device *dev, u32 len, u8 *data)
4203 {
4204 struct bnxt *bp = netdev_priv(dev);
4205 int rc;
4206 u32 dir_entries;
4207 u32 entry_length;
4208 u8 *buf;
4209 size_t buflen;
4210 dma_addr_t dma_handle;
4211 struct hwrm_nvm_get_dir_entries_input *req;
4212
4213 rc = nvm_get_dir_info(dev, &dir_entries, &entry_length);
4214 if (rc != 0)
4215 return rc;
4216
4217 if (!dir_entries || !entry_length)
4218 return -EIO;
4219
4220 /* Insert 2 bytes of directory info (count and size of entries) */
4221 if (len < 2)
4222 return -EINVAL;
4223
4224 *data++ = dir_entries;
4225 *data++ = entry_length;
4226 len -= 2;
4227 memset(data, 0xff, len);
4228
4229 rc = hwrm_req_init(bp, req, HWRM_NVM_GET_DIR_ENTRIES);
4230 if (rc)
4231 return rc;
4232
4233 buflen = mul_u32_u32(dir_entries, entry_length);
4234 buf = hwrm_req_dma_slice(bp, req, buflen, &dma_handle);
4235 if (!buf) {
4236 hwrm_req_drop(bp, req);
4237 return -ENOMEM;
4238 }
4239 req->host_dest_addr = cpu_to_le64(dma_handle);
4240
4241 hwrm_req_hold(bp, req); /* hold the slice */
4242 rc = hwrm_req_send(bp, req);
4243 if (rc == 0)
4244 memcpy(data, buf, len > buflen ? buflen : len);
4245 hwrm_req_drop(bp, req);
4246 return rc;
4247 }
4248
bnxt_get_nvram_item(struct net_device * dev,u32 index,u32 offset,u32 length,u8 * data)4249 int bnxt_get_nvram_item(struct net_device *dev, u32 index, u32 offset,
4250 u32 length, u8 *data)
4251 {
4252 struct bnxt *bp = netdev_priv(dev);
4253 int rc;
4254 u8 *buf;
4255 dma_addr_t dma_handle;
4256 struct hwrm_nvm_read_input *req;
4257
4258 if (!length)
4259 return -EINVAL;
4260
4261 rc = hwrm_req_init(bp, req, HWRM_NVM_READ);
4262 if (rc)
4263 return rc;
4264
4265 buf = hwrm_req_dma_slice(bp, req, length, &dma_handle);
4266 if (!buf) {
4267 hwrm_req_drop(bp, req);
4268 return -ENOMEM;
4269 }
4270
4271 req->host_dest_addr = cpu_to_le64(dma_handle);
4272 req->dir_idx = cpu_to_le16(index);
4273 req->offset = cpu_to_le32(offset);
4274 req->len = cpu_to_le32(length);
4275
4276 hwrm_req_hold(bp, req); /* hold the slice */
4277 rc = hwrm_req_send(bp, req);
4278 if (rc == 0)
4279 memcpy(data, buf, length);
4280 hwrm_req_drop(bp, req);
4281 return rc;
4282 }
4283
bnxt_find_nvram_item(struct net_device * dev,u16 type,u16 ordinal,u16 ext,u16 * index,u32 * item_length,u32 * data_length)4284 int bnxt_find_nvram_item(struct net_device *dev, u16 type, u16 ordinal,
4285 u16 ext, u16 *index, u32 *item_length,
4286 u32 *data_length)
4287 {
4288 struct hwrm_nvm_find_dir_entry_output *output;
4289 struct hwrm_nvm_find_dir_entry_input *req;
4290 struct bnxt *bp = netdev_priv(dev);
4291 int rc;
4292
4293 rc = hwrm_req_init(bp, req, HWRM_NVM_FIND_DIR_ENTRY);
4294 if (rc)
4295 return rc;
4296
4297 req->enables = 0;
4298 req->dir_idx = 0;
4299 req->dir_type = cpu_to_le16(type);
4300 req->dir_ordinal = cpu_to_le16(ordinal);
4301 req->dir_ext = cpu_to_le16(ext);
4302 req->opt_ordinal = NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ;
4303 output = hwrm_req_hold(bp, req);
4304 rc = hwrm_req_send_silent(bp, req);
4305 if (rc == 0) {
4306 if (index)
4307 *index = le16_to_cpu(output->dir_idx);
4308 if (item_length)
4309 *item_length = le32_to_cpu(output->dir_item_length);
4310 if (data_length)
4311 *data_length = le32_to_cpu(output->dir_data_length);
4312 }
4313 hwrm_req_drop(bp, req);
4314 return rc;
4315 }
4316
bnxt_parse_pkglog(int desired_field,u8 * data,size_t datalen)4317 static char *bnxt_parse_pkglog(int desired_field, u8 *data, size_t datalen)
4318 {
4319 char *retval = NULL;
4320 char *p;
4321 char *value;
4322 int field = 0;
4323
4324 if (datalen < 1)
4325 return NULL;
4326 /* null-terminate the log data (removing last '\n'): */
4327 data[datalen - 1] = 0;
4328 for (p = data; *p != 0; p++) {
4329 field = 0;
4330 retval = NULL;
4331 while (*p != 0 && *p != '\n') {
4332 value = p;
4333 while (*p != 0 && *p != '\t' && *p != '\n')
4334 p++;
4335 if (field == desired_field)
4336 retval = value;
4337 if (*p != '\t')
4338 break;
4339 *p = 0;
4340 field++;
4341 p++;
4342 }
4343 if (*p == 0)
4344 break;
4345 *p = 0;
4346 }
4347 return retval;
4348 }
4349
bnxt_get_pkginfo(struct net_device * dev,char * ver,int size)4350 int bnxt_get_pkginfo(struct net_device *dev, char *ver, int size)
4351 {
4352 struct bnxt *bp = netdev_priv(dev);
4353 u16 index = 0;
4354 char *pkgver;
4355 u32 pkglen;
4356 u8 *pkgbuf;
4357 int rc;
4358
4359 rc = bnxt_find_nvram_item(dev, BNX_DIR_TYPE_PKG_LOG,
4360 BNX_DIR_ORDINAL_FIRST, BNX_DIR_EXT_NONE,
4361 &index, NULL, &pkglen);
4362 if (rc)
4363 return rc;
4364
4365 pkgbuf = kzalloc(pkglen, GFP_KERNEL);
4366 if (!pkgbuf) {
4367 dev_err(&bp->pdev->dev, "Unable to allocate memory for pkg version, length = %u\n",
4368 pkglen);
4369 return -ENOMEM;
4370 }
4371
4372 rc = bnxt_get_nvram_item(dev, index, 0, pkglen, pkgbuf);
4373 if (rc)
4374 goto err;
4375
4376 pkgver = bnxt_parse_pkglog(BNX_PKG_LOG_FIELD_IDX_PKG_VERSION, pkgbuf,
4377 pkglen);
4378 if (pkgver && *pkgver != 0 && isdigit(*pkgver))
4379 strscpy(ver, pkgver, size);
4380 else
4381 rc = -ENOENT;
4382
4383 err:
4384 kfree(pkgbuf);
4385
4386 return rc;
4387 }
4388
bnxt_get_pkgver(struct net_device * dev)4389 static void bnxt_get_pkgver(struct net_device *dev)
4390 {
4391 struct bnxt *bp = netdev_priv(dev);
4392 char buf[FW_VER_STR_LEN - 5];
4393 int len;
4394
4395 if (!bnxt_get_pkginfo(dev, buf, sizeof(buf))) {
4396 len = strlen(bp->fw_ver_str);
4397 snprintf(bp->fw_ver_str + len, FW_VER_STR_LEN - len,
4398 "/pkg %s", buf);
4399 }
4400 }
4401
bnxt_get_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)4402 static int bnxt_get_eeprom(struct net_device *dev,
4403 struct ethtool_eeprom *eeprom,
4404 u8 *data)
4405 {
4406 u32 index;
4407 u32 offset;
4408
4409 if (eeprom->offset == 0) /* special offset value to get directory */
4410 return bnxt_get_nvram_directory(dev, eeprom->len, data);
4411
4412 index = eeprom->offset >> 24;
4413 offset = eeprom->offset & 0xffffff;
4414
4415 if (index == 0) {
4416 netdev_err(dev, "unsupported index value: %d\n", index);
4417 return -EINVAL;
4418 }
4419
4420 return bnxt_get_nvram_item(dev, index - 1, offset, eeprom->len, data);
4421 }
4422
bnxt_erase_nvram_directory(struct net_device * dev,u8 index)4423 static int bnxt_erase_nvram_directory(struct net_device *dev, u8 index)
4424 {
4425 struct hwrm_nvm_erase_dir_entry_input *req;
4426 struct bnxt *bp = netdev_priv(dev);
4427 int rc;
4428
4429 rc = hwrm_req_init(bp, req, HWRM_NVM_ERASE_DIR_ENTRY);
4430 if (rc)
4431 return rc;
4432
4433 req->dir_idx = cpu_to_le16(index);
4434 return hwrm_req_send(bp, req);
4435 }
4436
bnxt_set_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)4437 static int bnxt_set_eeprom(struct net_device *dev,
4438 struct ethtool_eeprom *eeprom,
4439 u8 *data)
4440 {
4441 struct bnxt *bp = netdev_priv(dev);
4442 u8 index, dir_op;
4443 u16 type, ext, ordinal, attr;
4444
4445 if (!BNXT_PF(bp)) {
4446 netdev_err(dev, "NVM write not supported from a virtual function\n");
4447 return -EINVAL;
4448 }
4449
4450 type = eeprom->magic >> 16;
4451
4452 if (type == 0xffff) { /* special value for directory operations */
4453 index = eeprom->magic & 0xff;
4454 dir_op = eeprom->magic >> 8;
4455 if (index == 0)
4456 return -EINVAL;
4457 switch (dir_op) {
4458 case 0x0e: /* erase */
4459 if (eeprom->offset != ~eeprom->magic)
4460 return -EINVAL;
4461 return bnxt_erase_nvram_directory(dev, index - 1);
4462 default:
4463 return -EINVAL;
4464 }
4465 }
4466
4467 /* Create or re-write an NVM item: */
4468 if (bnxt_dir_type_is_executable(type))
4469 return -EOPNOTSUPP;
4470 ext = eeprom->magic & 0xffff;
4471 ordinal = eeprom->offset >> 16;
4472 attr = eeprom->offset & 0xffff;
4473
4474 return bnxt_flash_nvram(dev, type, ordinal, ext, attr, 0, data,
4475 eeprom->len);
4476 }
4477
bnxt_set_eee(struct net_device * dev,struct ethtool_keee * edata)4478 static int bnxt_set_eee(struct net_device *dev, struct ethtool_keee *edata)
4479 {
4480 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
4481 __ETHTOOL_DECLARE_LINK_MODE_MASK(tmp);
4482 struct bnxt *bp = netdev_priv(dev);
4483 struct ethtool_keee *eee = &bp->eee;
4484 struct bnxt_link_info *link_info = &bp->link_info;
4485 int rc = 0;
4486
4487 if (!BNXT_PHY_CFG_ABLE(bp))
4488 return -EOPNOTSUPP;
4489
4490 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
4491 return -EOPNOTSUPP;
4492
4493 mutex_lock(&bp->link_lock);
4494 _bnxt_fw_to_linkmode(advertising, link_info->advertising);
4495 if (!edata->eee_enabled)
4496 goto eee_ok;
4497
4498 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4499 netdev_warn(dev, "EEE requires autoneg\n");
4500 rc = -EINVAL;
4501 goto eee_exit;
4502 }
4503 if (edata->tx_lpi_enabled) {
4504 if (bp->lpi_tmr_hi && (edata->tx_lpi_timer > bp->lpi_tmr_hi ||
4505 edata->tx_lpi_timer < bp->lpi_tmr_lo)) {
4506 netdev_warn(dev, "Valid LPI timer range is %d and %d microsecs\n",
4507 bp->lpi_tmr_lo, bp->lpi_tmr_hi);
4508 rc = -EINVAL;
4509 goto eee_exit;
4510 } else if (!bp->lpi_tmr_hi) {
4511 edata->tx_lpi_timer = eee->tx_lpi_timer;
4512 }
4513 }
4514 if (linkmode_empty(edata->advertised)) {
4515 linkmode_and(edata->advertised, advertising, eee->supported);
4516 } else if (linkmode_andnot(tmp, edata->advertised, advertising)) {
4517 netdev_warn(dev, "EEE advertised must be a subset of autoneg advertised speeds\n");
4518 rc = -EINVAL;
4519 goto eee_exit;
4520 }
4521
4522 linkmode_copy(eee->advertised, edata->advertised);
4523 eee->tx_lpi_enabled = edata->tx_lpi_enabled;
4524 eee->tx_lpi_timer = edata->tx_lpi_timer;
4525 eee_ok:
4526 eee->eee_enabled = edata->eee_enabled;
4527
4528 if (netif_running(dev))
4529 rc = bnxt_hwrm_set_link_setting(bp, false, true);
4530
4531 eee_exit:
4532 mutex_unlock(&bp->link_lock);
4533 return rc;
4534 }
4535
bnxt_get_eee(struct net_device * dev,struct ethtool_keee * edata)4536 static int bnxt_get_eee(struct net_device *dev, struct ethtool_keee *edata)
4537 {
4538 struct bnxt *bp = netdev_priv(dev);
4539
4540 if (!(bp->phy_flags & BNXT_PHY_FL_EEE_CAP))
4541 return -EOPNOTSUPP;
4542
4543 *edata = bp->eee;
4544 if (!bp->eee.eee_enabled) {
4545 /* Preserve tx_lpi_timer so that the last value will be used
4546 * by default when it is re-enabled.
4547 */
4548 linkmode_zero(edata->advertised);
4549 edata->tx_lpi_enabled = 0;
4550 }
4551
4552 if (!bp->eee.eee_active)
4553 linkmode_zero(edata->lp_advertised);
4554
4555 return 0;
4556 }
4557
bnxt_hwrm_pfcwd_qcfg(struct bnxt * bp,u16 * val)4558 static int bnxt_hwrm_pfcwd_qcfg(struct bnxt *bp, u16 *val)
4559 {
4560 struct hwrm_queue_pfcwd_timeout_qcfg_output *resp;
4561 struct hwrm_queue_pfcwd_timeout_qcfg_input *req;
4562 int rc;
4563
4564 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_QCFG);
4565 if (rc)
4566 return rc;
4567 resp = hwrm_req_hold(bp, req);
4568 rc = hwrm_req_send(bp, req);
4569 if (!rc)
4570 *val = le16_to_cpu(resp->pfcwd_timeout_value);
4571 hwrm_req_drop(bp, req);
4572 return rc;
4573 }
4574
bnxt_hwrm_pfcwd_cfg(struct bnxt * bp,u16 val)4575 static int bnxt_hwrm_pfcwd_cfg(struct bnxt *bp, u16 val)
4576 {
4577 struct hwrm_queue_pfcwd_timeout_cfg_input *req;
4578 int rc;
4579
4580 rc = hwrm_req_init(bp, req, HWRM_QUEUE_PFCWD_TIMEOUT_CFG);
4581 if (rc)
4582 return rc;
4583 req->pfcwd_timeout_value = cpu_to_le16(val);
4584 rc = hwrm_req_send(bp, req);
4585 return rc;
4586 }
4587
bnxt_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)4588 static int bnxt_set_tunable(struct net_device *dev,
4589 const struct ethtool_tunable *tuna,
4590 const void *data)
4591 {
4592 struct bnxt *bp = netdev_priv(dev);
4593 u32 rx_copybreak, val;
4594
4595 switch (tuna->id) {
4596 case ETHTOOL_RX_COPYBREAK:
4597 rx_copybreak = *(u32 *)data;
4598 if (rx_copybreak > BNXT_MAX_RX_HDR_BUF)
4599 return -ERANGE;
4600 if (rx_copybreak != bp->rx_copybreak) {
4601 if (netif_running(dev))
4602 return -EBUSY;
4603 bp->rx_copybreak = rx_copybreak;
4604 }
4605 return 0;
4606 case ETHTOOL_PFC_PREVENTION_TOUT:
4607 if (BNXT_VF(bp) || !bp->max_pfcwd_tmo_ms)
4608 return -EOPNOTSUPP;
4609
4610 val = *(u16 *)data;
4611 if (val > bp->max_pfcwd_tmo_ms &&
4612 val != PFC_STORM_PREVENTION_AUTO)
4613 return -EINVAL;
4614 return bnxt_hwrm_pfcwd_cfg(bp, val);
4615 default:
4616 return -EOPNOTSUPP;
4617 }
4618 }
4619
bnxt_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)4620 static int bnxt_get_tunable(struct net_device *dev,
4621 const struct ethtool_tunable *tuna, void *data)
4622 {
4623 struct bnxt *bp = netdev_priv(dev);
4624
4625 switch (tuna->id) {
4626 case ETHTOOL_RX_COPYBREAK:
4627 *(u32 *)data = bp->rx_copybreak;
4628 break;
4629 case ETHTOOL_PFC_PREVENTION_TOUT:
4630 if (!bp->max_pfcwd_tmo_ms)
4631 return -EOPNOTSUPP;
4632 return bnxt_hwrm_pfcwd_qcfg(bp, data);
4633 default:
4634 return -EOPNOTSUPP;
4635 }
4636
4637 return 0;
4638 }
4639
bnxt_read_sfp_module_eeprom_info(struct bnxt * bp,u16 i2c_addr,u16 page_number,u8 bank,u16 start_addr,u16 data_length,u8 * buf)4640 static int bnxt_read_sfp_module_eeprom_info(struct bnxt *bp, u16 i2c_addr,
4641 u16 page_number, u8 bank,
4642 u16 start_addr, u16 data_length,
4643 u8 *buf)
4644 {
4645 struct hwrm_port_phy_i2c_read_output *output;
4646 struct hwrm_port_phy_i2c_read_input *req;
4647 int rc, byte_offset = 0;
4648
4649 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_READ);
4650 if (rc)
4651 return rc;
4652
4653 output = hwrm_req_hold(bp, req);
4654 req->i2c_slave_addr = i2c_addr;
4655 req->page_number = cpu_to_le16(page_number);
4656 req->port_id = cpu_to_le16(bp->pf.port_id);
4657 do {
4658 u16 xfer_size;
4659
4660 xfer_size = min_t(u16, data_length, BNXT_MAX_PHY_I2C_RESP_SIZE);
4661 data_length -= xfer_size;
4662 req->page_offset = cpu_to_le16(start_addr + byte_offset);
4663 req->data_length = xfer_size;
4664 req->enables =
4665 cpu_to_le32((start_addr + byte_offset ?
4666 PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET :
4667 0) |
4668 (bank ?
4669 PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER :
4670 0));
4671 rc = hwrm_req_send(bp, req);
4672 if (!rc)
4673 memcpy(buf + byte_offset, output->data, xfer_size);
4674 byte_offset += xfer_size;
4675 } while (!rc && data_length > 0);
4676 hwrm_req_drop(bp, req);
4677
4678 return rc;
4679 }
4680
bnxt_get_module_info(struct net_device * dev,struct ethtool_modinfo * modinfo)4681 static int bnxt_get_module_info(struct net_device *dev,
4682 struct ethtool_modinfo *modinfo)
4683 {
4684 u8 data[SFF_DIAG_SUPPORT_OFFSET + 1];
4685 struct bnxt *bp = netdev_priv(dev);
4686 int rc;
4687
4688 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4689 return -EPERM;
4690
4691 /* No point in going further if phy status indicates
4692 * module is not inserted or if it is powered down or
4693 * if it is of type 10GBase-T
4694 */
4695 if (bp->link_info.module_status >
4696 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4697 return -EOPNOTSUPP;
4698
4699 /* This feature is not supported in older firmware versions */
4700 if (bp->hwrm_spec_code < 0x10202)
4701 return -EOPNOTSUPP;
4702
4703 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 0,
4704 SFF_DIAG_SUPPORT_OFFSET + 1,
4705 data);
4706 if (!rc) {
4707 u8 module_id = data[0];
4708 u8 diag_supported = data[SFF_DIAG_SUPPORT_OFFSET];
4709
4710 switch (module_id) {
4711 case SFF_MODULE_ID_SFP:
4712 modinfo->type = ETH_MODULE_SFF_8472;
4713 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
4714 if (!diag_supported)
4715 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4716 break;
4717 case SFF_MODULE_ID_QSFP:
4718 case SFF_MODULE_ID_QSFP_PLUS:
4719 modinfo->type = ETH_MODULE_SFF_8436;
4720 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
4721 break;
4722 case SFF_MODULE_ID_QSFP28:
4723 modinfo->type = ETH_MODULE_SFF_8636;
4724 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
4725 break;
4726 default:
4727 rc = -EOPNOTSUPP;
4728 break;
4729 }
4730 }
4731 return rc;
4732 }
4733
bnxt_get_module_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)4734 static int bnxt_get_module_eeprom(struct net_device *dev,
4735 struct ethtool_eeprom *eeprom,
4736 u8 *data)
4737 {
4738 struct bnxt *bp = netdev_priv(dev);
4739 u16 start = eeprom->offset, length = eeprom->len;
4740 int rc = 0;
4741
4742 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4743 return -EPERM;
4744
4745 memset(data, 0, eeprom->len);
4746
4747 /* Read A0 portion of the EEPROM */
4748 if (start < ETH_MODULE_SFF_8436_LEN) {
4749 if (start + eeprom->len > ETH_MODULE_SFF_8436_LEN)
4750 length = ETH_MODULE_SFF_8436_LEN - start;
4751 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
4752 start, length, data);
4753 if (rc)
4754 return rc;
4755 start += length;
4756 data += length;
4757 length = eeprom->len - length;
4758 }
4759
4760 /* Read A2 portion of the EEPROM */
4761 if (length) {
4762 start -= ETH_MODULE_SFF_8436_LEN;
4763 rc = bnxt_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A2, 0, 0,
4764 start, length, data);
4765 }
4766 return rc;
4767 }
4768
bnxt_get_module_status(struct bnxt * bp,struct netlink_ext_ack * extack)4769 static int bnxt_get_module_status(struct bnxt *bp, struct netlink_ext_ack *extack)
4770 {
4771 if (bp->link_info.module_status <=
4772 PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG)
4773 return 0;
4774
4775 if (bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASET ||
4776 bp->link_info.phy_type == PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE){
4777 NL_SET_ERR_MSG_MOD(extack, "Operation not supported as PHY type is Base-T");
4778 return -EOPNOTSUPP;
4779 }
4780 switch (bp->link_info.module_status) {
4781 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4782 NL_SET_ERR_MSG_MOD(extack, "Transceiver module is powering down");
4783 break;
4784 case PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED:
4785 NL_SET_ERR_MSG_MOD(extack, "Transceiver module not inserted");
4786 break;
4787 case PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT:
4788 NL_SET_ERR_MSG_MOD(extack, "Transceiver module disabled due to current fault");
4789 break;
4790 default:
4791 NL_SET_ERR_MSG_MOD(extack, "Unknown error");
4792 break;
4793 }
4794 return -EINVAL;
4795 }
4796
4797 static int
bnxt_mod_eeprom_by_page_precheck(struct bnxt * bp,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)4798 bnxt_mod_eeprom_by_page_precheck(struct bnxt *bp,
4799 const struct ethtool_module_eeprom *page_data,
4800 struct netlink_ext_ack *extack)
4801 {
4802 int rc;
4803
4804 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
4805 NL_SET_ERR_MSG_MOD(extack,
4806 "Module read/write not permitted on untrusted VF");
4807 return -EPERM;
4808 }
4809
4810 rc = bnxt_get_module_status(bp, extack);
4811 if (rc)
4812 return rc;
4813
4814 if (bp->hwrm_spec_code < 0x10202) {
4815 NL_SET_ERR_MSG_MOD(extack, "Firmware version too old");
4816 return -EINVAL;
4817 }
4818
4819 if (page_data->bank && !(bp->phy_flags & BNXT_PHY_FL_BANK_SEL)) {
4820 NL_SET_ERR_MSG_MOD(extack, "Firmware not capable for bank selection");
4821 return -EINVAL;
4822 }
4823 return 0;
4824 }
4825
bnxt_get_module_eeprom_by_page(struct net_device * dev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)4826 static int bnxt_get_module_eeprom_by_page(struct net_device *dev,
4827 const struct ethtool_module_eeprom *page_data,
4828 struct netlink_ext_ack *extack)
4829 {
4830 struct bnxt *bp = netdev_priv(dev);
4831 int rc;
4832
4833 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack);
4834 if (rc)
4835 return rc;
4836
4837 rc = bnxt_read_sfp_module_eeprom_info(bp, page_data->i2c_address << 1,
4838 page_data->page, page_data->bank,
4839 page_data->offset,
4840 page_data->length,
4841 page_data->data);
4842 if (rc) {
4843 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom read failed");
4844 return rc;
4845 }
4846 return page_data->length;
4847 }
4848
bnxt_write_sfp_module_eeprom_info(struct bnxt * bp,const struct ethtool_module_eeprom * page)4849 static int bnxt_write_sfp_module_eeprom_info(struct bnxt *bp,
4850 const struct ethtool_module_eeprom *page)
4851 {
4852 struct hwrm_port_phy_i2c_write_input *req;
4853 int bytes_written = 0;
4854 int rc;
4855
4856 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_I2C_WRITE);
4857 if (rc)
4858 return rc;
4859
4860 hwrm_req_hold(bp, req);
4861 req->i2c_slave_addr = page->i2c_address << 1;
4862 req->page_number = cpu_to_le16(page->page);
4863 req->bank_number = page->bank;
4864 req->port_id = cpu_to_le16(bp->pf.port_id);
4865 req->enables = cpu_to_le32(PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET |
4866 PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER);
4867
4868 while (bytes_written < page->length) {
4869 u16 xfer_size;
4870
4871 xfer_size = min_t(u16, page->length - bytes_written,
4872 BNXT_MAX_PHY_I2C_RESP_SIZE);
4873 req->page_offset = cpu_to_le16(page->offset + bytes_written);
4874 req->data_length = xfer_size;
4875 memcpy(req->data, page->data + bytes_written, xfer_size);
4876 rc = hwrm_req_send(bp, req);
4877 if (rc)
4878 break;
4879 bytes_written += xfer_size;
4880 }
4881
4882 hwrm_req_drop(bp, req);
4883 return rc;
4884 }
4885
bnxt_set_module_eeprom_by_page(struct net_device * dev,const struct ethtool_module_eeprom * page_data,struct netlink_ext_ack * extack)4886 static int bnxt_set_module_eeprom_by_page(struct net_device *dev,
4887 const struct ethtool_module_eeprom *page_data,
4888 struct netlink_ext_ack *extack)
4889 {
4890 struct bnxt *bp = netdev_priv(dev);
4891 int rc;
4892
4893 rc = bnxt_mod_eeprom_by_page_precheck(bp, page_data, extack);
4894 if (rc)
4895 return rc;
4896
4897 rc = bnxt_write_sfp_module_eeprom_info(bp, page_data);
4898 if (rc) {
4899 NL_SET_ERR_MSG_MOD(extack, "Module`s eeprom write failed");
4900 return rc;
4901 }
4902 return page_data->length;
4903 }
4904
bnxt_nway_reset(struct net_device * dev)4905 static int bnxt_nway_reset(struct net_device *dev)
4906 {
4907 int rc = 0;
4908
4909 struct bnxt *bp = netdev_priv(dev);
4910 struct bnxt_link_info *link_info = &bp->link_info;
4911
4912 if (!BNXT_PHY_CFG_ABLE(bp))
4913 return -EOPNOTSUPP;
4914
4915 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED))
4916 return -EINVAL;
4917
4918 if (netif_running(dev))
4919 rc = bnxt_hwrm_set_link_setting(bp, true, false);
4920
4921 return rc;
4922 }
4923
bnxt_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)4924 static int bnxt_set_phys_id(struct net_device *dev,
4925 enum ethtool_phys_id_state state)
4926 {
4927 struct hwrm_port_led_cfg_input *req;
4928 struct bnxt *bp = netdev_priv(dev);
4929 struct bnxt_pf_info *pf = &bp->pf;
4930 struct bnxt_led_cfg *led_cfg;
4931 u8 led_state;
4932 __le16 duration;
4933 int rc, i;
4934
4935 if (!bp->num_leds || BNXT_VF(bp))
4936 return -EOPNOTSUPP;
4937
4938 if (state == ETHTOOL_ID_ACTIVE) {
4939 led_state = PORT_LED_CFG_REQ_LED0_STATE_BLINKALT;
4940 duration = cpu_to_le16(500);
4941 } else if (state == ETHTOOL_ID_INACTIVE) {
4942 led_state = PORT_LED_CFG_REQ_LED1_STATE_DEFAULT;
4943 duration = cpu_to_le16(0);
4944 } else {
4945 return -EINVAL;
4946 }
4947 rc = hwrm_req_init(bp, req, HWRM_PORT_LED_CFG);
4948 if (rc)
4949 return rc;
4950
4951 req->port_id = cpu_to_le16(pf->port_id);
4952 req->num_leds = bp->num_leds;
4953 led_cfg = (struct bnxt_led_cfg *)&req->led0_id;
4954 for (i = 0; i < bp->num_leds; i++, led_cfg++) {
4955 req->enables |= BNXT_LED_DFLT_ENABLES(i);
4956 led_cfg->led_id = bp->leds[i].led_id;
4957 led_cfg->led_state = led_state;
4958 led_cfg->led_blink_on = duration;
4959 led_cfg->led_blink_off = duration;
4960 led_cfg->led_group_id = bp->leds[i].led_group_id;
4961 }
4962 return hwrm_req_send(bp, req);
4963 }
4964
bnxt_hwrm_selftest_irq(struct bnxt * bp,u16 cmpl_ring)4965 static int bnxt_hwrm_selftest_irq(struct bnxt *bp, u16 cmpl_ring)
4966 {
4967 struct hwrm_selftest_irq_input *req;
4968 int rc;
4969
4970 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_IRQ);
4971 if (rc)
4972 return rc;
4973
4974 req->cmpl_ring = cpu_to_le16(cmpl_ring);
4975 return hwrm_req_send(bp, req);
4976 }
4977
bnxt_test_irq(struct bnxt * bp)4978 static int bnxt_test_irq(struct bnxt *bp)
4979 {
4980 int i;
4981
4982 for (i = 0; i < bp->cp_nr_rings; i++) {
4983 u16 cmpl_ring = bp->grp_info[i].cp_fw_ring_id;
4984 int rc;
4985
4986 rc = bnxt_hwrm_selftest_irq(bp, cmpl_ring);
4987 if (rc)
4988 return rc;
4989 }
4990 return 0;
4991 }
4992
bnxt_hwrm_mac_loopback(struct bnxt * bp,bool enable)4993 static int bnxt_hwrm_mac_loopback(struct bnxt *bp, bool enable)
4994 {
4995 struct hwrm_port_mac_cfg_input *req;
4996 int rc;
4997
4998 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
4999 if (rc)
5000 return rc;
5001
5002 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_LPBK);
5003 if (enable)
5004 req->lpbk = PORT_MAC_CFG_REQ_LPBK_LOCAL;
5005 else
5006 req->lpbk = PORT_MAC_CFG_REQ_LPBK_NONE;
5007 return hwrm_req_send(bp, req);
5008 }
5009
bnxt_query_force_speeds(struct bnxt * bp,u16 * force_speeds)5010 static int bnxt_query_force_speeds(struct bnxt *bp, u16 *force_speeds)
5011 {
5012 struct hwrm_port_phy_qcaps_output *resp;
5013 struct hwrm_port_phy_qcaps_input *req;
5014 int rc;
5015
5016 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_QCAPS);
5017 if (rc)
5018 return rc;
5019
5020 resp = hwrm_req_hold(bp, req);
5021 rc = hwrm_req_send(bp, req);
5022 if (!rc)
5023 *force_speeds = le16_to_cpu(resp->supported_speeds_force_mode);
5024
5025 hwrm_req_drop(bp, req);
5026 return rc;
5027 }
5028
bnxt_disable_an_for_lpbk(struct bnxt * bp,struct hwrm_port_phy_cfg_input * req)5029 static int bnxt_disable_an_for_lpbk(struct bnxt *bp,
5030 struct hwrm_port_phy_cfg_input *req)
5031 {
5032 struct bnxt_link_info *link_info = &bp->link_info;
5033 u16 fw_advertising;
5034 u16 fw_speed;
5035 int rc;
5036
5037 if (!link_info->autoneg ||
5038 (bp->phy_flags & BNXT_PHY_FL_AN_PHY_LPBK))
5039 return 0;
5040
5041 rc = bnxt_query_force_speeds(bp, &fw_advertising);
5042 if (rc)
5043 return rc;
5044
5045 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB;
5046 if (BNXT_LINK_IS_UP(bp))
5047 fw_speed = bp->link_info.link_speed;
5048 else if (fw_advertising & BNXT_LINK_SPEED_MSK_10GB)
5049 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB;
5050 else if (fw_advertising & BNXT_LINK_SPEED_MSK_25GB)
5051 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB;
5052 else if (fw_advertising & BNXT_LINK_SPEED_MSK_40GB)
5053 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB;
5054 else if (fw_advertising & BNXT_LINK_SPEED_MSK_50GB)
5055 fw_speed = PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB;
5056
5057 req->force_link_speed = cpu_to_le16(fw_speed);
5058 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE |
5059 PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5060 rc = hwrm_req_send(bp, req);
5061 req->flags = 0;
5062 req->force_link_speed = cpu_to_le16(0);
5063 return rc;
5064 }
5065
bnxt_hwrm_phy_loopback(struct bnxt * bp,bool enable,bool ext)5066 static int bnxt_hwrm_phy_loopback(struct bnxt *bp, bool enable, bool ext)
5067 {
5068 struct hwrm_port_phy_cfg_input *req;
5069 int rc;
5070
5071 rc = hwrm_req_init(bp, req, HWRM_PORT_PHY_CFG);
5072 if (rc)
5073 return rc;
5074
5075 /* prevent bnxt_disable_an_for_lpbk() from consuming the request */
5076 hwrm_req_hold(bp, req);
5077
5078 if (enable) {
5079 bnxt_disable_an_for_lpbk(bp, req);
5080 if (ext)
5081 req->lpbk = PORT_PHY_CFG_REQ_LPBK_EXTERNAL;
5082 else
5083 req->lpbk = PORT_PHY_CFG_REQ_LPBK_LOCAL;
5084 } else {
5085 req->lpbk = PORT_PHY_CFG_REQ_LPBK_NONE;
5086 }
5087 req->enables = cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_LPBK);
5088 rc = hwrm_req_send(bp, req);
5089 hwrm_req_drop(bp, req);
5090 return rc;
5091 }
5092
bnxt_rx_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,u32 raw_cons,int pkt_size)5093 static int bnxt_rx_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
5094 u32 raw_cons, int pkt_size)
5095 {
5096 struct bnxt_napi *bnapi = cpr->bnapi;
5097 struct bnxt_rx_ring_info *rxr;
5098 struct bnxt_sw_rx_bd *rx_buf;
5099 struct rx_cmp *rxcmp;
5100 u16 cp_cons, cons;
5101 u8 *data;
5102 u32 len;
5103 int i;
5104
5105 rxr = bnapi->rx_ring;
5106 cp_cons = RING_CMP(raw_cons);
5107 rxcmp = (struct rx_cmp *)
5108 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
5109 cons = rxcmp->rx_cmp_opaque;
5110 rx_buf = &rxr->rx_buf_ring[cons];
5111 data = rx_buf->data_ptr;
5112 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
5113 if (len != pkt_size)
5114 return -EIO;
5115 i = ETH_ALEN;
5116 if (!ether_addr_equal(data + i, bnapi->bp->dev->dev_addr))
5117 return -EIO;
5118 i += ETH_ALEN;
5119 for ( ; i < pkt_size; i++) {
5120 if (data[i] != (u8)(i & 0xff))
5121 return -EIO;
5122 }
5123 return 0;
5124 }
5125
bnxt_poll_loopback(struct bnxt * bp,struct bnxt_cp_ring_info * cpr,int pkt_size)5126 static int bnxt_poll_loopback(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
5127 int pkt_size)
5128 {
5129 struct tx_cmp *txcmp;
5130 int rc = -EIO;
5131 u32 raw_cons;
5132 u32 cons;
5133 int i;
5134
5135 raw_cons = cpr->cp_raw_cons;
5136 for (i = 0; i < 200; i++) {
5137 cons = RING_CMP(raw_cons);
5138 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
5139
5140 if (!TX_CMP_VALID(txcmp, raw_cons)) {
5141 udelay(5);
5142 continue;
5143 }
5144
5145 /* The valid test of the entry must be done first before
5146 * reading any further.
5147 */
5148 dma_rmb();
5149 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_CMP ||
5150 TX_CMP_TYPE(txcmp) == CMP_TYPE_RX_L2_V3_CMP) {
5151 rc = bnxt_rx_loopback(bp, cpr, raw_cons, pkt_size);
5152 raw_cons = NEXT_RAW_CMP(raw_cons);
5153 raw_cons = NEXT_RAW_CMP(raw_cons);
5154 break;
5155 }
5156 raw_cons = NEXT_RAW_CMP(raw_cons);
5157 }
5158 cpr->cp_raw_cons = raw_cons;
5159 return rc;
5160 }
5161
bnxt_run_loopback(struct bnxt * bp)5162 static int bnxt_run_loopback(struct bnxt *bp)
5163 {
5164 struct bnxt_tx_ring_info *txr = &bp->tx_ring[0];
5165 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5166 struct bnxt_cp_ring_info *cpr;
5167 int pkt_size, i = 0;
5168 struct sk_buff *skb;
5169 dma_addr_t map;
5170 u8 *data;
5171 int rc;
5172
5173 cpr = &rxr->bnapi->cp_ring;
5174 if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
5175 cpr = rxr->rx_cpr;
5176 pkt_size = min(bp->dev->mtu + ETH_HLEN, max(BNXT_MIN_RX_HDR_BUF,
5177 bp->rx_copybreak));
5178 skb = netdev_alloc_skb(bp->dev, pkt_size);
5179 if (!skb)
5180 return -ENOMEM;
5181 data = skb_put(skb, pkt_size);
5182 ether_addr_copy(&data[i], bp->dev->dev_addr);
5183 i += ETH_ALEN;
5184 ether_addr_copy(&data[i], bp->dev->dev_addr);
5185 i += ETH_ALEN;
5186 for ( ; i < pkt_size; i++)
5187 data[i] = (u8)(i & 0xff);
5188
5189 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5190 DMA_TO_DEVICE);
5191 if (dma_mapping_error(&bp->pdev->dev, map)) {
5192 dev_kfree_skb(skb);
5193 return -EIO;
5194 }
5195 bnxt_xmit_bd(bp, txr, map, pkt_size, NULL);
5196
5197 /* Sync BD data before updating doorbell */
5198 wmb();
5199
5200 bnxt_db_write(bp, &txr->tx_db, txr->tx_prod);
5201 rc = bnxt_poll_loopback(bp, cpr, pkt_size);
5202
5203 dma_unmap_single(&bp->pdev->dev, map, pkt_size, DMA_TO_DEVICE);
5204 dev_kfree_skb(skb);
5205 return rc;
5206 }
5207
bnxt_run_fw_tests(struct bnxt * bp,u8 test_mask,u8 * test_results)5208 static int bnxt_run_fw_tests(struct bnxt *bp, u8 test_mask, u8 *test_results)
5209 {
5210 struct hwrm_selftest_exec_output *resp;
5211 struct hwrm_selftest_exec_input *req;
5212 int rc;
5213
5214 rc = hwrm_req_init(bp, req, HWRM_SELFTEST_EXEC);
5215 if (rc)
5216 return rc;
5217
5218 hwrm_req_timeout(bp, req, bp->test_info->timeout);
5219 req->flags = test_mask;
5220
5221 resp = hwrm_req_hold(bp, req);
5222 rc = hwrm_req_send(bp, req);
5223 *test_results = resp->test_success;
5224 hwrm_req_drop(bp, req);
5225 return rc;
5226 }
5227
5228 #define BNXT_DRV_TESTS 4
5229 #define BNXT_MACLPBK_TEST_IDX (bp->num_tests - BNXT_DRV_TESTS)
5230 #define BNXT_PHYLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 1)
5231 #define BNXT_EXTLPBK_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 2)
5232 #define BNXT_IRQ_TEST_IDX (BNXT_MACLPBK_TEST_IDX + 3)
5233
bnxt_self_test(struct net_device * dev,struct ethtool_test * etest,u64 * buf)5234 static void bnxt_self_test(struct net_device *dev, struct ethtool_test *etest,
5235 u64 *buf)
5236 {
5237 struct bnxt *bp = netdev_priv(dev);
5238 bool do_ext_lpbk = false;
5239 bool offline = false;
5240 u8 test_results = 0;
5241 u8 test_mask = 0;
5242 int rc = 0, i;
5243
5244 if (!bp->num_tests || !BNXT_PF(bp))
5245 return;
5246
5247 memset(buf, 0, sizeof(u64) * bp->num_tests);
5248 if (etest->flags & ETH_TEST_FL_OFFLINE &&
5249 bnxt_ulp_registered(bp->edev[BNXT_AUXDEV_RDMA])) {
5250 etest->flags |= ETH_TEST_FL_FAILED;
5251 netdev_warn(dev, "Offline tests cannot be run with RoCE driver loaded\n");
5252 return;
5253 }
5254
5255 if (!netif_running(dev)) {
5256 etest->flags |= ETH_TEST_FL_FAILED;
5257 return;
5258 }
5259
5260 if ((etest->flags & ETH_TEST_FL_EXTERNAL_LB) &&
5261 (bp->phy_flags & BNXT_PHY_FL_EXT_LPBK))
5262 do_ext_lpbk = true;
5263
5264 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5265 if (bp->pf.active_vfs || !BNXT_SINGLE_PF(bp)) {
5266 etest->flags |= ETH_TEST_FL_FAILED;
5267 netdev_warn(dev, "Offline tests cannot be run with active VFs or on shared PF\n");
5268 return;
5269 }
5270 offline = true;
5271 }
5272
5273 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
5274 u8 bit_val = 1 << i;
5275
5276 if (!(bp->test_info->offline_mask & bit_val))
5277 test_mask |= bit_val;
5278 else if (offline)
5279 test_mask |= bit_val;
5280 }
5281 if (!offline) {
5282 bnxt_run_fw_tests(bp, test_mask, &test_results);
5283 } else {
5284 bnxt_close_nic(bp, true, false);
5285 bnxt_run_fw_tests(bp, test_mask, &test_results);
5286
5287 rc = bnxt_half_open_nic(bp);
5288 if (rc) {
5289 etest->flags |= ETH_TEST_FL_FAILED;
5290 return;
5291 }
5292 buf[BNXT_MACLPBK_TEST_IDX] = 1;
5293 if (bp->mac_flags & BNXT_MAC_FL_NO_MAC_LPBK)
5294 goto skip_mac_loopback;
5295
5296 bnxt_hwrm_mac_loopback(bp, true);
5297 msleep(250);
5298 if (bnxt_run_loopback(bp))
5299 etest->flags |= ETH_TEST_FL_FAILED;
5300 else
5301 buf[BNXT_MACLPBK_TEST_IDX] = 0;
5302
5303 bnxt_hwrm_mac_loopback(bp, false);
5304 skip_mac_loopback:
5305 buf[BNXT_PHYLPBK_TEST_IDX] = 1;
5306 if (bp->phy_flags & BNXT_PHY_FL_NO_PHY_LPBK)
5307 goto skip_phy_loopback;
5308
5309 bnxt_hwrm_phy_loopback(bp, true, false);
5310 msleep(1000);
5311 if (bnxt_run_loopback(bp))
5312 etest->flags |= ETH_TEST_FL_FAILED;
5313 else
5314 buf[BNXT_PHYLPBK_TEST_IDX] = 0;
5315 skip_phy_loopback:
5316 buf[BNXT_EXTLPBK_TEST_IDX] = 1;
5317 if (do_ext_lpbk) {
5318 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
5319 bnxt_hwrm_phy_loopback(bp, true, true);
5320 msleep(1000);
5321 if (bnxt_run_loopback(bp))
5322 etest->flags |= ETH_TEST_FL_FAILED;
5323 else
5324 buf[BNXT_EXTLPBK_TEST_IDX] = 0;
5325 }
5326 bnxt_hwrm_phy_loopback(bp, false, false);
5327 bnxt_half_close_nic(bp);
5328 rc = bnxt_open_nic(bp, true, true);
5329 }
5330 if (rc || bnxt_test_irq(bp)) {
5331 buf[BNXT_IRQ_TEST_IDX] = 1;
5332 etest->flags |= ETH_TEST_FL_FAILED;
5333 }
5334 for (i = 0; i < bp->num_tests - BNXT_DRV_TESTS; i++) {
5335 u8 bit_val = 1 << i;
5336
5337 if ((test_mask & bit_val) && !(test_results & bit_val)) {
5338 buf[i] = 1;
5339 etest->flags |= ETH_TEST_FL_FAILED;
5340 }
5341 }
5342 }
5343
bnxt_reset(struct net_device * dev,u32 * flags)5344 static int bnxt_reset(struct net_device *dev, u32 *flags)
5345 {
5346 struct bnxt *bp = netdev_priv(dev);
5347 bool reload = false;
5348 u32 req = *flags;
5349
5350 if (!req)
5351 return -EINVAL;
5352
5353 if (!BNXT_PF(bp)) {
5354 netdev_err(dev, "Reset is not supported from a VF\n");
5355 return -EOPNOTSUPP;
5356 }
5357
5358 if (pci_vfs_assigned(bp->pdev) &&
5359 !(bp->fw_cap & BNXT_FW_CAP_HOT_RESET)) {
5360 netdev_err(dev,
5361 "Reset not allowed when VFs are assigned to VMs\n");
5362 return -EBUSY;
5363 }
5364
5365 if ((req & BNXT_FW_RESET_CHIP) == BNXT_FW_RESET_CHIP) {
5366 /* This feature is not supported in older firmware versions */
5367 if (bp->hwrm_spec_code >= 0x10803) {
5368 if (!bnxt_firmware_reset_chip(dev)) {
5369 netdev_info(dev, "Firmware reset request successful.\n");
5370 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET))
5371 reload = true;
5372 *flags &= ~BNXT_FW_RESET_CHIP;
5373 }
5374 } else if (req == BNXT_FW_RESET_CHIP) {
5375 return -EOPNOTSUPP; /* only request, fail hard */
5376 }
5377 }
5378
5379 if (!BNXT_CHIP_P4_PLUS(bp) && (req & BNXT_FW_RESET_AP)) {
5380 /* This feature is not supported in older firmware versions */
5381 if (bp->hwrm_spec_code >= 0x10803) {
5382 if (!bnxt_firmware_reset_ap(dev)) {
5383 netdev_info(dev, "Reset application processor successful.\n");
5384 reload = true;
5385 *flags &= ~BNXT_FW_RESET_AP;
5386 }
5387 } else if (req == BNXT_FW_RESET_AP) {
5388 return -EOPNOTSUPP; /* only request, fail hard */
5389 }
5390 }
5391
5392 if (reload)
5393 netdev_info(dev, "Reload driver to complete reset\n");
5394
5395 return 0;
5396 }
5397
bnxt_set_dump(struct net_device * dev,struct ethtool_dump * dump)5398 static int bnxt_set_dump(struct net_device *dev, struct ethtool_dump *dump)
5399 {
5400 struct bnxt *bp = netdev_priv(dev);
5401
5402 if (dump->flag > BNXT_DUMP_LIVE_WITH_CTX_L1_CACHE) {
5403 netdev_info(dev,
5404 "Supports only Live(0), Crash(1), Driver(2), Live with cached context(3) dumps.\n");
5405 return -EINVAL;
5406 }
5407
5408 if (dump->flag == BNXT_DUMP_CRASH) {
5409 if (bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR &&
5410 (!IS_ENABLED(CONFIG_TEE_BNXT_FW))) {
5411 netdev_info(dev,
5412 "Cannot collect crash dump as TEE_BNXT_FW config option is not enabled.\n");
5413 return -EOPNOTSUPP;
5414 } else if (!(bp->fw_dbg_cap & DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR)) {
5415 netdev_info(dev, "Crash dump collection from host memory is not supported on this interface.\n");
5416 return -EOPNOTSUPP;
5417 }
5418 }
5419
5420 bp->dump_flag = dump->flag;
5421 return 0;
5422 }
5423
bnxt_get_dump_flag(struct net_device * dev,struct ethtool_dump * dump)5424 static int bnxt_get_dump_flag(struct net_device *dev, struct ethtool_dump *dump)
5425 {
5426 struct bnxt *bp = netdev_priv(dev);
5427
5428 if (bp->hwrm_spec_code < 0x10801)
5429 return -EOPNOTSUPP;
5430
5431 dump->version = bp->ver_resp.hwrm_fw_maj_8b << 24 |
5432 bp->ver_resp.hwrm_fw_min_8b << 16 |
5433 bp->ver_resp.hwrm_fw_bld_8b << 8 |
5434 bp->ver_resp.hwrm_fw_rsvd_8b;
5435
5436 dump->flag = bp->dump_flag;
5437 dump->len = bnxt_get_coredump_length(bp, bp->dump_flag);
5438 return 0;
5439 }
5440
bnxt_get_dump_data(struct net_device * dev,struct ethtool_dump * dump,void * buf)5441 static int bnxt_get_dump_data(struct net_device *dev, struct ethtool_dump *dump,
5442 void *buf)
5443 {
5444 struct bnxt *bp = netdev_priv(dev);
5445
5446 if (bp->hwrm_spec_code < 0x10801)
5447 return -EOPNOTSUPP;
5448
5449 memset(buf, 0, dump->len);
5450
5451 dump->flag = bp->dump_flag;
5452 return bnxt_get_coredump(bp, dump->flag, buf, &dump->len);
5453 }
5454
bnxt_get_ts_info(struct net_device * dev,struct kernel_ethtool_ts_info * info)5455 static int bnxt_get_ts_info(struct net_device *dev,
5456 struct kernel_ethtool_ts_info *info)
5457 {
5458 struct bnxt *bp = netdev_priv(dev);
5459 struct bnxt_ptp_cfg *ptp;
5460
5461 ptp = bp->ptp_cfg;
5462 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE;
5463
5464 if (!ptp)
5465 return 0;
5466
5467 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
5468 SOF_TIMESTAMPING_RX_HARDWARE |
5469 SOF_TIMESTAMPING_RAW_HARDWARE;
5470 if (ptp->ptp_clock)
5471 info->phc_index = ptp_clock_index(ptp->ptp_clock);
5472
5473 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
5474
5475 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
5476 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
5477 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
5478
5479 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
5480 info->rx_filters |= (1 << HWTSTAMP_FILTER_ALL);
5481 return 0;
5482 }
5483
bnxt_hwrm_pcie_qstats(struct bnxt * bp)5484 static void bnxt_hwrm_pcie_qstats(struct bnxt *bp)
5485 {
5486 struct hwrm_pcie_qstats_output *resp;
5487 struct hwrm_pcie_qstats_input *req;
5488
5489 bp->pcie_stat_len = 0;
5490 if (!(bp->fw_cap & BNXT_FW_CAP_PCIE_STATS_SUPPORTED))
5491 return;
5492
5493 if (hwrm_req_init(bp, req, HWRM_PCIE_QSTATS))
5494 return;
5495
5496 resp = hwrm_req_hold(bp, req);
5497 if (__bnxt_hwrm_pcie_qstats(bp, req))
5498 bp->pcie_stat_len = min_t(u16,
5499 le16_to_cpu(resp->pcie_stat_size),
5500 sizeof(struct pcie_ctx_hw_stats_v2));
5501 hwrm_req_drop(bp, req);
5502 }
5503
bnxt_ethtool_init(struct bnxt * bp)5504 void bnxt_ethtool_init(struct bnxt *bp)
5505 {
5506 struct hwrm_selftest_qlist_output *resp;
5507 struct hwrm_selftest_qlist_input *req;
5508 struct bnxt_test_info *test_info;
5509 struct net_device *dev = bp->dev;
5510 int i, rc;
5511
5512 bnxt_hwrm_pcie_qstats(bp);
5513 if (!(bp->fw_cap & BNXT_FW_CAP_PKG_VER))
5514 bnxt_get_pkgver(dev);
5515
5516 bp->num_tests = 0;
5517 if (bp->hwrm_spec_code < 0x10704 || !BNXT_PF(bp))
5518 return;
5519
5520 test_info = bp->test_info;
5521 if (!test_info) {
5522 test_info = kzalloc_obj(*bp->test_info);
5523 if (!test_info)
5524 return;
5525 bp->test_info = test_info;
5526 }
5527
5528 if (hwrm_req_init(bp, req, HWRM_SELFTEST_QLIST))
5529 return;
5530
5531 resp = hwrm_req_hold(bp, req);
5532 rc = hwrm_req_send_silent(bp, req);
5533 if (rc)
5534 goto ethtool_init_exit;
5535
5536 bp->num_tests = resp->num_tests + BNXT_DRV_TESTS;
5537 if (bp->num_tests > BNXT_MAX_TEST)
5538 bp->num_tests = BNXT_MAX_TEST;
5539
5540 test_info->offline_mask = resp->offline_tests;
5541 test_info->timeout = le16_to_cpu(resp->test_timeout);
5542 if (!test_info->timeout)
5543 test_info->timeout = HWRM_CMD_TIMEOUT;
5544 for (i = 0; i < bp->num_tests; i++) {
5545 char *str = test_info->string[i];
5546 char *fw_str = resp->test_name[i];
5547
5548 if (i == BNXT_MACLPBK_TEST_IDX) {
5549 strcpy(str, "Mac loopback test (offline)");
5550 } else if (i == BNXT_PHYLPBK_TEST_IDX) {
5551 strcpy(str, "Phy loopback test (offline)");
5552 } else if (i == BNXT_EXTLPBK_TEST_IDX) {
5553 strcpy(str, "Ext loopback test (offline)");
5554 } else if (i == BNXT_IRQ_TEST_IDX) {
5555 strcpy(str, "Interrupt_test (offline)");
5556 } else {
5557 snprintf(str, ETH_GSTRING_LEN, "%s test (%s)",
5558 fw_str, test_info->offline_mask & (1 << i) ?
5559 "offline" : "online");
5560 }
5561 }
5562
5563 ethtool_init_exit:
5564 hwrm_req_drop(bp, req);
5565 }
5566
bnxt_get_eth_phy_stats(struct net_device * dev,struct ethtool_eth_phy_stats * phy_stats)5567 static void bnxt_get_eth_phy_stats(struct net_device *dev,
5568 struct ethtool_eth_phy_stats *phy_stats)
5569 {
5570 struct bnxt *bp = netdev_priv(dev);
5571 u64 *rx;
5572
5573 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5574 return;
5575
5576 rx = bp->rx_port_stats_ext.sw_stats;
5577 phy_stats->SymbolErrorDuringCarrier =
5578 *(rx + BNXT_RX_STATS_EXT_OFFSET(rx_pcs_symbol_err));
5579 }
5580
bnxt_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)5581 static void bnxt_get_eth_mac_stats(struct net_device *dev,
5582 struct ethtool_eth_mac_stats *mac_stats)
5583 {
5584 struct bnxt *bp = netdev_priv(dev);
5585 u64 *rx, *tx;
5586
5587 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5588 return;
5589
5590 rx = bp->port_stats.sw_stats;
5591 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
5592
5593 mac_stats->FramesReceivedOK =
5594 BNXT_GET_RX_PORT_STATS64(rx, rx_good_frames);
5595 mac_stats->FramesTransmittedOK =
5596 BNXT_GET_TX_PORT_STATS64(tx, tx_good_frames);
5597 mac_stats->FrameCheckSequenceErrors =
5598 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
5599 mac_stats->AlignmentErrors =
5600 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
5601 mac_stats->OutOfRangeLengthField =
5602 BNXT_GET_RX_PORT_STATS64(rx, rx_oor_len_frames);
5603 }
5604
bnxt_get_eth_ctrl_stats(struct net_device * dev,struct ethtool_eth_ctrl_stats * ctrl_stats)5605 static void bnxt_get_eth_ctrl_stats(struct net_device *dev,
5606 struct ethtool_eth_ctrl_stats *ctrl_stats)
5607 {
5608 struct bnxt *bp = netdev_priv(dev);
5609 u64 *rx;
5610
5611 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5612 return;
5613
5614 rx = bp->port_stats.sw_stats;
5615 ctrl_stats->MACControlFramesReceived =
5616 BNXT_GET_RX_PORT_STATS64(rx, rx_ctrl_frames);
5617 }
5618
5619 static const struct ethtool_rmon_hist_range bnxt_rmon_ranges[] = {
5620 { 0, 64 },
5621 { 65, 127 },
5622 { 128, 255 },
5623 { 256, 511 },
5624 { 512, 1023 },
5625 { 1024, 1518 },
5626 { 1519, 2047 },
5627 { 2048, 4095 },
5628 { 4096, 9216 },
5629 { 9217, 16383 },
5630 {}
5631 };
5632
bnxt_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)5633 static void bnxt_get_rmon_stats(struct net_device *dev,
5634 struct ethtool_rmon_stats *rmon_stats,
5635 const struct ethtool_rmon_hist_range **ranges)
5636 {
5637 struct bnxt *bp = netdev_priv(dev);
5638 u64 *rx, *tx;
5639
5640 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS))
5641 return;
5642
5643 rx = bp->port_stats.sw_stats;
5644 tx = bp->port_stats.sw_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
5645
5646 rmon_stats->jabbers =
5647 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
5648 rmon_stats->oversize_pkts =
5649 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames);
5650 rmon_stats->undersize_pkts =
5651 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames);
5652
5653 rmon_stats->hist[0] = BNXT_GET_RX_PORT_STATS64(rx, rx_64b_frames);
5654 rmon_stats->hist[1] = BNXT_GET_RX_PORT_STATS64(rx, rx_65b_127b_frames);
5655 rmon_stats->hist[2] = BNXT_GET_RX_PORT_STATS64(rx, rx_128b_255b_frames);
5656 rmon_stats->hist[3] = BNXT_GET_RX_PORT_STATS64(rx, rx_256b_511b_frames);
5657 rmon_stats->hist[4] =
5658 BNXT_GET_RX_PORT_STATS64(rx, rx_512b_1023b_frames);
5659 rmon_stats->hist[5] =
5660 BNXT_GET_RX_PORT_STATS64(rx, rx_1024b_1518b_frames);
5661 rmon_stats->hist[6] =
5662 BNXT_GET_RX_PORT_STATS64(rx, rx_1519b_2047b_frames);
5663 rmon_stats->hist[7] =
5664 BNXT_GET_RX_PORT_STATS64(rx, rx_2048b_4095b_frames);
5665 rmon_stats->hist[8] =
5666 BNXT_GET_RX_PORT_STATS64(rx, rx_4096b_9216b_frames);
5667 rmon_stats->hist[9] =
5668 BNXT_GET_RX_PORT_STATS64(rx, rx_9217b_16383b_frames);
5669
5670 rmon_stats->hist_tx[0] =
5671 BNXT_GET_TX_PORT_STATS64(tx, tx_64b_frames);
5672 rmon_stats->hist_tx[1] =
5673 BNXT_GET_TX_PORT_STATS64(tx, tx_65b_127b_frames);
5674 rmon_stats->hist_tx[2] =
5675 BNXT_GET_TX_PORT_STATS64(tx, tx_128b_255b_frames);
5676 rmon_stats->hist_tx[3] =
5677 BNXT_GET_TX_PORT_STATS64(tx, tx_256b_511b_frames);
5678 rmon_stats->hist_tx[4] =
5679 BNXT_GET_TX_PORT_STATS64(tx, tx_512b_1023b_frames);
5680 rmon_stats->hist_tx[5] =
5681 BNXT_GET_TX_PORT_STATS64(tx, tx_1024b_1518b_frames);
5682 rmon_stats->hist_tx[6] =
5683 BNXT_GET_TX_PORT_STATS64(tx, tx_1519b_2047b_frames);
5684 rmon_stats->hist_tx[7] =
5685 BNXT_GET_TX_PORT_STATS64(tx, tx_2048b_4095b_frames);
5686 rmon_stats->hist_tx[8] =
5687 BNXT_GET_TX_PORT_STATS64(tx, tx_4096b_9216b_frames);
5688 rmon_stats->hist_tx[9] =
5689 BNXT_GET_TX_PORT_STATS64(tx, tx_9217b_16383b_frames);
5690
5691 *ranges = bnxt_rmon_ranges;
5692 }
5693
bnxt_get_ptp_stats(struct net_device * dev,struct ethtool_ts_stats * ts_stats)5694 static void bnxt_get_ptp_stats(struct net_device *dev,
5695 struct ethtool_ts_stats *ts_stats)
5696 {
5697 struct bnxt *bp = netdev_priv(dev);
5698 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5699
5700 if (ptp) {
5701 ts_stats->pkts = ptp->stats.ts_pkts;
5702 ts_stats->lost = ptp->stats.ts_lost;
5703 ts_stats->err = atomic64_read(&ptp->stats.ts_err);
5704 }
5705 }
5706
bnxt_get_link_ext_stats(struct net_device * dev,struct ethtool_link_ext_stats * stats)5707 static void bnxt_get_link_ext_stats(struct net_device *dev,
5708 struct ethtool_link_ext_stats *stats)
5709 {
5710 struct bnxt *bp = netdev_priv(dev);
5711 u64 *rx;
5712
5713 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
5714 return;
5715
5716 rx = bp->rx_port_stats_ext.sw_stats;
5717 stats->link_down_events =
5718 *(rx + BNXT_RX_STATS_EXT_OFFSET(link_down_events));
5719 }
5720
bnxt_ethtool_free(struct bnxt * bp)5721 void bnxt_ethtool_free(struct bnxt *bp)
5722 {
5723 kfree(bp->test_info);
5724 bp->test_info = NULL;
5725 }
5726
5727 const struct ethtool_ops bnxt_ethtool_ops = {
5728 .cap_link_lanes_supported = 1,
5729 .rxfh_per_ctx_key = 1,
5730 .rxfh_max_num_contexts = BNXT_MAX_ETH_RSS_CTX + 1,
5731 .rxfh_indir_space = BNXT_MAX_RSS_TABLE_ENTRIES_P5,
5732 .rxfh_priv_size = sizeof(struct bnxt_rss_ctx),
5733 .op_needs_rtnl = ETHTOOL_OP_NEEDS_RTNL_SCHANNELS |
5734 ETHTOOL_OP_NEEDS_RTNL_SRINGPARAM |
5735 ETHTOOL_OP_NEEDS_RTNL_SCOALESCE |
5736 ETHTOOL_OP_NEEDS_RTNL_RSS,
5737 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5738 ETHTOOL_COALESCE_MAX_FRAMES |
5739 ETHTOOL_COALESCE_USECS_IRQ |
5740 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
5741 ETHTOOL_COALESCE_STATS_BLOCK_USECS |
5742 ETHTOOL_COALESCE_USE_ADAPTIVE_RX |
5743 ETHTOOL_COALESCE_USE_CQE,
5744 .supported_ring_params = ETHTOOL_RING_USE_TCP_DATA_SPLIT |
5745 ETHTOOL_RING_USE_HDS_THRS,
5746 .get_link_ksettings = bnxt_get_link_ksettings,
5747 .set_link_ksettings = bnxt_set_link_ksettings,
5748 .get_fec_stats = bnxt_get_fec_stats,
5749 .get_fecparam = bnxt_get_fecparam,
5750 .set_fecparam = bnxt_set_fecparam,
5751 .get_pause_stats = bnxt_get_pause_stats,
5752 .get_pauseparam = bnxt_get_pauseparam,
5753 .set_pauseparam = bnxt_set_pauseparam,
5754 .get_drvinfo = bnxt_get_drvinfo,
5755 .get_regs_len = bnxt_get_regs_len,
5756 .get_regs = bnxt_get_regs,
5757 .get_wol = bnxt_get_wol,
5758 .set_wol = bnxt_set_wol,
5759 .get_coalesce = bnxt_get_coalesce,
5760 .set_coalesce = bnxt_set_coalesce,
5761 .get_msglevel = bnxt_get_msglevel,
5762 .set_msglevel = bnxt_set_msglevel,
5763 .get_sset_count = bnxt_get_sset_count,
5764 .get_strings = bnxt_get_strings,
5765 .get_ethtool_stats = bnxt_get_ethtool_stats,
5766 .set_ringparam = bnxt_set_ringparam,
5767 .get_ringparam = bnxt_get_ringparam,
5768 .get_channels = bnxt_get_channels,
5769 .set_channels = bnxt_set_channels,
5770 .get_rxnfc = bnxt_get_rxnfc,
5771 .set_rxnfc = bnxt_set_rxnfc,
5772 .get_rx_ring_count = bnxt_get_rx_ring_count,
5773 .get_rxfh_indir_size = bnxt_get_rxfh_indir_size,
5774 .get_rxfh_key_size = bnxt_get_rxfh_key_size,
5775 .get_rxfh = bnxt_get_rxfh,
5776 .set_rxfh = bnxt_set_rxfh,
5777 .get_rxfh_fields = bnxt_get_rxfh_fields,
5778 .set_rxfh_fields = bnxt_set_rxfh_fields,
5779 .create_rxfh_context = bnxt_create_rxfh_context,
5780 .modify_rxfh_context = bnxt_modify_rxfh_context,
5781 .remove_rxfh_context = bnxt_remove_rxfh_context,
5782 .flash_device = bnxt_flash_device,
5783 .get_eeprom_len = bnxt_get_eeprom_len,
5784 .get_eeprom = bnxt_get_eeprom,
5785 .set_eeprom = bnxt_set_eeprom,
5786 .get_link = bnxt_get_link,
5787 .get_link_ext_state = bnxt_get_link_ext_state,
5788 .get_link_ext_stats = bnxt_get_link_ext_stats,
5789 .get_eee = bnxt_get_eee,
5790 .set_eee = bnxt_set_eee,
5791 .get_tunable = bnxt_get_tunable,
5792 .set_tunable = bnxt_set_tunable,
5793 .get_module_info = bnxt_get_module_info,
5794 .get_module_eeprom = bnxt_get_module_eeprom,
5795 .get_module_eeprom_by_page = bnxt_get_module_eeprom_by_page,
5796 .set_module_eeprom_by_page = bnxt_set_module_eeprom_by_page,
5797 .nway_reset = bnxt_nway_reset,
5798 .set_phys_id = bnxt_set_phys_id,
5799 .self_test = bnxt_self_test,
5800 .get_ts_info = bnxt_get_ts_info,
5801 .reset = bnxt_reset,
5802 .set_dump = bnxt_set_dump,
5803 .get_dump_flag = bnxt_get_dump_flag,
5804 .get_dump_data = bnxt_get_dump_data,
5805 .get_eth_phy_stats = bnxt_get_eth_phy_stats,
5806 .get_eth_mac_stats = bnxt_get_eth_mac_stats,
5807 .get_eth_ctrl_stats = bnxt_get_eth_ctrl_stats,
5808 .get_rmon_stats = bnxt_get_rmon_stats,
5809 .get_ts_stats = bnxt_get_ptp_stats,
5810 };
5811