1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio codec driver for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 #include "generic.h" 28 29 #include "ca0132_regs.h" 30 31 /* Enable this to see controls for tuning purpose. */ 32 #define ENABLE_TUNING_CONTROLS 33 34 #ifdef ENABLE_TUNING_CONTROLS 35 #include <sound/tlv.h> 36 #endif 37 38 #define FLOAT_ZERO 0x00000000 39 #define FLOAT_ONE 0x3f800000 40 #define FLOAT_TWO 0x40000000 41 #define FLOAT_THREE 0x40400000 42 #define FLOAT_FIVE 0x40a00000 43 #define FLOAT_SIX 0x40c00000 44 #define FLOAT_EIGHT 0x41000000 45 #define FLOAT_MINUS_5 0xc0a00000 46 47 #define UNSOL_TAG_DSP 0x16 48 49 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 50 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 51 52 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 53 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 54 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 55 56 #define MASTERCONTROL 0x80 57 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 58 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 59 60 #define WIDGET_CHIP_CTRL 0x15 61 #define WIDGET_DSP_CTRL 0x16 62 63 #define MEM_CONNID_MICIN1 3 64 #define MEM_CONNID_MICIN2 5 65 #define MEM_CONNID_MICOUT1 12 66 #define MEM_CONNID_MICOUT2 14 67 #define MEM_CONNID_WUH 10 68 #define MEM_CONNID_DSP 16 69 #define MEM_CONNID_DMIC 100 70 71 #define SCP_SET 0 72 #define SCP_GET 1 73 74 #define EFX_FILE "ctefx.bin" 75 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 76 #define R3DI_EFX_FILE "ctefx-r3di.bin" 77 78 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 79 MODULE_FIRMWARE(EFX_FILE); 80 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 81 MODULE_FIRMWARE(R3DI_EFX_FILE); 82 #endif 83 84 static const char *const dirstr[2] = { "Playback", "Capture" }; 85 86 #define NUM_OF_OUTPUTS 2 87 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 88 enum { 89 SPEAKER_OUT, 90 HEADPHONE_OUT, 91 }; 92 93 enum { 94 DIGITAL_MIC, 95 LINE_MIC_IN 96 }; 97 98 /* Strings for Input Source Enum Control */ 99 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 100 #define IN_SRC_NUM_OF_INPUTS 3 101 enum { 102 REAR_MIC, 103 REAR_LINE_IN, 104 FRONT_MIC, 105 }; 106 107 enum { 108 #define VNODE_START_NID 0x80 109 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 110 VNID_MIC, 111 VNID_HP_SEL, 112 VNID_AMIC1_SEL, 113 VNID_HP_ASEL, 114 VNID_AMIC1_ASEL, 115 VNODE_END_NID, 116 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 117 118 #define EFFECT_START_NID 0x90 119 #define OUT_EFFECT_START_NID EFFECT_START_NID 120 SURROUND = OUT_EFFECT_START_NID, 121 CRYSTALIZER, 122 DIALOG_PLUS, 123 SMART_VOLUME, 124 X_BASS, 125 EQUALIZER, 126 OUT_EFFECT_END_NID, 127 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 128 129 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 130 ECHO_CANCELLATION = IN_EFFECT_START_NID, 131 VOICE_FOCUS, 132 MIC_SVM, 133 NOISE_REDUCTION, 134 IN_EFFECT_END_NID, 135 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 136 137 VOICEFX = IN_EFFECT_END_NID, 138 PLAY_ENHANCEMENT, 139 CRYSTAL_VOICE, 140 EFFECT_END_NID, 141 OUTPUT_SOURCE_ENUM, 142 INPUT_SOURCE_ENUM, 143 XBASS_XOVER, 144 EQ_PRESET_ENUM, 145 SMART_VOLUME_ENUM, 146 MIC_BOOST_ENUM, 147 AE5_HEADPHONE_GAIN_ENUM, 148 AE5_SOUND_FILTER_ENUM, 149 ZXR_HEADPHONE_GAIN, 150 SPEAKER_CHANNEL_CFG_ENUM, 151 SPEAKER_FULL_RANGE_FRONT, 152 SPEAKER_FULL_RANGE_REAR, 153 BASS_REDIRECTION, 154 BASS_REDIRECTION_XOVER, 155 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 156 }; 157 158 /* Effects values size*/ 159 #define EFFECT_VALS_MAX_COUNT 12 160 161 /* 162 * Default values for the effect slider controls, they are in order of their 163 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 164 * X-bass. 165 */ 166 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 167 /* Amount of effect level sliders for ca0132_alt controls. */ 168 #define EFFECT_LEVEL_SLIDERS 5 169 170 /* Latency introduced by DSP blocks in milliseconds. */ 171 #define DSP_CAPTURE_INIT_LATENCY 0 172 #define DSP_CRYSTAL_VOICE_LATENCY 124 173 #define DSP_PLAYBACK_INIT_LATENCY 13 174 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 175 #define DSP_SPEAKER_OUT_LATENCY 7 176 177 struct ct_effect { 178 const char *name; 179 hda_nid_t nid; 180 int mid; /*effect module ID*/ 181 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 182 int direct; /* 0:output; 1:input*/ 183 int params; /* number of default non-on/off params */ 184 /*effect default values, 1st is on/off. */ 185 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 186 }; 187 188 #define EFX_DIR_OUT 0 189 #define EFX_DIR_IN 1 190 191 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 192 { .name = "Surround", 193 .nid = SURROUND, 194 .mid = 0x96, 195 .reqs = {0, 1}, 196 .direct = EFX_DIR_OUT, 197 .params = 1, 198 .def_vals = {0x3F800000, 0x3F2B851F} 199 }, 200 { .name = "Crystalizer", 201 .nid = CRYSTALIZER, 202 .mid = 0x96, 203 .reqs = {7, 8}, 204 .direct = EFX_DIR_OUT, 205 .params = 1, 206 .def_vals = {0x3F800000, 0x3F266666} 207 }, 208 { .name = "Dialog Plus", 209 .nid = DIALOG_PLUS, 210 .mid = 0x96, 211 .reqs = {2, 3}, 212 .direct = EFX_DIR_OUT, 213 .params = 1, 214 .def_vals = {0x00000000, 0x3F000000} 215 }, 216 { .name = "Smart Volume", 217 .nid = SMART_VOLUME, 218 .mid = 0x96, 219 .reqs = {4, 5, 6}, 220 .direct = EFX_DIR_OUT, 221 .params = 2, 222 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 223 }, 224 { .name = "X-Bass", 225 .nid = X_BASS, 226 .mid = 0x96, 227 .reqs = {24, 23, 25}, 228 .direct = EFX_DIR_OUT, 229 .params = 2, 230 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 231 }, 232 { .name = "Equalizer", 233 .nid = EQUALIZER, 234 .mid = 0x96, 235 .reqs = {9, 10, 11, 12, 13, 14, 236 15, 16, 17, 18, 19, 20}, 237 .direct = EFX_DIR_OUT, 238 .params = 11, 239 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000, 241 0x00000000, 0x00000000, 0x00000000, 0x00000000} 242 }, 243 { .name = "Echo Cancellation", 244 .nid = ECHO_CANCELLATION, 245 .mid = 0x95, 246 .reqs = {0, 1, 2, 3}, 247 .direct = EFX_DIR_IN, 248 .params = 3, 249 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 250 }, 251 { .name = "Voice Focus", 252 .nid = VOICE_FOCUS, 253 .mid = 0x95, 254 .reqs = {6, 7, 8, 9}, 255 .direct = EFX_DIR_IN, 256 .params = 3, 257 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 258 }, 259 { .name = "Mic SVM", 260 .nid = MIC_SVM, 261 .mid = 0x95, 262 .reqs = {44, 45}, 263 .direct = EFX_DIR_IN, 264 .params = 1, 265 .def_vals = {0x00000000, 0x3F3D70A4} 266 }, 267 { .name = "Noise Reduction", 268 .nid = NOISE_REDUCTION, 269 .mid = 0x95, 270 .reqs = {4, 5}, 271 .direct = EFX_DIR_IN, 272 .params = 1, 273 .def_vals = {0x3F800000, 0x3F000000} 274 }, 275 { .name = "VoiceFX", 276 .nid = VOICEFX, 277 .mid = 0x95, 278 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 279 .direct = EFX_DIR_IN, 280 .params = 8, 281 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 282 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 283 0x00000000} 284 } 285 }; 286 287 /* Tuning controls */ 288 #ifdef ENABLE_TUNING_CONTROLS 289 290 enum { 291 #define TUNING_CTL_START_NID 0xC0 292 WEDGE_ANGLE = TUNING_CTL_START_NID, 293 SVM_LEVEL, 294 EQUALIZER_BAND_0, 295 EQUALIZER_BAND_1, 296 EQUALIZER_BAND_2, 297 EQUALIZER_BAND_3, 298 EQUALIZER_BAND_4, 299 EQUALIZER_BAND_5, 300 EQUALIZER_BAND_6, 301 EQUALIZER_BAND_7, 302 EQUALIZER_BAND_8, 303 EQUALIZER_BAND_9, 304 TUNING_CTL_END_NID 305 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 306 }; 307 308 struct ct_tuning_ctl { 309 const char *name; 310 hda_nid_t parent_nid; 311 hda_nid_t nid; 312 int mid; /*effect module ID*/ 313 int req; /*effect module request*/ 314 int direct; /* 0:output; 1:input*/ 315 unsigned int def_val;/*effect default values*/ 316 }; 317 318 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 319 { .name = "Wedge Angle", 320 .parent_nid = VOICE_FOCUS, 321 .nid = WEDGE_ANGLE, 322 .mid = 0x95, 323 .req = 8, 324 .direct = EFX_DIR_IN, 325 .def_val = 0x41F00000 326 }, 327 { .name = "SVM Level", 328 .parent_nid = MIC_SVM, 329 .nid = SVM_LEVEL, 330 .mid = 0x95, 331 .req = 45, 332 .direct = EFX_DIR_IN, 333 .def_val = 0x3F3D70A4 334 }, 335 { .name = "EQ Band0", 336 .parent_nid = EQUALIZER, 337 .nid = EQUALIZER_BAND_0, 338 .mid = 0x96, 339 .req = 11, 340 .direct = EFX_DIR_OUT, 341 .def_val = 0x00000000 342 }, 343 { .name = "EQ Band1", 344 .parent_nid = EQUALIZER, 345 .nid = EQUALIZER_BAND_1, 346 .mid = 0x96, 347 .req = 12, 348 .direct = EFX_DIR_OUT, 349 .def_val = 0x00000000 350 }, 351 { .name = "EQ Band2", 352 .parent_nid = EQUALIZER, 353 .nid = EQUALIZER_BAND_2, 354 .mid = 0x96, 355 .req = 13, 356 .direct = EFX_DIR_OUT, 357 .def_val = 0x00000000 358 }, 359 { .name = "EQ Band3", 360 .parent_nid = EQUALIZER, 361 .nid = EQUALIZER_BAND_3, 362 .mid = 0x96, 363 .req = 14, 364 .direct = EFX_DIR_OUT, 365 .def_val = 0x00000000 366 }, 367 { .name = "EQ Band4", 368 .parent_nid = EQUALIZER, 369 .nid = EQUALIZER_BAND_4, 370 .mid = 0x96, 371 .req = 15, 372 .direct = EFX_DIR_OUT, 373 .def_val = 0x00000000 374 }, 375 { .name = "EQ Band5", 376 .parent_nid = EQUALIZER, 377 .nid = EQUALIZER_BAND_5, 378 .mid = 0x96, 379 .req = 16, 380 .direct = EFX_DIR_OUT, 381 .def_val = 0x00000000 382 }, 383 { .name = "EQ Band6", 384 .parent_nid = EQUALIZER, 385 .nid = EQUALIZER_BAND_6, 386 .mid = 0x96, 387 .req = 17, 388 .direct = EFX_DIR_OUT, 389 .def_val = 0x00000000 390 }, 391 { .name = "EQ Band7", 392 .parent_nid = EQUALIZER, 393 .nid = EQUALIZER_BAND_7, 394 .mid = 0x96, 395 .req = 18, 396 .direct = EFX_DIR_OUT, 397 .def_val = 0x00000000 398 }, 399 { .name = "EQ Band8", 400 .parent_nid = EQUALIZER, 401 .nid = EQUALIZER_BAND_8, 402 .mid = 0x96, 403 .req = 19, 404 .direct = EFX_DIR_OUT, 405 .def_val = 0x00000000 406 }, 407 { .name = "EQ Band9", 408 .parent_nid = EQUALIZER, 409 .nid = EQUALIZER_BAND_9, 410 .mid = 0x96, 411 .req = 20, 412 .direct = EFX_DIR_OUT, 413 .def_val = 0x00000000 414 } 415 }; 416 #endif 417 418 /* Voice FX Presets */ 419 #define VOICEFX_MAX_PARAM_COUNT 9 420 421 struct ct_voicefx { 422 const char *name; 423 hda_nid_t nid; 424 int mid; 425 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 426 }; 427 428 struct ct_voicefx_preset { 429 const char *name; /*preset name*/ 430 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 431 }; 432 433 static const struct ct_voicefx ca0132_voicefx = { 434 .name = "VoiceFX Capture Switch", 435 .nid = VOICEFX, 436 .mid = 0x95, 437 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 438 }; 439 440 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 441 { .name = "Neutral", 442 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 443 0x44FA0000, 0x3F800000, 0x3F800000, 444 0x3F800000, 0x00000000, 0x00000000 } 445 }, 446 { .name = "Female2Male", 447 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 448 0x44FA0000, 0x3F19999A, 0x3F866666, 449 0x3F800000, 0x00000000, 0x00000000 } 450 }, 451 { .name = "Male2Female", 452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 453 0x450AC000, 0x4017AE14, 0x3F6B851F, 454 0x3F800000, 0x00000000, 0x00000000 } 455 }, 456 { .name = "ScrappyKid", 457 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 458 0x44FA0000, 0x40400000, 0x3F28F5C3, 459 0x3F800000, 0x00000000, 0x00000000 } 460 }, 461 { .name = "Elderly", 462 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 463 0x44E10000, 0x3FB33333, 0x3FB9999A, 464 0x3F800000, 0x3E3A2E43, 0x00000000 } 465 }, 466 { .name = "Orc", 467 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 468 0x45098000, 0x3F266666, 0x3FC00000, 469 0x3F800000, 0x00000000, 0x00000000 } 470 }, 471 { .name = "Elf", 472 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 473 0x45193000, 0x3F8E147B, 0x3F75C28F, 474 0x3F800000, 0x00000000, 0x00000000 } 475 }, 476 { .name = "Dwarf", 477 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 478 0x45007000, 0x3F451EB8, 0x3F7851EC, 479 0x3F800000, 0x00000000, 0x00000000 } 480 }, 481 { .name = "AlienBrute", 482 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 483 0x451F6000, 0x3F266666, 0x3FA7D945, 484 0x3F800000, 0x3CF5C28F, 0x00000000 } 485 }, 486 { .name = "Robot", 487 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 488 0x44FA0000, 0x3FB2718B, 0x3F800000, 489 0xBC07010E, 0x00000000, 0x00000000 } 490 }, 491 { .name = "Marine", 492 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 493 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 494 0x3F0A3D71, 0x00000000, 0x00000000 } 495 }, 496 { .name = "Emo", 497 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 498 0x44FA0000, 0x3F800000, 0x3F800000, 499 0x3E4CCCCD, 0x00000000, 0x00000000 } 500 }, 501 { .name = "DeepVoice", 502 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 503 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 504 0x3F800000, 0x00000000, 0x00000000 } 505 }, 506 { .name = "Munchkin", 507 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 508 0x44FA0000, 0x3F800000, 0x3F1A043C, 509 0x3F800000, 0x00000000, 0x00000000 } 510 } 511 }; 512 513 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 514 515 #define EQ_PRESET_MAX_PARAM_COUNT 11 516 517 struct ct_eq { 518 const char *name; 519 hda_nid_t nid; 520 int mid; 521 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 522 }; 523 524 struct ct_eq_preset { 525 const char *name; /*preset name*/ 526 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 527 }; 528 529 static const struct ct_eq ca0132_alt_eq_enum = { 530 .name = "FX: Equalizer Preset Switch", 531 .nid = EQ_PRESET_ENUM, 532 .mid = 0x96, 533 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 534 }; 535 536 537 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 538 { .name = "Flat", 539 .vals = { 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000, 0x00000000, 542 0x00000000, 0x00000000 } 543 }, 544 { .name = "Acoustic", 545 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 546 0x40000000, 0x00000000, 0x00000000, 547 0x00000000, 0x00000000, 0x40000000, 548 0x40000000, 0x40000000 } 549 }, 550 { .name = "Classical", 551 .vals = { 0x00000000, 0x00000000, 0x40C00000, 552 0x40C00000, 0x40466666, 0x00000000, 553 0x00000000, 0x00000000, 0x00000000, 554 0x40466666, 0x40466666 } 555 }, 556 { .name = "Country", 557 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 558 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 559 0x00000000, 0x00000000, 0x40000000, 560 0x40466666, 0x40800000 } 561 }, 562 { .name = "Dance", 563 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 564 0x40466666, 0x40866666, 0xBF99999A, 565 0xBF99999A, 0x00000000, 0x00000000, 566 0x40800000, 0x40800000 } 567 }, 568 { .name = "Jazz", 569 .vals = { 0x00000000, 0x00000000, 0x00000000, 570 0x3F8CCCCD, 0x40800000, 0x40800000, 571 0x40800000, 0x00000000, 0x3F8CCCCD, 572 0x40466666, 0x40466666 } 573 }, 574 { .name = "New Age", 575 .vals = { 0x00000000, 0x00000000, 0x40000000, 576 0x40000000, 0x00000000, 0x00000000, 577 0x00000000, 0x3F8CCCCD, 0x40000000, 578 0x40000000, 0x40000000 } 579 }, 580 { .name = "Pop", 581 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 582 0x40000000, 0x40000000, 0x00000000, 583 0xBF99999A, 0xBF99999A, 0x00000000, 584 0x40466666, 0x40C00000 } 585 }, 586 { .name = "Rock", 587 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 588 0x3F8CCCCD, 0x40000000, 0xBF99999A, 589 0xBF99999A, 0x00000000, 0x00000000, 590 0x40800000, 0x40800000 } 591 }, 592 { .name = "Vocal", 593 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 594 0xBF99999A, 0x00000000, 0x40466666, 595 0x40800000, 0x40466666, 0x00000000, 596 0x00000000, 0x3F8CCCCD } 597 } 598 }; 599 600 /* 601 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 602 * set as not being full range, and bass redirection is enabled, all 603 * frequencies below the crossover frequency are redirected to the LFE 604 * channel. If the surround configuration has no LFE channel, this can't be 605 * enabled. X-Bass must be disabled when using these. 606 */ 607 enum speaker_range_reqs { 608 SPEAKER_BASS_REDIRECT = 0x15, 609 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 610 /* Between 0x16-0x1a are the X-Bass reqs. */ 611 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 612 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 613 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 614 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 615 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 616 }; 617 618 /* 619 * Definitions for the DSP req's to handle speaker tuning. These all belong to 620 * module ID 0x96, the output effects module. 621 */ 622 enum speaker_tuning_reqs { 623 /* 624 * Currently, this value is always set to 0.0f. However, on Windows, 625 * when selecting certain headphone profiles on the new Sound Blaster 626 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 627 * sent. This gets the speaker EQ address area, which is then used to 628 * send over (presumably) an equalizer profile for the specific 629 * headphone setup. It is sent using the same method the DSP 630 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 631 * file exists in linux firmware tree but goes unused. It would also 632 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 633 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 634 * set to 1.0f. 635 */ 636 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 637 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 638 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 639 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 640 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 641 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 642 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 643 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 644 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 645 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 646 /* 647 * Inversion is used when setting headphone virtualization to line 648 * out. Not sure why this is, but it's the only place it's ever used. 649 */ 650 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 651 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 652 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 653 SPEAKER_TUNING_LFE_INVERT = 0x2c, 654 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 655 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 656 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 657 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 658 /* Delay is used when setting surround speaker distance in Windows. */ 659 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 660 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 661 SPEAKER_TUNING_CENTER_DELAY = 0x33, 662 SPEAKER_TUNING_LFE_DELAY = 0x34, 663 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 664 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 665 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 666 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 667 /* Of these two, only mute seems to ever be used. */ 668 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 669 SPEAKER_TUNING_MUTE = 0x3a, 670 }; 671 672 /* Surround output channel count configuration structures. */ 673 #define SPEAKER_CHANNEL_CFG_COUNT 5 674 enum { 675 SPEAKER_CHANNELS_2_0, 676 SPEAKER_CHANNELS_2_1, 677 SPEAKER_CHANNELS_4_0, 678 SPEAKER_CHANNELS_4_1, 679 SPEAKER_CHANNELS_5_1, 680 }; 681 682 struct ca0132_alt_speaker_channel_cfg { 683 const char *name; 684 unsigned int val; 685 }; 686 687 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 688 { .name = "2.0", 689 .val = FLOAT_ONE 690 }, 691 { .name = "2.1", 692 .val = FLOAT_TWO 693 }, 694 { .name = "4.0", 695 .val = FLOAT_FIVE 696 }, 697 { .name = "4.1", 698 .val = FLOAT_SIX 699 }, 700 { .name = "5.1", 701 .val = FLOAT_EIGHT 702 } 703 }; 704 705 /* 706 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 707 * and I don't know what the third req is, but it's always zero. I assume it's 708 * some sort of update or set command to tell the DSP there's new volume info. 709 */ 710 #define DSP_VOL_OUT 0 711 #define DSP_VOL_IN 1 712 713 struct ct_dsp_volume_ctl { 714 hda_nid_t vnid; 715 int mid; /* module ID*/ 716 unsigned int reqs[3]; /* scp req ID */ 717 }; 718 719 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 720 { .vnid = VNID_SPK, 721 .mid = 0x32, 722 .reqs = {3, 4, 2} 723 }, 724 { .vnid = VNID_MIC, 725 .mid = 0x37, 726 .reqs = {2, 3, 1} 727 } 728 }; 729 730 /* Values for ca0113_mmio_command_set for selecting output. */ 731 #define AE_CA0113_OUT_SET_COMMANDS 6 732 struct ae_ca0113_output_set { 733 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 735 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 736 }; 737 738 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 739 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 740 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 741 /* Speakers. */ 742 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 743 /* Headphones. */ 744 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 745 }; 746 747 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 748 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 749 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 750 /* Speakers. */ 751 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 752 /* Headphones. */ 753 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 754 }; 755 756 /* ae5 ca0113 command sequences to set headphone gain levels. */ 757 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 758 struct ae5_headphone_gain_set { 759 const char *name; 760 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 761 }; 762 763 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 764 { .name = "Low (16-31", 765 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 766 }, 767 { .name = "Medium (32-149", 768 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 769 }, 770 { .name = "High (150-600", 771 .vals = { 0xff, 0xff, 0xff, 0x7f } 772 } 773 }; 774 775 struct ae5_filter_set { 776 const char *name; 777 unsigned int val; 778 }; 779 780 static const struct ae5_filter_set ae5_filter_presets[] = { 781 { .name = "Slow Roll Off", 782 .val = 0xa0 783 }, 784 { .name = "Minimum Phase", 785 .val = 0xc0 786 }, 787 { .name = "Fast Roll Off", 788 .val = 0x80 789 } 790 }; 791 792 /* 793 * Data structures for storing audio router remapping data. These are used to 794 * remap a currently active streams ports. 795 */ 796 struct chipio_stream_remap_data { 797 unsigned int stream_id; 798 unsigned int count; 799 800 unsigned int offset[16]; 801 unsigned int value[16]; 802 }; 803 804 static const struct chipio_stream_remap_data stream_remap_data[] = { 805 { .stream_id = 0x14, 806 .count = 0x04, 807 .offset = { 0x00, 0x04, 0x08, 0x0c }, 808 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, 809 }, 810 { .stream_id = 0x0c, 811 .count = 0x0c, 812 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 813 0x20, 0x24, 0x28, 0x2c }, 814 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 815 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 816 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, 817 }, 818 { .stream_id = 0x0c, 819 .count = 0x08, 820 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, 821 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 822 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, 823 } 824 }; 825 826 enum hda_cmd_vendor_io { 827 /* for DspIO node */ 828 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 829 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 830 831 VENDOR_DSPIO_STATUS = 0xF01, 832 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 833 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 834 VENDOR_DSPIO_DSP_INIT = 0x703, 835 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 836 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 837 838 /* for ChipIO node */ 839 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 840 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 841 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 842 VENDOR_CHIPIO_DATA_LOW = 0x300, 843 VENDOR_CHIPIO_DATA_HIGH = 0x400, 844 845 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 846 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 847 848 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 849 VENDOR_CHIPIO_STATUS = 0xF01, 850 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 851 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 852 853 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 854 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 855 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 856 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 857 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 858 859 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 860 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 861 862 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 863 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 864 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 865 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 866 VENDOR_CHIPIO_FLAG_SET = 0x70F, 867 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 868 VENDOR_CHIPIO_PARAM_SET = 0x710, 869 VENDOR_CHIPIO_PARAM_GET = 0xF10, 870 871 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 872 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 873 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 874 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 875 876 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 877 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 878 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 879 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 880 881 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 882 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 883 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 884 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 885 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 886 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 887 888 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 889 }; 890 891 /* 892 * Control flag IDs 893 */ 894 enum control_flag_id { 895 /* Connection manager stream setup is bypassed/enabled */ 896 CONTROL_FLAG_C_MGR = 0, 897 /* DSP DMA is bypassed/enabled */ 898 CONTROL_FLAG_DMA = 1, 899 /* 8051 'idle' mode is disabled/enabled */ 900 CONTROL_FLAG_IDLE_ENABLE = 2, 901 /* Tracker for the SPDIF-in path is bypassed/enabled */ 902 CONTROL_FLAG_TRACKER = 3, 903 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 904 CONTROL_FLAG_SPDIF2OUT = 4, 905 /* Digital Microphone is disabled/enabled */ 906 CONTROL_FLAG_DMIC = 5, 907 /* ADC_B rate is 48 kHz/96 kHz */ 908 CONTROL_FLAG_ADC_B_96KHZ = 6, 909 /* ADC_C rate is 48 kHz/96 kHz */ 910 CONTROL_FLAG_ADC_C_96KHZ = 7, 911 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 912 CONTROL_FLAG_DAC_96KHZ = 8, 913 /* DSP rate is 48 kHz/96 kHz */ 914 CONTROL_FLAG_DSP_96KHZ = 9, 915 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 916 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 917 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 918 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 919 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 920 CONTROL_FLAG_DECODE_LOOP = 12, 921 /* De-emphasis filter on DAC-1 disabled/enabled */ 922 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 923 /* De-emphasis filter on DAC-2 disabled/enabled */ 924 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 925 /* De-emphasis filter on DAC-3 disabled/enabled */ 926 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 927 /* High-pass filter on ADC_B disabled/enabled */ 928 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 929 /* High-pass filter on ADC_C disabled/enabled */ 930 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 931 /* Common mode on Port_A disabled/enabled */ 932 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 933 /* Common mode on Port_D disabled/enabled */ 934 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 935 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 936 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 937 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 938 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 939 /* ASI rate is 48kHz/96kHz */ 940 CONTROL_FLAG_ASI_96KHZ = 22, 941 /* DAC power settings able to control attached ports no/yes */ 942 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 943 /* Clock Stop OK reporting is disabled/enabled */ 944 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 945 /* Number of control flags */ 946 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 947 }; 948 949 /* 950 * Control parameter IDs 951 */ 952 enum control_param_id { 953 /* 0: None, 1: Mic1In*/ 954 CONTROL_PARAM_VIP_SOURCE = 1, 955 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 956 CONTROL_PARAM_SPDIF1_SOURCE = 2, 957 /* Port A output stage gain setting to use when 16 Ohm output 958 * impedance is selected*/ 959 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 960 /* Port D output stage gain setting to use when 16 Ohm output 961 * impedance is selected*/ 962 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 963 964 /* 965 * This control param name was found in the 8051 memory, and makes 966 * sense given the fact the AE-5 uses it and has the ASI flag set. 967 */ 968 CONTROL_PARAM_ASI = 23, 969 970 /* Stream Control */ 971 972 /* Select stream with the given ID */ 973 CONTROL_PARAM_STREAM_ID = 24, 974 /* Source connection point for the selected stream */ 975 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 976 /* Destination connection point for the selected stream */ 977 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 978 /* Number of audio channels in the selected stream */ 979 CONTROL_PARAM_STREAMS_CHANNELS = 27, 980 /*Enable control for the selected stream */ 981 CONTROL_PARAM_STREAM_CONTROL = 28, 982 983 /* Connection Point Control */ 984 985 /* Select connection point with the given ID */ 986 CONTROL_PARAM_CONN_POINT_ID = 29, 987 /* Connection point sample rate */ 988 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 989 990 /* Node Control */ 991 992 /* Select HDA node with the given ID */ 993 CONTROL_PARAM_NODE_ID = 31 994 }; 995 996 /* 997 * Dsp Io Status codes 998 */ 999 enum hda_vendor_status_dspio { 1000 /* Success */ 1001 VENDOR_STATUS_DSPIO_OK = 0x00, 1002 /* Busy, unable to accept new command, the host must retry */ 1003 VENDOR_STATUS_DSPIO_BUSY = 0x01, 1004 /* SCP command queue is full */ 1005 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 1006 /* SCP response queue is empty */ 1007 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 1008 }; 1009 1010 /* 1011 * Chip Io Status codes 1012 */ 1013 enum hda_vendor_status_chipio { 1014 /* Success */ 1015 VENDOR_STATUS_CHIPIO_OK = 0x00, 1016 /* Busy, unable to accept new command, the host must retry */ 1017 VENDOR_STATUS_CHIPIO_BUSY = 0x01 1018 }; 1019 1020 /* 1021 * CA0132 sample rate 1022 */ 1023 enum ca0132_sample_rate { 1024 SR_6_000 = 0x00, 1025 SR_8_000 = 0x01, 1026 SR_9_600 = 0x02, 1027 SR_11_025 = 0x03, 1028 SR_16_000 = 0x04, 1029 SR_22_050 = 0x05, 1030 SR_24_000 = 0x06, 1031 SR_32_000 = 0x07, 1032 SR_44_100 = 0x08, 1033 SR_48_000 = 0x09, 1034 SR_88_200 = 0x0A, 1035 SR_96_000 = 0x0B, 1036 SR_144_000 = 0x0C, 1037 SR_176_400 = 0x0D, 1038 SR_192_000 = 0x0E, 1039 SR_384_000 = 0x0F, 1040 1041 SR_COUNT = 0x10, 1042 1043 SR_RATE_UNKNOWN = 0x1F 1044 }; 1045 1046 enum dsp_download_state { 1047 DSP_DOWNLOAD_FAILED = -1, 1048 DSP_DOWNLOAD_INIT = 0, 1049 DSP_DOWNLOADING = 1, 1050 DSP_DOWNLOADED = 2 1051 }; 1052 1053 /* retrieve parameters from hda format */ 1054 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1055 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1056 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1057 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1058 1059 /* 1060 * CA0132 specific 1061 */ 1062 1063 struct ca0132_spec { 1064 struct hda_gen_spec gen; 1065 1066 const struct snd_kcontrol_new *mixers[5]; 1067 unsigned int num_mixers; 1068 const struct hda_verb *base_init_verbs; 1069 const struct hda_verb *base_exit_verbs; 1070 const struct hda_verb *chip_init_verbs; 1071 const struct hda_verb *desktop_init_verbs; 1072 struct hda_verb *spec_init_verbs; 1073 struct auto_pin_cfg autocfg; 1074 1075 /* Nodes configurations */ 1076 struct hda_multi_out multiout; 1077 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1078 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1079 unsigned int num_outputs; 1080 hda_nid_t input_pins[AUTO_PIN_LAST]; 1081 hda_nid_t adcs[AUTO_PIN_LAST]; 1082 hda_nid_t dig_out; 1083 hda_nid_t dig_in; 1084 unsigned int num_inputs; 1085 hda_nid_t shared_mic_nid; 1086 hda_nid_t shared_out_nid; 1087 hda_nid_t unsol_tag_hp; 1088 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1089 hda_nid_t unsol_tag_amic1; 1090 1091 /* chip access */ 1092 struct mutex chipio_mutex; /* chip access mutex */ 1093 u32 curr_chip_addx; 1094 1095 /* DSP download related */ 1096 enum dsp_download_state dsp_state; 1097 unsigned int dsp_stream_id; 1098 unsigned int wait_scp; 1099 unsigned int wait_scp_header; 1100 unsigned int wait_num_data; 1101 unsigned int scp_resp_header; 1102 unsigned int scp_resp_data[4]; 1103 unsigned int scp_resp_count; 1104 bool startup_check_entered; 1105 bool dsp_reload; 1106 1107 /* mixer and effects related */ 1108 unsigned char dmic_ctl; 1109 int cur_out_type; 1110 int cur_mic_type; 1111 long vnode_lvol[VNODES_COUNT]; 1112 long vnode_rvol[VNODES_COUNT]; 1113 long vnode_lswitch[VNODES_COUNT]; 1114 long vnode_rswitch[VNODES_COUNT]; 1115 long effects_switch[EFFECTS_COUNT]; 1116 long voicefx_val; 1117 long cur_mic_boost; 1118 /* ca0132_alt control related values */ 1119 unsigned char in_enum_val; 1120 unsigned char out_enum_val; 1121 unsigned char channel_cfg_val; 1122 unsigned char speaker_range_val[2]; 1123 unsigned char mic_boost_enum_val; 1124 unsigned char smart_volume_setting; 1125 unsigned char bass_redirection_val; 1126 long bass_redirect_xover_freq; 1127 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1128 long xbass_xover_freq; 1129 long eq_preset_val; 1130 unsigned int tlv[4]; 1131 struct hda_vmaster_mute_hook vmaster_mute; 1132 /* AE-5 Control values */ 1133 unsigned char ae5_headphone_gain_val; 1134 unsigned char ae5_filter_val; 1135 /* ZxR Control Values */ 1136 unsigned char zxr_gain_set; 1137 1138 struct hda_codec *codec; 1139 struct delayed_work unsol_hp_work; 1140 1141 #ifdef ENABLE_TUNING_CONTROLS 1142 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1143 #endif 1144 /* 1145 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1146 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1147 * things. 1148 */ 1149 bool use_pci_mmio; 1150 void __iomem *mem_base; 1151 1152 /* 1153 * Whether or not to use the alt functions like alt_select_out, 1154 * alt_select_in, etc. Only used on desktop codecs for now, because of 1155 * surround sound support. 1156 */ 1157 bool use_alt_functions; 1158 1159 /* 1160 * Whether or not to use alt controls: volume effect sliders, EQ 1161 * presets, smart volume presets, and new control names with FX prefix. 1162 * Renames PlayEnhancement and CrystalVoice too. 1163 */ 1164 bool use_alt_controls; 1165 }; 1166 1167 /* 1168 * CA0132 quirks table 1169 */ 1170 enum { 1171 QUIRK_ALIENWARE, 1172 QUIRK_ALIENWARE_M17XR4, 1173 QUIRK_SBZ, 1174 QUIRK_ZXR, 1175 QUIRK_ZXR_DBPRO, 1176 QUIRK_R3DI, 1177 QUIRK_R3D, 1178 QUIRK_AE5, 1179 QUIRK_AE7, 1180 QUIRK_GENERIC, 1181 QUIRK_NONE = HDA_FIXUP_ID_NOT_SET, 1182 }; 1183 1184 #ifdef CONFIG_PCI 1185 #define ca0132_quirk(spec) ((spec)->codec->fixup_id) 1186 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1187 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1188 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1189 #else 1190 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1191 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1192 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1193 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1194 #endif 1195 1196 static const struct hda_pintbl alienware_pincfgs[] = { 1197 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1198 { 0x0c, 0x411111f0 }, /* N/A */ 1199 { 0x0d, 0x411111f0 }, /* N/A */ 1200 { 0x0e, 0x411111f0 }, /* N/A */ 1201 { 0x0f, 0x0321101f }, /* HP */ 1202 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1203 { 0x11, 0x03a11021 }, /* Mic */ 1204 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1205 { 0x13, 0x411111f0 }, /* N/A */ 1206 { 0x18, 0x411111f0 }, /* N/A */ 1207 {} 1208 }; 1209 1210 /* Sound Blaster Z pin configs taken from Windows Driver */ 1211 static const struct hda_pintbl sbz_pincfgs[] = { 1212 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1213 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1214 { 0x0d, 0x014510f0 }, /* Digital Out */ 1215 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1216 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1217 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1218 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1219 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1220 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1221 { 0x18, 0x50d000f0 }, /* N/A */ 1222 {} 1223 }; 1224 1225 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1226 static const struct hda_pintbl zxr_pincfgs[] = { 1227 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1228 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1229 { 0x0d, 0x014510f0 }, /* Digital Out */ 1230 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1231 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1232 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1233 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1234 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1235 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1236 { 0x18, 0x50d000f0 }, /* N/A */ 1237 {} 1238 }; 1239 1240 /* Recon3D pin configs taken from Windows Driver */ 1241 static const struct hda_pintbl r3d_pincfgs[] = { 1242 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1243 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1244 { 0x0d, 0x014510f0 }, /* Digital Out */ 1245 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1246 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1247 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1248 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1249 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1250 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1251 { 0x18, 0x50d000f0 }, /* N/A */ 1252 {} 1253 }; 1254 1255 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1256 static const struct hda_pintbl ae5_pincfgs[] = { 1257 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1258 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1259 { 0x0d, 0x014510f0 }, /* Digital Out */ 1260 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1261 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1262 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1263 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1264 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1265 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1266 { 0x18, 0x50d000f0 }, /* N/A */ 1267 {} 1268 }; 1269 1270 /* Recon3D integrated pin configs taken from Windows Driver */ 1271 static const struct hda_pintbl r3di_pincfgs[] = { 1272 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1273 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1274 { 0x0d, 0x014510f0 }, /* Digital Out */ 1275 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1276 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1277 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1278 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1279 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1280 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1281 { 0x18, 0x500000f0 }, /* N/A */ 1282 {} 1283 }; 1284 1285 static const struct hda_pintbl ae7_pincfgs[] = { 1286 { 0x0b, 0x01017010 }, 1287 { 0x0c, 0x014510f0 }, 1288 { 0x0d, 0x414510f0 }, 1289 { 0x0e, 0x01c520f0 }, 1290 { 0x0f, 0x01017114 }, 1291 { 0x10, 0x01017011 }, 1292 { 0x11, 0x018170ff }, 1293 { 0x12, 0x01a170f0 }, 1294 { 0x13, 0x908700f0 }, 1295 { 0x18, 0x500000f0 }, 1296 {} 1297 }; 1298 1299 static const struct hda_pintbl ca0132_generic_pincfgs[] = { 1300 { 0x0b, 0x41014111 }, 1301 { 0x0c, 0x414520f0 }, /* SPDIF out */ 1302 { 0x0d, 0x01014010 }, /* lineout */ 1303 { 0x0e, 0x41c501f0 }, 1304 { 0x0f, 0x411111f0 }, /* disabled */ 1305 { 0x10, 0x411111f0 }, /* disabled */ 1306 { 0x11, 0x41012014 }, 1307 { 0x12, 0x37a790f0 }, /* mic */ 1308 { 0x13, 0x77a701f0 }, 1309 { 0x18, 0x500000f0 }, 1310 {} 1311 }; 1312 1313 static const struct hda_quirk ca0132_quirks[] = { 1314 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1315 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1316 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1317 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1318 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1319 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1320 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1321 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1322 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1323 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1324 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1325 SND_PCI_QUIRK(0x1458, 0xA046, "Gigabyte GA-Z170X-Gaming G1", QUIRK_GENERIC), 1326 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1327 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), 1328 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), 1329 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1330 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1331 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1332 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), 1333 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1334 {} 1335 }; 1336 1337 static const struct hda_model_fixup ca0132_quirk_models[] = { 1338 { .id = QUIRK_ALIENWARE, .name = "alienware" }, 1339 { .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" }, 1340 { .id = QUIRK_SBZ, .name = "sbz" }, 1341 { .id = QUIRK_ZXR, .name = "zxr" }, 1342 { .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" }, 1343 { .id = QUIRK_R3DI, .name = "r3di" }, 1344 { .id = QUIRK_R3D, .name = "r3d" }, 1345 { .id = QUIRK_AE5, .name = "ae5" }, 1346 { .id = QUIRK_AE7, .name = "ae7" }, 1347 { .id = QUIRK_GENERIC, .name = "generic" }, 1348 {} 1349 }; 1350 1351 /* Output selection quirk info structures. */ 1352 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1353 #define MAX_QUIRK_SCP_SET_VALS 2 1354 struct ca0132_alt_out_set_info { 1355 unsigned int dac2port; /* ParamID 0x0d value. */ 1356 1357 bool has_hda_gpio; 1358 char hda_gpio_pin; 1359 char hda_gpio_set; 1360 1361 unsigned int mmio_gpio_count; 1362 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1363 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1364 1365 unsigned int scp_cmds_count; 1366 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1367 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1368 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1369 1370 bool has_chipio_write; 1371 unsigned int chipio_write_addr; 1372 unsigned int chipio_write_data; 1373 }; 1374 1375 struct ca0132_alt_out_set_quirk_data { 1376 int quirk_id; 1377 1378 bool has_headphone_gain; 1379 bool is_ae_series; 1380 1381 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1382 }; 1383 1384 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1385 { .quirk_id = QUIRK_R3DI, 1386 .has_headphone_gain = false, 1387 .is_ae_series = false, 1388 .out_set_info = { 1389 /* Speakers. */ 1390 { .dac2port = 0x24, 1391 .has_hda_gpio = true, 1392 .hda_gpio_pin = 2, 1393 .hda_gpio_set = 1, 1394 .mmio_gpio_count = 0, 1395 .scp_cmds_count = 0, 1396 .has_chipio_write = false, 1397 }, 1398 /* Headphones. */ 1399 { .dac2port = 0x21, 1400 .has_hda_gpio = true, 1401 .hda_gpio_pin = 2, 1402 .hda_gpio_set = 0, 1403 .mmio_gpio_count = 0, 1404 .scp_cmds_count = 0, 1405 .has_chipio_write = false, 1406 } }, 1407 }, 1408 { .quirk_id = QUIRK_R3D, 1409 .has_headphone_gain = false, 1410 .is_ae_series = false, 1411 .out_set_info = { 1412 /* Speakers. */ 1413 { .dac2port = 0x24, 1414 .has_hda_gpio = false, 1415 .mmio_gpio_count = 1, 1416 .mmio_gpio_pin = { 1 }, 1417 .mmio_gpio_set = { 1 }, 1418 .scp_cmds_count = 0, 1419 .has_chipio_write = false, 1420 }, 1421 /* Headphones. */ 1422 { .dac2port = 0x21, 1423 .has_hda_gpio = false, 1424 .mmio_gpio_count = 1, 1425 .mmio_gpio_pin = { 1 }, 1426 .mmio_gpio_set = { 0 }, 1427 .scp_cmds_count = 0, 1428 .has_chipio_write = false, 1429 } }, 1430 }, 1431 { .quirk_id = QUIRK_SBZ, 1432 .has_headphone_gain = false, 1433 .is_ae_series = false, 1434 .out_set_info = { 1435 /* Speakers. */ 1436 { .dac2port = 0x18, 1437 .has_hda_gpio = false, 1438 .mmio_gpio_count = 3, 1439 .mmio_gpio_pin = { 7, 4, 1 }, 1440 .mmio_gpio_set = { 0, 1, 1 }, 1441 .scp_cmds_count = 0, 1442 .has_chipio_write = false, }, 1443 /* Headphones. */ 1444 { .dac2port = 0x12, 1445 .has_hda_gpio = false, 1446 .mmio_gpio_count = 3, 1447 .mmio_gpio_pin = { 7, 4, 1 }, 1448 .mmio_gpio_set = { 1, 1, 0 }, 1449 .scp_cmds_count = 0, 1450 .has_chipio_write = false, 1451 } }, 1452 }, 1453 { .quirk_id = QUIRK_ZXR, 1454 .has_headphone_gain = true, 1455 .is_ae_series = false, 1456 .out_set_info = { 1457 /* Speakers. */ 1458 { .dac2port = 0x24, 1459 .has_hda_gpio = false, 1460 .mmio_gpio_count = 3, 1461 .mmio_gpio_pin = { 2, 3, 5 }, 1462 .mmio_gpio_set = { 1, 1, 0 }, 1463 .scp_cmds_count = 0, 1464 .has_chipio_write = false, 1465 }, 1466 /* Headphones. */ 1467 { .dac2port = 0x21, 1468 .has_hda_gpio = false, 1469 .mmio_gpio_count = 3, 1470 .mmio_gpio_pin = { 2, 3, 5 }, 1471 .mmio_gpio_set = { 0, 1, 1 }, 1472 .scp_cmds_count = 0, 1473 .has_chipio_write = false, 1474 } }, 1475 }, 1476 { .quirk_id = QUIRK_AE5, 1477 .has_headphone_gain = true, 1478 .is_ae_series = true, 1479 .out_set_info = { 1480 /* Speakers. */ 1481 { .dac2port = 0xa4, 1482 .has_hda_gpio = false, 1483 .mmio_gpio_count = 0, 1484 .scp_cmds_count = 2, 1485 .scp_cmd_mid = { 0x96, 0x96 }, 1486 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1487 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1488 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1489 .has_chipio_write = true, 1490 .chipio_write_addr = 0x0018b03c, 1491 .chipio_write_data = 0x00000012 1492 }, 1493 /* Headphones. */ 1494 { .dac2port = 0xa1, 1495 .has_hda_gpio = false, 1496 .mmio_gpio_count = 0, 1497 .scp_cmds_count = 2, 1498 .scp_cmd_mid = { 0x96, 0x96 }, 1499 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1500 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1501 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1502 .has_chipio_write = true, 1503 .chipio_write_addr = 0x0018b03c, 1504 .chipio_write_data = 0x00000012 1505 } }, 1506 }, 1507 { .quirk_id = QUIRK_AE7, 1508 .has_headphone_gain = true, 1509 .is_ae_series = true, 1510 .out_set_info = { 1511 /* Speakers. */ 1512 { .dac2port = 0x58, 1513 .has_hda_gpio = false, 1514 .mmio_gpio_count = 1, 1515 .mmio_gpio_pin = { 0 }, 1516 .mmio_gpio_set = { 1 }, 1517 .scp_cmds_count = 2, 1518 .scp_cmd_mid = { 0x96, 0x96 }, 1519 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1520 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1521 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1522 .has_chipio_write = true, 1523 .chipio_write_addr = 0x0018b03c, 1524 .chipio_write_data = 0x00000000 1525 }, 1526 /* Headphones. */ 1527 { .dac2port = 0x58, 1528 .has_hda_gpio = false, 1529 .mmio_gpio_count = 1, 1530 .mmio_gpio_pin = { 0 }, 1531 .mmio_gpio_set = { 1 }, 1532 .scp_cmds_count = 2, 1533 .scp_cmd_mid = { 0x96, 0x96 }, 1534 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1535 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1536 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1537 .has_chipio_write = true, 1538 .chipio_write_addr = 0x0018b03c, 1539 .chipio_write_data = 0x00000010 1540 } }, 1541 } 1542 }; 1543 1544 /* 1545 * CA0132 codec access 1546 */ 1547 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1548 unsigned int verb, unsigned int parm, unsigned int *res) 1549 { 1550 unsigned int response; 1551 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1552 *res = response; 1553 1554 return ((response == -1) ? -1 : 0); 1555 } 1556 1557 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1558 unsigned short converter_format, unsigned int *res) 1559 { 1560 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1561 converter_format & 0xffff, res); 1562 } 1563 1564 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1565 hda_nid_t nid, unsigned char stream, 1566 unsigned char channel, unsigned int *res) 1567 { 1568 unsigned char converter_stream_channel = 0; 1569 1570 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1571 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1572 converter_stream_channel, res); 1573 } 1574 1575 /* Chip access helper function */ 1576 static int chipio_send(struct hda_codec *codec, 1577 unsigned int reg, 1578 unsigned int data) 1579 { 1580 unsigned int res; 1581 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1582 1583 /* send bits of data specified by reg */ 1584 do { 1585 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1586 reg, data); 1587 if (res == VENDOR_STATUS_CHIPIO_OK) 1588 return 0; 1589 msleep(20); 1590 } while (time_before(jiffies, timeout)); 1591 1592 return -EIO; 1593 } 1594 1595 /* 1596 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1597 */ 1598 static int chipio_write_address(struct hda_codec *codec, 1599 unsigned int chip_addx) 1600 { 1601 struct ca0132_spec *spec = codec->spec; 1602 int res; 1603 1604 if (spec->curr_chip_addx == chip_addx) 1605 return 0; 1606 1607 /* send low 16 bits of the address */ 1608 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1609 chip_addx & 0xffff); 1610 1611 if (res != -EIO) { 1612 /* send high 16 bits of the address */ 1613 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1614 chip_addx >> 16); 1615 } 1616 1617 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1618 1619 return res; 1620 } 1621 1622 /* 1623 * Write data through the vendor widget -- NOT protected by the Mutex! 1624 */ 1625 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1626 { 1627 struct ca0132_spec *spec = codec->spec; 1628 int res; 1629 1630 /* send low 16 bits of the data */ 1631 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1632 1633 if (res != -EIO) { 1634 /* send high 16 bits of the data */ 1635 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1636 data >> 16); 1637 } 1638 1639 /*If no error encountered, automatically increment the address 1640 as per chip behaviour*/ 1641 spec->curr_chip_addx = (res != -EIO) ? 1642 (spec->curr_chip_addx + 4) : ~0U; 1643 return res; 1644 } 1645 1646 /* 1647 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1648 */ 1649 static int chipio_write_data_multiple(struct hda_codec *codec, 1650 const u32 *data, 1651 unsigned int count) 1652 { 1653 int status = 0; 1654 1655 if (data == NULL) { 1656 codec_dbg(codec, "chipio_write_data null ptr\n"); 1657 return -EINVAL; 1658 } 1659 1660 while ((count-- != 0) && (status == 0)) 1661 status = chipio_write_data(codec, *data++); 1662 1663 return status; 1664 } 1665 1666 1667 /* 1668 * Read data through the vendor widget -- NOT protected by the Mutex! 1669 */ 1670 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1671 { 1672 struct ca0132_spec *spec = codec->spec; 1673 int res; 1674 1675 /* post read */ 1676 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1677 1678 if (res != -EIO) { 1679 /* read status */ 1680 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1681 } 1682 1683 if (res != -EIO) { 1684 /* read data */ 1685 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1686 VENDOR_CHIPIO_HIC_READ_DATA, 1687 0); 1688 } 1689 1690 /*If no error encountered, automatically increment the address 1691 as per chip behaviour*/ 1692 spec->curr_chip_addx = (res != -EIO) ? 1693 (spec->curr_chip_addx + 4) : ~0U; 1694 return res; 1695 } 1696 1697 /* 1698 * Write given value to the given address through the chip I/O widget. 1699 * protected by the Mutex 1700 */ 1701 static int chipio_write(struct hda_codec *codec, 1702 unsigned int chip_addx, const unsigned int data) 1703 { 1704 struct ca0132_spec *spec = codec->spec; 1705 int err; 1706 1707 guard(mutex)(&spec->chipio_mutex); 1708 1709 /* write the address, and if successful proceed to write data */ 1710 err = chipio_write_address(codec, chip_addx); 1711 if (err < 0) 1712 return err; 1713 1714 return chipio_write_data(codec, data); 1715 } 1716 1717 /* 1718 * Write given value to the given address through the chip I/O widget. 1719 * not protected by the Mutex 1720 */ 1721 static int chipio_write_no_mutex(struct hda_codec *codec, 1722 unsigned int chip_addx, const unsigned int data) 1723 { 1724 int err; 1725 1726 1727 /* write the address, and if successful proceed to write data */ 1728 err = chipio_write_address(codec, chip_addx); 1729 if (err < 0) 1730 goto exit; 1731 1732 err = chipio_write_data(codec, data); 1733 if (err < 0) 1734 goto exit; 1735 1736 exit: 1737 return err; 1738 } 1739 1740 /* 1741 * Write multiple values to the given address through the chip I/O widget. 1742 * protected by the Mutex 1743 */ 1744 static int chipio_write_multiple(struct hda_codec *codec, 1745 u32 chip_addx, 1746 const u32 *data, 1747 unsigned int count) 1748 { 1749 struct ca0132_spec *spec = codec->spec; 1750 int status; 1751 1752 guard(mutex)(&spec->chipio_mutex); 1753 status = chipio_write_address(codec, chip_addx); 1754 if (status < 0) 1755 return status; 1756 1757 return chipio_write_data_multiple(codec, data, count); 1758 } 1759 1760 /* 1761 * Read the given address through the chip I/O widget 1762 * protected by the Mutex 1763 */ 1764 static int chipio_read(struct hda_codec *codec, 1765 unsigned int chip_addx, unsigned int *data) 1766 { 1767 struct ca0132_spec *spec = codec->spec; 1768 int err; 1769 1770 guard(mutex)(&spec->chipio_mutex); 1771 1772 /* write the address, and if successful proceed to write data */ 1773 err = chipio_write_address(codec, chip_addx); 1774 if (err < 0) 1775 return err; 1776 1777 return chipio_read_data(codec, data); 1778 } 1779 1780 /* 1781 * Set chip control flags through the chip I/O widget. 1782 */ 1783 static void chipio_set_control_flag(struct hda_codec *codec, 1784 enum control_flag_id flag_id, 1785 bool flag_state) 1786 { 1787 unsigned int val; 1788 unsigned int flag_bit; 1789 1790 flag_bit = (flag_state ? 1 : 0); 1791 val = (flag_bit << 7) | (flag_id); 1792 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1793 VENDOR_CHIPIO_FLAG_SET, val); 1794 } 1795 1796 /* 1797 * Set chip parameters through the chip I/O widget. 1798 */ 1799 static void chipio_set_control_param(struct hda_codec *codec, 1800 enum control_param_id param_id, int param_val) 1801 { 1802 struct ca0132_spec *spec = codec->spec; 1803 int val; 1804 1805 if ((param_id < 32) && (param_val < 8)) { 1806 val = (param_val << 5) | (param_id); 1807 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1808 VENDOR_CHIPIO_PARAM_SET, val); 1809 } else { 1810 guard(mutex)(&spec->chipio_mutex); 1811 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1812 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1813 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1814 param_id); 1815 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1816 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1817 param_val); 1818 } 1819 } 1820 } 1821 1822 /* 1823 * Set chip parameters through the chip I/O widget. NO MUTEX. 1824 */ 1825 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1826 enum control_param_id param_id, int param_val) 1827 { 1828 int val; 1829 1830 if ((param_id < 32) && (param_val < 8)) { 1831 val = (param_val << 5) | (param_id); 1832 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1833 VENDOR_CHIPIO_PARAM_SET, val); 1834 } else { 1835 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1836 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1837 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1838 param_id); 1839 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1840 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1841 param_val); 1842 } 1843 } 1844 } 1845 /* 1846 * Connect stream to a source point, and then connect 1847 * that source point to a destination point. 1848 */ 1849 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1850 int streamid, int source_point, int dest_point) 1851 { 1852 chipio_set_control_param_no_mutex(codec, 1853 CONTROL_PARAM_STREAM_ID, streamid); 1854 chipio_set_control_param_no_mutex(codec, 1855 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1856 chipio_set_control_param_no_mutex(codec, 1857 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1858 } 1859 1860 /* 1861 * Set number of channels in the selected stream. 1862 */ 1863 static void chipio_set_stream_channels(struct hda_codec *codec, 1864 int streamid, unsigned int channels) 1865 { 1866 chipio_set_control_param_no_mutex(codec, 1867 CONTROL_PARAM_STREAM_ID, streamid); 1868 chipio_set_control_param_no_mutex(codec, 1869 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1870 } 1871 1872 /* 1873 * Enable/Disable audio stream. 1874 */ 1875 static void chipio_set_stream_control(struct hda_codec *codec, 1876 int streamid, int enable) 1877 { 1878 chipio_set_control_param_no_mutex(codec, 1879 CONTROL_PARAM_STREAM_ID, streamid); 1880 chipio_set_control_param_no_mutex(codec, 1881 CONTROL_PARAM_STREAM_CONTROL, enable); 1882 } 1883 1884 /* 1885 * Get ChipIO audio stream's status. 1886 */ 1887 static void chipio_get_stream_control(struct hda_codec *codec, 1888 int streamid, unsigned int *enable) 1889 { 1890 chipio_set_control_param_no_mutex(codec, 1891 CONTROL_PARAM_STREAM_ID, streamid); 1892 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1893 VENDOR_CHIPIO_PARAM_GET, 1894 CONTROL_PARAM_STREAM_CONTROL); 1895 } 1896 1897 /* 1898 * Set sampling rate of the connection point. NO MUTEX. 1899 */ 1900 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1901 int connid, enum ca0132_sample_rate rate) 1902 { 1903 chipio_set_control_param_no_mutex(codec, 1904 CONTROL_PARAM_CONN_POINT_ID, connid); 1905 chipio_set_control_param_no_mutex(codec, 1906 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1907 } 1908 1909 /* 1910 * Set sampling rate of the connection point. 1911 */ 1912 static void chipio_set_conn_rate(struct hda_codec *codec, 1913 int connid, enum ca0132_sample_rate rate) 1914 { 1915 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1916 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1917 rate); 1918 } 1919 1920 /* 1921 * Writes to the 8051's internal address space directly instead of indirectly, 1922 * giving access to the special function registers located at addresses 1923 * 0x80-0xFF. 1924 */ 1925 static void chipio_8051_write_direct(struct hda_codec *codec, 1926 unsigned int addr, unsigned int data) 1927 { 1928 unsigned int verb; 1929 1930 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1931 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1932 } 1933 1934 /* 1935 * Writes to the 8051's exram, which has 16-bits of address space. 1936 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. 1937 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by 1938 * setting the pmem bank selection SFR. 1939 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff 1940 * being writable. 1941 */ 1942 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) 1943 { 1944 unsigned int tmp; 1945 1946 /* Lower 8-bits. */ 1947 tmp = addr & 0xff; 1948 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1949 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); 1950 1951 /* Upper 8-bits. */ 1952 tmp = (addr >> 8) & 0xff; 1953 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1954 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); 1955 } 1956 1957 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) 1958 { 1959 /* 8-bits of data. */ 1960 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1961 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); 1962 } 1963 1964 static unsigned int chipio_8051_get_data(struct hda_codec *codec) 1965 { 1966 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1967 VENDOR_CHIPIO_8051_DATA_READ, 0); 1968 } 1969 1970 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ 1971 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) 1972 { 1973 /* 8-bits of data. */ 1974 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1975 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); 1976 } 1977 1978 static void chipio_8051_write_exram(struct hda_codec *codec, 1979 unsigned int addr, unsigned int data) 1980 { 1981 struct ca0132_spec *spec = codec->spec; 1982 1983 guard(mutex)(&spec->chipio_mutex); 1984 1985 chipio_8051_set_address(codec, addr); 1986 chipio_8051_set_data(codec, data); 1987 } 1988 1989 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, 1990 unsigned int addr, unsigned int data) 1991 { 1992 chipio_8051_set_address(codec, addr); 1993 chipio_8051_set_data(codec, data); 1994 } 1995 1996 /* Readback data from the 8051's exram. No mutex. */ 1997 static void chipio_8051_read_exram(struct hda_codec *codec, 1998 unsigned int addr, unsigned int *data) 1999 { 2000 chipio_8051_set_address(codec, addr); 2001 *data = chipio_8051_get_data(codec); 2002 } 2003 2004 static void chipio_8051_write_pll_pmu(struct hda_codec *codec, 2005 unsigned int addr, unsigned int data) 2006 { 2007 struct ca0132_spec *spec = codec->spec; 2008 2009 guard(mutex)(&spec->chipio_mutex); 2010 2011 chipio_8051_set_address(codec, addr & 0xff); 2012 chipio_8051_set_data_pll(codec, data); 2013 } 2014 2015 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, 2016 unsigned int addr, unsigned int data) 2017 { 2018 chipio_8051_set_address(codec, addr & 0xff); 2019 chipio_8051_set_data_pll(codec, data); 2020 } 2021 2022 /* 2023 * Enable clocks. 2024 */ 2025 static void chipio_enable_clocks(struct hda_codec *codec) 2026 { 2027 struct ca0132_spec *spec = codec->spec; 2028 2029 guard(mutex)(&spec->chipio_mutex); 2030 2031 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); 2032 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); 2033 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); 2034 } 2035 2036 /* 2037 * CA0132 DSP IO stuffs 2038 */ 2039 static int dspio_send(struct hda_codec *codec, unsigned int reg, 2040 unsigned int data) 2041 { 2042 int res; 2043 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2044 2045 /* send bits of data specified by reg to dsp */ 2046 do { 2047 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 2048 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 2049 return res; 2050 msleep(20); 2051 } while (time_before(jiffies, timeout)); 2052 2053 return -EIO; 2054 } 2055 2056 /* 2057 * Wait for DSP to be ready for commands 2058 */ 2059 static void dspio_write_wait(struct hda_codec *codec) 2060 { 2061 int status; 2062 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2063 2064 do { 2065 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2066 VENDOR_DSPIO_STATUS, 0); 2067 if ((status == VENDOR_STATUS_DSPIO_OK) || 2068 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 2069 break; 2070 msleep(1); 2071 } while (time_before(jiffies, timeout)); 2072 } 2073 2074 /* 2075 * Write SCP data to DSP 2076 */ 2077 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 2078 { 2079 struct ca0132_spec *spec = codec->spec; 2080 int status; 2081 2082 dspio_write_wait(codec); 2083 2084 guard(mutex)(&spec->chipio_mutex); 2085 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 2086 scp_data & 0xffff); 2087 if (status < 0) 2088 return status; 2089 2090 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 2091 scp_data >> 16); 2092 if (status < 0) 2093 return status; 2094 2095 /* OK, now check if the write itself has executed*/ 2096 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2097 VENDOR_DSPIO_STATUS, 0); 2098 2099 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 2100 -EIO : 0; 2101 } 2102 2103 /* 2104 * Write multiple SCP data to DSP 2105 */ 2106 static int dspio_write_multiple(struct hda_codec *codec, 2107 unsigned int *buffer, unsigned int size) 2108 { 2109 int status = 0; 2110 unsigned int count; 2111 2112 if (buffer == NULL) 2113 return -EINVAL; 2114 2115 count = 0; 2116 while (count < size) { 2117 status = dspio_write(codec, *buffer++); 2118 if (status != 0) 2119 break; 2120 count++; 2121 } 2122 2123 return status; 2124 } 2125 2126 static int dspio_read(struct hda_codec *codec, unsigned int *data) 2127 { 2128 int status; 2129 2130 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 2131 if (status == -EIO) 2132 return status; 2133 2134 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 2135 if (status == -EIO || 2136 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 2137 return -EIO; 2138 2139 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2140 VENDOR_DSPIO_SCP_READ_DATA, 0); 2141 2142 return 0; 2143 } 2144 2145 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2146 unsigned int *buf_size, unsigned int size_count) 2147 { 2148 int status = 0; 2149 unsigned int size = *buf_size; 2150 unsigned int count; 2151 unsigned int skip_count; 2152 unsigned int dummy; 2153 2154 if (buffer == NULL) 2155 return -1; 2156 2157 count = 0; 2158 while (count < size && count < size_count) { 2159 status = dspio_read(codec, buffer++); 2160 if (status != 0) 2161 break; 2162 count++; 2163 } 2164 2165 skip_count = count; 2166 if (status == 0) { 2167 while (skip_count < size) { 2168 status = dspio_read(codec, &dummy); 2169 if (status != 0) 2170 break; 2171 skip_count++; 2172 } 2173 } 2174 *buf_size = count; 2175 2176 return status; 2177 } 2178 2179 /* 2180 * Construct the SCP header using corresponding fields 2181 */ 2182 static inline unsigned int 2183 make_scp_header(unsigned int target_id, unsigned int source_id, 2184 unsigned int get_flag, unsigned int req, 2185 unsigned int device_flag, unsigned int resp_flag, 2186 unsigned int error_flag, unsigned int data_size) 2187 { 2188 unsigned int header = 0; 2189 2190 header = (data_size & 0x1f) << 27; 2191 header |= (error_flag & 0x01) << 26; 2192 header |= (resp_flag & 0x01) << 25; 2193 header |= (device_flag & 0x01) << 24; 2194 header |= (req & 0x7f) << 17; 2195 header |= (get_flag & 0x01) << 16; 2196 header |= (source_id & 0xff) << 8; 2197 header |= target_id & 0xff; 2198 2199 return header; 2200 } 2201 2202 /* 2203 * Extract corresponding fields from SCP header 2204 */ 2205 static inline void 2206 extract_scp_header(unsigned int header, 2207 unsigned int *target_id, unsigned int *source_id, 2208 unsigned int *get_flag, unsigned int *req, 2209 unsigned int *device_flag, unsigned int *resp_flag, 2210 unsigned int *error_flag, unsigned int *data_size) 2211 { 2212 if (data_size) 2213 *data_size = (header >> 27) & 0x1f; 2214 if (error_flag) 2215 *error_flag = (header >> 26) & 0x01; 2216 if (resp_flag) 2217 *resp_flag = (header >> 25) & 0x01; 2218 if (device_flag) 2219 *device_flag = (header >> 24) & 0x01; 2220 if (req) 2221 *req = (header >> 17) & 0x7f; 2222 if (get_flag) 2223 *get_flag = (header >> 16) & 0x01; 2224 if (source_id) 2225 *source_id = (header >> 8) & 0xff; 2226 if (target_id) 2227 *target_id = header & 0xff; 2228 } 2229 2230 #define SCP_MAX_DATA_WORDS (16) 2231 2232 /* Structure to contain any SCP message */ 2233 struct scp_msg { 2234 unsigned int hdr; 2235 unsigned int data[SCP_MAX_DATA_WORDS]; 2236 }; 2237 2238 static void dspio_clear_response_queue(struct hda_codec *codec) 2239 { 2240 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2241 unsigned int dummy = 0; 2242 int status; 2243 2244 /* clear all from the response queue */ 2245 do { 2246 status = dspio_read(codec, &dummy); 2247 } while (status == 0 && time_before(jiffies, timeout)); 2248 } 2249 2250 static int dspio_get_response_data(struct hda_codec *codec) 2251 { 2252 struct ca0132_spec *spec = codec->spec; 2253 unsigned int data = 0; 2254 unsigned int count; 2255 2256 if (dspio_read(codec, &data) < 0) 2257 return -EIO; 2258 2259 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2260 spec->scp_resp_header = data; 2261 spec->scp_resp_count = data >> 27; 2262 count = spec->wait_num_data; 2263 dspio_read_multiple(codec, spec->scp_resp_data, 2264 &spec->scp_resp_count, count); 2265 return 0; 2266 } 2267 2268 return -EIO; 2269 } 2270 2271 /* 2272 * Send SCP message to DSP 2273 */ 2274 static int dspio_send_scp_message(struct hda_codec *codec, 2275 unsigned char *send_buf, 2276 unsigned int send_buf_size, 2277 unsigned char *return_buf, 2278 unsigned int return_buf_size, 2279 unsigned int *bytes_returned) 2280 { 2281 struct ca0132_spec *spec = codec->spec; 2282 int status; 2283 unsigned int scp_send_size = 0; 2284 unsigned int total_size; 2285 bool waiting_for_resp = false; 2286 unsigned int header; 2287 struct scp_msg *ret_msg; 2288 unsigned int resp_src_id, resp_target_id; 2289 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2290 2291 if (bytes_returned) 2292 *bytes_returned = 0; 2293 2294 /* get scp header from buffer */ 2295 header = *((unsigned int *)send_buf); 2296 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2297 &device_flag, NULL, NULL, &data_size); 2298 scp_send_size = data_size + 1; 2299 total_size = (scp_send_size * 4); 2300 2301 if (send_buf_size < total_size) 2302 return -EINVAL; 2303 2304 if (get_flag || device_flag) { 2305 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2306 return -EINVAL; 2307 2308 spec->wait_scp_header = *((unsigned int *)send_buf); 2309 2310 /* swap source id with target id */ 2311 resp_target_id = src_id; 2312 resp_src_id = target_id; 2313 spec->wait_scp_header &= 0xffff0000; 2314 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2315 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2316 spec->wait_scp = 1; 2317 waiting_for_resp = true; 2318 } 2319 2320 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2321 scp_send_size); 2322 if (status < 0) { 2323 spec->wait_scp = 0; 2324 return status; 2325 } 2326 2327 if (waiting_for_resp) { 2328 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2329 memset(return_buf, 0, return_buf_size); 2330 do { 2331 msleep(20); 2332 } while (spec->wait_scp && time_before(jiffies, timeout)); 2333 waiting_for_resp = false; 2334 if (!spec->wait_scp) { 2335 ret_msg = (struct scp_msg *)return_buf; 2336 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2337 memcpy(&ret_msg->data, spec->scp_resp_data, 2338 spec->wait_num_data); 2339 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2340 status = 0; 2341 } else { 2342 status = -EIO; 2343 } 2344 spec->wait_scp = 0; 2345 } 2346 2347 return status; 2348 } 2349 2350 /** 2351 * dspio_scp - Prepare and send the SCP message to DSP 2352 * @codec: the HDA codec 2353 * @mod_id: ID of the DSP module to send the command 2354 * @src_id: ID of the source 2355 * @req: ID of request to send to the DSP module 2356 * @dir: SET or GET 2357 * @data: pointer to the data to send with the request, request specific 2358 * @len: length of the data, in bytes 2359 * @reply: point to the buffer to hold data returned for a reply 2360 * @reply_len: length of the reply buffer returned from GET 2361 * 2362 * Returns zero or a negative error code. 2363 */ 2364 static int dspio_scp(struct hda_codec *codec, 2365 int mod_id, int src_id, int req, int dir, const void *data, 2366 unsigned int len, void *reply, unsigned int *reply_len) 2367 { 2368 int status = 0; 2369 struct scp_msg scp_send, scp_reply; 2370 unsigned int ret_bytes, send_size, ret_size; 2371 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2372 unsigned int reply_data_size; 2373 2374 memset(&scp_send, 0, sizeof(scp_send)); 2375 memset(&scp_reply, 0, sizeof(scp_reply)); 2376 2377 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2378 return -EINVAL; 2379 2380 if (dir == SCP_GET && reply == NULL) { 2381 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2382 return -EINVAL; 2383 } 2384 2385 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2386 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2387 return -EINVAL; 2388 } 2389 2390 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2391 0, 0, 0, len/sizeof(unsigned int)); 2392 if (data != NULL && len > 0) { 2393 len = min((unsigned int)(sizeof(scp_send.data)), len); 2394 memcpy(scp_send.data, data, len); 2395 } 2396 2397 ret_bytes = 0; 2398 send_size = sizeof(unsigned int) + len; 2399 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2400 send_size, (unsigned char *)&scp_reply, 2401 sizeof(scp_reply), &ret_bytes); 2402 2403 if (status < 0) { 2404 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2405 return status; 2406 } 2407 2408 /* extract send and reply headers members */ 2409 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2410 NULL, NULL, NULL, NULL, NULL); 2411 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2412 &reply_resp_flag, &reply_error_flag, 2413 &reply_data_size); 2414 2415 if (!send_get_flag) 2416 return 0; 2417 2418 if (reply_resp_flag && !reply_error_flag) { 2419 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2420 / sizeof(unsigned int); 2421 2422 if (*reply_len < ret_size*sizeof(unsigned int)) { 2423 codec_dbg(codec, "reply too long for buf\n"); 2424 return -EINVAL; 2425 } else if (ret_size != reply_data_size) { 2426 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2427 return -EINVAL; 2428 } else if (!reply) { 2429 codec_dbg(codec, "NULL reply\n"); 2430 return -EINVAL; 2431 } else { 2432 *reply_len = ret_size*sizeof(unsigned int); 2433 memcpy(reply, scp_reply.data, *reply_len); 2434 } 2435 } else { 2436 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2437 return -EIO; 2438 } 2439 2440 return status; 2441 } 2442 2443 /* 2444 * Set DSP parameters 2445 */ 2446 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2447 int src_id, int req, const void *data, unsigned int len) 2448 { 2449 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2450 NULL); 2451 } 2452 2453 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2454 int req, const unsigned int data) 2455 { 2456 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2457 sizeof(unsigned int)); 2458 } 2459 2460 /* 2461 * Allocate a DSP DMA channel via an SCP message 2462 */ 2463 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2464 { 2465 int status = 0; 2466 unsigned int size = sizeof(*dma_chan); 2467 2468 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2469 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2470 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2471 dma_chan, &size); 2472 2473 if (status < 0) { 2474 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2475 return status; 2476 } 2477 2478 if ((*dma_chan + 1) == 0) { 2479 codec_dbg(codec, "no free dma channels to allocate\n"); 2480 return -EBUSY; 2481 } 2482 2483 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2484 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2485 2486 return status; 2487 } 2488 2489 /* 2490 * Free a DSP DMA via an SCP message 2491 */ 2492 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2493 { 2494 int status = 0; 2495 unsigned int dummy = 0; 2496 2497 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2498 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2499 2500 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2501 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2502 sizeof(dma_chan), NULL, &dummy); 2503 2504 if (status < 0) { 2505 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2506 return status; 2507 } 2508 2509 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2510 2511 return status; 2512 } 2513 2514 /* 2515 * (Re)start the DSP 2516 */ 2517 static int dsp_set_run_state(struct hda_codec *codec) 2518 { 2519 unsigned int dbg_ctrl_reg; 2520 unsigned int halt_state; 2521 int err; 2522 2523 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2524 if (err < 0) 2525 return err; 2526 2527 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2528 DSP_DBGCNTL_STATE_LOBIT; 2529 2530 if (halt_state != 0) { 2531 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2532 DSP_DBGCNTL_SS_MASK); 2533 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2534 dbg_ctrl_reg); 2535 if (err < 0) 2536 return err; 2537 2538 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2539 DSP_DBGCNTL_EXEC_MASK; 2540 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2541 dbg_ctrl_reg); 2542 if (err < 0) 2543 return err; 2544 } 2545 2546 return 0; 2547 } 2548 2549 /* 2550 * Reset the DSP 2551 */ 2552 static int dsp_reset(struct hda_codec *codec) 2553 { 2554 unsigned int res; 2555 int retry = 20; 2556 2557 codec_dbg(codec, "dsp_reset\n"); 2558 do { 2559 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2560 retry--; 2561 } while (res == -EIO && retry); 2562 2563 if (!retry) { 2564 codec_dbg(codec, "dsp_reset timeout\n"); 2565 return -EIO; 2566 } 2567 2568 return 0; 2569 } 2570 2571 /* 2572 * Convert chip address to DSP address 2573 */ 2574 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2575 bool *code, bool *yram) 2576 { 2577 *code = *yram = false; 2578 2579 if (UC_RANGE(chip_addx, 1)) { 2580 *code = true; 2581 return UC_OFF(chip_addx); 2582 } else if (X_RANGE_ALL(chip_addx, 1)) { 2583 return X_OFF(chip_addx); 2584 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2585 *yram = true; 2586 return Y_OFF(chip_addx); 2587 } 2588 2589 return INVALID_CHIP_ADDRESS; 2590 } 2591 2592 /* 2593 * Check if the DSP DMA is active 2594 */ 2595 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2596 { 2597 unsigned int dma_chnlstart_reg; 2598 2599 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2600 2601 return ((dma_chnlstart_reg & (1 << 2602 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2603 } 2604 2605 static int dsp_dma_setup_common(struct hda_codec *codec, 2606 unsigned int chip_addx, 2607 unsigned int dma_chan, 2608 unsigned int port_map_mask, 2609 bool ovly) 2610 { 2611 int status = 0; 2612 unsigned int chnl_prop; 2613 unsigned int dsp_addx; 2614 unsigned int active; 2615 bool code, yram; 2616 2617 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2618 2619 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2620 codec_dbg(codec, "dma chan num invalid\n"); 2621 return -EINVAL; 2622 } 2623 2624 if (dsp_is_dma_active(codec, dma_chan)) { 2625 codec_dbg(codec, "dma already active\n"); 2626 return -EBUSY; 2627 } 2628 2629 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2630 2631 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2632 codec_dbg(codec, "invalid chip addr\n"); 2633 return -ENXIO; 2634 } 2635 2636 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2637 active = 0; 2638 2639 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2640 2641 if (ovly) { 2642 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2643 &chnl_prop); 2644 2645 if (status < 0) { 2646 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2647 return status; 2648 } 2649 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2650 } 2651 2652 if (!code) 2653 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2654 else 2655 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2656 2657 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2658 2659 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2660 if (status < 0) { 2661 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2662 return status; 2663 } 2664 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2665 2666 if (ovly) { 2667 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2668 &active); 2669 2670 if (status < 0) { 2671 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2672 return status; 2673 } 2674 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2675 } 2676 2677 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2678 DSPDMAC_ACTIVE_AAR_MASK; 2679 2680 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2681 if (status < 0) { 2682 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2683 return status; 2684 } 2685 2686 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2687 2688 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2689 port_map_mask); 2690 if (status < 0) { 2691 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2692 return status; 2693 } 2694 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2695 2696 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2697 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2698 if (status < 0) { 2699 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2700 return status; 2701 } 2702 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2703 2704 codec_dbg(codec, 2705 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2706 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2707 chip_addx, dsp_addx, dma_chan, 2708 port_map_mask, chnl_prop, active); 2709 2710 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2711 2712 return 0; 2713 } 2714 2715 /* 2716 * Setup the DSP DMA per-transfer-specific registers 2717 */ 2718 static int dsp_dma_setup(struct hda_codec *codec, 2719 unsigned int chip_addx, 2720 unsigned int count, 2721 unsigned int dma_chan) 2722 { 2723 int status = 0; 2724 bool code, yram; 2725 unsigned int dsp_addx; 2726 unsigned int addr_field; 2727 unsigned int incr_field; 2728 unsigned int base_cnt; 2729 unsigned int cur_cnt; 2730 unsigned int dma_cfg = 0; 2731 unsigned int adr_ofs = 0; 2732 unsigned int xfr_cnt = 0; 2733 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2734 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2735 2736 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2737 2738 if (count > max_dma_count) { 2739 codec_dbg(codec, "count too big\n"); 2740 return -EINVAL; 2741 } 2742 2743 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2744 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2745 codec_dbg(codec, "invalid chip addr\n"); 2746 return -ENXIO; 2747 } 2748 2749 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2750 2751 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2752 incr_field = 0; 2753 2754 if (!code) { 2755 addr_field <<= 1; 2756 if (yram) 2757 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2758 2759 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2760 } 2761 2762 dma_cfg = addr_field + incr_field; 2763 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2764 dma_cfg); 2765 if (status < 0) { 2766 codec_dbg(codec, "write DMACFG Reg fail\n"); 2767 return status; 2768 } 2769 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2770 2771 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2772 (code ? 0 : 1)); 2773 2774 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2775 adr_ofs); 2776 if (status < 0) { 2777 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2778 return status; 2779 } 2780 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2781 2782 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2783 2784 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2785 2786 xfr_cnt = base_cnt | cur_cnt; 2787 2788 status = chipio_write(codec, 2789 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2790 if (status < 0) { 2791 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2792 return status; 2793 } 2794 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2795 2796 codec_dbg(codec, 2797 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2798 "ADROFS=0x%x, XFRCNT=0x%x\n", 2799 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2800 2801 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2802 2803 return 0; 2804 } 2805 2806 /* 2807 * Start the DSP DMA 2808 */ 2809 static int dsp_dma_start(struct hda_codec *codec, 2810 unsigned int dma_chan, bool ovly) 2811 { 2812 unsigned int reg = 0; 2813 int status = 0; 2814 2815 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2816 2817 if (ovly) { 2818 status = chipio_read(codec, 2819 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2820 2821 if (status < 0) { 2822 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2823 return status; 2824 } 2825 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2826 2827 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2828 DSPDMAC_CHNLSTART_DIS_MASK); 2829 } 2830 2831 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2832 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2833 if (status < 0) { 2834 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2835 return status; 2836 } 2837 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2838 2839 return status; 2840 } 2841 2842 /* 2843 * Stop the DSP DMA 2844 */ 2845 static int dsp_dma_stop(struct hda_codec *codec, 2846 unsigned int dma_chan, bool ovly) 2847 { 2848 unsigned int reg = 0; 2849 int status = 0; 2850 2851 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2852 2853 if (ovly) { 2854 status = chipio_read(codec, 2855 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2856 2857 if (status < 0) { 2858 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2859 return status; 2860 } 2861 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2862 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2863 DSPDMAC_CHNLSTART_DIS_MASK); 2864 } 2865 2866 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2867 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2868 if (status < 0) { 2869 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2870 return status; 2871 } 2872 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2873 2874 return status; 2875 } 2876 2877 /** 2878 * dsp_allocate_router_ports - Allocate router ports 2879 * 2880 * @codec: the HDA codec 2881 * @num_chans: number of channels in the stream 2882 * @ports_per_channel: number of ports per channel 2883 * @start_device: start device 2884 * @port_map: pointer to the port list to hold the allocated ports 2885 * 2886 * Returns zero or a negative error code. 2887 */ 2888 static int dsp_allocate_router_ports(struct hda_codec *codec, 2889 unsigned int num_chans, 2890 unsigned int ports_per_channel, 2891 unsigned int start_device, 2892 unsigned int *port_map) 2893 { 2894 int status = 0; 2895 int res; 2896 u8 val; 2897 2898 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2899 if (status < 0) 2900 return status; 2901 2902 val = start_device << 6; 2903 val |= (ports_per_channel - 1) << 4; 2904 val |= num_chans - 1; 2905 2906 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2907 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2908 val); 2909 2910 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2911 VENDOR_CHIPIO_PORT_ALLOC_SET, 2912 MEM_CONNID_DSP); 2913 2914 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2915 if (status < 0) 2916 return status; 2917 2918 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2919 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2920 2921 *port_map = res; 2922 2923 return (res < 0) ? res : 0; 2924 } 2925 2926 /* 2927 * Free router ports 2928 */ 2929 static int dsp_free_router_ports(struct hda_codec *codec) 2930 { 2931 int status = 0; 2932 2933 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2934 if (status < 0) 2935 return status; 2936 2937 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2938 VENDOR_CHIPIO_PORT_FREE_SET, 2939 MEM_CONNID_DSP); 2940 2941 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2942 2943 return status; 2944 } 2945 2946 /* 2947 * Allocate DSP ports for the download stream 2948 */ 2949 static int dsp_allocate_ports(struct hda_codec *codec, 2950 unsigned int num_chans, 2951 unsigned int rate_multi, unsigned int *port_map) 2952 { 2953 int status; 2954 2955 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2956 2957 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2958 codec_dbg(codec, "bad rate multiple\n"); 2959 return -EINVAL; 2960 } 2961 2962 status = dsp_allocate_router_ports(codec, num_chans, 2963 rate_multi, 0, port_map); 2964 2965 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2966 2967 return status; 2968 } 2969 2970 static int dsp_allocate_ports_format(struct hda_codec *codec, 2971 const unsigned short fmt, 2972 unsigned int *port_map) 2973 { 2974 unsigned int num_chans; 2975 2976 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2977 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2978 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2979 2980 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2981 codec_dbg(codec, "bad rate multiple\n"); 2982 return -EINVAL; 2983 } 2984 2985 num_chans = get_hdafmt_chs(fmt) + 1; 2986 2987 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2988 } 2989 2990 /* 2991 * free DSP ports 2992 */ 2993 static int dsp_free_ports(struct hda_codec *codec) 2994 { 2995 int status; 2996 2997 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2998 2999 status = dsp_free_router_ports(codec); 3000 if (status < 0) { 3001 codec_dbg(codec, "free router ports fail\n"); 3002 return status; 3003 } 3004 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 3005 3006 return status; 3007 } 3008 3009 /* 3010 * HDA DMA engine stuffs for DSP code download 3011 */ 3012 struct dma_engine { 3013 struct hda_codec *codec; 3014 unsigned short m_converter_format; 3015 struct snd_dma_buffer *dmab; 3016 unsigned int buf_size; 3017 }; 3018 3019 3020 enum dma_state { 3021 DMA_STATE_STOP = 0, 3022 DMA_STATE_RUN = 1 3023 }; 3024 3025 static int dma_convert_to_hda_format(struct hda_codec *codec, 3026 unsigned int sample_rate, 3027 unsigned short channels, 3028 unsigned short *hda_format) 3029 { 3030 unsigned int format_val; 3031 3032 format_val = snd_hdac_stream_format(channels, 32, sample_rate); 3033 3034 if (hda_format) 3035 *hda_format = (unsigned short)format_val; 3036 3037 return 0; 3038 } 3039 3040 /* 3041 * Reset DMA for DSP download 3042 */ 3043 static int dma_reset(struct dma_engine *dma) 3044 { 3045 struct hda_codec *codec = dma->codec; 3046 struct ca0132_spec *spec = codec->spec; 3047 int status; 3048 3049 if (dma->dmab->area) 3050 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 3051 3052 status = snd_hda_codec_load_dsp_prepare(codec, 3053 dma->m_converter_format, 3054 dma->buf_size, 3055 dma->dmab); 3056 if (status < 0) 3057 return status; 3058 spec->dsp_stream_id = status; 3059 return 0; 3060 } 3061 3062 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 3063 { 3064 bool cmd; 3065 3066 switch (state) { 3067 case DMA_STATE_STOP: 3068 cmd = false; 3069 break; 3070 case DMA_STATE_RUN: 3071 cmd = true; 3072 break; 3073 default: 3074 return 0; 3075 } 3076 3077 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 3078 return 0; 3079 } 3080 3081 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 3082 { 3083 return dma->dmab->bytes; 3084 } 3085 3086 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 3087 { 3088 return dma->dmab->area; 3089 } 3090 3091 static int dma_xfer(struct dma_engine *dma, 3092 const unsigned int *data, 3093 unsigned int count) 3094 { 3095 memcpy(dma->dmab->area, data, count); 3096 return 0; 3097 } 3098 3099 static void dma_get_converter_format( 3100 struct dma_engine *dma, 3101 unsigned short *format) 3102 { 3103 if (format) 3104 *format = dma->m_converter_format; 3105 } 3106 3107 static unsigned int dma_get_stream_id(struct dma_engine *dma) 3108 { 3109 struct ca0132_spec *spec = dma->codec->spec; 3110 3111 return spec->dsp_stream_id; 3112 } 3113 3114 struct dsp_image_seg { 3115 u32 magic; 3116 u32 chip_addr; 3117 u32 count; 3118 u32 data[]; 3119 }; 3120 3121 static const u32 g_magic_value = 0x4c46584d; 3122 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 3123 3124 static bool is_valid(const struct dsp_image_seg *p) 3125 { 3126 return p->magic == g_magic_value; 3127 } 3128 3129 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3130 { 3131 return g_chip_addr_magic_value == p->chip_addr; 3132 } 3133 3134 static bool is_last(const struct dsp_image_seg *p) 3135 { 3136 return p->count == 0; 3137 } 3138 3139 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3140 { 3141 return struct_size(p, data, p->count); 3142 } 3143 3144 static const struct dsp_image_seg *get_next_seg_ptr( 3145 const struct dsp_image_seg *p) 3146 { 3147 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3148 } 3149 3150 /* 3151 * CA0132 chip DSP transfer stuffs. For DSP download. 3152 */ 3153 #define INVALID_DMA_CHANNEL (~0U) 3154 3155 /* 3156 * Program a list of address/data pairs via the ChipIO widget. 3157 * The segment data is in the format of successive pairs of words. 3158 * These are repeated as indicated by the segment's count field. 3159 */ 3160 static int dspxfr_hci_write(struct hda_codec *codec, 3161 const struct dsp_image_seg *fls) 3162 { 3163 int status; 3164 const u32 *data; 3165 unsigned int count; 3166 3167 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3168 codec_dbg(codec, "hci_write invalid params\n"); 3169 return -EINVAL; 3170 } 3171 3172 count = fls->count; 3173 data = (u32 *)(fls->data); 3174 while (count >= 2) { 3175 status = chipio_write(codec, data[0], data[1]); 3176 if (status < 0) { 3177 codec_dbg(codec, "hci_write chipio failed\n"); 3178 return status; 3179 } 3180 count -= 2; 3181 data += 2; 3182 } 3183 return 0; 3184 } 3185 3186 /** 3187 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. 3188 * 3189 * @codec: the HDA codec 3190 * @fls: pointer to a fast load image 3191 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3192 * no relocation 3193 * @dma_engine: pointer to DMA engine to be used for DSP download 3194 * @dma_chan: The number of DMA channels used for DSP download 3195 * @port_map_mask: port mapping 3196 * @ovly: TRUE if overlay format is required 3197 * 3198 * Returns zero or a negative error code. 3199 */ 3200 static int dspxfr_one_seg(struct hda_codec *codec, 3201 const struct dsp_image_seg *fls, 3202 unsigned int reloc, 3203 struct dma_engine *dma_engine, 3204 unsigned int dma_chan, 3205 unsigned int port_map_mask, 3206 bool ovly) 3207 { 3208 int status = 0; 3209 bool comm_dma_setup_done = false; 3210 const unsigned int *data; 3211 unsigned int chip_addx; 3212 unsigned int words_to_write; 3213 unsigned int buffer_size_words; 3214 unsigned char *buffer_addx; 3215 unsigned short hda_format; 3216 unsigned int sample_rate_div; 3217 unsigned int sample_rate_mul; 3218 unsigned int num_chans; 3219 unsigned int hda_frame_size_words; 3220 unsigned int remainder_words; 3221 const u32 *data_remainder; 3222 u32 chip_addx_remainder; 3223 unsigned int run_size_words; 3224 const struct dsp_image_seg *hci_write = NULL; 3225 unsigned long timeout; 3226 bool dma_active; 3227 3228 if (fls == NULL) 3229 return -EINVAL; 3230 if (is_hci_prog_list_seg(fls)) { 3231 hci_write = fls; 3232 fls = get_next_seg_ptr(fls); 3233 } 3234 3235 if (hci_write && (!fls || is_last(fls))) { 3236 codec_dbg(codec, "hci_write\n"); 3237 return dspxfr_hci_write(codec, hci_write); 3238 } 3239 3240 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3241 codec_dbg(codec, "Invalid Params\n"); 3242 return -EINVAL; 3243 } 3244 3245 data = fls->data; 3246 chip_addx = fls->chip_addr; 3247 words_to_write = fls->count; 3248 3249 if (!words_to_write) 3250 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3251 if (reloc) 3252 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3253 3254 if (!UC_RANGE(chip_addx, words_to_write) && 3255 !X_RANGE_ALL(chip_addx, words_to_write) && 3256 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3257 codec_dbg(codec, "Invalid chip_addx Params\n"); 3258 return -EINVAL; 3259 } 3260 3261 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3262 sizeof(u32); 3263 3264 buffer_addx = dma_get_buffer_addr(dma_engine); 3265 3266 if (buffer_addx == NULL) { 3267 codec_dbg(codec, "dma_engine buffer NULL\n"); 3268 return -EINVAL; 3269 } 3270 3271 dma_get_converter_format(dma_engine, &hda_format); 3272 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3273 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3274 num_chans = get_hdafmt_chs(hda_format) + 1; 3275 3276 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3277 (num_chans * sample_rate_mul / sample_rate_div)); 3278 3279 if (hda_frame_size_words == 0) { 3280 codec_dbg(codec, "frmsz zero\n"); 3281 return -EINVAL; 3282 } 3283 3284 buffer_size_words = min(buffer_size_words, 3285 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3286 65536 : 32768)); 3287 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3288 codec_dbg(codec, 3289 "chpadr=0x%08x frmsz=%u nchan=%u " 3290 "rate_mul=%u div=%u bufsz=%u\n", 3291 chip_addx, hda_frame_size_words, num_chans, 3292 sample_rate_mul, sample_rate_div, buffer_size_words); 3293 3294 if (buffer_size_words < hda_frame_size_words) { 3295 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3296 return -EINVAL; 3297 } 3298 3299 remainder_words = words_to_write % hda_frame_size_words; 3300 data_remainder = data; 3301 chip_addx_remainder = chip_addx; 3302 3303 data += remainder_words; 3304 chip_addx += remainder_words*sizeof(u32); 3305 words_to_write -= remainder_words; 3306 3307 while (words_to_write != 0) { 3308 run_size_words = min(buffer_size_words, words_to_write); 3309 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3310 words_to_write, run_size_words, remainder_words); 3311 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3312 if (!comm_dma_setup_done) { 3313 status = dsp_dma_stop(codec, dma_chan, ovly); 3314 if (status < 0) 3315 return status; 3316 status = dsp_dma_setup_common(codec, chip_addx, 3317 dma_chan, port_map_mask, ovly); 3318 if (status < 0) 3319 return status; 3320 comm_dma_setup_done = true; 3321 } 3322 3323 status = dsp_dma_setup(codec, chip_addx, 3324 run_size_words, dma_chan); 3325 if (status < 0) 3326 return status; 3327 status = dsp_dma_start(codec, dma_chan, ovly); 3328 if (status < 0) 3329 return status; 3330 if (!dsp_is_dma_active(codec, dma_chan)) { 3331 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3332 return -EIO; 3333 } 3334 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3335 if (status < 0) 3336 return status; 3337 if (remainder_words != 0) { 3338 status = chipio_write_multiple(codec, 3339 chip_addx_remainder, 3340 data_remainder, 3341 remainder_words); 3342 if (status < 0) 3343 return status; 3344 remainder_words = 0; 3345 } 3346 if (hci_write) { 3347 status = dspxfr_hci_write(codec, hci_write); 3348 if (status < 0) 3349 return status; 3350 hci_write = NULL; 3351 } 3352 3353 timeout = jiffies + msecs_to_jiffies(2000); 3354 do { 3355 dma_active = dsp_is_dma_active(codec, dma_chan); 3356 if (!dma_active) 3357 break; 3358 msleep(20); 3359 } while (time_before(jiffies, timeout)); 3360 if (dma_active) 3361 break; 3362 3363 codec_dbg(codec, "+++++ DMA complete\n"); 3364 dma_set_state(dma_engine, DMA_STATE_STOP); 3365 status = dma_reset(dma_engine); 3366 3367 if (status < 0) 3368 return status; 3369 3370 data += run_size_words; 3371 chip_addx += run_size_words*sizeof(u32); 3372 words_to_write -= run_size_words; 3373 } 3374 3375 if (remainder_words != 0) { 3376 status = chipio_write_multiple(codec, chip_addx_remainder, 3377 data_remainder, remainder_words); 3378 } 3379 3380 return status; 3381 } 3382 3383 /** 3384 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories 3385 * 3386 * @codec: the HDA codec 3387 * @fls_data: pointer to a fast load image 3388 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3389 * no relocation 3390 * @sample_rate: sampling rate of the stream used for DSP download 3391 * @channels: channels of the stream used for DSP download 3392 * @ovly: TRUE if overlay format is required 3393 * 3394 * Returns zero or a negative error code. 3395 */ 3396 static int dspxfr_image(struct hda_codec *codec, 3397 const struct dsp_image_seg *fls_data, 3398 unsigned int reloc, 3399 unsigned int sample_rate, 3400 unsigned short channels, 3401 bool ovly) 3402 { 3403 struct ca0132_spec *spec = codec->spec; 3404 int status; 3405 unsigned short hda_format = 0; 3406 unsigned int response; 3407 unsigned char stream_id = 0; 3408 struct dma_engine *dma_engine; 3409 unsigned int dma_chan; 3410 unsigned int port_map_mask; 3411 3412 if (fls_data == NULL) 3413 return -EINVAL; 3414 3415 dma_engine = kzalloc_obj(*dma_engine); 3416 if (!dma_engine) 3417 return -ENOMEM; 3418 3419 dma_engine->dmab = kzalloc_obj(*dma_engine->dmab); 3420 if (!dma_engine->dmab) { 3421 kfree(dma_engine); 3422 return -ENOMEM; 3423 } 3424 3425 dma_engine->codec = codec; 3426 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3427 dma_engine->m_converter_format = hda_format; 3428 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3429 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3430 3431 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3432 3433 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3434 hda_format, &response); 3435 3436 if (status < 0) { 3437 codec_dbg(codec, "set converter format fail\n"); 3438 goto exit; 3439 } 3440 3441 status = snd_hda_codec_load_dsp_prepare(codec, 3442 dma_engine->m_converter_format, 3443 dma_engine->buf_size, 3444 dma_engine->dmab); 3445 if (status < 0) 3446 goto exit; 3447 spec->dsp_stream_id = status; 3448 3449 if (ovly) { 3450 status = dspio_alloc_dma_chan(codec, &dma_chan); 3451 if (status < 0) { 3452 codec_dbg(codec, "alloc dmachan fail\n"); 3453 dma_chan = INVALID_DMA_CHANNEL; 3454 goto exit; 3455 } 3456 } 3457 3458 port_map_mask = 0; 3459 status = dsp_allocate_ports_format(codec, hda_format, 3460 &port_map_mask); 3461 if (status < 0) { 3462 codec_dbg(codec, "alloc ports fail\n"); 3463 goto exit; 3464 } 3465 3466 stream_id = dma_get_stream_id(dma_engine); 3467 status = codec_set_converter_stream_channel(codec, 3468 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3469 if (status < 0) { 3470 codec_dbg(codec, "set stream chan fail\n"); 3471 goto exit; 3472 } 3473 3474 while ((fls_data != NULL) && !is_last(fls_data)) { 3475 if (!is_valid(fls_data)) { 3476 codec_dbg(codec, "FLS check fail\n"); 3477 status = -EINVAL; 3478 goto exit; 3479 } 3480 status = dspxfr_one_seg(codec, fls_data, reloc, 3481 dma_engine, dma_chan, 3482 port_map_mask, ovly); 3483 if (status < 0) 3484 break; 3485 3486 if (is_hci_prog_list_seg(fls_data)) 3487 fls_data = get_next_seg_ptr(fls_data); 3488 3489 if ((fls_data != NULL) && !is_last(fls_data)) 3490 fls_data = get_next_seg_ptr(fls_data); 3491 } 3492 3493 if (port_map_mask != 0) 3494 status = dsp_free_ports(codec); 3495 3496 if (status < 0) 3497 goto exit; 3498 3499 status = codec_set_converter_stream_channel(codec, 3500 WIDGET_CHIP_CTRL, 0, 0, &response); 3501 3502 exit: 3503 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3504 dspio_free_dma_chan(codec, dma_chan); 3505 3506 if (dma_engine->dmab->area) 3507 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3508 kfree(dma_engine->dmab); 3509 kfree(dma_engine); 3510 3511 return status; 3512 } 3513 3514 /* 3515 * CA0132 DSP download stuffs. 3516 */ 3517 static void dspload_post_setup(struct hda_codec *codec) 3518 { 3519 struct ca0132_spec *spec = codec->spec; 3520 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3521 if (!ca0132_use_alt_functions(spec)) { 3522 /*set DSP speaker to 2.0 configuration*/ 3523 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3524 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3525 3526 /*update write pointer*/ 3527 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3528 } 3529 } 3530 3531 /** 3532 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3533 * 3534 * @codec: the HDA codec 3535 * @fls: pointer to a fast load image 3536 * @ovly: TRUE if overlay format is required 3537 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3538 * no relocation 3539 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3540 * @router_chans: number of audio router channels to be allocated (0 means use 3541 * internal defaults; max is 32) 3542 * 3543 * Download DSP from a DSP Image Fast Load structure. This structure is a 3544 * linear, non-constant sized element array of structures, each of which 3545 * contain the count of the data to be loaded, the data itself, and the 3546 * corresponding starting chip address of the starting data location. 3547 * Returns zero or a negative error code. 3548 */ 3549 static int dspload_image(struct hda_codec *codec, 3550 const struct dsp_image_seg *fls, 3551 bool ovly, 3552 unsigned int reloc, 3553 bool autostart, 3554 int router_chans) 3555 { 3556 int status = 0; 3557 unsigned int sample_rate; 3558 unsigned short channels; 3559 3560 codec_dbg(codec, "---- dspload_image begin ------\n"); 3561 if (router_chans == 0) { 3562 if (!ovly) 3563 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3564 else 3565 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3566 } 3567 3568 sample_rate = 48000; 3569 channels = (unsigned short)router_chans; 3570 3571 while (channels > 16) { 3572 sample_rate *= 2; 3573 channels /= 2; 3574 } 3575 3576 do { 3577 codec_dbg(codec, "Ready to program DMA\n"); 3578 if (!ovly) 3579 status = dsp_reset(codec); 3580 3581 if (status < 0) 3582 break; 3583 3584 codec_dbg(codec, "dsp_reset() complete\n"); 3585 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3586 ovly); 3587 3588 if (status < 0) 3589 break; 3590 3591 codec_dbg(codec, "dspxfr_image() complete\n"); 3592 if (autostart && !ovly) { 3593 dspload_post_setup(codec); 3594 status = dsp_set_run_state(codec); 3595 } 3596 3597 codec_dbg(codec, "LOAD FINISHED\n"); 3598 } while (0); 3599 3600 return status; 3601 } 3602 3603 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3604 static bool dspload_is_loaded(struct hda_codec *codec) 3605 { 3606 unsigned int data = 0; 3607 int status = 0; 3608 3609 status = chipio_read(codec, 0x40004, &data); 3610 if ((status < 0) || (data != 1)) 3611 return false; 3612 3613 return true; 3614 } 3615 #else 3616 #define dspload_is_loaded(codec) false 3617 #endif 3618 3619 static bool dspload_wait_loaded(struct hda_codec *codec) 3620 { 3621 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3622 3623 do { 3624 if (dspload_is_loaded(codec)) { 3625 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3626 return true; 3627 } 3628 msleep(20); 3629 } while (time_before(jiffies, timeout)); 3630 3631 codec_err(codec, "ca0132 failed to download DSP\n"); 3632 return false; 3633 } 3634 3635 /* 3636 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3637 * based cards, and has a second mmio region, region2, that's used for special 3638 * commands. 3639 */ 3640 3641 /* 3642 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3643 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3644 * The first eight bits are just the number of the pin. So far, I've only seen 3645 * this number go to 7. 3646 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3647 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3648 * then off to send that bit. 3649 */ 3650 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3651 bool enable) 3652 { 3653 struct ca0132_spec *spec = codec->spec; 3654 unsigned short gpio_data; 3655 3656 gpio_data = gpio_pin & 0xF; 3657 gpio_data |= ((enable << 8) & 0x100); 3658 3659 writew(gpio_data, spec->mem_base + 0x320); 3660 } 3661 3662 /* 3663 * Special pci region2 commands that are only used by the AE-5. They follow 3664 * a set format, and require reads at certain points to seemingly 'clear' 3665 * the response data. My first tests didn't do these reads, and would cause 3666 * the card to get locked up until the memory was read. These commands 3667 * seem to work with three distinct values that I've taken to calling group, 3668 * target-id, and value. 3669 */ 3670 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3671 unsigned int target, unsigned int value) 3672 { 3673 struct ca0132_spec *spec = codec->spec; 3674 unsigned int write_val; 3675 3676 writel(0x0000007e, spec->mem_base + 0x210); 3677 readl(spec->mem_base + 0x210); 3678 writel(0x0000005a, spec->mem_base + 0x210); 3679 readl(spec->mem_base + 0x210); 3680 readl(spec->mem_base + 0x210); 3681 3682 writel(0x00800005, spec->mem_base + 0x20c); 3683 writel(group, spec->mem_base + 0x804); 3684 3685 writel(0x00800005, spec->mem_base + 0x20c); 3686 write_val = (target & 0xff); 3687 write_val |= (value << 8); 3688 3689 3690 writel(write_val, spec->mem_base + 0x204); 3691 /* 3692 * Need delay here or else it goes too fast and works inconsistently. 3693 */ 3694 msleep(20); 3695 3696 readl(spec->mem_base + 0x860); 3697 readl(spec->mem_base + 0x854); 3698 readl(spec->mem_base + 0x840); 3699 3700 writel(0x00800004, spec->mem_base + 0x20c); 3701 writel(0x00000000, spec->mem_base + 0x210); 3702 readl(spec->mem_base + 0x210); 3703 readl(spec->mem_base + 0x210); 3704 } 3705 3706 /* 3707 * This second type of command is used for setting the sound filter type. 3708 */ 3709 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3710 unsigned int group, unsigned int target, unsigned int value) 3711 { 3712 struct ca0132_spec *spec = codec->spec; 3713 unsigned int write_val; 3714 3715 writel(0x0000007e, spec->mem_base + 0x210); 3716 readl(spec->mem_base + 0x210); 3717 writel(0x0000005a, spec->mem_base + 0x210); 3718 readl(spec->mem_base + 0x210); 3719 readl(spec->mem_base + 0x210); 3720 3721 writel(0x00800003, spec->mem_base + 0x20c); 3722 writel(group, spec->mem_base + 0x804); 3723 3724 writel(0x00800005, spec->mem_base + 0x20c); 3725 write_val = (target & 0xff); 3726 write_val |= (value << 8); 3727 3728 3729 writel(write_val, spec->mem_base + 0x204); 3730 msleep(20); 3731 readl(spec->mem_base + 0x860); 3732 readl(spec->mem_base + 0x854); 3733 readl(spec->mem_base + 0x840); 3734 3735 writel(0x00800004, spec->mem_base + 0x20c); 3736 writel(0x00000000, spec->mem_base + 0x210); 3737 readl(spec->mem_base + 0x210); 3738 readl(spec->mem_base + 0x210); 3739 } 3740 3741 /* 3742 * Setup GPIO for the other variants of Core3D. 3743 */ 3744 3745 /* 3746 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3747 * the card shows as having no GPIO pins. 3748 */ 3749 static void ca0132_gpio_init(struct hda_codec *codec) 3750 { 3751 struct ca0132_spec *spec = codec->spec; 3752 3753 switch (ca0132_quirk(spec)) { 3754 case QUIRK_SBZ: 3755 case QUIRK_AE5: 3756 case QUIRK_AE7: 3757 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3758 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3759 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3760 break; 3761 case QUIRK_R3DI: 3762 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3763 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3764 break; 3765 default: 3766 break; 3767 } 3768 3769 } 3770 3771 /* Sets the GPIO for audio output. */ 3772 static void ca0132_gpio_setup(struct hda_codec *codec) 3773 { 3774 struct ca0132_spec *spec = codec->spec; 3775 3776 switch (ca0132_quirk(spec)) { 3777 case QUIRK_SBZ: 3778 snd_hda_codec_set_gpio(codec, 0x07, 0x07, 0x04, 0); 3779 snd_hda_codec_write(codec, 0x01, 0, 3780 AC_VERB_SET_GPIO_DATA, 0x06); 3781 break; 3782 case QUIRK_R3DI: 3783 snd_hda_codec_set_gpio(codec, 0x1F, 0x1E, 0x0C, 0); 3784 break; 3785 default: 3786 break; 3787 } 3788 } 3789 3790 /* 3791 * GPIO control functions for the Recon3D integrated. 3792 */ 3793 3794 enum r3di_gpio_bit { 3795 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3796 R3DI_MIC_SELECT_BIT = 1, 3797 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3798 R3DI_OUT_SELECT_BIT = 2, 3799 /* 3800 * I dunno what this actually does, but it stays on until the dsp 3801 * is downloaded. 3802 */ 3803 R3DI_GPIO_DSP_DOWNLOADING = 3, 3804 /* 3805 * Same as above, no clue what it does, but it comes on after the dsp 3806 * is downloaded. 3807 */ 3808 R3DI_GPIO_DSP_DOWNLOADED = 4 3809 }; 3810 3811 enum r3di_mic_select { 3812 /* Set GPIO bit 1 to 0 for rear mic */ 3813 R3DI_REAR_MIC = 0, 3814 /* Set GPIO bit 1 to 1 for front microphone*/ 3815 R3DI_FRONT_MIC = 1 3816 }; 3817 3818 enum r3di_out_select { 3819 /* Set GPIO bit 2 to 0 for headphone */ 3820 R3DI_HEADPHONE_OUT = 0, 3821 /* Set GPIO bit 2 to 1 for speaker */ 3822 R3DI_LINE_OUT = 1 3823 }; 3824 enum r3di_dsp_status { 3825 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3826 R3DI_DSP_DOWNLOADING = 0, 3827 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3828 R3DI_DSP_DOWNLOADED = 1 3829 }; 3830 3831 3832 static void r3di_gpio_mic_set(struct hda_codec *codec, 3833 enum r3di_mic_select cur_mic) 3834 { 3835 unsigned int cur_gpio; 3836 3837 /* Get the current GPIO Data setup */ 3838 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3839 3840 switch (cur_mic) { 3841 case R3DI_REAR_MIC: 3842 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3843 break; 3844 case R3DI_FRONT_MIC: 3845 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3846 break; 3847 } 3848 snd_hda_codec_write(codec, codec->core.afg, 0, 3849 AC_VERB_SET_GPIO_DATA, cur_gpio); 3850 } 3851 3852 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3853 enum r3di_dsp_status dsp_status) 3854 { 3855 unsigned int cur_gpio; 3856 3857 /* Get the current GPIO Data setup */ 3858 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3859 3860 switch (dsp_status) { 3861 case R3DI_DSP_DOWNLOADING: 3862 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3863 snd_hda_codec_write(codec, codec->core.afg, 0, 3864 AC_VERB_SET_GPIO_DATA, cur_gpio); 3865 break; 3866 case R3DI_DSP_DOWNLOADED: 3867 /* Set DOWNLOADING bit to 0. */ 3868 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3869 3870 snd_hda_codec_write(codec, codec->core.afg, 0, 3871 AC_VERB_SET_GPIO_DATA, cur_gpio); 3872 3873 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3874 break; 3875 } 3876 3877 snd_hda_codec_write(codec, codec->core.afg, 0, 3878 AC_VERB_SET_GPIO_DATA, cur_gpio); 3879 } 3880 3881 /* 3882 * PCM callbacks 3883 */ 3884 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3885 struct hda_codec *codec, 3886 unsigned int stream_tag, 3887 unsigned int format, 3888 struct snd_pcm_substream *substream) 3889 { 3890 struct ca0132_spec *spec = codec->spec; 3891 3892 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3893 3894 return 0; 3895 } 3896 3897 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3898 struct hda_codec *codec, 3899 struct snd_pcm_substream *substream) 3900 { 3901 struct ca0132_spec *spec = codec->spec; 3902 3903 if (spec->dsp_state == DSP_DOWNLOADING) 3904 return 0; 3905 3906 /*If Playback effects are on, allow stream some time to flush 3907 *effects tail*/ 3908 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3909 msleep(50); 3910 3911 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3912 3913 return 0; 3914 } 3915 3916 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3917 struct hda_codec *codec, 3918 struct snd_pcm_substream *substream) 3919 { 3920 struct ca0132_spec *spec = codec->spec; 3921 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3922 struct snd_pcm_runtime *runtime = substream->runtime; 3923 3924 if (spec->dsp_state != DSP_DOWNLOADED) 3925 return 0; 3926 3927 /* Add latency if playback enhancement and either effect is enabled. */ 3928 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3929 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3930 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3931 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3932 } 3933 3934 /* Applying Speaker EQ adds latency as well. */ 3935 if (spec->cur_out_type == SPEAKER_OUT) 3936 latency += DSP_SPEAKER_OUT_LATENCY; 3937 3938 return (latency * runtime->rate) / 1000; 3939 } 3940 3941 /* 3942 * Digital out 3943 */ 3944 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3945 struct hda_codec *codec, 3946 struct snd_pcm_substream *substream) 3947 { 3948 struct ca0132_spec *spec = codec->spec; 3949 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3950 } 3951 3952 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3953 struct hda_codec *codec, 3954 unsigned int stream_tag, 3955 unsigned int format, 3956 struct snd_pcm_substream *substream) 3957 { 3958 struct ca0132_spec *spec = codec->spec; 3959 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3960 stream_tag, format, substream); 3961 } 3962 3963 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3964 struct hda_codec *codec, 3965 struct snd_pcm_substream *substream) 3966 { 3967 struct ca0132_spec *spec = codec->spec; 3968 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3969 } 3970 3971 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3972 struct hda_codec *codec, 3973 struct snd_pcm_substream *substream) 3974 { 3975 struct ca0132_spec *spec = codec->spec; 3976 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3977 } 3978 3979 /* 3980 * Analog capture 3981 */ 3982 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3983 struct hda_codec *codec, 3984 unsigned int stream_tag, 3985 unsigned int format, 3986 struct snd_pcm_substream *substream) 3987 { 3988 snd_hda_codec_setup_stream(codec, hinfo->nid, 3989 stream_tag, 0, format); 3990 3991 return 0; 3992 } 3993 3994 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3995 struct hda_codec *codec, 3996 struct snd_pcm_substream *substream) 3997 { 3998 struct ca0132_spec *spec = codec->spec; 3999 4000 if (spec->dsp_state == DSP_DOWNLOADING) 4001 return 0; 4002 4003 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 4004 return 0; 4005 } 4006 4007 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 4008 struct hda_codec *codec, 4009 struct snd_pcm_substream *substream) 4010 { 4011 struct ca0132_spec *spec = codec->spec; 4012 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 4013 struct snd_pcm_runtime *runtime = substream->runtime; 4014 4015 if (spec->dsp_state != DSP_DOWNLOADED) 4016 return 0; 4017 4018 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4019 latency += DSP_CRYSTAL_VOICE_LATENCY; 4020 4021 return (latency * runtime->rate) / 1000; 4022 } 4023 4024 /* 4025 * Controls stuffs. 4026 */ 4027 4028 /* 4029 * Mixer controls helpers. 4030 */ 4031 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4032 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4033 .name = xname, \ 4034 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4035 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4036 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4037 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4038 .info = ca0132_volume_info, \ 4039 .get = ca0132_volume_get, \ 4040 .put = ca0132_volume_put, \ 4041 .tlv = { .c = ca0132_volume_tlv }, \ 4042 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4043 4044 /* 4045 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 4046 * volume put, which is used for setting the DSP volume. This was done because 4047 * the ca0132 functions were taking too much time and causing lag. 4048 */ 4049 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4050 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4051 .name = xname, \ 4052 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4053 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4054 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4055 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4056 .info = snd_hda_mixer_amp_volume_info, \ 4057 .get = snd_hda_mixer_amp_volume_get, \ 4058 .put = ca0132_alt_volume_put, \ 4059 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 4060 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4061 4062 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 4063 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4064 .name = xname, \ 4065 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4066 .info = snd_hda_mixer_amp_switch_info, \ 4067 .get = ca0132_switch_get, \ 4068 .put = ca0132_switch_put, \ 4069 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4070 4071 /* stereo */ 4072 #define CA0132_CODEC_VOL(xname, nid, dir) \ 4073 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 4074 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 4075 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 4076 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 4077 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 4078 4079 /* lookup tables */ 4080 /* 4081 * Lookup table with decibel values for the DSP. When volume is changed in 4082 * Windows, the DSP is also sent the dB value in floating point. In Windows, 4083 * these values have decimal points, probably because the Windows driver 4084 * actually uses floating point. We can't here, so I made a lookup table of 4085 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 4086 * DAC's, and 9 is the maximum. 4087 */ 4088 static const unsigned int float_vol_db_lookup[] = { 4089 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 4090 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 4091 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 4092 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 4093 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 4094 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 4095 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 4096 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 4097 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 4098 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 4099 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 4100 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4101 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4102 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4103 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4104 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4105 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 4106 }; 4107 4108 /* 4109 * This table counts from float 0 to 1 in increments of .01, which is 4110 * useful for a few different sliders. 4111 */ 4112 static const unsigned int float_zero_to_one_lookup[] = { 4113 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4114 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4115 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4116 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4117 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4118 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4119 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4120 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4121 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4122 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4123 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4124 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4125 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4126 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4127 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4128 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4129 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4130 }; 4131 4132 /* 4133 * This table counts from float 10 to 1000, which is the range of the x-bass 4134 * crossover slider in Windows. 4135 */ 4136 static const unsigned int float_xbass_xover_lookup[] = { 4137 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4138 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4139 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4140 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4141 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4142 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4143 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4144 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4145 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4146 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4147 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4148 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4149 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4150 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4151 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4152 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4153 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4154 }; 4155 4156 /* The following are for tuning of products */ 4157 #ifdef ENABLE_TUNING_CONTROLS 4158 4159 static const unsigned int voice_focus_vals_lookup[] = { 4160 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4161 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4162 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4163 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4164 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4165 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4166 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4167 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4168 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4169 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4170 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4171 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4172 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4173 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4174 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4175 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4176 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4177 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4178 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4179 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4180 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4181 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4182 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4183 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4184 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4185 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4186 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4187 }; 4188 4189 static const unsigned int mic_svm_vals_lookup[] = { 4190 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4191 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4192 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4193 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4194 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4195 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4196 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4197 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4198 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4199 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4200 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4201 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4202 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4203 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4204 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4205 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4206 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4207 }; 4208 4209 static const unsigned int equalizer_vals_lookup[] = { 4210 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4211 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4212 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4213 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4214 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4215 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4216 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4217 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4218 0x41C00000 4219 }; 4220 4221 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4222 const unsigned int *lookup, int idx) 4223 { 4224 int i; 4225 4226 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4227 if (nid == ca0132_tuning_ctls[i].nid) { 4228 CLASS(snd_hda_power, pm)(codec); 4229 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4230 ca0132_tuning_ctls[i].req, 4231 &(lookup[idx]), sizeof(unsigned int)); 4232 return 1; 4233 } 4234 } 4235 4236 return -EINVAL; 4237 } 4238 4239 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4240 struct snd_ctl_elem_value *ucontrol) 4241 { 4242 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4243 struct ca0132_spec *spec = codec->spec; 4244 hda_nid_t nid = get_amp_nid(kcontrol); 4245 long *valp = ucontrol->value.integer.value; 4246 int idx = nid - TUNING_CTL_START_NID; 4247 4248 *valp = spec->cur_ctl_vals[idx]; 4249 return 0; 4250 } 4251 4252 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4253 struct snd_ctl_elem_info *uinfo) 4254 { 4255 int chs = get_amp_channels(kcontrol); 4256 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4257 uinfo->count = chs == 3 ? 2 : 1; 4258 uinfo->value.integer.min = 20; 4259 uinfo->value.integer.max = 180; 4260 uinfo->value.integer.step = 1; 4261 4262 return 0; 4263 } 4264 4265 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4266 struct snd_ctl_elem_value *ucontrol) 4267 { 4268 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4269 struct ca0132_spec *spec = codec->spec; 4270 hda_nid_t nid = get_amp_nid(kcontrol); 4271 long *valp = ucontrol->value.integer.value; 4272 int idx; 4273 4274 idx = nid - TUNING_CTL_START_NID; 4275 /* any change? */ 4276 if (spec->cur_ctl_vals[idx] == *valp) 4277 return 0; 4278 4279 spec->cur_ctl_vals[idx] = *valp; 4280 4281 idx = *valp - 20; 4282 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4283 4284 return 1; 4285 } 4286 4287 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4288 struct snd_ctl_elem_info *uinfo) 4289 { 4290 int chs = get_amp_channels(kcontrol); 4291 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4292 uinfo->count = chs == 3 ? 2 : 1; 4293 uinfo->value.integer.min = 0; 4294 uinfo->value.integer.max = 100; 4295 uinfo->value.integer.step = 1; 4296 4297 return 0; 4298 } 4299 4300 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4301 struct snd_ctl_elem_value *ucontrol) 4302 { 4303 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4304 struct ca0132_spec *spec = codec->spec; 4305 hda_nid_t nid = get_amp_nid(kcontrol); 4306 long *valp = ucontrol->value.integer.value; 4307 int idx; 4308 4309 idx = nid - TUNING_CTL_START_NID; 4310 /* any change? */ 4311 if (spec->cur_ctl_vals[idx] == *valp) 4312 return 0; 4313 4314 spec->cur_ctl_vals[idx] = *valp; 4315 4316 idx = *valp; 4317 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4318 4319 return 0; 4320 } 4321 4322 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4323 struct snd_ctl_elem_info *uinfo) 4324 { 4325 int chs = get_amp_channels(kcontrol); 4326 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4327 uinfo->count = chs == 3 ? 2 : 1; 4328 uinfo->value.integer.min = 0; 4329 uinfo->value.integer.max = 48; 4330 uinfo->value.integer.step = 1; 4331 4332 return 0; 4333 } 4334 4335 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4336 struct snd_ctl_elem_value *ucontrol) 4337 { 4338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4339 struct ca0132_spec *spec = codec->spec; 4340 hda_nid_t nid = get_amp_nid(kcontrol); 4341 long *valp = ucontrol->value.integer.value; 4342 int idx; 4343 4344 idx = nid - TUNING_CTL_START_NID; 4345 /* any change? */ 4346 if (spec->cur_ctl_vals[idx] == *valp) 4347 return 0; 4348 4349 spec->cur_ctl_vals[idx] = *valp; 4350 4351 idx = *valp; 4352 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4353 4354 return 1; 4355 } 4356 4357 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4358 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4359 4360 static int add_tuning_control(struct hda_codec *codec, 4361 hda_nid_t pnid, hda_nid_t nid, 4362 const char *name, int dir) 4363 { 4364 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4365 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4366 struct snd_kcontrol_new knew = 4367 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4368 4369 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4370 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4371 knew.tlv.c = NULL; 4372 knew.tlv.p = NULL; 4373 switch (pnid) { 4374 case VOICE_FOCUS: 4375 knew.info = voice_focus_ctl_info; 4376 knew.get = tuning_ctl_get; 4377 knew.put = voice_focus_ctl_put; 4378 knew.tlv.p = voice_focus_db_scale; 4379 break; 4380 case MIC_SVM: 4381 knew.info = mic_svm_ctl_info; 4382 knew.get = tuning_ctl_get; 4383 knew.put = mic_svm_ctl_put; 4384 break; 4385 case EQUALIZER: 4386 knew.info = equalizer_ctl_info; 4387 knew.get = tuning_ctl_get; 4388 knew.put = equalizer_ctl_put; 4389 knew.tlv.p = eq_db_scale; 4390 break; 4391 default: 4392 return 0; 4393 } 4394 knew.private_value = 4395 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4396 snprintf(namestr, sizeof(namestr), "%s %s Volume", name, dirstr[dir]); 4397 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4398 } 4399 4400 static int add_tuning_ctls(struct hda_codec *codec) 4401 { 4402 int i; 4403 int err; 4404 4405 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4406 err = add_tuning_control(codec, 4407 ca0132_tuning_ctls[i].parent_nid, 4408 ca0132_tuning_ctls[i].nid, 4409 ca0132_tuning_ctls[i].name, 4410 ca0132_tuning_ctls[i].direct); 4411 if (err < 0) 4412 return err; 4413 } 4414 4415 return 0; 4416 } 4417 4418 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4419 { 4420 struct ca0132_spec *spec = codec->spec; 4421 int i; 4422 4423 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4424 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4425 /* SVM level defaults to 0.74. */ 4426 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4427 4428 /* EQ defaults to 0dB. */ 4429 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4430 spec->cur_ctl_vals[i] = 24; 4431 } 4432 #endif /*ENABLE_TUNING_CONTROLS*/ 4433 4434 /* 4435 * Select the active output. 4436 * If autodetect is enabled, output will be selected based on jack detection. 4437 * If jack inserted, headphone will be selected, else built-in speakers 4438 * If autodetect is disabled, output will be selected based on selection. 4439 */ 4440 static int ca0132_select_out(struct hda_codec *codec) 4441 { 4442 struct ca0132_spec *spec = codec->spec; 4443 unsigned int pin_ctl; 4444 int jack_present; 4445 int auto_jack; 4446 unsigned int tmp; 4447 int err; 4448 4449 codec_dbg(codec, "ca0132_select_out\n"); 4450 4451 CLASS(snd_hda_power_pm, pm)(codec); 4452 4453 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4454 4455 if (auto_jack) 4456 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4457 else 4458 jack_present = 4459 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4460 4461 if (jack_present) 4462 spec->cur_out_type = HEADPHONE_OUT; 4463 else 4464 spec->cur_out_type = SPEAKER_OUT; 4465 4466 if (spec->cur_out_type == SPEAKER_OUT) { 4467 codec_dbg(codec, "ca0132_select_out speaker\n"); 4468 /*speaker out config*/ 4469 tmp = FLOAT_ONE; 4470 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4471 if (err < 0) 4472 return err; 4473 /*enable speaker EQ*/ 4474 tmp = FLOAT_ONE; 4475 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4476 if (err < 0) 4477 return err; 4478 4479 /* Setup EAPD */ 4480 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4481 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4482 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4483 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4484 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4485 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4486 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4487 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4488 4489 /* disable headphone node */ 4490 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4491 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4492 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4493 pin_ctl & ~PIN_HP); 4494 /* enable speaker node */ 4495 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4496 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4497 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4498 pin_ctl | PIN_OUT); 4499 } else { 4500 codec_dbg(codec, "ca0132_select_out hp\n"); 4501 /*headphone out config*/ 4502 tmp = FLOAT_ZERO; 4503 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4504 if (err < 0) 4505 return err; 4506 /*disable speaker EQ*/ 4507 tmp = FLOAT_ZERO; 4508 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4509 if (err < 0) 4510 return err; 4511 4512 /* Setup EAPD */ 4513 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4514 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4515 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4516 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4517 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4518 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4519 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4520 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4521 4522 /* disable speaker*/ 4523 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4524 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4525 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4526 pin_ctl & ~PIN_HP); 4527 /* enable headphone*/ 4528 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4529 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4530 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4531 pin_ctl | PIN_HP); 4532 } 4533 4534 return 0; 4535 } 4536 4537 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4538 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4539 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4540 4541 static void ae5_mmio_select_out(struct hda_codec *codec) 4542 { 4543 struct ca0132_spec *spec = codec->spec; 4544 const struct ae_ca0113_output_set *out_cmds; 4545 unsigned int i; 4546 4547 if (ca0132_quirk(spec) == QUIRK_AE5) 4548 out_cmds = &ae5_ca0113_output_presets; 4549 else 4550 out_cmds = &ae7_ca0113_output_presets; 4551 4552 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4553 ca0113_mmio_command_set(codec, out_cmds->group[i], 4554 out_cmds->target[i], 4555 out_cmds->vals[spec->cur_out_type][i]); 4556 } 4557 4558 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4559 { 4560 struct ca0132_spec *spec = codec->spec; 4561 int quirk = ca0132_quirk(spec); 4562 unsigned int tmp; 4563 int err; 4564 4565 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4566 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4567 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4568 return 0; 4569 4570 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4571 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4572 err = dspio_set_uint_param(codec, 0x96, 4573 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4574 if (err < 0) 4575 return err; 4576 4577 /* When setting full-range rear, both rear and center/lfe are set. */ 4578 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4579 err = dspio_set_uint_param(codec, 0x96, 4580 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4581 if (err < 0) 4582 return err; 4583 4584 err = dspio_set_uint_param(codec, 0x96, 4585 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4586 if (err < 0) 4587 return err; 4588 4589 /* 4590 * Only the AE series cards set this value when setting full-range, 4591 * and it's always 1.0f. 4592 */ 4593 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4594 err = dspio_set_uint_param(codec, 0x96, 4595 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4596 if (err < 0) 4597 return err; 4598 } 4599 4600 return 0; 4601 } 4602 4603 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4604 bool val) 4605 { 4606 struct ca0132_spec *spec = codec->spec; 4607 unsigned int tmp; 4608 int err; 4609 4610 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4611 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4612 tmp = FLOAT_ONE; 4613 else 4614 tmp = FLOAT_ZERO; 4615 4616 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4617 if (err < 0) 4618 return err; 4619 4620 /* If it is enabled, make sure to set the crossover frequency. */ 4621 if (tmp) { 4622 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4623 err = dspio_set_uint_param(codec, 0x96, 4624 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4625 if (err < 0) 4626 return err; 4627 } 4628 4629 return 0; 4630 } 4631 4632 /* 4633 * These are the commands needed to setup output on each of the different card 4634 * types. 4635 */ 4636 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4637 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4638 { 4639 struct ca0132_spec *spec = codec->spec; 4640 int quirk = ca0132_quirk(spec); 4641 unsigned int i; 4642 4643 *quirk_data = NULL; 4644 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4645 if (quirk_out_set_data[i].quirk_id == quirk) { 4646 *quirk_data = &quirk_out_set_data[i]; 4647 return; 4648 } 4649 } 4650 } 4651 4652 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4653 { 4654 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4655 const struct ca0132_alt_out_set_info *out_info; 4656 struct ca0132_spec *spec = codec->spec; 4657 unsigned int i, gpio_data; 4658 int err; 4659 4660 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4661 if (!quirk_data) 4662 return 0; 4663 4664 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4665 if (quirk_data->is_ae_series) 4666 ae5_mmio_select_out(codec); 4667 4668 if (out_info->has_hda_gpio) { 4669 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4670 AC_VERB_GET_GPIO_DATA, 0); 4671 4672 if (out_info->hda_gpio_set) 4673 gpio_data |= (1 << out_info->hda_gpio_pin); 4674 else 4675 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4676 4677 snd_hda_codec_write(codec, codec->core.afg, 0, 4678 AC_VERB_SET_GPIO_DATA, gpio_data); 4679 } 4680 4681 if (out_info->mmio_gpio_count) { 4682 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4683 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4684 out_info->mmio_gpio_set[i]); 4685 } 4686 } 4687 4688 if (out_info->scp_cmds_count) { 4689 for (i = 0; i < out_info->scp_cmds_count; i++) { 4690 err = dspio_set_uint_param(codec, 4691 out_info->scp_cmd_mid[i], 4692 out_info->scp_cmd_req[i], 4693 out_info->scp_cmd_val[i]); 4694 if (err < 0) 4695 return err; 4696 } 4697 } 4698 4699 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4700 4701 if (out_info->has_chipio_write) { 4702 chipio_write(codec, out_info->chipio_write_addr, 4703 out_info->chipio_write_data); 4704 } 4705 4706 if (quirk_data->has_headphone_gain) { 4707 if (spec->cur_out_type != HEADPHONE_OUT) { 4708 if (quirk_data->is_ae_series) 4709 ae5_headphone_gain_set(codec, 2); 4710 else 4711 zxr_headphone_gain_set(codec, 0); 4712 } else { 4713 if (quirk_data->is_ae_series) 4714 ae5_headphone_gain_set(codec, 4715 spec->ae5_headphone_gain_val); 4716 else 4717 zxr_headphone_gain_set(codec, 4718 spec->zxr_gain_set); 4719 } 4720 } 4721 4722 return 0; 4723 } 4724 4725 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4726 bool out_enable, bool hp_enable) 4727 { 4728 unsigned int pin_ctl; 4729 4730 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4731 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4732 4733 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4734 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4735 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4736 } 4737 4738 /* 4739 * This function behaves similarly to the ca0132_select_out funciton above, 4740 * except with a few differences. It adds the ability to select the current 4741 * output with an enumerated control "output source" if the auto detect 4742 * mute switch is set to off. If the auto detect mute switch is enabled, it 4743 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4744 * It also adds the ability to auto-detect the front headphone port. 4745 */ 4746 static int ca0132_alt_select_out(struct hda_codec *codec) 4747 { 4748 struct ca0132_spec *spec = codec->spec; 4749 unsigned int tmp, outfx_set; 4750 int jack_present; 4751 int auto_jack; 4752 int err; 4753 /* Default Headphone is rear headphone */ 4754 hda_nid_t headphone_nid = spec->out_pins[1]; 4755 4756 codec_dbg(codec, "%s\n", __func__); 4757 4758 CLASS(snd_hda_power_pm, pm)(codec); 4759 4760 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4761 4762 /* 4763 * If headphone rear or front is plugged in, set to headphone. 4764 * If neither is plugged in, set to rear line out. Only if 4765 * hp/speaker auto detect is enabled. 4766 */ 4767 if (auto_jack) { 4768 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4769 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4770 4771 if (jack_present) 4772 spec->cur_out_type = HEADPHONE_OUT; 4773 else 4774 spec->cur_out_type = SPEAKER_OUT; 4775 } else 4776 spec->cur_out_type = spec->out_enum_val; 4777 4778 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4779 4780 /* Begin DSP output switch, mute DSP volume. */ 4781 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4782 if (err < 0) 4783 return err; 4784 4785 err = ca0132_alt_select_out_quirk_set(codec); 4786 if (err < 0) 4787 return err; 4788 4789 switch (spec->cur_out_type) { 4790 case SPEAKER_OUT: 4791 codec_dbg(codec, "%s speaker\n", __func__); 4792 4793 /* Enable EAPD */ 4794 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4795 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4796 4797 /* Disable headphone node. */ 4798 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4799 /* Set front L-R to output. */ 4800 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4801 /* Set Center/LFE to output. */ 4802 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4803 /* Set rear surround to output. */ 4804 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4805 4806 /* 4807 * Without PlayEnhancement being enabled, if we've got a 2.0 4808 * setup, set it to floating point eight to disable any DSP 4809 * processing effects. 4810 */ 4811 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4812 tmp = FLOAT_EIGHT; 4813 else 4814 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4815 4816 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4817 if (err < 0) 4818 return err; 4819 4820 break; 4821 case HEADPHONE_OUT: 4822 codec_dbg(codec, "%s hp\n", __func__); 4823 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4824 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4825 4826 /* Disable all speaker nodes. */ 4827 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4828 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4829 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4830 4831 /* enable headphone, either front or rear */ 4832 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4833 headphone_nid = spec->out_pins[2]; 4834 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4835 headphone_nid = spec->out_pins[1]; 4836 4837 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4838 4839 if (outfx_set) 4840 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4841 else 4842 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4843 4844 if (err < 0) 4845 return err; 4846 break; 4847 } 4848 /* 4849 * If output effects are enabled, set the X-Bass effect value again to 4850 * make sure that it's properly enabled/disabled for speaker 4851 * configurations with an LFE channel. 4852 */ 4853 if (outfx_set) 4854 ca0132_effects_set(codec, X_BASS, 4855 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4856 4857 /* Set speaker EQ bypass attenuation to 0. */ 4858 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4859 if (err < 0) 4860 return err; 4861 4862 /* 4863 * Although unused on all cards but the AE series, this is always set 4864 * to zero when setting the output. 4865 */ 4866 err = dspio_set_uint_param(codec, 0x96, 4867 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4868 if (err < 0) 4869 return err; 4870 4871 if (spec->cur_out_type == SPEAKER_OUT) 4872 err = ca0132_alt_surround_set_bass_redirection(codec, 4873 spec->bass_redirection_val); 4874 else 4875 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4876 if (err < 0) 4877 return err; 4878 4879 /* Unmute DSP now that we're done with output selection. */ 4880 err = dspio_set_uint_param(codec, 0x96, 4881 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4882 if (err < 0) 4883 return err; 4884 4885 if (spec->cur_out_type == SPEAKER_OUT) { 4886 err = ca0132_alt_set_full_range_speaker(codec); 4887 if (err < 0) 4888 return err; 4889 } 4890 4891 return 0; 4892 } 4893 4894 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4895 { 4896 struct ca0132_spec *spec = container_of( 4897 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4898 struct hda_jack_tbl *jack; 4899 4900 if (ca0132_use_alt_functions(spec)) 4901 ca0132_alt_select_out(spec->codec); 4902 else 4903 ca0132_select_out(spec->codec); 4904 4905 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4906 if (jack) { 4907 jack->block_report = 0; 4908 snd_hda_jack_report_sync(spec->codec); 4909 } 4910 } 4911 4912 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4913 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4914 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4915 static int stop_mic1(struct hda_codec *codec); 4916 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4917 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4918 4919 /* 4920 * Select the active VIP source 4921 */ 4922 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4923 { 4924 struct ca0132_spec *spec = codec->spec; 4925 unsigned int tmp; 4926 4927 if (spec->dsp_state != DSP_DOWNLOADED) 4928 return 0; 4929 4930 /* if CrystalVoice if off, vipsource should be 0 */ 4931 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4932 (val == 0)) { 4933 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4934 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4935 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4936 if (spec->cur_mic_type == DIGITAL_MIC) 4937 tmp = FLOAT_TWO; 4938 else 4939 tmp = FLOAT_ONE; 4940 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4941 tmp = FLOAT_ZERO; 4942 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4943 } else { 4944 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4945 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4946 if (spec->cur_mic_type == DIGITAL_MIC) 4947 tmp = FLOAT_TWO; 4948 else 4949 tmp = FLOAT_ONE; 4950 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4951 tmp = FLOAT_ONE; 4952 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4953 msleep(20); 4954 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4955 } 4956 4957 return 1; 4958 } 4959 4960 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4961 { 4962 struct ca0132_spec *spec = codec->spec; 4963 unsigned int tmp; 4964 4965 if (spec->dsp_state != DSP_DOWNLOADED) 4966 return 0; 4967 4968 codec_dbg(codec, "%s\n", __func__); 4969 4970 chipio_set_stream_control(codec, 0x03, 0); 4971 chipio_set_stream_control(codec, 0x04, 0); 4972 4973 /* if CrystalVoice is off, vipsource should be 0 */ 4974 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4975 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4976 codec_dbg(codec, "%s: off.", __func__); 4977 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4978 4979 tmp = FLOAT_ZERO; 4980 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4981 4982 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4983 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4984 if (ca0132_quirk(spec) == QUIRK_R3DI) 4985 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4986 4987 4988 if (spec->in_enum_val == REAR_LINE_IN) 4989 tmp = FLOAT_ZERO; 4990 else { 4991 if (ca0132_quirk(spec) == QUIRK_SBZ) 4992 tmp = FLOAT_THREE; 4993 else 4994 tmp = FLOAT_ONE; 4995 } 4996 4997 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4998 4999 } else { 5000 codec_dbg(codec, "%s: on.", __func__); 5001 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 5002 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 5003 if (ca0132_quirk(spec) == QUIRK_R3DI) 5004 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 5005 5006 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 5007 tmp = FLOAT_TWO; 5008 else 5009 tmp = FLOAT_ONE; 5010 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5011 5012 tmp = FLOAT_ONE; 5013 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 5014 5015 msleep(20); 5016 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 5017 } 5018 5019 chipio_set_stream_control(codec, 0x03, 1); 5020 chipio_set_stream_control(codec, 0x04, 1); 5021 5022 return 1; 5023 } 5024 5025 /* 5026 * Select the active microphone. 5027 * If autodetect is enabled, mic will be selected based on jack detection. 5028 * If jack inserted, ext.mic will be selected, else built-in mic 5029 * If autodetect is disabled, mic will be selected based on selection. 5030 */ 5031 static int ca0132_select_mic(struct hda_codec *codec) 5032 { 5033 struct ca0132_spec *spec = codec->spec; 5034 int jack_present; 5035 int auto_jack; 5036 5037 codec_dbg(codec, "ca0132_select_mic\n"); 5038 5039 CLASS(snd_hda_power_pm, pm)(codec); 5040 5041 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5042 5043 if (auto_jack) 5044 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 5045 else 5046 jack_present = 5047 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 5048 5049 if (jack_present) 5050 spec->cur_mic_type = LINE_MIC_IN; 5051 else 5052 spec->cur_mic_type = DIGITAL_MIC; 5053 5054 if (spec->cur_mic_type == DIGITAL_MIC) { 5055 /* enable digital Mic */ 5056 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 5057 ca0132_set_dmic(codec, 1); 5058 ca0132_mic_boost_set(codec, 0); 5059 /* set voice focus */ 5060 ca0132_effects_set(codec, VOICE_FOCUS, 5061 spec->effects_switch 5062 [VOICE_FOCUS - EFFECT_START_NID]); 5063 } else { 5064 /* disable digital Mic */ 5065 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 5066 ca0132_set_dmic(codec, 0); 5067 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 5068 /* disable voice focus */ 5069 ca0132_effects_set(codec, VOICE_FOCUS, 0); 5070 } 5071 5072 return 0; 5073 } 5074 5075 /* 5076 * Select the active input. 5077 * Mic detection isn't used, because it's kind of pointless on the SBZ. 5078 * The front mic has no jack-detection, so the only way to switch to it 5079 * is to do it manually in alsamixer. 5080 */ 5081 static int ca0132_alt_select_in(struct hda_codec *codec) 5082 { 5083 struct ca0132_spec *spec = codec->spec; 5084 unsigned int tmp; 5085 5086 codec_dbg(codec, "%s\n", __func__); 5087 5088 CLASS(snd_hda_power_pm, pm)(codec); 5089 5090 chipio_set_stream_control(codec, 0x03, 0); 5091 chipio_set_stream_control(codec, 0x04, 0); 5092 5093 spec->cur_mic_type = spec->in_enum_val; 5094 5095 switch (spec->cur_mic_type) { 5096 case REAR_MIC: 5097 switch (ca0132_quirk(spec)) { 5098 case QUIRK_SBZ: 5099 case QUIRK_R3D: 5100 ca0113_mmio_gpio_set(codec, 0, false); 5101 tmp = FLOAT_THREE; 5102 break; 5103 case QUIRK_ZXR: 5104 tmp = FLOAT_THREE; 5105 break; 5106 case QUIRK_R3DI: 5107 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5108 tmp = FLOAT_ONE; 5109 break; 5110 case QUIRK_AE5: 5111 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5112 tmp = FLOAT_THREE; 5113 break; 5114 case QUIRK_AE7: 5115 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5116 tmp = FLOAT_THREE; 5117 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5118 SR_96_000); 5119 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5120 SR_96_000); 5121 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5122 break; 5123 default: 5124 tmp = FLOAT_ONE; 5125 break; 5126 } 5127 5128 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5129 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5130 if (ca0132_quirk(spec) == QUIRK_R3DI) 5131 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5132 5133 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5134 5135 chipio_set_stream_control(codec, 0x03, 1); 5136 chipio_set_stream_control(codec, 0x04, 1); 5137 switch (ca0132_quirk(spec)) { 5138 case QUIRK_SBZ: 5139 chipio_write(codec, 0x18B098, 0x0000000C); 5140 chipio_write(codec, 0x18B09C, 0x0000000C); 5141 break; 5142 case QUIRK_ZXR: 5143 chipio_write(codec, 0x18B098, 0x0000000C); 5144 chipio_write(codec, 0x18B09C, 0x000000CC); 5145 break; 5146 case QUIRK_AE5: 5147 chipio_write(codec, 0x18B098, 0x0000000C); 5148 chipio_write(codec, 0x18B09C, 0x0000004C); 5149 break; 5150 default: 5151 break; 5152 } 5153 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5154 break; 5155 case REAR_LINE_IN: 5156 ca0132_mic_boost_set(codec, 0); 5157 switch (ca0132_quirk(spec)) { 5158 case QUIRK_SBZ: 5159 case QUIRK_R3D: 5160 ca0113_mmio_gpio_set(codec, 0, false); 5161 break; 5162 case QUIRK_R3DI: 5163 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5164 break; 5165 case QUIRK_AE5: 5166 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5167 break; 5168 case QUIRK_AE7: 5169 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5170 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5171 SR_96_000); 5172 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5173 SR_96_000); 5174 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5175 break; 5176 default: 5177 break; 5178 } 5179 5180 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5181 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5182 if (ca0132_quirk(spec) == QUIRK_R3DI) 5183 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5184 5185 if (ca0132_quirk(spec) == QUIRK_AE7) 5186 tmp = FLOAT_THREE; 5187 else 5188 tmp = FLOAT_ZERO; 5189 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5190 5191 switch (ca0132_quirk(spec)) { 5192 case QUIRK_SBZ: 5193 case QUIRK_AE5: 5194 chipio_write(codec, 0x18B098, 0x00000000); 5195 chipio_write(codec, 0x18B09C, 0x00000000); 5196 break; 5197 default: 5198 break; 5199 } 5200 chipio_set_stream_control(codec, 0x03, 1); 5201 chipio_set_stream_control(codec, 0x04, 1); 5202 break; 5203 case FRONT_MIC: 5204 switch (ca0132_quirk(spec)) { 5205 case QUIRK_SBZ: 5206 case QUIRK_R3D: 5207 ca0113_mmio_gpio_set(codec, 0, true); 5208 ca0113_mmio_gpio_set(codec, 5, false); 5209 tmp = FLOAT_THREE; 5210 break; 5211 case QUIRK_R3DI: 5212 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5213 tmp = FLOAT_ONE; 5214 break; 5215 case QUIRK_AE5: 5216 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5217 tmp = FLOAT_THREE; 5218 break; 5219 default: 5220 tmp = FLOAT_ONE; 5221 break; 5222 } 5223 5224 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5225 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5226 if (ca0132_quirk(spec) == QUIRK_R3DI) 5227 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5228 5229 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5230 5231 chipio_set_stream_control(codec, 0x03, 1); 5232 chipio_set_stream_control(codec, 0x04, 1); 5233 5234 switch (ca0132_quirk(spec)) { 5235 case QUIRK_SBZ: 5236 chipio_write(codec, 0x18B098, 0x0000000C); 5237 chipio_write(codec, 0x18B09C, 0x000000CC); 5238 break; 5239 case QUIRK_AE5: 5240 chipio_write(codec, 0x18B098, 0x0000000C); 5241 chipio_write(codec, 0x18B09C, 0x0000004C); 5242 break; 5243 default: 5244 break; 5245 } 5246 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5247 break; 5248 } 5249 ca0132_cvoice_switch_set(codec); 5250 5251 return 0; 5252 } 5253 5254 /* 5255 * Check if VNODE settings take effect immediately. 5256 */ 5257 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5258 hda_nid_t vnid, 5259 hda_nid_t *shared_nid) 5260 { 5261 struct ca0132_spec *spec = codec->spec; 5262 hda_nid_t nid; 5263 5264 switch (vnid) { 5265 case VNID_SPK: 5266 nid = spec->shared_out_nid; 5267 break; 5268 case VNID_MIC: 5269 nid = spec->shared_mic_nid; 5270 break; 5271 default: 5272 return false; 5273 } 5274 5275 if (shared_nid) 5276 *shared_nid = nid; 5277 5278 return true; 5279 } 5280 5281 /* 5282 * The following functions are control change helpers. 5283 * They return 0 if no changed. Return 1 if changed. 5284 */ 5285 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5286 { 5287 struct ca0132_spec *spec = codec->spec; 5288 unsigned int tmp; 5289 5290 /* based on CrystalVoice state to enable VoiceFX. */ 5291 if (enable) { 5292 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5293 FLOAT_ONE : FLOAT_ZERO; 5294 } else { 5295 tmp = FLOAT_ZERO; 5296 } 5297 5298 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5299 ca0132_voicefx.reqs[0], tmp); 5300 5301 return 1; 5302 } 5303 5304 /* 5305 * Set the effects parameters 5306 */ 5307 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5308 { 5309 struct ca0132_spec *spec = codec->spec; 5310 unsigned int on, tmp, channel_cfg; 5311 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5312 int err = 0; 5313 int idx = nid - EFFECT_START_NID; 5314 5315 if ((idx < 0) || (idx >= num_fx)) 5316 return 0; /* no changed */ 5317 5318 /* for out effect, qualify with PE */ 5319 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5320 /* if PE if off, turn off out effects. */ 5321 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5322 val = 0; 5323 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5324 channel_cfg = spec->channel_cfg_val; 5325 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5326 channel_cfg != SPEAKER_CHANNELS_4_0) 5327 val = 0; 5328 } 5329 } 5330 5331 /* for in effect, qualify with CrystalVoice */ 5332 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5333 /* if CrystalVoice if off, turn off in effects. */ 5334 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5335 val = 0; 5336 5337 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5338 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5339 val = 0; 5340 5341 /* If Voice Focus on SBZ, set to two channel. */ 5342 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5343 && (spec->cur_mic_type != REAR_LINE_IN)) { 5344 if (spec->effects_switch[CRYSTAL_VOICE - 5345 EFFECT_START_NID]) { 5346 5347 if (spec->effects_switch[VOICE_FOCUS - 5348 EFFECT_START_NID]) { 5349 tmp = FLOAT_TWO; 5350 val = 1; 5351 } else 5352 tmp = FLOAT_ONE; 5353 5354 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5355 } 5356 } 5357 /* 5358 * For SBZ noise reduction, there's an extra command 5359 * to module ID 0x47. No clue why. 5360 */ 5361 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5362 && (spec->cur_mic_type != REAR_LINE_IN)) { 5363 if (spec->effects_switch[CRYSTAL_VOICE - 5364 EFFECT_START_NID]) { 5365 if (spec->effects_switch[NOISE_REDUCTION - 5366 EFFECT_START_NID]) 5367 tmp = FLOAT_ONE; 5368 else 5369 tmp = FLOAT_ZERO; 5370 } else 5371 tmp = FLOAT_ZERO; 5372 5373 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5374 } 5375 5376 /* If rear line in disable effects. */ 5377 if (ca0132_use_alt_functions(spec) && 5378 spec->in_enum_val == REAR_LINE_IN) 5379 val = 0; 5380 } 5381 5382 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5383 nid, val); 5384 5385 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5386 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5387 ca0132_effects[idx].reqs[0], on); 5388 5389 if (err < 0) 5390 return 0; /* no changed */ 5391 5392 return 1; 5393 } 5394 5395 /* 5396 * Turn on/off Playback Enhancements 5397 */ 5398 static int ca0132_pe_switch_set(struct hda_codec *codec) 5399 { 5400 struct ca0132_spec *spec = codec->spec; 5401 hda_nid_t nid; 5402 int i, ret = 0; 5403 5404 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5405 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5406 5407 if (ca0132_use_alt_functions(spec)) 5408 ca0132_alt_select_out(codec); 5409 5410 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5411 nid = OUT_EFFECT_START_NID; 5412 /* PE affects all out effects */ 5413 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5414 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5415 5416 return ret; 5417 } 5418 5419 /* Check if Mic1 is streaming, if so, stop streaming */ 5420 static int stop_mic1(struct hda_codec *codec) 5421 { 5422 struct ca0132_spec *spec = codec->spec; 5423 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5424 AC_VERB_GET_CONV, 0); 5425 if (oldval != 0) 5426 snd_hda_codec_write(codec, spec->adcs[0], 0, 5427 AC_VERB_SET_CHANNEL_STREAMID, 5428 0); 5429 return oldval; 5430 } 5431 5432 /* Resume Mic1 streaming if it was stopped. */ 5433 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5434 { 5435 struct ca0132_spec *spec = codec->spec; 5436 /* Restore the previous stream and channel */ 5437 if (oldval != 0) 5438 snd_hda_codec_write(codec, spec->adcs[0], 0, 5439 AC_VERB_SET_CHANNEL_STREAMID, 5440 oldval); 5441 } 5442 5443 /* 5444 * Turn on/off CrystalVoice 5445 */ 5446 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5447 { 5448 struct ca0132_spec *spec = codec->spec; 5449 hda_nid_t nid; 5450 int i, ret = 0; 5451 unsigned int oldval; 5452 5453 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5454 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5455 5456 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5457 nid = IN_EFFECT_START_NID; 5458 /* CrystalVoice affects all in effects */ 5459 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5460 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5461 5462 /* including VoiceFX */ 5463 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5464 5465 /* set correct vipsource */ 5466 oldval = stop_mic1(codec); 5467 if (ca0132_use_alt_functions(spec)) 5468 ret |= ca0132_alt_set_vipsource(codec, 1); 5469 else 5470 ret |= ca0132_set_vipsource(codec, 1); 5471 resume_mic1(codec, oldval); 5472 return ret; 5473 } 5474 5475 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5476 { 5477 struct ca0132_spec *spec = codec->spec; 5478 int ret = 0; 5479 5480 if (val) /* on */ 5481 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5482 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5483 else /* off */ 5484 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5485 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5486 5487 return ret; 5488 } 5489 5490 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5491 { 5492 struct ca0132_spec *spec = codec->spec; 5493 int ret = 0; 5494 5495 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5496 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5497 return ret; 5498 } 5499 5500 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5501 { 5502 unsigned int i; 5503 5504 for (i = 0; i < 4; i++) 5505 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5506 ae5_headphone_gain_presets[val].vals[i]); 5507 return 0; 5508 } 5509 5510 /* 5511 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5512 * amplifier to handle a 600 ohm load. 5513 */ 5514 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5515 { 5516 ca0113_mmio_gpio_set(codec, 1, val); 5517 5518 return 0; 5519 } 5520 5521 /* 5522 * Manual output selection (HP/Speaker Playback Switch or alt Output Select) 5523 * is meaningful only when HP/Speaker auto-detect is disabled, since the 5524 * select_out path always prefers jack presence when auto-detect is on. When 5525 * the user explicitly chooses an output, turn auto-detect off so the manual 5526 * choice actually takes effect, and notify userspace so the auto-detect 5527 * control reflects the new state. 5528 */ 5529 static void ca0132_disable_hp_auto_detect(struct hda_codec *codec) 5530 { 5531 struct ca0132_spec *spec = codec->spec; 5532 struct snd_kcontrol *kctl; 5533 5534 if (!spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]) 5535 return; 5536 5537 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID] = 0; 5538 kctl = snd_hda_find_mixer_ctl(codec, 5539 "HP/Speaker Auto Detect Playback Switch"); 5540 if (kctl) 5541 snd_ctl_notify(codec->card, SNDRV_CTL_EVENT_MASK_VALUE, 5542 &kctl->id); 5543 } 5544 5545 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5546 struct snd_ctl_elem_value *ucontrol) 5547 { 5548 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5549 hda_nid_t nid = get_amp_nid(kcontrol); 5550 hda_nid_t shared_nid = 0; 5551 bool effective; 5552 int ret = 0; 5553 struct ca0132_spec *spec = codec->spec; 5554 int auto_jack; 5555 5556 if (nid == VNID_HP_SEL) { 5557 ca0132_disable_hp_auto_detect(codec); 5558 if (ca0132_use_alt_functions(spec)) 5559 ca0132_alt_select_out(codec); 5560 else 5561 ca0132_select_out(codec); 5562 return 1; 5563 } 5564 5565 if (nid == VNID_AMIC1_SEL) { 5566 auto_jack = 5567 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5568 if (!auto_jack) 5569 ca0132_select_mic(codec); 5570 return 1; 5571 } 5572 5573 if (nid == VNID_HP_ASEL) { 5574 if (ca0132_use_alt_functions(spec)) 5575 ca0132_alt_select_out(codec); 5576 else 5577 ca0132_select_out(codec); 5578 return 1; 5579 } 5580 5581 if (nid == VNID_AMIC1_ASEL) { 5582 ca0132_select_mic(codec); 5583 return 1; 5584 } 5585 5586 /* if effective conditions, then update hw immediately. */ 5587 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5588 if (effective) { 5589 int dir = get_amp_direction(kcontrol); 5590 int ch = get_amp_channels(kcontrol); 5591 unsigned long pval; 5592 5593 guard(mutex)(&codec->control_mutex); 5594 pval = kcontrol->private_value; 5595 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5596 0, dir); 5597 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5598 kcontrol->private_value = pval; 5599 } 5600 5601 return ret; 5602 } 5603 /* End of control change helpers. */ 5604 5605 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5606 long idx) 5607 { 5608 CLASS(snd_hda_power, pm)(codec); 5609 5610 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5611 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5612 } 5613 5614 /* 5615 * Below I've added controls to mess with the effect levels, I've only enabled 5616 * them on the Sound Blaster Z, but they would probably also work on the 5617 * Chromebook. I figured they were probably tuned specifically for it, and left 5618 * out for a reason. 5619 */ 5620 5621 /* Sets DSP effect level from the sliders above the controls */ 5622 5623 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5624 const unsigned int *lookup, int idx) 5625 { 5626 int i = 0; 5627 unsigned int y; 5628 /* 5629 * For X_BASS, req 2 is actually crossover freq instead of 5630 * effect level 5631 */ 5632 if (nid == X_BASS) 5633 y = 2; 5634 else 5635 y = 1; 5636 5637 CLASS(snd_hda_power, pm)(codec); 5638 if (nid == XBASS_XOVER) { 5639 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5640 if (ca0132_effects[i].nid == X_BASS) 5641 break; 5642 5643 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5644 ca0132_effects[i].reqs[1], 5645 &(lookup[idx - 1]), sizeof(unsigned int)); 5646 } else { 5647 /* Find the actual effect structure */ 5648 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5649 if (nid == ca0132_effects[i].nid) 5650 break; 5651 5652 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5653 ca0132_effects[i].reqs[y], 5654 &(lookup[idx]), sizeof(unsigned int)); 5655 } 5656 5657 return 0; 5658 } 5659 5660 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5661 struct snd_ctl_elem_value *ucontrol) 5662 { 5663 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5664 struct ca0132_spec *spec = codec->spec; 5665 long *valp = ucontrol->value.integer.value; 5666 hda_nid_t nid = get_amp_nid(kcontrol); 5667 5668 if (nid == BASS_REDIRECTION_XOVER) 5669 *valp = spec->bass_redirect_xover_freq; 5670 else 5671 *valp = spec->xbass_xover_freq; 5672 5673 return 0; 5674 } 5675 5676 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5677 struct snd_ctl_elem_value *ucontrol) 5678 { 5679 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5680 struct ca0132_spec *spec = codec->spec; 5681 hda_nid_t nid = get_amp_nid(kcontrol); 5682 long *valp = ucontrol->value.integer.value; 5683 int idx = nid - OUT_EFFECT_START_NID; 5684 5685 *valp = spec->fx_ctl_val[idx]; 5686 return 0; 5687 } 5688 5689 /* 5690 * The X-bass crossover starts at 10hz, so the min is 1. The 5691 * frequency is set in multiples of 10. 5692 */ 5693 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5694 struct snd_ctl_elem_info *uinfo) 5695 { 5696 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5697 uinfo->count = 1; 5698 uinfo->value.integer.min = 1; 5699 uinfo->value.integer.max = 100; 5700 uinfo->value.integer.step = 1; 5701 5702 return 0; 5703 } 5704 5705 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5706 struct snd_ctl_elem_info *uinfo) 5707 { 5708 int chs = get_amp_channels(kcontrol); 5709 5710 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5711 uinfo->count = chs == 3 ? 2 : 1; 5712 uinfo->value.integer.min = 0; 5713 uinfo->value.integer.max = 100; 5714 uinfo->value.integer.step = 1; 5715 5716 return 0; 5717 } 5718 5719 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5720 struct snd_ctl_elem_value *ucontrol) 5721 { 5722 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5723 struct ca0132_spec *spec = codec->spec; 5724 hda_nid_t nid = get_amp_nid(kcontrol); 5725 long *valp = ucontrol->value.integer.value; 5726 long *cur_val; 5727 int idx; 5728 5729 if (nid == BASS_REDIRECTION_XOVER) 5730 cur_val = &spec->bass_redirect_xover_freq; 5731 else 5732 cur_val = &spec->xbass_xover_freq; 5733 5734 /* any change? */ 5735 if (*cur_val == *valp) 5736 return 0; 5737 5738 *cur_val = *valp; 5739 5740 idx = *valp; 5741 if (nid == BASS_REDIRECTION_XOVER) 5742 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5743 else 5744 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5745 5746 return 0; 5747 } 5748 5749 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5750 struct snd_ctl_elem_value *ucontrol) 5751 { 5752 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5753 struct ca0132_spec *spec = codec->spec; 5754 hda_nid_t nid = get_amp_nid(kcontrol); 5755 long *valp = ucontrol->value.integer.value; 5756 int idx; 5757 5758 idx = nid - EFFECT_START_NID; 5759 /* any change? */ 5760 if (spec->fx_ctl_val[idx] == *valp) 5761 return 0; 5762 5763 spec->fx_ctl_val[idx] = *valp; 5764 5765 idx = *valp; 5766 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5767 5768 return 0; 5769 } 5770 5771 5772 /* 5773 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5774 * only has off or full 30 dB, and didn't like making a volume slider that has 5775 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5776 */ 5777 #define MIC_BOOST_NUM_OF_STEPS 4 5778 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5779 5780 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5781 struct snd_ctl_elem_info *uinfo) 5782 { 5783 const char *sfx = "dB"; 5784 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5785 5786 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5787 uinfo->count = 1; 5788 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5789 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5790 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5791 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5792 strscpy(uinfo->value.enumerated.name, namestr); 5793 return 0; 5794 } 5795 5796 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5797 struct snd_ctl_elem_value *ucontrol) 5798 { 5799 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5800 struct ca0132_spec *spec = codec->spec; 5801 5802 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5803 return 0; 5804 } 5805 5806 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5807 struct snd_ctl_elem_value *ucontrol) 5808 { 5809 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5810 struct ca0132_spec *spec = codec->spec; 5811 int sel = ucontrol->value.enumerated.item[0]; 5812 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5813 5814 if (sel >= items) 5815 return 0; 5816 5817 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5818 sel); 5819 5820 spec->mic_boost_enum_val = sel; 5821 5822 if (spec->in_enum_val != REAR_LINE_IN) 5823 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5824 5825 return 1; 5826 } 5827 5828 /* 5829 * Sound BlasterX AE-5 Headphone Gain Controls. 5830 */ 5831 #define AE5_HEADPHONE_GAIN_MAX 3 5832 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5833 struct snd_ctl_elem_info *uinfo) 5834 { 5835 const char *sfx = " Ohms)"; 5836 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5837 5838 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5839 uinfo->count = 1; 5840 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5841 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5842 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5843 sprintf(namestr, "%s %s", 5844 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5845 sfx); 5846 strscpy(uinfo->value.enumerated.name, namestr); 5847 return 0; 5848 } 5849 5850 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5851 struct snd_ctl_elem_value *ucontrol) 5852 { 5853 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5854 struct ca0132_spec *spec = codec->spec; 5855 5856 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5857 return 0; 5858 } 5859 5860 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5861 struct snd_ctl_elem_value *ucontrol) 5862 { 5863 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5864 struct ca0132_spec *spec = codec->spec; 5865 int sel = ucontrol->value.enumerated.item[0]; 5866 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5867 5868 if (sel >= items) 5869 return 0; 5870 5871 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5872 sel); 5873 5874 spec->ae5_headphone_gain_val = sel; 5875 5876 if (spec->out_enum_val == HEADPHONE_OUT) 5877 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5878 5879 return 1; 5880 } 5881 5882 /* 5883 * Sound BlasterX AE-5 sound filter enumerated control. 5884 */ 5885 #define AE5_SOUND_FILTER_MAX 3 5886 5887 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5888 struct snd_ctl_elem_info *uinfo) 5889 { 5890 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5891 5892 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5893 uinfo->count = 1; 5894 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5895 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5896 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5897 sprintf(namestr, "%s", 5898 ae5_filter_presets[uinfo->value.enumerated.item].name); 5899 strscpy(uinfo->value.enumerated.name, namestr); 5900 return 0; 5901 } 5902 5903 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5904 struct snd_ctl_elem_value *ucontrol) 5905 { 5906 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5907 struct ca0132_spec *spec = codec->spec; 5908 5909 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5910 return 0; 5911 } 5912 5913 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5914 struct snd_ctl_elem_value *ucontrol) 5915 { 5916 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5917 struct ca0132_spec *spec = codec->spec; 5918 int sel = ucontrol->value.enumerated.item[0]; 5919 unsigned int items = AE5_SOUND_FILTER_MAX; 5920 5921 if (sel >= items) 5922 return 0; 5923 5924 codec_dbg(codec, "ae5_sound_filter: %s\n", 5925 ae5_filter_presets[sel].name); 5926 5927 spec->ae5_filter_val = sel; 5928 5929 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5930 ae5_filter_presets[sel].val); 5931 5932 return 1; 5933 } 5934 5935 /* 5936 * Input Select Control for alternative ca0132 codecs. This exists because 5937 * front microphone has no auto-detect, and we need a way to set the rear 5938 * as line-in 5939 */ 5940 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5941 struct snd_ctl_elem_info *uinfo) 5942 { 5943 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5944 uinfo->count = 1; 5945 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5946 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5947 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5948 strscpy(uinfo->value.enumerated.name, 5949 in_src_str[uinfo->value.enumerated.item]); 5950 return 0; 5951 } 5952 5953 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5954 struct snd_ctl_elem_value *ucontrol) 5955 { 5956 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5957 struct ca0132_spec *spec = codec->spec; 5958 5959 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5960 return 0; 5961 } 5962 5963 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5964 struct snd_ctl_elem_value *ucontrol) 5965 { 5966 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5967 struct ca0132_spec *spec = codec->spec; 5968 int sel = ucontrol->value.enumerated.item[0]; 5969 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5970 5971 /* 5972 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5973 * line-in. 5974 */ 5975 if (ca0132_quirk(spec) == QUIRK_AE7) 5976 items = 2; 5977 5978 if (sel >= items) 5979 return 0; 5980 5981 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5982 sel, in_src_str[sel]); 5983 5984 spec->in_enum_val = sel; 5985 5986 ca0132_alt_select_in(codec); 5987 5988 return 1; 5989 } 5990 5991 /* Sound Blaster Z Output Select Control */ 5992 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5993 struct snd_ctl_elem_info *uinfo) 5994 { 5995 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5996 uinfo->count = 1; 5997 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5998 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5999 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 6000 strscpy(uinfo->value.enumerated.name, 6001 out_type_str[uinfo->value.enumerated.item]); 6002 return 0; 6003 } 6004 6005 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 6006 struct snd_ctl_elem_value *ucontrol) 6007 { 6008 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6009 struct ca0132_spec *spec = codec->spec; 6010 6011 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 6012 return 0; 6013 } 6014 6015 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 6016 struct snd_ctl_elem_value *ucontrol) 6017 { 6018 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6019 struct ca0132_spec *spec = codec->spec; 6020 int sel = ucontrol->value.enumerated.item[0]; 6021 unsigned int items = NUM_OF_OUTPUTS; 6022 6023 if (sel >= items) 6024 return 0; 6025 6026 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 6027 sel, out_type_str[sel]); 6028 6029 spec->out_enum_val = sel; 6030 6031 ca0132_disable_hp_auto_detect(codec); 6032 ca0132_alt_select_out(codec); 6033 6034 return 1; 6035 } 6036 6037 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 6038 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 6039 struct snd_ctl_elem_info *uinfo) 6040 { 6041 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6042 6043 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6044 uinfo->count = 1; 6045 uinfo->value.enumerated.items = items; 6046 if (uinfo->value.enumerated.item >= items) 6047 uinfo->value.enumerated.item = items - 1; 6048 strscpy(uinfo->value.enumerated.name, 6049 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 6050 return 0; 6051 } 6052 6053 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 6054 struct snd_ctl_elem_value *ucontrol) 6055 { 6056 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6057 struct ca0132_spec *spec = codec->spec; 6058 6059 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 6060 return 0; 6061 } 6062 6063 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 6064 struct snd_ctl_elem_value *ucontrol) 6065 { 6066 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6067 struct ca0132_spec *spec = codec->spec; 6068 int sel = ucontrol->value.enumerated.item[0]; 6069 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6070 6071 if (sel >= items) 6072 return 0; 6073 6074 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 6075 sel, speaker_channel_cfgs[sel].name); 6076 6077 spec->channel_cfg_val = sel; 6078 6079 if (spec->out_enum_val == SPEAKER_OUT) 6080 ca0132_alt_select_out(codec); 6081 6082 return 1; 6083 } 6084 6085 /* 6086 * Smart Volume output setting control. Three different settings, Normal, 6087 * which takes the value from the smart volume slider. The two others, loud 6088 * and night, disregard the slider value and have uneditable values. 6089 */ 6090 #define NUM_OF_SVM_SETTINGS 3 6091 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 6092 6093 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 6094 struct snd_ctl_elem_info *uinfo) 6095 { 6096 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6097 uinfo->count = 1; 6098 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 6099 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 6100 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 6101 strscpy(uinfo->value.enumerated.name, 6102 out_svm_set_enum_str[uinfo->value.enumerated.item]); 6103 return 0; 6104 } 6105 6106 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 6107 struct snd_ctl_elem_value *ucontrol) 6108 { 6109 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6110 struct ca0132_spec *spec = codec->spec; 6111 6112 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 6113 return 0; 6114 } 6115 6116 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 6117 struct snd_ctl_elem_value *ucontrol) 6118 { 6119 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6120 struct ca0132_spec *spec = codec->spec; 6121 int sel = ucontrol->value.enumerated.item[0]; 6122 unsigned int items = NUM_OF_SVM_SETTINGS; 6123 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6124 unsigned int tmp; 6125 6126 if (sel >= items) 6127 return 0; 6128 6129 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6130 sel, out_svm_set_enum_str[sel]); 6131 6132 spec->smart_volume_setting = sel; 6133 6134 switch (sel) { 6135 case 0: 6136 tmp = FLOAT_ZERO; 6137 break; 6138 case 1: 6139 tmp = FLOAT_ONE; 6140 break; 6141 case 2: 6142 tmp = FLOAT_TWO; 6143 break; 6144 default: 6145 tmp = FLOAT_ZERO; 6146 break; 6147 } 6148 /* Req 2 is the Smart Volume Setting req. */ 6149 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6150 ca0132_effects[idx].reqs[2], tmp); 6151 return 1; 6152 } 6153 6154 /* Sound Blaster Z EQ preset controls */ 6155 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6156 struct snd_ctl_elem_info *uinfo) 6157 { 6158 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6159 6160 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6161 uinfo->count = 1; 6162 uinfo->value.enumerated.items = items; 6163 if (uinfo->value.enumerated.item >= items) 6164 uinfo->value.enumerated.item = items - 1; 6165 strscpy(uinfo->value.enumerated.name, 6166 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6167 return 0; 6168 } 6169 6170 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6171 struct snd_ctl_elem_value *ucontrol) 6172 { 6173 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6174 struct ca0132_spec *spec = codec->spec; 6175 6176 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6177 return 0; 6178 } 6179 6180 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6181 struct snd_ctl_elem_value *ucontrol) 6182 { 6183 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6184 struct ca0132_spec *spec = codec->spec; 6185 int i, err = 0; 6186 int sel = ucontrol->value.enumerated.item[0]; 6187 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6188 6189 if (sel >= items) 6190 return 0; 6191 6192 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6193 ca0132_alt_eq_presets[sel].name); 6194 /* 6195 * Idx 0 is default. 6196 * Default needs to qualify with CrystalVoice state. 6197 */ 6198 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6199 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6200 ca0132_alt_eq_enum.reqs[i], 6201 ca0132_alt_eq_presets[sel].vals[i]); 6202 if (err < 0) 6203 break; 6204 } 6205 6206 if (err >= 0) 6207 spec->eq_preset_val = sel; 6208 6209 return 1; 6210 } 6211 6212 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6213 struct snd_ctl_elem_info *uinfo) 6214 { 6215 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6216 6217 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6218 uinfo->count = 1; 6219 uinfo->value.enumerated.items = items; 6220 if (uinfo->value.enumerated.item >= items) 6221 uinfo->value.enumerated.item = items - 1; 6222 strscpy(uinfo->value.enumerated.name, 6223 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6224 return 0; 6225 } 6226 6227 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6228 struct snd_ctl_elem_value *ucontrol) 6229 { 6230 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6231 struct ca0132_spec *spec = codec->spec; 6232 6233 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6234 return 0; 6235 } 6236 6237 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6238 struct snd_ctl_elem_value *ucontrol) 6239 { 6240 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6241 struct ca0132_spec *spec = codec->spec; 6242 int i, err = 0; 6243 int sel = ucontrol->value.enumerated.item[0]; 6244 6245 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6246 return 0; 6247 6248 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6249 sel, ca0132_voicefx_presets[sel].name); 6250 6251 /* 6252 * Idx 0 is default. 6253 * Default needs to qualify with CrystalVoice state. 6254 */ 6255 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6256 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6257 ca0132_voicefx.reqs[i], 6258 ca0132_voicefx_presets[sel].vals[i]); 6259 if (err < 0) 6260 break; 6261 } 6262 6263 if (err >= 0) { 6264 spec->voicefx_val = sel; 6265 /* enable voice fx */ 6266 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6267 } 6268 6269 return 1; 6270 } 6271 6272 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6273 struct snd_ctl_elem_value *ucontrol) 6274 { 6275 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6276 struct ca0132_spec *spec = codec->spec; 6277 hda_nid_t nid = get_amp_nid(kcontrol); 6278 int ch = get_amp_channels(kcontrol); 6279 long *valp = ucontrol->value.integer.value; 6280 6281 /* vnode */ 6282 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6283 if (ch & 1) { 6284 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6285 valp++; 6286 } 6287 if (ch & 2) { 6288 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6289 valp++; 6290 } 6291 return 0; 6292 } 6293 6294 /* effects, include PE and CrystalVoice */ 6295 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6296 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6297 return 0; 6298 } 6299 6300 /* mic boost */ 6301 if (nid == spec->input_pins[0]) { 6302 *valp = spec->cur_mic_boost; 6303 return 0; 6304 } 6305 6306 if (nid == ZXR_HEADPHONE_GAIN) { 6307 *valp = spec->zxr_gain_set; 6308 return 0; 6309 } 6310 6311 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6312 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6313 return 0; 6314 } 6315 6316 if (nid == BASS_REDIRECTION) { 6317 *valp = spec->bass_redirection_val; 6318 return 0; 6319 } 6320 6321 return 0; 6322 } 6323 6324 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6325 struct snd_ctl_elem_value *ucontrol) 6326 { 6327 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6328 struct ca0132_spec *spec = codec->spec; 6329 hda_nid_t nid = get_amp_nid(kcontrol); 6330 int ch = get_amp_channels(kcontrol); 6331 long *valp = ucontrol->value.integer.value; 6332 6333 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6334 nid, *valp); 6335 6336 CLASS(snd_hda_power, pm)(codec); 6337 /* vnode */ 6338 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6339 if (ch & 1) { 6340 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6341 valp++; 6342 } 6343 if (ch & 2) { 6344 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6345 valp++; 6346 } 6347 return ca0132_vnode_switch_set(kcontrol, ucontrol); 6348 } 6349 6350 /* PE */ 6351 if (nid == PLAY_ENHANCEMENT) { 6352 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6353 return ca0132_pe_switch_set(codec); 6354 } 6355 6356 /* CrystalVoice */ 6357 if (nid == CRYSTAL_VOICE) { 6358 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6359 return ca0132_cvoice_switch_set(codec); 6360 } 6361 6362 /* out and in effects */ 6363 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6364 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6365 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6366 return ca0132_effects_set(codec, nid, *valp); 6367 } 6368 6369 /* mic boost */ 6370 if (nid == spec->input_pins[0]) { 6371 spec->cur_mic_boost = *valp; 6372 if (ca0132_use_alt_functions(spec)) { 6373 if (spec->in_enum_val != REAR_LINE_IN) 6374 return ca0132_mic_boost_set(codec, *valp); 6375 } else { 6376 /* Mic boost does not apply to Digital Mic */ 6377 if (spec->cur_mic_type != DIGITAL_MIC) 6378 return ca0132_mic_boost_set(codec, *valp); 6379 } 6380 6381 return 1; 6382 } 6383 6384 if (nid == ZXR_HEADPHONE_GAIN) { 6385 spec->zxr_gain_set = *valp; 6386 if (spec->cur_out_type == HEADPHONE_OUT) 6387 return zxr_headphone_gain_set(codec, *valp); 6388 else 6389 return 0; 6390 } 6391 6392 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6393 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6394 if (spec->cur_out_type == SPEAKER_OUT) 6395 ca0132_alt_set_full_range_speaker(codec); 6396 6397 return 0; 6398 } 6399 6400 if (nid == BASS_REDIRECTION) { 6401 spec->bass_redirection_val = *valp; 6402 if (spec->cur_out_type == SPEAKER_OUT) 6403 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6404 6405 return 0; 6406 } 6407 6408 return 1; 6409 } 6410 6411 /* 6412 * Volume related 6413 */ 6414 /* 6415 * Sets the internal DSP decibel level to match the DAC for output, and the 6416 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6417 * all alternative codecs set DSP playback volume. 6418 */ 6419 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6420 { 6421 struct ca0132_spec *spec = codec->spec; 6422 unsigned int dsp_dir; 6423 unsigned int lookup_val; 6424 6425 if (nid == VNID_SPK) 6426 dsp_dir = DSP_VOL_OUT; 6427 else 6428 dsp_dir = DSP_VOL_IN; 6429 6430 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6431 6432 dspio_set_uint_param(codec, 6433 ca0132_alt_vol_ctls[dsp_dir].mid, 6434 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6435 float_vol_db_lookup[lookup_val]); 6436 6437 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6438 6439 dspio_set_uint_param(codec, 6440 ca0132_alt_vol_ctls[dsp_dir].mid, 6441 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6442 float_vol_db_lookup[lookup_val]); 6443 6444 dspio_set_uint_param(codec, 6445 ca0132_alt_vol_ctls[dsp_dir].mid, 6446 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6447 } 6448 6449 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6450 struct snd_ctl_elem_info *uinfo) 6451 { 6452 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6453 struct ca0132_spec *spec = codec->spec; 6454 hda_nid_t nid = get_amp_nid(kcontrol); 6455 int ch = get_amp_channels(kcontrol); 6456 int dir = get_amp_direction(kcontrol); 6457 unsigned long pval; 6458 int err; 6459 6460 switch (nid) { 6461 case VNID_SPK: 6462 /* follow shared_out info */ 6463 nid = spec->shared_out_nid; 6464 scoped_guard(mutex, &codec->control_mutex) { 6465 pval = kcontrol->private_value; 6466 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6467 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6468 kcontrol->private_value = pval; 6469 } 6470 break; 6471 case VNID_MIC: 6472 /* follow shared_mic info */ 6473 nid = spec->shared_mic_nid; 6474 scoped_guard(mutex, &codec->control_mutex) { 6475 pval = kcontrol->private_value; 6476 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6477 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6478 kcontrol->private_value = pval; 6479 } 6480 break; 6481 default: 6482 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6483 } 6484 return err; 6485 } 6486 6487 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6488 struct snd_ctl_elem_value *ucontrol) 6489 { 6490 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6491 struct ca0132_spec *spec = codec->spec; 6492 hda_nid_t nid = get_amp_nid(kcontrol); 6493 int ch = get_amp_channels(kcontrol); 6494 long *valp = ucontrol->value.integer.value; 6495 6496 /* store the left and right volume */ 6497 if (ch & 1) { 6498 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6499 valp++; 6500 } 6501 if (ch & 2) { 6502 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6503 valp++; 6504 } 6505 return 0; 6506 } 6507 6508 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6509 struct snd_ctl_elem_value *ucontrol) 6510 { 6511 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6512 struct ca0132_spec *spec = codec->spec; 6513 hda_nid_t nid = get_amp_nid(kcontrol); 6514 int ch = get_amp_channels(kcontrol); 6515 long *valp = ucontrol->value.integer.value; 6516 hda_nid_t shared_nid = 0; 6517 bool effective; 6518 int changed = 1; 6519 6520 /* store the left and right volume */ 6521 if (ch & 1) { 6522 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6523 valp++; 6524 } 6525 if (ch & 2) { 6526 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6527 valp++; 6528 } 6529 6530 /* if effective conditions, then update hw immediately. */ 6531 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6532 if (effective) { 6533 int dir = get_amp_direction(kcontrol); 6534 unsigned long pval; 6535 6536 CLASS(snd_hda_power, pm)(codec); 6537 guard(mutex)(&codec->control_mutex); 6538 pval = kcontrol->private_value; 6539 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6540 0, dir); 6541 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6542 kcontrol->private_value = pval; 6543 } 6544 6545 return changed; 6546 } 6547 6548 /* 6549 * This function is the same as the one above, because using an if statement 6550 * inside of the above volume control for the DSP volume would cause too much 6551 * lag. This is a lot more smooth. 6552 */ 6553 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6554 struct snd_ctl_elem_value *ucontrol) 6555 { 6556 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6557 struct ca0132_spec *spec = codec->spec; 6558 hda_nid_t nid = get_amp_nid(kcontrol); 6559 int ch = get_amp_channels(kcontrol); 6560 long *valp = ucontrol->value.integer.value; 6561 hda_nid_t vnid = 0; 6562 6563 switch (nid) { 6564 case 0x02: 6565 vnid = VNID_SPK; 6566 break; 6567 case 0x07: 6568 vnid = VNID_MIC; 6569 break; 6570 } 6571 6572 /* store the left and right volume */ 6573 if (ch & 1) { 6574 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6575 valp++; 6576 } 6577 if (ch & 2) { 6578 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6579 valp++; 6580 } 6581 6582 CLASS(snd_hda_power, pm)(codec); 6583 ca0132_alt_dsp_volume_put(codec, vnid); 6584 guard(mutex)(&codec->control_mutex); 6585 return snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6586 } 6587 6588 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6589 unsigned int size, unsigned int __user *tlv) 6590 { 6591 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6592 struct ca0132_spec *spec = codec->spec; 6593 hda_nid_t nid = get_amp_nid(kcontrol); 6594 int ch = get_amp_channels(kcontrol); 6595 int dir = get_amp_direction(kcontrol); 6596 unsigned long pval; 6597 int err; 6598 6599 switch (nid) { 6600 case VNID_SPK: 6601 /* follow shared_out tlv */ 6602 nid = spec->shared_out_nid; 6603 scoped_guard(mutex, &codec->control_mutex) { 6604 pval = kcontrol->private_value; 6605 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6606 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6607 kcontrol->private_value = pval; 6608 } 6609 break; 6610 case VNID_MIC: 6611 /* follow shared_mic tlv */ 6612 nid = spec->shared_mic_nid; 6613 scoped_guard(mutex, &codec->control_mutex) { 6614 pval = kcontrol->private_value; 6615 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6616 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6617 kcontrol->private_value = pval; 6618 } 6619 break; 6620 default: 6621 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6622 } 6623 return err; 6624 } 6625 6626 /* Add volume slider control for effect level */ 6627 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6628 const char *pfx, int dir) 6629 { 6630 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6631 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6632 struct snd_kcontrol_new knew = 6633 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6634 6635 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6636 6637 knew.tlv.c = NULL; 6638 6639 switch (nid) { 6640 case XBASS_XOVER: 6641 knew.info = ca0132_alt_xbass_xover_slider_info; 6642 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6643 knew.put = ca0132_alt_xbass_xover_slider_put; 6644 break; 6645 default: 6646 knew.info = ca0132_alt_effect_slider_info; 6647 knew.get = ca0132_alt_slider_ctl_get; 6648 knew.put = ca0132_alt_effect_slider_put; 6649 knew.private_value = 6650 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6651 break; 6652 } 6653 6654 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6655 } 6656 6657 /* 6658 * Added FX: prefix for the alternative codecs, because otherwise the surround 6659 * effect would conflict with the Surround sound volume control. Also seems more 6660 * clear as to what the switches do. Left alone for others. 6661 */ 6662 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6663 const char *pfx, int dir) 6664 { 6665 struct ca0132_spec *spec = codec->spec; 6666 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6667 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6668 struct snd_kcontrol_new knew = 6669 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6670 /* If using alt_controls, add FX: prefix. But, don't add FX: 6671 * prefix to OutFX or InFX enable controls. 6672 */ 6673 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6674 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6675 else 6676 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6677 6678 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6679 } 6680 6681 static int add_voicefx(struct hda_codec *codec) 6682 { 6683 struct snd_kcontrol_new knew = 6684 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6685 VOICEFX, 1, 0, HDA_INPUT); 6686 knew.info = ca0132_voicefx_info; 6687 knew.get = ca0132_voicefx_get; 6688 knew.put = ca0132_voicefx_put; 6689 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6690 } 6691 6692 /* Create the EQ Preset control */ 6693 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6694 { 6695 struct snd_kcontrol_new knew = 6696 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6697 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6698 knew.info = ca0132_alt_eq_preset_info; 6699 knew.get = ca0132_alt_eq_preset_get; 6700 knew.put = ca0132_alt_eq_preset_put; 6701 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6702 snd_ctl_new1(&knew, codec)); 6703 } 6704 6705 /* 6706 * Add enumerated control for the three different settings of the smart volume 6707 * output effect. Normal just uses the slider value, and loud and night are 6708 * their own things that ignore that value. 6709 */ 6710 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6711 { 6712 struct snd_kcontrol_new knew = 6713 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6714 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6715 knew.info = ca0132_alt_svm_setting_info; 6716 knew.get = ca0132_alt_svm_setting_get; 6717 knew.put = ca0132_alt_svm_setting_put; 6718 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6719 snd_ctl_new1(&knew, codec)); 6720 6721 } 6722 6723 /* 6724 * Create an Output Select enumerated control for codecs with surround 6725 * out capabilities. 6726 */ 6727 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6728 { 6729 struct snd_kcontrol_new knew = 6730 HDA_CODEC_MUTE_MONO("Output Select", 6731 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6732 knew.info = ca0132_alt_output_select_get_info; 6733 knew.get = ca0132_alt_output_select_get; 6734 knew.put = ca0132_alt_output_select_put; 6735 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6736 snd_ctl_new1(&knew, codec)); 6737 } 6738 6739 /* 6740 * Add a control for selecting channel count on speaker output. Setting this 6741 * allows the DSP to do bass redirection and channel upmixing on surround 6742 * configurations. 6743 */ 6744 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6745 { 6746 struct snd_kcontrol_new knew = 6747 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6748 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6749 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6750 knew.get = ca0132_alt_speaker_channel_cfg_get; 6751 knew.put = ca0132_alt_speaker_channel_cfg_put; 6752 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6753 snd_ctl_new1(&knew, codec)); 6754 } 6755 6756 /* 6757 * Full range front stereo and rear surround switches. When these are set to 6758 * full range, the lower frequencies from these channels are no longer 6759 * redirected to the LFE channel. 6760 */ 6761 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6762 { 6763 struct snd_kcontrol_new knew = 6764 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6765 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6766 6767 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6768 snd_ctl_new1(&knew, codec)); 6769 } 6770 6771 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6772 { 6773 struct snd_kcontrol_new knew = 6774 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6775 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6776 6777 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6778 snd_ctl_new1(&knew, codec)); 6779 } 6780 6781 /* 6782 * Bass redirection redirects audio below the crossover frequency to the LFE 6783 * channel on speakers that are set as not being full-range. On configurations 6784 * without an LFE channel, it does nothing. Bass redirection seems to be the 6785 * replacement for X-Bass on configurations with an LFE channel. 6786 */ 6787 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6788 { 6789 const char *namestr = "Bass Redirection Crossover"; 6790 struct snd_kcontrol_new knew = 6791 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6792 HDA_OUTPUT); 6793 6794 knew.tlv.c = NULL; 6795 knew.info = ca0132_alt_xbass_xover_slider_info; 6796 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6797 knew.put = ca0132_alt_xbass_xover_slider_put; 6798 6799 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6800 snd_ctl_new1(&knew, codec)); 6801 } 6802 6803 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6804 { 6805 const char *namestr = "Bass Redirection"; 6806 struct snd_kcontrol_new knew = 6807 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6808 HDA_OUTPUT); 6809 6810 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6811 snd_ctl_new1(&knew, codec)); 6812 } 6813 6814 /* 6815 * Create an Input Source enumerated control for the alternate ca0132 codecs 6816 * because the front microphone has no auto-detect, and Line-in has to be set 6817 * somehow. 6818 */ 6819 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6820 { 6821 struct snd_kcontrol_new knew = 6822 HDA_CODEC_MUTE_MONO("Input Source", 6823 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6824 knew.info = ca0132_alt_input_source_info; 6825 knew.get = ca0132_alt_input_source_get; 6826 knew.put = ca0132_alt_input_source_put; 6827 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6828 snd_ctl_new1(&knew, codec)); 6829 } 6830 6831 /* 6832 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6833 * more control than the original mic boost, which is either full 30dB or off. 6834 */ 6835 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6836 { 6837 struct snd_kcontrol_new knew = 6838 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6839 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6840 knew.info = ca0132_alt_mic_boost_info; 6841 knew.get = ca0132_alt_mic_boost_get; 6842 knew.put = ca0132_alt_mic_boost_put; 6843 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6844 snd_ctl_new1(&knew, codec)); 6845 6846 } 6847 6848 /* 6849 * Add headphone gain enumerated control for the AE-5. This switches between 6850 * three modes, low, medium, and high. When non-headphone outputs are selected, 6851 * it is automatically set to high. This is the same behavior as Windows. 6852 */ 6853 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6854 { 6855 struct snd_kcontrol_new knew = 6856 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6857 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6858 knew.info = ae5_headphone_gain_info; 6859 knew.get = ae5_headphone_gain_get; 6860 knew.put = ae5_headphone_gain_put; 6861 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6862 snd_ctl_new1(&knew, codec)); 6863 } 6864 6865 /* 6866 * Add sound filter enumerated control for the AE-5. This adds three different 6867 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6868 * read into it, it changes the DAC's interpolation filter. 6869 */ 6870 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6871 { 6872 struct snd_kcontrol_new knew = 6873 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6874 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6875 knew.info = ae5_sound_filter_info; 6876 knew.get = ae5_sound_filter_get; 6877 knew.put = ae5_sound_filter_put; 6878 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6879 snd_ctl_new1(&knew, codec)); 6880 } 6881 6882 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6883 { 6884 struct snd_kcontrol_new knew = 6885 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6886 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6887 6888 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6889 snd_ctl_new1(&knew, codec)); 6890 } 6891 6892 /* 6893 * Need to create follower controls for the alternate codecs that have surround 6894 * capabilities. 6895 */ 6896 static const char * const ca0132_alt_follower_pfxs[] = { 6897 "Front", "Surround", "Center", "LFE", NULL, 6898 }; 6899 6900 /* 6901 * Also need special channel map, because the default one is incorrect. 6902 * I think this has to do with the pin for rear surround being 0x11, 6903 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6904 */ 6905 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6906 { .channels = 2, 6907 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6908 { .channels = 4, 6909 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6910 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6911 { .channels = 6, 6912 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6913 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6914 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6915 { } 6916 }; 6917 6918 /* Add the correct chmap for streams with 6 channels. */ 6919 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6920 { 6921 int err = 0; 6922 struct hda_pcm *pcm; 6923 6924 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6925 struct hda_pcm_stream *hinfo = 6926 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6927 struct snd_pcm_chmap *chmap; 6928 const struct snd_pcm_chmap_elem *elem; 6929 6930 elem = ca0132_alt_chmaps; 6931 if (hinfo->channels_max == 6) { 6932 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6933 SNDRV_PCM_STREAM_PLAYBACK, 6934 elem, hinfo->channels_max, 0, &chmap); 6935 if (err < 0) 6936 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6937 } 6938 } 6939 } 6940 6941 /* 6942 * When changing Node IDs for Mixer Controls below, make sure to update 6943 * Node IDs in ca0132_config() as well. 6944 */ 6945 static const struct snd_kcontrol_new ca0132_mixer[] = { 6946 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6947 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6948 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6949 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6950 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6951 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6952 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6953 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6954 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6955 0x12, 1, HDA_INPUT), 6956 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6957 VNID_HP_SEL, 1, HDA_OUTPUT), 6958 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6959 VNID_AMIC1_SEL, 1, HDA_INPUT), 6960 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6961 VNID_HP_ASEL, 1, HDA_OUTPUT), 6962 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6963 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6964 { } /* end */ 6965 }; 6966 6967 /* 6968 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6969 * surround controls. Also sets both the Front Playback and Capture Volume 6970 * controls to alt so they set the DSP's decibel level. 6971 */ 6972 static const struct snd_kcontrol_new desktop_mixer[] = { 6973 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6974 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6975 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6976 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6977 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6978 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6979 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6980 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6981 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6982 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6983 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6984 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6985 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6986 VNID_HP_ASEL, 1, HDA_OUTPUT), 6987 { } /* end */ 6988 }; 6989 6990 /* 6991 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6992 * because it doesn't set decibel levels for the DSP for capture. 6993 */ 6994 static const struct snd_kcontrol_new r3di_mixer[] = { 6995 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6996 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6997 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6998 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6999 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 7000 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 7001 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 7002 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 7003 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 7004 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 7005 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 7006 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 7007 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 7008 VNID_HP_ASEL, 1, HDA_OUTPUT), 7009 { } /* end */ 7010 }; 7011 7012 static int ca0132_build_controls(struct hda_codec *codec) 7013 { 7014 struct ca0132_spec *spec = codec->spec; 7015 int i, num_fx, num_sliders; 7016 int err = 0; 7017 7018 /* Add Mixer controls */ 7019 for (i = 0; i < spec->num_mixers; i++) { 7020 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 7021 if (err < 0) 7022 return err; 7023 } 7024 /* Setup vmaster with surround followers for desktop ca0132 devices */ 7025 if (ca0132_use_alt_functions(spec)) { 7026 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 7027 spec->tlv); 7028 snd_hda_add_vmaster(codec, "Master Playback Volume", 7029 spec->tlv, ca0132_alt_follower_pfxs, 7030 "Playback Volume", 0); 7031 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 7032 NULL, ca0132_alt_follower_pfxs, 7033 "Playback Switch", 7034 true, 0, &spec->vmaster_mute.sw_kctl); 7035 if (err < 0) 7036 return err; 7037 } 7038 7039 /* Add in and out effects controls. 7040 * VoiceFX, PE and CrystalVoice are added separately. 7041 */ 7042 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7043 for (i = 0; i < num_fx; i++) { 7044 /* Desktop cards break if Echo Cancellation is used. */ 7045 if (ca0132_use_pci_mmio(spec)) { 7046 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 7047 OUT_EFFECTS_COUNT)) 7048 continue; 7049 } 7050 7051 err = add_fx_switch(codec, ca0132_effects[i].nid, 7052 ca0132_effects[i].name, 7053 ca0132_effects[i].direct); 7054 if (err < 0) 7055 return err; 7056 } 7057 /* 7058 * If codec has use_alt_controls set to true, add effect level sliders, 7059 * EQ presets, and Smart Volume presets. Also, change names to add FX 7060 * prefix, and change PlayEnhancement and CrystalVoice to match. 7061 */ 7062 if (ca0132_use_alt_controls(spec)) { 7063 err = ca0132_alt_add_svm_enum(codec); 7064 if (err < 0) 7065 return err; 7066 7067 err = add_ca0132_alt_eq_presets(codec); 7068 if (err < 0) 7069 return err; 7070 7071 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7072 "Enable OutFX", 0); 7073 if (err < 0) 7074 return err; 7075 7076 err = add_fx_switch(codec, CRYSTAL_VOICE, 7077 "Enable InFX", 1); 7078 if (err < 0) 7079 return err; 7080 7081 num_sliders = OUT_EFFECTS_COUNT - 1; 7082 for (i = 0; i < num_sliders; i++) { 7083 err = ca0132_alt_add_effect_slider(codec, 7084 ca0132_effects[i].nid, 7085 ca0132_effects[i].name, 7086 ca0132_effects[i].direct); 7087 if (err < 0) 7088 return err; 7089 } 7090 7091 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 7092 "X-Bass Crossover", EFX_DIR_OUT); 7093 7094 if (err < 0) 7095 return err; 7096 } else { 7097 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7098 "PlayEnhancement", 0); 7099 if (err < 0) 7100 return err; 7101 7102 err = add_fx_switch(codec, CRYSTAL_VOICE, 7103 "CrystalVoice", 1); 7104 if (err < 0) 7105 return err; 7106 } 7107 err = add_voicefx(codec); 7108 if (err < 0) 7109 return err; 7110 7111 /* 7112 * If the codec uses alt_functions, you need the enumerated controls 7113 * to select the new outputs and inputs, plus add the new mic boost 7114 * setting control. 7115 */ 7116 if (ca0132_use_alt_functions(spec)) { 7117 err = ca0132_alt_add_output_enum(codec); 7118 if (err < 0) 7119 return err; 7120 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7121 if (err < 0) 7122 return err; 7123 err = ca0132_alt_add_front_full_range_switch(codec); 7124 if (err < 0) 7125 return err; 7126 err = ca0132_alt_add_rear_full_range_switch(codec); 7127 if (err < 0) 7128 return err; 7129 err = ca0132_alt_add_bass_redirection_crossover(codec); 7130 if (err < 0) 7131 return err; 7132 err = ca0132_alt_add_bass_redirection_switch(codec); 7133 if (err < 0) 7134 return err; 7135 err = ca0132_alt_add_mic_boost_enum(codec); 7136 if (err < 0) 7137 return err; 7138 /* 7139 * ZxR only has microphone input, there is no front panel 7140 * header on the card, and aux-in is handled by the DBPro board. 7141 */ 7142 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7143 err = ca0132_alt_add_input_enum(codec); 7144 if (err < 0) 7145 return err; 7146 } 7147 } 7148 7149 switch (ca0132_quirk(spec)) { 7150 case QUIRK_AE5: 7151 case QUIRK_AE7: 7152 err = ae5_add_headphone_gain_enum(codec); 7153 if (err < 0) 7154 return err; 7155 err = ae5_add_sound_filter_enum(codec); 7156 if (err < 0) 7157 return err; 7158 break; 7159 case QUIRK_ZXR: 7160 err = zxr_add_headphone_gain_switch(codec); 7161 if (err < 0) 7162 return err; 7163 break; 7164 default: 7165 break; 7166 } 7167 7168 #ifdef ENABLE_TUNING_CONTROLS 7169 add_tuning_ctls(codec); 7170 #endif 7171 7172 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7173 if (err < 0) 7174 return err; 7175 7176 if (spec->dig_out) { 7177 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7178 spec->dig_out); 7179 if (err < 0) 7180 return err; 7181 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7182 if (err < 0) 7183 return err; 7184 /* spec->multiout.share_spdif = 1; */ 7185 } 7186 7187 if (spec->dig_in) { 7188 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7189 if (err < 0) 7190 return err; 7191 } 7192 7193 if (ca0132_use_alt_functions(spec)) 7194 ca0132_alt_add_chmap_ctls(codec); 7195 7196 return 0; 7197 } 7198 7199 static int dbpro_build_controls(struct hda_codec *codec) 7200 { 7201 struct ca0132_spec *spec = codec->spec; 7202 int err = 0; 7203 7204 if (spec->dig_out) { 7205 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7206 spec->dig_out); 7207 if (err < 0) 7208 return err; 7209 } 7210 7211 if (spec->dig_in) { 7212 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7213 if (err < 0) 7214 return err; 7215 } 7216 7217 return 0; 7218 } 7219 7220 /* 7221 * PCM 7222 */ 7223 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7224 .substreams = 1, 7225 .channels_min = 2, 7226 .channels_max = 6, 7227 .ops = { 7228 .prepare = ca0132_playback_pcm_prepare, 7229 .cleanup = ca0132_playback_pcm_cleanup, 7230 .get_delay = ca0132_playback_pcm_delay, 7231 }, 7232 }; 7233 7234 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7235 .substreams = 1, 7236 .channels_min = 2, 7237 .channels_max = 2, 7238 .ops = { 7239 .prepare = ca0132_capture_pcm_prepare, 7240 .cleanup = ca0132_capture_pcm_cleanup, 7241 .get_delay = ca0132_capture_pcm_delay, 7242 }, 7243 }; 7244 7245 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7246 .substreams = 1, 7247 .channels_min = 2, 7248 .channels_max = 2, 7249 .ops = { 7250 .open = ca0132_dig_playback_pcm_open, 7251 .close = ca0132_dig_playback_pcm_close, 7252 .prepare = ca0132_dig_playback_pcm_prepare, 7253 .cleanup = ca0132_dig_playback_pcm_cleanup 7254 }, 7255 }; 7256 7257 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7258 .substreams = 1, 7259 .channels_min = 2, 7260 .channels_max = 2, 7261 }; 7262 7263 static int ca0132_build_pcms(struct hda_codec *codec) 7264 { 7265 struct ca0132_spec *spec = codec->spec; 7266 struct hda_pcm *info; 7267 7268 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7269 if (!info) 7270 return -ENOMEM; 7271 if (ca0132_use_alt_functions(spec)) { 7272 info->own_chmap = true; 7273 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7274 = ca0132_alt_chmaps; 7275 } 7276 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7277 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7278 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7279 spec->multiout.max_channels; 7280 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7281 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7282 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7283 7284 /* With the DSP enabled, desktops don't use this ADC. */ 7285 if (!ca0132_use_alt_functions(spec)) { 7286 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7287 if (!info) 7288 return -ENOMEM; 7289 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7290 ca0132_pcm_analog_capture; 7291 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7292 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7293 } 7294 7295 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7296 if (!info) 7297 return -ENOMEM; 7298 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7299 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7300 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7301 7302 if (!spec->dig_out && !spec->dig_in) 7303 return 0; 7304 7305 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7306 if (!info) 7307 return -ENOMEM; 7308 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7309 if (spec->dig_out) { 7310 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7311 ca0132_pcm_digital_playback; 7312 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7313 } 7314 if (spec->dig_in) { 7315 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7316 ca0132_pcm_digital_capture; 7317 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7318 } 7319 7320 return 0; 7321 } 7322 7323 static int dbpro_build_pcms(struct hda_codec *codec) 7324 { 7325 struct ca0132_spec *spec = codec->spec; 7326 struct hda_pcm *info; 7327 7328 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7329 if (!info) 7330 return -ENOMEM; 7331 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7332 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7333 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7334 7335 7336 if (!spec->dig_out && !spec->dig_in) 7337 return 0; 7338 7339 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7340 if (!info) 7341 return -ENOMEM; 7342 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7343 if (spec->dig_out) { 7344 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7345 ca0132_pcm_digital_playback; 7346 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7347 } 7348 if (spec->dig_in) { 7349 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7350 ca0132_pcm_digital_capture; 7351 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7352 } 7353 7354 return 0; 7355 } 7356 7357 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7358 { 7359 if (pin) { 7360 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7361 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7362 snd_hda_codec_write(codec, pin, 0, 7363 AC_VERB_SET_AMP_GAIN_MUTE, 7364 AMP_OUT_UNMUTE); 7365 } 7366 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7367 snd_hda_codec_write(codec, dac, 0, 7368 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7369 } 7370 7371 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7372 { 7373 if (pin) { 7374 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7375 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7376 snd_hda_codec_write(codec, pin, 0, 7377 AC_VERB_SET_AMP_GAIN_MUTE, 7378 AMP_IN_UNMUTE(0)); 7379 } 7380 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7381 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7382 AMP_IN_UNMUTE(0)); 7383 7384 /* init to 0 dB and unmute. */ 7385 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7386 HDA_AMP_VOLMASK, 0x5a); 7387 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7388 HDA_AMP_MUTE, 0); 7389 } 7390 } 7391 7392 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7393 { 7394 unsigned int caps; 7395 7396 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7397 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7398 snd_hda_override_amp_caps(codec, nid, dir, caps); 7399 } 7400 7401 /* 7402 * Switch between Digital built-in mic and analog mic. 7403 */ 7404 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7405 { 7406 struct ca0132_spec *spec = codec->spec; 7407 unsigned int tmp; 7408 u8 val; 7409 unsigned int oldval; 7410 7411 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7412 7413 oldval = stop_mic1(codec); 7414 ca0132_set_vipsource(codec, 0); 7415 if (enable) { 7416 /* set DMic input as 2-ch */ 7417 tmp = FLOAT_TWO; 7418 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7419 7420 val = spec->dmic_ctl; 7421 val |= 0x80; 7422 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7423 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7424 7425 if (!(spec->dmic_ctl & 0x20)) 7426 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7427 } else { 7428 /* set AMic input as mono */ 7429 tmp = FLOAT_ONE; 7430 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7431 7432 val = spec->dmic_ctl; 7433 /* clear bit7 and bit5 to disable dmic */ 7434 val &= 0x5f; 7435 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7436 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7437 7438 if (!(spec->dmic_ctl & 0x20)) 7439 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7440 } 7441 ca0132_set_vipsource(codec, 1); 7442 resume_mic1(codec, oldval); 7443 } 7444 7445 /* 7446 * Initialization for Digital Mic. 7447 */ 7448 static void ca0132_init_dmic(struct hda_codec *codec) 7449 { 7450 struct ca0132_spec *spec = codec->spec; 7451 u8 val; 7452 7453 /* Setup Digital Mic here, but don't enable. 7454 * Enable based on jack detect. 7455 */ 7456 7457 /* MCLK uses MPIO1, set to enable. 7458 * Bit 2-0: MPIO select 7459 * Bit 3: set to disable 7460 * Bit 7-4: reserved 7461 */ 7462 val = 0x01; 7463 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7464 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7465 7466 /* Data1 uses MPIO3. Data2 not use 7467 * Bit 2-0: Data1 MPIO select 7468 * Bit 3: set disable Data1 7469 * Bit 6-4: Data2 MPIO select 7470 * Bit 7: set disable Data2 7471 */ 7472 val = 0x83; 7473 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7474 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7475 7476 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7477 * Bit 3-0: Channel mask 7478 * Bit 4: set for 48KHz, clear for 32KHz 7479 * Bit 5: mode 7480 * Bit 6: set to select Data2, clear for Data1 7481 * Bit 7: set to enable DMic, clear for AMic 7482 */ 7483 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7484 val = 0x33; 7485 else 7486 val = 0x23; 7487 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7488 spec->dmic_ctl = val; 7489 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7490 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7491 } 7492 7493 /* 7494 * Initialization for Analog Mic 2 7495 */ 7496 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7497 { 7498 struct ca0132_spec *spec = codec->spec; 7499 7500 guard(mutex)(&spec->chipio_mutex); 7501 7502 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); 7503 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); 7504 } 7505 7506 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7507 { 7508 struct ca0132_spec *spec = codec->spec; 7509 int i; 7510 7511 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7512 snd_hda_codec_update_widgets(codec); 7513 7514 for (i = 0; i < spec->multiout.num_dacs; i++) 7515 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7516 7517 for (i = 0; i < spec->num_outputs; i++) 7518 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7519 7520 for (i = 0; i < spec->num_inputs; i++) { 7521 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7522 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7523 } 7524 } 7525 7526 7527 /* If there is an active channel for some reason, find it and free it. */ 7528 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) 7529 { 7530 unsigned int i, tmp; 7531 int status; 7532 7533 /* Read active DSPDMAC channel register. */ 7534 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); 7535 if (status >= 0) { 7536 /* AND against 0xfff to get the active channel bits. */ 7537 tmp = tmp & 0xfff; 7538 7539 /* If there are no active channels, nothing to free. */ 7540 if (!tmp) 7541 return; 7542 } else { 7543 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", 7544 __func__); 7545 return; 7546 } 7547 7548 /* 7549 * Check each DSP DMA channel for activity, and if the channel is 7550 * active, free it. 7551 */ 7552 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { 7553 if (dsp_is_dma_active(codec, i)) { 7554 status = dspio_free_dma_chan(codec, i); 7555 if (status < 0) 7556 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", 7557 __func__, i); 7558 } 7559 } 7560 } 7561 7562 /* 7563 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in 7564 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. 7565 * Instead, audio is now routed through the DSP's DMA controllers, which 7566 * the DSP is tasked with setting up itself. Through debugging, it seems the 7567 * cause of most of the no-audio on startup issues were due to improperly 7568 * configured DSP DMA channels. 7569 * 7570 * Normally, the DSP configures these the first time an HDA audio stream is 7571 * started post DSP firmware download. That is why creating a 'dummy' stream 7572 * worked in fixing the audio in some cases. This works most of the time, but 7573 * sometimes if a stream is started/stopped before the DSP can setup the DMA 7574 * configuration registers, it ends up in a broken state. Issues can also 7575 * arise if streams are started in an unusual order, i.e the audio output dma 7576 * channel being sandwiched between the mic1 and mic2 dma channels. 7577 * 7578 * The solution to this is to make sure that the DSP has no DMA channels 7579 * in use post DSP firmware download, and then to manually start each default 7580 * DSP stream that uses the DMA channels. These are 0x0c, the audio output 7581 * stream, 0x03, analog mic 1, and 0x04, analog mic 2. 7582 */ 7583 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) 7584 { 7585 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; 7586 struct ca0132_spec *spec = codec->spec; 7587 unsigned int i, tmp; 7588 7589 /* 7590 * Check if any of the default streams are active, and if they are, 7591 * stop them. 7592 */ 7593 scoped_guard(mutex, &spec->chipio_mutex) { 7594 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7595 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); 7596 7597 if (tmp) { 7598 chipio_set_stream_control(codec, 7599 dsp_dma_stream_ids[i], 0); 7600 } 7601 } 7602 } 7603 7604 /* 7605 * If all DSP streams are inactive, there should be no active DSP DMA 7606 * channels. Check and make sure this is the case, and if it isn't, 7607 * free any active channels. 7608 */ 7609 ca0132_alt_free_active_dma_channels(codec); 7610 7611 guard(mutex)(&spec->chipio_mutex); 7612 7613 /* Make sure stream 0x0c is six channels. */ 7614 chipio_set_stream_channels(codec, 0x0c, 6); 7615 7616 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7617 chipio_set_stream_control(codec, 7618 dsp_dma_stream_ids[i], 1); 7619 7620 /* Give the DSP some time to setup the DMA channel. */ 7621 msleep(75); 7622 } 7623 } 7624 7625 /* 7626 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio 7627 * router', where each entry represents a 48khz audio channel, with a format 7628 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number 7629 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, 7630 * and 3 if it's using Sample Rate Converter ports. 7631 * An example is: 7632 * 0x0001f8c0 7633 * In this case, f8 is the destination, and c0 is the source. The number value 7634 * is 1. 7635 * This region of memory is normally managed internally by the 8051, where 7636 * the region of exram memory from 0x1477-0x1575 has each byte represent an 7637 * entry within the 0x190000 range, and when a range of entries is in use, the 7638 * ending value is overwritten with 0xff. 7639 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO 7640 * streamID's, where each entry is a starting 0x190000 port offset. 7641 * 0x159d in exram is the same as 0x1578, except it contains the ending port 7642 * offset for the corresponding streamID. 7643 * 7644 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by 7645 * the 8051, then manually overwritten to remap the ports to work with the 7646 * new DACs. 7647 * 7648 * Currently known portID's: 7649 * 0x00-0x1f: HDA audio stream input/output ports. 7650 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to 7651 * have the lower-nibble set to 0x1, 0x2, and 0x9. 7652 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. 7653 * 0xe0-0xff: DAC/ADC audio input/output ports. 7654 * 7655 * Currently known streamID's: 7656 * 0x03: Mic1 ADC to DSP. 7657 * 0x04: Mic2 ADC to DSP. 7658 * 0x05: HDA node 0x02 audio stream to DSP. 7659 * 0x0f: DSP Mic exit to HDA node 0x07. 7660 * 0x0c: DSP processed audio to DACs. 7661 * 0x14: DAC0, front L/R. 7662 * 7663 * It is possible to route the HDA audio streams directly to the DAC and 7664 * bypass the DSP entirely, with the only downside being that since the DSP 7665 * does volume control, the only volume control you'll get is through PCM on 7666 * the PC side, in the same way volume is handled for optical out. This may be 7667 * useful for debugging. 7668 */ 7669 static void chipio_remap_stream(struct hda_codec *codec, 7670 const struct chipio_stream_remap_data *remap_data) 7671 { 7672 unsigned int i, stream_offset; 7673 7674 /* Get the starting port for the stream to be remapped. */ 7675 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7676 &stream_offset); 7677 7678 /* 7679 * Check if the stream's port value is 0xff, because the 8051 may not 7680 * have gotten around to setting up the stream yet. Wait until it's 7681 * setup to remap it's ports. 7682 */ 7683 if (stream_offset == 0xff) { 7684 for (i = 0; i < 5; i++) { 7685 msleep(25); 7686 7687 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7688 &stream_offset); 7689 7690 if (stream_offset != 0xff) 7691 break; 7692 } 7693 } 7694 7695 if (stream_offset == 0xff) { 7696 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", 7697 __func__, remap_data->stream_id); 7698 return; 7699 } 7700 7701 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ 7702 stream_offset *= 0x04; 7703 stream_offset += 0x190000; 7704 7705 for (i = 0; i < remap_data->count; i++) { 7706 chipio_write_no_mutex(codec, 7707 stream_offset + remap_data->offset[i], 7708 remap_data->value[i]); 7709 } 7710 7711 /* Update stream map configuration. */ 7712 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7713 } 7714 7715 /* 7716 * Default speaker tuning values setup for alternative codecs. 7717 */ 7718 static const unsigned int sbz_default_delay_values[] = { 7719 /* Non-zero values are floating point 0.000198. */ 7720 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7721 }; 7722 7723 static const unsigned int zxr_default_delay_values[] = { 7724 /* Non-zero values are floating point 0.000220. */ 7725 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7726 }; 7727 7728 static const unsigned int ae5_default_delay_values[] = { 7729 /* Non-zero values are floating point 0.000100. */ 7730 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7731 }; 7732 7733 /* 7734 * If we never change these, probably only need them on initialization. 7735 */ 7736 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7737 { 7738 struct ca0132_spec *spec = codec->spec; 7739 unsigned int i, tmp, start_req, end_req; 7740 const unsigned int *values; 7741 7742 switch (ca0132_quirk(spec)) { 7743 case QUIRK_SBZ: 7744 values = sbz_default_delay_values; 7745 break; 7746 case QUIRK_ZXR: 7747 values = zxr_default_delay_values; 7748 break; 7749 case QUIRK_AE5: 7750 case QUIRK_AE7: 7751 values = ae5_default_delay_values; 7752 break; 7753 default: 7754 values = sbz_default_delay_values; 7755 break; 7756 } 7757 7758 tmp = FLOAT_ZERO; 7759 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7760 7761 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7762 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7763 for (i = start_req; i < end_req + 1; i++) 7764 dspio_set_uint_param(codec, 0x96, i, tmp); 7765 7766 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7767 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7768 for (i = start_req; i < end_req + 1; i++) 7769 dspio_set_uint_param(codec, 0x96, i, tmp); 7770 7771 7772 for (i = 0; i < 6; i++) 7773 dspio_set_uint_param(codec, 0x96, 7774 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7775 } 7776 7777 /* 7778 * Initialize mic for non-chromebook ca0132 implementations. 7779 */ 7780 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7781 { 7782 struct ca0132_spec *spec = codec->spec; 7783 unsigned int tmp; 7784 7785 /* Mic 1 Setup */ 7786 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7787 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7788 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7789 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7790 tmp = FLOAT_ONE; 7791 } else 7792 tmp = FLOAT_THREE; 7793 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7794 7795 /* Mic 2 setup (not present on desktop cards) */ 7796 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7797 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7798 if (ca0132_quirk(spec) == QUIRK_R3DI) 7799 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7800 tmp = FLOAT_ZERO; 7801 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7802 } 7803 7804 /* 7805 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7806 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7807 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7808 * having an updated DAC, which changes the destination to that DAC. 7809 */ 7810 static void sbz_connect_streams(struct hda_codec *codec) 7811 { 7812 struct ca0132_spec *spec = codec->spec; 7813 7814 guard(mutex)(&spec->chipio_mutex); 7815 7816 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7817 7818 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7819 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7820 7821 /* Setup stream 0x14 with it's source and destination points */ 7822 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7823 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7824 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7825 chipio_set_stream_channels(codec, 0x14, 2); 7826 chipio_set_stream_control(codec, 0x14, 1); 7827 7828 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7829 } 7830 7831 /* 7832 * Write data through ChipIO to setup proper stream destinations. 7833 * Not sure how it exactly works, but it seems to direct data 7834 * to different destinations. Example is f8 to c0, e0 to c0. 7835 * All I know is, if you don't set these, you get no sound. 7836 */ 7837 static void sbz_chipio_startup_data(struct hda_codec *codec) 7838 { 7839 const struct chipio_stream_remap_data *dsp_out_remap_data; 7840 struct ca0132_spec *spec = codec->spec; 7841 7842 guard(mutex)(&spec->chipio_mutex); 7843 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7844 7845 /* Remap DAC0's output ports. */ 7846 chipio_remap_stream(codec, &stream_remap_data[0]); 7847 7848 /* Remap DSP audio output stream ports. */ 7849 switch (ca0132_quirk(spec)) { 7850 case QUIRK_SBZ: 7851 dsp_out_remap_data = &stream_remap_data[1]; 7852 break; 7853 7854 case QUIRK_ZXR: 7855 dsp_out_remap_data = &stream_remap_data[2]; 7856 break; 7857 7858 default: 7859 dsp_out_remap_data = NULL; 7860 break; 7861 } 7862 7863 if (dsp_out_remap_data) 7864 chipio_remap_stream(codec, dsp_out_remap_data); 7865 7866 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7867 } 7868 7869 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7870 { 7871 struct ca0132_spec *spec = codec->spec; 7872 unsigned int tmp; 7873 7874 chipio_set_stream_control(codec, 0x03, 0); 7875 chipio_set_stream_control(codec, 0x04, 0); 7876 7877 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7878 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7879 7880 tmp = FLOAT_THREE; 7881 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7882 7883 chipio_set_stream_control(codec, 0x03, 1); 7884 chipio_set_stream_control(codec, 0x04, 1); 7885 7886 switch (ca0132_quirk(spec)) { 7887 case QUIRK_SBZ: 7888 chipio_write(codec, 0x18b098, 0x0000000c); 7889 chipio_write(codec, 0x18b09C, 0x0000000c); 7890 break; 7891 case QUIRK_AE5: 7892 chipio_write(codec, 0x18b098, 0x0000000c); 7893 chipio_write(codec, 0x18b09c, 0x0000004c); 7894 break; 7895 default: 7896 break; 7897 } 7898 } 7899 7900 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7901 { 7902 struct ca0132_spec *spec = codec->spec; 7903 7904 chipio_8051_write_direct(codec, 0x93, 0x10); 7905 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 7906 7907 writeb(0xff, spec->mem_base + 0x304); 7908 writeb(0xff, spec->mem_base + 0x304); 7909 writeb(0xff, spec->mem_base + 0x304); 7910 writeb(0xff, spec->mem_base + 0x304); 7911 writeb(0x00, spec->mem_base + 0x100); 7912 writeb(0xff, spec->mem_base + 0x304); 7913 writeb(0x00, spec->mem_base + 0x100); 7914 writeb(0xff, spec->mem_base + 0x304); 7915 writeb(0x00, spec->mem_base + 0x100); 7916 writeb(0xff, spec->mem_base + 0x304); 7917 writeb(0x00, spec->mem_base + 0x100); 7918 writeb(0xff, spec->mem_base + 0x304); 7919 7920 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7921 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7922 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7923 } 7924 7925 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7926 { 7927 /* 7928 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7929 * which seems to be 'multichannel'. This is also mentioned in the 7930 * AE-5's registry values in Windows. 7931 */ 7932 chipio_set_control_param(codec, 3, 0); 7933 /* 7934 * I believe ASI is 'audio serial interface' and that it's used to 7935 * change colors on the external LED strip connected to the AE-5. 7936 */ 7937 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7938 7939 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7940 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7941 7942 chipio_8051_write_exram(codec, 0xfa92, 0x22); 7943 } 7944 7945 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7946 { 7947 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 7948 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); 7949 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); 7950 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 7951 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); 7952 } 7953 7954 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7955 { 7956 struct ca0132_spec *spec = codec->spec; 7957 7958 guard(mutex)(&spec->chipio_mutex); 7959 7960 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7961 7962 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7963 7964 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7965 7966 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7967 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7968 chipio_set_stream_channels(codec, 0x18, 6); 7969 chipio_set_stream_control(codec, 0x18, 1); 7970 7971 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7972 7973 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 7974 7975 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7976 } 7977 7978 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7979 { 7980 struct ca0132_spec *spec = codec->spec; 7981 7982 guard(mutex)(&spec->chipio_mutex); 7983 7984 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7985 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7986 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7987 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7988 7989 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7990 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7991 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7992 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7993 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7994 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7995 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7996 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7997 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7998 ca0113_mmio_gpio_set(codec, 0, true); 7999 ca0113_mmio_gpio_set(codec, 1, true); 8000 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 8001 8002 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 8003 8004 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8005 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8006 } 8007 8008 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 8009 { 8010 struct ca0132_spec *spec = codec->spec; 8011 8012 guard(mutex)(&spec->chipio_mutex); 8013 8014 /* Seems to share the same port remapping as the SBZ. */ 8015 chipio_remap_stream(codec, &stream_remap_data[1]); 8016 8017 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8018 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 8019 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 8020 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 8021 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 8022 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 8023 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 8024 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 8025 } 8026 8027 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 8028 { 8029 struct ca0132_spec *spec = codec->spec; 8030 8031 guard(mutex)(&spec->chipio_mutex); 8032 8033 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 8034 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8035 8036 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 8037 8038 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8039 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8040 8041 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8042 chipio_set_stream_channels(codec, 0x18, 6); 8043 chipio_set_stream_control(codec, 0x18, 1); 8044 8045 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8046 } 8047 8048 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 8049 { 8050 static const unsigned int addr[] = { 8051 0x41, 0x45, 0x40, 0x43, 0x51 8052 }; 8053 static const unsigned int data[] = { 8054 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 8055 }; 8056 unsigned int i; 8057 8058 for (i = 0; i < ARRAY_SIZE(addr); i++) 8059 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); 8060 } 8061 8062 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 8063 { 8064 struct ca0132_spec *spec = codec->spec; 8065 static const unsigned int target[] = { 8066 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 8067 }; 8068 static const unsigned int data[] = { 8069 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 8070 }; 8071 unsigned int i; 8072 8073 guard(mutex)(&spec->chipio_mutex); 8074 8075 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8076 8077 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8078 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8079 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8080 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8081 8082 ae7_post_dsp_pll_setup(codec); 8083 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8084 8085 for (i = 0; i < ARRAY_SIZE(target); i++) 8086 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 8087 8088 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8089 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8090 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8091 8092 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 8093 chipio_set_stream_channels(codec, 0x21, 2); 8094 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 8095 8096 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 8097 /* 8098 * In the 8051's memory, this param is referred to as 'n2sid', which I 8099 * believe is 'node to streamID'. It seems to be a way to assign a 8100 * stream to a given HDA node. 8101 */ 8102 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 8103 8104 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 8105 8106 /* 8107 * Now, at this point on Windows, an actual stream is setup and 8108 * seemingly sends data to the HDA node 0x09, which is the digital 8109 * audio input node. This is left out here, because obviously I don't 8110 * know what data is being sent. Interestingly, the AE-5 seems to go 8111 * through the motions of getting here and never actually takes this 8112 * step, but the AE-7 does. 8113 */ 8114 8115 ca0113_mmio_gpio_set(codec, 0, 1); 8116 ca0113_mmio_gpio_set(codec, 1, 1); 8117 8118 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8119 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 8120 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8121 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8122 8123 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8124 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8125 8126 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8127 chipio_set_stream_channels(codec, 0x18, 6); 8128 8129 /* 8130 * Runs again, this has been repeated a few times, but I'm just 8131 * following what the Windows driver does. 8132 */ 8133 ae7_post_dsp_pll_setup(codec); 8134 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8135 } 8136 8137 /* 8138 * The Windows driver has commands that seem to setup ASI, which I believe to 8139 * be some sort of audio serial interface. My current speculation is that it's 8140 * related to communicating with the new DAC. 8141 */ 8142 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8143 { 8144 chipio_8051_write_direct(codec, 0x93, 0x10); 8145 8146 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 8147 8148 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8149 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8150 8151 chipio_set_control_param(codec, 3, 3); 8152 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8153 8154 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8155 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8156 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8157 8158 chipio_8051_write_exram(codec, 0xfa92, 0x22); 8159 8160 ae7_post_dsp_pll_setup(codec); 8161 ae7_post_dsp_asi_stream_setup(codec); 8162 8163 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 8164 8165 ae7_post_dsp_asi_setup_ports(codec); 8166 } 8167 8168 /* 8169 * Setup default parameters for DSP 8170 */ 8171 static void ca0132_setup_defaults(struct hda_codec *codec) 8172 { 8173 struct ca0132_spec *spec = codec->spec; 8174 unsigned int tmp; 8175 int num_fx; 8176 int idx, i; 8177 8178 if (spec->dsp_state != DSP_DOWNLOADED) 8179 return; 8180 8181 /* out, in effects + voicefx */ 8182 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8183 for (idx = 0; idx < num_fx; idx++) { 8184 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8185 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8186 ca0132_effects[idx].reqs[i], 8187 ca0132_effects[idx].def_vals[i]); 8188 } 8189 } 8190 8191 /*remove DSP headroom*/ 8192 tmp = FLOAT_ZERO; 8193 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8194 8195 /*set speaker EQ bypass attenuation*/ 8196 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8197 8198 /* set AMic1 and AMic2 as mono mic */ 8199 tmp = FLOAT_ONE; 8200 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8201 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8202 8203 /* set AMic1 as CrystalVoice input */ 8204 tmp = FLOAT_ONE; 8205 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8206 8207 /* set WUH source */ 8208 tmp = FLOAT_TWO; 8209 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8210 } 8211 8212 /* 8213 * Setup default parameters for Recon3D/Recon3Di DSP. 8214 */ 8215 8216 static void r3d_setup_defaults(struct hda_codec *codec) 8217 { 8218 struct ca0132_spec *spec = codec->spec; 8219 unsigned int tmp; 8220 int num_fx; 8221 int idx, i; 8222 8223 if (spec->dsp_state != DSP_DOWNLOADED) 8224 return; 8225 8226 ca0132_alt_init_analog_mics(codec); 8227 ca0132_alt_start_dsp_audio_streams(codec); 8228 8229 /*remove DSP headroom*/ 8230 tmp = FLOAT_ZERO; 8231 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8232 8233 /* set WUH source */ 8234 tmp = FLOAT_TWO; 8235 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8236 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8237 8238 /* Set speaker source? */ 8239 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8240 8241 if (ca0132_quirk(spec) == QUIRK_R3DI) 8242 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8243 8244 /* Disable mute on Center/LFE. */ 8245 if (ca0132_quirk(spec) == QUIRK_R3D) { 8246 ca0113_mmio_gpio_set(codec, 2, false); 8247 ca0113_mmio_gpio_set(codec, 4, true); 8248 } 8249 8250 /* Setup effect defaults */ 8251 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8252 for (idx = 0; idx < num_fx; idx++) { 8253 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8254 dspio_set_uint_param(codec, 8255 ca0132_effects[idx].mid, 8256 ca0132_effects[idx].reqs[i], 8257 ca0132_effects[idx].def_vals[i]); 8258 } 8259 } 8260 } 8261 8262 /* 8263 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8264 * than the Chromebook setup. 8265 */ 8266 static void sbz_setup_defaults(struct hda_codec *codec) 8267 { 8268 struct ca0132_spec *spec = codec->spec; 8269 unsigned int tmp; 8270 int num_fx; 8271 int idx, i; 8272 8273 if (spec->dsp_state != DSP_DOWNLOADED) 8274 return; 8275 8276 ca0132_alt_init_analog_mics(codec); 8277 ca0132_alt_start_dsp_audio_streams(codec); 8278 sbz_connect_streams(codec); 8279 sbz_chipio_startup_data(codec); 8280 8281 /* 8282 * Sets internal input loopback to off, used to have a switch to 8283 * enable input loopback, but turned out to be way too buggy. 8284 */ 8285 tmp = FLOAT_ONE; 8286 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8287 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8288 8289 /*remove DSP headroom*/ 8290 tmp = FLOAT_ZERO; 8291 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8292 8293 /* set WUH source */ 8294 tmp = FLOAT_TWO; 8295 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8296 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8297 8298 /* Set speaker source? */ 8299 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8300 8301 ca0132_alt_dsp_initial_mic_setup(codec); 8302 8303 /* out, in effects + voicefx */ 8304 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8305 for (idx = 0; idx < num_fx; idx++) { 8306 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8307 dspio_set_uint_param(codec, 8308 ca0132_effects[idx].mid, 8309 ca0132_effects[idx].reqs[i], 8310 ca0132_effects[idx].def_vals[i]); 8311 } 8312 } 8313 8314 ca0132_alt_init_speaker_tuning(codec); 8315 } 8316 8317 /* 8318 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8319 */ 8320 static void ae5_setup_defaults(struct hda_codec *codec) 8321 { 8322 struct ca0132_spec *spec = codec->spec; 8323 unsigned int tmp; 8324 int num_fx; 8325 int idx, i; 8326 8327 if (spec->dsp_state != DSP_DOWNLOADED) 8328 return; 8329 8330 ca0132_alt_init_analog_mics(codec); 8331 ca0132_alt_start_dsp_audio_streams(codec); 8332 8333 /* New, unknown SCP req's */ 8334 tmp = FLOAT_ZERO; 8335 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8336 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8337 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8338 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8339 8340 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8341 ca0113_mmio_gpio_set(codec, 0, false); 8342 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8343 8344 /* Internal loopback off */ 8345 tmp = FLOAT_ONE; 8346 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8347 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8348 8349 /*remove DSP headroom*/ 8350 tmp = FLOAT_ZERO; 8351 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8352 8353 /* set WUH source */ 8354 tmp = FLOAT_TWO; 8355 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8356 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8357 8358 /* Set speaker source? */ 8359 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8360 8361 ca0132_alt_dsp_initial_mic_setup(codec); 8362 ae5_post_dsp_register_set(codec); 8363 ae5_post_dsp_param_setup(codec); 8364 ae5_post_dsp_pll_setup(codec); 8365 ae5_post_dsp_stream_setup(codec); 8366 ae5_post_dsp_startup_data(codec); 8367 8368 /* out, in effects + voicefx */ 8369 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8370 for (idx = 0; idx < num_fx; idx++) { 8371 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8372 dspio_set_uint_param(codec, 8373 ca0132_effects[idx].mid, 8374 ca0132_effects[idx].reqs[i], 8375 ca0132_effects[idx].def_vals[i]); 8376 } 8377 } 8378 8379 ca0132_alt_init_speaker_tuning(codec); 8380 } 8381 8382 /* 8383 * Setup default parameters for the Sound Blaster AE-7 DSP. 8384 */ 8385 static void ae7_setup_defaults(struct hda_codec *codec) 8386 { 8387 struct ca0132_spec *spec = codec->spec; 8388 unsigned int tmp; 8389 int num_fx; 8390 int idx, i; 8391 8392 if (spec->dsp_state != DSP_DOWNLOADED) 8393 return; 8394 8395 ca0132_alt_init_analog_mics(codec); 8396 ca0132_alt_start_dsp_audio_streams(codec); 8397 ae7_post_dsp_setup_ports(codec); 8398 8399 tmp = FLOAT_ZERO; 8400 dspio_set_uint_param(codec, 0x96, 8401 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8402 dspio_set_uint_param(codec, 0x96, 8403 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8404 8405 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8406 8407 /* New, unknown SCP req's */ 8408 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8409 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8410 8411 ca0113_mmio_gpio_set(codec, 0, false); 8412 8413 /* Internal loopback off */ 8414 tmp = FLOAT_ONE; 8415 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8416 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8417 8418 /*remove DSP headroom*/ 8419 tmp = FLOAT_ZERO; 8420 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8421 8422 /* set WUH source */ 8423 tmp = FLOAT_TWO; 8424 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8425 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8426 8427 /* Set speaker source? */ 8428 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8429 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8430 8431 /* 8432 * This is the second time we've called this, but this is seemingly 8433 * what Windows does. 8434 */ 8435 ca0132_alt_init_analog_mics(codec); 8436 8437 ae7_post_dsp_asi_setup(codec); 8438 8439 /* 8440 * Not sure why, but these are both set to 1. They're only set to 0 8441 * upon shutdown. 8442 */ 8443 ca0113_mmio_gpio_set(codec, 0, true); 8444 ca0113_mmio_gpio_set(codec, 1, true); 8445 8446 /* Volume control related. */ 8447 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8448 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8449 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8450 8451 /* out, in effects + voicefx */ 8452 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8453 for (idx = 0; idx < num_fx; idx++) { 8454 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8455 dspio_set_uint_param(codec, 8456 ca0132_effects[idx].mid, 8457 ca0132_effects[idx].reqs[i], 8458 ca0132_effects[idx].def_vals[i]); 8459 } 8460 } 8461 8462 ca0132_alt_init_speaker_tuning(codec); 8463 } 8464 8465 /* 8466 * Initialization of flags in chip 8467 */ 8468 static void ca0132_init_flags(struct hda_codec *codec) 8469 { 8470 struct ca0132_spec *spec = codec->spec; 8471 8472 if (ca0132_use_alt_functions(spec)) { 8473 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8474 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8475 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8476 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8477 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8478 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8479 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8480 chipio_set_control_flag(codec, 8481 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8482 chipio_set_control_flag(codec, 8483 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8484 } else { 8485 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8486 chipio_set_control_flag(codec, 8487 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8488 chipio_set_control_flag(codec, 8489 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8490 chipio_set_control_flag(codec, 8491 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8492 chipio_set_control_flag(codec, 8493 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8494 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8495 } 8496 } 8497 8498 /* 8499 * Initialization of parameters in chip 8500 */ 8501 static void ca0132_init_params(struct hda_codec *codec) 8502 { 8503 struct ca0132_spec *spec = codec->spec; 8504 8505 if (ca0132_use_alt_functions(spec)) { 8506 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8507 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8508 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8509 chipio_set_control_param(codec, 0, 0); 8510 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8511 } 8512 8513 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8514 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8515 } 8516 8517 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8518 { 8519 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8520 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8521 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8522 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8523 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8524 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8525 8526 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8527 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8528 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8529 } 8530 8531 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8532 { 8533 bool dsp_loaded = false; 8534 struct ca0132_spec *spec = codec->spec; 8535 const struct dsp_image_seg *dsp_os_image; 8536 const struct firmware *fw_entry = NULL; 8537 /* 8538 * Alternate firmwares for different variants. The Recon3Di apparently 8539 * can use the default firmware, but I'll leave the option in case 8540 * it needs it again. 8541 */ 8542 switch (ca0132_quirk(spec)) { 8543 case QUIRK_SBZ: 8544 case QUIRK_R3D: 8545 case QUIRK_AE5: 8546 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8547 codec->card->dev) != 0) 8548 codec_dbg(codec, "Desktop firmware not found."); 8549 else 8550 codec_dbg(codec, "Desktop firmware selected."); 8551 break; 8552 case QUIRK_R3DI: 8553 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8554 codec->card->dev) != 0) 8555 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8556 else 8557 codec_dbg(codec, "Recon3Di firmware selected."); 8558 break; 8559 default: 8560 break; 8561 } 8562 /* 8563 * Use default ctefx.bin if no alt firmware is detected, or if none 8564 * exists for your particular codec. 8565 */ 8566 if (!fw_entry) { 8567 codec_dbg(codec, "Default firmware selected."); 8568 if (request_firmware(&fw_entry, EFX_FILE, 8569 codec->card->dev) != 0) 8570 return false; 8571 } 8572 8573 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8574 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8575 codec_err(codec, "ca0132 DSP load image failed\n"); 8576 goto exit_download; 8577 } 8578 8579 dsp_loaded = dspload_wait_loaded(codec); 8580 8581 exit_download: 8582 release_firmware(fw_entry); 8583 8584 return dsp_loaded; 8585 } 8586 8587 static void ca0132_download_dsp(struct hda_codec *codec) 8588 { 8589 struct ca0132_spec *spec = codec->spec; 8590 8591 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8592 return; /* NOP */ 8593 #endif 8594 8595 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8596 return; /* don't retry failures */ 8597 8598 chipio_enable_clocks(codec); 8599 if (spec->dsp_state != DSP_DOWNLOADED) { 8600 spec->dsp_state = DSP_DOWNLOADING; 8601 8602 if (!ca0132_download_dsp_images(codec)) 8603 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8604 else 8605 spec->dsp_state = DSP_DOWNLOADED; 8606 } 8607 8608 /* For codecs using alt functions, this is already done earlier */ 8609 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8610 ca0132_set_dsp_msr(codec, true); 8611 } 8612 8613 static void ca0132_process_dsp_response(struct hda_codec *codec, 8614 struct hda_jack_callback *callback) 8615 { 8616 struct ca0132_spec *spec = codec->spec; 8617 8618 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8619 CLASS(snd_hda_power_pm, pm)(codec); 8620 if (spec->wait_scp) { 8621 if (dspio_get_response_data(codec) >= 0) 8622 spec->wait_scp = 0; 8623 } 8624 8625 dspio_clear_response_queue(codec); 8626 } 8627 8628 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8629 { 8630 struct ca0132_spec *spec = codec->spec; 8631 struct hda_jack_tbl *tbl; 8632 8633 /* Delay enabling the HP amp, to let the mic-detection 8634 * state machine run. 8635 */ 8636 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8637 if (tbl) 8638 tbl->block_report = 1; 8639 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8640 } 8641 8642 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8643 { 8644 struct ca0132_spec *spec = codec->spec; 8645 8646 if (ca0132_use_alt_functions(spec)) 8647 ca0132_alt_select_in(codec); 8648 else 8649 ca0132_select_mic(codec); 8650 } 8651 8652 static void ca0132_setup_unsol(struct hda_codec *codec) 8653 { 8654 struct ca0132_spec *spec = codec->spec; 8655 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8656 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8657 amic_callback); 8658 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8659 ca0132_process_dsp_response); 8660 /* Front headphone jack detection */ 8661 if (ca0132_use_alt_functions(spec)) 8662 snd_hda_jack_detect_enable_callback(codec, 8663 spec->unsol_tag_front_hp, hp_callback); 8664 } 8665 8666 /* 8667 * Verbs tables. 8668 */ 8669 8670 /* Sends before DSP download. */ 8671 static const struct hda_verb ca0132_base_init_verbs[] = { 8672 /*enable ct extension*/ 8673 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8674 {} 8675 }; 8676 8677 /* Send at exit. */ 8678 static const struct hda_verb ca0132_base_exit_verbs[] = { 8679 /*set afg to D3*/ 8680 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8681 /*disable ct extension*/ 8682 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8683 {} 8684 }; 8685 8686 /* Other verbs tables. Sends after DSP download. */ 8687 8688 static const struct hda_verb ca0132_init_verbs0[] = { 8689 /* chip init verbs */ 8690 {0x15, 0x70D, 0xF0}, 8691 {0x15, 0x70E, 0xFE}, 8692 {0x15, 0x707, 0x75}, 8693 {0x15, 0x707, 0xD3}, 8694 {0x15, 0x707, 0x09}, 8695 {0x15, 0x707, 0x53}, 8696 {0x15, 0x707, 0xD4}, 8697 {0x15, 0x707, 0xEF}, 8698 {0x15, 0x707, 0x75}, 8699 {0x15, 0x707, 0xD3}, 8700 {0x15, 0x707, 0x09}, 8701 {0x15, 0x707, 0x02}, 8702 {0x15, 0x707, 0x37}, 8703 {0x15, 0x707, 0x78}, 8704 {0x15, 0x53C, 0xCE}, 8705 {0x15, 0x575, 0xC9}, 8706 {0x15, 0x53D, 0xCE}, 8707 {0x15, 0x5B7, 0xC9}, 8708 {0x15, 0x70D, 0xE8}, 8709 {0x15, 0x70E, 0xFE}, 8710 {0x15, 0x707, 0x02}, 8711 {0x15, 0x707, 0x68}, 8712 {0x15, 0x707, 0x62}, 8713 {0x15, 0x53A, 0xCE}, 8714 {0x15, 0x546, 0xC9}, 8715 {0x15, 0x53B, 0xCE}, 8716 {0x15, 0x5E8, 0xC9}, 8717 {} 8718 }; 8719 8720 /* Extra init verbs for desktop cards. */ 8721 static const struct hda_verb ca0132_init_verbs1[] = { 8722 {0x15, 0x70D, 0x20}, 8723 {0x15, 0x70E, 0x19}, 8724 {0x15, 0x707, 0x00}, 8725 {0x15, 0x539, 0xCE}, 8726 {0x15, 0x546, 0xC9}, 8727 {0x15, 0x70D, 0xB7}, 8728 {0x15, 0x70E, 0x09}, 8729 {0x15, 0x707, 0x10}, 8730 {0x15, 0x70D, 0xAF}, 8731 {0x15, 0x70E, 0x09}, 8732 {0x15, 0x707, 0x01}, 8733 {0x15, 0x707, 0x05}, 8734 {0x15, 0x70D, 0x73}, 8735 {0x15, 0x70E, 0x09}, 8736 {0x15, 0x707, 0x14}, 8737 {0x15, 0x6FF, 0xC4}, 8738 {} 8739 }; 8740 8741 static void ca0132_init_chip(struct hda_codec *codec) 8742 { 8743 struct ca0132_spec *spec = codec->spec; 8744 int num_fx; 8745 int i; 8746 unsigned int on; 8747 8748 mutex_init(&spec->chipio_mutex); 8749 8750 /* 8751 * The Windows driver always does this upon startup, which seems to 8752 * clear out any previous configuration. This should help issues where 8753 * a boot into Windows prior to a boot into Linux breaks things. Also, 8754 * Windows always sends the reset twice. 8755 */ 8756 if (ca0132_use_alt_functions(spec)) { 8757 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8758 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); 8759 8760 snd_hda_codec_write(codec, codec->core.afg, 0, 8761 AC_VERB_SET_CODEC_RESET, 0); 8762 snd_hda_codec_write(codec, codec->core.afg, 0, 8763 AC_VERB_SET_CODEC_RESET, 0); 8764 } 8765 8766 spec->cur_out_type = SPEAKER_OUT; 8767 if (!ca0132_use_alt_functions(spec)) 8768 spec->cur_mic_type = DIGITAL_MIC; 8769 else 8770 spec->cur_mic_type = REAR_MIC; 8771 8772 spec->cur_mic_boost = 0; 8773 8774 for (i = 0; i < VNODES_COUNT; i++) { 8775 spec->vnode_lvol[i] = 0x5a; 8776 spec->vnode_rvol[i] = 0x5a; 8777 spec->vnode_lswitch[i] = 0; 8778 spec->vnode_rswitch[i] = 0; 8779 } 8780 8781 /* 8782 * Default states for effects are in ca0132_effects[]. 8783 */ 8784 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8785 for (i = 0; i < num_fx; i++) { 8786 on = (unsigned int)ca0132_effects[i].reqs[0]; 8787 spec->effects_switch[i] = on ? 1 : 0; 8788 } 8789 /* 8790 * Sets defaults for the effect slider controls, only for alternative 8791 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8792 */ 8793 if (ca0132_use_alt_controls(spec)) { 8794 /* Set speakers to default to full range. */ 8795 spec->speaker_range_val[0] = 1; 8796 spec->speaker_range_val[1] = 1; 8797 8798 spec->xbass_xover_freq = 8; 8799 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8800 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8801 8802 spec->bass_redirect_xover_freq = 8; 8803 } 8804 8805 spec->voicefx_val = 0; 8806 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8807 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8808 8809 /* 8810 * The ZxR doesn't have a front panel header, and it's line-in is on 8811 * the daughter board. So, there is no input enum control, and we need 8812 * to make sure that spec->in_enum_val is set properly. 8813 */ 8814 if (ca0132_quirk(spec) == QUIRK_ZXR) 8815 spec->in_enum_val = REAR_MIC; 8816 8817 #ifdef ENABLE_TUNING_CONTROLS 8818 ca0132_init_tuning_defaults(codec); 8819 #endif 8820 } 8821 8822 /* 8823 * Recon3Di exit specific commands. 8824 */ 8825 /* prevents popping noise on shutdown */ 8826 static void r3di_gpio_shutdown(struct hda_codec *codec) 8827 { 8828 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8829 } 8830 8831 /* 8832 * Sound Blaster Z exit specific commands. 8833 */ 8834 static void sbz_region2_exit(struct hda_codec *codec) 8835 { 8836 struct ca0132_spec *spec = codec->spec; 8837 unsigned int i; 8838 8839 for (i = 0; i < 4; i++) 8840 writeb(0x0, spec->mem_base + 0x100); 8841 for (i = 0; i < 8; i++) 8842 writeb(0xb3, spec->mem_base + 0x304); 8843 8844 ca0113_mmio_gpio_set(codec, 0, false); 8845 ca0113_mmio_gpio_set(codec, 1, false); 8846 ca0113_mmio_gpio_set(codec, 4, true); 8847 ca0113_mmio_gpio_set(codec, 5, false); 8848 ca0113_mmio_gpio_set(codec, 7, false); 8849 } 8850 8851 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8852 { 8853 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8854 unsigned int i; 8855 8856 snd_hda_codec_write(codec, 0x11, 0, 8857 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8858 8859 for (i = 0; i < ARRAY_SIZE(pins); i++) 8860 snd_hda_codec_write(codec, pins[i], 0, 8861 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8862 } 8863 8864 static void ca0132_clear_unsolicited(struct hda_codec *codec) 8865 { 8866 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8867 unsigned int i; 8868 8869 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8870 snd_hda_codec_write(codec, pins[i], 0, 8871 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8872 } 8873 } 8874 8875 /* On shutdown, sends commands in sets of three */ 8876 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8877 int mask, int data) 8878 { 8879 if (dir >= 0) 8880 snd_hda_codec_write(codec, 0x01, 0, 8881 AC_VERB_SET_GPIO_DIRECTION, dir); 8882 if (mask >= 0) 8883 snd_hda_codec_write(codec, 0x01, 0, 8884 AC_VERB_SET_GPIO_MASK, mask); 8885 8886 if (data >= 0) 8887 snd_hda_codec_write(codec, 0x01, 0, 8888 AC_VERB_SET_GPIO_DATA, data); 8889 } 8890 8891 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8892 { 8893 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8894 unsigned int i; 8895 8896 for (i = 0; i < ARRAY_SIZE(pins); i++) 8897 snd_hda_codec_write(codec, pins[i], 0, 8898 AC_VERB_SET_POWER_STATE, 0x03); 8899 } 8900 8901 static void sbz_exit_chip(struct hda_codec *codec) 8902 { 8903 chipio_set_stream_control(codec, 0x03, 0); 8904 chipio_set_stream_control(codec, 0x04, 0); 8905 8906 /* Mess with GPIO */ 8907 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8908 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8909 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8910 8911 chipio_set_stream_control(codec, 0x14, 0); 8912 chipio_set_stream_control(codec, 0x0C, 0); 8913 8914 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8915 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8916 8917 chipio_write(codec, 0x18a020, 0x00000083); 8918 8919 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8920 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8921 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8922 8923 chipio_set_stream_control(codec, 0x0C, 0); 8924 8925 chipio_set_control_param(codec, 0x0D, 0x24); 8926 8927 ca0132_clear_unsolicited(codec); 8928 sbz_set_pin_ctl_default(codec); 8929 8930 snd_hda_codec_write(codec, 0x0B, 0, 8931 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8932 8933 sbz_region2_exit(codec); 8934 } 8935 8936 static void r3d_exit_chip(struct hda_codec *codec) 8937 { 8938 ca0132_clear_unsolicited(codec); 8939 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8940 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8941 } 8942 8943 static void ae5_exit_chip(struct hda_codec *codec) 8944 { 8945 chipio_set_stream_control(codec, 0x03, 0); 8946 chipio_set_stream_control(codec, 0x04, 0); 8947 8948 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8949 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8950 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8951 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8952 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8953 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 8954 ca0113_mmio_gpio_set(codec, 0, false); 8955 ca0113_mmio_gpio_set(codec, 1, false); 8956 8957 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8958 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8959 8960 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8961 8962 chipio_set_stream_control(codec, 0x18, 0); 8963 chipio_set_stream_control(codec, 0x0c, 0); 8964 8965 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 8966 } 8967 8968 static void ae7_exit_chip(struct hda_codec *codec) 8969 { 8970 chipio_set_stream_control(codec, 0x18, 0); 8971 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 8972 chipio_set_stream_channels(codec, 0x21, 0); 8973 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 8974 chipio_set_control_param(codec, 0x20, 0x01); 8975 8976 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8977 8978 chipio_set_stream_control(codec, 0x18, 0); 8979 chipio_set_stream_control(codec, 0x0c, 0); 8980 8981 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8982 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 8983 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8984 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8985 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 8986 ca0113_mmio_gpio_set(codec, 0, false); 8987 ca0113_mmio_gpio_set(codec, 1, false); 8988 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8989 8990 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8991 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8992 } 8993 8994 static void zxr_exit_chip(struct hda_codec *codec) 8995 { 8996 chipio_set_stream_control(codec, 0x03, 0); 8997 chipio_set_stream_control(codec, 0x04, 0); 8998 chipio_set_stream_control(codec, 0x14, 0); 8999 chipio_set_stream_control(codec, 0x0C, 0); 9000 9001 chipio_set_conn_rate(codec, 0x41, SR_192_000); 9002 chipio_set_conn_rate(codec, 0x91, SR_192_000); 9003 9004 chipio_write(codec, 0x18a020, 0x00000083); 9005 9006 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 9007 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 9008 9009 ca0132_clear_unsolicited(codec); 9010 sbz_set_pin_ctl_default(codec); 9011 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 9012 9013 ca0113_mmio_gpio_set(codec, 5, false); 9014 ca0113_mmio_gpio_set(codec, 2, false); 9015 ca0113_mmio_gpio_set(codec, 3, false); 9016 ca0113_mmio_gpio_set(codec, 0, false); 9017 ca0113_mmio_gpio_set(codec, 4, true); 9018 ca0113_mmio_gpio_set(codec, 0, true); 9019 ca0113_mmio_gpio_set(codec, 5, true); 9020 ca0113_mmio_gpio_set(codec, 2, false); 9021 ca0113_mmio_gpio_set(codec, 3, false); 9022 } 9023 9024 static void ca0132_exit_chip(struct hda_codec *codec) 9025 { 9026 /* put any chip cleanup stuffs here. */ 9027 9028 if (dspload_is_loaded(codec)) 9029 dsp_reset(codec); 9030 } 9031 9032 /* 9033 * This fixes a problem that was hard to reproduce. Very rarely, I would 9034 * boot up, and there would be no sound, but the DSP indicated it had loaded 9035 * properly. I did a few memory dumps to see if anything was different, and 9036 * there were a few areas of memory uninitialized with a1a2a3a4. This function 9037 * checks if those areas are uninitialized, and if they are, it'll attempt to 9038 * reload the card 3 times. Usually it fixes by the second. 9039 */ 9040 static void sbz_dsp_startup_check(struct hda_codec *codec) 9041 { 9042 struct ca0132_spec *spec = codec->spec; 9043 unsigned int dsp_data_check[4]; 9044 unsigned int cur_address = 0x390; 9045 unsigned int i; 9046 unsigned int failure = 0; 9047 unsigned int reload = 3; 9048 9049 if (spec->startup_check_entered) 9050 return; 9051 9052 spec->startup_check_entered = true; 9053 9054 for (i = 0; i < 4; i++) { 9055 chipio_read(codec, cur_address, &dsp_data_check[i]); 9056 cur_address += 0x4; 9057 } 9058 for (i = 0; i < 4; i++) { 9059 if (dsp_data_check[i] == 0xa1a2a3a4) 9060 failure = 1; 9061 } 9062 9063 codec_dbg(codec, "Startup Check: %d ", failure); 9064 if (failure) 9065 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 9066 /* 9067 * While the failure condition is true, and we haven't reached our 9068 * three reload limit, continue trying to reload the driver and 9069 * fix the issue. 9070 */ 9071 while (failure && (reload != 0)) { 9072 codec_info(codec, "Reloading... Tries left: %d", reload); 9073 sbz_exit_chip(codec); 9074 spec->dsp_state = DSP_DOWNLOAD_INIT; 9075 snd_hda_codec_init(codec); 9076 failure = 0; 9077 for (i = 0; i < 4; i++) { 9078 chipio_read(codec, cur_address, &dsp_data_check[i]); 9079 cur_address += 0x4; 9080 } 9081 for (i = 0; i < 4; i++) { 9082 if (dsp_data_check[i] == 0xa1a2a3a4) 9083 failure = 1; 9084 } 9085 reload--; 9086 } 9087 9088 if (!failure && reload < 3) 9089 codec_info(codec, "DSP fixed."); 9090 9091 if (!failure) 9092 return; 9093 9094 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 9095 } 9096 9097 /* 9098 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 9099 * extra precision for decibel values. If you had the dB value in floating point 9100 * you would take the value after the decimal point, multiply by 64, and divide 9101 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 9102 * implement fixed point or floating point dB volumes. For now, I'll set them 9103 * to 0 just incase a value has lingered from a boot into Windows. 9104 */ 9105 static void ca0132_alt_vol_setup(struct hda_codec *codec) 9106 { 9107 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 9108 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 9109 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 9110 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 9111 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 9112 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 9113 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 9114 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 9115 } 9116 9117 /* 9118 * Extra commands that don't really fit anywhere else. 9119 */ 9120 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9121 { 9122 struct ca0132_spec *spec = codec->spec; 9123 9124 writel(0x00820680, spec->mem_base + 0x01C); 9125 writel(0x00820680, spec->mem_base + 0x01C); 9126 9127 chipio_write(codec, 0x18b0a4, 0x000000c2); 9128 9129 snd_hda_codec_write(codec, 0x11, 0, 9130 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9131 } 9132 9133 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9134 { 9135 chipio_write(codec, 0x18b0a4, 0x000000c2); 9136 9137 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9138 9139 snd_hda_codec_write(codec, 0x11, 0, 9140 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9141 } 9142 9143 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9144 { 9145 chipio_write(codec, 0x18b0a4, 0x000000c2); 9146 9147 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9148 chipio_8051_write_exram(codec, 0x1920, 0x00); 9149 chipio_8051_write_exram(codec, 0x1921, 0x40); 9150 9151 snd_hda_codec_write(codec, 0x11, 0, 9152 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9153 } 9154 9155 /* 9156 * The ZxR seems to use alternative DAC's for the surround channels, which 9157 * require PLL PMU setup for the clock rate, I'm guessing. Without setting 9158 * this up, we get no audio out of the surround jacks. 9159 */ 9160 static void zxr_pre_dsp_setup(struct hda_codec *codec) 9161 { 9162 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; 9163 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; 9164 unsigned int i; 9165 9166 chipio_write(codec, 0x189000, 0x0001f100); 9167 msleep(50); 9168 chipio_write(codec, 0x18900c, 0x0001f100); 9169 msleep(50); 9170 9171 /* 9172 * This writes a RET instruction at the entry point of the function at 9173 * 0xfa92 in exram. This function seems to have something to do with 9174 * ASI. Might be some way to prevent the card from reconfiguring the 9175 * ASI stuff itself. 9176 */ 9177 chipio_8051_write_exram(codec, 0xfa92, 0x22); 9178 9179 chipio_8051_write_pll_pmu(codec, 0x51, 0x98); 9180 9181 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); 9182 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); 9183 9184 chipio_write(codec, 0x18902c, 0x00000000); 9185 msleep(50); 9186 chipio_write(codec, 0x18902c, 0x00000003); 9187 msleep(50); 9188 9189 for (i = 0; i < ARRAY_SIZE(addr); i++) 9190 chipio_8051_write_pll_pmu(codec, addr[i], data[i]); 9191 } 9192 9193 /* 9194 * These are sent before the DSP is downloaded. Not sure 9195 * what they do, or if they're necessary. Could possibly 9196 * be removed. Figure they're better to leave in. 9197 */ 9198 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9199 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9200 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9201 }; 9202 9203 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9204 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9205 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9206 0x000000c1, 0x00000080 9207 }; 9208 9209 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9210 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9211 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9212 0x000000c1, 0x00000080 9213 }; 9214 9215 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9216 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9217 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9218 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9219 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9220 }; 9221 9222 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9223 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9224 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9225 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9226 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9227 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9228 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9229 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9230 0x00000080, 0x00880680 9231 }; 9232 9233 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9234 { 9235 struct ca0132_spec *spec = codec->spec; 9236 unsigned int tmp[2], i, count, cur_addr; 9237 const unsigned int *addr, *data; 9238 9239 addr = ca0113_mmio_init_address_sbz; 9240 for (i = 0; i < 3; i++) 9241 writel(0x00000000, spec->mem_base + addr[i]); 9242 9243 cur_addr = i; 9244 switch (ca0132_quirk(spec)) { 9245 case QUIRK_ZXR: 9246 tmp[0] = 0x00880480; 9247 tmp[1] = 0x00000080; 9248 break; 9249 case QUIRK_SBZ: 9250 tmp[0] = 0x00820680; 9251 tmp[1] = 0x00000083; 9252 break; 9253 case QUIRK_R3D: 9254 tmp[0] = 0x00880680; 9255 tmp[1] = 0x00000083; 9256 break; 9257 default: 9258 tmp[0] = 0x00000000; 9259 tmp[1] = 0x00000000; 9260 break; 9261 } 9262 9263 for (i = 0; i < 2; i++) 9264 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9265 9266 cur_addr += i; 9267 9268 switch (ca0132_quirk(spec)) { 9269 case QUIRK_ZXR: 9270 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9271 data = ca0113_mmio_init_data_zxr; 9272 break; 9273 default: 9274 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9275 data = ca0113_mmio_init_data_sbz; 9276 break; 9277 } 9278 9279 for (i = 0; i < count; i++) 9280 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9281 } 9282 9283 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9284 { 9285 struct ca0132_spec *spec = codec->spec; 9286 const unsigned int *addr, *data; 9287 unsigned int i, count; 9288 9289 addr = ca0113_mmio_init_address_ae5; 9290 data = ca0113_mmio_init_data_ae5; 9291 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9292 9293 if (ca0132_quirk(spec) == QUIRK_AE7) { 9294 writel(0x00000680, spec->mem_base + 0x1c); 9295 writel(0x00880680, spec->mem_base + 0x1c); 9296 } 9297 9298 for (i = 0; i < count; i++) { 9299 /* 9300 * AE-7 shares all writes with the AE-5, except that it writes 9301 * a different value to 0x20c. 9302 */ 9303 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9304 writel(0x00800001, spec->mem_base + addr[i]); 9305 continue; 9306 } 9307 9308 writel(data[i], spec->mem_base + addr[i]); 9309 } 9310 9311 if (ca0132_quirk(spec) == QUIRK_AE5) 9312 writel(0x00880680, spec->mem_base + 0x1c); 9313 } 9314 9315 static void ca0132_mmio_init(struct hda_codec *codec) 9316 { 9317 struct ca0132_spec *spec = codec->spec; 9318 9319 switch (ca0132_quirk(spec)) { 9320 case QUIRK_R3D: 9321 case QUIRK_SBZ: 9322 case QUIRK_ZXR: 9323 ca0132_mmio_init_sbz(codec); 9324 break; 9325 case QUIRK_AE5: 9326 ca0132_mmio_init_ae5(codec); 9327 break; 9328 default: 9329 break; 9330 } 9331 } 9332 9333 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9334 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9335 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9336 }; 9337 9338 static const unsigned char ca0132_ae5_register_set_data[] = { 9339 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9340 0x01, 0x6b, 0x57 9341 }; 9342 9343 /* 9344 * This function writes to some SFR's, does some region2 writes, and then 9345 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9346 * what it does. 9347 */ 9348 static void ae5_register_set(struct hda_codec *codec) 9349 { 9350 struct ca0132_spec *spec = codec->spec; 9351 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9352 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9353 const unsigned char *data = ca0132_ae5_register_set_data; 9354 unsigned int i, cur_addr; 9355 unsigned char tmp[3]; 9356 9357 if (ca0132_quirk(spec) == QUIRK_AE7) 9358 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 9359 9360 chipio_8051_write_direct(codec, 0x93, 0x10); 9361 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 9362 9363 if (ca0132_quirk(spec) == QUIRK_AE7) { 9364 tmp[0] = 0x03; 9365 tmp[1] = 0x03; 9366 tmp[2] = 0x07; 9367 } else { 9368 tmp[0] = 0x0f; 9369 tmp[1] = 0x0f; 9370 tmp[2] = 0x0f; 9371 } 9372 9373 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9374 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9375 9376 /* 9377 * First writes are in single bytes, final are in 4 bytes. So, we use 9378 * writeb, then writel. 9379 */ 9380 for (i = 0; cur_addr < 12; i++, cur_addr++) 9381 writeb(data[i], spec->mem_base + addr[cur_addr]); 9382 9383 for (; cur_addr < count; i++, cur_addr++) 9384 writel(data[i], spec->mem_base + addr[cur_addr]); 9385 9386 writel(0x00800001, spec->mem_base + 0x20c); 9387 9388 if (ca0132_quirk(spec) == QUIRK_AE7) { 9389 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9390 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9391 } else { 9392 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9393 } 9394 9395 chipio_8051_write_direct(codec, 0x90, 0x00); 9396 chipio_8051_write_direct(codec, 0x90, 0x10); 9397 9398 if (ca0132_quirk(spec) == QUIRK_AE5) 9399 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9400 } 9401 9402 /* 9403 * Extra init functions for alternative ca0132 codecs. Done 9404 * here so they don't clutter up the main ca0132_init function 9405 * anymore than they have to. 9406 */ 9407 static void ca0132_alt_init(struct hda_codec *codec) 9408 { 9409 struct ca0132_spec *spec = codec->spec; 9410 9411 ca0132_alt_vol_setup(codec); 9412 9413 switch (ca0132_quirk(spec)) { 9414 case QUIRK_SBZ: 9415 codec_dbg(codec, "SBZ alt_init"); 9416 ca0132_gpio_init(codec); 9417 sbz_pre_dsp_setup(codec); 9418 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9419 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9420 break; 9421 case QUIRK_R3DI: 9422 codec_dbg(codec, "R3DI alt_init"); 9423 ca0132_gpio_init(codec); 9424 ca0132_gpio_setup(codec); 9425 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9426 r3di_pre_dsp_setup(codec); 9427 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9428 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9429 break; 9430 case QUIRK_R3D: 9431 r3d_pre_dsp_setup(codec); 9432 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9433 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9434 break; 9435 case QUIRK_AE5: 9436 ca0132_gpio_init(codec); 9437 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9438 chipio_write(codec, 0x18b030, 0x00000020); 9439 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9440 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9441 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9442 break; 9443 case QUIRK_AE7: 9444 ca0132_gpio_init(codec); 9445 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9446 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9447 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9448 chipio_write(codec, 0x18b008, 0x000000f8); 9449 chipio_write(codec, 0x18b008, 0x000000f0); 9450 chipio_write(codec, 0x18b030, 0x00000020); 9451 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9452 break; 9453 case QUIRK_ZXR: 9454 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9455 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9456 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9457 zxr_pre_dsp_setup(codec); 9458 break; 9459 default: 9460 break; 9461 } 9462 } 9463 9464 static int ca0132_init(struct hda_codec *codec) 9465 { 9466 struct ca0132_spec *spec = codec->spec; 9467 struct auto_pin_cfg *cfg = &spec->autocfg; 9468 int i; 9469 bool dsp_loaded; 9470 9471 /* 9472 * If the DSP is already downloaded, and init has been entered again, 9473 * there's only two reasons for it. One, the codec has awaken from a 9474 * suspended state, and in that case dspload_is_loaded will return 9475 * false, and the init will be ran again. The other reason it gets 9476 * re entered is on startup for some reason it triggers a suspend and 9477 * resume state. In this case, it will check if the DSP is downloaded, 9478 * and not run the init function again. For codecs using alt_functions, 9479 * it will check if the DSP is loaded properly. 9480 */ 9481 if (spec->dsp_state == DSP_DOWNLOADED) { 9482 dsp_loaded = dspload_is_loaded(codec); 9483 if (!dsp_loaded) { 9484 spec->dsp_reload = true; 9485 spec->dsp_state = DSP_DOWNLOAD_INIT; 9486 } else { 9487 if (ca0132_quirk(spec) == QUIRK_SBZ) 9488 sbz_dsp_startup_check(codec); 9489 return 0; 9490 } 9491 } 9492 9493 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9494 spec->dsp_state = DSP_DOWNLOAD_INIT; 9495 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9496 9497 if (ca0132_use_pci_mmio(spec)) 9498 ca0132_mmio_init(codec); 9499 9500 CLASS(snd_hda_power_pm, pm)(codec); 9501 9502 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9503 ae5_register_set(codec); 9504 9505 ca0132_init_params(codec); 9506 ca0132_init_flags(codec); 9507 9508 snd_hda_sequence_write(codec, spec->base_init_verbs); 9509 9510 if (ca0132_use_alt_functions(spec)) 9511 ca0132_alt_init(codec); 9512 9513 ca0132_download_dsp(codec); 9514 9515 ca0132_refresh_widget_caps(codec); 9516 9517 switch (ca0132_quirk(spec)) { 9518 case QUIRK_R3DI: 9519 case QUIRK_R3D: 9520 r3d_setup_defaults(codec); 9521 break; 9522 case QUIRK_SBZ: 9523 case QUIRK_ZXR: 9524 sbz_setup_defaults(codec); 9525 break; 9526 case QUIRK_AE5: 9527 ae5_setup_defaults(codec); 9528 break; 9529 case QUIRK_AE7: 9530 ae7_setup_defaults(codec); 9531 break; 9532 default: 9533 ca0132_setup_defaults(codec); 9534 ca0132_init_analog_mic2(codec); 9535 ca0132_init_dmic(codec); 9536 break; 9537 } 9538 9539 for (i = 0; i < spec->num_outputs; i++) 9540 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9541 9542 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9543 9544 for (i = 0; i < spec->num_inputs; i++) 9545 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9546 9547 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9548 9549 if (!ca0132_use_alt_functions(spec)) { 9550 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9551 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9552 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9553 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9554 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9555 } 9556 9557 if (ca0132_quirk(spec) == QUIRK_SBZ) 9558 ca0132_gpio_setup(codec); 9559 9560 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9561 if (ca0132_use_alt_functions(spec)) { 9562 ca0132_alt_select_out(codec); 9563 ca0132_alt_select_in(codec); 9564 } else { 9565 ca0132_select_out(codec); 9566 ca0132_select_mic(codec); 9567 } 9568 9569 snd_hda_jack_report_sync(codec); 9570 9571 /* 9572 * Re set the PlayEnhancement switch on a resume event, because the 9573 * controls will not be reloaded. 9574 */ 9575 if (spec->dsp_reload) { 9576 spec->dsp_reload = false; 9577 ca0132_pe_switch_set(codec); 9578 } 9579 9580 return 0; 9581 } 9582 9583 static int dbpro_init(struct hda_codec *codec) 9584 { 9585 struct ca0132_spec *spec = codec->spec; 9586 struct auto_pin_cfg *cfg = &spec->autocfg; 9587 unsigned int i; 9588 9589 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9590 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9591 9592 for (i = 0; i < spec->num_inputs; i++) 9593 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9594 9595 return 0; 9596 } 9597 9598 static void ca0132_free(struct hda_codec *codec) 9599 { 9600 struct ca0132_spec *spec = codec->spec; 9601 9602 cancel_delayed_work_sync(&spec->unsol_hp_work); 9603 snd_hda_power_up(codec); 9604 switch (ca0132_quirk(spec)) { 9605 case QUIRK_SBZ: 9606 sbz_exit_chip(codec); 9607 break; 9608 case QUIRK_ZXR: 9609 zxr_exit_chip(codec); 9610 break; 9611 case QUIRK_R3D: 9612 r3d_exit_chip(codec); 9613 break; 9614 case QUIRK_AE5: 9615 ae5_exit_chip(codec); 9616 break; 9617 case QUIRK_AE7: 9618 ae7_exit_chip(codec); 9619 break; 9620 case QUIRK_R3DI: 9621 r3di_gpio_shutdown(codec); 9622 break; 9623 default: 9624 break; 9625 } 9626 9627 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9628 ca0132_exit_chip(codec); 9629 9630 snd_hda_power_down(codec); 9631 #ifdef CONFIG_PCI 9632 if (spec->mem_base) 9633 pci_iounmap(codec->bus->pci, spec->mem_base); 9634 #endif 9635 kfree(spec->spec_init_verbs); 9636 kfree(codec->spec); 9637 } 9638 9639 static void dbpro_free(struct hda_codec *codec) 9640 { 9641 struct ca0132_spec *spec = codec->spec; 9642 9643 zxr_dbpro_power_state_shutdown(codec); 9644 9645 kfree(spec->spec_init_verbs); 9646 kfree(codec->spec); 9647 } 9648 9649 static void ca0132_config(struct hda_codec *codec) 9650 { 9651 struct ca0132_spec *spec = codec->spec; 9652 9653 spec->dacs[0] = 0x2; 9654 spec->dacs[1] = 0x3; 9655 spec->dacs[2] = 0x4; 9656 9657 spec->multiout.dac_nids = spec->dacs; 9658 spec->multiout.num_dacs = 3; 9659 9660 if (!ca0132_use_alt_functions(spec)) 9661 spec->multiout.max_channels = 2; 9662 else 9663 spec->multiout.max_channels = 6; 9664 9665 switch (ca0132_quirk(spec)) { 9666 case QUIRK_ALIENWARE: 9667 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9668 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9669 break; 9670 case QUIRK_SBZ: 9671 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9672 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9673 break; 9674 case QUIRK_ZXR: 9675 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9676 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9677 break; 9678 case QUIRK_R3D: 9679 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9680 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9681 break; 9682 case QUIRK_R3DI: 9683 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9684 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9685 break; 9686 case QUIRK_AE5: 9687 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9688 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9689 break; 9690 case QUIRK_AE7: 9691 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9692 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9693 break; 9694 default: 9695 break; 9696 } 9697 9698 switch (ca0132_quirk(spec)) { 9699 case QUIRK_ALIENWARE: 9700 spec->num_outputs = 2; 9701 spec->out_pins[0] = 0x0b; /* speaker out */ 9702 spec->out_pins[1] = 0x0f; 9703 spec->shared_out_nid = 0x2; 9704 spec->unsol_tag_hp = 0x0f; 9705 9706 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9707 spec->adcs[1] = 0x8; /* analog mic2 */ 9708 spec->adcs[2] = 0xa; /* what u hear */ 9709 9710 spec->num_inputs = 3; 9711 spec->input_pins[0] = 0x12; 9712 spec->input_pins[1] = 0x11; 9713 spec->input_pins[2] = 0x13; 9714 spec->shared_mic_nid = 0x7; 9715 spec->unsol_tag_amic1 = 0x11; 9716 break; 9717 case QUIRK_SBZ: 9718 case QUIRK_R3D: 9719 spec->num_outputs = 2; 9720 spec->out_pins[0] = 0x0B; /* Line out */ 9721 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9722 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9723 spec->out_pins[3] = 0x11; /* Rear surround */ 9724 spec->shared_out_nid = 0x2; 9725 spec->unsol_tag_hp = spec->out_pins[1]; 9726 spec->unsol_tag_front_hp = spec->out_pins[2]; 9727 9728 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9729 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9730 spec->adcs[2] = 0xa; /* what u hear */ 9731 9732 spec->num_inputs = 2; 9733 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9734 spec->input_pins[1] = 0x13; /* What U Hear */ 9735 spec->shared_mic_nid = 0x7; 9736 spec->unsol_tag_amic1 = spec->input_pins[0]; 9737 9738 /* SPDIF I/O */ 9739 spec->dig_out = 0x05; 9740 spec->multiout.dig_out_nid = spec->dig_out; 9741 spec->dig_in = 0x09; 9742 break; 9743 case QUIRK_ZXR: 9744 spec->num_outputs = 2; 9745 spec->out_pins[0] = 0x0B; /* Line out */ 9746 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9747 spec->out_pins[2] = 0x10; /* Center/LFE */ 9748 spec->out_pins[3] = 0x11; /* Rear surround */ 9749 spec->shared_out_nid = 0x2; 9750 spec->unsol_tag_hp = spec->out_pins[1]; 9751 spec->unsol_tag_front_hp = spec->out_pins[2]; 9752 9753 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9754 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9755 spec->adcs[2] = 0xa; /* what u hear */ 9756 9757 spec->num_inputs = 2; 9758 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9759 spec->input_pins[1] = 0x13; /* What U Hear */ 9760 spec->shared_mic_nid = 0x7; 9761 spec->unsol_tag_amic1 = spec->input_pins[0]; 9762 break; 9763 case QUIRK_ZXR_DBPRO: 9764 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9765 9766 spec->num_inputs = 1; 9767 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9768 9769 spec->dig_out = 0x05; 9770 spec->multiout.dig_out_nid = spec->dig_out; 9771 9772 spec->dig_in = 0x09; 9773 break; 9774 case QUIRK_AE5: 9775 case QUIRK_AE7: 9776 spec->num_outputs = 2; 9777 spec->out_pins[0] = 0x0B; /* Line out */ 9778 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9779 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9780 spec->out_pins[3] = 0x0F; /* Rear surround */ 9781 spec->shared_out_nid = 0x2; 9782 spec->unsol_tag_hp = spec->out_pins[1]; 9783 spec->unsol_tag_front_hp = spec->out_pins[2]; 9784 9785 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9786 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9787 spec->adcs[2] = 0xa; /* what u hear */ 9788 9789 spec->num_inputs = 2; 9790 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9791 spec->input_pins[1] = 0x13; /* What U Hear */ 9792 spec->shared_mic_nid = 0x7; 9793 spec->unsol_tag_amic1 = spec->input_pins[0]; 9794 9795 /* SPDIF I/O */ 9796 spec->dig_out = 0x05; 9797 spec->multiout.dig_out_nid = spec->dig_out; 9798 break; 9799 case QUIRK_R3DI: 9800 spec->num_outputs = 2; 9801 spec->out_pins[0] = 0x0B; /* Line out */ 9802 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9803 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9804 spec->out_pins[3] = 0x11; /* Rear surround */ 9805 spec->shared_out_nid = 0x2; 9806 spec->unsol_tag_hp = spec->out_pins[1]; 9807 spec->unsol_tag_front_hp = spec->out_pins[2]; 9808 9809 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9810 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9811 spec->adcs[2] = 0x0a; /* what u hear */ 9812 9813 spec->num_inputs = 2; 9814 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9815 spec->input_pins[1] = 0x13; /* What U Hear */ 9816 spec->shared_mic_nid = 0x7; 9817 spec->unsol_tag_amic1 = spec->input_pins[0]; 9818 9819 /* SPDIF I/O */ 9820 spec->dig_out = 0x05; 9821 spec->multiout.dig_out_nid = spec->dig_out; 9822 break; 9823 default: 9824 spec->num_outputs = 2; 9825 spec->out_pins[0] = 0x0b; /* speaker out */ 9826 spec->out_pins[1] = 0x10; /* headphone out */ 9827 spec->shared_out_nid = 0x2; 9828 spec->unsol_tag_hp = spec->out_pins[1]; 9829 9830 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9831 spec->adcs[1] = 0x8; /* analog mic2 */ 9832 spec->adcs[2] = 0xa; /* what u hear */ 9833 9834 spec->num_inputs = 3; 9835 spec->input_pins[0] = 0x12; 9836 spec->input_pins[1] = 0x11; 9837 spec->input_pins[2] = 0x13; 9838 spec->shared_mic_nid = 0x7; 9839 spec->unsol_tag_amic1 = spec->input_pins[0]; 9840 9841 /* SPDIF I/O */ 9842 spec->dig_out = 0x05; 9843 spec->multiout.dig_out_nid = spec->dig_out; 9844 spec->dig_in = 0x09; 9845 break; 9846 } 9847 9848 /* Default HP/Speaker auto-detect from headphone pin verb: enable if the 9849 * pin config indicates presence detect (not AC_DEFCFG_MISC_NO_PRESENCE). 9850 */ 9851 if (spec->unsol_tag_hp && 9852 (snd_hda_query_pin_caps(codec, spec->unsol_tag_hp) & AC_PINCAP_PRES_DETECT) && 9853 !(get_defcfg_misc(snd_hda_codec_get_pincfg(codec, spec->unsol_tag_hp)) & 9854 AC_DEFCFG_MISC_NO_PRESENCE)) 9855 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID] = 1; 9856 } 9857 9858 static int ca0132_prepare_verbs(struct hda_codec *codec) 9859 { 9860 /* Verbs + terminator (an empty element) */ 9861 #define NUM_SPEC_VERBS 2 9862 struct ca0132_spec *spec = codec->spec; 9863 9864 spec->chip_init_verbs = ca0132_init_verbs0; 9865 /* 9866 * Since desktop cards use pci_mmio, this can be used to determine 9867 * whether or not to use these verbs instead of a separate bool. 9868 */ 9869 if (ca0132_use_pci_mmio(spec)) 9870 spec->desktop_init_verbs = ca0132_init_verbs1; 9871 spec->spec_init_verbs = kzalloc_objs(struct hda_verb, NUM_SPEC_VERBS); 9872 if (!spec->spec_init_verbs) 9873 return -ENOMEM; 9874 9875 /* config EAPD */ 9876 spec->spec_init_verbs[0].nid = 0x0b; 9877 spec->spec_init_verbs[0].param = 0x78D; 9878 spec->spec_init_verbs[0].verb = 0x00; 9879 9880 /* Previously commented configuration */ 9881 /* 9882 spec->spec_init_verbs[2].nid = 0x0b; 9883 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9884 spec->spec_init_verbs[2].verb = 0x02; 9885 9886 spec->spec_init_verbs[3].nid = 0x10; 9887 spec->spec_init_verbs[3].param = 0x78D; 9888 spec->spec_init_verbs[3].verb = 0x02; 9889 9890 spec->spec_init_verbs[4].nid = 0x10; 9891 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9892 spec->spec_init_verbs[4].verb = 0x02; 9893 */ 9894 9895 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9896 return 0; 9897 } 9898 9899 /* 9900 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9901 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9902 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9903 * daughter boards ID. 9904 */ 9905 static void sbz_detect_quirk(struct hda_codec *codec) 9906 { 9907 switch (codec->core.subsystem_id) { 9908 case 0x11020033: 9909 codec->fixup_id = QUIRK_ZXR; 9910 break; 9911 case 0x1102003f: 9912 codec->fixup_id = QUIRK_ZXR_DBPRO; 9913 break; 9914 default: 9915 codec->fixup_id = QUIRK_SBZ; 9916 break; 9917 } 9918 } 9919 9920 static void ca0132_generic_init_hook(struct hda_codec *codec) 9921 { 9922 struct ca0132_spec *spec = codec->spec; 9923 9924 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9925 } 9926 9927 static int ca0132_generic_probe(struct hda_codec *codec) 9928 { 9929 struct ca0132_spec *spec = codec->spec; 9930 struct auto_pin_cfg *cfg = &spec->gen.autocfg; 9931 int err; 9932 9933 snd_hda_gen_spec_init(&spec->gen); 9934 9935 snd_hda_apply_pincfgs(codec, ca0132_generic_pincfgs); 9936 9937 ca0132_init_chip(codec); 9938 9939 err = ca0132_prepare_verbs(codec); 9940 if (err < 0) 9941 return err; 9942 9943 err = snd_hda_parse_pin_def_config(codec, cfg, NULL); 9944 if (err < 0) 9945 return err; 9946 err = snd_hda_gen_parse_auto_config(codec, cfg); 9947 if (err < 0) 9948 return err; 9949 9950 spec->gen.init_hook = ca0132_generic_init_hook; 9951 spec->gen.automute_speaker = 0; 9952 spec->gen.automute_lo = 0; 9953 9954 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9955 return 0; 9956 } 9957 9958 static void ca0132_codec_remove(struct hda_codec *codec) 9959 { 9960 struct ca0132_spec *spec = codec->spec; 9961 9962 switch (ca0132_quirk(spec)) { 9963 case QUIRK_GENERIC: 9964 snd_hda_gen_remove(codec); 9965 return; 9966 case QUIRK_ZXR_DBPRO: 9967 return dbpro_free(codec); 9968 default: 9969 return ca0132_free(codec); 9970 } 9971 } 9972 9973 static int ca0132_codec_probe(struct hda_codec *codec, 9974 const struct hda_device_id *id) 9975 { 9976 struct ca0132_spec *spec; 9977 int err; 9978 9979 codec_dbg(codec, "%s\n", __func__); 9980 9981 spec = kzalloc_obj(*spec); 9982 if (!spec) 9983 return -ENOMEM; 9984 codec->spec = spec; 9985 spec->codec = codec; 9986 9987 /* These must be set before any path is taken */ 9988 codec->pcm_format_first = 1; 9989 codec->no_sticky_stream = 1; 9990 9991 /* Detect codec quirk */ 9992 snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL); 9993 switch (ca0132_quirk(spec)) { 9994 case QUIRK_SBZ: 9995 sbz_detect_quirk(codec); 9996 break; 9997 case QUIRK_GENERIC: 9998 return ca0132_generic_probe(codec); 9999 default: 10000 break; 10001 } 10002 10003 spec->dsp_state = DSP_DOWNLOAD_INIT; 10004 spec->num_mixers = 1; 10005 10006 /* Set which mixers each quirk uses. */ 10007 switch (ca0132_quirk(spec)) { 10008 case QUIRK_SBZ: 10009 spec->mixers[0] = desktop_mixer; 10010 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 10011 break; 10012 case QUIRK_ZXR: 10013 spec->mixers[0] = desktop_mixer; 10014 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 10015 break; 10016 case QUIRK_ZXR_DBPRO: 10017 break; 10018 case QUIRK_R3D: 10019 spec->mixers[0] = desktop_mixer; 10020 snd_hda_codec_set_name(codec, "Recon3D"); 10021 break; 10022 case QUIRK_R3DI: 10023 spec->mixers[0] = r3di_mixer; 10024 snd_hda_codec_set_name(codec, "Recon3Di"); 10025 break; 10026 case QUIRK_AE5: 10027 spec->mixers[0] = desktop_mixer; 10028 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 10029 break; 10030 case QUIRK_AE7: 10031 spec->mixers[0] = desktop_mixer; 10032 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 10033 break; 10034 default: 10035 spec->mixers[0] = ca0132_mixer; 10036 break; 10037 } 10038 10039 /* Setup whether or not to use alt functions/controls/pci_mmio */ 10040 switch (ca0132_quirk(spec)) { 10041 case QUIRK_SBZ: 10042 case QUIRK_R3D: 10043 case QUIRK_AE5: 10044 case QUIRK_AE7: 10045 case QUIRK_ZXR: 10046 spec->use_alt_controls = true; 10047 spec->use_alt_functions = true; 10048 spec->use_pci_mmio = true; 10049 break; 10050 case QUIRK_R3DI: 10051 spec->use_alt_controls = true; 10052 spec->use_alt_functions = true; 10053 spec->use_pci_mmio = false; 10054 break; 10055 default: 10056 spec->use_alt_controls = false; 10057 spec->use_alt_functions = false; 10058 spec->use_pci_mmio = false; 10059 break; 10060 } 10061 10062 #ifdef CONFIG_PCI 10063 if (spec->use_pci_mmio) { 10064 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 10065 if (spec->mem_base == NULL) { 10066 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 10067 codec->fixup_id = QUIRK_NONE; 10068 } 10069 } 10070 #endif 10071 10072 spec->base_init_verbs = ca0132_base_init_verbs; 10073 spec->base_exit_verbs = ca0132_base_exit_verbs; 10074 10075 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 10076 10077 ca0132_init_chip(codec); 10078 10079 ca0132_config(codec); 10080 10081 err = ca0132_prepare_verbs(codec); 10082 if (err < 0) 10083 goto error; 10084 10085 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 10086 if (err < 0) 10087 goto error; 10088 10089 ca0132_setup_unsol(codec); 10090 10091 return 0; 10092 10093 error: 10094 ca0132_codec_remove(codec); 10095 return err; 10096 } 10097 10098 static int ca0132_codec_build_controls(struct hda_codec *codec) 10099 { 10100 struct ca0132_spec *spec = codec->spec; 10101 10102 switch (ca0132_quirk(spec)) { 10103 case QUIRK_GENERIC: 10104 return snd_hda_gen_build_controls(codec); 10105 case QUIRK_ZXR_DBPRO: 10106 return dbpro_build_controls(codec); 10107 default: 10108 return ca0132_build_controls(codec); 10109 } 10110 } 10111 10112 static int ca0132_codec_build_pcms(struct hda_codec *codec) 10113 { 10114 struct ca0132_spec *spec = codec->spec; 10115 10116 switch (ca0132_quirk(spec)) { 10117 case QUIRK_GENERIC: 10118 return snd_hda_gen_build_pcms(codec); 10119 case QUIRK_ZXR_DBPRO: 10120 return dbpro_build_pcms(codec); 10121 default: 10122 return ca0132_build_pcms(codec); 10123 } 10124 } 10125 10126 static int ca0132_codec_init(struct hda_codec *codec) 10127 { 10128 struct ca0132_spec *spec = codec->spec; 10129 10130 switch (ca0132_quirk(spec)) { 10131 case QUIRK_GENERIC: 10132 return snd_hda_gen_init(codec); 10133 case QUIRK_ZXR_DBPRO: 10134 return dbpro_init(codec); 10135 default: 10136 return ca0132_init(codec); 10137 } 10138 } 10139 10140 static int ca0132_codec_suspend(struct hda_codec *codec) 10141 { 10142 struct ca0132_spec *spec = codec->spec; 10143 10144 if (ca0132_quirk(spec) == QUIRK_GENERIC) 10145 return 0; 10146 10147 cancel_delayed_work_sync(&spec->unsol_hp_work); 10148 return 0; 10149 } 10150 10151 static const struct hda_codec_ops ca0132_codec_ops = { 10152 .probe = ca0132_codec_probe, 10153 .remove = ca0132_codec_remove, 10154 .build_controls = ca0132_codec_build_controls, 10155 .build_pcms = ca0132_codec_build_pcms, 10156 .init = ca0132_codec_init, 10157 .unsol_event = snd_hda_jack_unsol_event, 10158 .suspend = ca0132_codec_suspend, 10159 }; 10160 10161 /* 10162 * driver entries 10163 */ 10164 static const struct hda_device_id snd_hda_id_ca0132[] = { 10165 HDA_CODEC_ID(0x11020011, "CA0132"), 10166 {} /* terminator */ 10167 }; 10168 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 10169 10170 MODULE_LICENSE("GPL"); 10171 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 10172 10173 static struct hda_codec_driver ca0132_driver = { 10174 .id = snd_hda_id_ca0132, 10175 .ops = &ca0132_codec_ops, 10176 }; 10177 10178 module_hda_codec_driver(ca0132_driver); 10179