1 /* 2 * Copyright 2012-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_ddc_types.h" 36 #include "dc_dp_types.h" 37 #include "dc_hdmi_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 #include "grph_object_ctrl_defs.h" 42 43 #include "dm_cp_psp.h" 44 45 /* forward declarations */ 46 struct dc_plane_state; 47 struct dc_stream_state; 48 struct dc_link; 49 struct dc_sink; 50 struct dal; 51 struct dc_dmub_srv; 52 53 /******************************** 54 * Environment definitions 55 ********************************/ 56 enum dce_environment { 57 DCE_ENV_PRODUCTION_DRV = 0, 58 /* Emulation on FPGA, in "Maximus" System. 59 * This environment enforces that *only* DC registers accessed. 60 * (access to non-DC registers will hang FPGA) */ 61 DCE_ENV_FPGA_MAXIMUS, 62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 63 * requirements of Diagnostics team. */ 64 DCE_ENV_DIAG, 65 /* 66 * Guest VM system, DC HW may exist but is not virtualized and 67 * should not be used. SW support for VDI only. 68 */ 69 DCE_ENV_VIRTUAL_HW 70 }; 71 72 struct dc_perf_trace { 73 unsigned long read_count; 74 unsigned long write_count; 75 unsigned long last_entry_read; 76 unsigned long last_entry_write; 77 }; 78 79 #define NUM_PIXEL_FORMATS 10 80 81 enum tiling_mode { 82 TILING_MODE_INVALID, 83 TILING_MODE_LINEAR, 84 TILING_MODE_TILED, 85 TILING_MODE_COUNT 86 }; 87 88 enum view_3d_format { 89 VIEW_3D_FORMAT_NONE = 0, 90 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 91 VIEW_3D_FORMAT_SIDE_BY_SIDE, 92 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 93 VIEW_3D_FORMAT_COUNT, 94 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 95 }; 96 97 enum plane_stereo_format { 98 PLANE_STEREO_FORMAT_NONE = 0, 99 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 100 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 101 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 102 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 103 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 104 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 105 }; 106 107 /* TODO: Find way to calculate number of bits 108 * Please increase if pixel_format enum increases 109 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 110 */ 111 112 enum dc_edid_connector_type { 113 DC_EDID_CONNECTOR_UNKNOWN = 0, 114 DC_EDID_CONNECTOR_ANALOG = 1, 115 DC_EDID_CONNECTOR_DIGITAL = 10, 116 DC_EDID_CONNECTOR_DVI = 11, 117 DC_EDID_CONNECTOR_HDMIA = 12, 118 DC_EDID_CONNECTOR_MDDI = 14, 119 DC_EDID_CONNECTOR_DISPLAYPORT = 15 120 }; 121 122 enum dc_edid_status { 123 EDID_OK, 124 EDID_BAD_INPUT, 125 EDID_NO_RESPONSE, 126 EDID_BAD_CHECKSUM, 127 EDID_THE_SAME, 128 EDID_FALL_BACK, 129 EDID_PARTIAL_VALID, 130 }; 131 132 enum act_return_status { 133 ACT_SUCCESS, 134 ACT_LINK_LOST, 135 ACT_FAILED 136 }; 137 138 /* audio capability from EDID*/ 139 struct dc_cea_audio_mode { 140 uint8_t format_code; /* ucData[0] [6:3]*/ 141 uint8_t channel_count; /* ucData[0] [2:0]*/ 142 uint8_t sample_rate; /* ucData[1]*/ 143 union { 144 uint8_t sample_size; /* for LPCM*/ 145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 146 uint8_t max_bit_rate; 147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 148 }; 149 }; 150 151 struct dc_edid { 152 uint32_t length; 153 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 154 }; 155 156 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 157 * is used. In this case we assume speaker location are: front left, front 158 * right and front center. */ 159 #define DEFAULT_SPEAKER_LOCATION 5 160 161 #define DC_MAX_AUDIO_DESC_COUNT 16 162 163 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 164 165 struct dc_panel_patch { 166 unsigned int dppowerup_delay; 167 unsigned int extra_t12_ms; 168 unsigned int extra_delay_backlight_off; 169 unsigned int extra_t7_ms; 170 unsigned int skip_scdc_overwrite; 171 unsigned int delay_ignore_msa; 172 unsigned int disable_fec; 173 unsigned int extra_t3_ms; 174 unsigned int max_dsc_target_bpp_limit; 175 unsigned int embedded_tiled_slave; 176 unsigned int disable_fams; 177 unsigned int skip_avmute; 178 unsigned int skip_audio_sab_check; 179 unsigned int mst_start_top_delay; 180 unsigned int remove_sink_ext_caps; 181 unsigned int disable_colorimetry; 182 uint8_t blankstream_before_otg_off; 183 bool oled_optimize_display_on; 184 unsigned int force_mst_blocked_discovery; 185 unsigned int wait_after_dpcd_poweroff_ms; 186 }; 187 188 /** 189 * struct dc_edid_caps - Capabilities read from EDID. 190 * @analog: Whether the monitor is analog. Used by DVI-I handling. 191 */ 192 struct dc_edid_caps { 193 /* sink identification */ 194 uint16_t manufacturer_id; 195 uint16_t product_id; 196 uint32_t serial_number; 197 uint8_t manufacture_week; 198 uint8_t manufacture_year; 199 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 200 201 /* audio caps */ 202 uint8_t speaker_flags; 203 uint32_t audio_mode_count; 204 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 205 uint32_t audio_latency; 206 uint32_t video_latency; 207 208 unsigned char freesync_vcp_code; 209 210 uint8_t qs_bit; 211 uint8_t qy_bit; 212 213 uint32_t max_tmds_clk_mhz; 214 215 /*HDMI 2.0 caps*/ 216 bool lte_340mcsc_scramble; 217 218 bool edid_hdmi; 219 bool hdr_supported; 220 bool rr_capable; 221 bool scdc_present; 222 bool analog; 223 224 struct dc_panel_patch panel_patch; 225 }; 226 227 struct dc_mode_flags { 228 /* note: part of refresh rate flag*/ 229 uint32_t INTERLACE :1; 230 /* native display timing*/ 231 uint32_t NATIVE :1; 232 /* preferred is the recommended mode, one per display */ 233 uint32_t PREFERRED :1; 234 /* true if this mode should use reduced blanking timings 235 *_not_ related to the Reduced Blanking adjustment*/ 236 uint32_t REDUCED_BLANKING :1; 237 /* note: part of refreshrate flag*/ 238 uint32_t VIDEO_OPTIMIZED_RATE :1; 239 /* should be reported to upper layers as mode_flags*/ 240 uint32_t PACKED_PIXEL_FORMAT :1; 241 /*< preferred view*/ 242 uint32_t PREFERRED_VIEW :1; 243 /* this timing should be used only in tiled mode*/ 244 uint32_t TILED_MODE :1; 245 uint32_t DSE_MODE :1; 246 /* Refresh rate divider when Miracast sink is using a 247 different rate than the output display device 248 Must be zero for wired displays and non-zero for 249 Miracast displays*/ 250 uint32_t MIRACAST_REFRESH_DIVIDER; 251 }; 252 253 254 enum dc_timing_source { 255 TIMING_SOURCE_UNDEFINED, 256 257 /* explicitly specifed by user, most important*/ 258 TIMING_SOURCE_USER_FORCED, 259 TIMING_SOURCE_USER_OVERRIDE, 260 TIMING_SOURCE_CUSTOM, 261 TIMING_SOURCE_EXPLICIT, 262 263 /* explicitly specified by the display device, more important*/ 264 TIMING_SOURCE_EDID_CEA_SVD_3D, 265 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 266 TIMING_SOURCE_EDID_CEA_SVD_420, 267 TIMING_SOURCE_EDID_DETAILED, 268 TIMING_SOURCE_EDID_ESTABLISHED, 269 TIMING_SOURCE_EDID_STANDARD, 270 TIMING_SOURCE_EDID_CEA_SVD, 271 TIMING_SOURCE_EDID_CVT_3BYTE, 272 TIMING_SOURCE_EDID_4BYTE, 273 TIMING_SOURCE_EDID_CEA_DISPLAYID_VTDB, 274 TIMING_SOURCE_EDID_CEA_RID, 275 TIMING_SOURCE_EDID_DISPLAYID_TYPE5, 276 TIMING_SOURCE_VBIOS, 277 TIMING_SOURCE_CV, 278 TIMING_SOURCE_TV, 279 TIMING_SOURCE_HDMI_VIC, 280 TIMING_SOURCE_CEA_VIC, 281 282 /* implicitly specified by display device, still safe but less important*/ 283 TIMING_SOURCE_DEFAULT, 284 285 /* only used for custom base modes */ 286 TIMING_SOURCE_CUSTOM_BASE, 287 288 /* these timing might not work, least important*/ 289 TIMING_SOURCE_RANGELIMIT, 290 TIMING_SOURCE_OS_FORCED, 291 TIMING_SOURCE_IMPLICIT, 292 293 /* only used by default mode list*/ 294 TIMING_SOURCE_BASICMODE, 295 296 TIMING_SOURCE_COUNT 297 }; 298 299 300 struct stereo_3d_features { 301 bool supported ; 302 bool allTimings ; 303 bool cloneMode ; 304 bool scaling ; 305 bool singleFrameSWPacked; 306 }; 307 308 enum dc_timing_support_method { 309 TIMING_SUPPORT_METHOD_UNDEFINED, 310 TIMING_SUPPORT_METHOD_EXPLICIT, 311 TIMING_SUPPORT_METHOD_IMPLICIT, 312 TIMING_SUPPORT_METHOD_NATIVE 313 }; 314 315 struct dc_mode_info { 316 uint32_t pixel_width; 317 uint32_t pixel_height; 318 uint32_t field_rate; 319 /* Vertical refresh rate for progressive modes. 320 * Field rate for interlaced modes.*/ 321 322 enum dc_timing_standard timing_standard; 323 enum dc_timing_source timing_source; 324 struct dc_mode_flags flags; 325 }; 326 327 enum dc_power_state { 328 DC_POWER_STATE_ON = 1, 329 DC_POWER_STATE_STANDBY, 330 DC_POWER_STATE_SUSPEND, 331 DC_POWER_STATE_OFF 332 }; 333 334 /* DC PowerStates */ 335 enum dc_video_power_state { 336 DC_VIDEO_POWER_UNSPECIFIED = 0, 337 DC_VIDEO_POWER_ON = 1, 338 DC_VIDEO_POWER_STANDBY, 339 DC_VIDEO_POWER_SUSPEND, 340 DC_VIDEO_POWER_OFF, 341 DC_VIDEO_POWER_HIBERNATE, 342 DC_VIDEO_POWER_SHUTDOWN, 343 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 344 DC_VIDEO_POWER_AFTER_RESET, 345 DC_VIDEO_POWER_MAXIMUM 346 }; 347 348 enum dc_acpi_cm_power_state { 349 DC_ACPI_CM_POWER_STATE_D0 = 1, 350 DC_ACPI_CM_POWER_STATE_D1 = 2, 351 DC_ACPI_CM_POWER_STATE_D2 = 4, 352 DC_ACPI_CM_POWER_STATE_D3 = 8 353 }; 354 355 enum dc_connection_type { 356 dc_connection_none, 357 dc_connection_single, 358 dc_connection_mst_branch, 359 dc_connection_sst_branch, 360 dc_connection_analog_load 361 }; 362 363 struct dc_csc_adjustments { 364 struct fixed31_32 contrast; 365 struct fixed31_32 saturation; 366 struct fixed31_32 brightness; 367 struct fixed31_32 hue; 368 }; 369 370 /* Scaling format */ 371 enum scaling_transformation { 372 SCALING_TRANSFORMATION_UNINITIALIZED, 373 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 374 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 375 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 376 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 377 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 378 SCALING_TRANSFORMATION_INVALID = 0x80000000, 379 380 /* Flag the first and last */ 381 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 382 SCALING_TRANSFORMATION_END = 383 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 384 }; 385 386 enum display_content_type { 387 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 388 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 389 DISPLAY_CONTENT_TYPE_PHOTO = 2, 390 DISPLAY_CONTENT_TYPE_CINEMA = 4, 391 DISPLAY_CONTENT_TYPE_GAME = 8 392 }; 393 394 enum cm_gamut_adjust_type { 395 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 396 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 397 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 398 }; 399 400 struct cm_grph_csc_adjustment { 401 struct fixed31_32 temperature_matrix[12]; 402 enum cm_gamut_adjust_type gamut_adjust_type; 403 enum cm_gamut_coef_format gamut_coef_format; 404 }; 405 406 /* writeback */ 407 struct dwb_stereo_params { 408 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 409 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 410 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 411 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 412 }; 413 414 struct dc_dwb_cnv_params { 415 unsigned int src_width; /* input active width */ 416 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 417 unsigned int crop_width; /* cropped window width at cnv output */ 418 bool crop_en; /* window cropping enable in cnv */ 419 unsigned int crop_height; /* cropped window height at cnv output */ 420 unsigned int crop_x; /* cropped window start x value at cnv output */ 421 unsigned int crop_y; /* cropped window start y value at cnv output */ 422 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 423 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 424 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 425 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 426 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 427 }; 428 429 struct dc_dwb_params { 430 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 431 unsigned int hdr_mult; /* must be in FP1.6.12 */ 432 struct cm_grph_csc_adjustment csc_params; 433 struct dwb_stereo_params stereo_params; 434 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 435 unsigned int dest_width; /* Destination width */ 436 unsigned int dest_height; /* Destination height */ 437 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 438 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 439 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 440 struct scaling_taps scaler_taps; /* Scaling taps */ 441 enum dwb_subsample_position subsample_position; 442 const struct dc_transfer_func *out_transfer_func; 443 }; 444 445 /* audio*/ 446 447 union audio_sample_rates { 448 struct sample_rates { 449 uint8_t RATE_32:1; 450 uint8_t RATE_44_1:1; 451 uint8_t RATE_48:1; 452 uint8_t RATE_88_2:1; 453 uint8_t RATE_96:1; 454 uint8_t RATE_176_4:1; 455 uint8_t RATE_192:1; 456 } rate; 457 458 uint8_t all; 459 }; 460 461 struct audio_speaker_flags { 462 uint32_t FL_FR:1; 463 uint32_t LFE:1; 464 uint32_t FC:1; 465 uint32_t RL_RR:1; 466 uint32_t RC:1; 467 uint32_t FLC_FRC:1; 468 uint32_t RLC_RRC:1; 469 uint32_t SUPPORT_AI:1; 470 }; 471 472 struct audio_speaker_info { 473 uint32_t ALLSPEAKERS:7; 474 uint32_t SUPPORT_AI:1; 475 }; 476 477 478 struct audio_info_flags { 479 480 union { 481 482 struct audio_speaker_flags speaker_flags; 483 struct audio_speaker_info info; 484 485 uint8_t all; 486 }; 487 }; 488 489 enum audio_format_code { 490 AUDIO_FORMAT_CODE_FIRST = 1, 491 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 492 493 AUDIO_FORMAT_CODE_AC3, 494 /*Layers 1 & 2 */ 495 AUDIO_FORMAT_CODE_MPEG1, 496 /*MPEG1 Layer 3 */ 497 AUDIO_FORMAT_CODE_MP3, 498 /*multichannel */ 499 AUDIO_FORMAT_CODE_MPEG2, 500 AUDIO_FORMAT_CODE_AAC, 501 AUDIO_FORMAT_CODE_DTS, 502 AUDIO_FORMAT_CODE_ATRAC, 503 AUDIO_FORMAT_CODE_1BITAUDIO, 504 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 505 AUDIO_FORMAT_CODE_DTS_HD, 506 AUDIO_FORMAT_CODE_MAT_MLP, 507 AUDIO_FORMAT_CODE_DST, 508 AUDIO_FORMAT_CODE_WMAPRO, 509 AUDIO_FORMAT_CODE_LAST, 510 AUDIO_FORMAT_CODE_COUNT = 511 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 512 }; 513 514 struct audio_mode { 515 /* ucData[0] [6:3] */ 516 enum audio_format_code format_code; 517 /* ucData[0] [2:0] */ 518 uint8_t channel_count; 519 /* ucData[1] */ 520 union audio_sample_rates sample_rates; 521 union { 522 /* for LPCM */ 523 uint8_t sample_size; 524 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 525 uint8_t max_bit_rate; 526 /* for Audio Formats 9-15 */ 527 uint8_t vendor_specific; 528 }; 529 }; 530 531 struct audio_info { 532 struct audio_info_flags flags; 533 uint32_t video_latency; 534 uint32_t audio_latency; 535 uint32_t display_index; 536 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 537 uint32_t manufacture_id; 538 uint32_t product_id; 539 /* PortID used for ContainerID when defined */ 540 uint32_t port_id[2]; 541 uint32_t mode_count; 542 /* this field must be last in this struct */ 543 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 544 }; 545 struct audio_check { 546 unsigned int audio_packet_type; 547 unsigned int max_audiosample_rate; 548 unsigned int acat; 549 }; 550 enum dc_infoframe_type { 551 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 552 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 553 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 554 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 555 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 556 }; 557 558 struct dc_info_packet { 559 bool valid; 560 uint8_t hb0; 561 uint8_t hb1; 562 uint8_t hb2; 563 uint8_t hb3; 564 uint8_t sb[32]; 565 }; 566 567 struct dc_info_packet_128 { 568 bool valid; 569 uint8_t hb0; 570 uint8_t hb1; 571 uint8_t hb2; 572 uint8_t hb3; 573 uint8_t sb[128]; 574 }; 575 576 struct dc_edid_read_policy { 577 uint32_t max_retry_count; 578 uint32_t delay_time_ms; 579 uint32_t ignore_checksum; 580 }; 581 582 #define DC_PLANE_UPDATE_TIMES_MAX 10 583 584 struct dc_plane_flip_time { 585 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 586 unsigned int index; 587 unsigned int prev_update_time_in_us; 588 }; 589 590 enum dc_alpm_mode { 591 DC_ALPM_AUXWAKE = 0, 592 DC_ALPM_AUXLESS = 1, 593 DC_ALPM_UNSUPPORTED = 0xF, 594 }; 595 596 enum dc_psr_state { 597 PSR_STATE0 = 0x0, 598 PSR_STATE1, 599 PSR_STATE1a, 600 PSR_STATE2, 601 PSR_STATE2a, 602 PSR_STATE2b, 603 PSR_STATE3, 604 PSR_STATE3Init, 605 PSR_STATE4, 606 PSR_STATE4a, 607 PSR_STATE4b, 608 PSR_STATE4c, 609 PSR_STATE4d, 610 PSR_STATE4_FULL_FRAME, 611 PSR_STATE4a_FULL_FRAME, 612 PSR_STATE4b_FULL_FRAME, 613 PSR_STATE4c_FULL_FRAME, 614 PSR_STATE4_FULL_FRAME_POWERUP, 615 PSR_STATE4_FULL_FRAME_HW_LOCK, 616 PSR_STATE5, 617 PSR_STATE5a, 618 PSR_STATE5b, 619 PSR_STATE5c, 620 PSR_STATE_HWLOCK_MGR, 621 PSR_STATE_POLLVUPDATE, 622 PSR_STATE_RELEASE_HWLOCK_MGR_FULL_FRAME, 623 PSR_STATE_INVALID = 0xFF 624 }; 625 626 struct psr_config { 627 unsigned char psr_version; 628 unsigned int psr_rfb_setup_time; 629 bool psr_exit_link_training_required; 630 bool psr_frame_capture_indication_req; 631 unsigned int psr_sdp_transmit_line_num_deadline; 632 bool allow_smu_optimizations; 633 bool allow_multi_disp_optimizations; 634 /* Panel self refresh 2 selective update granularity required */ 635 bool su_granularity_required; 636 /* psr2 selective update y granularity capability */ 637 uint8_t su_y_granularity; 638 unsigned int line_time_in_us; 639 uint8_t rate_control_caps; 640 uint16_t dsc_slice_height; 641 bool os_request_force_ffu; 642 }; 643 644 union dmcu_psr_level { 645 struct { 646 unsigned int SKIP_CRC:1; 647 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 648 unsigned int SKIP_PHY_POWER_DOWN:1; 649 unsigned int SKIP_AUX_ACK_CHECK:1; 650 unsigned int SKIP_CRTC_DISABLE:1; 651 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 652 unsigned int SKIP_SMU_NOTIFICATION:1; 653 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 654 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 655 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 656 unsigned int DISABLE_ALPM:1; 657 unsigned int ALPM_DEFAULT_PD_MODE:1; 658 unsigned int RESERVED:20; 659 } bits; 660 unsigned int u32all; 661 }; 662 663 enum physical_phy_id { 664 PHYLD_0, 665 PHYLD_1, 666 PHYLD_2, 667 PHYLD_3, 668 PHYLD_4, 669 PHYLD_5, 670 PHYLD_6, 671 PHYLD_7, 672 PHYLD_8, 673 PHYLD_9, 674 PHYLD_COUNT, 675 PHYLD_UNKNOWN = (-1L) 676 }; 677 678 enum phy_type { 679 PHY_TYPE_UNKNOWN = 1, 680 PHY_TYPE_PCIE_PHY = 2, 681 PHY_TYPE_UNIPHY = 3, 682 }; 683 684 struct psr_context { 685 /* ddc line */ 686 enum channel_id channel; 687 /* Transmitter id */ 688 enum transmitter transmitterId; 689 /* Engine Id is used for Dig Be source select */ 690 enum engine_id engineId; 691 /* Controller Id used for Dig Fe source select */ 692 enum controller_id controllerId; 693 /* Pcie or Uniphy */ 694 enum phy_type phyType; 695 /* Physical PHY Id used by SMU interpretation */ 696 enum physical_phy_id smuPhyId; 697 /* Vertical total pixels from crtc timing. 698 * This is used for static screen detection. 699 * ie. If we want to detect half a frame, 700 * we use this to determine the hyst lines. 701 */ 702 unsigned int crtcTimingVerticalTotal; 703 /* PSR supported from panel capabilities and 704 * current display configuration 705 */ 706 bool psrSupportedDisplayConfig; 707 /* Whether fast link training is supported by the panel */ 708 bool psrExitLinkTrainingRequired; 709 /* If RFB setup time is greater than the total VBLANK time, 710 * it is not possible for the sink to capture the video frame 711 * in the same frame the SDP is sent. In this case, 712 * the frame capture indication bit should be set and an extra 713 * static frame should be transmitted to the sink. 714 */ 715 bool psrFrameCaptureIndicationReq; 716 /* Set the last possible line SDP may be transmitted without violating 717 * the RFB setup time or entering the active video frame. 718 */ 719 unsigned int sdpTransmitLineNumDeadline; 720 /* The VSync rate in Hz used to calculate the 721 * step size for smooth brightness feature 722 */ 723 unsigned int vsync_rate_hz; 724 unsigned int skipPsrWaitForPllLock; 725 unsigned int numberOfControllers; 726 /* Unused, for future use. To indicate that first changed frame from 727 * state3 shouldn't result in psr_inactive, but rather to perform 728 * an automatic single frame rfb_update. 729 */ 730 bool rfb_update_auto_en; 731 /* Number of frame before entering static screen */ 732 unsigned int timehyst_frames; 733 /* Partial frames before entering static screen */ 734 unsigned int hyst_lines; 735 /* # of repeated AUX transaction attempts to make before 736 * indicating failure to the driver 737 */ 738 unsigned int aux_repeats; 739 /* Controls hw blocks to power down during PSR active state */ 740 union dmcu_psr_level psr_level; 741 /* Controls additional delay after remote frame capture before 742 * continuing powerd own 743 */ 744 unsigned int frame_delay; 745 bool allow_smu_optimizations; 746 bool allow_multi_disp_optimizations; 747 /* Panel self refresh 2 selective update granularity required */ 748 bool su_granularity_required; 749 /* psr2 selective update y granularity capability */ 750 uint8_t su_y_granularity; 751 unsigned int line_time_in_us; 752 uint8_t rate_control_caps; 753 uint16_t dsc_slice_height; 754 bool os_request_force_ffu; 755 }; 756 757 struct colorspace_transform { 758 struct fixed31_32 matrix[12]; 759 bool enable_remap; 760 }; 761 762 enum i2c_mot_mode { 763 I2C_MOT_UNDEF, 764 I2C_MOT_TRUE, 765 I2C_MOT_FALSE 766 }; 767 768 struct AsicStateEx { 769 unsigned int memoryClock; 770 unsigned int displayClock; 771 unsigned int engineClock; 772 unsigned int maxSupportedDppClock; 773 unsigned int dppClock; 774 unsigned int socClock; 775 unsigned int dcfClockDeepSleep; 776 unsigned int fClock; 777 unsigned int phyClock; 778 }; 779 780 781 enum dc_clock_type { 782 DC_CLOCK_TYPE_DISPCLK = 0, 783 DC_CLOCK_TYPE_DPPCLK = 1, 784 }; 785 786 struct dc_clock_config { 787 uint32_t max_clock_khz; 788 uint32_t min_clock_khz; 789 uint32_t bw_requirequired_clock_khz; 790 uint32_t current_clock_khz;/*current clock in use*/ 791 }; 792 793 struct hw_asic_id { 794 uint32_t chip_id; 795 uint32_t chip_family; 796 uint32_t pci_revision_id; 797 uint32_t hw_internal_rev; 798 uint32_t vram_type; 799 uint32_t vram_width; 800 uint32_t feature_flags; 801 uint32_t fake_paths_num; 802 void *atombios_base_address; 803 }; 804 805 struct dc_context { 806 struct dc *dc; 807 808 void *driver_context; /* e.g. amdgpu_device */ 809 struct dal_logger *logger; 810 struct dc_perf_trace *perf_trace; 811 void *cgs_device; 812 813 enum dce_environment dce_environment; 814 struct hw_asic_id asic_id; 815 816 /* todo: below should probably move to dc. to facilitate removal 817 * of AS we will store these here 818 */ 819 enum dce_version dce_version; 820 struct dc_bios *dc_bios; 821 bool created_bios; 822 struct gpio_service *gpio_service; 823 uint32_t dc_sink_id_count; 824 uint32_t dc_stream_id_count; 825 uint32_t dc_edp_id_count; 826 uint64_t fbc_gpu_addr; 827 struct dc_dmub_srv *dmub_srv; 828 struct cp_psp cp_psp; 829 uint32_t *dcn_reg_offsets; 830 uint32_t *nbio_reg_offsets; 831 uint32_t *clk_reg_offsets; 832 }; 833 834 /* DSC DPCD capabilities */ 835 union dsc_slice_caps1 { 836 struct { 837 uint8_t NUM_SLICES_1 : 1; 838 uint8_t NUM_SLICES_2 : 1; 839 uint8_t RESERVED : 1; 840 uint8_t NUM_SLICES_4 : 1; 841 uint8_t NUM_SLICES_6 : 1; 842 uint8_t NUM_SLICES_8 : 1; 843 uint8_t NUM_SLICES_10 : 1; 844 uint8_t NUM_SLICES_12 : 1; 845 } bits; 846 uint8_t raw; 847 }; 848 849 union dsc_slice_caps2 { 850 struct { 851 uint8_t NUM_SLICES_16 : 1; 852 uint8_t NUM_SLICES_20 : 1; 853 uint8_t NUM_SLICES_24 : 1; 854 uint8_t RESERVED : 5; 855 } bits; 856 uint8_t raw; 857 }; 858 859 union dsc_color_formats { 860 struct { 861 uint8_t RGB : 1; 862 uint8_t YCBCR_444 : 1; 863 uint8_t YCBCR_SIMPLE_422 : 1; 864 uint8_t YCBCR_NATIVE_422 : 1; 865 uint8_t YCBCR_NATIVE_420 : 1; 866 uint8_t RESERVED : 3; 867 } bits; 868 uint8_t raw; 869 }; 870 871 union dsc_color_depth { 872 struct { 873 uint8_t RESERVED1 : 1; 874 uint8_t COLOR_DEPTH_8_BPC : 1; 875 uint8_t COLOR_DEPTH_10_BPC : 1; 876 uint8_t COLOR_DEPTH_12_BPC : 1; 877 uint8_t RESERVED2 : 3; 878 } bits; 879 uint8_t raw; 880 }; 881 882 struct dsc_dec_dpcd_caps { 883 bool is_dsc_supported; 884 uint8_t dsc_version; 885 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 886 union dsc_slice_caps1 slice_caps1; 887 union dsc_slice_caps2 slice_caps2; 888 int32_t lb_bit_depth; 889 bool is_block_pred_supported; 890 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 891 union dsc_color_formats color_formats; 892 union dsc_color_depth color_depth; 893 int32_t throughput_mode_0_mps; /* In MPs */ 894 int32_t throughput_mode_1_mps; /* In MPs */ 895 int32_t max_slice_width; 896 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 897 898 /* Extended DSC caps */ 899 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 900 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 901 uint32_t branch_max_line_width; 902 bool is_dp; /* Decoded format */ 903 }; 904 905 struct hblank_expansion_dpcd_caps { 906 bool expansion_supported; 907 bool reduction_supported; 908 bool buffer_unit_bytes; /* True: buffer size in bytes. False: buffer size in pixels*/ 909 bool buffer_per_port; /* True: buffer size per port. False: buffer size per lane*/ 910 uint32_t buffer_size; /* Add 1 to value and multiply by 32 */ 911 }; 912 913 struct dc_golden_table { 914 uint16_t dc_golden_table_ver; 915 uint32_t aux_dphy_rx_control0_val; 916 uint32_t aux_dphy_tx_control_val; 917 uint32_t aux_dphy_rx_control1_val; 918 uint32_t dc_gpio_aux_ctrl_0_val; 919 uint32_t dc_gpio_aux_ctrl_1_val; 920 uint32_t dc_gpio_aux_ctrl_2_val; 921 uint32_t dc_gpio_aux_ctrl_3_val; 922 uint32_t dc_gpio_aux_ctrl_4_val; 923 uint32_t dc_gpio_aux_ctrl_5_val; 924 }; 925 926 enum dc_gpu_mem_alloc_type { 927 DC_MEM_ALLOC_TYPE_GART, 928 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 929 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 930 DC_MEM_ALLOC_TYPE_AGP 931 }; 932 933 enum dc_link_encoding_format { 934 DC_LINK_ENCODING_UNSPECIFIED = 0, 935 DC_LINK_ENCODING_DP_8b_10b, 936 DC_LINK_ENCODING_DP_128b_132b, 937 DC_LINK_ENCODING_HDMI_TMDS, 938 DC_LINK_ENCODING_HDMI_FRL 939 }; 940 941 enum dc_psr_version { 942 DC_PSR_VERSION_1 = 0, 943 DC_PSR_VERSION_SU_1 = 1, 944 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 945 }; 946 947 enum dc_replay_version { 948 DC_FREESYNC_REPLAY = 0, 949 DC_VESA_PANEL_REPLAY = 1, 950 DC_REPLAY_VERSION_UNSUPPORTED = 0XFF, 951 }; 952 953 /* Possible values of display_endpoint_id.endpoint */ 954 enum display_endpoint_type { 955 DISPLAY_ENDPOINT_PHY = 0, /* Physical connector. */ 956 DISPLAY_ENDPOINT_USB4_DPIA, /* USB4 DisplayPort tunnel. */ 957 DISPLAY_ENDPOINT_UNKNOWN = -1 958 }; 959 960 /* Extends graphics_object_id with an additional member 'ep_type' for 961 * distinguishing between physical endpoints (with entries in BIOS connector table) and 962 * logical endpoints. 963 */ 964 struct display_endpoint_id { 965 struct graphics_object_id link_id; 966 enum display_endpoint_type ep_type; 967 }; 968 969 enum dc_panel_type { 970 PANEL_TYPE_NONE = 0, // UNKONWN, not determined yet 971 PANEL_TYPE_LCD = 1, 972 PANEL_TYPE_OLED = 2, 973 PANEL_TYPE_MINILED = 3, 974 }; 975 976 enum backlight_control_type { 977 BACKLIGHT_CONTROL_PWM = 0, 978 BACKLIGHT_CONTROL_VESA_AUX = 1, 979 BACKLIGHT_CONTROL_AMD_AUX = 2, 980 }; 981 982 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) 983 #define MAX_CRC_WINDOW_NUM 2 984 985 struct otg_phy_mux { 986 uint8_t phy_output_num; 987 uint8_t otg_output_num; 988 }; 989 990 struct crc_window { 991 struct rect rect; 992 bool enable; 993 }; 994 #endif 995 996 enum dc_detect_reason { 997 DETECT_REASON_BOOT, 998 DETECT_REASON_RESUMEFROMS3S4, 999 DETECT_REASON_HPD, 1000 DETECT_REASON_HPDRX, 1001 DETECT_REASON_FALLBACK, 1002 DETECT_REASON_RETRAIN, 1003 DETECT_REASON_TDR, 1004 }; 1005 1006 struct dc_link_status { 1007 bool link_active; 1008 struct dpcd_caps *dpcd_caps; 1009 }; 1010 1011 union hdcp_rx_caps { 1012 struct { 1013 uint8_t version; 1014 uint8_t reserved; 1015 struct { 1016 uint8_t repeater : 1; 1017 uint8_t hdcp_capable : 1; 1018 uint8_t reserved : 6; 1019 } byte0; 1020 } fields; 1021 uint8_t raw[3]; 1022 }; 1023 1024 union hdcp_bcaps { 1025 struct { 1026 uint8_t HDCP_CAPABLE:1; 1027 uint8_t REPEATER:1; 1028 uint8_t RESERVED:6; 1029 } bits; 1030 uint8_t raw; 1031 }; 1032 1033 struct hdcp_caps { 1034 union hdcp_rx_caps rx_caps; 1035 union hdcp_bcaps bcaps; 1036 }; 1037 1038 /* DP MST stream allocation (payload bandwidth number) */ 1039 struct link_mst_stream_allocation { 1040 /* DIG front */ 1041 const struct stream_encoder *stream_enc; 1042 /* HPO DP Stream Encoder */ 1043 const struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 1044 /* associate DRM payload table with DC stream encoder */ 1045 uint8_t vcp_id; 1046 /* number of slots required for the DP stream in transport packet */ 1047 uint8_t slot_count; 1048 }; 1049 1050 #define MAX_CONTROLLER_NUM 6 1051 1052 /* DP MST stream allocation table */ 1053 struct link_mst_stream_allocation_table { 1054 /* number of DP video streams */ 1055 int stream_count; 1056 /* array of stream allocations */ 1057 struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM]; 1058 }; 1059 1060 /* PSR feature flags */ 1061 struct psr_settings { 1062 bool psr_feature_enabled; // PSR is supported by sink 1063 bool psr_allow_active; // PSR is currently active 1064 enum dc_psr_version psr_version; // Internal PSR version, determined based on DPCD 1065 bool psr_vtotal_control_support; // Vtotal control is supported by sink 1066 unsigned long long psr_dirty_rects_change_timestamp_ns; // for delay of enabling PSR-SU 1067 1068 /* These parameters are calculated in Driver, 1069 * based on display timing and Sink capabilities. 1070 * If VBLANK region is too small and Sink takes a long time 1071 * to set up RFB, it may take an extra frame to enter PSR state. 1072 */ 1073 bool psr_frame_capture_indication_req; 1074 unsigned int psr_sdp_transmit_line_num_deadline; 1075 uint8_t force_ffu_mode; 1076 unsigned int psr_power_opt; 1077 1078 /** 1079 * Some panels cannot handle idle pattern during PSR entry. 1080 * To power down phy before disable stream to avoid sending 1081 * idle pattern. 1082 */ 1083 uint8_t power_down_phy_before_disable_stream; 1084 }; 1085 1086 enum replay_coasting_vtotal_type { 1087 PR_COASTING_TYPE_NOM = 0, 1088 PR_COASTING_TYPE_STATIC, 1089 PR_COASTING_TYPE_FULL_SCREEN_VIDEO, 1090 PR_COASTING_TYPE_TEST_HARNESS, 1091 PR_COASTING_TYPE_VIDEO_CONFERENCING_V2, 1092 PR_COASTING_TYPE_NUM, 1093 }; 1094 1095 enum replay_link_off_frame_count_level { 1096 PR_LINK_OFF_FRAME_COUNT_FAIL = 0x0, 1097 PR_LINK_OFF_FRAME_COUNT_GOOD = 0x2, 1098 PR_LINK_OFF_FRAME_COUNT_BEST = 0x6, 1099 }; 1100 1101 /* 1102 * This is general Interface for Replay to 1103 * set an 32 bit variable to dmub 1104 * The Message_type indicates which variable 1105 * passed to DMUB. 1106 */ 1107 enum replay_FW_Message_type { 1108 Replay_Msg_Not_Support = -1, 1109 Replay_Set_Timing_Sync_Supported, 1110 Replay_Set_Residency_Frameupdate_Timer, 1111 Replay_Set_Pseudo_VTotal, 1112 Replay_Disabled_Adaptive_Sync_SDP, 1113 Replay_Set_General_Cmd, 1114 }; 1115 1116 union replay_error_status { 1117 struct { 1118 unsigned int STATE_TRANSITION_ERROR :1; 1119 unsigned int LINK_CRC_ERROR :1; 1120 unsigned int DESYNC_ERROR :1; 1121 unsigned int RESERVED_3 :1; 1122 unsigned int LOW_RR_INCORRECT_VTOTAL :1; 1123 unsigned int NO_DOUBLED_RR :1; 1124 unsigned int RESERVED_6_7 :2; 1125 } bits; 1126 unsigned char raw; 1127 }; 1128 1129 union replay_low_refresh_rate_enable_options { 1130 struct { 1131 //BIT[0-3]: Replay Low Hz Support control 1132 unsigned int ENABLE_LOW_RR_SUPPORT :1; 1133 unsigned int SKIP_ASIC_CHECK :1; 1134 unsigned int RESERVED_2_3 :2; 1135 //BIT[4-15]: Replay Low Hz Enable Scenarios 1136 unsigned int ENABLE_STATIC_SCREEN :1; 1137 unsigned int ENABLE_FULL_SCREEN_VIDEO :1; 1138 unsigned int ENABLE_GENERAL_UI :1; 1139 unsigned int RESERVED_7_15 :9; 1140 //BIT[16-31]: Replay Low Hz Enable Check 1141 unsigned int ENABLE_STATIC_FLICKER_CHECK :1; 1142 unsigned int RESERVED_17_31 :15; 1143 } bits; 1144 unsigned int raw; 1145 }; 1146 1147 union replay_optimization { 1148 struct { 1149 //BIT[0-1]: Replay Teams Optimization 1150 unsigned int TEAMS_OPTIMIZATION_VER_1 :1; 1151 unsigned int TEAMS_OPTIMIZATION_VER_2 :1; 1152 //BIT[2]: Replay Live Capture with CVT 1153 unsigned int LIVE_CAPTURE_WITH_CVT :1; 1154 unsigned int RESERVED_3 :1; 1155 } bits; 1156 1157 unsigned int raw; 1158 }; 1159 1160 struct replay_config { 1161 /* Replay version */ 1162 enum dc_replay_version replay_version; 1163 /* Replay feature is supported */ 1164 bool replay_supported; 1165 /* Replay caps support DPCD & EDID caps*/ 1166 bool replay_cap_support; 1167 /* Power opt flags that are supported */ 1168 unsigned int replay_power_opt_supported; 1169 /* SMU optimization is supported */ 1170 bool replay_smu_opt_supported; 1171 /* Replay enablement option */ 1172 unsigned int replay_enable_option; 1173 /* Replay debug flags */ 1174 uint32_t debug_flags; 1175 /* Replay sync is supported */ 1176 bool replay_timing_sync_supported; 1177 /* Replay Disable desync error check. */ 1178 bool force_disable_desync_error_check; 1179 /* Replay Received Desync Error HPD. */ 1180 bool received_desync_error_hpd; 1181 /* Replay feature is supported long vblank */ 1182 bool replay_support_fast_resync_in_ultra_sleep_mode; 1183 /* Replay error status */ 1184 union replay_error_status replay_error_status; 1185 /* Replay Low Hz enable Options */ 1186 union replay_low_refresh_rate_enable_options low_rr_enable_options; 1187 /* Replay coasting vtotal is within low refresh rate range. */ 1188 bool low_rr_activated; 1189 /* Replay low refresh rate supported*/ 1190 bool low_rr_supported; 1191 /* Replay Video Conferencing Optimization Enabled */ 1192 bool replay_video_conferencing_optimization_enabled; 1193 /* Replay alpm mode */ 1194 enum dc_alpm_mode alpm_mode; 1195 /* Replay full screen only */ 1196 bool os_request_force_ffu; 1197 /* Replay optimization */ 1198 union replay_optimization replay_optimization; 1199 /* Replay sub feature Frame Skipping is supported */ 1200 bool frame_skip_supported; 1201 /* Replay Received Frame Skipping Error HPD. */ 1202 bool received_frame_skipping_error_hpd; 1203 /* Live capture with CVT is activated */ 1204 bool live_capture_with_cvt_activated; 1205 }; 1206 1207 /* Replay feature flags*/ 1208 struct replay_settings { 1209 /* Replay configuration */ 1210 struct replay_config config; 1211 /* Replay feature is ready for activating */ 1212 bool replay_feature_enabled; 1213 /* Replay is currently active */ 1214 bool replay_allow_active; 1215 /* Replay is currently active */ 1216 bool replay_allow_long_vblank; 1217 /* Power opt flags that are activated currently */ 1218 unsigned int replay_power_opt_active; 1219 /* SMU optimization is enabled */ 1220 bool replay_smu_opt_enable; 1221 /* Current Coasting vtotal */ 1222 uint32_t coasting_vtotal; 1223 /* Coasting vtotal table */ 1224 uint32_t coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1225 /* Defer Update Coasting vtotal table */ 1226 uint32_t defer_update_coasting_vtotal_table[PR_COASTING_TYPE_NUM]; 1227 /* Skip frame number table */ 1228 uint32_t frame_skip_number_table[PR_COASTING_TYPE_NUM]; 1229 /* Defer skip frame number table */ 1230 uint32_t defer_frame_skip_number_table[PR_COASTING_TYPE_NUM]; 1231 /* Maximum link off frame count */ 1232 uint32_t link_off_frame_count; 1233 /* Replay pseudo vtotal for low refresh rate*/ 1234 uint16_t low_rr_full_screen_video_pseudo_vtotal; 1235 /* Replay last pseudo vtotal set to DMUB */ 1236 uint16_t last_pseudo_vtotal; 1237 /* Replay desync error */ 1238 uint32_t replay_desync_error_fail_count; 1239 /* The frame skip number dal send to DMUB */ 1240 uint16_t frame_skip_number; 1241 /* Current Panel Replay events */ 1242 uint32_t replay_events; 1243 }; 1244 1245 /* To split out "global" and "per-panel" config settings. 1246 * Add a struct dc_panel_config under dc_link 1247 */ 1248 struct dc_panel_config { 1249 /* extra panel power sequence parameters */ 1250 struct pps { 1251 unsigned int extra_t3_ms; 1252 unsigned int extra_t7_ms; 1253 unsigned int extra_delay_backlight_off; 1254 unsigned int extra_post_t7_ms; 1255 unsigned int extra_pre_t11_ms; 1256 unsigned int extra_t12_ms; 1257 unsigned int extra_post_OUI_ms; 1258 } pps; 1259 /* nit brightness */ 1260 struct nits_brightness { 1261 unsigned int peak; /* nits */ 1262 unsigned int max_avg; /* nits */ 1263 unsigned int min; /* 1/10000 nits */ 1264 unsigned int max_nonboost_brightness_millinits; 1265 unsigned int min_brightness_millinits; 1266 } nits_brightness; 1267 /* PSR/Replay */ 1268 struct psr { 1269 bool disable_psr; 1270 bool disallow_psrsu; 1271 bool disallow_replay; 1272 bool rc_disable; 1273 bool rc_allow_static_screen; 1274 bool rc_allow_fullscreen_VPB; 1275 bool read_psrcap_again; 1276 unsigned int replay_enable_option; 1277 bool enable_frame_skipping; 1278 bool enable_teams_optimization; 1279 } psr; 1280 /* ABM */ 1281 struct varib { 1282 unsigned int varibright_feature_enable; 1283 unsigned int def_varibright_level; 1284 unsigned int abm_config_setting; 1285 } varib; 1286 /* edp DSC */ 1287 struct dsc { 1288 bool disable_dsc_edp; 1289 unsigned int force_dsc_edp_policy; 1290 } dsc; 1291 /* eDP ILR */ 1292 struct ilr { 1293 bool optimize_edp_link_rate; /* eDP ILR */ 1294 } ilr; 1295 /* Adaptive VariBright*/ 1296 struct adaptive_vb { 1297 bool disable_adaptive_vb; 1298 unsigned int default_abm_vb_levels; // default value = 0xDCAA6414 1299 unsigned int default_cacp_vb_levels; 1300 unsigned int default_abm_vb_hdr_levels; // default value = 0xB4805A40 1301 unsigned int default_cacp_vb_hdr_levels; 1302 unsigned int abm_scaling_factors; // default value = 0x23210012 1303 unsigned int cacp_scaling_factors; 1304 unsigned int battery_life_configures; // default value = 0x0A141E 1305 unsigned int abm_backlight_adaptive_pwl_1; // default value = 0x6A4F7244 1306 unsigned int abm_backlight_adaptive_pwl_2; // default value = 0x4C615659 1307 unsigned int abm_backlight_adaptive_pwl_3; // default value = 0x0064 1308 unsigned int cacp_backlight_adaptive_pwl_1; 1309 unsigned int cacp_backlight_adaptive_pwl_2; 1310 unsigned int cacp_backlight_adaptive_pwl_3; 1311 } adaptive_vb; 1312 /* Ramless Idle Opt*/ 1313 struct rio { 1314 bool disable_rio; 1315 } rio; 1316 }; 1317 1318 struct mccs_caps { 1319 bool freesync_supported; 1320 }; 1321 1322 #define MAX_SINKS_PER_LINK 4 1323 1324 /* 1325 * USB4 DPIA BW ALLOCATION STRUCTS 1326 */ 1327 struct dc_dpia_bw_alloc { 1328 int remote_sink_req_bw[MAX_SINKS_PER_LINK]; // BW requested by remote sinks 1329 int link_verified_bw; // The Verified BW that link can allocated and use that has been verified already 1330 int link_max_bw; // The Max BW that link can require/support 1331 int allocated_bw; // The Actual Allocated BW for this DPIA 1332 int estimated_bw; // The estimated available BW for this DPIA 1333 int bw_granularity; // BW Granularity 1334 int dp_overhead; // DP overhead in dp tunneling 1335 bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3: DP-Tx & Dpia & CM 1336 uint8_t nrd_max_lane_count; // Non-reduced max lane count 1337 uint8_t nrd_max_link_rate; // Non-reduced max link rate 1338 }; 1339 1340 enum dc_hpd_enable_select { 1341 HPD_EN_FOR_ALL_EDP = 0, 1342 HPD_EN_FOR_PRIMARY_EDP_ONLY, 1343 HPD_EN_FOR_SECONDARY_EDP_ONLY, 1344 }; 1345 1346 enum dc_cm2_shaper_3dlut_setting { 1347 DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL, 1348 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER, 1349 /* Bypassing Shaper will always bypass 3DLUT */ 1350 DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT 1351 }; 1352 1353 enum dc_cm2_gpu_mem_layout { 1354 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB, 1355 DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR, 1356 DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR 1357 }; 1358 1359 enum dc_cm2_gpu_mem_pixel_component_order { 1360 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, 1361 DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA 1362 }; 1363 1364 enum dc_cm2_gpu_mem_format { 1365 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB, 1366 DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB, 1367 DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10 1368 }; 1369 1370 struct dc_cm2_gpu_mem_format_parameters { 1371 enum dc_cm2_gpu_mem_format format; 1372 union { 1373 struct { 1374 /* bias & scale for float only */ 1375 uint16_t bias; 1376 uint16_t scale; 1377 } float_params; 1378 }; 1379 }; 1380 1381 enum dc_cm2_gpu_mem_size { 1382 DC_CM2_GPU_MEM_SIZE_171717, 1383 DC_CM2_GPU_MEM_SIZE_333333, 1384 DC_CM2_GPU_MEM_SIZE_454545, 1385 DC_CM2_GPU_MEM_SIZE_656565, 1386 DC_CM2_GPU_MEM_SIZE_TRANSFORMED, 1387 }; 1388 1389 struct dc_cm2_gpu_mem_parameters { 1390 struct dc_plane_address addr; 1391 enum dc_cm2_gpu_mem_layout layout; 1392 struct dc_cm2_gpu_mem_format_parameters format_params; 1393 enum dc_cm2_gpu_mem_pixel_component_order component_order; 1394 enum dc_cm2_gpu_mem_size size; 1395 uint16_t bit_depth; 1396 }; 1397 1398 enum dc_cm2_transfer_func_source { 1399 DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM, 1400 DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM 1401 }; 1402 1403 struct dc_cm2_component_settings { 1404 enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting; 1405 bool lut1d_enable; 1406 }; 1407 1408 /* 1409 * All pointers in this struct must remain valid for as long as the 3DLUTs are used 1410 */ 1411 struct dc_cm2_func_luts { 1412 const struct dc_transfer_func *shaper; 1413 struct { 1414 enum dc_cm2_transfer_func_source lut3d_src; 1415 union { 1416 const struct dc_3dlut *lut3d_func; 1417 struct dc_cm2_gpu_mem_parameters gpu_mem_params; 1418 }; 1419 bool rmcm_3dlut_shaper_select; 1420 bool mpc_3dlut_enable; 1421 bool rmcm_3dlut_enable; 1422 bool mpc_mcm_post_blend; 1423 uint8_t rmcm_tmz; 1424 } lut3d_data; 1425 const struct dc_transfer_func *lut1d_func; 1426 }; 1427 1428 struct dc_cm2_parameters { 1429 struct dc_cm2_component_settings component_settings; 1430 struct dc_cm2_func_luts cm2_luts; 1431 }; 1432 1433 enum mall_stream_type { 1434 SUBVP_NONE, // subvp not in use 1435 SUBVP_MAIN, // subvp in use, this stream is main stream 1436 SUBVP_PHANTOM, // subvp in use, this stream is a phantom stream 1437 }; 1438 1439 enum dc_power_source_type { 1440 DC_POWER_SOURCE_AC, // wall power 1441 DC_POWER_SOURCE_DC, // battery power 1442 }; 1443 1444 struct dc_state_create_params { 1445 enum dc_power_source_type power_source; 1446 }; 1447 1448 struct dc_commit_streams_params { 1449 struct dc_stream_state **streams; 1450 uint8_t stream_count; 1451 enum dc_power_source_type power_source; 1452 }; 1453 1454 struct set_backlight_level_params { 1455 /* backlight in pwm */ 1456 uint32_t backlight_pwm_u16_16; 1457 /* brightness ramping */ 1458 uint32_t frame_ramp; 1459 /* backlight control type 1460 * 0: PWM backlight control 1461 * 1: VESA AUX backlight control 1462 * 2: AMD AUX backlight control 1463 */ 1464 enum backlight_control_type control_type; 1465 /* backlight in millinits */ 1466 uint32_t backlight_millinits; 1467 /* transition time in ms */ 1468 uint32_t transition_time_in_ms; 1469 /* minimum luminance in nits */ 1470 uint32_t min_luminance; 1471 /* maximum luminance in nits */ 1472 uint32_t max_luminance; 1473 /* minimum backlight in pwm */ 1474 uint32_t min_backlight_pwm; 1475 /* maximum backlight in pwm */ 1476 uint32_t max_backlight_pwm; 1477 /* AUX HW instance */ 1478 uint8_t aux_inst; 1479 }; 1480 1481 enum dc_validate_mode { 1482 /* validate the mode and program HW */ 1483 DC_VALIDATE_MODE_AND_PROGRAMMING = 0, 1484 /* only validate the mode */ 1485 DC_VALIDATE_MODE_ONLY = 1, 1486 /* validate the mode and get the max state (voltage level) */ 1487 DC_VALIDATE_MODE_AND_STATE_INDEX = 2, 1488 }; 1489 1490 struct dc_validation_dpia_set { 1491 const struct dc_link *link; 1492 const struct dc_tunnel_settings *tunnel_settings; 1493 uint32_t required_bw; 1494 }; 1495 1496 enum dc_cm_lut_swizzle { 1497 CM_LUT_3D_SWIZZLE_LINEAR_RGB, 1498 CM_LUT_3D_SWIZZLE_LINEAR_BGR, 1499 CM_LUT_1D_PACKED_LINEAR 1500 }; 1501 1502 enum dc_cm_lut_pixel_format { 1503 CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB, 1504 CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB, 1505 CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB, 1506 CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB, 1507 CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10, 1508 CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10 1509 }; 1510 1511 enum dc_cm_lut_size { 1512 CM_LUT_SIZE_NONE, 1513 CM_LUT_SIZE_999, 1514 CM_LUT_SIZE_171717, 1515 CM_LUT_SIZE_333333, 1516 CM_LUT_SIZE_454545, 1517 CM_LUT_SIZE_656565, 1518 }; 1519 1520 #endif /* DC_TYPES_H_ */ 1521