1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef RVU_H 9 #define RVU_H 10 11 #include <linux/pci.h> 12 #include <net/devlink.h> 13 #include <linux/soc/marvell/silicons.h> 14 15 #include "rvu_struct.h" 16 #include "rvu_devlink.h" 17 #include "common.h" 18 #include "mbox.h" 19 #include "npc.h" 20 #include "rvu_reg.h" 21 #include "ptp.h" 22 23 /* PCI device IDs */ 24 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065 25 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 26 #define PCI_DEVID_OCTEONTX2_LBK 0xA061 27 28 /* Subsystem Device ID */ 29 #define PCI_SUBSYS_DEVID_98XX 0xB100 30 #define PCI_SUBSYS_DEVID_96XX 0xB200 31 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900 32 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00 33 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00 34 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00 35 #define PCI_SUBSYS_DEVID_CN20KA 0xC220 36 #define PCI_SUBSYS_DEVID_CNF20KA 0xC320 37 38 /* PCI BAR nos */ 39 #define PCI_AF_REG_BAR_NUM 0 40 #define PCI_PF_REG_BAR_NUM 2 41 #define PCI_MBOX_BAR_NUM 4 42 43 #define NAME_SIZE 32 44 #define MAX_NIX_BLKS 2 45 #define MAX_CPT_BLKS 2 46 47 /* PF_FUNC */ 48 #define RVU_OTX2_PFVF_PF_SHIFT 10 49 #define RVU_OTX2_PFVF_PF_MASK 0x3F 50 #define RVU_PFVF_FUNC_SHIFT 0 51 #define RVU_PFVF_FUNC_MASK 0x3FF 52 #define RVU_CN20K_PFVF_PF_SHIFT 9 53 #define RVU_CN20K_PFVF_PF_MASK 0x7F 54 55 static inline u16 rvu_make_pcifunc(struct pci_dev *pdev, int pf, int func) 56 { 57 if (is_cn20k(pdev)) 58 return ((pf & RVU_CN20K_PFVF_PF_MASK) << 59 RVU_CN20K_PFVF_PF_SHIFT) | 60 ((func & RVU_PFVF_FUNC_MASK) << 61 RVU_PFVF_FUNC_SHIFT); 62 else 63 return ((pf & RVU_OTX2_PFVF_PF_MASK) << 64 RVU_OTX2_PFVF_PF_SHIFT) | 65 ((func & RVU_PFVF_FUNC_MASK) << 66 RVU_PFVF_FUNC_SHIFT); 67 } 68 69 static inline int rvu_pcifunc_pf_mask(struct pci_dev *pdev) 70 { 71 if (is_cn20k(pdev)) 72 return ~(RVU_CN20K_PFVF_PF_MASK << RVU_CN20K_PFVF_PF_SHIFT); 73 else 74 return ~(RVU_OTX2_PFVF_PF_MASK << RVU_OTX2_PFVF_PF_SHIFT); 75 } 76 77 #define RVU_AFPF 25 78 79 #ifdef CONFIG_DEBUG_FS 80 81 struct dump_ctx { 82 int lf; 83 int id; 84 bool all; 85 }; 86 87 struct cpt_ctx { 88 int blkaddr; 89 struct rvu *rvu; 90 }; 91 92 struct rvu_debugfs { 93 struct dentry *root; 94 struct dentry *cgx_root; 95 struct dentry *cgx; 96 struct dentry *lmac; 97 struct dentry *npa; 98 struct dentry *nix; 99 struct dentry *npc; 100 struct dentry *cpt; 101 struct dentry *mcs_root; 102 struct dentry *mcs; 103 struct dentry *mcs_rx; 104 struct dentry *mcs_tx; 105 struct dump_ctx npa_aura_ctx; 106 struct dump_ctx npa_pool_ctx; 107 struct dump_ctx nix_cq_ctx; 108 struct dump_ctx nix_rq_ctx; 109 struct dump_ctx nix_sq_ctx; 110 struct dump_ctx nix_tm_ctx; 111 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; 112 int npa_qsize_id; 113 int nix_qsize_id; 114 }; 115 #endif 116 117 struct rvu_work { 118 struct work_struct work; 119 struct rvu *rvu; 120 int num_msgs; 121 int up_num_msgs; 122 }; 123 124 struct rsrc_bmap { 125 unsigned long *bmap; /* Pointer to resource bitmap */ 126 u16 max; /* Max resource id or count */ 127 }; 128 129 struct rvu_block { 130 struct rsrc_bmap lf; 131 struct admin_queue *aq; /* NIX/NPA AQ */ 132 u16 *fn_map; /* LF to pcifunc mapping */ 133 bool multislot; 134 bool implemented; 135 u8 addr; /* RVU_BLOCK_ADDR_E */ 136 u8 type; /* RVU_BLOCK_TYPE_E */ 137 u8 lfshift; 138 u64 lookup_reg; 139 u64 pf_lfcnt_reg; 140 u64 vf_lfcnt_reg; 141 u64 lfcfg_reg; 142 u64 msixcfg_reg; 143 u64 lfreset_reg; 144 unsigned char name[NAME_SIZE]; 145 struct rvu *rvu; 146 u64 cpt_flt_eng_map[3]; 147 u64 cpt_rcvrd_eng_map[3]; 148 }; 149 150 struct nix_mcast { 151 struct qmem *mce_ctx; 152 struct qmem *mcast_buf; 153 int replay_pkind; 154 struct rsrc_bmap mce_counter[2]; 155 /* Counters for both ingress and egress mcast lists */ 156 struct mutex mce_lock; /* Serialize MCE updates */ 157 }; 158 159 struct nix_mce_list { 160 struct hlist_head head; 161 int count; 162 int max; 163 }; 164 165 struct nix_mcast_grp_elem { 166 struct nix_mce_list mcast_mce_list; 167 u32 mcast_grp_idx; 168 u32 pcifunc; 169 int mcam_index; 170 int mce_start_index; 171 struct list_head list; 172 u8 dir; 173 }; 174 175 struct nix_mcast_grp { 176 struct list_head mcast_grp_head; 177 int count; 178 int next_grp_index; 179 struct mutex mcast_grp_lock; /* Serialize MCE updates */ 180 }; 181 182 /* layer metadata to uniquely identify a packet header field */ 183 struct npc_layer_mdata { 184 u8 lid; 185 u8 ltype; 186 u8 hdr; 187 u8 key; 188 u8 len; 189 }; 190 191 /* Structure to represent a field present in the 192 * generated key. A key field may present anywhere and can 193 * be of any size in the generated key. Once this structure 194 * is populated for fields of interest then field's presence 195 * and location (if present) can be known. 196 */ 197 struct npc_key_field { 198 /* Masks where all set bits indicate position 199 * of a field in the key 200 */ 201 u64 kw_mask[NPC_KWS_IN_KEY_SZ_MAX]; 202 /* Number of words in the key a field spans. If a field is 203 * of 16 bytes and key offset is 4 then the field will use 204 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and 205 * nr_kws will be 3(KW0, KW1 and KW2). 206 */ 207 int nr_kws; 208 /* used by packet header fields */ 209 struct npc_layer_mdata layer_mdata; 210 }; 211 212 struct npc_mcam { 213 struct rsrc_bmap counters; 214 struct mutex lock; /* MCAM entries and counters update lock */ 215 unsigned long *bmap; /* bitmap, 0 => bmap_entries */ 216 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */ 217 u16 bmap_entries; /* Number of unreserved MCAM entries */ 218 u16 bmap_fcnt; /* MCAM entries free count */ 219 u16 *entry2pfvf_map; 220 u16 *entry2cntr_map; 221 u16 *cntr2pfvf_map; 222 u16 *cntr_refcnt; 223 u16 *entry2target_pffunc; 224 u8 keysize; /* MCAM keysize 112/224/448 bits */ 225 u8 banks; /* Number of MCAM banks */ 226 u8 banks_per_entry;/* Number of keywords in key */ 227 u16 banksize; /* Number of MCAM entries in each bank */ 228 u16 total_entries; /* Total number of MCAM entries */ 229 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */ 230 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */ 231 u16 lprio_count; 232 u16 lprio_start; 233 u16 hprio_count; 234 u16 hprio_end; 235 u16 rx_miss_act_cntr; /* Counter for RX MISS action */ 236 /* fields present in the generated key */ 237 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX]; 238 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX]; 239 u64 tx_features; 240 u64 rx_features; 241 struct list_head mcam_rules; 242 }; 243 244 /* Structure for per RVU func info ie PF/VF */ 245 struct rvu_pfvf { 246 bool npalf; /* Only one NPALF per RVU_FUNC */ 247 bool nixlf; /* Only one NIXLF per RVU_FUNC */ 248 u16 sso; 249 u16 ssow; 250 u16 cptlfs; 251 u16 timlfs; 252 u16 cpt1_lfs; 253 u8 cgx_lmac; 254 255 /* Block LF's MSIX vector info */ 256 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */ 257 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF)) 258 u16 *msix_lfmap; /* Vector to block LF mapping */ 259 260 /* NPA contexts */ 261 struct qmem *aura_ctx; 262 struct qmem *pool_ctx; 263 struct qmem *npa_qints_ctx; 264 unsigned long *aura_bmap; 265 unsigned long *pool_bmap; 266 267 /* NIX contexts */ 268 struct qmem *rq_ctx; 269 struct qmem *sq_ctx; 270 struct qmem *cq_ctx; 271 struct qmem *rss_ctx; 272 struct qmem *cq_ints_ctx; 273 struct qmem *nix_qints_ctx; 274 unsigned long *sq_bmap; 275 unsigned long *rq_bmap; 276 unsigned long *cq_bmap; 277 278 u16 rx_chan_base; 279 u16 tx_chan_base; 280 u8 rx_chan_cnt; /* total number of RX channels */ 281 u8 tx_chan_cnt; /* total number of TX channels */ 282 u16 maxlen; 283 u16 minlen; 284 285 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */ 286 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */ 287 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */ 288 289 /* Broadcast/Multicast/Promisc pkt replication info */ 290 u16 bcast_mce_idx; 291 u16 mcast_mce_idx; 292 u16 promisc_mce_idx; 293 struct nix_mce_list bcast_mce_list; 294 struct nix_mce_list mcast_mce_list; 295 struct nix_mce_list promisc_mce_list; 296 bool use_mce_list; 297 298 struct rvu_npc_mcam_rule *def_ucast_rule; 299 300 bool cgx_in_use; /* this PF/VF using CGX? */ 301 int cgx_users; /* number of cgx users - used only by PFs */ 302 303 int intf_mode; 304 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */ 305 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */ 306 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */ 307 u8 lbkid; /* NIX0/1 lbk link ID */ 308 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/ 309 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/ 310 unsigned long flags; 311 struct sdp_node_info *sdp_info; 312 u8 hw_prio; /* Hw priority of default rules */ 313 }; 314 315 enum rvu_pfvf_flags { 316 NIXLF_INITIALIZED = 0, 317 PF_SET_VF_MAC, 318 PF_SET_VF_CFG, 319 PF_SET_VF_TRUSTED, 320 }; 321 322 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC) 323 324 struct nix_bp { 325 struct rsrc_bmap bpids; /* free bpids bitmap */ 326 u16 cgx_bpid_cnt; 327 u16 sdp_bpid_cnt; 328 u16 free_pool_base; 329 u16 *fn_map; /* pcifunc mapping */ 330 u8 *intf_map; /* interface type map */ 331 u8 *ref_cnt; 332 }; 333 334 struct nix_txsch { 335 struct rsrc_bmap schq; 336 u8 lvl; 337 #define NIX_TXSCHQ_FREE BIT_ULL(1) 338 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0) 339 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF) 340 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16) 341 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16)) 342 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16)) 343 u32 *pfvf_map; 344 }; 345 346 struct nix_mark_format { 347 u8 total; 348 u8 in_use; 349 u32 *cfg; 350 }; 351 352 /* smq(flush) to tl1 cir/pir info */ 353 struct nix_smq_tree_ctx { 354 u16 schq; 355 u64 cir_off; 356 u64 cir_val; 357 u64 pir_off; 358 u64 pir_val; 359 }; 360 361 /* smq flush context */ 362 struct nix_smq_flush_ctx { 363 int smq; 364 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT]; 365 }; 366 367 struct npc_pkind { 368 struct rsrc_bmap rsrc; 369 u32 *pfchan_map; 370 }; 371 372 struct nix_flowkey { 373 #define NIX_FLOW_KEY_ALG_MAX 32 374 u32 flowkey[NIX_FLOW_KEY_ALG_MAX]; 375 int in_use; 376 }; 377 378 struct nix_lso { 379 u8 total; 380 u8 in_use; 381 }; 382 383 struct nix_txvlan { 384 #define NIX_TX_VTAG_DEF_MAX 0x400 385 struct rsrc_bmap rsrc; 386 u16 *entry2pfvf_map; 387 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 388 }; 389 390 struct nix_ipolicer { 391 struct rsrc_bmap band_prof; 392 u16 *pfvf_map; 393 u16 *match_id; 394 u16 *ref_count; 395 }; 396 397 struct nix_hw { 398 int blkaddr; 399 struct rvu *rvu; 400 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */ 401 struct nix_mcast mcast; 402 struct nix_mcast_grp mcast_grp; 403 struct nix_flowkey flowkey; 404 struct nix_mark_format mark_format; 405 struct nix_lso lso; 406 struct nix_txvlan txvlan; 407 struct nix_ipolicer *ipolicer; 408 struct nix_bp bp; 409 u64 *tx_credits; 410 u8 cc_mcs_cnt; 411 }; 412 413 /* RVU block's capabilities or functionality, 414 * which vary by silicon version/skew. 415 */ 416 struct hw_cap { 417 /* Transmit side supported functionality */ 418 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */ 419 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */ 420 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */ 421 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */ 422 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */ 423 bool nix_shaping; /* Is shaping and coloring supported */ 424 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */ 425 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */ 426 bool nix_rx_multicast; /* Rx packet replication support */ 427 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */ 428 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */ 429 bool programmable_chans; /* Channels programmable ? */ 430 bool ipolicer; 431 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */ 432 bool npc_hash_extract; /* Hash extract enabled ? */ 433 bool npc_exact_match_enabled; /* Exact match supported ? */ 434 bool cpt_rxc; /* Is CPT-RXC supported */ 435 }; 436 437 struct rvu_hwinfo { 438 u8 total_pfs; /* MAX RVU PFs HW supports */ 439 u16 total_vfs; /* Max RVU VFs HW supports */ 440 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */ 441 u8 cgx; 442 u8 lmac_per_cgx; 443 u16 cgx_chan_base; /* CGX base channel number */ 444 u16 lbk_chan_base; /* LBK base channel number */ 445 u16 sdp_chan_base; /* SDP base channel number */ 446 u16 cpt_chan_base; /* CPT base channel number */ 447 u8 cgx_links; 448 u8 lbk_links; 449 u8 sdp_links; 450 u8 cpt_links; /* Number of CPT links */ 451 u8 npc_kpus; /* No of parser units */ 452 u8 npc_kpms; /* Number of enhanced parser units */ 453 u8 npc_kex_extr; /* Number of LDATA extractors per KEX */ 454 u8 npc_pkinds; /* No of port kinds */ 455 u8 npc_intfs; /* No of interfaces */ 456 u16 npc_kpu_entries; /* No of KPU entries */ 457 u16 npc_counters; /* No of match stats counters */ 458 u32 lbk_bufsize; /* FIFO size supported by LBK */ 459 bool npc_ext_set; /* Extended register set */ 460 u64 npc_stat_ena; /* Match stats enable bit */ 461 462 struct hw_cap cap; 463 struct rvu_block block[BLK_COUNT]; /* Block info */ 464 struct nix_hw *nix; 465 struct rvu *rvu; 466 struct npc_pkind pkind; 467 struct npc_mcam mcam; 468 struct npc_exact_table *table; 469 }; 470 471 struct mbox_wq_info { 472 struct otx2_mbox mbox; 473 struct rvu_work *mbox_wrk; 474 475 struct otx2_mbox mbox_up; 476 struct rvu_work *mbox_wrk_up; 477 478 struct workqueue_struct *mbox_wq; 479 }; 480 481 struct rvu_irq_data { 482 u64 intr_status; 483 void (*rvu_queue_work_hdlr)(struct mbox_wq_info *mw, int first, 484 int mdevs, u64 intr); 485 void (*afvf_queue_work_hdlr)(struct mbox_wq_info *mw, int first, 486 int mdevs, u64 intr); 487 struct rvu *rvu; 488 int vec_num; 489 int start; 490 int mdevs; 491 }; 492 493 struct mbox_ops { 494 irqreturn_t (*pf_intr_handler)(int irq, void *rvu_irq); 495 irqreturn_t (*afvf_intr_handler)(int irq, void *rvu_irq); 496 }; 497 498 struct channel_fwdata { 499 struct sdp_node_info info; 500 u8 valid; 501 #define RVU_CHANL_INFO_RESERVED 379 502 u8 reserved[RVU_CHANL_INFO_RESERVED]; 503 }; 504 505 struct altaf_intr_notify { 506 unsigned long flr_pf_bmap[2]; 507 unsigned long flr_vf_bmap[2]; 508 unsigned long gint_paddr; 509 unsigned long gint_iova_addr; 510 unsigned long reserved[6]; 511 }; 512 513 struct rvu_fwdata { 514 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/ 515 #define RVU_FWDATA_VERSION 0x0001 516 u32 header_magic; 517 u32 version; /* version id */ 518 519 /* MAC address */ 520 #define PF_MACNUM_MAX 32 521 #define VF_MACNUM_MAX 256 522 u64 pf_macs[PF_MACNUM_MAX]; 523 u64 vf_macs[VF_MACNUM_MAX]; 524 u64 sclk; 525 u64 rclk; 526 u64 mcam_addr; 527 u64 mcam_sz; 528 u64 msixtr_base; 529 u32 ptp_ext_clk_rate; 530 u32 ptp_ext_tstamp; 531 struct channel_fwdata channel_data; 532 struct altaf_intr_notify altaf_intr_info; 533 #define FWDATA_RESERVED_MEM 946 534 u64 reserved[FWDATA_RESERVED_MEM]; 535 #define CGX_MAX 9 536 #define CGX_LMACS_MAX 4 537 #define CGX_LMACS_USX 8 538 #define FWDATA_CGX_LMAC_OFFSET 10536 539 union { 540 struct cgx_lmac_fwdata_s 541 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX]; 542 struct cgx_lmac_fwdata_s 543 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX]; 544 }; 545 /* Do not add new fields below this line */ 546 }; 547 548 struct ptp; 549 550 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the 551 * source where it came from. 552 */ 553 struct npc_kpu_profile_adapter { 554 const char *name; 555 u64 version; 556 const struct npc_lt_def_cfg *lt_def; 557 struct npc_kpu_profile_action *ikpu; /* array[pkinds] */ 558 struct npc_kpu_profile_action *ikpu2; /* array[pkinds] */ 559 struct npc_kpu_profile *kpu; /* array[kpus] */ 560 union npc_mcam_key_prfl { 561 const struct npc_mcam_kex *mkex; 562 /* used for cn9k and cn10k */ 563 const struct npc_mcam_kex_extr *mkex_extr; /* used for cn20k */ 564 } mcam_kex_prfl; 565 struct npc_mcam_kex_hash *mkex_hash; 566 bool custom; 567 size_t pkinds; 568 size_t kpus; 569 bool from_fs; 570 }; 571 572 #define RVU_SWITCH_LBK_CHAN 63 573 574 struct rvu_switch { 575 struct mutex switch_lock; /* Serialize flow installation */ 576 u32 used_entries; 577 u16 *entry2pcifunc; 578 u16 mode; 579 u16 start_entry; 580 }; 581 582 struct rep_evtq_ent { 583 struct list_head node; 584 struct rep_event event; 585 }; 586 587 struct rvu { 588 void __iomem *afreg_base; 589 void __iomem *pfreg_base; 590 struct pci_dev *pdev; 591 struct device *dev; 592 struct rvu_hwinfo *hw; 593 struct rvu_pfvf *pf; 594 struct rvu_pfvf *hwvf; 595 struct mutex rsrc_lock; /* Serialize resource alloc/free */ 596 struct mutex alias_lock; /* Serialize bar2 alias access */ 597 int vfs; /* Number of VFs attached to RVU */ 598 u16 vf_devid; /* VF devices id */ 599 bool def_rule_cntr_en; 600 int nix_blkaddr[MAX_NIX_BLKS]; 601 602 /* Mbox */ 603 struct mbox_wq_info afpf_wq_info; 604 struct mbox_wq_info afvf_wq_info; 605 606 /* PF FLR */ 607 struct rvu_work *flr_wrk; 608 struct workqueue_struct *flr_wq; 609 struct mutex flr_lock; /* Serialize FLRs */ 610 611 /* MSI-X */ 612 u16 num_vec; 613 char *irq_name; 614 bool *irq_allocated; 615 dma_addr_t msix_base_iova; 616 u64 msixtr_base_phy; /* Register reset value */ 617 618 /* CGX */ 619 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */ 620 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */ 621 u8 cgx_mapped_pfs; 622 u8 cgx_cnt_max; /* CGX port count max */ 623 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */ 624 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for 625 * every cgx lmac port 626 */ 627 unsigned long pf_notify_bmap; /* Flags for PF notification */ 628 void **cgx_idmap; /* cgx id to cgx data map table */ 629 struct work_struct cgx_evh_work; 630 struct workqueue_struct *cgx_evh_wq; 631 spinlock_t cgx_evq_lock; /* cgx event queue lock */ 632 struct list_head cgx_evq_head; /* cgx event queue head */ 633 struct mutex cgx_cfg_lock; /* serialize cgx configuration */ 634 635 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */ 636 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */ 637 638 /* Firmware data */ 639 struct rvu_fwdata *fwdata; 640 const void *kpu_fwdata; 641 size_t kpu_fwdata_sz; 642 void __iomem *kpu_prfl_addr; 643 644 /* NPC KPU data */ 645 struct npc_kpu_profile_adapter kpu; 646 647 struct ptp *ptp; 648 649 int mcs_blk_cnt; 650 int cpt_pf_num; 651 652 #ifdef CONFIG_DEBUG_FS 653 struct rvu_debugfs rvu_dbg; 654 #endif 655 struct rvu_devlink *rvu_dl; 656 657 /* RVU switch implementation over NPC with DMAC rules */ 658 struct rvu_switch rswitch; 659 660 struct work_struct mcs_intr_work; 661 struct workqueue_struct *mcs_intr_wq; 662 struct list_head mcs_intrq_head; 663 /* mcs interrupt queue lock */ 664 spinlock_t mcs_intrq_lock; 665 /* CPT interrupt lock */ 666 spinlock_t cpt_intr_lock; 667 668 struct mutex mbox_lock; /* Serialize mbox up and down msgs */ 669 u16 rep_pcifunc; 670 bool altaf_ready; 671 int rep_cnt; 672 u16 *rep2pfvf_map; 673 u8 rep_mode; 674 struct work_struct rep_evt_work; 675 struct workqueue_struct *rep_evt_wq; 676 struct list_head rep_evtq_head; 677 /* Representor event lock */ 678 spinlock_t rep_evtq_lock; 679 680 struct ng_rvu *ng_rvu; 681 }; 682 683 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 684 { 685 writeq(val, rvu->afreg_base + ((block << 28) | offset)); 686 } 687 688 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) 689 { 690 return readq(rvu->afreg_base + ((block << 28) | offset)); 691 } 692 693 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) 694 { 695 writeq(val, rvu->pfreg_base + offset); 696 } 697 698 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) 699 { 700 return readq(rvu->pfreg_base + offset); 701 } 702 703 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) 704 { 705 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of 706 * write operation. 707 */ 708 rvu_write64(rvu, block, offset, val); 709 rvu_read64(rvu, block, offset); 710 /* Barrier to ensure read completes before accessing LF registers */ 711 mb(); 712 } 713 714 /* Silicon revisions */ 715 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu) 716 { 717 struct pci_dev *pdev = rvu->pdev; 718 /* 96XX A0/B0, 95XX A0/A1/B0 chips */ 719 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) || 720 (pdev->revision == 0x10) || (pdev->revision == 0x11) || 721 (pdev->revision == 0x14)); 722 } 723 724 static inline bool is_rvu_96xx_A0(struct rvu *rvu) 725 { 726 struct pci_dev *pdev = rvu->pdev; 727 728 return (pdev->revision == 0x00); 729 } 730 731 static inline bool is_rvu_96xx_B0(struct rvu *rvu) 732 { 733 struct pci_dev *pdev = rvu->pdev; 734 735 return (pdev->revision == 0x00) || (pdev->revision == 0x01); 736 } 737 738 static inline bool is_rvu_95xx_A0(struct rvu *rvu) 739 { 740 struct pci_dev *pdev = rvu->pdev; 741 742 return (pdev->revision == 0x10) || (pdev->revision == 0x11); 743 } 744 745 /* REVID for PCIe devices. 746 * Bits 0..1: minor pass, bit 3..2: major pass 747 * bits 7..4: midr id 748 */ 749 #define PCI_REVISION_ID_96XX 0x00 750 #define PCI_REVISION_ID_95XX 0x10 751 #define PCI_REVISION_ID_95XXN 0x20 752 #define PCI_REVISION_ID_98XX 0x30 753 #define PCI_REVISION_ID_95XXMM 0x40 754 #define PCI_REVISION_ID_95XXO 0xE0 755 756 static inline bool is_rvu_otx2(struct rvu *rvu) 757 { 758 struct pci_dev *pdev = rvu->pdev; 759 760 u8 midr = pdev->revision & 0xF0; 761 762 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 763 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 764 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 765 } 766 767 static inline bool is_cnf10ka_a0(struct rvu *rvu) 768 { 769 struct pci_dev *pdev = rvu->pdev; 770 771 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A && 772 (pdev->revision & 0x0F) == 0x0) 773 return true; 774 return false; 775 } 776 777 static inline bool is_cn10ka_a0(struct rvu *rvu) 778 { 779 struct pci_dev *pdev = rvu->pdev; 780 781 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 782 (pdev->revision & 0x0F) == 0x0) 783 return true; 784 return false; 785 } 786 787 static inline bool is_cn10ka_a1(struct rvu *rvu) 788 { 789 struct pci_dev *pdev = rvu->pdev; 790 791 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A && 792 (pdev->revision & 0x0F) == 0x1) 793 return true; 794 return false; 795 } 796 797 static inline bool is_cn10kb(struct rvu *rvu) 798 { 799 struct pci_dev *pdev = rvu->pdev; 800 801 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B) 802 return true; 803 return false; 804 } 805 806 static inline bool is_cgx_mapped_to_nix(unsigned short id, u8 cgx_id) 807 { 808 /* On CNF10KA and CNF10KB silicons only two CGX blocks are connected 809 * to NIX. 810 */ 811 if (id == PCI_SUBSYS_DEVID_CNF10K_A || id == PCI_SUBSYS_DEVID_CNF10K_B) 812 return cgx_id <= 1; 813 814 return !(cgx_id && !(id == PCI_SUBSYS_DEVID_96XX || 815 id == PCI_SUBSYS_DEVID_98XX || 816 id == PCI_SUBSYS_DEVID_CN10K_A || 817 id == PCI_SUBSYS_DEVID_CN10K_B)); 818 } 819 820 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu) 821 { 822 u64 npc_const3; 823 824 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3); 825 if (!(npc_const3 & BIT_ULL(62))) 826 return false; 827 828 return true; 829 } 830 831 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, 832 u8 lmacid, u8 chan) 833 { 834 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 835 u16 cgx_chans = nix_const & 0xFFULL; 836 struct rvu_hwinfo *hw = rvu->hw; 837 838 if (!hw->cap.programmable_chans) 839 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan); 840 841 return rvu->hw->cgx_chan_base + 842 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; 843 } 844 845 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, 846 u8 chan) 847 { 848 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST); 849 u16 lbk_chans = (nix_const >> 16) & 0xFFULL; 850 struct rvu_hwinfo *hw = rvu->hw; 851 852 if (!hw->cap.programmable_chans) 853 return NIX_CHAN_LBK_CHX(lbkid, chan); 854 855 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; 856 } 857 858 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan) 859 { 860 struct rvu_hwinfo *hw = rvu->hw; 861 862 if (!hw->cap.programmable_chans) 863 return NIX_CHAN_SDP_CHX(chan); 864 865 return hw->sdp_chan_base + chan; 866 } 867 868 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) 869 { 870 return rvu->hw->cpt_chan_base + chan; 871 } 872 873 static inline bool is_rvu_supports_nix1(struct rvu *rvu) 874 { 875 struct pci_dev *pdev = rvu->pdev; 876 877 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX) 878 return true; 879 880 return false; 881 } 882 883 /* Function Prototypes 884 * RVU 885 */ 886 static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc) 887 { 888 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) && 889 (rvu->vf_devid == PCI_DEVID_OCTEONTX2_RVU_AFVF)); 890 } 891 892 static inline bool is_vf(u16 pcifunc) 893 { 894 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 895 } 896 897 /* check if PF_FUNC is AF */ 898 static inline bool is_pffunc_af(u16 pcifunc) 899 { 900 return !pcifunc; 901 } 902 903 static inline bool is_rvu_fwdata_valid(struct rvu *rvu) 904 { 905 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) && 906 (rvu->fwdata->version == RVU_FWDATA_VERSION); 907 } 908 909 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc); 910 void rvu_free_bitmap(struct rsrc_bmap *rsrc); 911 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc); 912 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id); 913 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id); 914 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc); 915 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc); 916 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start); 917 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc); 918 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr); 919 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc); 920 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf); 921 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr); 922 bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc); 923 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype); 924 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot); 925 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 926 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc); 927 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero); 928 int rvu_get_num_lbk_chans(void); 929 int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset); 930 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc, 931 u16 global_slot, u16 *slot_in_block); 932 933 /* RVU HW reg validation */ 934 enum regmap_block { 935 TXSCHQ_HWREGMAP = 0, 936 MAX_HWREGMAP, 937 }; 938 939 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg); 940 941 /* NPA/NIX AQ APIs */ 942 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue, 943 int qsize, int inst_size, int res_size); 944 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq); 945 946 /* SDP APIs */ 947 int rvu_sdp_init(struct rvu *rvu); 948 bool is_sdp_pfvf(struct rvu *rvu, u16 pcifunc); 949 bool is_sdp_pf(struct rvu *rvu, u16 pcifunc); 950 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc); 951 952 static inline bool is_rep_dev(struct rvu *rvu, u16 pcifunc) 953 { 954 if (rvu->rep_pcifunc && rvu->rep_pcifunc == pcifunc) 955 return true; 956 957 return false; 958 } 959 960 static inline int rvu_get_pf(struct pci_dev *pdev, u16 pcifunc) 961 { 962 if (is_cn20k(pdev)) 963 return (pcifunc >> RVU_CN20K_PFVF_PF_SHIFT) & 964 RVU_CN20K_PFVF_PF_MASK; 965 else 966 return (pcifunc >> RVU_OTX2_PFVF_PF_SHIFT) & 967 RVU_OTX2_PFVF_PF_MASK; 968 } 969 970 /* CGX APIs */ 971 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf) 972 { 973 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) && 974 !is_sdp_pf(rvu, rvu_make_pcifunc(rvu->pdev, pf, 0)); 975 } 976 977 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id) 978 { 979 *cgx_id = (map >> 4) & 0xF; 980 *lmac_id = (map & 0xF); 981 } 982 983 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc) 984 { 985 return ((pcifunc & RVU_PFVF_FUNC_MASK) && 986 is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc))); 987 } 988 989 #define M(_name, _id, fn_name, req, rsp) \ 990 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *); 991 MBOX_MESSAGES 992 #undef M 993 994 /* Mbox APIs */ 995 void rvu_queue_work(struct mbox_wq_info *mw, int first, 996 int mdevs, u64 intr); 997 998 int rvu_cgx_init(struct rvu *rvu); 999 int rvu_cgx_exit(struct rvu *rvu); 1000 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu); 1001 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start); 1002 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable); 1003 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start); 1004 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index, 1005 int rxtxflag, u64 *stat); 1006 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc); 1007 1008 /* NPA APIs */ 1009 int rvu_npa_init(struct rvu *rvu); 1010 void rvu_npa_freemem(struct rvu *rvu); 1011 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf); 1012 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, 1013 struct npa_aq_enq_rsp *rsp); 1014 1015 /* NIX APIs */ 1016 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc); 1017 int rvu_nix_init(struct rvu *rvu); 1018 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw, 1019 int blkaddr, u32 cfg); 1020 void rvu_nix_freemem(struct rvu *rvu); 1021 int rvu_get_nixlf_count(struct rvu *rvu); 1022 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf); 1023 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr); 1024 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc, 1025 struct nix_mce_list *mce_list, 1026 int mce_idx, int mcam_index, bool add); 1027 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type, 1028 struct nix_mce_list **mce_list, int *mce_idx); 1029 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr); 1030 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 1031 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc); 1032 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc, 1033 struct nix_hw **nix_hw, int *blkaddr); 1034 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc, 1035 u16 rq_idx, u16 match_id); 1036 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw, 1037 struct nix_cn10k_aq_enq_req *aq_req, 1038 struct nix_cn10k_aq_enq_rsp *aq_rsp, 1039 u16 pcifunc, u8 ctype, u32 qidx); 1040 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc); 1041 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type); 1042 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu); 1043 u32 convert_bytes_to_dwrr_mtu(u32 bytes); 1044 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc, 1045 struct nix_txsch *txsch, bool enable); 1046 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc); 1047 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc, 1048 u32 mcast_grp_idx); 1049 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc, 1050 u32 mcast_grp_idx, u16 mcam_index); 1051 void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc); 1052 int rvu_alloc_cint_qint_mem(struct rvu *rvu, struct rvu_pfvf *pfvf, 1053 int blkaddr, int nixlf); 1054 void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr); 1055 int rvu_nix_aq_enq_inst(struct rvu *rvu, struct nix_aq_enq_req *req, 1056 struct nix_aq_enq_rsp *rsp); 1057 1058 /* NPC APIs */ 1059 void rvu_npc_freemem(struct rvu *rvu); 1060 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); 1061 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf); 1062 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en); 1063 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc, 1064 int nixlf, u64 chan, u8 *mac_addr); 1065 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc, 1066 int nixlf, u64 chan, u8 chan_cnt); 1067 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1068 bool enable); 1069 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc, 1070 int nixlf, u64 chan); 1071 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1072 u64 chan); 1073 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf, 1074 bool enable); 1075 1076 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc, 1077 int nixlf, int type, bool enable); 1078 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1079 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable); 1080 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1081 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1082 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf); 1083 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf, 1084 int group, int alg_idx, int mcam_index); 1085 void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc, 1086 struct rvu_npc_mcam_rule *rule); 1087 void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc, 1088 struct rvu_npc_mcam_rule *rule, 1089 struct npc_install_flow_rsp *rsp); 1090 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc, 1091 int blkaddr, int *alloc_cnt, 1092 int *enable_cnt); 1093 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc, 1094 int blkaddr, int *alloc_cnt, 1095 int *enable_cnt); 1096 void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf); 1097 1098 bool is_npc_intf_tx(u8 intf); 1099 bool is_npc_intf_rx(u8 intf); 1100 bool is_npc_interface_valid(struct rvu *rvu, u8 intf); 1101 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena); 1102 int npc_flow_steering_init(struct rvu *rvu, int blkaddr); 1103 const char *npc_get_field_name(u8 hdr); 1104 int npc_get_bank(struct npc_mcam *mcam, int index); 1105 void npc_mcam_enable_flows(struct rvu *rvu, u16 target); 1106 void npc_mcam_disable_flows(struct rvu *rvu, u16 target); 1107 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 1108 int blkaddr, int index, bool enable); 1109 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 1110 int blkaddr, int index); 1111 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam, 1112 int blkaddr, int index, u64 cfg); 1113 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam, 1114 int blkaddr, u16 src, struct mcam_entry *entry, 1115 u8 *intf, u8 *ena); 1116 int npc_config_cntr_default_entries(struct rvu *rvu, bool enable); 1117 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc); 1118 bool rvu_cgx_check_permission_and_set_pkind(struct rvu *rvu, u16 pcifunc, int pkind); 1119 bool rvu_cgx_is_pkind_config_permitted(struct rvu *rvu, u16 pcifunc); 1120 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); 1121 u32 rvu_cgx_get_fifolen(struct rvu *rvu); 1122 void *rvu_first_cgx_pdata(struct rvu *rvu); 1123 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id); 1124 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable); 1125 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable); 1126 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause, 1127 u16 pfc_en); 1128 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause); 1129 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc); 1130 u64 rvu_cgx_get_dmacflt_dropped_pktcnt(void *cgxd, int lmac_id); 1131 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac); 1132 void cgx_start_linkup(struct rvu *rvu); 1133 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, 1134 u16 pcifunc, int nixlf, int type); 1135 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr, 1136 int index); 1137 int rvu_npc_init(struct rvu *rvu); 1138 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx, 1139 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask, 1140 u64 bcast_mcast_val, u64 bcast_mcast_mask); 1141 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx); 1142 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf); 1143 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr); 1144 void npc_mcam_rsrcs_deinit(struct rvu *rvu); 1145 1146 /* CPT APIs */ 1147 int rvu_cpt_register_interrupts(struct rvu *rvu); 1148 void rvu_cpt_unregister_interrupts(struct rvu *rvu); 1149 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, 1150 int slot); 1151 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc); 1152 int rvu_cpt_init(struct rvu *rvu); 1153 u32 rvu_get_cpt_chan_mask(struct rvu *rvu); 1154 1155 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0) 1156 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16) 1157 1158 /* CN10K RVU */ 1159 int rvu_set_channels_base(struct rvu *rvu); 1160 void rvu_program_channels(struct rvu *rvu); 1161 1162 /* CN10K NIX */ 1163 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); 1164 1165 /* CN10K RVU - LMT*/ 1166 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); 1167 void rvu_apr_block_cn10k_init(struct rvu *rvu); 1168 1169 #ifdef CONFIG_DEBUG_FS 1170 void rvu_dbg_init(struct rvu *rvu); 1171 void rvu_dbg_exit(struct rvu *rvu); 1172 #else 1173 static inline void rvu_dbg_init(struct rvu *rvu) {} 1174 static inline void rvu_dbg_exit(struct rvu *rvu) {} 1175 #endif 1176 1177 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr); 1178 1179 /* RVU Switch */ 1180 void rvu_switch_enable(struct rvu *rvu); 1181 void rvu_switch_disable(struct rvu *rvu); 1182 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); 1183 void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena); 1184 1185 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir, 1186 u64 pkind, u8 var_len_off, u8 var_len_off_mask, 1187 u8 shift_dir, u8 skip_size); 1188 int rvu_get_hwvf(struct rvu *rvu, int pcifunc); 1189 1190 /* CN10K MCS */ 1191 int rvu_mcs_init(struct rvu *rvu); 1192 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc); 1193 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena); 1194 void rvu_mcs_exit(struct rvu *rvu); 1195 1196 /* Representor APIs */ 1197 int rvu_rep_pf_init(struct rvu *rvu); 1198 int rvu_rep_install_mcam_rules(struct rvu *rvu); 1199 void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); 1200 int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable); 1201 int npc_mcam_verify_entry(struct npc_mcam *mcam, u16 pcifunc, int entry); 1202 #endif /* RVU_H */ 1203