1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_DP_H 8 #define ATH12K_DP_H 9 10 #include "dp_stats.h" 11 #include "hw.h" 12 #include "dp_htt.h" 13 #include "dp_cmn.h" 14 #include <linux/rhashtable.h> 15 16 #define MAX_RXDMA_PER_PDEV 2 17 18 struct ath12k_base; 19 struct ath12k_dp_link_peer; 20 struct ath12k_dp; 21 struct ath12k_vif; 22 struct ath12k_link_vif; 23 struct ath12k_ext_irq_grp; 24 struct ath12k_dp_rx_tid; 25 struct ath12k_dp_rx_tid_rxq; 26 27 struct ath12k_dp_profile_params { 28 u32 tx_comp_ring_size; 29 u32 rxdma_monitor_buf_ring_size; 30 u32 rxdma_monitor_dst_ring_size; 31 u32 num_pool_tx_desc; 32 u32 rx_desc_count; 33 u32 rx_release_ring_size; 34 u32 rxdma_buf_ring_size; 35 }; 36 37 #define DP_MON_PURGE_TIMEOUT_MS 100 38 #define DP_MON_SERVICE_BUDGET 128 39 40 #define DP_ENCAP_TYPE_MAX 4 41 #define DP_ENCRYPT_TYPE_MAX 12 42 #define DP_DESC_TYPE_MAX 2 43 44 struct dp_srng { 45 u32 *vaddr_unaligned; 46 u32 *vaddr; 47 dma_addr_t paddr_unaligned; 48 dma_addr_t paddr; 49 int size; 50 u32 ring_id; 51 }; 52 53 struct dp_rxdma_mon_ring { 54 struct dp_srng refill_buf_ring; 55 struct idr bufs_idr; 56 /* Protects bufs_idr */ 57 spinlock_t idr_lock; 58 int bufs_max; 59 }; 60 61 struct dp_rxdma_ring { 62 struct dp_srng refill_buf_ring; 63 int bufs_max; 64 }; 65 66 #define ATH12K_TX_COMPL_NEXT(ring_size, x) (((x) + 1) % (ring_size)) 67 68 struct dp_tx_ring { 69 u8 tcl_data_ring_id; 70 struct dp_srng tcl_data_ring; 71 struct dp_srng tcl_comp_ring; 72 struct hal_wbm_completion_ring_tx *tx_status; 73 int tx_status_head; 74 int tx_status_tail; 75 }; 76 77 struct ath12k_pdev_mon_stats { 78 u32 status_ppdu_state; 79 u32 status_ppdu_start; 80 u32 status_ppdu_end; 81 u32 status_ppdu_compl; 82 u32 status_ppdu_start_mis; 83 u32 status_ppdu_end_mis; 84 u32 status_ppdu_done; 85 u32 dest_ppdu_done; 86 u32 dest_mpdu_done; 87 u32 dest_mpdu_drop; 88 u32 dup_mon_linkdesc_cnt; 89 u32 dup_mon_buf_cnt; 90 u32 dest_mon_stuck; 91 u32 dest_mon_not_reaped; 92 }; 93 94 enum dp_mon_status_buf_state { 95 DP_MON_STATUS_MATCH, 96 DP_MON_STATUS_NO_DMA, 97 DP_MON_STATUS_LAG, 98 DP_MON_STATUS_LEAD, 99 DP_MON_STATUS_REPLINISH, 100 }; 101 102 struct dp_link_desc_bank { 103 void *vaddr_unaligned; 104 void *vaddr; 105 dma_addr_t paddr_unaligned; 106 dma_addr_t paddr; 107 u32 size; 108 }; 109 110 /* Size to enforce scatter idle list mode */ 111 #define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 112 #define DP_LINK_DESC_BANKS_MAX 8 113 114 #define DP_LINK_DESC_START 0x4000 115 #define DP_LINK_DESC_SHIFT 3 116 117 #define DP_LINK_DESC_COOKIE_SET(id, page) \ 118 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 119 120 #define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 121 122 #define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 123 #define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 124 #define DP_RX_DESC_COOKIE_MAX \ 125 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 126 #define DP_NOT_PPDU_ID_WRAP_AROUND 20000 127 128 enum ath12k_dp_ppdu_state { 129 DP_PPDU_STATUS_START, 130 DP_PPDU_STATUS_DONE, 131 }; 132 133 struct dp_mon_mpdu { 134 struct list_head list; 135 struct sk_buff *head; 136 struct sk_buff *tail; 137 u32 err_bitmap; 138 u8 decap_format; 139 }; 140 141 #define DP_MON_MAX_STATUS_BUF 32 142 143 struct ath12k_mon_data { 144 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 145 struct hal_rx_mon_ppdu_info mon_ppdu_info; 146 147 u32 mon_ppdu_status; 148 u32 mon_last_buf_cookie; 149 u64 mon_last_linkdesc_paddr; 150 u16 chan_noise_floor; 151 u32 err_bitmap; 152 u8 decap_format; 153 154 struct ath12k_pdev_mon_stats rx_mon_stats; 155 enum dp_mon_status_buf_state buf_state; 156 /* lock for monitor data */ 157 spinlock_t mon_lock; 158 struct sk_buff_head rx_status_q; 159 struct dp_mon_mpdu *mon_mpdu; 160 struct list_head dp_rx_mon_mpdu_list; 161 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 162 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 163 }; 164 165 struct ath12k_pdev_dp { 166 u32 mac_id; 167 atomic_t num_tx_pending; 168 wait_queue_head_t tx_empty_waitq; 169 170 struct ath12k_dp *dp; 171 struct ieee80211_hw *hw; 172 u8 hw_link_id; 173 struct ath12k_dp_hw *dp_hw; 174 175 /* Protects ppdu stats */ 176 spinlock_t ppdu_list_lock; 177 struct ath12k_per_peer_tx_stats peer_tx_stats; 178 struct list_head ppdu_stats_info; 179 u32 ppdu_stat_list_depth; 180 181 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 182 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 183 184 struct ieee80211_rx_status rx_status; 185 struct ath12k_mon_data mon_data; 186 }; 187 188 #define DP_NUM_CLIENTS_MAX 64 189 #define DP_AVG_TIDS_PER_CLIENT 2 190 #define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 191 #define DP_AVG_MSDUS_PER_FLOW 128 192 #define DP_AVG_FLOWS_PER_TID 2 193 #define DP_AVG_MPDUS_PER_TID_MAX 128 194 #define DP_AVG_MSDUS_PER_MPDU 4 195 196 #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 197 198 #define DP_BA_WIN_SZ_MAX 1024 199 200 #define DP_TCL_NUM_RING_MAX 4 201 202 #define DP_IDLE_SCATTER_BUFS_MAX 16 203 204 #define DP_WBM_RELEASE_RING_SIZE 64 205 #define DP_TCL_DATA_RING_SIZE 512 206 #define DP_TCL_CMD_RING_SIZE 32 207 #define DP_TCL_STATUS_RING_SIZE 32 208 #define DP_REO_DST_RING_MAX 8 209 #define DP_REO_DST_RING_SIZE 2048 210 #define DP_REO_REINJECT_RING_SIZE 32 211 #define DP_REO_EXCEPTION_RING_SIZE 128 212 #define DP_REO_CMD_RING_SIZE 256 213 #define DP_REO_STATUS_RING_SIZE 2048 214 #define DP_RX_MAC_BUF_RING_SIZE 4096 215 #define DP_RXDMA_REFILL_RING_SIZE 2048 216 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 217 #define DP_RXDMA_MON_STATUS_RING_SIZE 1024 218 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 219 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 220 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 221 222 #define DP_TX_MONITOR_BUF_SIZE 2048 223 #define DP_TX_MONITOR_BUF_SIZE_MIN 48 224 #define DP_TX_MONITOR_BUF_SIZE_MAX 8192 225 226 #define DP_RX_BUFFER_SIZE 2048 227 #define DP_RX_BUFFER_SIZE_LITE 1024 228 #define DP_RX_BUFFER_ALIGN_SIZE 128 229 230 #define RX_MON_STATUS_BASE_BUF_SIZE 2048 231 #define RX_MON_STATUS_BUF_ALIGN 128 232 #define RX_MON_STATUS_BUF_RESERVATION 128 233 #define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 234 (RX_MON_STATUS_BUF_RESERVATION + \ 235 RX_MON_STATUS_BUF_ALIGN + \ 236 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))) 237 238 #define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 239 #define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 240 241 #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 242 #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 243 244 #define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 245 #define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 246 #define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 247 248 #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 249 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 250 251 #define ATH12K_PAGE_SIZE PAGE_SIZE 252 253 /* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 254 * SPT pages which makes lower 12bits 0 255 */ 256 #define ATH12K_MAX_PPT_ENTRIES 1024 257 258 /* Total 512 entries in a SPT, i.e 4K Page/8 */ 259 #define ATH12K_MAX_SPT_ENTRIES 512 260 261 #define ATH12K_TX_SPT_PAGE_OFFSET 0 262 263 #define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 264 265 /* 4K aligned address have last 12 bits set to 0, this check is done 266 * so that two spt pages address can be stored per 8bytes 267 * of CMEM (PPT) 268 */ 269 #define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 270 #define ATH12K_SPT_4K_ALIGN_OFFSET 12 271 #define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 272 273 /* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 274 #define ATH12K_CMEM_ADDR_MSB 0x10 275 276 /* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 277 #define ATH12K_CC_SPT_MSB 8 278 #define ATH12K_CC_PPT_MSB 19 279 #define ATH12K_CC_PPT_SHIFT 9 280 #define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0) 281 #define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 282 283 #define DP_REO_QREF_NUM GENMASK(31, 16) 284 #define DP_MAX_PEER_ID 2047 285 286 /* Total size of the LUT is based on 2K peers, each having reference 287 * for 17tids, note each entry is of type ath12k_reo_queue_ref 288 * hence total size is 2048 * 17 * 8 = 278528 289 */ 290 #define DP_REOQ_LUT_SIZE 278528 291 292 /* Invalid TX Bank ID value */ 293 #define DP_INVALID_BANK_ID -1 294 295 #define MAX_TQM_RELEASE_REASON 15 296 #define MAX_FW_TX_STATUS 7 297 298 struct ath12k_dp_tx_bank_profile { 299 u8 is_configured; 300 u32 num_users; 301 u32 bank_config; 302 }; 303 304 struct ath12k_hp_update_timer { 305 struct timer_list timer; 306 bool started; 307 bool init; 308 u32 tx_num; 309 u32 timer_tx_num; 310 u32 ring_id; 311 u32 interval; 312 struct ath12k_base *ab; 313 }; 314 315 struct ath12k_rx_desc_info { 316 struct list_head list; 317 struct sk_buff *skb; 318 u32 cookie; 319 u32 magic; 320 u8 in_use : 1, 321 device_id : 3, 322 reserved : 4; 323 }; 324 325 struct ath12k_tx_desc_info { 326 struct list_head list; 327 struct sk_buff *skb; 328 struct sk_buff *skb_ext_desc; 329 u32 desc_id; /* Cookie */ 330 u8 mac_id; 331 u8 pool_id; 332 }; 333 334 struct ath12k_tx_desc_params { 335 struct sk_buff *skb; 336 struct sk_buff *skb_ext_desc; 337 u8 mac_id; 338 }; 339 340 struct ath12k_spt_info { 341 dma_addr_t paddr; 342 u64 *vaddr; 343 }; 344 345 struct ath12k_reo_queue_ref { 346 u32 info0; 347 u32 info1; 348 } __packed; 349 350 struct ath12k_reo_q_addr_lut { 351 u32 *vaddr_unaligned; 352 u32 *vaddr; 353 dma_addr_t paddr_unaligned; 354 dma_addr_t paddr; 355 u32 size; 356 }; 357 358 struct ath12k_link_stats { 359 u32 tx_enqueued; 360 u32 tx_completed; 361 u32 tx_bcast_mcast; 362 u32 tx_dropped; 363 u32 tx_encap_type[DP_ENCAP_TYPE_MAX]; 364 u32 tx_encrypt_type[DP_ENCRYPT_TYPE_MAX]; 365 u32 tx_desc_type[DP_DESC_TYPE_MAX]; 366 }; 367 368 /* DP arch ops to communicate from common module 369 * to arch specific module 370 */ 371 struct ath12k_dp_arch_ops { 372 int (*service_srng)(struct ath12k_dp *dp, 373 struct ath12k_ext_irq_grp *irq_grp, 374 int budget); 375 u32 (*tx_get_vdev_bank_config)(struct ath12k_base *ab, 376 struct ath12k_link_vif *arvif); 377 int (*reo_cmd_send)(struct ath12k_base *ab, 378 struct ath12k_dp_rx_tid_rxq *rx_tid, 379 enum hal_reo_cmd_type type, 380 struct ath12k_hal_reo_cmd *cmd, 381 void (*cb)(struct ath12k_dp *dp, void *ctx, 382 enum hal_reo_cmd_status status)); 383 void (*setup_pn_check_reo_cmd)(struct ath12k_hal_reo_cmd *cmd, 384 struct ath12k_dp_rx_tid *rx_tid, 385 u32 cipher, enum set_key_cmd key_cmd); 386 void (*rx_peer_tid_delete)(struct ath12k_base *ab, 387 struct ath12k_dp_link_peer *peer, u8 tid); 388 int (*reo_cache_flush)(struct ath12k_base *ab, 389 struct ath12k_dp_rx_tid_rxq *rx_tid); 390 int (*rx_link_desc_return)(struct ath12k_dp *dp, 391 struct ath12k_buffer_addr *buf_addr_info, 392 enum hal_wbm_rel_bm_act action); 393 void (*rx_frags_cleanup)(struct ath12k_dp_rx_tid *rx_tid, 394 bool rel_link_desc); 395 int (*peer_rx_tid_reo_update)(struct ath12k_dp *dp, 396 struct ath12k_dp_link_peer *peer, 397 struct ath12k_dp_rx_tid *rx_tid, 398 u32 ba_win_sz, u16 ssn, 399 bool update_ssn); 400 int (*rx_assign_reoq)(struct ath12k_base *ab, struct ath12k_dp_peer *dp_peer, 401 struct ath12k_dp_rx_tid *rx_tid, 402 u16 ssn, enum hal_pn_type pn_type); 403 void (*peer_rx_tid_qref_setup)(struct ath12k_base *ab, u16 peer_id, u16 tid, 404 dma_addr_t paddr); 405 void (*peer_rx_tid_qref_reset)(struct ath12k_base *ab, u16 peer_id, u16 tid); 406 int (*rx_tid_delete_handler)(struct ath12k_base *ab, 407 struct ath12k_dp_rx_tid_rxq *rx_tid); 408 }; 409 410 struct ath12k_device_dp_tx_err_stats { 411 /* TCL Ring Descriptor unavailable */ 412 u32 desc_na[DP_TCL_NUM_RING_MAX]; 413 /* TX descriptor pool exhausted (per pool_id / traffic class) */ 414 u32 txbuf_na[ATH12K_HW_MAX_QUEUES]; 415 /* Other failures during dp_tx due to mem allocation failure 416 * idr unavailable etc. 417 */ 418 atomic_t misc_fail; 419 }; 420 421 struct ath12k_device_dp_rx_wbm_err_stats { 422 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 423 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 424 u32 drop[WBM_ERR_DROP_MAX]; 425 u32 sw_desc_fallback; 426 }; 427 428 struct ath12k_device_dp_stats { 429 u32 err_ring_pkts; 430 u32 invalid_rbm; 431 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 432 struct ath12k_device_dp_tx_err_stats tx_err; 433 struct ath12k_device_dp_rx_wbm_err_stats wbm_err; 434 u32 reo_rx[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES]; 435 u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX][ATH12K_MAX_DEVICES]; 436 u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON]; 437 u32 fw_tx_status[MAX_FW_TX_STATUS]; 438 u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX]; 439 u32 tx_enqueued[DP_TCL_NUM_RING_MAX]; 440 u32 tx_completed[DP_TCL_NUM_RING_MAX]; 441 u32 reo_excep_msdu_buf_type; 442 u32 sent_to_stack[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES]; 443 }; 444 445 struct ath12k_dp { 446 struct ath12k_base *ab; 447 u32 mon_dest_ring_stuck_cnt; 448 u8 num_bank_profiles; 449 /* protects the access and update of bank_profiles */ 450 spinlock_t tx_bank_lock; 451 struct ath12k_dp_tx_bank_profile *bank_profiles; 452 enum ath12k_htc_ep_id eid; 453 struct completion htt_tgt_version_received; 454 u8 htt_tgt_ver_major; 455 u8 htt_tgt_ver_minor; 456 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 457 enum hal_rx_buf_return_buf_manager idle_link_rbm; 458 struct dp_srng wbm_idle_ring; 459 struct dp_srng wbm_desc_rel_ring; 460 struct dp_srng reo_reinject_ring; 461 struct dp_srng rx_rel_ring; 462 struct dp_srng reo_except_ring; 463 struct dp_srng reo_cmd_ring; 464 struct dp_srng reo_status_ring; 465 enum ath12k_peer_metadata_version peer_metadata_ver; 466 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 467 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 468 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 469 struct list_head reo_cmd_update_rx_queue_list; 470 struct list_head reo_cmd_cache_flush_list; 471 u32 reo_cmd_cache_flush_count; 472 /* protects access to below fields, 473 * - reo_cmd_update_rx_queue_list 474 * - reo_cmd_cache_flush_list 475 * - reo_cmd_cache_flush_count 476 */ 477 spinlock_t reo_rxq_flush_lock; 478 struct list_head reo_cmd_list; 479 /* protects access to below fields, 480 * - reo_cmd_list 481 */ 482 spinlock_t reo_cmd_lock; 483 struct ath12k_hp_update_timer reo_cmd_timer; 484 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 485 struct ath12k_spt_info *spt_info; 486 u32 num_spt_pages; 487 u32 rx_ppt_base; 488 struct ath12k_rx_desc_info **rxbaddr; 489 struct ath12k_tx_desc_info **txbaddr; 490 struct list_head rx_desc_free_list; 491 /* protects the free desc list */ 492 spinlock_t rx_desc_lock; 493 494 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 495 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 496 /* protects the free and used desc lists */ 497 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 498 499 struct dp_rxdma_ring rx_refill_buf_ring; 500 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 501 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 502 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 503 struct dp_rxdma_mon_ring tx_mon_buf_ring; 504 struct dp_rxdma_mon_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 505 struct ath12k_reo_q_addr_lut reoq_lut; 506 struct ath12k_reo_q_addr_lut ml_reoq_lut; 507 const struct ath12k_hw_params *hw_params; 508 struct device *dev; 509 struct ath12k_hal *hal; 510 511 /* RCU on dp_pdevs[] provides a teardown synchronization mechanism, 512 * ensuring in-flight data path readers complete before reclaim. Writers 513 * update internal fields under their own synchronization, while readers of 514 * internal fields may perform lockless read if occasional inconsistency 515 * is acceptable or use additional synchronization for a coherent view. 516 * 517 * RCU is used for dp_pdevs[] at this stage to align with 518 * ab->pdevs_active[]. However, if the teardown paths ensure quiescence, 519 * both dp_pdevs[] and pdevs_active[] can be converted to plain pointers, 520 * removing RCU synchronize overhead. 521 * 522 * TODO: evaluate removal of RCU from dp_pdevs in the future 523 */ 524 struct ath12k_pdev_dp __rcu *dp_pdevs[MAX_RADIOS]; 525 526 struct ath12k_hw_group *ag; 527 u8 device_id; 528 529 /* Lock for protection of peers and rhead_peer_addr */ 530 spinlock_t dp_lock; 531 532 const struct ath12k_dp_arch_ops *ops; 533 534 /* Linked list of struct ath12k_dp_link_peer */ 535 struct list_head peers; 536 537 /* For rhash table init and deinit protection */ 538 struct mutex link_peer_rhash_tbl_lock; 539 540 /* The rhashtable containing struct ath12k_link_peer keyed by mac addr */ 541 struct rhashtable *rhead_peer_addr; 542 struct rhashtable_params rhash_peer_addr_param; 543 struct ath12k_device_dp_stats device_stats; 544 }; 545 546 static inline u32 ath12k_dp_arch_tx_get_vdev_bank_config(struct ath12k_dp *dp, 547 struct ath12k_link_vif *arvif) 548 { 549 return dp->ops->tx_get_vdev_bank_config(dp->ab, arvif); 550 } 551 552 static inline int ath12k_dp_arch_reo_cmd_send(struct ath12k_dp *dp, 553 struct ath12k_dp_rx_tid_rxq *rx_tid, 554 enum hal_reo_cmd_type type, 555 struct ath12k_hal_reo_cmd *cmd, 556 void (*cb)(struct ath12k_dp *dp, void *ctx, 557 enum hal_reo_cmd_status status)) 558 { 559 return dp->ops->reo_cmd_send(dp->ab, rx_tid, type, cmd, cb); 560 } 561 562 static inline 563 void ath12k_dp_arch_setup_pn_check_reo_cmd(struct ath12k_dp *dp, 564 struct ath12k_hal_reo_cmd *cmd, 565 struct ath12k_dp_rx_tid *rx_tid, 566 u32 cipher, 567 enum set_key_cmd key_cmd) 568 { 569 dp->ops->setup_pn_check_reo_cmd(cmd, rx_tid, cipher, key_cmd); 570 } 571 572 static inline void ath12k_dp_arch_rx_peer_tid_delete(struct ath12k_dp *dp, 573 struct ath12k_dp_link_peer *peer, 574 u8 tid) 575 { 576 dp->ops->rx_peer_tid_delete(dp->ab, peer, tid); 577 } 578 579 static inline int ath12k_dp_arch_reo_cache_flush(struct ath12k_dp *dp, 580 struct ath12k_dp_rx_tid_rxq *rx_tid) 581 { 582 return dp->ops->reo_cache_flush(dp->ab, rx_tid); 583 } 584 585 static inline 586 int ath12k_dp_arch_rx_link_desc_return(struct ath12k_dp *dp, 587 struct ath12k_buffer_addr *buf_addr_info, 588 enum hal_wbm_rel_bm_act action) 589 { 590 return dp->ops->rx_link_desc_return(dp, buf_addr_info, action); 591 } 592 593 static inline 594 void ath12k_dp_arch_rx_frags_cleanup(struct ath12k_dp *dp, 595 struct ath12k_dp_rx_tid *rx_tid, 596 bool rel_link_desc) 597 { 598 dp->ops->rx_frags_cleanup(rx_tid, rel_link_desc); 599 } 600 601 static inline int ath12k_dp_arch_peer_rx_tid_reo_update(struct ath12k_dp *dp, 602 struct ath12k_dp_link_peer *peer, 603 struct ath12k_dp_rx_tid *rx_tid, 604 u32 ba_win_sz, u16 ssn, 605 bool update_ssn) 606 { 607 return dp->ops->peer_rx_tid_reo_update(dp, peer, rx_tid, 608 ba_win_sz, ssn, update_ssn); 609 } 610 611 static inline int ath12k_dp_arch_rx_assign_reoq(struct ath12k_dp *dp, 612 struct ath12k_dp_peer *dp_peer, 613 struct ath12k_dp_rx_tid *rx_tid, 614 u16 ssn, enum hal_pn_type pn_type) 615 { 616 return dp->ops->rx_assign_reoq(dp->ab, dp_peer, rx_tid, ssn, pn_type); 617 } 618 619 static inline void ath12k_dp_arch_peer_rx_tid_qref_setup(struct ath12k_dp *dp, 620 u16 peer_id, u16 tid, 621 dma_addr_t paddr) 622 { 623 dp->ops->peer_rx_tid_qref_setup(dp->ab, peer_id, tid, paddr); 624 } 625 626 static inline void ath12k_dp_arch_peer_rx_tid_qref_reset(struct ath12k_dp *dp, 627 u16 peer_id, u16 tid) 628 { 629 dp->ops->peer_rx_tid_qref_reset(dp->ab, peer_id, tid); 630 } 631 632 static inline 633 int ath12k_dp_arch_rx_tid_delete_handler(struct ath12k_dp *dp, 634 struct ath12k_dp_rx_tid_rxq *rx_tid) 635 { 636 return dp->ops->rx_tid_delete_handler(dp->ab, rx_tid); 637 } 638 639 static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 640 { 641 memcpy(addr, &addr_l32, 4); 642 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 643 } 644 645 static inline struct ath12k_dp * 646 ath12k_dp_hw_grp_to_dp(struct ath12k_dp_hw_group *dp_hw_grp, u8 device_id) 647 { 648 return dp_hw_grp->dp[device_id]; 649 } 650 651 static inline int 652 ath12k_dp_service_srng(struct ath12k_dp *dp, struct ath12k_ext_irq_grp *irq_grp, 653 int budget) 654 { 655 return dp->ops->service_srng(dp, irq_grp, budget); 656 } 657 658 static inline struct ieee80211_hw * 659 ath12k_pdev_dp_to_hw(struct ath12k_pdev_dp *pdev) 660 { 661 return pdev->hw; 662 } 663 664 static inline struct ath12k_pdev_dp * 665 ath12k_dp_to_pdev_dp(struct ath12k_dp *dp, u8 pdev_idx) 666 { 667 RCU_LOCKDEP_WARN(!rcu_read_lock_held(), 668 "ath12k dp to dp pdev called without rcu lock"); 669 670 return rcu_dereference(dp->dp_pdevs[pdev_idx]); 671 } 672 673 static inline u32 674 ath12k_dp_tx_comp_ring_size(const struct ath12k_dp_profile_params *p) 675 { 676 return p->tx_comp_ring_size; 677 } 678 679 static inline u32 680 ath12k_dp_rxdma_monitor_buf_ring_size(const struct ath12k_dp_profile_params *p) 681 { 682 return p->rxdma_monitor_buf_ring_size; 683 } 684 685 static inline u32 686 ath12k_dp_rxdma_monitor_dst_ring_size(const struct ath12k_dp_profile_params *p) 687 { 688 return p->rxdma_monitor_dst_ring_size; 689 } 690 691 static inline u32 692 ath12k_dp_num_pool_tx_desc(const struct ath12k_dp_profile_params *p) 693 { 694 return p->num_pool_tx_desc; 695 } 696 697 static inline u32 698 ath12k_dp_tx_spt_pages_per_pool(const struct ath12k_dp_profile_params *p) 699 { 700 return ath12k_dp_num_pool_tx_desc(p) / ATH12K_MAX_SPT_ENTRIES; 701 } 702 703 static inline u32 704 ath12k_dp_num_tx_spt_pages(const struct ath12k_dp_profile_params *p) 705 { 706 return ath12k_dp_tx_spt_pages_per_pool(p) * ATH12K_HW_MAX_QUEUES; 707 } 708 709 static inline u32 710 ath12k_dp_rx_spt_page_offset(const struct ath12k_dp_profile_params *p) 711 { 712 return ath12k_dp_num_tx_spt_pages(p); 713 } 714 715 static inline u32 716 ath12k_dp_rx_desc_count(const struct ath12k_dp_profile_params *p) 717 { 718 return p->rx_desc_count; 719 } 720 721 static inline u32 722 ath12k_dp_num_rx_spt_pages(const struct ath12k_dp_profile_params *p) 723 { 724 return ath12k_dp_rx_desc_count(p) / ATH12K_MAX_SPT_ENTRIES; 725 } 726 727 static inline u32 728 ath12k_dp_rx_release_ring_size(const struct ath12k_dp_profile_params *p) 729 { 730 return p->rx_release_ring_size; 731 } 732 733 static inline u32 734 ath12k_dp_rxdma_buf_ring_size(const struct ath12k_dp_profile_params *p) 735 { 736 return p->rxdma_buf_ring_size; 737 } 738 739 void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif); 740 void ath12k_dp_partner_cc_init(struct ath12k_base *ab); 741 int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 742 void ath12k_dp_pdev_pre_alloc(struct ath12k *ar); 743 void ath12k_dp_pdev_free(struct ath12k_base *ab); 744 int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 745 void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 746 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 747 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 748 enum hal_ring_type type, int ring_num, 749 int mac_id, int num_entries); 750 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 751 struct dp_link_desc_bank *desc_bank, 752 u32 ring_type, struct dp_srng *ring); 753 int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 754 struct dp_link_desc_bank *link_desc_banks, 755 u32 ring_type, struct hal_srng *srng, 756 u32 n_link_desc); 757 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_dp *dp, 758 u32 cookie); 759 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_dp *dp, 760 u32 desc_id); 761 void ath12k_dp_reoq_lut_addr_reset(struct ath12k_dp *dp); 762 #endif 763