1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file owns the programming sequence of stream's dpms state associated 28 * with the link and link's enable/disable sequences as result of the stream's 29 * dpms state change. 30 * 31 * TODO - The reason link owns stream's dpms programming sequence is 32 * because dpms programming sequence is highly dependent on underlying signal 33 * specific link protocols. This unfortunately causes link to own a portion of 34 * stream state programming sequence. This creates a gray area where the 35 * boundary between link and stream is not clearly defined. 36 */ 37 38 #include "link_dpms.h" 39 #include "link_hwss.h" 40 #include "link_validation.h" 41 #include "accessories/link_dp_trace.h" 42 #include "protocols/link_dpcd.h" 43 #include "protocols/link_ddc.h" 44 #include "protocols/link_hpd.h" 45 #include "protocols/link_dp_phy.h" 46 #include "protocols/link_dp_capability.h" 47 #include "protocols/link_dp_training.h" 48 #include "protocols/link_edp_panel_control.h" 49 #include "protocols/link_dp_dpia_bw.h" 50 51 #include "dm_helpers.h" 52 #include "link_enc_cfg.h" 53 #include "resource.h" 54 #include "dsc.h" 55 #include "dccg.h" 56 #include "clk_mgr.h" 57 #include "atomfirmware.h" 58 #include "vpg.h" 59 60 #define DC_LOGGER \ 61 dc_logger 62 #define DC_LOGGER_INIT(logger) \ 63 struct dal_logger *dc_logger = logger 64 65 #define LINK_INFO(...) \ 66 DC_LOG_HW_HOTPLUG( \ 67 __VA_ARGS__) 68 69 #define RETIMER_REDRIVER_INFO(...) \ 70 DC_LOG_RETIMER_REDRIVER( \ 71 __VA_ARGS__) 72 73 #define MAX_MTP_SLOT_COUNT 64 74 #define LINK_TRAINING_ATTEMPTS 4 75 #define PEAK_FACTOR_X1000 1006 76 77 void link_blank_all_dp_displays(struct dc *dc) 78 { 79 unsigned int i; 80 uint8_t dpcd_power_state = '\0'; 81 enum dc_status status = DC_ERROR_UNEXPECTED; 82 83 for (i = 0; i < dc->link_count; i++) { 84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || 85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) 86 continue; 87 88 /* DP 2.0 spec requires that we read LTTPR caps first */ 89 dp_retrieve_lttpr_cap(dc->links[i]); 90 /* if any of the displays are lit up turn them off */ 91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 92 &dpcd_power_state, sizeof(dpcd_power_state)); 93 94 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 95 link_blank_dp_stream(dc->links[i], true); 96 } 97 98 } 99 100 void link_blank_all_edp_displays(struct dc *dc) 101 { 102 unsigned int i; 103 uint8_t dpcd_power_state = '\0'; 104 enum dc_status status = DC_ERROR_UNEXPECTED; 105 106 for (i = 0; i < dc->link_count; i++) { 107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || 108 (!dc->links[i]->edp_sink_present)) 109 continue; 110 111 /* if any of the displays are lit up turn them off */ 112 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 113 &dpcd_power_state, sizeof(dpcd_power_state)); 114 115 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) 116 link_blank_dp_stream(dc->links[i], true); 117 } 118 } 119 120 void link_blank_dp_stream(struct dc_link *link, bool hw_init) 121 { 122 unsigned int j; 123 struct dc *dc = link->ctx->dc; 124 enum signal_type signal = link->connector_signal; 125 126 if ((signal == SIGNAL_TYPE_EDP) || 127 (signal == SIGNAL_TYPE_DISPLAY_PORT)) { 128 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 129 link->link_enc->funcs->get_dig_frontend && 130 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 131 int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc); 132 133 if (fe != ENGINE_ID_UNKNOWN) 134 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 135 if (fe == dc->res_pool->stream_enc[j]->id) { 136 dc->res_pool->stream_enc[j]->funcs->dp_blank(link, 137 dc->res_pool->stream_enc[j]); 138 break; 139 } 140 } 141 } 142 143 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init) 144 dpcd_write_rx_power_ctrl(link, false); 145 } 146 } 147 148 void link_set_all_streams_dpms_off_for_link(struct dc_link *link) 149 { 150 struct pipe_ctx *pipes[MAX_PIPES]; 151 struct dc_state *state = link->dc->current_state; 152 uint8_t count; 153 int i; 154 struct dc_stream_update stream_update; 155 bool dpms_off = true; 156 struct link_resource link_res = {0}; 157 158 memset(&stream_update, 0, sizeof(stream_update)); 159 stream_update.dpms_off = &dpms_off; 160 161 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); 162 163 for (i = 0; i < count; i++) { 164 stream_update.stream = pipes[i]->stream; 165 dc_commit_updates_for_stream(link->ctx->dc, NULL, 0, 166 pipes[i]->stream, &stream_update, 167 state); 168 } 169 170 /* link can be also enabled by vbios. In this case it is not recorded 171 * in pipe_ctx. Disable link phy here to make sure it is completely off 172 */ 173 dp_disable_link_phy(link, &link_res, link->connector_signal); 174 } 175 176 void link_resume(struct dc_link *link) 177 { 178 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 179 program_hpd_filter(link); 180 } 181 182 /* This function returns true if the pipe is used to feed video signal directly 183 * to the link. 184 */ 185 static bool is_master_pipe_for_link(const struct dc_link *link, 186 const struct pipe_ctx *pipe) 187 { 188 return resource_is_pipe_type(pipe, OTG_MASTER) && 189 pipe->stream->link == link; 190 } 191 192 /* 193 * This function finds all master pipes feeding to a given link with dpms set to 194 * on in given dc state. 195 */ 196 void link_get_master_pipes_with_dpms_on(const struct dc_link *link, 197 struct dc_state *state, 198 uint8_t *count, 199 struct pipe_ctx *pipes[MAX_PIPES]) 200 { 201 int i; 202 struct pipe_ctx *pipe = NULL; 203 204 *count = 0; 205 for (i = 0; i < MAX_PIPES; i++) { 206 pipe = &state->res_ctx.pipe_ctx[i]; 207 208 if (is_master_pipe_for_link(link, pipe) && 209 pipe->stream->dpms_off == false) { 210 pipes[(*count)++] = pipe; 211 } 212 } 213 } 214 215 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 216 enum engine_id eng_id, 217 struct ext_hdmi_settings *settings) 218 { 219 bool result = false; 220 int i = 0; 221 struct integrated_info *integrated_info = 222 pipe_ctx->stream->ctx->dc_bios->integrated_info; 223 224 if (integrated_info == NULL) 225 return false; 226 227 /* 228 * Get retimer settings from sbios for passing SI eye test for DCE11 229 * The setting values are varied based on board revision and port id 230 * Therefore the setting values of each ports is passed by sbios. 231 */ 232 233 // Check if current bios contains ext Hdmi settings 234 if (integrated_info->gpu_cap_info & 0x20) { 235 switch (eng_id) { 236 case ENGINE_ID_DIGA: 237 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 238 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 239 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 240 memmove(settings->reg_settings, 241 integrated_info->dp0_ext_hdmi_reg_settings, 242 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 243 memmove(settings->reg_settings_6g, 244 integrated_info->dp0_ext_hdmi_6g_reg_settings, 245 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 246 result = true; 247 break; 248 case ENGINE_ID_DIGB: 249 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 250 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 251 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 252 memmove(settings->reg_settings, 253 integrated_info->dp1_ext_hdmi_reg_settings, 254 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 255 memmove(settings->reg_settings_6g, 256 integrated_info->dp1_ext_hdmi_6g_reg_settings, 257 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 258 result = true; 259 break; 260 case ENGINE_ID_DIGC: 261 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 262 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 263 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 264 memmove(settings->reg_settings, 265 integrated_info->dp2_ext_hdmi_reg_settings, 266 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 267 memmove(settings->reg_settings_6g, 268 integrated_info->dp2_ext_hdmi_6g_reg_settings, 269 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 270 result = true; 271 break; 272 case ENGINE_ID_DIGD: 273 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 274 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 275 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 276 memmove(settings->reg_settings, 277 integrated_info->dp3_ext_hdmi_reg_settings, 278 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 279 memmove(settings->reg_settings_6g, 280 integrated_info->dp3_ext_hdmi_6g_reg_settings, 281 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 282 result = true; 283 break; 284 default: 285 break; 286 } 287 288 if (result == true) { 289 // Validate settings from bios integrated info table 290 if (settings->slv_addr == 0) 291 return false; 292 if (settings->reg_num > 9) 293 return false; 294 if (settings->reg_num_6g > 3) 295 return false; 296 297 for (i = 0; i < settings->reg_num; i++) { 298 if (settings->reg_settings[i].i2c_reg_index > 0x20) 299 return false; 300 } 301 302 for (i = 0; i < settings->reg_num_6g; i++) { 303 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 304 return false; 305 } 306 } 307 } 308 309 return result; 310 } 311 312 static bool write_i2c(struct pipe_ctx *pipe_ctx, 313 uint8_t address, uint8_t *buffer, uint32_t length) 314 { 315 struct i2c_command cmd = {0}; 316 struct i2c_payload payload = {0}; 317 318 memset(&payload, 0, sizeof(payload)); 319 memset(&cmd, 0, sizeof(cmd)); 320 321 cmd.number_of_payloads = 1; 322 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 323 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 324 325 payload.address = address; 326 payload.data = buffer; 327 payload.length = length; 328 payload.write = true; 329 cmd.payloads = &payload; 330 331 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 332 pipe_ctx->stream->link, &cmd)) 333 return true; 334 335 return false; 336 } 337 338 static void write_i2c_retimer_setting( 339 struct pipe_ctx *pipe_ctx, 340 bool is_vga_mode, 341 bool is_over_340mhz, 342 struct ext_hdmi_settings *settings) 343 { 344 uint8_t slave_address = (settings->slv_addr >> 1); 345 uint8_t buffer[2]; 346 const uint8_t apply_rx_tx_change = 0x4; 347 uint8_t offset = 0xA; 348 uint8_t value = 0; 349 int i = 0; 350 bool i2c_success = false; 351 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 352 353 memset(&buffer, 0, sizeof(buffer)); 354 355 /* Start Ext-Hdmi programming*/ 356 357 for (i = 0; i < settings->reg_num; i++) { 358 /* Apply 3G settings */ 359 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 360 361 buffer[0] = settings->reg_settings[i].i2c_reg_index; 362 buffer[1] = settings->reg_settings[i].i2c_reg_val; 363 i2c_success = write_i2c(pipe_ctx, slave_address, 364 buffer, sizeof(buffer)); 365 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 366 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 367 slave_address, buffer[0], buffer[1], i2c_success?1:0); 368 369 if (!i2c_success) 370 goto i2c_write_fail; 371 372 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 373 * needs to be set to 1 on every 0xA-0xC write. 374 */ 375 if (settings->reg_settings[i].i2c_reg_index == 0xA || 376 settings->reg_settings[i].i2c_reg_index == 0xB || 377 settings->reg_settings[i].i2c_reg_index == 0xC) { 378 379 /* Query current value from offset 0xA */ 380 if (settings->reg_settings[i].i2c_reg_index == 0xA) 381 value = settings->reg_settings[i].i2c_reg_val; 382 else { 383 i2c_success = 384 link_query_ddc_data( 385 pipe_ctx->stream->link->ddc, 386 slave_address, &offset, 1, &value, 1); 387 if (!i2c_success) 388 goto i2c_write_fail; 389 } 390 391 buffer[0] = offset; 392 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 393 buffer[1] = value | apply_rx_tx_change; 394 i2c_success = write_i2c(pipe_ctx, slave_address, 395 buffer, sizeof(buffer)); 396 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 397 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 398 slave_address, buffer[0], buffer[1], i2c_success?1:0); 399 if (!i2c_success) 400 goto i2c_write_fail; 401 } 402 } 403 } 404 405 /* Apply 3G settings */ 406 if (is_over_340mhz) { 407 for (i = 0; i < settings->reg_num_6g; i++) { 408 /* Apply 3G settings */ 409 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 410 411 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 412 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 413 i2c_success = write_i2c(pipe_ctx, slave_address, 414 buffer, sizeof(buffer)); 415 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 416 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 417 slave_address, buffer[0], buffer[1], i2c_success?1:0); 418 419 if (!i2c_success) 420 goto i2c_write_fail; 421 422 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 423 * needs to be set to 1 on every 0xA-0xC write. 424 */ 425 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 426 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 427 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 428 429 /* Query current value from offset 0xA */ 430 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 431 value = settings->reg_settings_6g[i].i2c_reg_val; 432 else { 433 i2c_success = 434 link_query_ddc_data( 435 pipe_ctx->stream->link->ddc, 436 slave_address, &offset, 1, &value, 1); 437 if (!i2c_success) 438 goto i2c_write_fail; 439 } 440 441 buffer[0] = offset; 442 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 443 buffer[1] = value | apply_rx_tx_change; 444 i2c_success = write_i2c(pipe_ctx, slave_address, 445 buffer, sizeof(buffer)); 446 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 447 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 448 slave_address, buffer[0], buffer[1], i2c_success?1:0); 449 if (!i2c_success) 450 goto i2c_write_fail; 451 } 452 } 453 } 454 } 455 456 if (is_vga_mode) { 457 /* Program additional settings if using 640x480 resolution */ 458 459 /* Write offset 0xFF to 0x01 */ 460 buffer[0] = 0xff; 461 buffer[1] = 0x01; 462 i2c_success = write_i2c(pipe_ctx, slave_address, 463 buffer, sizeof(buffer)); 464 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 465 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 466 slave_address, buffer[0], buffer[1], i2c_success?1:0); 467 if (!i2c_success) 468 goto i2c_write_fail; 469 470 /* Write offset 0x00 to 0x23 */ 471 buffer[0] = 0x00; 472 buffer[1] = 0x23; 473 i2c_success = write_i2c(pipe_ctx, slave_address, 474 buffer, sizeof(buffer)); 475 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 476 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 477 slave_address, buffer[0], buffer[1], i2c_success?1:0); 478 if (!i2c_success) 479 goto i2c_write_fail; 480 481 /* Write offset 0xff to 0x00 */ 482 buffer[0] = 0xff; 483 buffer[1] = 0x00; 484 i2c_success = write_i2c(pipe_ctx, slave_address, 485 buffer, sizeof(buffer)); 486 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 487 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 488 slave_address, buffer[0], buffer[1], i2c_success?1:0); 489 if (!i2c_success) 490 goto i2c_write_fail; 491 492 } 493 494 return; 495 496 i2c_write_fail: 497 DC_LOG_DEBUG("Set retimer failed"); 498 } 499 500 static void write_i2c_default_retimer_setting( 501 struct pipe_ctx *pipe_ctx, 502 bool is_vga_mode, 503 bool is_over_340mhz) 504 { 505 uint8_t slave_address = (0xBA >> 1); 506 uint8_t buffer[2]; 507 bool i2c_success = false; 508 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 509 510 memset(&buffer, 0, sizeof(buffer)); 511 512 /* Program Slave Address for tuning single integrity */ 513 /* Write offset 0x0A to 0x13 */ 514 buffer[0] = 0x0A; 515 buffer[1] = 0x13; 516 i2c_success = write_i2c(pipe_ctx, slave_address, 517 buffer, sizeof(buffer)); 518 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 519 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 520 slave_address, buffer[0], buffer[1], i2c_success?1:0); 521 if (!i2c_success) 522 goto i2c_write_fail; 523 524 /* Write offset 0x0A to 0x17 */ 525 buffer[0] = 0x0A; 526 buffer[1] = 0x17; 527 i2c_success = write_i2c(pipe_ctx, slave_address, 528 buffer, sizeof(buffer)); 529 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 530 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 531 slave_address, buffer[0], buffer[1], i2c_success?1:0); 532 if (!i2c_success) 533 goto i2c_write_fail; 534 535 /* Write offset 0x0B to 0xDA or 0xD8 */ 536 buffer[0] = 0x0B; 537 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 538 i2c_success = write_i2c(pipe_ctx, slave_address, 539 buffer, sizeof(buffer)); 540 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 541 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 542 slave_address, buffer[0], buffer[1], i2c_success?1:0); 543 if (!i2c_success) 544 goto i2c_write_fail; 545 546 /* Write offset 0x0A to 0x17 */ 547 buffer[0] = 0x0A; 548 buffer[1] = 0x17; 549 i2c_success = write_i2c(pipe_ctx, slave_address, 550 buffer, sizeof(buffer)); 551 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 552 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 553 slave_address, buffer[0], buffer[1], i2c_success?1:0); 554 if (!i2c_success) 555 goto i2c_write_fail; 556 557 /* Write offset 0x0C to 0x1D or 0x91 */ 558 buffer[0] = 0x0C; 559 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 560 i2c_success = write_i2c(pipe_ctx, slave_address, 561 buffer, sizeof(buffer)); 562 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 563 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 564 slave_address, buffer[0], buffer[1], i2c_success?1:0); 565 if (!i2c_success) 566 goto i2c_write_fail; 567 568 /* Write offset 0x0A to 0x17 */ 569 buffer[0] = 0x0A; 570 buffer[1] = 0x17; 571 i2c_success = write_i2c(pipe_ctx, slave_address, 572 buffer, sizeof(buffer)); 573 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 574 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 575 slave_address, buffer[0], buffer[1], i2c_success?1:0); 576 if (!i2c_success) 577 goto i2c_write_fail; 578 579 580 if (is_vga_mode) { 581 /* Program additional settings if using 640x480 resolution */ 582 583 /* Write offset 0xFF to 0x01 */ 584 buffer[0] = 0xff; 585 buffer[1] = 0x01; 586 i2c_success = write_i2c(pipe_ctx, slave_address, 587 buffer, sizeof(buffer)); 588 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 589 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 590 slave_address, buffer[0], buffer[1], i2c_success?1:0); 591 if (!i2c_success) 592 goto i2c_write_fail; 593 594 /* Write offset 0x00 to 0x23 */ 595 buffer[0] = 0x00; 596 buffer[1] = 0x23; 597 i2c_success = write_i2c(pipe_ctx, slave_address, 598 buffer, sizeof(buffer)); 599 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 600 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 601 slave_address, buffer[0], buffer[1], i2c_success?1:0); 602 if (!i2c_success) 603 goto i2c_write_fail; 604 605 /* Write offset 0xff to 0x00 */ 606 buffer[0] = 0xff; 607 buffer[1] = 0x00; 608 i2c_success = write_i2c(pipe_ctx, slave_address, 609 buffer, sizeof(buffer)); 610 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 611 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 612 slave_address, buffer[0], buffer[1], i2c_success?1:0); 613 if (!i2c_success) 614 goto i2c_write_fail; 615 } 616 617 return; 618 619 i2c_write_fail: 620 DC_LOG_DEBUG("Set default retimer failed"); 621 } 622 623 static void write_i2c_redriver_setting( 624 struct pipe_ctx *pipe_ctx, 625 bool is_over_340mhz) 626 { 627 uint8_t slave_address = (0xF0 >> 1); 628 uint8_t buffer[16]; 629 bool i2c_success = false; 630 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 631 632 memset(&buffer, 0, sizeof(buffer)); 633 634 // Program Slave Address for tuning single integrity 635 buffer[3] = 0x4E; 636 buffer[4] = 0x4E; 637 buffer[5] = 0x4E; 638 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 639 640 i2c_success = write_i2c(pipe_ctx, slave_address, 641 buffer, sizeof(buffer)); 642 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 643 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 644 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 645 i2c_success = %d\n", 646 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 647 648 if (!i2c_success) 649 DC_LOG_DEBUG("Set redriver failed"); 650 } 651 652 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 653 { 654 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 655 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 656 struct cp_psp_stream_config config = {0}; 657 enum dp_panel_mode panel_mode = 658 dp_get_panel_mode(pipe_ctx->stream->link); 659 660 if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL) 661 return; 662 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) 663 link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); 664 ASSERT(link_enc); 665 if (link_enc == NULL) 666 return; 667 668 /* otg instance */ 669 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 670 671 /* dig front end */ 672 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; 673 674 /* stream encoder index */ 675 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; 676 if (dp_is_128b_132b_signal(pipe_ctx)) 677 config.stream_enc_idx = 678 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; 679 680 /* dig back end */ 681 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; 682 683 /* link encoder index */ 684 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 685 if (dp_is_128b_132b_signal(pipe_ctx)) 686 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst; 687 688 /* dio output index is dpia index for DPIA endpoint & dcio index by default */ 689 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 690 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1; 691 else 692 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; 693 694 695 /* phy index */ 696 config.phy_idx = resource_transmitter_to_phy_idx( 697 pipe_ctx->stream->link->dc, link_enc->transmitter); 698 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 699 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */ 700 config.phy_idx = 0; 701 702 /* stream properties */ 703 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0; 704 config.mst_enabled = (pipe_ctx->stream->signal == 705 SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0; 706 config.dp2_enabled = dp_is_128b_132b_signal(pipe_ctx) ? 1 : 0; 707 config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? 708 1 : 0; 709 config.dpms_off = dpms_off; 710 711 /* dm stream context */ 712 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 713 714 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 715 } 716 717 static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 718 { 719 struct dc *dc = pipe_ctx->stream->ctx->dc; 720 721 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 722 return; 723 724 dc->hwss.set_avmute(pipe_ctx, enable); 725 } 726 727 static void enable_mst_on_sink(struct dc_link *link, bool enable) 728 { 729 unsigned char mstmCntl = 0; 730 731 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 732 if (enable) 733 mstmCntl |= DP_MST_EN; 734 else 735 mstmCntl &= (~DP_MST_EN); 736 737 core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1); 738 } 739 740 static void dsc_optc_config_log(struct display_stream_compressor *dsc, 741 struct dsc_optc_config *config) 742 { 743 uint32_t precision = 1 << 28; 744 uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision; 745 uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision; 746 uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod; 747 DC_LOGGER_INIT(dsc->ctx->logger); 748 749 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC 750 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is 751 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal 752 */ 753 ll_bytes_per_pix_fraq *= 10000000; 754 ll_bytes_per_pix_fraq /= precision; 755 756 DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)", 757 config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq); 758 DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444); 759 DC_LOG_DSC("\tslice_width %d", config->slice_width); 760 } 761 762 static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) 763 { 764 struct dc *dc = pipe_ctx->stream->ctx->dc; 765 struct dc_stream_state *stream = pipe_ctx->stream; 766 bool result = false; 767 768 if (dc_is_virtual_signal(stream->signal)) 769 result = true; 770 else 771 result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); 772 return result; 773 } 774 775 static bool dp_set_hblank_reduction_on_rx(struct pipe_ctx *pipe_ctx) 776 { 777 struct dc *dc = pipe_ctx->stream->ctx->dc; 778 struct dc_stream_state *stream = pipe_ctx->stream; 779 bool result = false; 780 781 if (dc_is_virtual_signal(stream->signal)) 782 result = true; 783 else 784 result = dm_helpers_dp_write_hblank_reduction(dc->ctx, stream); 785 return result; 786 } 787 788 789 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, 790 * i.e. after dp_enable_dsc_on_rx() had been called 791 */ 792 void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) 793 { 794 /* TODO: Move this to HWSS as this is hardware programming sequence not a 795 * link layer sequence 796 */ 797 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 798 struct dc *dc = pipe_ctx->stream->ctx->dc; 799 struct dc_stream_state *stream = pipe_ctx->stream; 800 struct pipe_ctx *odm_pipe; 801 int opp_cnt = 1; 802 struct dccg *dccg = dc->res_pool->dccg; 803 /* It has been found that when DSCCLK is lower than 16Mhz, we will get DCN 804 * register access hung. When DSCCLk is based on refclk, DSCCLk is always a 805 * fixed value higher than 16Mhz so the issue doesn't occur. When DSCCLK is 806 * generated by DTO, DSCCLK would be based on 1/3 dispclk. For small timings 807 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger 808 * this problem. We are implementing a workaround here to keep using dscclk 809 * based on fixed value refclk when timing is smaller than 3x16Mhz (i.e 810 * 48Mhz) pixel clock to avoid hitting this problem. 811 */ 812 bool should_use_dto_dscclk = (dccg->funcs->set_dto_dscclk != NULL) && 813 stream->timing.pix_clk_100hz > 480000; 814 DC_LOGGER_INIT(dsc->ctx->logger); 815 816 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 817 opp_cnt++; 818 819 if (enable) { 820 struct dsc_config dsc_cfg; 821 struct dsc_optc_config dsc_optc_cfg = {0}; 822 enum optc_dsc_mode optc_dsc_mode; 823 824 /* Enable DSC hw block */ 825 dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->hblank_borrow + 826 stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 827 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 828 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 829 dsc_cfg.color_depth = stream->timing.display_color_depth; 830 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 831 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 832 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 833 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 834 835 if (should_use_dto_dscclk) 836 dccg->funcs->set_dto_dscclk(dccg, dsc->inst); 837 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 838 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); 839 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 840 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; 841 842 if (should_use_dto_dscclk) 843 dccg->funcs->set_dto_dscclk(dccg, odm_dsc->inst); 844 odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg); 845 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); 846 } 847 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; 848 dsc_cfg.pic_width *= opp_cnt; 849 850 optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; 851 852 /* Enable DSC in encoder */ 853 if (dc_is_dp_signal(stream->signal) && !dp_is_128b_132b_signal(pipe_ctx)) { 854 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); 855 dsc_optc_config_log(dsc, &dsc_optc_cfg); 856 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 857 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, 858 optc_dsc_mode, 859 dsc_optc_cfg.bytes_per_pixel, 860 dsc_optc_cfg.slice_width); 861 862 /* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */ 863 } 864 865 /* Enable DSC in OPTC */ 866 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); 867 dsc_optc_config_log(dsc, &dsc_optc_cfg); 868 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, 869 optc_dsc_mode, 870 dsc_optc_cfg.bytes_per_pixel, 871 dsc_optc_cfg.slice_width); 872 } else { 873 /* disable DSC in OPTC */ 874 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 875 pipe_ctx->stream_res.tg, 876 OPTC_DSC_DISABLED, 0, 0); 877 878 /* disable DSC in stream encoder */ 879 if (dc_is_dp_signal(stream->signal)) { 880 if (dp_is_128b_132b_signal(pipe_ctx)) 881 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 882 pipe_ctx->stream_res.hpo_dp_stream_enc, 883 false, 884 NULL, 885 true); 886 else { 887 if (pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config) 888 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config( 889 pipe_ctx->stream_res.stream_enc, 890 OPTC_DSC_DISABLED, 0, 0); 891 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 892 pipe_ctx->stream_res.stream_enc, false, NULL, true); 893 } 894 } 895 896 /* disable DSC block */ 897 for (odm_pipe = pipe_ctx; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 898 odm_pipe->stream_res.dsc->funcs->dsc_disconnect(odm_pipe->stream_res.dsc); 899 /* 900 * TODO - dsc_disconnect is a double buffered register. 901 * by the time we call dsc_disable, dsc may still remain 902 * connected to OPP. In this case OPTC will no longer 903 * get correct pixel data because DSCC is off. However 904 * we also can't wait for the disconnect pending 905 * complete, because this function can be called 906 * with/without OTG master lock acquired. When the lock 907 * is acquired we will never get pending complete until 908 * we release the lock later. So there is no easy way to 909 * solve this problem especially when the lock is 910 * acquired. DSC is a front end hw block it should be 911 * programmed as part of front end sequence, where the 912 * commit sequence without lock and update sequence 913 * with lock are completely separated. However because 914 * we are programming dsc as part of back end link 915 * programming sequence, we don't know if front end OPTC 916 * master lock is acquired. The back end should be 917 * agnostic to front end lock. DSC programming shouldn't 918 * belong to this sequence. 919 */ 920 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); 921 if (dccg->funcs->set_ref_dscclk) 922 dccg->funcs->set_ref_dscclk(dccg, odm_pipe->stream_res.dsc->inst); 923 } 924 } 925 } 926 927 /* 928 * For dynamic bpp change case, dsc is programmed with MASTER_UPDATE_LOCK enabled; 929 * hence PPS info packet update need to use frame update instead of immediate update. 930 * Added parameter immediate_update for this purpose. 931 * The decision to use frame update is hard-coded in function dp_update_dsc_config(), 932 * which is the only place where a "false" would be passed in for param immediate_update. 933 * 934 * immediate_update is only applicable when DSC is enabled. 935 */ 936 bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update) 937 { 938 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 939 struct dc_stream_state *stream = pipe_ctx->stream; 940 941 if (!pipe_ctx->stream->timing.flags.DSC) 942 return false; 943 944 if (!dsc) 945 return false; 946 947 DC_LOGGER_INIT(dsc->ctx->logger); 948 949 if (enable) { 950 struct dsc_config dsc_cfg; 951 uint8_t dsc_packed_pps[128]; 952 953 memset(&dsc_cfg, 0, sizeof(dsc_cfg)); 954 memset(dsc_packed_pps, 0, 128); 955 956 /* Enable DSC hw block */ 957 dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; 958 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; 959 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 960 dsc_cfg.color_depth = stream->timing.display_color_depth; 961 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 962 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 963 964 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]); 965 memcpy(&stream->dsc_packed_pps[0], &dsc_packed_pps[0], sizeof(stream->dsc_packed_pps)); 966 if (dc_is_dp_signal(stream->signal)) { 967 DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id); 968 if (dp_is_128b_132b_signal(pipe_ctx)) 969 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 970 pipe_ctx->stream_res.hpo_dp_stream_enc, 971 true, 972 &dsc_packed_pps[0], 973 immediate_update); 974 else 975 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 976 pipe_ctx->stream_res.stream_enc, 977 true, 978 &dsc_packed_pps[0], 979 immediate_update); 980 } 981 } else { 982 /* disable DSC PPS in stream encoder */ 983 memset(&stream->dsc_packed_pps[0], 0, sizeof(stream->dsc_packed_pps)); 984 if (dc_is_dp_signal(stream->signal)) { 985 if (dp_is_128b_132b_signal(pipe_ctx)) 986 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_set_dsc_pps_info_packet( 987 pipe_ctx->stream_res.hpo_dp_stream_enc, 988 false, 989 NULL, 990 true); 991 else 992 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet( 993 pipe_ctx->stream_res.stream_enc, false, NULL, true); 994 } 995 } 996 997 return true; 998 } 999 1000 bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 1001 { 1002 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1003 bool result = false; 1004 1005 if (!pipe_ctx->stream->timing.flags.DSC) 1006 goto out; 1007 if (!dsc) 1008 goto out; 1009 1010 if (enable) { 1011 { 1012 link_set_dsc_on_stream(pipe_ctx, true); 1013 result = true; 1014 } 1015 } else { 1016 dp_set_dsc_on_rx(pipe_ctx, false); 1017 link_set_dsc_on_stream(pipe_ctx, false); 1018 result = true; 1019 } 1020 out: 1021 return result; 1022 } 1023 1024 bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) 1025 { 1026 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; 1027 1028 if (!pipe_ctx->stream->timing.flags.DSC) 1029 return false; 1030 if (!dsc) 1031 return false; 1032 1033 link_set_dsc_on_stream(pipe_ctx, true); 1034 link_set_dsc_pps_packet(pipe_ctx, true, false); 1035 return true; 1036 } 1037 1038 static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1039 { 1040 struct dc_stream_state *stream = pipe_ctx->stream; 1041 1042 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) { 1043 struct dc_link *link = stream->link; 1044 union down_spread_ctrl old_downspread; 1045 union down_spread_ctrl new_downspread; 1046 1047 memset(&old_downspread, 0, sizeof(old_downspread)); 1048 1049 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1050 &old_downspread.raw, sizeof(old_downspread)); 1051 1052 new_downspread.raw = old_downspread.raw; 1053 1054 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1055 (stream->ignore_msa_timing_param) ? 1 : 0; 1056 1057 if (new_downspread.raw != old_downspread.raw) { 1058 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1059 &new_downspread.raw, sizeof(new_downspread)); 1060 } 1061 1062 } else { 1063 dm_helpers_mst_enable_stream_features(stream); 1064 } 1065 } 1066 1067 static void log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp) 1068 { 1069 const uint32_t VCP_Y_PRECISION = 1000; 1070 uint64_t vcp_x, vcp_y; 1071 DC_LOGGER_INIT(link->ctx->logger); 1072 1073 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision 1074 avg_time_slots_per_mtp = dc_fixpt_add( 1075 avg_time_slots_per_mtp, 1076 dc_fixpt_from_fraction( 1077 1, 1078 2*VCP_Y_PRECISION)); 1079 1080 vcp_x = dc_fixpt_floor( 1081 avg_time_slots_per_mtp); 1082 vcp_y = dc_fixpt_floor( 1083 dc_fixpt_mul_int( 1084 dc_fixpt_sub_int( 1085 avg_time_slots_per_mtp, 1086 dc_fixpt_floor( 1087 avg_time_slots_per_mtp)), 1088 VCP_Y_PRECISION)); 1089 1090 1091 if (link->type == dc_connection_mst_branch) 1092 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream " 1093 "X: %llu " 1094 "Y: %llu/%d", 1095 vcp_x, 1096 vcp_y, 1097 VCP_Y_PRECISION); 1098 else 1099 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream " 1100 "X: %llu " 1101 "Y: %llu/%d", 1102 vcp_x, 1103 vcp_y, 1104 VCP_Y_PRECISION); 1105 } 1106 1107 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 1108 { 1109 struct fixed31_32 mbytes_per_sec; 1110 uint32_t link_rate_in_mbytes_per_sec = dp_link_bandwidth_kbps(stream->link, 1111 &stream->link->cur_link_settings); 1112 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 1113 1114 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 1115 1116 return dc_fixpt_div_int(mbytes_per_sec, 54); 1117 } 1118 1119 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps) 1120 { 1121 struct fixed31_32 peak_kbps; 1122 uint32_t numerator = 0; 1123 uint32_t denominator = 1; 1124 1125 /* 1126 * The 1.006 factor (margin 5300ppm + 300ppm ~ 0.6% as per spec) is not 1127 * required when determining PBN/time slot utilization on the link between 1128 * us and the branch, since that overhead is already accounted for in 1129 * the get_pbn_per_slot function. 1130 * 1131 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 1132 * common multiplier to render an integer PBN for all link rate/lane 1133 * counts combinations 1134 * calculate 1135 * peak_kbps *= (64/54) 1136 * peak_kbps /= (8 * 1000) convert to bytes 1137 */ 1138 1139 numerator = 64; 1140 denominator = 54 * 8 * 1000; 1141 kbps *= numerator; 1142 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 1143 1144 return peak_kbps; 1145 } 1146 1147 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 1148 { 1149 uint64_t kbps; 1150 enum dc_link_encoding_format link_encoding; 1151 1152 if (dp_is_128b_132b_signal(pipe_ctx)) 1153 link_encoding = DC_LINK_ENCODING_DP_128b_132b; 1154 else 1155 link_encoding = DC_LINK_ENCODING_DP_8b_10b; 1156 1157 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing, link_encoding); 1158 return get_pbn_from_bw_in_kbps(kbps); 1159 } 1160 1161 1162 // TODO - DP2.0 Link: Fix get_lane_status to handle LTTPR offset (SST and MST) 1163 static void get_lane_status( 1164 struct dc_link *link, 1165 uint32_t lane_count, 1166 union lane_status *status, 1167 union lane_align_status_updated *status_updated) 1168 { 1169 unsigned int lane; 1170 uint8_t dpcd_buf[3] = {0}; 1171 1172 if (status == NULL || status_updated == NULL) { 1173 return; 1174 } 1175 1176 core_link_read_dpcd( 1177 link, 1178 DP_LANE0_1_STATUS, 1179 dpcd_buf, 1180 sizeof(dpcd_buf)); 1181 1182 for (lane = 0; lane < lane_count; lane++) { 1183 status[lane].raw = dp_get_nibble_at_index(&dpcd_buf[0], lane); 1184 } 1185 1186 status_updated->raw = dpcd_buf[2]; 1187 } 1188 1189 static bool poll_for_allocation_change_trigger(struct dc_link *link) 1190 { 1191 /* 1192 * wait for ACT handled 1193 */ 1194 int i; 1195 const int act_retries = 30; 1196 enum act_return_status result = ACT_FAILED; 1197 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1198 union payload_table_update_status update_status = {0}; 1199 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; 1200 union lane_align_status_updated lane_status_updated; 1201 DC_LOGGER_INIT(link->ctx->logger); 1202 1203 if (!display_connected || link->aux_access_disabled) 1204 return true; 1205 for (i = 0; i < act_retries; i++) { 1206 get_lane_status(link, link->cur_link_settings.lane_count, dpcd_lane_status, &lane_status_updated); 1207 1208 if (!dp_is_cr_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1209 !dp_is_ch_eq_done(link->cur_link_settings.lane_count, dpcd_lane_status) || 1210 !dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) || 1211 !dp_is_interlane_aligned(lane_status_updated)) { 1212 DC_LOG_ERROR("SST Update Payload: Link loss occurred while " 1213 "polling for ACT handled."); 1214 result = ACT_LINK_LOST; 1215 break; 1216 } 1217 core_link_read_dpcd( 1218 link, 1219 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1220 &update_status.raw, 1221 1); 1222 1223 if (update_status.bits.ACT_HANDLED == 1) { 1224 DC_LOG_DP2("SST Update Payload: ACT handled by downstream."); 1225 result = ACT_SUCCESS; 1226 break; 1227 } 1228 1229 fsleep(5000); 1230 } 1231 1232 if (result == ACT_FAILED) { 1233 DC_LOG_ERROR("SST Update Payload: ACT still not handled after retries, " 1234 "continue on. Something is wrong with the branch."); 1235 } 1236 1237 return (result == ACT_SUCCESS); 1238 } 1239 1240 static void update_mst_stream_alloc_table( 1241 struct dc_link *link, 1242 struct stream_encoder *stream_enc, 1243 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc? 1244 const struct dc_dp_mst_stream_allocation_table *proposed_table) 1245 { 1246 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 }; 1247 struct link_mst_stream_allocation *dc_alloc; 1248 1249 int i; 1250 int j; 1251 1252 /* if DRM proposed_table has more than one new payload */ 1253 ASSERT(proposed_table->stream_count - 1254 link->mst_stream_alloc_table.stream_count < 2); 1255 1256 /* copy proposed_table to link, add stream encoder */ 1257 for (i = 0; i < proposed_table->stream_count; i++) { 1258 1259 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 1260 dc_alloc = 1261 &link->mst_stream_alloc_table.stream_allocations[j]; 1262 1263 if (dc_alloc->vcp_id == 1264 proposed_table->stream_allocations[i].vcp_id) { 1265 1266 work_table[i] = *dc_alloc; 1267 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count; 1268 break; /* exit j loop */ 1269 } 1270 } 1271 1272 /* new vcp_id */ 1273 if (j == link->mst_stream_alloc_table.stream_count) { 1274 work_table[i].vcp_id = 1275 proposed_table->stream_allocations[i].vcp_id; 1276 work_table[i].slot_count = 1277 proposed_table->stream_allocations[i].slot_count; 1278 work_table[i].stream_enc = stream_enc; 1279 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc; 1280 } 1281 } 1282 1283 /* update link->mst_stream_alloc_table with work_table */ 1284 link->mst_stream_alloc_table.stream_count = 1285 proposed_table->stream_count; 1286 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 1287 link->mst_stream_alloc_table.stream_allocations[i] = 1288 work_table[i]; 1289 } 1290 1291 static void remove_stream_from_alloc_table( 1292 struct dc_link *link, 1293 struct stream_encoder *dio_stream_enc, 1294 struct hpo_dp_stream_encoder *hpo_dp_stream_enc) 1295 { 1296 int i = 0; 1297 struct link_mst_stream_allocation_table *table = 1298 &link->mst_stream_alloc_table; 1299 1300 if (hpo_dp_stream_enc) { 1301 for (; i < table->stream_count; i++) 1302 if (hpo_dp_stream_enc == table->stream_allocations[i].hpo_dp_stream_enc) 1303 break; 1304 } else { 1305 for (; i < table->stream_count; i++) 1306 if (dio_stream_enc == table->stream_allocations[i].stream_enc) 1307 break; 1308 } 1309 1310 if (i < table->stream_count) { 1311 i++; 1312 for (; i < table->stream_count; i++) 1313 table->stream_allocations[i-1] = table->stream_allocations[i]; 1314 memset(&table->stream_allocations[table->stream_count-1], 0, 1315 sizeof(struct link_mst_stream_allocation)); 1316 table->stream_count--; 1317 } 1318 } 1319 1320 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 1321 { 1322 struct dc_stream_state *stream = pipe_ctx->stream; 1323 struct dc_link *link = stream->link; 1324 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1325 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1326 int i; 1327 bool mst_mode = (link->type == dc_connection_mst_branch); 1328 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1329 const struct dc_link_settings empty_link_settings = {0}; 1330 DC_LOGGER_INIT(link->ctx->logger); 1331 1332 /* deallocate_mst_payload is called before disable link. When mode or 1333 * disable/enable monitor, new stream is created which is not in link 1334 * stream[] yet. For this, payload is not allocated yet, so de-alloc 1335 * should not done. For new mode set, map_resources will get engine 1336 * for new stream, so stream_enc->id should be validated until here. 1337 */ 1338 1339 /* slot X.Y */ 1340 if (link_hwss->ext.set_throttled_vcp_size) 1341 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1342 if (link_hwss->ext.set_hblank_min_symbol_width) 1343 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1344 &empty_link_settings, 1345 avg_time_slots_per_mtp); 1346 1347 if (mst_mode) { 1348 /* when link is in mst mode, reply on mst manager to remove 1349 * payload 1350 */ 1351 if (dm_helpers_dp_mst_write_payload_allocation_table( 1352 stream->ctx, 1353 stream, 1354 &proposed_table, 1355 false)) 1356 update_mst_stream_alloc_table( 1357 link, 1358 pipe_ctx->stream_res.stream_enc, 1359 pipe_ctx->stream_res.hpo_dp_stream_enc, 1360 &proposed_table); 1361 else 1362 DC_LOG_WARNING("Failed to update" 1363 "MST allocation table for" 1364 "pipe idx:%d\n", 1365 pipe_ctx->pipe_idx); 1366 } else { 1367 /* when link is no longer in mst mode (mst hub unplugged), 1368 * remove payload with default dc logic 1369 */ 1370 remove_stream_from_alloc_table(link, pipe_ctx->stream_res.stream_enc, 1371 pipe_ctx->stream_res.hpo_dp_stream_enc); 1372 } 1373 1374 DC_LOG_MST("%s" 1375 "stream_count: %d: ", 1376 __func__, 1377 link->mst_stream_alloc_table.stream_count); 1378 1379 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1380 DC_LOG_MST("stream_enc[%d]: %p " 1381 "stream[%d].hpo_dp_stream_enc: %p " 1382 "stream[%d].vcp_id: %d " 1383 "stream[%d].slot_count: %d\n", 1384 i, 1385 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1386 i, 1387 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1388 i, 1389 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1390 i, 1391 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1392 } 1393 1394 /* update mst stream allocation table hardware state */ 1395 if (link_hwss->ext.update_stream_allocation_table == NULL || 1396 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1397 DC_LOG_DEBUG("Unknown encoding format\n"); 1398 return DC_ERROR_UNEXPECTED; 1399 } 1400 1401 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1402 &link->mst_stream_alloc_table); 1403 1404 if (mst_mode) 1405 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1406 stream->ctx, 1407 stream); 1408 1409 dm_helpers_dp_mst_update_mst_mgr_for_deallocation( 1410 stream->ctx, 1411 stream); 1412 1413 return DC_OK; 1414 } 1415 1416 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 1417 * because stream_encoder is not exposed to dm 1418 */ 1419 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 1420 { 1421 struct dc_stream_state *stream = pipe_ctx->stream; 1422 struct dc_link *link = stream->link; 1423 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1424 struct fixed31_32 avg_time_slots_per_mtp; 1425 struct fixed31_32 pbn; 1426 struct fixed31_32 pbn_per_slot; 1427 int i; 1428 enum act_return_status ret; 1429 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1430 DC_LOGGER_INIT(link->ctx->logger); 1431 1432 /* enable_link_dp_mst already check link->enabled_stream_count 1433 * and stream is in link->stream[]. This is called during set mode, 1434 * stream_enc is available. 1435 */ 1436 1437 /* get calculate VC payload for stream: stream_alloc */ 1438 if (dm_helpers_dp_mst_write_payload_allocation_table( 1439 stream->ctx, 1440 stream, 1441 &proposed_table, 1442 true)) 1443 update_mst_stream_alloc_table( 1444 link, 1445 pipe_ctx->stream_res.stream_enc, 1446 pipe_ctx->stream_res.hpo_dp_stream_enc, 1447 &proposed_table); 1448 else 1449 DC_LOG_WARNING("Failed to update" 1450 "MST allocation table for" 1451 "pipe idx:%d\n", 1452 pipe_ctx->pipe_idx); 1453 1454 DC_LOG_MST("%s " 1455 "stream_count: %d: \n ", 1456 __func__, 1457 link->mst_stream_alloc_table.stream_count); 1458 1459 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1460 DC_LOG_MST("stream_enc[%d]: %p " 1461 "stream[%d].hpo_dp_stream_enc: %p " 1462 "stream[%d].vcp_id: %d " 1463 "stream[%d].slot_count: %d\n", 1464 i, 1465 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1466 i, 1467 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1468 i, 1469 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1470 i, 1471 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1472 } 1473 1474 ASSERT(proposed_table.stream_count > 0); 1475 1476 /* program DP source TX for payload */ 1477 if (link_hwss->ext.update_stream_allocation_table == NULL || 1478 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1479 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1480 return DC_ERROR_UNEXPECTED; 1481 } 1482 1483 link_hwss->ext.update_stream_allocation_table(link, 1484 &pipe_ctx->link_res, 1485 &link->mst_stream_alloc_table); 1486 1487 /* send down message */ 1488 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1489 stream->ctx, 1490 stream); 1491 1492 if (ret != ACT_LINK_LOST) 1493 dm_helpers_dp_mst_send_payload_allocation( 1494 stream->ctx, 1495 stream); 1496 1497 /* slot X.Y for only current stream */ 1498 pbn_per_slot = get_pbn_per_slot(stream); 1499 if (pbn_per_slot.value == 0) { 1500 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n"); 1501 return DC_UNSUPPORTED_VALUE; 1502 } 1503 pbn = get_pbn_from_timing(pipe_ctx); 1504 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1505 1506 log_vcp_x_y(link, avg_time_slots_per_mtp); 1507 1508 if (link_hwss->ext.set_throttled_vcp_size) 1509 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1510 if (link_hwss->ext.set_hblank_min_symbol_width) 1511 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1512 &link->cur_link_settings, 1513 avg_time_slots_per_mtp); 1514 1515 return DC_OK; 1516 } 1517 1518 struct fixed31_32 link_calculate_sst_avg_time_slots_per_mtp( 1519 const struct dc_stream_state *stream, 1520 const struct dc_link *link) 1521 { 1522 struct fixed31_32 link_bw_effective = 1523 dc_fixpt_from_int( 1524 dp_link_bandwidth_kbps(link, &link->cur_link_settings)); 1525 struct fixed31_32 timeslot_bw_effective = 1526 dc_fixpt_div_int(link_bw_effective, MAX_MTP_SLOT_COUNT); 1527 struct fixed31_32 timing_bw = 1528 dc_fixpt_from_int( 1529 dc_bandwidth_in_kbps_from_timing(&stream->timing, 1530 dc_link_get_highest_encoding_format(link))); 1531 struct fixed31_32 avg_time_slots_per_mtp = 1532 dc_fixpt_div(timing_bw, timeslot_bw_effective); 1533 1534 return avg_time_slots_per_mtp; 1535 } 1536 1537 1538 static bool write_128b_132b_sst_payload_allocation_table( 1539 const struct dc_stream_state *stream, 1540 struct dc_link *link, 1541 struct link_mst_stream_allocation_table *proposed_table, 1542 bool allocate) 1543 { 1544 const uint8_t vc_id = 1; /// VC ID always 1 for SST 1545 const uint8_t start_time_slot = 0; /// Always start at time slot 0 for SST 1546 bool result = false; 1547 uint8_t req_slot_count = 0; 1548 struct fixed31_32 avg_time_slots_per_mtp = { 0 }; 1549 union payload_table_update_status update_status = { 0 }; 1550 const uint32_t max_retries = 30; 1551 uint32_t retries = 0; 1552 enum dc_connection_type display_connected = (link->type != dc_connection_none); 1553 DC_LOGGER_INIT(link->ctx->logger); 1554 1555 if (allocate) { 1556 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1557 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp); 1558 /// Validation should filter out modes that exceed link BW 1559 ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT); 1560 if (req_slot_count > MAX_MTP_SLOT_COUNT) 1561 return false; 1562 } else { 1563 /// Leave req_slot_count = 0 if allocate is false. 1564 } 1565 1566 proposed_table->stream_count = 1; /// Always 1 stream for SST 1567 proposed_table->stream_allocations[0].slot_count = req_slot_count; 1568 proposed_table->stream_allocations[0].vcp_id = vc_id; 1569 1570 if (!display_connected || link->aux_access_disabled) 1571 return true; 1572 1573 /// Write DPCD 2C0 = 1 to start updating 1574 update_status.bits.VC_PAYLOAD_TABLE_UPDATED = 1; 1575 core_link_write_dpcd( 1576 link, 1577 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1578 &update_status.raw, 1579 1); 1580 1581 /// Program the changes in DPCD 1C0 - 1C2 1582 ASSERT(vc_id == 1); 1583 core_link_write_dpcd( 1584 link, 1585 DP_PAYLOAD_ALLOCATE_SET, 1586 &vc_id, 1587 1); 1588 1589 ASSERT(start_time_slot == 0); 1590 core_link_write_dpcd( 1591 link, 1592 DP_PAYLOAD_ALLOCATE_START_TIME_SLOT, 1593 &start_time_slot, 1594 1); 1595 1596 core_link_write_dpcd( 1597 link, 1598 DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT, 1599 &req_slot_count, 1600 1); 1601 1602 /// Poll till DPCD 2C0 read 1 1603 /// Try for at least 150ms (30 retries, with 5ms delay after each attempt) 1604 1605 while (retries < max_retries) { 1606 if (core_link_read_dpcd( 1607 link, 1608 DP_PAYLOAD_TABLE_UPDATE_STATUS, 1609 &update_status.raw, 1610 1) == DC_OK) { 1611 if (update_status.bits.VC_PAYLOAD_TABLE_UPDATED == 1) { 1612 DC_LOG_DP2("SST Update Payload: downstream payload table updated."); 1613 result = true; 1614 break; 1615 } 1616 } else { 1617 union dpcd_rev dpcdRev = {0}; 1618 1619 if (core_link_read_dpcd( 1620 link, 1621 DP_DPCD_REV, 1622 &dpcdRev.raw, 1623 1) != DC_OK) { 1624 DC_LOG_ERROR("SST Update Payload: Unable to read DPCD revision " 1625 "of sink while polling payload table " 1626 "updated status bit."); 1627 break; 1628 } 1629 } 1630 retries++; 1631 fsleep(5000); 1632 } 1633 1634 if (!result && retries == max_retries) { 1635 DC_LOG_ERROR("SST Update Payload: Payload table not updated after retries, " 1636 "continue on. Something is wrong with the branch."); 1637 // TODO - DP2.0 Payload: Read and log the payload table from downstream branch 1638 } 1639 1640 return result; 1641 } 1642 1643 /* 1644 * Payload allocation/deallocation for SST introduced in DP2.0 1645 */ 1646 static enum dc_status update_sst_payload(struct pipe_ctx *pipe_ctx, 1647 bool allocate) 1648 { 1649 struct dc_stream_state *stream = pipe_ctx->stream; 1650 struct dc_link *link = stream->link; 1651 struct link_mst_stream_allocation_table proposed_table = {0}; 1652 struct fixed31_32 avg_time_slots_per_mtp; 1653 const struct dc_link_settings empty_link_settings = {0}; 1654 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1655 DC_LOGGER_INIT(link->ctx->logger); 1656 1657 /* slot X.Y for SST payload deallocate */ 1658 if (!allocate) { 1659 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 1660 1661 log_vcp_x_y(link, avg_time_slots_per_mtp); 1662 1663 if (link_hwss->ext.set_throttled_vcp_size) 1664 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1665 avg_time_slots_per_mtp); 1666 if (link_hwss->ext.set_hblank_min_symbol_width) 1667 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1668 &empty_link_settings, 1669 avg_time_slots_per_mtp); 1670 } 1671 1672 /* calculate VC payload and update branch with new payload allocation table*/ 1673 if (!write_128b_132b_sst_payload_allocation_table( 1674 stream, 1675 link, 1676 &proposed_table, 1677 allocate)) { 1678 DC_LOG_ERROR("SST Update Payload: Failed to update " 1679 "allocation table for " 1680 "pipe idx: %d\n", 1681 pipe_ctx->pipe_idx); 1682 return DC_FAIL_DP_PAYLOAD_ALLOCATION; 1683 } 1684 1685 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; 1686 1687 ASSERT(proposed_table.stream_count == 1); 1688 1689 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id 1690 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p " 1691 "vcp_id: %d " 1692 "slot_count: %d\n", 1693 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc, 1694 proposed_table.stream_allocations[0].vcp_id, 1695 proposed_table.stream_allocations[0].slot_count); 1696 1697 /* program DP source TX for payload */ 1698 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1699 &proposed_table); 1700 1701 /* poll for ACT handled */ 1702 if (!poll_for_allocation_change_trigger(link)) { 1703 // Failures will result in blackscreen and errors logged 1704 BREAK_TO_DEBUGGER(); 1705 } 1706 1707 /* slot X.Y for SST payload allocate */ 1708 if (allocate && link_dp_get_encoding_format(&link->cur_link_settings) == 1709 DP_128b_132b_ENCODING) { 1710 avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link); 1711 1712 log_vcp_x_y(link, avg_time_slots_per_mtp); 1713 1714 if (link_hwss->ext.set_throttled_vcp_size) 1715 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, 1716 avg_time_slots_per_mtp); 1717 if (link_hwss->ext.set_hblank_min_symbol_width) 1718 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1719 &link->cur_link_settings, 1720 avg_time_slots_per_mtp); 1721 } 1722 1723 /* Always return DC_OK. 1724 * If part of sequence fails, log failure(s) and show blackscreen 1725 */ 1726 return DC_OK; 1727 } 1728 1729 enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1730 { 1731 struct dc_stream_state *stream = pipe_ctx->stream; 1732 struct dc_link *link = stream->link; 1733 struct fixed31_32 avg_time_slots_per_mtp; 1734 struct fixed31_32 pbn; 1735 struct fixed31_32 pbn_per_slot; 1736 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1737 uint8_t i; 1738 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1739 DC_LOGGER_INIT(link->ctx->logger); 1740 1741 /* decrease throttled vcp size */ 1742 pbn_per_slot = get_pbn_per_slot(stream); 1743 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1744 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1745 1746 if (link_hwss->ext.set_throttled_vcp_size) 1747 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1748 if (link_hwss->ext.set_hblank_min_symbol_width) 1749 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1750 &link->cur_link_settings, 1751 avg_time_slots_per_mtp); 1752 1753 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1754 dm_helpers_dp_mst_send_payload_allocation( 1755 stream->ctx, 1756 stream); 1757 1758 /* notify immediate branch device table update */ 1759 if (dm_helpers_dp_mst_write_payload_allocation_table( 1760 stream->ctx, 1761 stream, 1762 &proposed_table, 1763 true)) { 1764 /* update mst stream allocation table software state */ 1765 update_mst_stream_alloc_table( 1766 link, 1767 pipe_ctx->stream_res.stream_enc, 1768 pipe_ctx->stream_res.hpo_dp_stream_enc, 1769 &proposed_table); 1770 } else { 1771 DC_LOG_WARNING("Failed to update" 1772 "MST allocation table for" 1773 "pipe idx:%d\n", 1774 pipe_ctx->pipe_idx); 1775 } 1776 1777 DC_LOG_MST("%s " 1778 "stream_count: %d: \n ", 1779 __func__, 1780 link->mst_stream_alloc_table.stream_count); 1781 1782 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1783 DC_LOG_MST("stream_enc[%d]: %p " 1784 "stream[%d].hpo_dp_stream_enc: %p " 1785 "stream[%d].vcp_id: %d " 1786 "stream[%d].slot_count: %d\n", 1787 i, 1788 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1789 i, 1790 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1791 i, 1792 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1793 i, 1794 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1795 } 1796 1797 ASSERT(proposed_table.stream_count > 0); 1798 1799 /* update mst stream allocation table hardware state */ 1800 if (link_hwss->ext.update_stream_allocation_table == NULL || 1801 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1802 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1803 return DC_ERROR_UNEXPECTED; 1804 } 1805 1806 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1807 &link->mst_stream_alloc_table); 1808 1809 /* poll for immediate branch device ACT handled */ 1810 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1811 stream->ctx, 1812 stream); 1813 1814 return DC_OK; 1815 } 1816 1817 enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps) 1818 { 1819 struct dc_stream_state *stream = pipe_ctx->stream; 1820 struct dc_link *link = stream->link; 1821 struct fixed31_32 avg_time_slots_per_mtp; 1822 struct fixed31_32 pbn; 1823 struct fixed31_32 pbn_per_slot; 1824 struct dc_dp_mst_stream_allocation_table proposed_table = {0}; 1825 uint8_t i; 1826 enum act_return_status ret; 1827 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1828 DC_LOGGER_INIT(link->ctx->logger); 1829 1830 /* notify immediate branch device table update */ 1831 if (dm_helpers_dp_mst_write_payload_allocation_table( 1832 stream->ctx, 1833 stream, 1834 &proposed_table, 1835 true)) { 1836 /* update mst stream allocation table software state */ 1837 update_mst_stream_alloc_table( 1838 link, 1839 pipe_ctx->stream_res.stream_enc, 1840 pipe_ctx->stream_res.hpo_dp_stream_enc, 1841 &proposed_table); 1842 } 1843 1844 DC_LOG_MST("%s " 1845 "stream_count: %d: \n ", 1846 __func__, 1847 link->mst_stream_alloc_table.stream_count); 1848 1849 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 1850 DC_LOG_MST("stream_enc[%d]: %p " 1851 "stream[%d].hpo_dp_stream_enc: %p " 1852 "stream[%d].vcp_id: %d " 1853 "stream[%d].slot_count: %d\n", 1854 i, 1855 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 1856 i, 1857 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, 1858 i, 1859 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 1860 i, 1861 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 1862 } 1863 1864 ASSERT(proposed_table.stream_count > 0); 1865 1866 /* update mst stream allocation table hardware state */ 1867 if (link_hwss->ext.update_stream_allocation_table == NULL || 1868 link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { 1869 DC_LOG_ERROR("Failure: unknown encoding format\n"); 1870 return DC_ERROR_UNEXPECTED; 1871 } 1872 1873 link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, 1874 &link->mst_stream_alloc_table); 1875 1876 /* poll for immediate branch device ACT handled */ 1877 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 1878 stream->ctx, 1879 stream); 1880 1881 if (ret != ACT_LINK_LOST) { 1882 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */ 1883 dm_helpers_dp_mst_send_payload_allocation( 1884 stream->ctx, 1885 stream); 1886 } 1887 1888 /* increase throttled vcp size */ 1889 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps); 1890 pbn_per_slot = get_pbn_per_slot(stream); 1891 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 1892 1893 if (link_hwss->ext.set_throttled_vcp_size) 1894 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); 1895 if (link_hwss->ext.set_hblank_min_symbol_width) 1896 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, 1897 &link->cur_link_settings, 1898 avg_time_slots_per_mtp); 1899 1900 return DC_OK; 1901 } 1902 1903 static void disable_link_dp(struct dc_link *link, 1904 const struct link_resource *link_res, 1905 enum signal_type signal) 1906 { 1907 struct dc_link_settings link_settings = link->cur_link_settings; 1908 1909 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && 1910 link->mst_stream_alloc_table.stream_count > 0) 1911 /* disable MST link only when last vc payload is deallocated */ 1912 return; 1913 1914 dp_disable_link_phy(link, link_res, signal); 1915 1916 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1917 if (!link->skip_implict_edp_power_control) 1918 link->dc->hwss.edp_power_control(link, false); 1919 } 1920 1921 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 1922 /* set the sink to SST mode after disabling the link */ 1923 enable_mst_on_sink(link, false); 1924 1925 if (link_dp_get_encoding_format(&link_settings) == 1926 DP_8b_10b_ENCODING) { 1927 dp_set_fec_enable(link, link_res, false); 1928 dp_set_fec_ready(link, link_res, false); 1929 } 1930 } 1931 1932 static void disable_link(struct dc_link *link, 1933 const struct link_resource *link_res, 1934 enum signal_type signal) 1935 { 1936 if (dc_is_dp_signal(signal)) { 1937 disable_link_dp(link, link_res, signal); 1938 } else if (signal == SIGNAL_TYPE_VIRTUAL) { 1939 link->dc->hwss.disable_link_output(link, link_res, SIGNAL_TYPE_DISPLAY_PORT); 1940 } else { 1941 link->dc->hwss.disable_link_output(link, link_res, signal); 1942 } 1943 1944 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 1945 /* MST disable link only when no stream use the link */ 1946 if (link->mst_stream_alloc_table.stream_count <= 0) 1947 link->link_status.link_active = false; 1948 } else { 1949 link->link_status.link_active = false; 1950 } 1951 } 1952 1953 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 1954 { 1955 struct dc_stream_state *stream = pipe_ctx->stream; 1956 struct dc_link *link = stream->link; 1957 enum dc_color_depth display_color_depth; 1958 enum engine_id eng_id; 1959 struct ext_hdmi_settings settings = {0}; 1960 bool is_over_340mhz = false; 1961 bool is_vga_mode = (stream->timing.h_addressable == 640) 1962 && (stream->timing.v_addressable == 480); 1963 struct dc *dc = pipe_ctx->stream->ctx->dc; 1964 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1965 1966 if (stream->phy_pix_clk == 0) 1967 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 1968 if (stream->phy_pix_clk > 340000) 1969 is_over_340mhz = true; 1970 if (dc_is_tmds_signal(stream->signal) && stream->phy_pix_clk > 6000000UL) { 1971 ASSERT(false); 1972 return; 1973 } 1974 1975 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 1976 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 1977 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 1978 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 1979 /* DP159, Retimer settings */ 1980 eng_id = pipe_ctx->stream_res.stream_enc->id; 1981 1982 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 1983 write_i2c_retimer_setting(pipe_ctx, 1984 is_vga_mode, is_over_340mhz, &settings); 1985 } else { 1986 write_i2c_default_retimer_setting(pipe_ctx, 1987 is_vga_mode, is_over_340mhz); 1988 } 1989 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 1990 /* PI3EQX1204, Redriver settings */ 1991 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 1992 } 1993 } 1994 1995 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 1996 write_scdc_data( 1997 stream->link->ddc, 1998 stream->phy_pix_clk, 1999 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2000 2001 memset(&stream->link->cur_link_settings, 0, 2002 sizeof(struct dc_link_settings)); 2003 2004 display_color_depth = stream->timing.display_color_depth; 2005 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2006 display_color_depth = COLOR_DEPTH_888; 2007 2008 /* We need to enable stream encoder for TMDS first to apply 1/4 TMDS 2009 * character clock in case that beyond 340MHz. 2010 */ 2011 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) || dc_is_dvi_signal(pipe_ctx->stream->signal)) 2012 link_hwss->setup_stream_encoder(pipe_ctx); 2013 2014 dc->hwss.enable_tmds_link_output( 2015 link, 2016 &pipe_ctx->link_res, 2017 pipe_ctx->stream->signal, 2018 pipe_ctx->clock_source->id, 2019 display_color_depth, 2020 stream->phy_pix_clk); 2021 2022 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2023 read_scdc_data(link->ddc); 2024 } 2025 2026 static enum dc_status enable_link_dp(struct dc_state *state, 2027 struct pipe_ctx *pipe_ctx) 2028 { 2029 struct dc_stream_state *stream = pipe_ctx->stream; 2030 enum dc_status status; 2031 bool skip_video_pattern; 2032 struct dc_link *link = stream->link; 2033 const struct dc_link_settings *link_settings = 2034 &pipe_ctx->link_config.dp_link_settings; 2035 bool fec_enable; 2036 int i; 2037 bool apply_seamless_boot_optimization = false; 2038 uint32_t bl_oled_enable_delay = 50; // in ms 2039 uint32_t post_oui_delay = 30; // 30ms 2040 /* Reduce link bandwidth between failed link training attempts. */ 2041 bool do_fallback = false; 2042 int lt_attempts = LINK_TRAINING_ATTEMPTS; 2043 2044 // Increase retry count if attempting DP1.x on FIXED_VS link 2045 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && 2046 link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2047 lt_attempts = 10; 2048 2049 // check for seamless boot 2050 for (i = 0; i < state->stream_count; i++) { 2051 if (state->streams[i]->apply_seamless_boot_optimization) { 2052 apply_seamless_boot_optimization = true; 2053 break; 2054 } 2055 } 2056 2057 /* Train with fallback when enabling DPIA link. Conventional links are 2058 * trained with fallback during sink detection. 2059 */ 2060 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 2061 !link->dc->config.enable_dpia_pre_training) 2062 do_fallback = true; 2063 2064 /* 2065 * Temporary w/a to get DP2.0 link rates to work with SST. 2066 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved. 2067 */ 2068 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING && 2069 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2070 link->dc->debug.set_mst_en_for_sst) { 2071 enable_mst_on_sink(link, true); 2072 } 2073 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 2074 /*in case it is not on*/ 2075 if (!link->dc->config.edp_no_power_sequencing) 2076 link->dc->hwss.edp_power_control(link, true); 2077 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 2078 } 2079 2080 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { 2081 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */ 2082 } else { 2083 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 2084 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 2085 if (state->clk_mgr && !apply_seamless_boot_optimization) 2086 state->clk_mgr->funcs->update_clocks(state->clk_mgr, 2087 state, false); 2088 } 2089 2090 // during mode switch we do DP_SET_POWER off then on, and OUI is lost 2091 dpcd_set_source_specific_data(link); 2092 if (link->dpcd_sink_ext_caps.raw != 0) { 2093 post_oui_delay += link->panel_config.pps.extra_post_OUI_ms; 2094 msleep(post_oui_delay); 2095 } 2096 2097 // similarly, mode switch can cause loss of cable ID 2098 dpcd_write_cable_id_to_dprx(link); 2099 2100 skip_video_pattern = true; 2101 2102 if (link_settings->link_rate == LINK_RATE_LOW) 2103 skip_video_pattern = false; 2104 2105 if (stream->sink_patches.oled_optimize_display_on) 2106 set_default_brightness_aux(link); 2107 2108 if (perform_link_training_with_retries(link_settings, 2109 skip_video_pattern, 2110 lt_attempts, 2111 pipe_ctx, 2112 pipe_ctx->stream->signal, 2113 do_fallback)) { 2114 status = DC_OK; 2115 } else { 2116 status = DC_FAIL_DP_LINK_TRAINING; 2117 } 2118 2119 if (link->preferred_training_settings.fec_enable) 2120 fec_enable = *link->preferred_training_settings.fec_enable; 2121 else 2122 fec_enable = true; 2123 2124 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) 2125 dp_set_fec_enable(link, &pipe_ctx->link_res, fec_enable); 2126 2127 // during mode set we do DP_SET_POWER off then on, aux writes are lost 2128 if (link->dpcd_sink_ext_caps.bits.oled == 1 || 2129 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || 2130 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { 2131 if (!stream->sink_patches.oled_optimize_display_on) { 2132 set_default_brightness_aux(link); 2133 if (link->dpcd_sink_ext_caps.bits.oled == 1) 2134 msleep(bl_oled_enable_delay); 2135 edp_backlight_enable_aux(link, true); 2136 } else { 2137 edp_backlight_enable_aux(link, true); 2138 } 2139 } 2140 2141 return status; 2142 } 2143 2144 static enum dc_status enable_link_edp( 2145 struct dc_state *state, 2146 struct pipe_ctx *pipe_ctx) 2147 { 2148 return enable_link_dp(state, pipe_ctx); 2149 } 2150 2151 static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2152 { 2153 struct dc_stream_state *stream = pipe_ctx->stream; 2154 struct dc_link *link = stream->link; 2155 struct dc *dc = stream->ctx->dc; 2156 2157 if (stream->phy_pix_clk == 0) 2158 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2159 2160 memset(&stream->link->cur_link_settings, 0, 2161 sizeof(struct dc_link_settings)); 2162 dc->hwss.enable_lvds_link_output( 2163 link, 2164 &pipe_ctx->link_res, 2165 pipe_ctx->clock_source->id, 2166 stream->phy_pix_clk); 2167 2168 } 2169 2170 static enum dc_status enable_link_dp_mst( 2171 struct dc_state *state, 2172 struct pipe_ctx *pipe_ctx) 2173 { 2174 struct dc_link *link = pipe_ctx->stream->link; 2175 unsigned char mstm_cntl = 0; 2176 2177 /* sink signal type after MST branch is MST. Multiple MST sinks 2178 * share one link. Link DP PHY is enable or training only once. 2179 */ 2180 if (link->link_status.link_active) 2181 return DC_OK; 2182 2183 /* clear payload table */ 2184 core_link_read_dpcd(link, DP_MSTM_CTRL, &mstm_cntl, 1); 2185 if (mstm_cntl & DP_MST_EN) 2186 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 2187 2188 /* to make sure the pending down rep can be processed 2189 * before enabling the link 2190 */ 2191 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 2192 2193 /* set the sink to MST mode before enabling the link */ 2194 enable_mst_on_sink(link, true); 2195 2196 return enable_link_dp(state, pipe_ctx); 2197 } 2198 2199 static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) 2200 { 2201 struct dc_link *link = pipe_ctx->stream->link; 2202 2203 link->dc->hwss.enable_dp_link_output(link, 2204 &pipe_ctx->link_res, 2205 SIGNAL_TYPE_DISPLAY_PORT, 2206 pipe_ctx->clock_source->id, 2207 &pipe_ctx->link_config.dp_link_settings); 2208 return DC_OK; 2209 } 2210 2211 static enum dc_status enable_link( 2212 struct dc_state *state, 2213 struct pipe_ctx *pipe_ctx) 2214 { 2215 enum dc_status status = DC_ERROR_UNEXPECTED; 2216 struct dc_stream_state *stream = pipe_ctx->stream; 2217 struct dc_link *link = stream->link; 2218 2219 /* There's some scenarios where driver is unloaded with display 2220 * still enabled. When driver is reloaded, it may cause a display 2221 * to not light up if there is a mismatch between old and new 2222 * link settings. Need to call disable first before enabling at 2223 * new link settings. 2224 */ 2225 if (link->link_status.link_active) 2226 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2227 2228 switch (pipe_ctx->stream->signal) { 2229 case SIGNAL_TYPE_DISPLAY_PORT: 2230 status = enable_link_dp(state, pipe_ctx); 2231 break; 2232 case SIGNAL_TYPE_EDP: 2233 status = enable_link_edp(state, pipe_ctx); 2234 break; 2235 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2236 status = enable_link_dp_mst(state, pipe_ctx); 2237 msleep(200); 2238 break; 2239 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2240 case SIGNAL_TYPE_DVI_DUAL_LINK: 2241 case SIGNAL_TYPE_HDMI_TYPE_A: 2242 enable_link_hdmi(pipe_ctx); 2243 status = DC_OK; 2244 break; 2245 case SIGNAL_TYPE_LVDS: 2246 enable_link_lvds(pipe_ctx); 2247 status = DC_OK; 2248 break; 2249 case SIGNAL_TYPE_VIRTUAL: 2250 status = enable_link_virtual(pipe_ctx); 2251 break; 2252 default: 2253 break; 2254 } 2255 2256 if (status == DC_OK) { 2257 pipe_ctx->stream->link->link_status.link_active = true; 2258 } 2259 2260 return status; 2261 } 2262 2263 static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, int bw) 2264 { 2265 struct dc_link *link = stream->sink->link; 2266 int req_bw = bw; 2267 2268 DC_LOGGER_INIT(link->ctx->logger); 2269 2270 if (!link->dpia_bw_alloc_config.bw_alloc_enabled) 2271 return false; 2272 2273 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2274 int sink_index = 0; 2275 int i = 0; 2276 2277 for (i = 0; i < link->sink_count; i++) { 2278 if (link->remote_sinks[i] == NULL) 2279 continue; 2280 2281 if (stream->sink->sink_id != link->remote_sinks[i]->sink_id) 2282 req_bw += link->dpia_bw_alloc_config.remote_sink_req_bw[i]; 2283 else 2284 sink_index = i; 2285 } 2286 2287 link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw; 2288 } 2289 2290 /* get dp overhead for dp tunneling */ 2291 link->dpia_bw_alloc_config.dp_overhead = link_dp_dpia_get_dp_overhead_in_dp_tunneling(link); 2292 req_bw += link->dpia_bw_alloc_config.dp_overhead; 2293 2294 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw); 2295 2296 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2297 int i = 0; 2298 2299 for (i = 0; i < link->sink_count; i++) { 2300 if (link->remote_sinks[i] == NULL) 2301 continue; 2302 DC_LOG_DEBUG("%s, remote_sink=%s, request_bw=%d\n", __func__, 2303 (const char *)(&link->remote_sinks[i]->edid_caps.display_name[0]), 2304 link->dpia_bw_alloc_config.remote_sink_req_bw[i]); 2305 } 2306 } 2307 2308 return true; 2309 } 2310 2311 static bool allocate_usb4_bandwidth(struct dc_stream_state *stream) 2312 { 2313 bool ret; 2314 2315 int bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, 2316 dc_link_get_highest_encoding_format(stream->sink->link)); 2317 2318 ret = allocate_usb4_bandwidth_for_stream(stream, bw); 2319 2320 return ret; 2321 } 2322 2323 static bool deallocate_usb4_bandwidth(struct dc_stream_state *stream) 2324 { 2325 bool ret; 2326 2327 ret = allocate_usb4_bandwidth_for_stream(stream, 0); 2328 2329 return ret; 2330 } 2331 2332 void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 2333 { 2334 struct dc *dc = pipe_ctx->stream->ctx->dc; 2335 struct dc_stream_state *stream = pipe_ctx->stream; 2336 struct dc_link *link = stream->sink->link; 2337 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2338 enum dp_panel_mode panel_mode_dp = dp_get_panel_mode(link); 2339 2340 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2341 2342 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2343 2344 if (dp_is_128b_132b_signal(pipe_ctx)) 2345 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2346 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2347 return; 2348 2349 if (pipe_ctx->stream->sink) { 2350 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2351 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2352 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2353 pipe_ctx->stream->sink->edid_caps.display_name, 2354 pipe_ctx->stream->signal); 2355 } 2356 } 2357 2358 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) { 2359 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2360 set_avmute(pipe_ctx, true); 2361 } 2362 2363 dc->hwss.disable_audio_stream(pipe_ctx); 2364 2365 update_psp_stream_config(pipe_ctx, true); 2366 dc->hwss.blank_stream(pipe_ctx); 2367 2368 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2369 deallocate_usb4_bandwidth(pipe_ctx->stream); 2370 2371 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2372 deallocate_mst_payload(pipe_ctx); 2373 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2374 dp_is_128b_132b_signal(pipe_ctx)) 2375 update_sst_payload(pipe_ctx, false); 2376 2377 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2378 struct ext_hdmi_settings settings = {0}; 2379 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 2380 2381 unsigned short masked_chip_caps = link->chip_caps & 2382 AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2383 //Need to inform that sink is going to use legacy HDMI mode. 2384 write_scdc_data( 2385 link->ddc, 2386 165000,//vbios only handles 165Mhz. 2387 false); 2388 if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2389 /* DP159, Retimer settings */ 2390 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 2391 write_i2c_retimer_setting(pipe_ctx, 2392 false, false, &settings); 2393 else 2394 write_i2c_default_retimer_setting(pipe_ctx, 2395 false, false); 2396 } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2397 /* PI3EQX1204, Redriver settings */ 2398 write_i2c_redriver_setting(pipe_ctx, false); 2399 } 2400 } 2401 2402 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && 2403 !dp_is_128b_132b_signal(pipe_ctx)) { 2404 2405 /* In DP1.x SST mode, our encoder will go to TPS1 2406 * when link is on but stream is off. 2407 * Disabling link before stream will avoid exposing TPS1 pattern 2408 * during the disable sequence as it will confuse some receivers 2409 * state machine. 2410 * In DP2 or MST mode, our encoder will stay video active 2411 */ 2412 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2413 dc->hwss.disable_stream(pipe_ctx); 2414 } else { 2415 dc->hwss.disable_stream(pipe_ctx); 2416 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal); 2417 } 2418 edp_set_panel_assr(link, pipe_ctx, &panel_mode_dp, false); 2419 2420 if (pipe_ctx->stream->timing.flags.DSC) { 2421 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2422 link_set_dsc_enable(pipe_ctx, false); 2423 } 2424 if (dp_is_128b_132b_signal(pipe_ctx)) { 2425 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) 2426 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO); 2427 } 2428 2429 if (vpg && vpg->funcs->vpg_powerdown) 2430 vpg->funcs->vpg_powerdown(vpg); 2431 2432 /* for psp not exist case */ 2433 if (link->connector_signal == SIGNAL_TYPE_EDP && dc->debug.psp_disabled_wa) { 2434 /* reset internal save state to default since eDP is off */ 2435 enum dp_panel_mode panel_mode = dp_get_panel_mode(pipe_ctx->stream->link); 2436 /* since current psp not loaded, we need to reset it to default*/ 2437 link->panel_mode = panel_mode; 2438 } 2439 } 2440 2441 void link_set_dpms_on( 2442 struct dc_state *state, 2443 struct pipe_ctx *pipe_ctx) 2444 { 2445 struct dc *dc = pipe_ctx->stream->ctx->dc; 2446 struct dc_stream_state *stream = pipe_ctx->stream; 2447 struct dc_link *link = stream->sink->link; 2448 enum dc_status status; 2449 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 2450 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO; 2451 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg; 2452 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 2453 bool apply_edp_fast_boot_optimization = 2454 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2455 2456 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2457 2458 ASSERT(is_master_pipe_for_link(link, pipe_ctx)); 2459 2460 if (dp_is_128b_132b_signal(pipe_ctx)) 2461 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg; 2462 if (dc_is_virtual_signal(pipe_ctx->stream->signal)) 2463 return; 2464 2465 if (pipe_ctx->stream->sink) { 2466 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 2467 pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 2468 DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__, 2469 pipe_ctx->stream->sink->edid_caps.display_name, 2470 pipe_ctx->stream->signal); 2471 } 2472 } 2473 2474 if (!dc->config.unify_link_enc_assignment) 2475 link_enc = link_enc_cfg_get_link_enc(link); 2476 ASSERT(link_enc); 2477 2478 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) 2479 && !dp_is_128b_132b_signal(pipe_ctx)) { 2480 if (link_enc) 2481 link_enc->funcs->setup( 2482 link_enc, 2483 pipe_ctx->stream->signal); 2484 } 2485 2486 pipe_ctx->stream->link->link_state_valid = true; 2487 2488 if (pipe_ctx->stream_res.tg->funcs->set_out_mux) { 2489 if (dp_is_128b_132b_signal(pipe_ctx)) 2490 otg_out_dest = OUT_MUX_HPO_DP; 2491 else 2492 otg_out_dest = OUT_MUX_DIO; 2493 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest); 2494 } 2495 2496 link_hwss->setup_stream_attribute(pipe_ctx); 2497 2498 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2499 2500 // Enable VPG before building infoframe 2501 if (vpg && vpg->funcs->vpg_poweron) 2502 vpg->funcs->vpg_poweron(vpg); 2503 2504 resource_build_info_frame(pipe_ctx); 2505 dc->hwss.update_info_frame(pipe_ctx); 2506 2507 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2508 dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME); 2509 2510 /* Do not touch link on seamless boot optimization. */ 2511 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 2512 pipe_ctx->stream->dpms_off = false; 2513 2514 /* Still enable stream features & audio on seamless boot for DP external displays */ 2515 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { 2516 enable_stream_features(pipe_ctx); 2517 dc->hwss.enable_audio_stream(pipe_ctx); 2518 } 2519 2520 update_psp_stream_config(pipe_ctx, false); 2521 return; 2522 } 2523 2524 /* eDP lit up by bios already, no need to enable again. */ 2525 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 2526 apply_edp_fast_boot_optimization && 2527 !pipe_ctx->stream->timing.flags.DSC && 2528 !pipe_ctx->next_odm_pipe) { 2529 pipe_ctx->stream->dpms_off = false; 2530 update_psp_stream_config(pipe_ctx, false); 2531 return; 2532 } 2533 2534 if (pipe_ctx->stream->dpms_off) 2535 return; 2536 2537 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing 2538 * current link and processing the pending HPD. If we enable the link now, we may end up with a 2539 * link that is not actually connected to a sink. So we skip enabling the link in this case. 2540 */ 2541 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending) { 2542 DC_LOG_DEBUG("%s, Link%d HPD is pending, not enable it.\n", __func__, link->link_index); 2543 return; 2544 } 2545 2546 /* Have to setup DSC before DIG FE and BE are connected (which happens before the 2547 * link training). This is to make sure the bandwidth sent to DIG BE won't be 2548 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag 2549 * will be automatically set at a later time when the video is enabled 2550 * (DP_VID_STREAM_EN = 1). 2551 */ 2552 if (pipe_ctx->stream->timing.flags.DSC) { 2553 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2554 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2555 link_set_dsc_enable(pipe_ctx, true); 2556 } 2557 2558 status = enable_link(state, pipe_ctx); 2559 2560 if (status != DC_OK) { 2561 DC_LOG_WARNING("enabling link %u failed: %d\n", 2562 pipe_ctx->stream->link->link_index, 2563 status); 2564 2565 /* Abort stream enable *unless* the failure was due to 2566 * DP link training - some DP monitors will recover and 2567 * show the stream anyway. But MST displays can't proceed 2568 * without link training. 2569 */ 2570 if (status != DC_FAIL_DP_LINK_TRAINING || 2571 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2572 if (false == stream->link->link_status.link_active) 2573 disable_link(stream->link, &pipe_ctx->link_res, 2574 pipe_ctx->stream->signal); 2575 BREAK_TO_DEBUGGER(); 2576 return; 2577 } 2578 } 2579 2580 /* turn off otg test pattern if enable */ 2581 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 2582 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 2583 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 2584 COLOR_DEPTH_UNDEFINED); 2585 2586 /* This second call is needed to reconfigure the DIG 2587 * as a workaround for the incorrect value being applied 2588 * from transmitter control. 2589 */ 2590 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) || 2591 dp_is_128b_132b_signal(pipe_ctx))) { 2592 2593 if (link_enc) 2594 link_enc->funcs->setup( 2595 link_enc, 2596 pipe_ctx->stream->signal); 2597 2598 } 2599 2600 dc->hwss.enable_stream(pipe_ctx); 2601 2602 /* Set DPS PPS SDP (AKA "info frames") */ 2603 if (pipe_ctx->stream->timing.flags.DSC) { 2604 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 2605 dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2606 dp_set_dsc_on_rx(pipe_ctx, true); 2607 link_set_dsc_pps_packet(pipe_ctx, true, true); 2608 } 2609 } 2610 2611 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2612 dp_set_hblank_reduction_on_rx(pipe_ctx); 2613 2614 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 2615 allocate_usb4_bandwidth(pipe_ctx->stream); 2616 2617 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 2618 allocate_mst_payload(pipe_ctx); 2619 else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && 2620 dp_is_128b_132b_signal(pipe_ctx)) 2621 update_sst_payload(pipe_ctx, true); 2622 2623 dc->hwss.unblank_stream(pipe_ctx, 2624 &pipe_ctx->stream->link->cur_link_settings); 2625 2626 if (stream->sink_patches.delay_ignore_msa > 0) 2627 msleep(stream->sink_patches.delay_ignore_msa); 2628 2629 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2630 enable_stream_features(pipe_ctx); 2631 update_psp_stream_config(pipe_ctx, false); 2632 2633 dc->hwss.enable_audio_stream(pipe_ctx); 2634 2635 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2636 set_avmute(pipe_ctx, false); 2637 } 2638 } 2639