1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 #include <linux/acpi.h> 64 65 #include <asm/acpi.h> 66 #include <asm/cacheinfo.h> 67 #include <asm/cpuid/api.h> 68 #include <asm/desc.h> 69 #include <asm/nmi.h> 70 #include <asm/irq.h> 71 #include <asm/realmode.h> 72 #include <asm/cpu.h> 73 #include <asm/numa.h> 74 #include <asm/tlbflush.h> 75 #include <asm/mtrr.h> 76 #include <asm/mwait.h> 77 #include <asm/apic.h> 78 #include <asm/io_apic.h> 79 #include <asm/fpu/api.h> 80 #include <asm/setup.h> 81 #include <asm/uv/uv.h> 82 #include <asm/microcode.h> 83 #include <asm/i8259.h> 84 #include <asm/misc.h> 85 #include <asm/qspinlock.h> 86 #include <asm/intel-family.h> 87 #include <asm/cpu_device_id.h> 88 #include <asm/spec-ctrl.h> 89 #include <asm/hw_irq.h> 90 #include <asm/stackprotector.h> 91 #include <asm/sev.h> 92 #include <asm/spec-ctrl.h> 93 94 /* representing HT siblings of each logical CPU */ 95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 96 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 97 98 /* representing HT and core siblings of each logical CPU */ 99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 100 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 101 102 /* representing HT, core, and die siblings of each logical CPU */ 103 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 104 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 105 106 /* Representing CPUs for which sibling maps can be computed */ 107 static cpumask_var_t cpu_sibling_setup_mask; 108 109 struct mwait_cpu_dead { 110 unsigned int control; 111 unsigned int status; 112 }; 113 114 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 115 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 116 117 /* 118 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 119 * that it's unlikely to be touched by other CPUs. 120 */ 121 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 122 123 /* Maximum number of SMT threads on any online core */ 124 int __read_mostly __max_smt_threads = 1; 125 126 /* Flag to indicate if a complete sched domain rebuild is required */ 127 bool x86_topology_update; 128 129 int arch_update_cpu_topology(void) 130 { 131 int retval = x86_topology_update; 132 133 x86_topology_update = false; 134 return retval; 135 } 136 137 static unsigned int smpboot_warm_reset_vector_count; 138 139 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 140 { 141 unsigned long flags; 142 143 spin_lock_irqsave(&rtc_lock, flags); 144 if (!smpboot_warm_reset_vector_count++) { 145 CMOS_WRITE(0xa, 0xf); 146 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 147 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 148 } 149 spin_unlock_irqrestore(&rtc_lock, flags); 150 } 151 152 static inline void smpboot_restore_warm_reset_vector(void) 153 { 154 unsigned long flags; 155 156 /* 157 * Paranoid: Set warm reset code and vector here back 158 * to default values. 159 */ 160 spin_lock_irqsave(&rtc_lock, flags); 161 if (!--smpboot_warm_reset_vector_count) { 162 CMOS_WRITE(0, 0xf); 163 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 164 } 165 spin_unlock_irqrestore(&rtc_lock, flags); 166 167 } 168 169 /* Run the next set of setup steps for the upcoming CPU */ 170 static void ap_starting(void) 171 { 172 int cpuid = smp_processor_id(); 173 174 /* Mop up eventual mwait_play_dead() wreckage */ 175 this_cpu_write(mwait_cpu_dead.status, 0); 176 this_cpu_write(mwait_cpu_dead.control, 0); 177 178 /* 179 * If woken up by an INIT in an 82489DX configuration the alive 180 * synchronization guarantees that the CPU does not reach this 181 * point before an INIT_deassert IPI reaches the local APIC, so it 182 * is now safe to touch the local APIC. 183 * 184 * Set up this CPU, first the APIC, which is probably redundant on 185 * most boards. 186 */ 187 apic_ap_setup(); 188 189 /* Save the processor parameters. */ 190 identify_secondary_cpu(cpuid); 191 192 /* 193 * The topology information must be up to date before 194 * notify_cpu_starting(). 195 */ 196 set_cpu_sibling_map(cpuid); 197 198 ap_init_aperfmperf(); 199 200 pr_debug("Stack at about %p\n", &cpuid); 201 202 wmb(); 203 204 /* 205 * This runs the AP through all the cpuhp states to its target 206 * state CPUHP_ONLINE. 207 */ 208 notify_cpu_starting(cpuid); 209 } 210 211 static void ap_calibrate_delay(void) 212 { 213 /* 214 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 215 * identify_secondary_cpu() stored a value that is close but not as 216 * accurate as the value just calculated. 217 * 218 * As this is invoked after the TSC synchronization check, 219 * calibrate_delay_is_known() will skip the calibration routine 220 * when TSC is synchronized across sockets. 221 */ 222 calibrate_delay(); 223 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 224 } 225 226 /* 227 * Activate a secondary processor. 228 */ 229 static void notrace __noendbr start_secondary(void *unused) 230 { 231 /* 232 * Don't put *anything* except direct CPU state initialization 233 * before cpu_init(), SMP booting is too fragile that we want to 234 * limit the things done here to the most necessary things. 235 */ 236 cr4_init(); 237 238 /* 239 * 32-bit specific. 64-bit reaches this code with the correct page 240 * table established. Yet another historical divergence. 241 */ 242 if (IS_ENABLED(CONFIG_X86_32)) { 243 /* switch away from the initial page table */ 244 load_cr3(swapper_pg_dir); 245 __flush_tlb_all(); 246 } 247 248 cpu_init_exception_handling(false); 249 250 /* 251 * Load the microcode before reaching the AP alive synchronization 252 * point below so it is not part of the full per CPU serialized 253 * bringup part when "parallel" bringup is enabled. 254 * 255 * That's even safe when hyperthreading is enabled in the CPU as 256 * the core code starts the primary threads first and leaves the 257 * secondary threads waiting for SIPI. Loading microcode on 258 * physical cores concurrently is a safe operation. 259 * 260 * This covers both the Intel specific issue that concurrent 261 * microcode loading on SMT siblings must be prohibited and the 262 * vendor independent issue`that microcode loading which changes 263 * CPUID, MSRs etc. must be strictly serialized to maintain 264 * software state correctness. 265 */ 266 load_ucode_ap(); 267 268 /* 269 * Synchronization point with the hotplug core. Sets this CPUs 270 * synchronization state to ALIVE and spin-waits for the control CPU to 271 * release this CPU for further bringup. 272 */ 273 cpuhp_ap_sync_alive(); 274 275 cpu_init(); 276 fpu__init_cpu(); 277 rcutree_report_cpu_starting(raw_smp_processor_id()); 278 x86_cpuinit.early_percpu_clock_init(); 279 280 ap_starting(); 281 282 /* Check TSC synchronization with the control CPU. */ 283 check_tsc_sync_target(); 284 285 /* 286 * Calibrate the delay loop after the TSC synchronization check. 287 * This allows to skip the calibration when TSC is synchronized 288 * across sockets. 289 */ 290 ap_calibrate_delay(); 291 292 speculative_store_bypass_ht_init(); 293 294 /* 295 * Lock vector_lock, set CPU online and bring the vector 296 * allocator online. Online must be set with vector_lock held 297 * to prevent a concurrent irq setup/teardown from seeing a 298 * half valid vector space. 299 */ 300 lock_vector_lock(); 301 set_cpu_online(smp_processor_id(), true); 302 lapic_online(); 303 unlock_vector_lock(); 304 x86_platform.nmi_init(); 305 306 /* enable local interrupts */ 307 local_irq_enable(); 308 309 x86_cpuinit.setup_percpu_clockev(); 310 311 wmb(); 312 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 313 } 314 ANNOTATE_NOENDBR_SYM(start_secondary); 315 316 static bool 317 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 318 { 319 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 320 321 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 322 } 323 324 static bool 325 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 326 { 327 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 328 329 return !WARN_ONCE(!topology_same_node(c, o), 330 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 331 "[node: %d != %d]. Ignoring dependency.\n", 332 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 333 } 334 335 #define link_mask(mfunc, c1, c2) \ 336 do { \ 337 cpumask_set_cpu((c1), mfunc(c2)); \ 338 cpumask_set_cpu((c2), mfunc(c1)); \ 339 } while (0) 340 341 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 342 { 343 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 344 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 345 346 if (c->topo.pkg_id == o->topo.pkg_id && 347 c->topo.die_id == o->topo.die_id && 348 c->topo.amd_node_id == o->topo.amd_node_id && 349 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) { 350 if (c->topo.core_id == o->topo.core_id) 351 return topology_sane(c, o, "smt"); 352 353 if ((c->topo.cu_id != 0xff) && 354 (o->topo.cu_id != 0xff) && 355 (c->topo.cu_id == o->topo.cu_id)) 356 return topology_sane(c, o, "smt"); 357 } 358 359 } else if (c->topo.pkg_id == o->topo.pkg_id && 360 c->topo.die_id == o->topo.die_id && 361 c->topo.core_id == o->topo.core_id) { 362 return topology_sane(c, o, "smt"); 363 } 364 365 return false; 366 } 367 368 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 369 { 370 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id) 371 return false; 372 373 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1) 374 return c->topo.amd_node_id == o->topo.amd_node_id; 375 376 return true; 377 } 378 379 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 380 { 381 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 382 383 /* If the arch didn't set up l2c_id, fall back to SMT */ 384 if (per_cpu_l2c_id(cpu1) == BAD_APICID) 385 return match_smt(c, o); 386 387 /* Do not match if L2 cache id does not match: */ 388 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2)) 389 return false; 390 391 return topology_sane(c, o, "l2c"); 392 } 393 394 /* 395 * Unlike the other levels, we do not enforce keeping a 396 * multicore group inside a NUMA node. If this happens, we will 397 * discard the MC level of the topology later. 398 */ 399 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 400 { 401 if (c->topo.pkg_id == o->topo.pkg_id) 402 return true; 403 return false; 404 } 405 406 /* 407 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 408 * 409 * Any Intel CPU that has multiple nodes per package and does not 410 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 411 * 412 * When in SNC mode, these CPUs enumerate an LLC that is shared 413 * by multiple NUMA nodes. The LLC is shared for off-package data 414 * access but private to the NUMA node (half of the package) for 415 * on-package access. CPUID (the source of the information about 416 * the LLC) can only enumerate the cache as shared or unshared, 417 * but not this particular configuration. 418 */ 419 420 static const struct x86_cpu_id intel_cod_cpu[] = { 421 X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */ 422 X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */ 423 X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */ 424 {} 425 }; 426 427 /* 428 * Allows splitting the LLC by matching 'core_id % split_llc'. 429 * 430 * This is mostly a debug hack to emulate systems with multiple LLCs per node 431 * on systems that do not naturally have this. 432 */ 433 static unsigned int split_llc = 0; 434 435 static int __init split_llc_setup(char *str) 436 { 437 get_option(&str, &split_llc); 438 return 0; 439 } 440 early_param("split_llc", split_llc_setup); 441 442 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 443 { 444 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 445 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 446 bool intel_snc = id && id->driver_data; 447 448 /* Do not match if we do not have a valid APICID for cpu: */ 449 if (per_cpu_llc_id(cpu1) == BAD_APICID) 450 return false; 451 452 /* Do not match if LLC id does not match: */ 453 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2)) 454 return false; 455 456 if (split_llc && 457 (per_cpu_core_id(cpu1) % split_llc) != 458 (per_cpu_core_id(cpu2) % split_llc)) 459 return false; 460 461 /* 462 * Allow the SNC topology without warning. Return of false 463 * means 'c' does not share the LLC of 'o'. This will be 464 * reflected to userspace. 465 */ 466 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 467 return false; 468 469 return topology_sane(c, o, "llc"); 470 } 471 472 473 static inline int x86_sched_itmt_flags(void) 474 { 475 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 476 } 477 478 #ifdef CONFIG_SCHED_MC 479 static int x86_core_flags(void) 480 { 481 return cpu_core_flags() | x86_sched_itmt_flags(); 482 } 483 #endif 484 #ifdef CONFIG_SCHED_CLUSTER 485 static int x86_cluster_flags(void) 486 { 487 return cpu_cluster_flags() | x86_sched_itmt_flags(); 488 } 489 #endif 490 491 static struct sched_domain_topology_level x86_topology[] = { 492 SDTL_INIT(tl_smt_mask, cpu_smt_flags, SMT), 493 #ifdef CONFIG_SCHED_CLUSTER 494 SDTL_INIT(tl_cls_mask, x86_cluster_flags, CLS), 495 #endif 496 #ifdef CONFIG_SCHED_MC 497 SDTL_INIT(tl_mc_mask, x86_core_flags, MC), 498 #endif 499 SDTL_INIT(tl_pkg_mask, x86_sched_itmt_flags, PKG), 500 { NULL }, 501 }; 502 503 static void __init build_sched_topology(void) 504 { 505 struct sched_domain_topology_level *topology = x86_topology; 506 507 /* 508 * When there is NUMA topology inside the package invalidate the 509 * PKG domain since the NUMA domains will auto-magically create the 510 * right spanning domains based on the SLIT. 511 */ 512 if (topology_num_nodes_per_package() > 1) { 513 unsigned int pkgdom = ARRAY_SIZE(x86_topology) - 2; 514 515 memset(&x86_topology[pkgdom], 0, sizeof(x86_topology[pkgdom])); 516 } 517 518 /* 519 * Drop the SMT domains if there is only one thread per-core 520 * since it'll get degenerated by the scheduler anyways. 521 */ 522 if (cpu_smt_num_threads <= 1) 523 ++topology; 524 525 set_sched_topology(topology); 526 } 527 528 #ifdef CONFIG_NUMA 529 /* 530 * Test if the on-trace cluster at (N,N) is symmetric. 531 * Uses upper triangle iteration to avoid obvious duplicates. 532 */ 533 static bool slit_cluster_symmetric(int N) 534 { 535 int u = topology_num_nodes_per_package(); 536 537 for (int k = 0; k < u; k++) { 538 for (int l = k; l < u; l++) { 539 if (node_distance(N + k, N + l) != 540 node_distance(N + l, N + k)) 541 return false; 542 } 543 } 544 545 return true; 546 } 547 548 /* 549 * Return the package-id of the cluster, or ~0 if indeterminate. 550 * Each node in the on-trace cluster should have the same package-id. 551 */ 552 static u32 slit_cluster_package(int N) 553 { 554 int u = topology_num_nodes_per_package(); 555 u32 pkg_id = ~0; 556 557 for (int n = 0; n < u; n++) { 558 const struct cpumask *cpus = cpumask_of_node(N + n); 559 int cpu; 560 561 for_each_cpu(cpu, cpus) { 562 u32 id = topology_logical_package_id(cpu); 563 564 if (pkg_id == ~0) 565 pkg_id = id; 566 if (pkg_id != id) 567 return ~0; 568 } 569 } 570 571 return pkg_id; 572 } 573 574 /* 575 * Validate the SLIT table is of the form expected for SNC, specifically: 576 * 577 * - each on-trace cluster should be symmetric, 578 * - each on-trace cluster should have a unique package-id. 579 * 580 * If you NUMA_EMU on top of SNC, you get to keep the pieces. 581 */ 582 static bool slit_validate(void) 583 { 584 int u = topology_num_nodes_per_package(); 585 u32 pkg_id, prev_pkg_id = ~0; 586 587 for (int pkg = 0; pkg < topology_max_packages(); pkg++) { 588 int n = pkg * u; 589 590 /* 591 * Ensure the on-trace cluster is symmetric and each cluster 592 * has a different package id. 593 */ 594 if (!slit_cluster_symmetric(n)) 595 return false; 596 pkg_id = slit_cluster_package(n); 597 if (pkg_id == ~0) 598 return false; 599 if (pkg && pkg_id == prev_pkg_id) 600 return false; 601 602 prev_pkg_id = pkg_id; 603 } 604 605 return true; 606 } 607 608 /* 609 * Compute a sanitized SLIT table for SNC; notably SNC-3 can end up with 610 * asymmetric off-trace clusters, reflecting physical assymmetries. However 611 * this leads to 'unfortunate' sched_domain configurations. 612 * 613 * For example dual socket GNR with SNC-3: 614 * 615 * node distances: 616 * node 0 1 2 3 4 5 617 * 0: 10 15 17 21 28 26 618 * 1: 15 10 15 23 26 23 619 * 2: 17 15 10 26 23 21 620 * 3: 21 28 26 10 15 17 621 * 4: 23 26 23 15 10 15 622 * 5: 26 23 21 17 15 10 623 * 624 * Fix things up by averaging out the off-trace clusters; resulting in: 625 * 626 * node 0 1 2 3 4 5 627 * 0: 10 15 17 24 24 24 628 * 1: 15 10 15 24 24 24 629 * 2: 17 15 10 24 24 24 630 * 3: 24 24 24 10 15 17 631 * 4: 24 24 24 15 10 15 632 * 5: 24 24 24 17 15 10 633 */ 634 static int slit_cluster_distance(int i, int j) 635 { 636 static int slit_valid = -1; 637 int u = topology_num_nodes_per_package(); 638 long d = 0; 639 int x, y; 640 641 if (slit_valid < 0) { 642 slit_valid = slit_validate(); 643 if (!slit_valid) 644 pr_err(FW_BUG "SLIT table doesn't have the expected form for SNC -- fixup disabled!\n"); 645 else 646 pr_info("Fixing up SNC SLIT table.\n"); 647 } 648 649 /* 650 * Is this a unit cluster on the trace? 651 */ 652 if ((i / u) == (j / u) || !slit_valid) 653 return node_distance(i, j); 654 655 /* 656 * Off-trace cluster. 657 * 658 * Notably average out the symmetric pair of off-trace clusters to 659 * ensure the resulting SLIT table is symmetric. 660 */ 661 x = i - (i % u); 662 y = j - (j % u); 663 664 for (i = x; i < x + u; i++) { 665 for (j = y; j < y + u; j++) { 666 d += node_distance(i, j); 667 d += node_distance(j, i); 668 } 669 } 670 671 return d / (2*u*u); 672 } 673 674 int arch_sched_node_distance(int from, int to) 675 { 676 int d = node_distance(from, to); 677 678 switch (boot_cpu_data.x86_vfm) { 679 case INTEL_GRANITERAPIDS_X: 680 case INTEL_ATOM_DARKMONT_X: 681 if (topology_max_packages() == 1 || 682 topology_num_nodes_per_package() < 3) 683 return d; 684 685 /* 686 * Handle SNC-3 asymmetries. 687 */ 688 return slit_cluster_distance(from, to); 689 } 690 return d; 691 } 692 #endif /* CONFIG_NUMA */ 693 694 void set_cpu_sibling_map(int cpu) 695 { 696 bool has_smt = __max_threads_per_core > 1; 697 bool has_mp = has_smt || topology_num_cores_per_package() > 1; 698 struct cpuinfo_x86 *c = &cpu_data(cpu); 699 struct cpuinfo_x86 *o; 700 int i, threads; 701 702 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 703 704 if (!has_mp) { 705 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 706 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 707 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 708 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 709 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 710 c->booted_cores = 1; 711 return; 712 } 713 714 for_each_cpu(i, cpu_sibling_setup_mask) { 715 o = &cpu_data(i); 716 717 if (match_pkg(c, o) && !topology_same_node(c, o)) 718 WARN_ON_ONCE(topology_num_nodes_per_package() == 1); 719 720 if ((i == cpu) || (has_smt && match_smt(c, o))) 721 link_mask(topology_sibling_cpumask, cpu, i); 722 723 if ((i == cpu) || (has_mp && match_llc(c, o))) 724 link_mask(cpu_llc_shared_mask, cpu, i); 725 726 if ((i == cpu) || (has_mp && match_l2c(c, o))) 727 link_mask(cpu_l2c_shared_mask, cpu, i); 728 729 if ((i == cpu) || (has_mp && match_die(c, o))) 730 link_mask(topology_die_cpumask, cpu, i); 731 } 732 733 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 734 if (threads > __max_smt_threads) 735 __max_smt_threads = threads; 736 737 for_each_cpu(i, topology_sibling_cpumask(cpu)) 738 cpu_data(i).smt_active = threads > 1; 739 740 /* 741 * This needs a separate iteration over the cpus because we rely on all 742 * topology_sibling_cpumask links to be set-up. 743 */ 744 for_each_cpu(i, cpu_sibling_setup_mask) { 745 o = &cpu_data(i); 746 747 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 748 link_mask(topology_core_cpumask, cpu, i); 749 750 /* 751 * Does this new cpu bringup a new core? 752 */ 753 if (threads == 1) { 754 /* 755 * for each core in package, increment 756 * the booted_cores for this new cpu 757 */ 758 if (cpumask_first( 759 topology_sibling_cpumask(i)) == i) 760 c->booted_cores++; 761 /* 762 * increment the core count for all 763 * the other cpus in this package 764 */ 765 if (i != cpu) 766 cpu_data(i).booted_cores++; 767 } else if (i != cpu && !c->booted_cores) 768 c->booted_cores = cpu_data(i).booted_cores; 769 } 770 } 771 } 772 773 /* maps the cpu to the sched domain representing multi-core */ 774 const struct cpumask *cpu_coregroup_mask(int cpu) 775 { 776 return cpu_llc_shared_mask(cpu); 777 } 778 779 const struct cpumask *cpu_clustergroup_mask(int cpu) 780 { 781 return cpu_l2c_shared_mask(cpu); 782 } 783 EXPORT_SYMBOL_GPL(cpu_clustergroup_mask); 784 785 static void impress_friends(void) 786 { 787 int cpu; 788 unsigned long bogosum = 0; 789 /* 790 * Allow the user to impress friends. 791 */ 792 pr_debug("Before bogomips\n"); 793 for_each_online_cpu(cpu) 794 bogosum += cpu_data(cpu).loops_per_jiffy; 795 796 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 797 num_online_cpus(), 798 bogosum/(500000/HZ), 799 (bogosum/(5000/HZ))%100); 800 801 pr_debug("Before bogocount - setting activated=1\n"); 802 } 803 804 /* 805 * The Multiprocessor Specification 1.4 (1997) example code suggests 806 * that there should be a 10ms delay between the BSP asserting INIT 807 * and de-asserting INIT, when starting a remote processor. 808 * But that slows boot and resume on modern processors, which include 809 * many cores and don't require that delay. 810 * 811 * Cmdline "cpu_init_udelay=" is available to override this delay. 812 */ 813 #define UDELAY_10MS_LEGACY 10000 814 815 static unsigned int init_udelay = UINT_MAX; 816 817 static int __init cpu_init_udelay(char *str) 818 { 819 get_option(&str, &init_udelay); 820 821 return 0; 822 } 823 early_param("cpu_init_udelay", cpu_init_udelay); 824 825 static void __init smp_set_init_udelay(void) 826 { 827 /* if cmdline changed it from default, leave it alone */ 828 if (init_udelay != UINT_MAX) 829 return; 830 831 /* if modern processor, use no delay */ 832 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) || 833 (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON && boot_cpu_data.x86 >= 0x18) || 834 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && boot_cpu_data.x86 >= 0xF)) { 835 init_udelay = 0; 836 return; 837 } 838 /* else, use legacy delay */ 839 init_udelay = UDELAY_10MS_LEGACY; 840 } 841 842 /* 843 * Wake up AP by INIT, INIT, STARTUP sequence. 844 */ 845 static void send_init_sequence(u32 phys_apicid) 846 { 847 int maxlvt = lapic_get_maxlvt(); 848 849 /* Be paranoid about clearing APIC errors. */ 850 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 851 /* Due to the Pentium erratum 3AP. */ 852 if (maxlvt > 3) 853 apic_write(APIC_ESR, 0); 854 apic_read(APIC_ESR); 855 } 856 857 /* Assert INIT on the target CPU */ 858 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 859 safe_apic_wait_icr_idle(); 860 861 udelay(init_udelay); 862 863 /* Deassert INIT on the target CPU */ 864 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 865 safe_apic_wait_icr_idle(); 866 } 867 868 /* 869 * Wake up AP by INIT, INIT, STARTUP sequence. 870 */ 871 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip, unsigned int cpu) 872 { 873 unsigned long send_status = 0, accept_status = 0; 874 int num_starts, j, maxlvt; 875 876 preempt_disable(); 877 maxlvt = lapic_get_maxlvt(); 878 send_init_sequence(phys_apicid); 879 880 mb(); 881 882 /* 883 * Should we send STARTUP IPIs ? 884 * 885 * Determine this based on the APIC version. 886 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 887 */ 888 if (APIC_INTEGRATED(boot_cpu_apic_version)) 889 num_starts = 2; 890 else 891 num_starts = 0; 892 893 /* 894 * Run STARTUP IPI loop. 895 */ 896 pr_debug("#startup loops: %d\n", num_starts); 897 898 for (j = 1; j <= num_starts; j++) { 899 pr_debug("Sending STARTUP #%d\n", j); 900 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 901 apic_write(APIC_ESR, 0); 902 apic_read(APIC_ESR); 903 pr_debug("After apic_write\n"); 904 905 /* 906 * STARTUP IPI 907 */ 908 909 /* Target chip */ 910 /* Boot on the stack */ 911 /* Kick the second */ 912 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 913 phys_apicid); 914 915 /* 916 * Give the other CPU some time to accept the IPI. 917 */ 918 if (init_udelay == 0) 919 udelay(10); 920 else 921 udelay(300); 922 923 pr_debug("Startup point 1\n"); 924 925 pr_debug("Waiting for send to finish...\n"); 926 send_status = safe_apic_wait_icr_idle(); 927 928 /* 929 * Give the other CPU some time to accept the IPI. 930 */ 931 if (init_udelay == 0) 932 udelay(10); 933 else 934 udelay(200); 935 936 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 937 apic_write(APIC_ESR, 0); 938 accept_status = (apic_read(APIC_ESR) & 0xEF); 939 if (send_status || accept_status) 940 break; 941 } 942 pr_debug("After Startup\n"); 943 944 if (send_status) 945 pr_err("APIC never delivered???\n"); 946 if (accept_status) 947 pr_err("APIC delivery error (%lx)\n", accept_status); 948 949 preempt_enable(); 950 return (send_status | accept_status); 951 } 952 953 /* reduce the number of lines printed when booting a large cpu count system */ 954 static void announce_cpu(int cpu, int apicid) 955 { 956 static int width, node_width, first = 1; 957 static int current_node = NUMA_NO_NODE; 958 int node = early_cpu_to_node(cpu); 959 960 if (!width) 961 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 962 963 if (!node_width) 964 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 965 966 if (system_state < SYSTEM_RUNNING) { 967 if (first) 968 pr_info("x86: Booting SMP configuration:\n"); 969 970 if (node != current_node) { 971 if (current_node > (-1)) 972 pr_cont("\n"); 973 current_node = node; 974 975 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 976 node_width - num_digits(node), " ", node); 977 } 978 979 /* Add padding for the BSP */ 980 if (first) 981 pr_cont("%*s", width + 1, " "); 982 first = 0; 983 984 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 985 } else 986 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 987 node, cpu, apicid); 988 } 989 990 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 991 { 992 int ret; 993 994 /* Just in case we booted with a single CPU. */ 995 alternatives_enable_smp(); 996 997 per_cpu(current_task, cpu) = idle; 998 cpu_init_stack_canary(cpu, idle); 999 1000 /* Initialize the interrupt stack(s) */ 1001 ret = irq_init_percpu_irqstack(cpu); 1002 if (ret) 1003 return ret; 1004 1005 #ifdef CONFIG_X86_32 1006 /* Stack for startup_32 can be just as for start_secondary onwards */ 1007 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 1008 #endif 1009 return 0; 1010 } 1011 1012 /* 1013 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1014 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1015 * Returns zero if startup was successfully sent, else error code from 1016 * ->wakeup_secondary_cpu. 1017 */ 1018 static int do_boot_cpu(u32 apicid, unsigned int cpu, struct task_struct *idle) 1019 { 1020 unsigned long start_ip = real_mode_header->trampoline_start; 1021 int ret; 1022 1023 #ifdef CONFIG_X86_64 1024 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1025 if (apic->wakeup_secondary_cpu_64) 1026 start_ip = real_mode_header->trampoline_start64; 1027 #endif 1028 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1029 initial_code = (unsigned long)start_secondary; 1030 1031 if (IS_ENABLED(CONFIG_X86_32)) { 1032 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1033 initial_stack = idle->thread.sp; 1034 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 1035 smpboot_control = cpu; 1036 } 1037 1038 /* Enable the espfix hack for this CPU */ 1039 init_espfix_ap(cpu); 1040 1041 /* So we see what's up */ 1042 announce_cpu(cpu, apicid); 1043 1044 /* 1045 * This grunge runs the startup process for 1046 * the targeted processor. 1047 */ 1048 if (x86_platform.legacy.warm_reset) { 1049 1050 pr_debug("Setting warm reset code and vector.\n"); 1051 1052 smpboot_setup_warm_reset_vector(start_ip); 1053 /* 1054 * Be paranoid about clearing APIC errors. 1055 */ 1056 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1057 apic_write(APIC_ESR, 0); 1058 apic_read(APIC_ESR); 1059 } 1060 } 1061 1062 smp_mb(); 1063 1064 /* 1065 * Wake up a CPU in difference cases: 1066 * - Use a method from the APIC driver if one defined, with wakeup 1067 * straight to 64-bit mode preferred over wakeup to RM. 1068 * Otherwise, 1069 * - Use an INIT boot APIC message 1070 */ 1071 if (apic->wakeup_secondary_cpu_64) 1072 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip, cpu); 1073 else if (apic->wakeup_secondary_cpu) 1074 ret = apic->wakeup_secondary_cpu(apicid, start_ip, cpu); 1075 else 1076 ret = wakeup_secondary_cpu_via_init(apicid, start_ip, cpu); 1077 1078 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 1079 if (ret) 1080 arch_cpuhp_cleanup_kick_cpu(cpu); 1081 return ret; 1082 } 1083 1084 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1085 { 1086 u32 apicid = apic->cpu_present_to_apicid(cpu); 1087 int err; 1088 1089 lockdep_assert_irqs_enabled(); 1090 1091 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1092 1093 if (apicid == BAD_APICID || !apic_id_valid(apicid)) { 1094 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid); 1095 return -EINVAL; 1096 } 1097 1098 if (!test_bit(apicid, phys_cpu_present_map)) { 1099 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid); 1100 return -EINVAL; 1101 } 1102 1103 /* 1104 * Save current MTRR state in case it was changed since early boot 1105 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1106 */ 1107 mtrr_save_state(); 1108 1109 /* the FPU context is blank, nobody can own it */ 1110 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1111 1112 err = common_cpu_up(cpu, tidle); 1113 if (err) 1114 return err; 1115 1116 err = do_boot_cpu(apicid, cpu, tidle); 1117 if (err) 1118 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1119 1120 return err; 1121 } 1122 1123 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1124 { 1125 return smp_ops.kick_ap_alive(cpu, tidle); 1126 } 1127 1128 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1129 { 1130 /* Cleanup possible dangling ends... */ 1131 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1132 smpboot_restore_warm_reset_vector(); 1133 } 1134 1135 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1136 { 1137 if (smp_ops.cleanup_dead_cpu) 1138 smp_ops.cleanup_dead_cpu(cpu); 1139 1140 if (system_state == SYSTEM_RUNNING) 1141 pr_info("CPU %u is now offline\n", cpu); 1142 } 1143 1144 void arch_cpuhp_sync_state_poll(void) 1145 { 1146 if (smp_ops.poll_sync_state) 1147 smp_ops.poll_sync_state(); 1148 } 1149 1150 /** 1151 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1152 */ 1153 void __init arch_disable_smp_support(void) 1154 { 1155 disable_ioapic_support(); 1156 } 1157 1158 /* 1159 * Fall back to non SMP mode after errors. 1160 * 1161 * RED-PEN audit/test this more. I bet there is more state messed up here. 1162 */ 1163 static __init void disable_smp(void) 1164 { 1165 pr_info("SMP disabled\n"); 1166 1167 disable_ioapic_support(); 1168 topology_reset_possible_cpus_up(); 1169 1170 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1171 cpumask_set_cpu(0, topology_core_cpumask(0)); 1172 cpumask_set_cpu(0, topology_die_cpumask(0)); 1173 } 1174 1175 void __init smp_prepare_cpus_common(void) 1176 { 1177 unsigned int cpu, node; 1178 1179 /* Mark all except the boot CPU as hotpluggable */ 1180 for_each_possible_cpu(cpu) { 1181 if (cpu) 1182 per_cpu(cpu_info.cpu_index, cpu) = nr_cpu_ids; 1183 } 1184 1185 for_each_possible_cpu(cpu) { 1186 node = cpu_to_node(cpu); 1187 1188 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), GFP_KERNEL, node); 1189 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), GFP_KERNEL, node); 1190 zalloc_cpumask_var_node(&per_cpu(cpu_die_map, cpu), GFP_KERNEL, node); 1191 zalloc_cpumask_var_node(&per_cpu(cpu_llc_shared_map, cpu), GFP_KERNEL, node); 1192 zalloc_cpumask_var_node(&per_cpu(cpu_l2c_shared_map, cpu), GFP_KERNEL, node); 1193 } 1194 1195 set_cpu_sibling_map(0); 1196 } 1197 1198 void __init smp_prepare_boot_cpu(void) 1199 { 1200 smp_ops.smp_prepare_boot_cpu(); 1201 } 1202 1203 #ifdef CONFIG_X86_64 1204 /* Establish whether parallel bringup can be supported. */ 1205 bool __init arch_cpuhp_init_parallel_bringup(void) 1206 { 1207 if (!x86_cpuinit.parallel_bringup) { 1208 pr_info("Parallel CPU startup disabled by the platform\n"); 1209 return false; 1210 } 1211 1212 smpboot_control = STARTUP_READ_APICID; 1213 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1214 return true; 1215 } 1216 #endif 1217 1218 /* 1219 * Prepare for SMP bootup. 1220 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1221 * for common interface support. 1222 */ 1223 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1224 { 1225 smp_prepare_cpus_common(); 1226 1227 switch (apic_intr_mode) { 1228 case APIC_PIC: 1229 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1230 disable_smp(); 1231 return; 1232 case APIC_SYMMETRIC_IO_NO_ROUTING: 1233 disable_smp(); 1234 /* Setup local timer */ 1235 x86_init.timers.setup_percpu_clockev(); 1236 return; 1237 case APIC_VIRTUAL_WIRE: 1238 case APIC_SYMMETRIC_IO: 1239 break; 1240 } 1241 1242 /* Setup local timer */ 1243 x86_init.timers.setup_percpu_clockev(); 1244 1245 pr_info("CPU0: "); 1246 print_cpu_info(&cpu_data(0)); 1247 1248 uv_system_init(); 1249 1250 smp_set_init_udelay(); 1251 1252 speculative_store_bypass_ht_init(); 1253 1254 snp_set_wakeup_secondary_cpu(); 1255 } 1256 1257 void arch_thaw_secondary_cpus_begin(void) 1258 { 1259 set_cache_aps_delayed_init(true); 1260 } 1261 1262 void arch_thaw_secondary_cpus_end(void) 1263 { 1264 cache_aps_init(); 1265 } 1266 1267 /* 1268 * Early setup to make printk work. 1269 */ 1270 void __init native_smp_prepare_boot_cpu(void) 1271 { 1272 int me = smp_processor_id(); 1273 1274 /* SMP handles this from setup_per_cpu_areas() */ 1275 if (!IS_ENABLED(CONFIG_SMP)) 1276 switch_gdt_and_percpu_base(me); 1277 1278 native_pv_lock_init(); 1279 } 1280 1281 void __init native_smp_cpus_done(unsigned int max_cpus) 1282 { 1283 pr_debug("Boot done\n"); 1284 1285 build_sched_topology(); 1286 nmi_selftest(); 1287 impress_friends(); 1288 cache_aps_init(); 1289 } 1290 1291 /* correctly size the local cpu masks */ 1292 void __init setup_cpu_local_masks(void) 1293 { 1294 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1295 } 1296 1297 #ifdef CONFIG_HOTPLUG_CPU 1298 1299 /* Recompute SMT state for all CPUs on offline */ 1300 static void recompute_smt_state(void) 1301 { 1302 int max_threads, cpu; 1303 1304 max_threads = 0; 1305 for_each_online_cpu (cpu) { 1306 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1307 1308 if (threads > max_threads) 1309 max_threads = threads; 1310 } 1311 __max_smt_threads = max_threads; 1312 } 1313 1314 static void remove_siblinginfo(int cpu) 1315 { 1316 int sibling; 1317 struct cpuinfo_x86 *c = &cpu_data(cpu); 1318 1319 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1320 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1321 /*/ 1322 * last thread sibling in this cpu core going down 1323 */ 1324 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1325 cpu_data(sibling).booted_cores--; 1326 } 1327 1328 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1329 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1330 1331 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1332 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1333 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1334 cpu_data(sibling).smt_active = false; 1335 } 1336 1337 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1338 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1339 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1340 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1341 cpumask_clear(cpu_llc_shared_mask(cpu)); 1342 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1343 cpumask_clear(topology_sibling_cpumask(cpu)); 1344 cpumask_clear(topology_core_cpumask(cpu)); 1345 cpumask_clear(topology_die_cpumask(cpu)); 1346 c->topo.core_id = 0; 1347 c->booted_cores = 0; 1348 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1349 recompute_smt_state(); 1350 } 1351 1352 static void remove_cpu_from_maps(int cpu) 1353 { 1354 set_cpu_online(cpu, false); 1355 numa_remove_cpu(cpu); 1356 } 1357 1358 void cpu_disable_common(void) 1359 { 1360 int cpu = smp_processor_id(); 1361 1362 remove_siblinginfo(cpu); 1363 1364 /* 1365 * Stop allowing kernel-mode FPU. This is needed so that if the CPU is 1366 * brought online again, the initial state is not allowed: 1367 */ 1368 this_cpu_write(kernel_fpu_allowed, false); 1369 1370 /* It's now safe to remove this processor from the online map */ 1371 lock_vector_lock(); 1372 remove_cpu_from_maps(cpu); 1373 unlock_vector_lock(); 1374 fixup_irqs(); 1375 lapic_offline(); 1376 } 1377 1378 int native_cpu_disable(void) 1379 { 1380 int ret; 1381 1382 ret = lapic_can_unplug_cpu(); 1383 if (ret) 1384 return ret; 1385 1386 cpu_disable_common(); 1387 1388 /* 1389 * Disable the local APIC. Otherwise IPI broadcasts will reach 1390 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1391 * messages. 1392 * 1393 * Disabling the APIC must happen after cpu_disable_common() 1394 * which invokes fixup_irqs(). 1395 * 1396 * Disabling the APIC preserves already set bits in IRR, but 1397 * an interrupt arriving after disabling the local APIC does not 1398 * set the corresponding IRR bit. 1399 * 1400 * fixup_irqs() scans IRR for set bits so it can raise a not 1401 * yet handled interrupt on the new destination CPU via an IPI 1402 * but obviously it can't do so for IRR bits which are not set. 1403 * IOW, interrupts arriving after disabling the local APIC will 1404 * be lost. 1405 */ 1406 apic_soft_disable(); 1407 1408 return 0; 1409 } 1410 1411 void play_dead_common(void) 1412 { 1413 idle_task_exit(); 1414 1415 cpuhp_ap_report_dead(); 1416 1417 local_irq_disable(); 1418 } 1419 1420 /* 1421 * We need to flush the caches before going to sleep, lest we have 1422 * dirty data in our caches when we come back up. 1423 */ 1424 void __noreturn mwait_play_dead(unsigned int eax_hint) 1425 { 1426 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1427 1428 /* Set up state for the kexec() hack below */ 1429 md->status = CPUDEAD_MWAIT_WAIT; 1430 md->control = CPUDEAD_MWAIT_WAIT; 1431 1432 wbinvd(); 1433 1434 while (1) { 1435 /* 1436 * The CLFLUSH is a workaround for erratum AAI65 for 1437 * the Xeon 7400 series. It's not clear it is actually 1438 * needed, but it should be harmless in either case. 1439 * The WBINVD is insufficient due to the spurious-wakeup 1440 * case where we return around the loop. 1441 */ 1442 mb(); 1443 clflush(md); 1444 mb(); 1445 __monitor(md, 0, 0); 1446 mb(); 1447 __mwait(eax_hint, 0); 1448 1449 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1450 /* 1451 * Kexec is about to happen. Don't go back into mwait() as 1452 * the kexec kernel might overwrite text and data including 1453 * page tables and stack. So mwait() would resume when the 1454 * monitor cache line is written to and then the CPU goes 1455 * south due to overwritten text, page tables and stack. 1456 * 1457 * Note: This does _NOT_ protect against a stray MCE, NMI, 1458 * SMI. They will resume execution at the instruction 1459 * following the HLT instruction and run into the problem 1460 * which this is trying to prevent. 1461 */ 1462 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1463 while(1) 1464 native_halt(); 1465 } 1466 } 1467 } 1468 1469 /* 1470 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1471 * mwait_play_dead(). 1472 */ 1473 void smp_kick_mwait_play_dead(void) 1474 { 1475 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1476 struct mwait_cpu_dead *md; 1477 unsigned int cpu, i; 1478 1479 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1480 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1481 1482 /* Does it sit in mwait_play_dead() ? */ 1483 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1484 continue; 1485 1486 /* Wait up to 5ms */ 1487 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1488 /* Bring it out of mwait */ 1489 WRITE_ONCE(md->control, newstate); 1490 udelay(5); 1491 } 1492 1493 if (READ_ONCE(md->status) != newstate) 1494 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1495 } 1496 } 1497 1498 void __noreturn hlt_play_dead(void) 1499 { 1500 if (__this_cpu_read(cpu_info.x86) >= 4) 1501 wbinvd(); 1502 1503 while (1) 1504 native_halt(); 1505 } 1506 1507 void __noreturn native_play_dead(void) 1508 { 1509 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 1510 __update_spec_ctrl(0); 1511 1512 play_dead_common(); 1513 tboot_shutdown(TB_SHUTDOWN_WFS); 1514 1515 /* Below returns only on error. */ 1516 cpuidle_play_dead(); 1517 hlt_play_dead(); 1518 } 1519 1520 #else /* ... !CONFIG_HOTPLUG_CPU */ 1521 int native_cpu_disable(void) 1522 { 1523 return -ENOSYS; 1524 } 1525 1526 void __noreturn native_play_dead(void) 1527 { 1528 BUG(); 1529 } 1530 1531 #endif 1532