1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_damage_helper.h> 28 #include <drm/drm_debugfs.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_vblank.h> 31 32 #include "intel_alpm.h" 33 #include "intel_atomic.h" 34 #include "intel_crtc.h" 35 #include "intel_cursor_regs.h" 36 #include "intel_ddi.h" 37 #include "intel_de.h" 38 #include "intel_display_irq.h" 39 #include "intel_display_regs.h" 40 #include "intel_display_rpm.h" 41 #include "intel_display_types.h" 42 #include "intel_display_utils.h" 43 #include "intel_display_wa.h" 44 #include "intel_dmc.h" 45 #include "intel_dp.h" 46 #include "intel_dpcd.h" 47 #include "intel_dp_aux.h" 48 #include "intel_dsb.h" 49 #include "intel_frontbuffer.h" 50 #include "intel_hdmi.h" 51 #include "intel_psr.h" 52 #include "intel_psr_regs.h" 53 #include "intel_quirks.h" 54 #include "intel_snps_phy.h" 55 #include "intel_step.h" 56 #include "intel_vblank.h" 57 #include "intel_vdsc.h" 58 #include "intel_vrr.h" 59 #include "skl_universal_plane.h" 60 61 /** 62 * DOC: Panel Self Refresh (PSR/SRD) 63 * 64 * Since Haswell Display controller supports Panel Self-Refresh on display 65 * panels witch have a remote frame buffer (RFB) implemented according to PSR 66 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 67 * when system is idle but display is on as it eliminates display refresh 68 * request to DDR memory completely as long as the frame buffer for that 69 * display is unchanged. 70 * 71 * Panel Self Refresh must be supported by both Hardware (source) and 72 * Panel (sink). 73 * 74 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 75 * to power down the link and memory controller. For DSI panels the same idea 76 * is called "manual mode". 77 * 78 * The implementation uses the hardware-based PSR support which automatically 79 * enters/exits self-refresh mode. The hardware takes care of sending the 80 * required DP aux message and could even retrain the link (that part isn't 81 * enabled yet though). The hardware also keeps track of any frontbuffer 82 * changes to know when to exit self-refresh mode again. Unfortunately that 83 * part doesn't work too well, hence why the i915 PSR support uses the 84 * software frontbuffer tracking to make sure it doesn't miss a screen 85 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 86 * get called by the frontbuffer tracking code. Note that because of locking 87 * issues the self-refresh re-enable code is done from a work queue, which 88 * must be correctly synchronized/cancelled when shutting down the pipe." 89 * 90 * DC3CO (DC3 clock off) 91 * 92 * On top of PSR2, GEN12 adds a intermediate power savings state that turns 93 * clock off automatically during PSR2 idle state. 94 * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep 95 * entry/exit allows the HW to enter a low-power state even when page flipping 96 * periodically (for instance a 30fps video playback scenario). 97 * 98 * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), 99 * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 100 * frames, if no other flip occurs and the function above is executed, DC3CO is 101 * disabled and PSR2 is configured to enter deep sleep, resetting again in case 102 * of another flip. 103 * Front buffer modifications do not trigger DC3CO activation on purpose as it 104 * would bring a lot of complexity and most of the moderns systems will only 105 * use page flips. 106 */ 107 108 /* 109 * Description of PSR mask bits: 110 * 111 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl): 112 * 113 * When unmasked (nearly) all display register writes (eg. even 114 * SWF) trigger a PSR exit. Some registers are excluded from this 115 * and they have a more specific mask (described below). On icl+ 116 * this bit no longer exists and is effectively always set. 117 * 118 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+): 119 * 120 * When unmasked (nearly) all pipe/plane register writes 121 * trigger a PSR exit. Some plane registers are excluded from this 122 * and they have a more specific mask (described below). 123 * 124 * CHICKEN_PIPESL_1[11]/SKL_PSR_MASK_PLANE_FLIP (skl+): 125 * PIPE_MISC[23]/PIPE_MISC_PSR_MASK_PRIMARY_FLIP (bdw): 126 * EDP_PSR_DEBUG[23]/EDP_PSR_DEBUG_MASK_PRIMARY_FLIP (hsw): 127 * 128 * When unmasked PRI_SURF/PLANE_SURF writes trigger a PSR exit. 129 * SPR_SURF/CURBASE are not included in this and instead are 130 * controlled by PIPE_MISC_PSR_MASK_PIPE_REG_WRITE (skl+) or 131 * EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw/bdw). 132 * 133 * PIPE_MISC[22]/PIPE_MISC_PSR_MASK_SPRITE_ENABLE (bdw): 134 * EDP_PSR_DEBUG[21]/EDP_PSR_DEBUG_MASK_SPRITE_ENABLE (hsw): 135 * 136 * When unmasked PSR is blocked as long as the sprite 137 * plane is enabled. skl+ with their universal planes no 138 * longer have a mask bit like this, and no plane being 139 * enabledb blocks PSR. 140 * 141 * PIPE_MISC[21]/PIPE_MISC_PSR_MASK_CURSOR_MOVE (bdw): 142 * EDP_PSR_DEBUG[20]/EDP_PSR_DEBUG_MASK_CURSOR_MOVE (hsw): 143 * 144 * When umasked CURPOS writes trigger a PSR exit. On skl+ 145 * this doesn't exit but CURPOS is included in the 146 * PIPE_MISC_PSR_MASK_PIPE_REG_WRITE mask. 147 * 148 * PIPE_MISC[20]/PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT (bdw+): 149 * EDP_PSR_DEBUG[19]/EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT (hsw): 150 * 151 * When unmasked PSR is blocked as long as vblank and/or vsync 152 * interrupt is unmasked in IMR *and* enabled in IER. 153 * 154 * CHICKEN_TRANS[30]/SKL_UNMASK_VBL_TO_PIPE_IN_SRD (skl+): 155 * CHICKEN_PAR1_1[15]/HSW_MASK_VBL_TO_PIPE_IN_SRD (hsw/bdw): 156 * 157 * Selectcs whether PSR exit generates an extra vblank before 158 * the first frame is transmitted. Also note the opposite polarity 159 * if the bit on hsw/bdw vs. skl+ (masked==generate the extra vblank, 160 * unmasked==do not generate the extra vblank). 161 * 162 * With DC states enabled the extra vblank happens after link training, 163 * with DC states disabled it happens immediately upuon PSR exit trigger. 164 * No idea as of now why there is a difference. HSW/BDW (which don't 165 * even have DMC) always generate it after link training. Go figure. 166 * 167 * Unfortunately CHICKEN_TRANS itself seems to be double buffered 168 * and thus won't latch until the first vblank. So with DC states 169 * enabled the register effectively uses the reset value during DC5 170 * exit+PSR exit sequence, and thus the bit does nothing until 171 * latched by the vblank that it was trying to prevent from being 172 * generated in the first place. So we should probably call this 173 * one a chicken/egg bit instead on skl+. 174 * 175 * In standby mode (as opposed to link-off) this makes no difference 176 * as the timing generator keeps running the whole time generating 177 * normal periodic vblanks. 178 * 179 * WaPsrDPAMaskVBlankInSRD asks us to set the bit on hsw/bdw, 180 * and doing so makes the behaviour match the skl+ reset value. 181 * 182 * CHICKEN_PIPESL_1[0]/BDW_UNMASK_VBL_TO_REGS_IN_SRD (bdw): 183 * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): 184 * 185 * On BDW without this bit is no vblanks whatsoever are 186 * generated after PSR exit. On HSW this has no apparent effect. 187 * WaPsrDPRSUnmaskVBlankInSRD says to set this. 188 * 189 * The rest of the bits are more self-explanatory and/or 190 * irrelevant for normal operation. 191 * 192 * Description of intel_crtc_state variables. has_psr, has_panel_replay and 193 * has_sel_update: 194 * 195 * has_psr (alone): PSR1 196 * has_psr + has_sel_update: PSR2 197 * has_psr + has_panel_replay: Panel Replay 198 * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update 199 * 200 * Description of some intel_psr variables. enabled, panel_replay_enabled, 201 * sel_update_enabled 202 * 203 * enabled (alone): PSR1 204 * enabled + sel_update_enabled: PSR2 205 * enabled + panel_replay_enabled: Panel Replay 206 * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay SU 207 */ 208 209 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ 210 (intel_dp)->psr.source_support) 211 212 bool intel_encoder_can_psr(struct intel_encoder *encoder) 213 { 214 if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST) 215 return CAN_PSR(enc_to_intel_dp(encoder)) || 216 CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); 217 else 218 return false; 219 } 220 221 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, 222 const struct intel_crtc_state *crtc_state) 223 { 224 /* 225 * For PSR/PR modes only eDP requires the AUX IO power to be enabled whenever 226 * the output is enabled. For non-eDP outputs the main link is always 227 * on, hence it doesn't require the HW initiated AUX wake-up signaling used 228 * for eDP. 229 * 230 * TODO: 231 * - Consider leaving AUX IO disabled for eDP / PR as well, in case 232 * the ALPM with main-link off mode is not enabled. 233 * - Leave AUX IO enabled for DP / PR, once support for ALPM with 234 * main-link off mode is added for it and this mode gets enabled. 235 */ 236 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) && 237 intel_encoder_can_psr(encoder); 238 } 239 240 static bool psr_global_enabled(struct intel_dp *intel_dp) 241 { 242 struct intel_connector *connector = intel_dp->attached_connector; 243 244 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 245 case I915_PSR_DEBUG_DEFAULT: 246 return intel_dp_is_edp(intel_dp) ? 247 connector->panel.vbt.psr.enable : true; 248 case I915_PSR_DEBUG_DISABLE: 249 return false; 250 default: 251 return true; 252 } 253 } 254 255 static bool sel_update_global_enabled(struct intel_dp *intel_dp) 256 { 257 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { 258 case I915_PSR_DEBUG_DISABLE: 259 case I915_PSR_DEBUG_FORCE_PSR1: 260 return false; 261 default: 262 return true; 263 } 264 } 265 266 static bool panel_replay_global_enabled(struct intel_dp *intel_dp) 267 { 268 struct intel_display *display = to_intel_display(intel_dp); 269 270 return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) && 271 display->params.enable_panel_replay; 272 } 273 274 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) 275 { 276 struct intel_display *display = to_intel_display(intel_dp); 277 278 return DISPLAY_VER(display) >= 12 ? TGL_PSR_ERROR : 279 EDP_PSR_ERROR(intel_dp->psr.transcoder); 280 } 281 282 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp) 283 { 284 struct intel_display *display = to_intel_display(intel_dp); 285 286 return DISPLAY_VER(display) >= 12 ? TGL_PSR_POST_EXIT : 287 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); 288 } 289 290 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp) 291 { 292 struct intel_display *display = to_intel_display(intel_dp); 293 294 return DISPLAY_VER(display) >= 12 ? TGL_PSR_PRE_ENTRY : 295 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); 296 } 297 298 static u32 psr_irq_mask_get(struct intel_dp *intel_dp) 299 { 300 struct intel_display *display = to_intel_display(intel_dp); 301 302 return DISPLAY_VER(display) >= 12 ? TGL_PSR_MASK : 303 EDP_PSR_MASK(intel_dp->psr.transcoder); 304 } 305 306 static i915_reg_t psr_ctl_reg(struct intel_display *display, 307 enum transcoder cpu_transcoder) 308 { 309 if (DISPLAY_VER(display) >= 8) 310 return EDP_PSR_CTL(display, cpu_transcoder); 311 else 312 return HSW_SRD_CTL; 313 } 314 315 static i915_reg_t psr_debug_reg(struct intel_display *display, 316 enum transcoder cpu_transcoder) 317 { 318 if (DISPLAY_VER(display) >= 8) 319 return EDP_PSR_DEBUG(display, cpu_transcoder); 320 else 321 return HSW_SRD_DEBUG; 322 } 323 324 static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, 325 enum transcoder cpu_transcoder) 326 { 327 if (DISPLAY_VER(display) >= 8) 328 return EDP_PSR_PERF_CNT(display, cpu_transcoder); 329 else 330 return HSW_SRD_PERF_CNT; 331 } 332 333 static i915_reg_t psr_status_reg(struct intel_display *display, 334 enum transcoder cpu_transcoder) 335 { 336 if (DISPLAY_VER(display) >= 8) 337 return EDP_PSR_STATUS(display, cpu_transcoder); 338 else 339 return HSW_SRD_STATUS; 340 } 341 342 static i915_reg_t psr_imr_reg(struct intel_display *display, 343 enum transcoder cpu_transcoder) 344 { 345 if (DISPLAY_VER(display) >= 12) 346 return TRANS_PSR_IMR(display, cpu_transcoder); 347 else 348 return EDP_PSR_IMR; 349 } 350 351 static i915_reg_t psr_iir_reg(struct intel_display *display, 352 enum transcoder cpu_transcoder) 353 { 354 if (DISPLAY_VER(display) >= 12) 355 return TRANS_PSR_IIR(display, cpu_transcoder); 356 else 357 return EDP_PSR_IIR; 358 } 359 360 static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, 361 enum transcoder cpu_transcoder) 362 { 363 if (DISPLAY_VER(display) >= 8) 364 return EDP_PSR_AUX_CTL(display, cpu_transcoder); 365 else 366 return HSW_SRD_AUX_CTL; 367 } 368 369 static i915_reg_t psr_aux_data_reg(struct intel_display *display, 370 enum transcoder cpu_transcoder, int i) 371 { 372 if (DISPLAY_VER(display) >= 8) 373 return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); 374 else 375 return HSW_SRD_AUX_DATA(i); 376 } 377 378 static void psr_irq_control(struct intel_dp *intel_dp) 379 { 380 struct intel_display *display = to_intel_display(intel_dp); 381 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 382 u32 mask; 383 384 if (intel_dp->psr.panel_replay_enabled) 385 return; 386 387 mask = psr_irq_psr_error_bit_get(intel_dp); 388 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) 389 mask |= psr_irq_post_exit_bit_get(intel_dp) | 390 psr_irq_pre_entry_bit_get(intel_dp); 391 392 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 393 psr_irq_mask_get(intel_dp), ~mask); 394 } 395 396 static void psr_event_print(struct intel_display *display, 397 u32 val, bool sel_update_enabled) 398 { 399 drm_dbg_kms(display->drm, "PSR exit events: 0x%x\n", val); 400 if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) 401 drm_dbg_kms(display->drm, "\tPSR2 watchdog timer expired\n"); 402 if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) 403 drm_dbg_kms(display->drm, "\tPSR2 disabled\n"); 404 if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) 405 drm_dbg_kms(display->drm, "\tSU dirty FIFO underrun\n"); 406 if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN) 407 drm_dbg_kms(display->drm, "\tSU CRC FIFO underrun\n"); 408 if (val & PSR_EVENT_GRAPHICS_RESET) 409 drm_dbg_kms(display->drm, "\tGraphics reset\n"); 410 if (val & PSR_EVENT_PCH_INTERRUPT) 411 drm_dbg_kms(display->drm, "\tPCH interrupt\n"); 412 if (val & PSR_EVENT_MEMORY_UP) 413 drm_dbg_kms(display->drm, "\tMemory up\n"); 414 if (val & PSR_EVENT_FRONT_BUFFER_MODIFY) 415 drm_dbg_kms(display->drm, "\tFront buffer modification\n"); 416 if (val & PSR_EVENT_WD_TIMER_EXPIRE) 417 drm_dbg_kms(display->drm, "\tPSR watchdog timer expired\n"); 418 if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE) 419 drm_dbg_kms(display->drm, "\tPIPE registers updated\n"); 420 if (val & PSR_EVENT_REGISTER_UPDATE) 421 drm_dbg_kms(display->drm, "\tRegister updated\n"); 422 if (val & PSR_EVENT_HDCP_ENABLE) 423 drm_dbg_kms(display->drm, "\tHDCP enabled\n"); 424 if (val & PSR_EVENT_KVMR_SESSION_ENABLE) 425 drm_dbg_kms(display->drm, "\tKVMR session enabled\n"); 426 if (val & PSR_EVENT_VBI_ENABLE) 427 drm_dbg_kms(display->drm, "\tVBI enabled\n"); 428 if (val & PSR_EVENT_LPSP_MODE_EXIT) 429 drm_dbg_kms(display->drm, "\tLPSP mode exited\n"); 430 if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) 431 drm_dbg_kms(display->drm, "\tPSR disabled\n"); 432 } 433 434 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) 435 { 436 struct intel_display *display = to_intel_display(intel_dp); 437 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 438 ktime_t time_ns = ktime_get(); 439 440 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { 441 intel_dp->psr.last_entry_attempt = time_ns; 442 drm_dbg_kms(display->drm, 443 "[transcoder %s] PSR entry attempt in 2 vblanks\n", 444 transcoder_name(cpu_transcoder)); 445 } 446 447 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) { 448 intel_dp->psr.last_exit = time_ns; 449 drm_dbg_kms(display->drm, 450 "[transcoder %s] PSR exit completed\n", 451 transcoder_name(cpu_transcoder)); 452 453 if (DISPLAY_VER(display) >= 9) { 454 u32 val; 455 456 val = intel_de_rmw(display, 457 PSR_EVENT(display, cpu_transcoder), 458 0, 0); 459 460 psr_event_print(display, val, intel_dp->psr.sel_update_enabled); 461 } 462 } 463 464 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) { 465 drm_warn(display->drm, "[transcoder %s] PSR aux error\n", 466 transcoder_name(cpu_transcoder)); 467 468 intel_dp->psr.irq_aux_error = true; 469 470 /* 471 * If this interruption is not masked it will keep 472 * interrupting so fast that it prevents the scheduled 473 * work to run. 474 * Also after a PSR error, we don't want to arm PSR 475 * again so we don't care about unmask the interruption 476 * or unset irq_aux_error. 477 */ 478 intel_de_rmw(display, psr_imr_reg(display, cpu_transcoder), 479 0, psr_irq_psr_error_bit_get(intel_dp)); 480 481 queue_work(display->wq.unordered, &intel_dp->psr.work); 482 } 483 } 484 485 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) 486 { 487 struct intel_display *display = to_intel_display(intel_dp); 488 u8 val = 8; /* assume the worst if we can't read the value */ 489 490 if (drm_dp_dpcd_readb(&intel_dp->aux, 491 DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1) 492 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 493 else 494 drm_dbg_kms(display->drm, 495 "Unable to get sink synchronization latency, assuming 8 frames\n"); 496 return val; 497 } 498 499 static void _psr_compute_su_granularity(struct intel_dp *intel_dp, 500 struct intel_connector *connector) 501 { 502 struct intel_display *display = to_intel_display(intel_dp); 503 ssize_t r; 504 __le16 w; 505 u8 y; 506 507 /* 508 * If sink don't have specific granularity requirements set legacy 509 * ones. 510 */ 511 if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 512 /* As PSR2 HW sends full lines, we do not care about x granularity */ 513 w = cpu_to_le16(4); 514 y = 4; 515 goto exit; 516 } 517 518 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w)); 519 if (r != sizeof(w)) 520 drm_dbg_kms(display->drm, 521 "Unable to read selective update x granularity\n"); 522 /* 523 * Spec says that if the value read is 0 the default granularity should 524 * be used instead. 525 */ 526 if (r != sizeof(w) || w == 0) 527 w = cpu_to_le16(4); 528 529 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 530 if (r != 1) { 531 drm_dbg_kms(display->drm, 532 "Unable to read selective update y granularity\n"); 533 y = 4; 534 } 535 if (y == 0) 536 y = 1; 537 538 exit: 539 connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w); 540 connector->dp.psr_caps.su_y_granularity = y; 541 } 542 543 static enum intel_panel_replay_dsc_support 544 compute_pr_dsc_support(struct intel_connector *connector) 545 { 546 u8 pr_dsc_mode; 547 u8 val; 548 549 val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 550 pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); 551 552 switch (pr_dsc_mode) { 553 case DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY: 554 return INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY; 555 case DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED: 556 return INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE; 557 default: 558 MISSING_CASE(pr_dsc_mode); 559 fallthrough; 560 case DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED: 561 case DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED: 562 return INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 563 } 564 } 565 566 static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_support dsc_support) 567 { 568 switch (dsc_support) { 569 case INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED: 570 return "not supported"; 571 case INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY: 572 return "full frame only"; 573 case INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE: 574 return "selective update"; 575 default: 576 MISSING_CASE(dsc_support); 577 return "n/a"; 578 }; 579 } 580 581 static void _panel_replay_compute_su_granularity(struct intel_connector *connector) 582 { 583 u16 w; 584 u8 y; 585 586 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 587 DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) { 588 w = 4; 589 y = 4; 590 goto exit; 591 } 592 593 /* 594 * Spec says that if the value read is 0 the default granularity should 595 * be used instead. 596 */ 597 w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4; 598 y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1; 599 600 exit: 601 connector->dp.panel_replay_caps.su_w_granularity = w; 602 connector->dp.panel_replay_caps.su_y_granularity = y; 603 } 604 605 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 606 { 607 struct intel_display *display = to_intel_display(intel_dp); 608 int ret; 609 610 /* TODO: Enable Panel Replay on MST once it's properly implemented. */ 611 if (intel_dp->mst_detect == DRM_DP_MST) 612 return; 613 614 if (intel_dp_is_edp(intel_dp) && 615 intel_has_dpcd_quirk(intel_dp, QUIRK_DISABLE_EDP_PANEL_REPLAY)) { 616 drm_dbg_kms(display->drm, 617 "Panel Replay support not currently available for this setup\n"); 618 return; 619 } 620 621 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 622 &connector->dp.panel_replay_caps.dpcd, 623 sizeof(connector->dp.panel_replay_caps.dpcd)); 624 if (ret < 0) 625 return; 626 627 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 628 DP_PANEL_REPLAY_SUPPORT)) 629 return; 630 631 if (intel_dp_is_edp(intel_dp)) { 632 if (!intel_alpm_aux_less_wake_supported(intel_dp)) { 633 drm_dbg_kms(display->drm, 634 "Panel doesn't support AUX-less ALPM, eDP Panel Replay not possible\n"); 635 return; 636 } 637 638 if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 639 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { 640 drm_dbg_kms(display->drm, 641 "Panel doesn't support early transport, eDP Panel Replay not possible\n"); 642 return; 643 } 644 } 645 646 connector->dp.panel_replay_caps.support = true; 647 intel_dp->psr.sink_panel_replay_support = true; 648 649 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 650 DP_PANEL_REPLAY_SU_SUPPORT) { 651 connector->dp.panel_replay_caps.su_support = true; 652 653 _panel_replay_compute_su_granularity(connector); 654 } 655 656 connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector); 657 658 drm_dbg_kms(display->drm, 659 "Panel replay %sis supported by panel (in DSC mode: %s)\n", 660 connector->dp.panel_replay_caps.su_support ? 661 "selective_update " : "", 662 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 663 } 664 665 static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 666 { 667 struct intel_display *display = to_intel_display(intel_dp); 668 int ret; 669 670 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd, 671 sizeof(connector->dp.psr_caps.dpcd)); 672 if (ret < 0) 673 return; 674 675 if (!connector->dp.psr_caps.dpcd[0]) 676 return; 677 678 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", 679 connector->dp.psr_caps.dpcd[0]); 680 681 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 682 drm_dbg_kms(display->drm, 683 "PSR support not currently available for this panel\n"); 684 return; 685 } 686 687 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { 688 drm_dbg_kms(display->drm, 689 "Panel lacks power state control, PSR cannot be enabled\n"); 690 return; 691 } 692 693 connector->dp.psr_caps.support = true; 694 intel_dp->psr.sink_support = true; 695 696 connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); 697 698 if (DISPLAY_VER(display) >= 9 && 699 connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 700 bool y_req = connector->dp.psr_caps.dpcd[1] & 701 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 702 703 /* 704 * All panels that supports PSR version 03h (PSR2 + 705 * Y-coordinate) can handle Y-coordinates in VSC but we are 706 * only sure that it is going to be used when required by the 707 * panel. This way panel is capable to do selective update 708 * without a aux frame sync. 709 * 710 * To support PSR version 02h and PSR version 03h without 711 * Y-coordinate requirement panels we would need to enable 712 * GTC first. 713 */ 714 connector->dp.psr_caps.su_support = y_req && 715 intel_alpm_aux_wake_supported(intel_dp); 716 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", 717 connector->dp.psr_caps.su_support ? "" : "not "); 718 } 719 720 if (connector->dp.psr_caps.su_support) { 721 ret = drm_dp_dpcd_read_byte(&intel_dp->aux, 722 INTEL_DPCD_INTEL_WA_REGISTER_CAPS, 723 &connector->dp.psr_caps.intel_wa_dpcd); 724 if (ret < 0) 725 return; 726 _psr_compute_su_granularity(intel_dp, connector); 727 } 728 } 729 730 void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 731 { 732 _psr_init_dpcd(intel_dp, connector); 733 734 _panel_replay_init_dpcd(intel_dp, connector); 735 } 736 737 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) 738 { 739 struct intel_display *display = to_intel_display(intel_dp); 740 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 741 u32 aux_clock_divider, aux_ctl; 742 /* write DP_SET_POWER=D0 */ 743 static const u8 aux_msg[] = { 744 [0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf), 745 [1] = (DP_SET_POWER >> 8) & 0xff, 746 [2] = DP_SET_POWER & 0xff, 747 [3] = 1 - 1, 748 [4] = DP_SET_POWER_D0, 749 }; 750 int i; 751 752 BUILD_BUG_ON(sizeof(aux_msg) > 20); 753 for (i = 0; i < sizeof(aux_msg); i += 4) 754 intel_de_write(display, 755 psr_aux_data_reg(display, cpu_transcoder, i >> 2), 756 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); 757 758 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 759 760 /* Start with bits set for DDI_AUX_CTL register */ 761 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), 762 aux_clock_divider); 763 764 /* Select only valid bits for SRD_AUX_CTL */ 765 aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK | 766 EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | 767 EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | 768 EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; 769 770 intel_de_write(display, psr_aux_ctl_reg(display, cpu_transcoder), 771 aux_ctl); 772 } 773 774 static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay) 775 { 776 struct intel_dp *intel_dp = intel_attached_dp(connector); 777 struct intel_display *display = to_intel_display(intel_dp); 778 779 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || 780 intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) 781 return false; 782 783 return panel_replay ? 784 connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 785 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : 786 connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 787 } 788 789 static void _panel_replay_enable_sink(struct intel_dp *intel_dp, 790 const struct intel_crtc_state *crtc_state) 791 { 792 u8 val = DP_PANEL_REPLAY_ENABLE | 793 DP_PANEL_REPLAY_VSC_SDP_CRC_EN | 794 DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | 795 DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | 796 DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; 797 u8 panel_replay_config2 = DP_PANEL_REPLAY_CRC_VERIFICATION; 798 799 if (crtc_state->has_sel_update) 800 val |= DP_PANEL_REPLAY_SU_ENABLE; 801 802 if (crtc_state->enable_psr2_su_region_et) 803 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 804 805 if (crtc_state->req_psr2_sdp_prior_scanline) 806 panel_replay_config2 |= 807 DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE; 808 809 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); 810 811 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG2, 812 panel_replay_config2); 813 } 814 815 static void _psr_enable_sink(struct intel_dp *intel_dp, 816 const struct intel_crtc_state *crtc_state) 817 { 818 struct intel_display *display = to_intel_display(intel_dp); 819 u8 val = 0; 820 821 if (crtc_state->has_sel_update) { 822 val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; 823 } else { 824 if (intel_dp->psr.link_standby) 825 val |= DP_PSR_MAIN_LINK_ACTIVE; 826 827 if (DISPLAY_VER(display) >= 8) 828 val |= DP_PSR_CRC_VERIFICATION; 829 } 830 831 if (crtc_state->req_psr2_sdp_prior_scanline) 832 val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; 833 834 if (crtc_state->enable_psr2_su_region_et) 835 val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; 836 837 if (intel_dp->psr.entry_setup_frames > 0) 838 val |= DP_PSR_FRAME_CAPTURE; 839 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 840 841 val |= DP_PSR_ENABLE; 842 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); 843 } 844 845 static void intel_psr_enable_sink(struct intel_dp *intel_dp, 846 const struct intel_crtc_state *crtc_state) 847 { 848 intel_alpm_enable_sink(intel_dp, crtc_state); 849 850 crtc_state->has_panel_replay ? 851 _panel_replay_enable_sink(intel_dp, crtc_state) : 852 _psr_enable_sink(intel_dp, crtc_state); 853 854 if (intel_dp_is_edp(intel_dp)) 855 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 856 } 857 858 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) 859 { 860 /* 861 * NOTE: We might want to trigger mode set when 862 * disabling/enabling Panel Replay via debugfs interface to 863 * ensure this bit is cleared/set accordingly. 864 */ 865 if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp)) 866 drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, 867 DP_PANEL_REPLAY_ENABLE); 868 } 869 870 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) 871 { 872 struct intel_display *display = to_intel_display(intel_dp); 873 struct intel_connector *connector = intel_dp->attached_connector; 874 u32 val = 0; 875 876 if (DISPLAY_VER(display) >= 11) 877 val |= EDP_PSR_TP4_TIME_0us; 878 879 if (display->params.psr_safest_params) { 880 val |= EDP_PSR_TP1_TIME_2500us; 881 val |= EDP_PSR_TP2_TP3_TIME_2500us; 882 goto check_tp3_sel; 883 } 884 885 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) 886 val |= EDP_PSR_TP1_TIME_0us; 887 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) 888 val |= EDP_PSR_TP1_TIME_100us; 889 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) 890 val |= EDP_PSR_TP1_TIME_500us; 891 else 892 val |= EDP_PSR_TP1_TIME_2500us; 893 894 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 895 val |= EDP_PSR_TP2_TP3_TIME_0us; 896 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) 897 val |= EDP_PSR_TP2_TP3_TIME_100us; 898 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) 899 val |= EDP_PSR_TP2_TP3_TIME_500us; 900 else 901 val |= EDP_PSR_TP2_TP3_TIME_2500us; 902 903 /* 904 * WA 0479: hsw,bdw 905 * "Do not skip both TP1 and TP2/TP3" 906 */ 907 if (DISPLAY_VER(display) < 9 && 908 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && 909 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) 910 val |= EDP_PSR_TP2_TP3_TIME_100us; 911 912 check_tp3_sel: 913 if (intel_dp_source_supports_tps3(display) && 914 drm_dp_tps3_supported(intel_dp->dpcd)) 915 val |= EDP_PSR_TP_TP1_TP3; 916 else 917 val |= EDP_PSR_TP_TP1_TP2; 918 919 return val; 920 } 921 922 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) 923 { 924 struct intel_display *display = to_intel_display(intel_dp); 925 struct intel_connector *connector = intel_dp->attached_connector; 926 int idle_frames; 927 928 /* Let's use 6 as the minimum to cover all known cases including the 929 * off-by-one issue that HW has in some cases. 930 */ 931 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 932 idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1); 933 934 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) 935 idle_frames = 0xf; 936 937 return idle_frames; 938 } 939 940 static bool is_dc5_dc6_blocked(struct intel_dp *intel_dp) 941 { 942 struct intel_display *display = to_intel_display(intel_dp); 943 u32 current_dc_state = intel_display_power_get_current_dc_state(display); 944 struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe); 945 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 946 947 return (current_dc_state != DC_STATE_EN_UPTO_DC5 && 948 current_dc_state != DC_STATE_EN_UPTO_DC6) || 949 intel_dp->psr.active_non_psr_pipes || 950 READ_ONCE(vblank->enabled); 951 } 952 953 static void hsw_activate_psr1(struct intel_dp *intel_dp) 954 { 955 struct intel_display *display = to_intel_display(intel_dp); 956 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 957 u32 max_sleep_time = 0x1f; 958 u32 val = EDP_PSR_ENABLE; 959 960 val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); 961 962 if (DISPLAY_VER(display) < 20) 963 val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); 964 965 if (display->platform.haswell) 966 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 967 968 if (intel_dp->psr.link_standby) 969 val |= EDP_PSR_LINK_STANDBY; 970 971 val |= intel_psr1_get_tp_time(intel_dp); 972 973 if (DISPLAY_VER(display) >= 8) 974 val |= EDP_PSR_CRC_ENABLE; 975 976 if (DISPLAY_VER(display) >= 20) 977 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 978 979 intel_de_rmw(display, psr_ctl_reg(display, cpu_transcoder), 980 ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); 981 982 /* Wa_16025596647 */ 983 if ((DISPLAY_VER(display) == 20 || 984 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 985 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 986 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 987 intel_dp->psr.pipe, 988 true); 989 } 990 991 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) 992 { 993 struct intel_display *display = to_intel_display(intel_dp); 994 struct intel_connector *connector = intel_dp->attached_connector; 995 u32 val = 0; 996 997 if (display->params.psr_safest_params) 998 return EDP_PSR2_TP2_TIME_2500us; 999 1000 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && 1001 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) 1002 val |= EDP_PSR2_TP2_TIME_50us; 1003 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) 1004 val |= EDP_PSR2_TP2_TIME_100us; 1005 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) 1006 val |= EDP_PSR2_TP2_TIME_500us; 1007 else 1008 val |= EDP_PSR2_TP2_TIME_2500us; 1009 1010 return val; 1011 } 1012 1013 static int 1014 psr2_block_count_lines(u8 io_wake_lines, u8 fast_wake_lines) 1015 { 1016 return io_wake_lines < 9 && fast_wake_lines < 9 ? 8 : 12; 1017 } 1018 1019 static int psr2_block_count(struct intel_dp *intel_dp) 1020 { 1021 return psr2_block_count_lines(intel_dp->psr.io_wake_lines, 1022 intel_dp->psr.fast_wake_lines) / 4; 1023 } 1024 1025 static u8 frames_before_su_entry(struct intel_dp *intel_dp) 1026 { 1027 struct intel_connector *connector = intel_dp->attached_connector; 1028 u8 frames_before_su_entry; 1029 1030 frames_before_su_entry = max_t(u8, 1031 connector->dp.psr_caps.sync_latency + 1, 1032 2); 1033 1034 /* Entry setup frames must be at least 1 less than frames before SU entry */ 1035 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) 1036 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; 1037 1038 return frames_before_su_entry; 1039 } 1040 1041 static void dg2_activate_panel_replay(struct intel_dp *intel_dp) 1042 { 1043 struct intel_display *display = to_intel_display(intel_dp); 1044 struct intel_psr *psr = &intel_dp->psr; 1045 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1046 1047 if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { 1048 u32 val = psr->su_region_et_enabled ? 1049 LNL_EDP_PSR2_SU_REGION_ET_ENABLE : 0; 1050 1051 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1052 val |= EDP_PSR2_SU_SDP_SCANLINE; 1053 1054 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), 1055 val); 1056 } 1057 1058 intel_de_rmw(display, 1059 PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 1060 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); 1061 1062 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, 1063 TRANS_DP2_PANEL_REPLAY_ENABLE); 1064 } 1065 1066 static void hsw_activate_psr2(struct intel_dp *intel_dp) 1067 { 1068 struct intel_display *display = to_intel_display(intel_dp); 1069 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1070 u32 val = EDP_PSR2_ENABLE; 1071 u32 psr_val = 0; 1072 u8 idle_frames; 1073 1074 /* Wa_16025596647 */ 1075 if ((DISPLAY_VER(display) == 20 || 1076 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 1077 is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used) 1078 idle_frames = 0; 1079 else 1080 idle_frames = psr_compute_idle_frames(intel_dp); 1081 val |= EDP_PSR2_IDLE_FRAMES(idle_frames); 1082 1083 if (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p) 1084 val |= EDP_SU_TRACK_ENABLE; 1085 1086 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) 1087 val |= EDP_Y_COORDINATE_ENABLE; 1088 1089 val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp)); 1090 1091 val |= intel_psr2_get_tp_time(intel_dp); 1092 1093 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { 1094 if (psr2_block_count(intel_dp) > 2) 1095 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; 1096 else 1097 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; 1098 } 1099 1100 /* Wa_22012278275:adl-p */ 1101 if (intel_display_wa(display, INTEL_DISPLAY_WA_22012278275)) { 1102 static const u8 map[] = { 1103 2, /* 5 lines */ 1104 1, /* 6 lines */ 1105 0, /* 7 lines */ 1106 3, /* 8 lines */ 1107 6, /* 9 lines */ 1108 5, /* 10 lines */ 1109 4, /* 11 lines */ 1110 7, /* 12 lines */ 1111 }; 1112 /* 1113 * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see 1114 * comments below for more information 1115 */ 1116 int tmp; 1117 1118 tmp = map[intel_dp->psr.io_wake_lines - 1119 TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; 1120 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES); 1121 1122 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; 1123 val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); 1124 } else if (DISPLAY_VER(display) >= 20) { 1125 val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1126 } else if (DISPLAY_VER(display) >= 12) { 1127 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1128 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1129 } else if (DISPLAY_VER(display) >= 9) { 1130 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); 1131 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); 1132 } 1133 1134 if (intel_dp->psr.req_psr2_sdp_prior_scanline) 1135 val |= EDP_PSR2_SU_SDP_SCANLINE; 1136 1137 if (DISPLAY_VER(display) >= 20) 1138 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); 1139 1140 if (intel_dp->psr.psr2_sel_fetch_enabled) { 1141 u32 tmp; 1142 1143 tmp = intel_de_read(display, 1144 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1145 drm_WARN_ON(display->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); 1146 } else if (HAS_PSR2_SEL_FETCH(display)) { 1147 intel_de_write(display, 1148 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 0); 1149 } 1150 1151 if (intel_dp->psr.su_region_et_enabled) 1152 val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; 1153 1154 /* 1155 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is 1156 * recommending keep this bit unset while PSR2 is enabled. 1157 */ 1158 intel_de_write(display, psr_ctl_reg(display, cpu_transcoder), psr_val); 1159 1160 intel_de_write(display, EDP_PSR2_CTL(display, cpu_transcoder), val); 1161 } 1162 1163 static bool 1164 transcoder_has_psr2(struct intel_display *display, enum transcoder cpu_transcoder) 1165 { 1166 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1167 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; 1168 else if (DISPLAY_VER(display) >= 12) 1169 return cpu_transcoder == TRANSCODER_A; 1170 else if (DISPLAY_VER(display) >= 9) 1171 return cpu_transcoder == TRANSCODER_EDP; 1172 else 1173 return false; 1174 } 1175 1176 static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state) 1177 { 1178 if (!crtc_state->hw.active) 1179 return 0; 1180 1181 return DIV_ROUND_UP(1000 * 1000, 1182 drm_mode_vrefresh(&crtc_state->hw.adjusted_mode)); 1183 } 1184 1185 static void psr2_program_idle_frames(struct intel_dp *intel_dp, 1186 u32 idle_frames) 1187 { 1188 struct intel_display *display = to_intel_display(intel_dp); 1189 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1190 1191 intel_de_rmw(display, EDP_PSR2_CTL(display, cpu_transcoder), 1192 EDP_PSR2_IDLE_FRAMES_MASK, 1193 EDP_PSR2_IDLE_FRAMES(idle_frames)); 1194 } 1195 1196 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 1197 { 1198 struct intel_display *display = to_intel_display(intel_dp); 1199 1200 psr2_program_idle_frames(intel_dp, 0); 1201 intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO); 1202 } 1203 1204 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 1205 { 1206 struct intel_display *display = to_intel_display(intel_dp); 1207 1208 intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1209 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 1210 } 1211 1212 static void tgl_dc3co_disable_work(struct work_struct *work) 1213 { 1214 struct intel_dp *intel_dp = 1215 container_of(work, typeof(*intel_dp), psr.dc3co_work.work); 1216 1217 mutex_lock(&intel_dp->psr.lock); 1218 /* If delayed work is pending, it is not idle */ 1219 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) 1220 goto unlock; 1221 1222 tgl_psr2_disable_dc3co(intel_dp); 1223 unlock: 1224 mutex_unlock(&intel_dp->psr.lock); 1225 } 1226 1227 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) 1228 { 1229 if (!intel_dp->psr.dc3co_exitline) 1230 return; 1231 1232 cancel_delayed_work(&intel_dp->psr.dc3co_work); 1233 /* Before PSR2 exit disallow dc3co*/ 1234 tgl_psr2_disable_dc3co(intel_dp); 1235 } 1236 1237 static bool 1238 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp, 1239 struct intel_crtc_state *crtc_state) 1240 { 1241 struct intel_display *display = to_intel_display(intel_dp); 1242 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1243 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 1244 enum port port = dig_port->base.port; 1245 1246 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1247 return pipe <= PIPE_B && port <= PORT_B; 1248 else 1249 return pipe == PIPE_A && port == PORT_A; 1250 } 1251 1252 static void 1253 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, 1254 struct intel_crtc_state *crtc_state) 1255 { 1256 struct intel_display *display = to_intel_display(intel_dp); 1257 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; 1258 struct i915_power_domains *power_domains = &display->power.domains; 1259 u32 exit_scanlines; 1260 1261 /* 1262 * FIXME: Due to the changed sequence of activating/deactivating DC3CO, 1263 * disable DC3CO until the changed dc3co activating/deactivating sequence 1264 * is applied. B.Specs:49196 1265 */ 1266 return; 1267 1268 /* 1269 * DMC's DC3CO exit mechanism has an issue with Selective Fecth 1270 * TODO: when the issue is addressed, this restriction should be removed. 1271 */ 1272 if (crtc_state->enable_psr2_sel_fetch) 1273 return; 1274 1275 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) 1276 return; 1277 1278 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state)) 1279 return; 1280 1281 /* Wa_16011303918:adl-p */ 1282 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918)) 1283 return; 1284 1285 /* 1286 * DC3CO Exit time 200us B.Spec 49196 1287 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 1288 */ 1289 exit_scanlines = 1290 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; 1291 1292 if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay)) 1293 return; 1294 1295 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; 1296 } 1297 1298 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, 1299 struct intel_crtc_state *crtc_state) 1300 { 1301 struct intel_display *display = to_intel_display(intel_dp); 1302 1303 if (!display->params.enable_psr2_sel_fetch && 1304 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 1305 drm_dbg_kms(display->drm, 1306 "PSR2 sel fetch not enabled, disabled by parameter\n"); 1307 return false; 1308 } 1309 1310 return crtc_state->enable_psr2_sel_fetch = true; 1311 } 1312 1313 static bool psr2_granularity_check(struct intel_crtc_state *crtc_state, 1314 struct intel_connector *connector) 1315 { 1316 struct intel_dp *intel_dp = intel_attached_dp(connector); 1317 struct intel_display *display = to_intel_display(intel_dp); 1318 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1319 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1320 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1321 u16 y_granularity = 0; 1322 u16 sink_y_granularity = crtc_state->has_panel_replay ? 1323 connector->dp.panel_replay_caps.su_y_granularity : 1324 connector->dp.psr_caps.su_y_granularity; 1325 u16 sink_w_granularity; 1326 1327 if (crtc_state->has_panel_replay) 1328 sink_w_granularity = connector->dp.panel_replay_caps.su_w_granularity == 1329 DP_PANEL_REPLAY_FULL_LINE_GRANULARITY ? 1330 crtc_hdisplay : connector->dp.panel_replay_caps.su_w_granularity; 1331 else 1332 sink_w_granularity = connector->dp.psr_caps.su_w_granularity; 1333 1334 /* PSR2 HW only send full lines so we only need to validate the width */ 1335 if (crtc_hdisplay % sink_w_granularity) 1336 return false; 1337 1338 if (crtc_vdisplay % sink_y_granularity) 1339 return false; 1340 1341 /* HW tracking is only aligned to 4 lines */ 1342 if (!crtc_state->enable_psr2_sel_fetch) 1343 return sink_y_granularity == 4; 1344 1345 /* 1346 * adl_p and mtl platforms have 1 line granularity. 1347 * For other platforms with SW tracking we can adjust the y coordinates 1348 * to match sink requirement if multiple of 4. 1349 */ 1350 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1351 y_granularity = sink_y_granularity; 1352 else if (sink_y_granularity <= 2) 1353 y_granularity = 4; 1354 else if ((sink_y_granularity % 4) == 0) 1355 y_granularity = sink_y_granularity; 1356 1357 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 1358 return false; 1359 1360 if (crtc_state->dsc.compression_enable && 1361 vdsc_cfg->slice_height % y_granularity) 1362 return false; 1363 1364 crtc_state->su_y_granularity = y_granularity; 1365 return true; 1366 } 1367 1368 static bool apply_scanline_indication_wa(struct intel_crtc_state *crtc_state, 1369 struct intel_connector *connector) 1370 { 1371 struct intel_dp *intel_dp = intel_attached_dp(connector); 1372 u8 early_scanline_support = connector->dp.psr_caps.intel_wa_dpcd & 1373 INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_EARLYSCANLINE_SDP_SUPPORT_MASK; 1374 1375 if (intel_dp->edp_dpcd[0] >= DP_EDP_15) 1376 return true; 1377 1378 switch (early_scanline_support) { 1379 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_FALL_BACK_TO_PSR1: 1380 crtc_state->req_psr2_sdp_prior_scanline = false; 1381 return false; 1382 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITH_EARLY_SCANLINE: 1383 return true; 1384 case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITHOUT_EARLY_SCANLINE: 1385 crtc_state->req_psr2_sdp_prior_scanline = false; 1386 return true; 1387 default: 1388 MISSING_CASE(early_scanline_support); 1389 return false; 1390 } 1391 } 1392 1393 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_crtc_state *crtc_state, 1394 struct intel_connector *connector) 1395 { 1396 struct intel_dp *intel_dp = intel_attached_dp(connector); 1397 struct intel_display *display = to_intel_display(intel_dp); 1398 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; 1399 u32 hblank_total, hblank_ns, req_ns; 1400 1401 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 1402 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); 1403 1404 /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ 1405 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); 1406 1407 if ((hblank_ns - req_ns) > 100) 1408 return true; 1409 1410 /* Not supported <13 / Wa_22012279113:adl-p */ 1411 if (DISPLAY_VER(display) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b) 1412 return false; 1413 1414 crtc_state->req_psr2_sdp_prior_scanline = true; 1415 1416 return apply_scanline_indication_wa(crtc_state, connector); 1417 } 1418 1419 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, 1420 struct drm_connector_state *conn_state, 1421 const struct drm_display_mode *adjusted_mode) 1422 { 1423 struct intel_display *display = to_intel_display(intel_dp); 1424 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1425 int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd); 1426 int entry_setup_frames = 0; 1427 1428 if (psr_setup_time < 0) { 1429 drm_dbg_kms(display->drm, 1430 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1431 connector->dp.psr_caps.dpcd[1]); 1432 return -ETIME; 1433 } 1434 1435 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 1436 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 1437 if (DISPLAY_VER(display) >= 20) { 1438 /* setup entry frames can be up to 3 frames */ 1439 entry_setup_frames = 1; 1440 drm_dbg_kms(display->drm, 1441 "PSR setup entry frames %d\n", 1442 entry_setup_frames); 1443 } else { 1444 drm_dbg_kms(display->drm, 1445 "PSR condition failed: PSR setup time (%d us) too long\n", 1446 psr_setup_time); 1447 return -ETIME; 1448 } 1449 } 1450 1451 return entry_setup_frames; 1452 } 1453 1454 static 1455 int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state, 1456 bool needs_panel_replay, 1457 bool needs_sel_update) 1458 { 1459 struct intel_display *display = to_intel_display(crtc_state); 1460 1461 if (!crtc_state->has_psr) 1462 return 0; 1463 1464 /* Wa_14015401596 */ 1465 if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14)) 1466 return 1; 1467 1468 /* Rest is for SRD_STATUS needed on LunarLake and onwards */ 1469 if (DISPLAY_VER(display) < 20) 1470 return 0; 1471 1472 /* 1473 * Comment on SRD_STATUS register in Bspec for LunarLake and onwards: 1474 * 1475 * To deterministically capture the transition of the state machine 1476 * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least 1477 * one line after the non-delayed V. Blank. 1478 * 1479 * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0 1480 * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ] 1481 * - TRANS_VTOTAL[ Vertical Active ]) 1482 * 1483 * SRD_STATUS is used only by PSR1 on PantherLake. 1484 * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake. 1485 */ 1486 1487 if (DISPLAY_VER(display) >= 30 && (needs_panel_replay || 1488 needs_sel_update)) 1489 return 0; 1490 else if (DISPLAY_VER(display) < 30 && (needs_sel_update || 1491 intel_crtc_has_type(crtc_state, 1492 INTEL_OUTPUT_EDP))) 1493 return 0; 1494 else 1495 return 1; 1496 } 1497 1498 static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state, 1499 int vblank, 1500 int wake_lines) 1501 { 1502 if (crtc_state->req_psr2_sdp_prior_scanline) 1503 vblank -= 1; 1504 1505 /* Vblank >= PSR2_CTL Block Count Number maximum line count */ 1506 if (vblank < wake_lines) 1507 return false; 1508 1509 return true; 1510 } 1511 1512 static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, 1513 const struct intel_crtc_state *crtc_state, 1514 bool aux_less, 1515 bool needs_panel_replay, 1516 bool needs_sel_update) 1517 { 1518 struct intel_display *display = to_intel_display(intel_dp); 1519 int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - 1520 crtc_state->hw.adjusted_mode.crtc_vblank_start; 1521 int wake_lines; 1522 int scl = _intel_psr_min_set_context_latency(crtc_state, 1523 needs_panel_replay, 1524 needs_sel_update); 1525 vblank -= scl; 1526 1527 if (aux_less) 1528 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 1529 else 1530 wake_lines = DISPLAY_VER(display) < 20 ? 1531 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 1532 crtc_state->alpm_state.fast_wake_lines) : 1533 crtc_state->alpm_state.io_wake_lines; 1534 1535 /* 1536 * Guardband has not been computed yet, so we conservatively check if the 1537 * full vblank duration is sufficient to accommodate wake line requirements 1538 * for PSR features like Panel Replay and Selective Update. 1539 * 1540 * Once the actual guardband is available, a more accurate validation is 1541 * performed in intel_psr_compute_config_late(), and PSR features are 1542 * disabled if wake lines exceed the available guardband. 1543 */ 1544 return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines); 1545 } 1546 1547 static bool alpm_config_valid(struct intel_dp *intel_dp, 1548 struct intel_crtc_state *crtc_state, 1549 bool aux_less, 1550 bool needs_panel_replay, 1551 bool needs_sel_update) 1552 { 1553 struct intel_display *display = to_intel_display(intel_dp); 1554 1555 if (!intel_alpm_compute_params(intel_dp, crtc_state)) { 1556 drm_dbg_kms(display->drm, 1557 "PSR2/Panel Replay not enabled, Unable to use long enough wake times\n"); 1558 return false; 1559 } 1560 1561 if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less, 1562 needs_panel_replay, needs_sel_update)) { 1563 drm_dbg_kms(display->drm, 1564 "PSR2/Panel Replay not enabled, too short vblank time\n"); 1565 return false; 1566 } 1567 1568 return true; 1569 } 1570 1571 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 1572 struct intel_crtc_state *crtc_state, 1573 struct drm_connector_state *conn_state) 1574 { 1575 struct intel_display *display = to_intel_display(intel_dp); 1576 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1577 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1578 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1579 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 1580 1581 if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1) 1582 return false; 1583 1584 /* JSL and EHL only supports eDP 1.3 */ 1585 if (display->platform.jasperlake || display->platform.elkhartlake) { 1586 drm_dbg_kms(display->drm, "PSR2 not supported by phy\n"); 1587 return false; 1588 } 1589 1590 /* Wa_16011181250 */ 1591 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011181250)) { 1592 drm_dbg_kms(display->drm, 1593 "PSR2 is defeatured for this platform\n"); 1594 return false; 1595 } 1596 1597 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1598 drm_dbg_kms(display->drm, 1599 "PSR2 not completely functional in this stepping\n"); 1600 return false; 1601 } 1602 1603 if (!transcoder_has_psr2(display, crtc_state->cpu_transcoder)) { 1604 drm_dbg_kms(display->drm, 1605 "PSR2 not supported in transcoder %s\n", 1606 transcoder_name(crtc_state->cpu_transcoder)); 1607 return false; 1608 } 1609 1610 /* 1611 * DSC and PSR2 cannot be enabled simultaneously. If a requested 1612 * resolution requires DSC to be enabled, priority is given to DSC 1613 * over PSR2. 1614 */ 1615 if (crtc_state->dsc.compression_enable && 1616 (DISPLAY_VER(display) < 14 && !display->platform.alderlake_p)) { 1617 drm_dbg_kms(display->drm, 1618 "PSR2 cannot be enabled since DSC is enabled\n"); 1619 return false; 1620 } 1621 1622 if (DISPLAY_VER(display) >= 20) { 1623 psr_max_h = crtc_hdisplay; 1624 psr_max_v = crtc_vdisplay; 1625 max_bpp = crtc_state->pipe_bpp; 1626 } else if (IS_DISPLAY_VER(display, 12, 14)) { 1627 psr_max_h = 5120; 1628 psr_max_v = 3200; 1629 max_bpp = 30; 1630 } else if (IS_DISPLAY_VER(display, 10, 11)) { 1631 psr_max_h = 4096; 1632 psr_max_v = 2304; 1633 max_bpp = 24; 1634 } else if (DISPLAY_VER(display) == 9) { 1635 psr_max_h = 3640; 1636 psr_max_v = 2304; 1637 max_bpp = 24; 1638 } 1639 1640 if (crtc_state->pipe_bpp > max_bpp) { 1641 drm_dbg_kms(display->drm, 1642 "PSR2 not enabled, pipe bpp %d > max supported %d\n", 1643 crtc_state->pipe_bpp, max_bpp); 1644 return false; 1645 } 1646 1647 /* Wa_16011303918:adl-p */ 1648 if (crtc_state->vrr.enable && 1649 display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 1650 drm_dbg_kms(display->drm, 1651 "PSR2 not enabled, not compatible with HW stepping + VRR\n"); 1652 return false; 1653 } 1654 1655 if (!alpm_config_valid(intel_dp, crtc_state, false, false, true)) 1656 return false; 1657 1658 if (!crtc_state->enable_psr2_sel_fetch && 1659 (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { 1660 drm_dbg_kms(display->drm, 1661 "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", 1662 crtc_hdisplay, crtc_vdisplay, 1663 psr_max_h, psr_max_v); 1664 return false; 1665 } 1666 1667 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); 1668 1669 return true; 1670 } 1671 1672 static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, 1673 struct drm_connector_state *conn_state) 1674 { 1675 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1676 struct intel_dp *intel_dp = intel_attached_dp(connector); 1677 struct intel_display *display = to_intel_display(intel_dp); 1678 1679 if (HAS_PSR2_SEL_FETCH(display) && 1680 !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && 1681 !HAS_PSR_HW_TRACKING(display)) { 1682 drm_dbg_kms(display->drm, 1683 "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); 1684 goto unsupported; 1685 } 1686 1687 if (!sel_update_global_enabled(intel_dp)) { 1688 drm_dbg_kms(display->drm, 1689 "Selective update disabled by flag\n"); 1690 goto unsupported; 1691 } 1692 1693 if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state, 1694 conn_state)) 1695 goto unsupported; 1696 1697 if (!_compute_psr2_sdp_prior_scanline_indication(crtc_state, connector)) { 1698 drm_dbg_kms(display->drm, 1699 "Selective update not enabled, SDP indication do not fit in hblank\n"); 1700 goto unsupported; 1701 } 1702 1703 if (crtc_state->has_panel_replay) { 1704 if (DISPLAY_VER(display) < 14) 1705 goto unsupported; 1706 1707 if (!connector->dp.panel_replay_caps.su_support) 1708 goto unsupported; 1709 1710 if (intel_dsc_enabled_on_link(crtc_state) && 1711 connector->dp.panel_replay_caps.dsc_support != 1712 INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { 1713 drm_dbg_kms(display->drm, 1714 "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); 1715 goto unsupported; 1716 } 1717 } 1718 1719 if (crtc_state->crc_enabled) { 1720 drm_dbg_kms(display->drm, 1721 "Selective update not enabled because it would inhibit pipe CRC calculation\n"); 1722 goto unsupported; 1723 } 1724 1725 if (!psr2_granularity_check(crtc_state, connector)) { 1726 drm_dbg_kms(display->drm, 1727 "Selective update not enabled, SU granularity not compatible\n"); 1728 goto unsupported; 1729 } 1730 1731 crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector, 1732 crtc_state->has_panel_replay); 1733 1734 return true; 1735 1736 unsupported: 1737 crtc_state->enable_psr2_sel_fetch = false; 1738 return false; 1739 } 1740 1741 static bool _psr_compute_config(struct intel_dp *intel_dp, 1742 struct intel_crtc_state *crtc_state, 1743 struct drm_connector_state *conn_state) 1744 { 1745 struct intel_display *display = to_intel_display(intel_dp); 1746 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1747 int entry_setup_frames; 1748 1749 if (!CAN_PSR(intel_dp) || !display->params.enable_psr) 1750 return false; 1751 1752 /* 1753 * Currently PSR doesn't work reliably with VRR enabled. 1754 */ 1755 if (crtc_state->vrr.enable) 1756 return false; 1757 1758 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); 1759 1760 if (entry_setup_frames >= 0) { 1761 crtc_state->entry_setup_frames = entry_setup_frames; 1762 } else { 1763 crtc_state->no_psr_reason = "PSR setup timing not met"; 1764 drm_dbg_kms(display->drm, 1765 "PSR condition failed: PSR setup timing not met\n"); 1766 return false; 1767 } 1768 1769 return true; 1770 } 1771 1772 static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector) 1773 { 1774 return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1775 DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP); 1776 } 1777 1778 static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector) 1779 { 1780 return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1781 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 1782 } 1783 1784 static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state, 1785 const struct drm_connector_state *conn_state) 1786 { 1787 struct intel_connector *connector = 1788 to_intel_connector(conn_state->connector); 1789 struct intel_dp *intel_dp = intel_attached_dp(connector); 1790 struct intel_display *display = to_intel_display(intel_dp); 1791 struct intel_hdcp *hdcp = &connector->hdcp; 1792 1793 if (!CAN_PANEL_REPLAY(intel_dp)) 1794 return false; 1795 1796 if (!connector->dp.panel_replay_caps.support) 1797 return false; 1798 1799 if (!panel_replay_global_enabled(intel_dp)) { 1800 drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); 1801 return false; 1802 } 1803 1804 if (crtc_state->crc_enabled) { 1805 drm_dbg_kms(display->drm, 1806 "Panel Replay not enabled because it would inhibit pipe CRC calculation\n"); 1807 return false; 1808 } 1809 1810 if (intel_dsc_enabled_on_link(crtc_state) && 1811 connector->dp.panel_replay_caps.dsc_support == 1812 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { 1813 drm_dbg_kms(display->drm, 1814 "Panel Replay not enabled because it's not supported with DSC\n"); 1815 return false; 1816 } 1817 1818 crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector); 1819 crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector); 1820 1821 if (!intel_dp_is_edp(intel_dp)) 1822 return true; 1823 1824 /* Remaining checks are for eDP only */ 1825 1826 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A && 1827 to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B) 1828 return false; 1829 1830 /* 128b/132b Panel Replay is not supported on eDP */ 1831 if (intel_dp_is_uhbr(crtc_state)) { 1832 drm_dbg_kms(display->drm, 1833 "Panel Replay is not supported with 128b/132b\n"); 1834 return false; 1835 } 1836 1837 /* HW will not allow Panel Replay on eDP when HDCP enabled */ 1838 if (conn_state->content_protection == 1839 DRM_MODE_CONTENT_PROTECTION_DESIRED || 1840 (conn_state->content_protection == 1841 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 1842 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) { 1843 drm_dbg_kms(display->drm, 1844 "Panel Replay is not supported with HDCP\n"); 1845 return false; 1846 } 1847 1848 if (!alpm_config_valid(intel_dp, crtc_state, true, true, false)) 1849 return false; 1850 1851 return true; 1852 } 1853 1854 static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, 1855 struct intel_crtc_state *crtc_state) 1856 { 1857 struct intel_display *display = to_intel_display(intel_dp); 1858 1859 return (DISPLAY_VER(display) == 20 && crtc_state->entry_setup_frames > 0 && 1860 !crtc_state->has_sel_update); 1861 } 1862 1863 static 1864 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp, 1865 struct intel_crtc_state *crtc_state) 1866 { 1867 struct intel_display *display = to_intel_display(intel_dp); 1868 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 1869 struct intel_crtc *crtc; 1870 u8 active_pipes = 0; 1871 1872 /* Wa_16025596647 */ 1873 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 1874 return; 1875 1876 /* Not needed by Panel Replay */ 1877 if (crtc_state->has_panel_replay) 1878 return; 1879 1880 /* We ignore possible secondary PSR/Panel Replay capable eDP */ 1881 for_each_intel_crtc(display->drm, crtc) 1882 active_pipes |= crtc->active ? BIT(crtc->pipe) : 0; 1883 1884 active_pipes = intel_calc_active_pipes(state, active_pipes); 1885 1886 crtc_state->active_non_psr_pipes = active_pipes & 1887 ~BIT(to_intel_crtc(crtc_state->uapi.crtc)->pipe); 1888 } 1889 1890 void intel_psr_compute_config(struct intel_dp *intel_dp, 1891 struct intel_crtc_state *crtc_state, 1892 struct drm_connector_state *conn_state) 1893 { 1894 struct intel_display *display = to_intel_display(intel_dp); 1895 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1896 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1897 1898 if (!psr_global_enabled(intel_dp)) { 1899 drm_dbg_kms(display->drm, "PSR disabled by flag\n"); 1900 return; 1901 } 1902 1903 if (intel_dp->psr.sink_not_reliable) { 1904 drm_dbg_kms(display->drm, 1905 "PSR sink implementation is not reliable\n"); 1906 return; 1907 } 1908 1909 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1910 drm_dbg_kms(display->drm, 1911 "PSR condition failed: Interlaced mode enabled\n"); 1912 return; 1913 } 1914 1915 /* 1916 * FIXME figure out what is wrong with PSR+joiner and 1917 * fix it. Presumably something related to the fact that 1918 * PSR is a transcoder level feature. 1919 */ 1920 if (crtc_state->joiner_pipes) { 1921 drm_dbg_kms(display->drm, 1922 "PSR disabled due to joiner\n"); 1923 return; 1924 } 1925 1926 /* Only used for state verification. */ 1927 crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support; 1928 crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state); 1929 1930 crtc_state->has_psr = crtc_state->has_panel_replay ? true : 1931 _psr_compute_config(intel_dp, crtc_state, conn_state); 1932 1933 if (!crtc_state->has_psr) 1934 return; 1935 1936 crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state); 1937 } 1938 1939 void intel_psr_get_config(struct intel_encoder *encoder, 1940 struct intel_crtc_state *pipe_config) 1941 { 1942 struct intel_display *display = to_intel_display(encoder); 1943 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1944 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 1945 struct intel_dp *intel_dp; 1946 u32 val; 1947 1948 if (!dig_port) 1949 return; 1950 1951 intel_dp = &dig_port->dp; 1952 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) 1953 return; 1954 1955 mutex_lock(&intel_dp->psr.lock); 1956 if (!intel_dp->psr.enabled) 1957 goto unlock; 1958 1959 if (intel_dp->psr.panel_replay_enabled) { 1960 pipe_config->has_psr = pipe_config->has_panel_replay = true; 1961 } else { 1962 /* 1963 * Not possible to read EDP_PSR/PSR2_CTL registers as it is 1964 * enabled/disabled because of frontbuffer tracking and others. 1965 */ 1966 pipe_config->has_psr = true; 1967 } 1968 1969 pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; 1970 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1971 1972 if (!intel_dp->psr.sel_update_enabled) 1973 goto unlock; 1974 1975 if (HAS_PSR2_SEL_FETCH(display)) { 1976 val = intel_de_read(display, 1977 PSR2_MAN_TRK_CTL(display, cpu_transcoder)); 1978 if (val & PSR2_MAN_TRK_CTL_ENABLE) 1979 pipe_config->enable_psr2_sel_fetch = true; 1980 } 1981 1982 pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; 1983 1984 if (DISPLAY_VER(display) >= 12) { 1985 val = intel_de_read(display, 1986 TRANS_EXITLINE(display, cpu_transcoder)); 1987 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); 1988 } 1989 unlock: 1990 mutex_unlock(&intel_dp->psr.lock); 1991 } 1992 1993 static void intel_psr_activate(struct intel_dp *intel_dp) 1994 { 1995 struct intel_display *display = to_intel_display(intel_dp); 1996 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 1997 1998 drm_WARN_ON(display->drm, 1999 transcoder_has_psr2(display, cpu_transcoder) && 2000 intel_de_read(display, EDP_PSR2_CTL(display, cpu_transcoder)) & EDP_PSR2_ENABLE); 2001 2002 drm_WARN_ON(display->drm, 2003 intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)) & EDP_PSR_ENABLE); 2004 2005 drm_WARN_ON(display->drm, intel_dp->psr.active); 2006 2007 drm_WARN_ON(display->drm, !intel_dp->psr.enabled); 2008 2009 lockdep_assert_held(&intel_dp->psr.lock); 2010 2011 /* psr1, psr2 and panel-replay are mutually exclusive.*/ 2012 if (intel_dp->psr.panel_replay_enabled) 2013 dg2_activate_panel_replay(intel_dp); 2014 else if (intel_dp->psr.sel_update_enabled) 2015 hsw_activate_psr2(intel_dp); 2016 else 2017 hsw_activate_psr1(intel_dp); 2018 2019 intel_dp->psr.active = true; 2020 intel_dp->psr.no_psr_reason = NULL; 2021 } 2022 2023 /* 2024 * Wa_16013835468 2025 * Wa_14015648006 2026 */ 2027 static void wm_optimization_wa(struct intel_dp *intel_dp, 2028 const struct intel_crtc_state *crtc_state) 2029 { 2030 struct intel_display *display = to_intel_display(intel_dp); 2031 enum pipe pipe = intel_dp->psr.pipe; 2032 bool activate = false; 2033 2034 /* Wa_14015648006 */ 2035 if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) 2036 activate = true; 2037 2038 /* Wa_16013835468 */ 2039 if (DISPLAY_VER(display) == 12 && 2040 crtc_state->hw.adjusted_mode.crtc_vblank_start != 2041 crtc_state->hw.adjusted_mode.crtc_vdisplay) 2042 activate = true; 2043 2044 if (activate) 2045 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2046 0, LATENCY_REPORTING_REMOVED(pipe)); 2047 else 2048 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2049 LATENCY_REPORTING_REMOVED(pipe), 0); 2050 } 2051 2052 static void intel_psr_enable_source(struct intel_dp *intel_dp, 2053 const struct intel_crtc_state *crtc_state) 2054 { 2055 struct intel_display *display = to_intel_display(intel_dp); 2056 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2057 u32 mask = 0; 2058 2059 /* 2060 * Only HSW and BDW have PSR AUX registers that need to be setup. 2061 * SKL+ use hardcoded values PSR AUX transactions 2062 */ 2063 if (DISPLAY_VER(display) < 9) 2064 hsw_psr_setup_aux(intel_dp); 2065 2066 /* 2067 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also 2068 * mask LPSP to avoid dependency on other drivers that might block 2069 * runtime_pm besides preventing other hw tracking issues now we 2070 * can rely on frontbuffer tracking. 2071 * 2072 * From bspec prior LunarLake: 2073 * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in 2074 * panel replay mode. 2075 * 2076 * From bspec beyod LunarLake: 2077 * Panel Replay on DP: No bits are applicable 2078 * Panel Replay on eDP: All bits are applicable 2079 */ 2080 if (DISPLAY_VER(display) < 20 || intel_dp_is_edp(intel_dp)) 2081 mask = EDP_PSR_DEBUG_MASK_HPD; 2082 2083 if (intel_dp_is_edp(intel_dp)) { 2084 mask |= EDP_PSR_DEBUG_MASK_MEMUP; 2085 2086 /* 2087 * For some unknown reason on HSW non-ULT (or at least on 2088 * Dell Latitude E6540) external displays start to flicker 2089 * when PSR is enabled on the eDP. SR/PC6 residency is much 2090 * higher than should be possible with an external display. 2091 * As a workaround leave LPSP unmasked to prevent PSR entry 2092 * when external displays are active. 2093 */ 2094 if (DISPLAY_VER(display) >= 8 || display->platform.haswell_ult) 2095 mask |= EDP_PSR_DEBUG_MASK_LPSP; 2096 2097 if (DISPLAY_VER(display) < 20) 2098 mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP; 2099 2100 /* 2101 * No separate pipe reg write mask on hsw/bdw, so have to unmask all 2102 * registers in order to keep the CURSURFLIVE tricks working :( 2103 */ 2104 if (IS_DISPLAY_VER(display, 9, 10)) 2105 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; 2106 2107 /* allow PSR with sprite enabled */ 2108 if (display->platform.haswell) 2109 mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; 2110 } 2111 2112 intel_de_write(display, psr_debug_reg(display, cpu_transcoder), mask); 2113 2114 psr_irq_control(intel_dp); 2115 2116 /* 2117 * TODO: if future platforms supports DC3CO in more than one 2118 * transcoder, EXITLINE will need to be unset when disabling PSR 2119 */ 2120 if (intel_dp->psr.dc3co_exitline) 2121 intel_de_rmw(display, 2122 TRANS_EXITLINE(display, cpu_transcoder), 2123 EXITLINE_MASK, 2124 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); 2125 2126 if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display)) 2127 intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, 2128 intel_dp->psr.psr2_sel_fetch_enabled ? 2129 IGNORE_PSR2_HW_TRACKING : 0); 2130 2131 /* 2132 * Wa_16013835468 2133 * Wa_14015648006 2134 */ 2135 wm_optimization_wa(intel_dp, crtc_state); 2136 2137 if (intel_dp->psr.sel_update_enabled) { 2138 if (DISPLAY_VER(display) == 9) 2139 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, 2140 PSR2_VSC_ENABLE_PROG_HEADER | 2141 PSR2_ADD_VERTICAL_LINE_COUNT); 2142 2143 /* 2144 * Wa_16014451276:adlp,mtl[a0,b0] 2145 * All supported adlp panels have 1-based X granularity, this may 2146 * cause issues if non-supported panels are used. 2147 */ 2148 if (!intel_dp->psr.panel_replay_enabled && 2149 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2150 display->platform.alderlake_p)) 2151 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 2152 0, ADLP_1_BASED_X_GRANULARITY); 2153 2154 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2155 if (!intel_dp->psr.panel_replay_enabled && 2156 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2157 intel_de_rmw(display, 2158 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2159 0, 2160 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); 2161 else if (display->platform.alderlake_p) 2162 intel_de_rmw(display, CLKGATE_DIS_MISC, 0, 2163 CLKGATE_DIS_MISC_DMASC_GATING_DIS); 2164 } 2165 2166 /* Wa_16025596647 */ 2167 if ((DISPLAY_VER(display) == 20 || 2168 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2169 !intel_dp->psr.panel_replay_enabled) 2170 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true); 2171 2172 intel_alpm_configure(intel_dp, crtc_state); 2173 2174 if (HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display)) 2175 intel_vrr_psr_frame_change_enable(crtc_state); 2176 } 2177 2178 static bool psr_interrupt_error_check(struct intel_dp *intel_dp) 2179 { 2180 struct intel_display *display = to_intel_display(intel_dp); 2181 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2182 u32 val; 2183 2184 if (intel_dp->psr.panel_replay_enabled) 2185 goto no_err; 2186 2187 /* 2188 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR 2189 * will still keep the error set even after the reset done in the 2190 * irq_preinstall and irq_uninstall hooks. 2191 * And enabling in this situation cause the screen to freeze in the 2192 * first time that PSR HW tries to activate so lets keep PSR disabled 2193 * to avoid any rendering problems. 2194 */ 2195 val = intel_de_read(display, psr_iir_reg(display, cpu_transcoder)); 2196 val &= psr_irq_psr_error_bit_get(intel_dp); 2197 if (val) { 2198 intel_dp->psr.sink_not_reliable = true; 2199 drm_dbg_kms(display->drm, 2200 "PSR interruption error set, not enabling PSR\n"); 2201 return false; 2202 } 2203 2204 no_err: 2205 return true; 2206 } 2207 2208 static void intel_psr_enable_locked(struct intel_dp *intel_dp, 2209 const struct intel_crtc_state *crtc_state) 2210 { 2211 struct intel_display *display = to_intel_display(intel_dp); 2212 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2213 u32 val; 2214 2215 drm_WARN_ON(display->drm, intel_dp->psr.enabled); 2216 2217 intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; 2218 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; 2219 intel_dp->psr.busy_frontbuffer_bits = 0; 2220 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; 2221 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; 2222 /* DC5/DC6 requires at least 6 idle frames */ 2223 val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); 2224 intel_dp->psr.dc3co_exit_delay = val; 2225 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; 2226 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; 2227 intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; 2228 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2229 intel_dp->psr.req_psr2_sdp_prior_scanline = 2230 crtc_state->req_psr2_sdp_prior_scanline; 2231 intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes; 2232 intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used; 2233 intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines; 2234 intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines; 2235 intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames; 2236 2237 if (!psr_interrupt_error_check(intel_dp)) 2238 return; 2239 2240 if (intel_dp->psr.panel_replay_enabled) 2241 drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); 2242 else 2243 drm_dbg_kms(display->drm, "Enabling PSR%s\n", 2244 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2245 2246 /* 2247 * Enabling sink PSR/Panel Replay here only for PSR. Panel Replay enable 2248 * bit is already written at this point. Sink ALPM is enabled here for 2249 * PSR and Panel Replay. See 2250 * intel_psr_panel_replay_enable_sink. Modifiers/options: 2251 * - Selective Update 2252 * - Region Early Transport 2253 * - Selective Update Region Scanline Capture 2254 * - VSC_SDP_CRC 2255 * - HPD on different Errors 2256 * - CRC verification 2257 * are written for PSR and Panel Replay here. 2258 */ 2259 intel_psr_enable_sink(intel_dp, crtc_state); 2260 2261 if (intel_dp_is_edp(intel_dp)) 2262 intel_snps_phy_update_psr_power_state(&dig_port->base, true); 2263 2264 intel_psr_enable_source(intel_dp, crtc_state); 2265 intel_dp->psr.enabled = true; 2266 intel_dp->psr.pause_counter = 0; 2267 2268 /* 2269 * Link_ok is sticky and set here on PSR enable. We can assume link 2270 * training is complete as we never continue to PSR enable with 2271 * untrained link. Link_ok is kept as set until first short pulse 2272 * interrupt. This is targeted to workaround panels stating bad link 2273 * after PSR is enabled. 2274 */ 2275 intel_dp->psr.link_ok = true; 2276 2277 intel_psr_activate(intel_dp); 2278 } 2279 2280 static void intel_psr_exit(struct intel_dp *intel_dp) 2281 { 2282 struct intel_display *display = to_intel_display(intel_dp); 2283 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2284 u32 val; 2285 2286 if (!intel_dp->psr.active) { 2287 if (transcoder_has_psr2(display, cpu_transcoder)) { 2288 val = intel_de_read(display, 2289 EDP_PSR2_CTL(display, cpu_transcoder)); 2290 drm_WARN_ON(display->drm, val & EDP_PSR2_ENABLE); 2291 } 2292 2293 val = intel_de_read(display, 2294 psr_ctl_reg(display, cpu_transcoder)); 2295 drm_WARN_ON(display->drm, val & EDP_PSR_ENABLE); 2296 2297 return; 2298 } 2299 2300 if (intel_dp->psr.panel_replay_enabled) { 2301 intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 2302 TRANS_DP2_PANEL_REPLAY_ENABLE, 0); 2303 } else if (intel_dp->psr.sel_update_enabled) { 2304 tgl_disallow_dc3co_on_psr2_exit(intel_dp); 2305 2306 val = intel_de_rmw(display, 2307 EDP_PSR2_CTL(display, cpu_transcoder), 2308 EDP_PSR2_ENABLE, 0); 2309 2310 drm_WARN_ON(display->drm, !(val & EDP_PSR2_ENABLE)); 2311 } else { 2312 if ((DISPLAY_VER(display) == 20 || 2313 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2314 intel_dp->psr.pkg_c_latency_used) 2315 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 2316 intel_dp->psr.pipe, 2317 false); 2318 2319 val = intel_de_rmw(display, 2320 psr_ctl_reg(display, cpu_transcoder), 2321 EDP_PSR_ENABLE, 0); 2322 2323 drm_WARN_ON(display->drm, !(val & EDP_PSR_ENABLE)); 2324 } 2325 intel_dp->psr.active = false; 2326 } 2327 2328 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) 2329 { 2330 struct intel_display *display = to_intel_display(intel_dp); 2331 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2332 i915_reg_t psr_status; 2333 u32 psr_status_mask; 2334 2335 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 2336 intel_dp->psr.panel_replay_enabled)) { 2337 psr_status = EDP_PSR2_STATUS(display, cpu_transcoder); 2338 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 2339 } else { 2340 psr_status = psr_status_reg(display, cpu_transcoder); 2341 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 2342 } 2343 2344 /* Wait till PSR is idle */ 2345 if (intel_de_wait_for_clear_ms(display, psr_status, 2346 psr_status_mask, 2000)) 2347 drm_err(display->drm, "Timed out waiting PSR idle state\n"); 2348 } 2349 2350 static void intel_psr_disable_locked(struct intel_dp *intel_dp) 2351 { 2352 struct intel_display *display = to_intel_display(intel_dp); 2353 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 2354 2355 lockdep_assert_held(&intel_dp->psr.lock); 2356 2357 if (!intel_dp->psr.enabled) 2358 return; 2359 2360 if (intel_dp->psr.panel_replay_enabled) 2361 drm_dbg_kms(display->drm, "Disabling Panel Replay\n"); 2362 else 2363 drm_dbg_kms(display->drm, "Disabling PSR%s\n", 2364 intel_dp->psr.sel_update_enabled ? "2" : "1"); 2365 2366 intel_psr_exit(intel_dp); 2367 intel_psr_wait_exit_locked(intel_dp); 2368 2369 /* 2370 * Wa_16013835468 2371 * Wa_14015648006 2372 */ 2373 if (DISPLAY_VER(display) >= 11) 2374 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2375 LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); 2376 2377 if (intel_dp->psr.sel_update_enabled) { 2378 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2379 if (!intel_dp->psr.panel_replay_enabled && 2380 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0)) 2381 intel_de_rmw(display, 2382 MTL_CLKGATE_DIS_TRANS(display, cpu_transcoder), 2383 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); 2384 else if (display->platform.alderlake_p) 2385 intel_de_rmw(display, CLKGATE_DIS_MISC, 2386 CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0); 2387 } 2388 2389 if (intel_dp_is_edp(intel_dp)) 2390 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false); 2391 2392 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) 2393 intel_alpm_disable(intel_dp); 2394 2395 /* Disable PSR on Sink */ 2396 if (!intel_dp->psr.panel_replay_enabled) { 2397 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 2398 2399 if (intel_dp->psr.sel_update_enabled) 2400 drm_dp_dpcd_writeb(&intel_dp->aux, 2401 DP_RECEIVER_ALPM_CONFIG, 0); 2402 } 2403 2404 /* Wa_16025596647 */ 2405 if ((DISPLAY_VER(display) == 20 || 2406 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2407 !intel_dp->psr.panel_replay_enabled) 2408 intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false); 2409 2410 intel_dp->psr.enabled = false; 2411 intel_dp->psr.panel_replay_enabled = false; 2412 intel_dp->psr.sel_update_enabled = false; 2413 intel_dp->psr.psr2_sel_fetch_enabled = false; 2414 intel_dp->psr.su_region_et_enabled = false; 2415 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 2416 intel_dp->psr.active_non_psr_pipes = 0; 2417 intel_dp->psr.pkg_c_latency_used = 0; 2418 } 2419 2420 /** 2421 * intel_psr_disable - Disable PSR 2422 * @intel_dp: Intel DP 2423 * @old_crtc_state: old CRTC state 2424 * 2425 * This function needs to be called before disabling pipe. 2426 */ 2427 void intel_psr_disable(struct intel_dp *intel_dp, 2428 const struct intel_crtc_state *old_crtc_state) 2429 { 2430 struct intel_display *display = to_intel_display(intel_dp); 2431 2432 if (!old_crtc_state->has_psr) 2433 return; 2434 2435 if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && 2436 !CAN_PANEL_REPLAY(intel_dp))) 2437 return; 2438 2439 mutex_lock(&intel_dp->psr.lock); 2440 2441 intel_psr_disable_locked(intel_dp); 2442 2443 intel_dp->psr.link_ok = false; 2444 2445 mutex_unlock(&intel_dp->psr.lock); 2446 cancel_work_sync(&intel_dp->psr.work); 2447 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); 2448 } 2449 2450 /** 2451 * intel_psr_pause - Pause PSR 2452 * @intel_dp: Intel DP 2453 * 2454 * This function need to be called after enabling psr. 2455 */ 2456 void intel_psr_pause(struct intel_dp *intel_dp) 2457 { 2458 struct intel_psr *psr = &intel_dp->psr; 2459 2460 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2461 return; 2462 2463 mutex_lock(&psr->lock); 2464 2465 if (!psr->enabled) { 2466 mutex_unlock(&psr->lock); 2467 return; 2468 } 2469 2470 if (intel_dp->psr.pause_counter++ == 0) { 2471 intel_psr_exit(intel_dp); 2472 intel_psr_wait_exit_locked(intel_dp); 2473 } 2474 2475 mutex_unlock(&psr->lock); 2476 2477 cancel_work_sync(&psr->work); 2478 cancel_delayed_work_sync(&psr->dc3co_work); 2479 } 2480 2481 /** 2482 * intel_psr_resume - Resume PSR 2483 * @intel_dp: Intel DP 2484 * 2485 * This function need to be called after pausing psr. 2486 */ 2487 void intel_psr_resume(struct intel_dp *intel_dp) 2488 { 2489 struct intel_display *display = to_intel_display(intel_dp); 2490 struct intel_psr *psr = &intel_dp->psr; 2491 2492 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 2493 return; 2494 2495 mutex_lock(&psr->lock); 2496 2497 if (!psr->enabled) 2498 goto out; 2499 2500 if (!psr->pause_counter) { 2501 drm_warn(display->drm, "Unbalanced PSR pause/resume!\n"); 2502 goto out; 2503 } 2504 2505 if (--intel_dp->psr.pause_counter == 0) 2506 intel_psr_activate(intel_dp); 2507 2508 out: 2509 mutex_unlock(&psr->lock); 2510 } 2511 2512 /** 2513 * intel_psr_needs_vblank_notification - Check if PSR need vblank enable/disable 2514 * notification. 2515 * @crtc_state: CRTC status 2516 * 2517 * We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't 2518 * prevent it in case of Panel Replay. Panel Replay switches main link off on 2519 * DC entry. This means vblank interrupts are not fired and is a problem if 2520 * user-space is polling for vblank events. Also Wa_16025596647 needs 2521 * information when vblank is enabled/disabled. 2522 */ 2523 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state) 2524 { 2525 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2526 struct intel_display *display = to_intel_display(crtc_state); 2527 struct intel_encoder *encoder; 2528 2529 for_each_encoder_on_crtc(crtc->base.dev, &crtc->base, encoder) { 2530 struct intel_dp *intel_dp; 2531 2532 if (!intel_encoder_is_dp(encoder)) 2533 continue; 2534 2535 intel_dp = enc_to_intel_dp(encoder); 2536 2537 if (!intel_dp_is_edp(intel_dp)) 2538 continue; 2539 2540 if (CAN_PANEL_REPLAY(intel_dp)) 2541 return true; 2542 2543 if ((DISPLAY_VER(display) == 20 || 2544 IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) && 2545 CAN_PSR(intel_dp)) 2546 return true; 2547 } 2548 2549 return false; 2550 } 2551 2552 /** 2553 * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event 2554 * @dsb: DSB context 2555 * @state: the atomic state 2556 * @crtc: the CRTC 2557 * 2558 * Generate PSR "Frame Change" event. 2559 */ 2560 void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, 2561 struct intel_atomic_state *state, 2562 struct intel_crtc *crtc) 2563 { 2564 const struct intel_crtc_state *crtc_state = 2565 intel_pre_commit_crtc_state(state, crtc); 2566 struct intel_display *display = to_intel_display(crtc); 2567 2568 if (!crtc_state->has_psr || intel_psr_use_trans_push(crtc_state)) 2569 return; 2570 2571 intel_de_write_dsb(display, dsb, 2572 CURSURFLIVE(display, crtc->pipe), 0); 2573 } 2574 2575 /** 2576 * intel_psr_min_set_context_latency - Minimum 'set context latency' lines needed by PSR 2577 * @crtc_state: the crtc state 2578 * 2579 * Return minimum SCL lines/delay needed by PSR. 2580 */ 2581 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state) 2582 { 2583 2584 return _intel_psr_min_set_context_latency(crtc_state, 2585 crtc_state->has_panel_replay, 2586 crtc_state->has_sel_update); 2587 } 2588 2589 static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) 2590 { 2591 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 0 : 2592 PSR2_MAN_TRK_CTL_ENABLE; 2593 } 2594 2595 static u32 man_trk_ctl_single_full_frame_bit_get(struct intel_display *display) 2596 { 2597 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2598 ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME : 2599 PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; 2600 } 2601 2602 static u32 man_trk_ctl_partial_frame_bit_get(struct intel_display *display) 2603 { 2604 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2605 ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE : 2606 PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; 2607 } 2608 2609 static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) 2610 { 2611 return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? 2612 ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : 2613 PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; 2614 } 2615 2616 static void intel_psr_force_update(struct intel_dp *intel_dp) 2617 { 2618 struct intel_display *display = to_intel_display(intel_dp); 2619 2620 /* 2621 * Display WA #0884: skl+ 2622 * This documented WA for bxt can be safely applied 2623 * broadly so we can force HW tracking to exit PSR 2624 * instead of disabling and re-enabling. 2625 * Workaround tells us to write 0 to CUR_SURFLIVE_A, 2626 * but it makes more sense write to the current active 2627 * pipe. 2628 * 2629 * This workaround do not exist for platforms with display 10 or newer 2630 * but testing proved that it works for up display 13, for newer 2631 * than that testing will be needed. 2632 */ 2633 intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); 2634 } 2635 2636 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 2637 const struct intel_crtc_state *crtc_state) 2638 { 2639 struct intel_display *display = to_intel_display(crtc_state); 2640 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2641 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2642 struct intel_encoder *encoder; 2643 2644 if (!crtc_state->enable_psr2_sel_fetch) 2645 return; 2646 2647 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2648 crtc_state->uapi.encoder_mask) { 2649 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2650 2651 if (!dsb) 2652 lockdep_assert_held(&intel_dp->psr.lock); 2653 2654 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) 2655 return; 2656 break; 2657 } 2658 2659 intel_de_write_dsb(display, dsb, 2660 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 2661 crtc_state->psr2_man_track_ctl); 2662 2663 if (!crtc_state->enable_psr2_su_region_et) 2664 return; 2665 2666 intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 2667 crtc_state->pipe_srcsz_early_tpt); 2668 2669 if (!crtc_state->dsc.compression_enable) 2670 return; 2671 2672 intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state, 2673 drm_rect_height(&crtc_state->psr2_su_area)); 2674 } 2675 2676 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, 2677 bool full_update) 2678 { 2679 struct intel_display *display = to_intel_display(crtc_state); 2680 u32 val = man_trk_ctl_enable_bit_get(display); 2681 2682 /* SF partial frame enable has to be set even on full update */ 2683 val |= man_trk_ctl_partial_frame_bit_get(display); 2684 2685 if (full_update) { 2686 val |= man_trk_ctl_continuos_full_frame(display); 2687 goto exit; 2688 } 2689 2690 if (crtc_state->psr2_su_area.y1 == -1) 2691 goto exit; 2692 2693 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) { 2694 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(crtc_state->psr2_su_area.y1); 2695 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(crtc_state->psr2_su_area.y2 - 1); 2696 } else { 2697 drm_WARN_ON(crtc_state->uapi.crtc->dev, 2698 crtc_state->psr2_su_area.y1 % 4 || 2699 crtc_state->psr2_su_area.y2 % 4); 2700 2701 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR( 2702 crtc_state->psr2_su_area.y1 / 4 + 1); 2703 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR( 2704 crtc_state->psr2_su_area.y2 / 4 + 1); 2705 } 2706 exit: 2707 crtc_state->psr2_man_track_ctl = val; 2708 } 2709 2710 static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, 2711 bool full_update) 2712 { 2713 int width, height; 2714 2715 if (!crtc_state->enable_psr2_su_region_et || full_update) 2716 return 0; 2717 2718 width = drm_rect_width(&crtc_state->psr2_su_area); 2719 height = drm_rect_height(&crtc_state->psr2_su_area); 2720 2721 return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); 2722 } 2723 2724 static void clip_area_update(struct drm_rect *overlap_damage_area, 2725 struct drm_rect *damage_area, 2726 struct drm_rect *display_area) 2727 { 2728 if (!drm_rect_intersect(damage_area, display_area)) 2729 return; 2730 2731 if (overlap_damage_area->y1 == -1) { 2732 overlap_damage_area->y1 = damage_area->y1; 2733 overlap_damage_area->y2 = damage_area->y2; 2734 return; 2735 } 2736 2737 if (damage_area->y1 < overlap_damage_area->y1) 2738 overlap_damage_area->y1 = damage_area->y1; 2739 2740 if (damage_area->y2 > overlap_damage_area->y2) 2741 overlap_damage_area->y2 = damage_area->y2; 2742 } 2743 2744 static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state) 2745 { 2746 struct intel_display *display = to_intel_display(crtc_state); 2747 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 2748 u16 y_alignment; 2749 bool su_area_changed = false; 2750 2751 /* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */ 2752 if (crtc_state->dsc.compression_enable && 2753 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 2754 y_alignment = vdsc_cfg->slice_height; 2755 else 2756 y_alignment = crtc_state->su_y_granularity; 2757 2758 if (crtc_state->psr2_su_area.y1 % y_alignment) { 2759 crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment; 2760 su_area_changed = true; 2761 } 2762 2763 if (crtc_state->psr2_su_area.y2 % y_alignment) { 2764 crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 / 2765 y_alignment) + 1) * y_alignment; 2766 su_area_changed = true; 2767 } 2768 2769 return su_area_changed; 2770 } 2771 2772 /* 2773 * When early transport is in use we need to extend SU area to cover 2774 * cursor fully when cursor is in SU area. 2775 */ 2776 static void 2777 intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state, 2778 struct intel_crtc *crtc, 2779 struct drm_rect *display_area, 2780 bool *cursor_in_su_area) 2781 { 2782 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2783 struct intel_plane_state *new_plane_state; 2784 struct intel_plane *plane; 2785 int i; 2786 2787 if (!crtc_state->enable_psr2_su_region_et) 2788 return; 2789 2790 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 2791 struct drm_rect inter; 2792 2793 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2794 continue; 2795 2796 if (plane->id != PLANE_CURSOR) 2797 continue; 2798 2799 if (!new_plane_state->uapi.visible) 2800 continue; 2801 2802 inter = crtc_state->psr2_su_area; 2803 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) 2804 continue; 2805 2806 clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst, 2807 display_area); 2808 *cursor_in_su_area = true; 2809 } 2810 } 2811 2812 /* 2813 * TODO: Not clear how to handle planes with negative position, 2814 * also planes are not updated if they have a negative X 2815 * position so for now doing a full update in this cases 2816 * 2817 * Plane scaling and rotation is not supported by selective fetch and both 2818 * properties can change without a modeset, so need to be check at every 2819 * atomic commit. 2820 */ 2821 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state) 2822 { 2823 if (plane_state->uapi.dst.y1 < 0 || 2824 plane_state->uapi.dst.x1 < 0 || 2825 plane_state->scaler_id >= 0 || 2826 plane_state->hw.rotation != DRM_MODE_ROTATE_0) 2827 return false; 2828 2829 return true; 2830 } 2831 2832 /* 2833 * Check for pipe properties that is not supported by selective fetch. 2834 * 2835 * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed 2836 * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch 2837 * enabled and going to the full update path. 2838 */ 2839 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 2840 { 2841 if (crtc_state->scaler_state.scaler_id >= 0 || 2842 crtc_state->async_flip_planes) 2843 return false; 2844 2845 return true; 2846 } 2847 2848 /* Wa 14019834836 */ 2849 static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state) 2850 { 2851 struct intel_display *display = to_intel_display(crtc_state); 2852 struct intel_encoder *encoder; 2853 int hactive_limit; 2854 2855 if (crtc_state->psr2_su_area.y1 != 0 || 2856 crtc_state->psr2_su_area.y2 != 0) 2857 return; 2858 2859 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2860 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546; 2861 else 2862 hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273; 2863 2864 if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit) 2865 return; 2866 2867 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 2868 crtc_state->uapi.encoder_mask) { 2869 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2870 2871 if (!intel_dp_is_edp(intel_dp) && 2872 intel_dp->psr.panel_replay_enabled && 2873 intel_dp->psr.sel_update_enabled) { 2874 crtc_state->psr2_su_area.y2++; 2875 return; 2876 } 2877 } 2878 } 2879 2880 static void 2881 intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) 2882 { 2883 struct intel_display *display = to_intel_display(crtc_state); 2884 2885 /* Wa_14014971492 */ 2886 if (!crtc_state->has_panel_replay && 2887 ((IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 2888 display->platform.alderlake_p || display->platform.tigerlake)) && 2889 crtc_state->splitter.enable) 2890 crtc_state->psr2_su_area.y1 = 0; 2891 2892 /* Wa 14019834836 */ 2893 if (DISPLAY_VER(display) == 30) 2894 intel_psr_apply_pr_link_on_su_wa(crtc_state); 2895 } 2896 2897 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, 2898 struct intel_crtc *crtc) 2899 { 2900 struct intel_display *display = to_intel_display(state); 2901 struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 2902 struct intel_plane_state *new_plane_state, *old_plane_state; 2903 struct intel_plane *plane; 2904 struct drm_rect display_area = { 2905 .x1 = 0, 2906 .y1 = 0, 2907 .x2 = crtc_state->hw.adjusted_mode.crtc_hdisplay, 2908 .y2 = crtc_state->hw.adjusted_mode.crtc_vdisplay, 2909 }; 2910 bool full_update = false, su_area_changed; 2911 int i, ret; 2912 2913 if (!crtc_state->enable_psr2_sel_fetch) 2914 return 0; 2915 2916 if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) { 2917 full_update = true; 2918 goto skip_sel_fetch_set_loop; 2919 } 2920 2921 crtc_state->psr2_su_area.x1 = 0; 2922 crtc_state->psr2_su_area.y1 = -1; 2923 crtc_state->psr2_su_area.x2 = drm_rect_width(&display_area); 2924 crtc_state->psr2_su_area.y2 = -1; 2925 2926 /* 2927 * Calculate minimal selective fetch area of each plane and calculate 2928 * the pipe damaged area. 2929 * In the next loop the plane selective fetch area will actually be set 2930 * using whole pipe damaged area. 2931 */ 2932 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 2933 new_plane_state, i) { 2934 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 2935 .x2 = INT_MAX }; 2936 2937 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2938 continue; 2939 2940 if (!new_plane_state->uapi.visible && 2941 !old_plane_state->uapi.visible) 2942 continue; 2943 2944 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 2945 full_update = true; 2946 break; 2947 } 2948 2949 /* 2950 * If visibility or plane moved, mark the whole plane area as 2951 * damaged as it needs to be complete redraw in the new and old 2952 * position. 2953 */ 2954 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || 2955 !drm_rect_equals(&new_plane_state->uapi.dst, 2956 &old_plane_state->uapi.dst)) { 2957 if (old_plane_state->uapi.visible) { 2958 damaged_area.y1 = old_plane_state->uapi.dst.y1; 2959 damaged_area.y2 = old_plane_state->uapi.dst.y2; 2960 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2961 &display_area); 2962 } 2963 2964 if (new_plane_state->uapi.visible) { 2965 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2966 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2967 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2968 &display_area); 2969 } 2970 continue; 2971 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { 2972 /* If alpha changed mark the whole plane area as damaged */ 2973 damaged_area.y1 = new_plane_state->uapi.dst.y1; 2974 damaged_area.y2 = new_plane_state->uapi.dst.y2; 2975 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, 2976 &display_area); 2977 continue; 2978 } 2979 2980 src = drm_plane_state_src(&new_plane_state->uapi); 2981 drm_rect_fp_to_int(&src, &src); 2982 2983 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, 2984 &new_plane_state->uapi, &damaged_area)) 2985 continue; 2986 2987 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; 2988 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; 2989 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; 2990 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; 2991 2992 clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &display_area); 2993 } 2994 2995 /* 2996 * TODO: For now we are just using full update in case 2997 * selective fetch area calculation fails. To optimize this we 2998 * should identify cases where this happens and fix the area 2999 * calculation for those. 3000 */ 3001 if (crtc_state->psr2_su_area.y1 == -1) { 3002 drm_info_once(display->drm, 3003 "Selective fetch area calculation failed in pipe %c\n", 3004 pipe_name(crtc->pipe)); 3005 full_update = true; 3006 } 3007 3008 if (full_update) 3009 goto skip_sel_fetch_set_loop; 3010 3011 intel_psr_apply_su_area_workarounds(crtc_state); 3012 3013 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 3014 if (ret) 3015 return ret; 3016 3017 do { 3018 bool cursor_in_su_area = false; 3019 3020 /* 3021 * Adjust su area to cover cursor fully as necessary 3022 * (early transport). This needs to be done after 3023 * drm_atomic_add_affected_planes to ensure visible 3024 * cursor is added into affected planes even when 3025 * cursor is not updated by itself. 3026 */ 3027 intel_psr2_sel_fetch_et_alignment(state, crtc, &display_area, 3028 &cursor_in_su_area); 3029 3030 su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state); 3031 3032 /* 3033 * If the cursor was outside the SU area before 3034 * alignment, the alignment step (which only expands 3035 * SU) may pull the cursor partially inside, so we 3036 * must run ET alignment again to fully cover it. But 3037 * if the cursor was already fully inside before 3038 * alignment, expanding the SU area won't change that, 3039 * so no further work is needed. 3040 */ 3041 if (cursor_in_su_area) 3042 break; 3043 } while (su_area_changed); 3044 3045 /* 3046 * Now that we have the pipe damaged area check if it intersect with 3047 * every plane, if it does set the plane selective fetch area. 3048 */ 3049 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 3050 new_plane_state, i) { 3051 struct drm_rect *sel_fetch_area, inter; 3052 struct intel_plane *linked = new_plane_state->planar_linked_plane; 3053 3054 if (new_plane_state->hw.crtc != crtc_state->uapi.crtc || 3055 !new_plane_state->uapi.visible) 3056 continue; 3057 3058 inter = crtc_state->psr2_su_area; 3059 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3060 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) { 3061 sel_fetch_area->y1 = -1; 3062 sel_fetch_area->y2 = -1; 3063 /* 3064 * if plane sel fetch was previously enabled -> 3065 * disable it 3066 */ 3067 if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0) 3068 crtc_state->update_planes |= BIT(plane->id); 3069 3070 continue; 3071 } 3072 3073 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) { 3074 full_update = true; 3075 break; 3076 } 3077 3078 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; 3079 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; 3080 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; 3081 crtc_state->update_planes |= BIT(plane->id); 3082 3083 /* 3084 * Sel_fetch_area is calculated for UV plane. Use 3085 * same area for Y plane as well. 3086 */ 3087 if (linked) { 3088 struct intel_plane_state *linked_new_plane_state; 3089 struct drm_rect *linked_sel_fetch_area; 3090 3091 linked_new_plane_state = intel_atomic_get_plane_state(state, linked); 3092 if (IS_ERR(linked_new_plane_state)) 3093 return PTR_ERR(linked_new_plane_state); 3094 3095 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; 3096 linked_sel_fetch_area->y1 = sel_fetch_area->y1; 3097 linked_sel_fetch_area->y2 = sel_fetch_area->y2; 3098 crtc_state->update_planes |= BIT(linked->id); 3099 } 3100 } 3101 3102 skip_sel_fetch_set_loop: 3103 if (full_update) 3104 clip_area_update(&crtc_state->psr2_su_area, &display_area, 3105 &display_area); 3106 3107 psr2_man_trk_ctl_calc(crtc_state, full_update); 3108 crtc_state->pipe_srcsz_early_tpt = 3109 psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); 3110 return 0; 3111 } 3112 3113 void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state) 3114 { 3115 struct intel_display *display = to_intel_display(crtc_state); 3116 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3117 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3118 u32 val = man_trk_ctl_enable_bit_get(display); 3119 3120 /* SF partial frame enable has to be set even on full update */ 3121 val |= man_trk_ctl_partial_frame_bit_get(display); 3122 val |= man_trk_ctl_continuos_full_frame(display); 3123 3124 /* Directly write the register */ 3125 intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val); 3126 3127 if (!crtc_state->enable_psr2_su_region_et) 3128 return; 3129 3130 intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); 3131 } 3132 3133 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 3134 struct intel_crtc *crtc) 3135 { 3136 struct intel_display *display = to_intel_display(state); 3137 const struct intel_crtc_state *old_crtc_state = 3138 intel_atomic_get_old_crtc_state(state, crtc); 3139 const struct intel_crtc_state *new_crtc_state = 3140 intel_atomic_get_new_crtc_state(state, crtc); 3141 struct intel_encoder *encoder; 3142 3143 if (!HAS_PSR(display)) 3144 return; 3145 3146 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3147 old_crtc_state->uapi.encoder_mask) { 3148 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3149 struct intel_psr *psr = &intel_dp->psr; 3150 3151 mutex_lock(&psr->lock); 3152 3153 if (!new_crtc_state->has_psr) 3154 psr->no_psr_reason = new_crtc_state->no_psr_reason; 3155 3156 if (psr->enabled) { 3157 /* 3158 * Reasons to disable: 3159 * - PSR disabled in new state 3160 * - All planes will go inactive 3161 * - Changing between PSR versions 3162 * - Region Early Transport changing 3163 * - Display WA #1136: skl, bxt 3164 */ 3165 if (intel_crtc_needs_modeset(new_crtc_state) || 3166 new_crtc_state->update_m_n || 3167 new_crtc_state->update_lrr || 3168 !new_crtc_state->has_psr || 3169 !new_crtc_state->active_planes || 3170 new_crtc_state->has_sel_update != psr->sel_update_enabled || 3171 new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || 3172 new_crtc_state->has_panel_replay != psr->panel_replay_enabled || 3173 (DISPLAY_VER(display) < 11 && new_crtc_state->wm_level_disabled)) 3174 intel_psr_disable_locked(intel_dp); 3175 else if (new_crtc_state->wm_level_disabled) 3176 /* Wa_14015648006 */ 3177 wm_optimization_wa(intel_dp, new_crtc_state); 3178 } 3179 3180 mutex_unlock(&psr->lock); 3181 } 3182 } 3183 3184 static void 3185 verify_panel_replay_dsc_state(const struct intel_crtc_state *crtc_state) 3186 { 3187 struct intel_display *display = to_intel_display(crtc_state); 3188 3189 if (!crtc_state->has_panel_replay) 3190 return; 3191 3192 drm_WARN_ON(display->drm, 3193 intel_dsc_enabled_on_link(crtc_state) && 3194 crtc_state->panel_replay_dsc_support == 3195 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED); 3196 } 3197 3198 void intel_psr_post_plane_update(struct intel_atomic_state *state, 3199 struct intel_crtc *crtc) 3200 { 3201 struct intel_display *display = to_intel_display(state); 3202 const struct intel_crtc_state *crtc_state = 3203 intel_atomic_get_new_crtc_state(state, crtc); 3204 struct intel_encoder *encoder; 3205 3206 if (!crtc_state->has_psr) 3207 return; 3208 3209 verify_panel_replay_dsc_state(crtc_state); 3210 3211 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, 3212 crtc_state->uapi.encoder_mask) { 3213 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3214 struct intel_psr *psr = &intel_dp->psr; 3215 bool keep_disabled = false; 3216 3217 mutex_lock(&psr->lock); 3218 3219 drm_WARN_ON(display->drm, 3220 psr->enabled && !crtc_state->active_planes); 3221 3222 if (psr->sink_not_reliable) 3223 keep_disabled = true; 3224 3225 if (!crtc_state->active_planes) { 3226 psr->no_psr_reason = "All planes inactive"; 3227 keep_disabled = true; 3228 } 3229 3230 /* Display WA #1136: skl, bxt */ 3231 if (DISPLAY_VER(display) < 11 && crtc_state->wm_level_disabled) { 3232 psr->no_psr_reason = "Workaround #1136 for skl, bxt"; 3233 keep_disabled = true; 3234 } 3235 3236 if (!psr->enabled && !keep_disabled) 3237 intel_psr_enable_locked(intel_dp, crtc_state); 3238 else if (psr->enabled && !crtc_state->wm_level_disabled) 3239 /* Wa_14015648006 */ 3240 wm_optimization_wa(intel_dp, crtc_state); 3241 3242 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ 3243 if (crtc_state->crc_enabled && psr->enabled) 3244 intel_psr_force_update(intel_dp); 3245 3246 /* 3247 * Clear possible busy bits in case we have 3248 * invalidate -> flip -> flush sequence. 3249 */ 3250 intel_dp->psr.busy_frontbuffer_bits = 0; 3251 3252 mutex_unlock(&psr->lock); 3253 } 3254 } 3255 3256 /* 3257 * From bspec: Panel Self Refresh (BDW+) 3258 * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of 3259 * exit training time + 1.5 ms of aux channel handshake. 50 ms is 3260 * defensive enough to cover everything. 3261 */ 3262 #define PSR_IDLE_TIMEOUT_MS 50 3263 3264 static int 3265 _psr2_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3266 struct intel_dsb *dsb) 3267 { 3268 struct intel_display *display = to_intel_display(new_crtc_state); 3269 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3270 3271 /* 3272 * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough. 3273 * As all higher states has bit 4 of PSR2 state set we can just wait for 3274 * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. 3275 */ 3276 if (dsb) { 3277 intel_dsb_poll(dsb, EDP_PSR2_STATUS(display, cpu_transcoder), 3278 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 0, 200, 3279 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3280 return true; 3281 } 3282 3283 return intel_de_wait_for_clear_ms(display, 3284 EDP_PSR2_STATUS(display, cpu_transcoder), 3285 EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 3286 PSR_IDLE_TIMEOUT_MS); 3287 } 3288 3289 static int 3290 _psr1_ready_for_pipe_update_locked(const struct intel_crtc_state *new_crtc_state, 3291 struct intel_dsb *dsb) 3292 { 3293 struct intel_display *display = to_intel_display(new_crtc_state); 3294 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 3295 3296 if (dsb) { 3297 intel_dsb_poll(dsb, psr_status_reg(display, cpu_transcoder), 3298 EDP_PSR_STATUS_STATE_MASK, 0, 200, 3299 PSR_IDLE_TIMEOUT_MS * 1000 / 200); 3300 return true; 3301 } 3302 3303 return intel_de_wait_for_clear_ms(display, 3304 psr_status_reg(display, cpu_transcoder), 3305 EDP_PSR_STATUS_STATE_MASK, 3306 PSR_IDLE_TIMEOUT_MS); 3307 } 3308 3309 /** 3310 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update 3311 * @new_crtc_state: new CRTC state 3312 * 3313 * This function is expected to be called from pipe_update_start() where it is 3314 * not expected to race with PSR enable or disable. 3315 */ 3316 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state) 3317 { 3318 struct intel_display *display = to_intel_display(new_crtc_state); 3319 struct intel_encoder *encoder; 3320 3321 if (!new_crtc_state->has_psr) 3322 return; 3323 3324 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3325 new_crtc_state->uapi.encoder_mask) { 3326 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3327 int ret; 3328 3329 lockdep_assert_held(&intel_dp->psr.lock); 3330 3331 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 3332 continue; 3333 3334 if (intel_dp->psr.sel_update_enabled) 3335 ret = _psr2_ready_for_pipe_update_locked(new_crtc_state, 3336 NULL); 3337 else 3338 ret = _psr1_ready_for_pipe_update_locked(new_crtc_state, 3339 NULL); 3340 3341 if (ret) 3342 drm_err(display->drm, 3343 "PSR wait timed out, atomic update may fail\n"); 3344 } 3345 } 3346 3347 void intel_psr_wait_for_idle_dsb(struct intel_dsb *dsb, 3348 const struct intel_crtc_state *new_crtc_state) 3349 { 3350 if (!new_crtc_state->has_psr || new_crtc_state->has_panel_replay) 3351 return; 3352 3353 if (new_crtc_state->has_sel_update) 3354 _psr2_ready_for_pipe_update_locked(new_crtc_state, dsb); 3355 else 3356 _psr1_ready_for_pipe_update_locked(new_crtc_state, dsb); 3357 } 3358 3359 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) 3360 { 3361 struct intel_display *display = to_intel_display(intel_dp); 3362 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3363 i915_reg_t reg; 3364 u32 mask; 3365 int err; 3366 3367 if (!intel_dp->psr.enabled) 3368 return false; 3369 3370 if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || 3371 intel_dp->psr.panel_replay_enabled)) { 3372 reg = EDP_PSR2_STATUS(display, cpu_transcoder); 3373 mask = EDP_PSR2_STATUS_STATE_MASK; 3374 } else { 3375 reg = psr_status_reg(display, cpu_transcoder); 3376 mask = EDP_PSR_STATUS_STATE_MASK; 3377 } 3378 3379 mutex_unlock(&intel_dp->psr.lock); 3380 3381 err = intel_de_wait_for_clear_ms(display, reg, mask, 50); 3382 if (err) 3383 drm_err(display->drm, 3384 "Timed out waiting for PSR Idle for re-enable\n"); 3385 3386 /* After the unlocked wait, verify that PSR is still wanted! */ 3387 mutex_lock(&intel_dp->psr.lock); 3388 return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter; 3389 } 3390 3391 static int intel_psr_fastset_force(struct intel_display *display) 3392 { 3393 struct drm_connector_list_iter conn_iter; 3394 struct drm_modeset_acquire_ctx ctx; 3395 struct drm_atomic_state *state; 3396 struct drm_connector *conn; 3397 int err = 0; 3398 3399 state = drm_atomic_state_alloc(display->drm); 3400 if (!state) 3401 return -ENOMEM; 3402 3403 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 3404 3405 state->acquire_ctx = &ctx; 3406 to_intel_atomic_state(state)->internal = true; 3407 3408 retry: 3409 drm_connector_list_iter_begin(display->drm, &conn_iter); 3410 drm_for_each_connector_iter(conn, &conn_iter) { 3411 struct drm_connector_state *conn_state; 3412 struct drm_crtc_state *crtc_state; 3413 3414 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) 3415 continue; 3416 3417 conn_state = drm_atomic_get_connector_state(state, conn); 3418 if (IS_ERR(conn_state)) { 3419 err = PTR_ERR(conn_state); 3420 break; 3421 } 3422 3423 if (!conn_state->crtc) 3424 continue; 3425 3426 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); 3427 if (IS_ERR(crtc_state)) { 3428 err = PTR_ERR(crtc_state); 3429 break; 3430 } 3431 3432 /* Mark mode as changed to trigger a pipe->update() */ 3433 crtc_state->mode_changed = true; 3434 } 3435 drm_connector_list_iter_end(&conn_iter); 3436 3437 if (err == 0) 3438 err = drm_atomic_commit(state); 3439 3440 if (err == -EDEADLK) { 3441 drm_atomic_state_clear(state); 3442 err = drm_modeset_backoff(&ctx); 3443 if (!err) 3444 goto retry; 3445 } 3446 3447 drm_modeset_drop_locks(&ctx); 3448 drm_modeset_acquire_fini(&ctx); 3449 drm_atomic_state_put(state); 3450 3451 return err; 3452 } 3453 3454 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) 3455 { 3456 struct intel_display *display = to_intel_display(intel_dp); 3457 const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; 3458 const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3459 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3460 u32 old_mode, old_disable_bits; 3461 int ret; 3462 3463 if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3464 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | 3465 I915_PSR_DEBUG_MODE_MASK) || 3466 mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { 3467 drm_dbg_kms(display->drm, "Invalid debug mask %llx\n", val); 3468 return -EINVAL; 3469 } 3470 3471 ret = mutex_lock_interruptible(&intel_dp->psr.lock); 3472 if (ret) 3473 return ret; 3474 3475 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; 3476 old_disable_bits = intel_dp->psr.debug & 3477 (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | 3478 I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); 3479 3480 intel_dp->psr.debug = val; 3481 3482 /* 3483 * Do it right away if it's already enabled, otherwise it will be done 3484 * when enabling the source. 3485 */ 3486 if (intel_dp->psr.enabled) 3487 psr_irq_control(intel_dp); 3488 3489 mutex_unlock(&intel_dp->psr.lock); 3490 3491 if (old_mode != mode || old_disable_bits != disable_bits) 3492 ret = intel_psr_fastset_force(display); 3493 3494 return ret; 3495 } 3496 3497 static void intel_psr_handle_irq(struct intel_dp *intel_dp) 3498 { 3499 struct intel_psr *psr = &intel_dp->psr; 3500 3501 intel_psr_disable_locked(intel_dp); 3502 psr->sink_not_reliable = true; 3503 /* let's make sure that sink is awaken */ 3504 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); 3505 } 3506 3507 static void intel_psr_work(struct work_struct *work) 3508 { 3509 struct intel_dp *intel_dp = 3510 container_of(work, typeof(*intel_dp), psr.work); 3511 3512 mutex_lock(&intel_dp->psr.lock); 3513 3514 if (!intel_dp->psr.enabled) 3515 goto unlock; 3516 3517 if (READ_ONCE(intel_dp->psr.irq_aux_error)) { 3518 intel_psr_handle_irq(intel_dp); 3519 goto unlock; 3520 } 3521 3522 if (intel_dp->psr.pause_counter) 3523 goto unlock; 3524 3525 /* 3526 * We have to make sure PSR is ready for re-enable 3527 * otherwise it keeps disabled until next full enable/disable cycle. 3528 * PSR might take some time to get fully disabled 3529 * and be ready for re-enable. 3530 */ 3531 if (!__psr_wait_for_idle_locked(intel_dp)) 3532 goto unlock; 3533 3534 /* 3535 * The delayed work can race with an invalidate hence we need to 3536 * recheck. Since psr_flush first clears this and then reschedules we 3537 * won't ever miss a flush when bailing out here. 3538 */ 3539 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) 3540 goto unlock; 3541 3542 intel_psr_activate(intel_dp); 3543 unlock: 3544 mutex_unlock(&intel_dp->psr.lock); 3545 } 3546 3547 static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) 3548 { 3549 struct intel_display *display = to_intel_display(intel_dp); 3550 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 3551 3552 if (!intel_dp->psr.psr2_sel_fetch_enabled) 3553 return; 3554 3555 if (DISPLAY_VER(display) >= 20) 3556 intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), 3557 LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); 3558 else 3559 intel_de_write(display, 3560 PSR2_MAN_TRK_CTL(display, cpu_transcoder), 3561 man_trk_ctl_enable_bit_get(display) | 3562 man_trk_ctl_partial_frame_bit_get(display) | 3563 man_trk_ctl_single_full_frame_bit_get(display) | 3564 man_trk_ctl_continuos_full_frame(display)); 3565 } 3566 3567 static void _psr_invalidate_handle(struct intel_dp *intel_dp) 3568 { 3569 struct intel_display *display = to_intel_display(intel_dp); 3570 3571 if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) { 3572 if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3573 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; 3574 intel_psr_configure_full_frame_update(intel_dp); 3575 } 3576 3577 intel_psr_force_update(intel_dp); 3578 } else { 3579 intel_psr_exit(intel_dp); 3580 } 3581 } 3582 3583 /** 3584 * intel_psr_invalidate - Invalidate PSR 3585 * @display: display device 3586 * @frontbuffer_bits: frontbuffer plane tracking bits 3587 * @origin: which operation caused the invalidate 3588 * 3589 * Since the hardware frontbuffer tracking has gaps we need to integrate 3590 * with the software frontbuffer tracking. This function gets called every 3591 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 3592 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 3593 * 3594 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 3595 */ 3596 void intel_psr_invalidate(struct intel_display *display, 3597 unsigned frontbuffer_bits, enum fb_op_origin origin) 3598 { 3599 struct intel_encoder *encoder; 3600 3601 if (origin == ORIGIN_FLIP) 3602 return; 3603 3604 for_each_intel_encoder_with_psr(display->drm, encoder) { 3605 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3606 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3607 3608 mutex_lock(&intel_dp->psr.lock); 3609 if (!intel_dp->psr.enabled) { 3610 mutex_unlock(&intel_dp->psr.lock); 3611 continue; 3612 } 3613 3614 pipe_frontbuffer_bits &= 3615 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3616 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; 3617 3618 if (pipe_frontbuffer_bits) 3619 _psr_invalidate_handle(intel_dp); 3620 3621 mutex_unlock(&intel_dp->psr.lock); 3622 } 3623 } 3624 /* 3625 * When we will be completely rely on PSR2 S/W tracking in future, 3626 * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP 3627 * event also therefore tgl_dc3co_flush_locked() require to be changed 3628 * accordingly in future. 3629 */ 3630 static void 3631 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, 3632 enum fb_op_origin origin) 3633 { 3634 struct intel_display *display = to_intel_display(intel_dp); 3635 3636 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || 3637 !intel_dp->psr.active) 3638 return; 3639 3640 /* 3641 * At every frontbuffer flush flip event modified delay of delayed work, 3642 * when delayed work schedules that means display has been idle. 3643 */ 3644 if (!(frontbuffer_bits & 3645 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) 3646 return; 3647 3648 tgl_psr2_enable_dc3co(intel_dp); 3649 mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work, 3650 intel_dp->psr.dc3co_exit_delay); 3651 } 3652 3653 static void _psr_flush_handle(struct intel_dp *intel_dp) 3654 { 3655 struct intel_display *display = to_intel_display(intel_dp); 3656 3657 if (DISPLAY_VER(display) >= 20) { 3658 /* 3659 * We can use PSR exit on LunarLake onwards. Also 3660 * using trans push mechanism to trigger Frame Change 3661 * event requires using PSR exit. 3662 */ 3663 intel_psr_exit(intel_dp); 3664 } else if (intel_dp->psr.psr2_sel_fetch_enabled) { 3665 /* Selective fetch prior LNL */ 3666 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { 3667 /* can we turn CFF off? */ 3668 if (intel_dp->psr.busy_frontbuffer_bits == 0) 3669 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; 3670 } 3671 3672 /* 3673 * Still keep cff bit enabled as we don't have proper SU 3674 * configuration in case update is sent for any reason after 3675 * sff bit gets cleared by the HW on next vblank. 3676 * 3677 * NOTE: Setting cff bit is not needed for LunarLake onwards as 3678 * we have own register for SFF bit and we are not overwriting 3679 * existing SU configuration 3680 */ 3681 intel_psr_configure_full_frame_update(intel_dp); 3682 3683 intel_psr_force_update(intel_dp); 3684 } else { 3685 /* 3686 * On older platforms using PSR exit was seen causing problems 3687 */ 3688 intel_psr_force_update(intel_dp); 3689 } 3690 3691 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) 3692 queue_work(display->wq.unordered, &intel_dp->psr.work); 3693 } 3694 3695 /** 3696 * intel_psr_flush - Flush PSR 3697 * @display: display device 3698 * @frontbuffer_bits: frontbuffer plane tracking bits 3699 * @origin: which operation caused the flush 3700 * 3701 * Since the hardware frontbuffer tracking has gaps we need to integrate 3702 * with the software frontbuffer tracking. This function gets called every 3703 * time frontbuffer rendering has completed and flushed out to memory. PSR 3704 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 3705 * 3706 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 3707 */ 3708 void intel_psr_flush(struct intel_display *display, 3709 unsigned frontbuffer_bits, enum fb_op_origin origin) 3710 { 3711 struct intel_encoder *encoder; 3712 3713 for_each_intel_encoder_with_psr(display->drm, encoder) { 3714 unsigned int pipe_frontbuffer_bits = frontbuffer_bits; 3715 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3716 3717 mutex_lock(&intel_dp->psr.lock); 3718 if (!intel_dp->psr.enabled) { 3719 mutex_unlock(&intel_dp->psr.lock); 3720 continue; 3721 } 3722 3723 pipe_frontbuffer_bits &= 3724 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); 3725 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; 3726 3727 /* 3728 * If the PSR is paused by an explicit intel_psr_paused() call, 3729 * we have to ensure that the PSR is not activated until 3730 * intel_psr_resume() is called. 3731 */ 3732 if (intel_dp->psr.pause_counter) 3733 goto unlock; 3734 3735 if (origin == ORIGIN_FLIP || 3736 (origin == ORIGIN_CURSOR_UPDATE && 3737 !intel_dp->psr.psr2_sel_fetch_enabled)) { 3738 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin); 3739 goto unlock; 3740 } 3741 3742 if (pipe_frontbuffer_bits == 0) 3743 goto unlock; 3744 3745 /* By definition flush = invalidate + flush */ 3746 _psr_flush_handle(intel_dp); 3747 unlock: 3748 mutex_unlock(&intel_dp->psr.lock); 3749 } 3750 } 3751 3752 /** 3753 * intel_psr_init - Init basic PSR work and mutex. 3754 * @intel_dp: Intel DP 3755 * 3756 * This function is called after the initializing connector. 3757 * (the initializing of connector treats the handling of connector capabilities) 3758 * And it initializes basic PSR stuff for each DP Encoder. 3759 */ 3760 void intel_psr_init(struct intel_dp *intel_dp) 3761 { 3762 struct intel_display *display = to_intel_display(intel_dp); 3763 struct intel_connector *connector = intel_dp->attached_connector; 3764 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3765 3766 if (!(HAS_PSR(display) || HAS_DP20(display))) 3767 return; 3768 3769 /* 3770 * HSW spec explicitly says PSR is tied to port A. 3771 * BDW+ platforms have a instance of PSR registers per transcoder but 3772 * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder 3773 * than eDP one. 3774 * For now it only supports one instance of PSR for BDW, GEN9 and GEN11. 3775 * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11. 3776 * But GEN12 supports a instance of PSR registers per transcoder. 3777 */ 3778 if (DISPLAY_VER(display) < 12 && dig_port->base.port != PORT_A) { 3779 drm_dbg_kms(display->drm, 3780 "PSR condition failed: Port not supported\n"); 3781 return; 3782 } 3783 3784 if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) || 3785 DISPLAY_VER(display) >= 20) 3786 intel_dp->psr.source_panel_replay_support = true; 3787 3788 if (HAS_PSR(display) && intel_dp_is_edp(intel_dp)) 3789 intel_dp->psr.source_support = true; 3790 3791 /* Set link_standby x link_off defaults */ 3792 if (DISPLAY_VER(display) < 12) 3793 /* For new platforms up to TGL let's respect VBT back again */ 3794 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; 3795 3796 INIT_WORK(&intel_dp->psr.work, intel_psr_work); 3797 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); 3798 mutex_init(&intel_dp->psr.lock); 3799 } 3800 3801 static int psr_get_status_and_error_status(struct intel_dp *intel_dp, 3802 u8 *status, u8 *error_status) 3803 { 3804 struct drm_dp_aux *aux = &intel_dp->aux; 3805 int ret; 3806 unsigned int offset; 3807 3808 offset = intel_dp->psr.panel_replay_enabled ? 3809 DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS; 3810 3811 ret = drm_dp_dpcd_readb(aux, offset, status); 3812 if (ret != 1) 3813 return ret; 3814 3815 offset = intel_dp->psr.panel_replay_enabled ? 3816 DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS; 3817 3818 ret = drm_dp_dpcd_readb(aux, offset, error_status); 3819 if (ret != 1) 3820 return ret; 3821 3822 *status = *status & DP_PSR_SINK_STATE_MASK; 3823 3824 return 0; 3825 } 3826 3827 static void psr_alpm_check(struct intel_dp *intel_dp) 3828 { 3829 struct intel_psr *psr = &intel_dp->psr; 3830 3831 if (!psr->sel_update_enabled) 3832 return; 3833 3834 if (intel_alpm_get_error(intel_dp)) { 3835 intel_psr_disable_locked(intel_dp); 3836 psr->sink_not_reliable = true; 3837 } 3838 } 3839 3840 static void psr_capability_changed_check(struct intel_dp *intel_dp) 3841 { 3842 struct intel_display *display = to_intel_display(intel_dp); 3843 struct intel_psr *psr = &intel_dp->psr; 3844 u8 val; 3845 int r; 3846 3847 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); 3848 if (r != 1) { 3849 drm_err(display->drm, "Error reading DP_PSR_ESI\n"); 3850 return; 3851 } 3852 3853 if (val & DP_PSR_CAPS_CHANGE) { 3854 intel_psr_disable_locked(intel_dp); 3855 psr->sink_not_reliable = true; 3856 drm_dbg_kms(display->drm, 3857 "Sink PSR capability changed, disabling PSR\n"); 3858 3859 /* Clearing it */ 3860 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); 3861 } 3862 } 3863 3864 /* 3865 * On common bits: 3866 * DP_PSR_RFB_STORAGE_ERROR == DP_PANEL_REPLAY_RFB_STORAGE_ERROR 3867 * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR == DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR 3868 * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR 3869 * this function is relying on PSR definitions 3870 */ 3871 void intel_psr_short_pulse(struct intel_dp *intel_dp) 3872 { 3873 struct intel_display *display = to_intel_display(intel_dp); 3874 struct intel_psr *psr = &intel_dp->psr; 3875 u8 status, error_status; 3876 const u8 errors = DP_PSR_RFB_STORAGE_ERROR | 3877 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 3878 DP_PSR_LINK_CRC_ERROR; 3879 3880 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) 3881 return; 3882 3883 mutex_lock(&psr->lock); 3884 3885 psr->link_ok = false; 3886 3887 if (!psr->enabled) 3888 goto exit; 3889 3890 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { 3891 drm_err(display->drm, 3892 "Error reading PSR status or error status\n"); 3893 goto exit; 3894 } 3895 3896 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) || 3897 (error_status & errors)) { 3898 intel_psr_disable_locked(intel_dp); 3899 psr->sink_not_reliable = true; 3900 } 3901 3902 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR && 3903 !error_status) 3904 drm_dbg_kms(display->drm, 3905 "PSR sink internal error, disabling PSR\n"); 3906 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 3907 drm_dbg_kms(display->drm, 3908 "PSR RFB storage error, disabling PSR\n"); 3909 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 3910 drm_dbg_kms(display->drm, 3911 "PSR VSC SDP uncorrectable error, disabling PSR\n"); 3912 if (error_status & DP_PSR_LINK_CRC_ERROR) 3913 drm_dbg_kms(display->drm, 3914 "PSR Link CRC error, disabling PSR\n"); 3915 3916 if (error_status & ~errors) 3917 drm_err(display->drm, 3918 "PSR_ERROR_STATUS unhandled errors %x\n", 3919 error_status & ~errors); 3920 /* clear status register */ 3921 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); 3922 3923 if (!psr->panel_replay_enabled) { 3924 psr_alpm_check(intel_dp); 3925 psr_capability_changed_check(intel_dp); 3926 } 3927 3928 exit: 3929 mutex_unlock(&psr->lock); 3930 } 3931 3932 bool intel_psr_enabled(struct intel_dp *intel_dp) 3933 { 3934 bool ret; 3935 3936 if (!CAN_PSR(intel_dp)) 3937 return false; 3938 3939 mutex_lock(&intel_dp->psr.lock); 3940 ret = intel_dp->psr.enabled; 3941 mutex_unlock(&intel_dp->psr.lock); 3942 3943 return ret; 3944 } 3945 3946 /** 3947 * intel_psr_link_ok - return psr->link_ok 3948 * @intel_dp: struct intel_dp 3949 * 3950 * We are seeing unexpected link re-trainings with some panels. This is caused 3951 * by panel stating bad link status after PSR is enabled. Code checking link 3952 * status can call this to ensure it can ignore bad link status stated by the 3953 * panel I.e. if panel is stating bad link and intel_psr_link_ok is stating link 3954 * is ok caller should rely on latter. 3955 * 3956 * Return value of link_ok 3957 */ 3958 bool intel_psr_link_ok(struct intel_dp *intel_dp) 3959 { 3960 bool ret; 3961 3962 if ((!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp)) || 3963 !intel_dp_is_edp(intel_dp)) 3964 return false; 3965 3966 mutex_lock(&intel_dp->psr.lock); 3967 ret = intel_dp->psr.link_ok; 3968 mutex_unlock(&intel_dp->psr.lock); 3969 3970 return ret; 3971 } 3972 3973 /** 3974 * intel_psr_lock - grab PSR lock 3975 * @crtc_state: the crtc state 3976 * 3977 * This is initially meant to be used by around CRTC update, when 3978 * vblank sensitive registers are updated and we need grab the lock 3979 * before it to avoid vblank evasion. 3980 */ 3981 void intel_psr_lock(const struct intel_crtc_state *crtc_state) 3982 { 3983 struct intel_display *display = to_intel_display(crtc_state); 3984 struct intel_encoder *encoder; 3985 3986 if (!crtc_state->has_psr) 3987 return; 3988 3989 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 3990 crtc_state->uapi.encoder_mask) { 3991 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3992 3993 mutex_lock(&intel_dp->psr.lock); 3994 break; 3995 } 3996 } 3997 3998 /** 3999 * intel_psr_unlock - release PSR lock 4000 * @crtc_state: the crtc state 4001 * 4002 * Release the PSR lock that was held during pipe update. 4003 */ 4004 void intel_psr_unlock(const struct intel_crtc_state *crtc_state) 4005 { 4006 struct intel_display *display = to_intel_display(crtc_state); 4007 struct intel_encoder *encoder; 4008 4009 if (!crtc_state->has_psr) 4010 return; 4011 4012 for_each_intel_encoder_mask_with_psr(display->drm, encoder, 4013 crtc_state->uapi.encoder_mask) { 4014 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4015 4016 mutex_unlock(&intel_dp->psr.lock); 4017 break; 4018 } 4019 } 4020 4021 /* Wa_16025596647 */ 4022 static void intel_psr_apply_underrun_on_idle_wa_locked(struct intel_dp *intel_dp) 4023 { 4024 struct intel_display *display = to_intel_display(intel_dp); 4025 bool dc5_dc6_blocked; 4026 4027 if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used) 4028 return; 4029 4030 dc5_dc6_blocked = is_dc5_dc6_blocked(intel_dp); 4031 4032 if (intel_dp->psr.sel_update_enabled) 4033 psr2_program_idle_frames(intel_dp, dc5_dc6_blocked ? 0 : 4034 psr_compute_idle_frames(intel_dp)); 4035 else 4036 intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(display, 4037 intel_dp->psr.pipe, 4038 dc5_dc6_blocked); 4039 } 4040 4041 static void psr_dc5_dc6_wa_work(struct work_struct *work) 4042 { 4043 struct intel_display *display = container_of(work, typeof(*display), 4044 psr_dc5_dc6_wa_work); 4045 struct intel_encoder *encoder; 4046 4047 for_each_intel_encoder_with_psr(display->drm, encoder) { 4048 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4049 4050 mutex_lock(&intel_dp->psr.lock); 4051 4052 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4053 !intel_dp->psr.pkg_c_latency_used) 4054 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4055 4056 mutex_unlock(&intel_dp->psr.lock); 4057 } 4058 } 4059 4060 /** 4061 * intel_psr_notify_dc5_dc6 - Notify PSR about enable/disable dc5/dc6 4062 * @display: intel atomic state 4063 * 4064 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to schedule 4065 * psr_dc5_dc6_wa_work used for applying/removing the workaround. 4066 */ 4067 void intel_psr_notify_dc5_dc6(struct intel_display *display) 4068 { 4069 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4070 return; 4071 4072 schedule_work(&display->psr_dc5_dc6_wa_work); 4073 } 4074 4075 /** 4076 * intel_psr_dc5_dc6_wa_init - Init work for underrun on idle PSR HW bug wa 4077 * @display: intel atomic state 4078 * 4079 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to init 4080 * psr_dc5_dc6_wa_work used for applying the workaround. 4081 */ 4082 void intel_psr_dc5_dc6_wa_init(struct intel_display *display) 4083 { 4084 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4085 return; 4086 4087 INIT_WORK(&display->psr_dc5_dc6_wa_work, psr_dc5_dc6_wa_work); 4088 } 4089 4090 /** 4091 * intel_psr_notify_pipe_change - Notify PSR about enable/disable of a pipe 4092 * @state: intel atomic state 4093 * @crtc: intel crtc 4094 * @enable: enable/disable 4095 * 4096 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4097 * remove the workaround when pipe is getting enabled/disabled 4098 */ 4099 void intel_psr_notify_pipe_change(struct intel_atomic_state *state, 4100 struct intel_crtc *crtc, bool enable) 4101 { 4102 struct intel_display *display = to_intel_display(state); 4103 struct intel_encoder *encoder; 4104 4105 if (!intel_display_wa(display, INTEL_DISPLAY_WA_16025596647)) 4106 return; 4107 4108 for_each_intel_encoder_with_psr(display->drm, encoder) { 4109 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4110 u8 active_non_psr_pipes; 4111 4112 mutex_lock(&intel_dp->psr.lock); 4113 4114 if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled) 4115 goto unlock; 4116 4117 active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes; 4118 4119 if (enable) 4120 active_non_psr_pipes |= BIT(crtc->pipe); 4121 else 4122 active_non_psr_pipes &= ~BIT(crtc->pipe); 4123 4124 if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes) 4125 goto unlock; 4126 4127 if ((enable && intel_dp->psr.active_non_psr_pipes) || 4128 (!enable && !intel_dp->psr.active_non_psr_pipes) || 4129 !intel_dp->psr.pkg_c_latency_used) { 4130 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4131 goto unlock; 4132 } 4133 4134 intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes; 4135 4136 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4137 unlock: 4138 mutex_unlock(&intel_dp->psr.lock); 4139 } 4140 } 4141 4142 /** 4143 * intel_psr_notify_vblank_enable_disable - Notify PSR about enable/disable of vblank 4144 * @display: intel display struct 4145 * @enable: enable/disable 4146 * 4147 * This is targeted for underrun on idle PSR HW bug (Wa_16025596647) to apply 4148 * remove the workaround when vblank is getting enabled/disabled 4149 */ 4150 void intel_psr_notify_vblank_enable_disable(struct intel_display *display, 4151 bool enable) 4152 { 4153 struct intel_encoder *encoder; 4154 4155 for_each_intel_encoder_with_psr(display->drm, encoder) { 4156 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4157 4158 mutex_lock(&intel_dp->psr.lock); 4159 if (CAN_PANEL_REPLAY(intel_dp)) { 4160 if (enable) 4161 intel_dp->psr.vblank_wakeref = 4162 intel_display_power_get(display, 4163 POWER_DOMAIN_DC_OFF); 4164 else 4165 intel_display_power_put(display, POWER_DOMAIN_DC_OFF, 4166 intel_dp->psr.vblank_wakeref); 4167 } 4168 4169 if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled && 4170 intel_dp->psr.pkg_c_latency_used) 4171 intel_psr_apply_underrun_on_idle_wa_locked(intel_dp); 4172 4173 mutex_unlock(&intel_dp->psr.lock); 4174 } 4175 } 4176 4177 static void 4178 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) 4179 { 4180 struct intel_display *display = to_intel_display(intel_dp); 4181 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4182 const char *status = "unknown"; 4183 u32 val, status_val; 4184 4185 if ((intel_dp_is_edp(intel_dp) || DISPLAY_VER(display) >= 30) && 4186 (intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) { 4187 static const char * const live_status[] = { 4188 "IDLE", 4189 "CAPTURE", 4190 "CAPTURE_FS", 4191 "SLEEP", 4192 "BUFON_FW", 4193 "ML_UP", 4194 "SU_STANDBY", 4195 "FAST_SLEEP", 4196 "DEEP_SLEEP", 4197 "BUF_ON", 4198 "TG_ON" 4199 }; 4200 val = intel_de_read(display, 4201 EDP_PSR2_STATUS(display, cpu_transcoder)); 4202 status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); 4203 if (status_val < ARRAY_SIZE(live_status)) 4204 status = live_status[status_val]; 4205 } else { 4206 static const char * const live_status[] = { 4207 "IDLE", 4208 "SRDONACK", 4209 "SRDENT", 4210 "BUFOFF", 4211 "BUFON", 4212 "AUXACK", 4213 "SRDOFFACK", 4214 "SRDENT_ON", 4215 }; 4216 val = intel_de_read(display, 4217 psr_status_reg(display, cpu_transcoder)); 4218 status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); 4219 if (status_val < ARRAY_SIZE(live_status)) 4220 status = live_status[status_val]; 4221 } 4222 4223 seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); 4224 } 4225 4226 static void intel_psr_sink_capability(struct intel_connector *connector, 4227 struct seq_file *m) 4228 { 4229 seq_printf(m, "Sink support: PSR = %s", 4230 str_yes_no(connector->dp.psr_caps.support)); 4231 4232 if (connector->dp.psr_caps.support) 4233 seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]); 4234 if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4235 seq_printf(m, " (Early Transport)"); 4236 seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support)); 4237 seq_printf(m, ", Panel Replay Selective Update = %s", 4238 str_yes_no(connector->dp.panel_replay_caps.su_support)); 4239 seq_printf(m, ", Panel Replay DSC support = %s", 4240 panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 4241 if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4242 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) 4243 seq_printf(m, " (Early Transport)"); 4244 seq_printf(m, "\n"); 4245 } 4246 4247 static void intel_psr_print_mode(struct intel_dp *intel_dp, 4248 struct seq_file *m) 4249 { 4250 struct intel_psr *psr = &intel_dp->psr; 4251 const char *status, *mode, *region_et; 4252 4253 if (psr->enabled) 4254 status = " enabled"; 4255 else 4256 status = "disabled"; 4257 4258 if (psr->panel_replay_enabled && psr->sel_update_enabled) 4259 mode = "Panel Replay Selective Update"; 4260 else if (psr->panel_replay_enabled) 4261 mode = "Panel Replay"; 4262 else if (psr->sel_update_enabled) 4263 mode = "PSR2"; 4264 else if (psr->enabled) 4265 mode = "PSR1"; 4266 else 4267 mode = ""; 4268 4269 if (psr->su_region_et_enabled) 4270 region_et = " (Early Transport)"; 4271 else 4272 region_et = ""; 4273 4274 seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); 4275 if (psr->no_psr_reason) 4276 seq_printf(m, " %s\n", psr->no_psr_reason); 4277 } 4278 4279 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp, 4280 struct intel_connector *connector) 4281 { 4282 struct intel_display *display = to_intel_display(intel_dp); 4283 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; 4284 struct intel_psr *psr = &intel_dp->psr; 4285 struct ref_tracker *wakeref; 4286 bool enabled; 4287 u32 val, psr2_ctl; 4288 4289 intel_psr_sink_capability(connector, m); 4290 4291 if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support)) 4292 return 0; 4293 4294 wakeref = intel_display_rpm_get(display); 4295 mutex_lock(&psr->lock); 4296 4297 intel_psr_print_mode(intel_dp, m); 4298 4299 if (!psr->enabled) { 4300 seq_printf(m, "PSR sink not reliable: %s\n", 4301 str_yes_no(psr->sink_not_reliable)); 4302 4303 goto unlock; 4304 } 4305 4306 if (psr->panel_replay_enabled) { 4307 val = intel_de_read(display, TRANS_DP2_CTL(cpu_transcoder)); 4308 4309 if (intel_dp_is_edp(intel_dp)) 4310 psr2_ctl = intel_de_read(display, 4311 EDP_PSR2_CTL(display, 4312 cpu_transcoder)); 4313 4314 enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; 4315 } else if (psr->sel_update_enabled) { 4316 val = intel_de_read(display, 4317 EDP_PSR2_CTL(display, cpu_transcoder)); 4318 enabled = val & EDP_PSR2_ENABLE; 4319 } else { 4320 val = intel_de_read(display, psr_ctl_reg(display, cpu_transcoder)); 4321 enabled = val & EDP_PSR_ENABLE; 4322 } 4323 seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n", 4324 str_enabled_disabled(enabled), val); 4325 if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) 4326 seq_printf(m, "PSR2_CTL: 0x%08x\n", 4327 psr2_ctl); 4328 psr_source_status(intel_dp, m); 4329 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", 4330 psr->busy_frontbuffer_bits); 4331 4332 /* 4333 * SKL+ Perf counter is reset to 0 everytime DC state is entered 4334 */ 4335 val = intel_de_read(display, psr_perf_cnt_reg(display, cpu_transcoder)); 4336 seq_printf(m, "Performance counter: %u\n", 4337 REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val)); 4338 4339 if (psr->debug & I915_PSR_DEBUG_IRQ) { 4340 seq_printf(m, "Last attempted entry at: %lld\n", 4341 psr->last_entry_attempt); 4342 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); 4343 } 4344 4345 if (psr->sel_update_enabled) { 4346 u32 su_frames_val[3]; 4347 int frame; 4348 4349 /* 4350 * PSR2_SU_STATUS register has been tied-off since DG2/ADL-P 4351 * (it returns zeros only) and it has been removed on Xe2_LPD. 4352 */ 4353 if (DISPLAY_VER(display) < 13) { 4354 /* 4355 * Reading all 3 registers before hand to minimize crossing a 4356 * frame boundary between register reads 4357 */ 4358 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { 4359 val = intel_de_read(display, 4360 PSR2_SU_STATUS(display, cpu_transcoder, frame)); 4361 su_frames_val[frame / 3] = val; 4362 } 4363 4364 seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); 4365 4366 for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { 4367 u32 su_blocks; 4368 4369 su_blocks = su_frames_val[frame / 3] & 4370 PSR2_SU_STATUS_MASK(frame); 4371 su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); 4372 seq_printf(m, "%d\t%d\n", frame, su_blocks); 4373 } 4374 } 4375 4376 seq_printf(m, "PSR2 selective fetch: %s\n", 4377 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); 4378 } 4379 4380 unlock: 4381 mutex_unlock(&psr->lock); 4382 intel_display_rpm_put(display, wakeref); 4383 4384 return 0; 4385 } 4386 4387 static int i915_edp_psr_status_show(struct seq_file *m, void *data) 4388 { 4389 struct intel_display *display = m->private; 4390 struct intel_dp *intel_dp = NULL; 4391 struct intel_encoder *encoder; 4392 4393 if (!HAS_PSR(display)) 4394 return -ENODEV; 4395 4396 /* Find the first EDP which supports PSR */ 4397 for_each_intel_encoder_with_psr(display->drm, encoder) { 4398 intel_dp = enc_to_intel_dp(encoder); 4399 break; 4400 } 4401 4402 if (!intel_dp) 4403 return -ENODEV; 4404 4405 return intel_psr_status(m, intel_dp, intel_dp->attached_connector); 4406 } 4407 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); 4408 4409 static int 4410 i915_edp_psr_debug_set(void *data, u64 val) 4411 { 4412 struct intel_display *display = data; 4413 struct intel_encoder *encoder; 4414 int ret = -ENODEV; 4415 4416 if (!HAS_PSR(display)) 4417 return ret; 4418 4419 for_each_intel_encoder_with_psr(display->drm, encoder) { 4420 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4421 4422 drm_dbg_kms(display->drm, "Setting PSR debug to %llx\n", val); 4423 4424 // TODO: split to each transcoder's PSR debug state 4425 with_intel_display_rpm(display) 4426 ret = intel_psr_debug_set(intel_dp, val); 4427 } 4428 4429 return ret; 4430 } 4431 4432 static int 4433 i915_edp_psr_debug_get(void *data, u64 *val) 4434 { 4435 struct intel_display *display = data; 4436 struct intel_encoder *encoder; 4437 4438 if (!HAS_PSR(display)) 4439 return -ENODEV; 4440 4441 for_each_intel_encoder_with_psr(display->drm, encoder) { 4442 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4443 4444 // TODO: split to each transcoder's PSR debug state 4445 *val = READ_ONCE(intel_dp->psr.debug); 4446 return 0; 4447 } 4448 4449 return -ENODEV; 4450 } 4451 4452 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, 4453 i915_edp_psr_debug_get, i915_edp_psr_debug_set, 4454 "%llu\n"); 4455 4456 void intel_psr_debugfs_register(struct intel_display *display) 4457 { 4458 struct dentry *debugfs_root = display->drm->debugfs_root; 4459 4460 debugfs_create_file("i915_edp_psr_debug", 0644, debugfs_root, 4461 display, &i915_edp_psr_debug_fops); 4462 4463 debugfs_create_file("i915_edp_psr_status", 0444, debugfs_root, 4464 display, &i915_edp_psr_status_fops); 4465 } 4466 4467 static const char *psr_mode_str(struct intel_dp *intel_dp) 4468 { 4469 if (intel_dp->psr.panel_replay_enabled) 4470 return "PANEL-REPLAY"; 4471 else if (intel_dp->psr.enabled) 4472 return "PSR"; 4473 4474 return "unknown"; 4475 } 4476 4477 static int i915_psr_sink_status_show(struct seq_file *m, void *data) 4478 { 4479 struct intel_connector *connector = m->private; 4480 struct intel_dp *intel_dp = intel_attached_dp(connector); 4481 static const char * const sink_status[] = { 4482 "inactive", 4483 "transition to active, capture and display", 4484 "active, display from RFB", 4485 "active, capture and display on sink device timings", 4486 "transition to inactive, capture and display, timing re-sync", 4487 "reserved", 4488 "reserved", 4489 "sink internal error", 4490 }; 4491 const char *str; 4492 int ret; 4493 u8 status, error_status; 4494 4495 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) { 4496 seq_puts(m, "PSR/Panel-Replay Unsupported\n"); 4497 return -ENODEV; 4498 } 4499 4500 if (connector->base.status != connector_status_connected) 4501 return -ENODEV; 4502 4503 ret = psr_get_status_and_error_status(intel_dp, &status, &error_status); 4504 if (ret) 4505 return ret; 4506 4507 status &= DP_PSR_SINK_STATE_MASK; 4508 if (status < ARRAY_SIZE(sink_status)) 4509 str = sink_status[status]; 4510 else 4511 str = "unknown"; 4512 4513 seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str); 4514 4515 seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status); 4516 4517 if (error_status & (DP_PSR_RFB_STORAGE_ERROR | 4518 DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR | 4519 DP_PSR_LINK_CRC_ERROR)) 4520 seq_puts(m, ":\n"); 4521 else 4522 seq_puts(m, "\n"); 4523 if (error_status & DP_PSR_RFB_STORAGE_ERROR) 4524 seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp)); 4525 if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) 4526 seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp)); 4527 if (error_status & DP_PSR_LINK_CRC_ERROR) 4528 seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp)); 4529 4530 return ret; 4531 } 4532 DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); 4533 4534 static int i915_psr_status_show(struct seq_file *m, void *data) 4535 { 4536 struct intel_connector *connector = m->private; 4537 struct intel_dp *intel_dp = intel_attached_dp(connector); 4538 4539 return intel_psr_status(m, intel_dp, connector); 4540 } 4541 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 4542 4543 void intel_psr_connector_debugfs_add(struct intel_connector *connector) 4544 { 4545 struct intel_display *display = to_intel_display(connector); 4546 struct dentry *root = connector->base.debugfs_entry; 4547 4548 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && 4549 connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) 4550 return; 4551 4552 debugfs_create_file("i915_psr_sink_status", 0444, root, 4553 connector, &i915_psr_sink_status_fops); 4554 4555 if (HAS_PSR(display) || HAS_DP20(display)) 4556 debugfs_create_file("i915_psr_status", 0444, root, 4557 connector, &i915_psr_status_fops); 4558 } 4559 4560 bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) 4561 { 4562 /* 4563 * eDP Panel Replay uses always ALPM 4564 * PSR2 uses ALPM but PSR1 doesn't 4565 */ 4566 return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update || 4567 crtc_state->has_panel_replay); 4568 } 4569 4570 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, 4571 const struct intel_crtc_state *crtc_state) 4572 { 4573 return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay; 4574 } 4575 4576 void intel_psr_compute_config_late(struct intel_dp *intel_dp, 4577 struct intel_crtc_state *crtc_state) 4578 { 4579 struct intel_display *display = to_intel_display(intel_dp); 4580 int vblank = intel_crtc_vblank_length(crtc_state); 4581 int wake_lines; 4582 4583 if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)) 4584 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4585 else if (intel_psr_needs_alpm(intel_dp, crtc_state)) 4586 wake_lines = DISPLAY_VER(display) < 20 ? 4587 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4588 crtc_state->alpm_state.fast_wake_lines) : 4589 crtc_state->alpm_state.io_wake_lines; 4590 else 4591 wake_lines = 0; 4592 4593 /* 4594 * Disable the PSR features if wake lines exceed the available vblank. 4595 * Though SCL is computed based on these PSR features, it is not reset 4596 * even if the PSR features are disabled to avoid changing vblank start 4597 * at this stage. 4598 */ 4599 if (wake_lines && !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) { 4600 drm_dbg_kms(display->drm, 4601 "Adjusting PSR/PR mode: vblank too short for wake lines = %d\n", 4602 wake_lines); 4603 4604 if (crtc_state->has_panel_replay) { 4605 crtc_state->has_panel_replay = false; 4606 /* 4607 * #TODO : Add fall back to PSR/PSR2 4608 * Since panel replay cannot be supported, we can fall back to PSR/PSR2. 4609 * This will require calling compute_config for psr and psr2 with check for 4610 * actual guardband instead of vblank_length. 4611 */ 4612 crtc_state->has_psr = false; 4613 } 4614 4615 crtc_state->has_sel_update = false; 4616 crtc_state->enable_psr2_su_region_et = false; 4617 crtc_state->enable_psr2_sel_fetch = false; 4618 } 4619 4620 /* Wa_18037818876 */ 4621 if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { 4622 crtc_state->has_psr = false; 4623 drm_dbg_kms(display->drm, 4624 "PSR disabled to workaround PSR FSM hang issue\n"); 4625 } 4626 4627 intel_psr_set_non_psr_pipes(intel_dp, crtc_state); 4628 } 4629 4630 int intel_psr_min_guardband(struct intel_crtc_state *crtc_state) 4631 { 4632 struct intel_display *display = to_intel_display(crtc_state); 4633 int psr_min_guardband; 4634 int wake_lines; 4635 4636 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 4637 return 0; 4638 4639 if (crtc_state->has_panel_replay) 4640 wake_lines = crtc_state->alpm_state.aux_less_wake_lines; 4641 else if (crtc_state->has_sel_update) 4642 wake_lines = DISPLAY_VER(display) < 20 ? 4643 psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines, 4644 crtc_state->alpm_state.fast_wake_lines) : 4645 crtc_state->alpm_state.io_wake_lines; 4646 else 4647 return 0; 4648 4649 psr_min_guardband = wake_lines + crtc_state->set_context_latency; 4650 4651 if (crtc_state->req_psr2_sdp_prior_scanline) 4652 psr_min_guardband++; 4653 4654 return psr_min_guardband; 4655 } 4656 4657 bool intel_psr_use_trans_push(const struct intel_crtc_state *crtc_state) 4658 { 4659 struct intel_display *display = to_intel_display(crtc_state); 4660 4661 return HAS_PSR_TRANS_PUSH_FRAME_CHANGE(display) && crtc_state->has_psr; 4662 } 4663