1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright (c) 2016-2017 Hisilicon Limited. 3 4 #include <linux/acpi.h> 5 #include <linux/device.h> 6 #include <linux/etherdevice.h> 7 #include <linux/init.h> 8 #include <linux/interrupt.h> 9 #include <linux/irq.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/pci.h> 14 #include <linux/platform_device.h> 15 #include <linux/if_vlan.h> 16 #include <linux/crash_dump.h> 17 18 #include <net/rtnetlink.h> 19 #include "hclge_cmd.h" 20 #include "hclge_dcb.h" 21 #include "hclge_fd.h" 22 #include "hclge_main.h" 23 #include "hclge_mbx.h" 24 #include "hclge_mdio.h" 25 #include "hclge_regs.h" 26 #include "hclge_tm.h" 27 #include "hclge_err.h" 28 #include "hnae3.h" 29 #include "hclge_devlink.h" 30 #include "hclge_comm_cmd.h" 31 32 #include "hclge_trace.h" 33 34 #define HCLGE_NAME "hclge" 35 36 #define HCLGE_BUF_SIZE_UNIT 256U 37 #define HCLGE_BUF_MUL_BY 2 38 #define HCLGE_BUF_DIV_BY 2 39 #define NEED_RESERVE_TC_NUM 2 40 #define BUF_MAX_PERCENT 100 41 #define BUF_RESERVE_PERCENT 90 42 43 #define HCLGE_RESET_MAX_FAIL_CNT 5 44 #define HCLGE_RESET_SYNC_TIME 100 45 #define HCLGE_PF_RESET_SYNC_TIME 20 46 #define HCLGE_PF_RESET_SYNC_CNT 1500 47 48 #define HCLGE_LINK_STATUS_MS 10 49 50 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps); 51 static int hclge_init_vlan_config(struct hclge_dev *hdev); 52 static void hclge_sync_vlan_filter(struct hclge_dev *hdev); 53 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); 54 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle); 55 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 56 unsigned long *addr); 57 static int hclge_set_default_loopback(struct hclge_dev *hdev); 58 59 static void hclge_sync_mac_table(struct hclge_dev *hdev); 60 static void hclge_restore_hw_table(struct hclge_dev *hdev); 61 static void hclge_sync_promisc_mode(struct hclge_dev *hdev); 62 static void hclge_update_fec_stats(struct hclge_dev *hdev); 63 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 64 int wait_cnt); 65 static int hclge_update_port_info(struct hclge_dev *hdev); 66 67 static struct hnae3_ae_algo ae_algo; 68 69 static struct workqueue_struct *hclge_wq; 70 71 static const struct pci_device_id ae_algo_pci_tbl[] = { 72 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE) }, 73 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE) }, 74 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA) }, 75 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC) }, 76 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA) }, 77 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC) }, 78 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC) }, 79 { PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA) }, 80 /* required last entry */ 81 { } 82 }; 83 84 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); 85 86 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { 87 "External Loopback test", 88 "App Loopback test", 89 "Serdes serial Loopback test", 90 "Serdes parallel Loopback test", 91 "Phy Loopback test" 92 }; 93 94 static const struct hclge_comm_stats_str g_mac_stats_string[] = { 95 {"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 96 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, 97 {"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1, 98 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, 99 {"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 100 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)}, 101 {"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 102 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)}, 103 {"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 104 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)}, 105 {"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 106 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)}, 107 {"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 108 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)}, 109 {"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, 111 {"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, 113 {"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, 115 {"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, 117 {"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, 119 {"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, 121 {"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, 123 {"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, 125 {"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)}, 127 {"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)}, 129 {"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)}, 131 {"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)}, 133 {"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)}, 135 {"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)}, 137 {"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)}, 139 {"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)}, 141 {"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 142 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)}, 143 {"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 144 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, 145 {"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, 147 {"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, 149 {"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, 151 {"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, 153 {"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, 155 {"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, 157 {"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, 159 {"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)}, 161 {"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)}, 163 {"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)}, 165 {"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)}, 167 {"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)}, 169 {"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)}, 171 {"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)}, 173 {"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2, 174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)}, 175 {"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 176 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, 177 {"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 178 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, 179 {"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 180 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, 181 {"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 182 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, 183 {"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 184 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, 185 {"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 186 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, 187 {"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 188 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, 189 {"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 190 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, 191 {"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 192 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, 193 {"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 194 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, 195 {"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 196 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, 197 {"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 198 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, 199 {"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 200 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, 201 {"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 202 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, 203 {"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 204 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, 205 {"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 206 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, 207 {"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 208 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, 209 {"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 210 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, 211 {"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 212 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, 213 {"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 214 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, 215 {"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 216 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, 217 {"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 218 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, 219 {"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 220 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, 221 {"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 222 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, 223 {"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 224 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, 225 {"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 226 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, 227 {"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, 229 {"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 230 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, 231 {"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 232 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, 233 {"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 234 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, 235 {"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1, 236 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, 237 {"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 238 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, 239 {"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 240 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, 241 {"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 242 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, 243 {"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 244 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, 245 {"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, 247 {"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, 249 {"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, 251 {"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, 253 {"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, 255 {"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, 257 {"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, 259 {"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, 261 {"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 262 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, 263 {"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 264 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, 265 {"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 266 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, 267 {"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 268 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, 269 {"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 270 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, 271 {"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 272 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, 273 {"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 274 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, 275 276 {"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, 278 {"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, 280 {"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, 282 {"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, 284 {"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, 286 {"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, 288 {"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 289 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, 290 {"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 291 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, 292 {"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 293 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, 294 {"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 295 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, 296 {"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, 298 {"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1, 299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} 300 }; 301 302 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { 303 { 304 .flags = HCLGE_MAC_MGR_MASK_VLAN_B, 305 .ethter_type = cpu_to_le16(ETH_P_LLDP), 306 .mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e}, 307 .i_port_bitmap = 0x1, 308 }, 309 }; 310 311 /** 312 * hclge_cmd_send - send command to command queue 313 * @hw: pointer to the hw struct 314 * @desc: prefilled descriptor for describing the command 315 * @num : the number of descriptors to be sent 316 * 317 * This is the main send command for command queue, it 318 * sends the queue, cleans the queue, etc 319 **/ 320 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) 321 { 322 return hclge_comm_cmd_send(&hw->hw, desc, num); 323 } 324 325 static void hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, 326 int num, bool is_special) 327 { 328 int i; 329 330 trace_hclge_pf_cmd_send(hw, desc, 0, num); 331 332 if (!is_special) { 333 for (i = 1; i < num; i++) 334 trace_hclge_pf_cmd_send(hw, &desc[i], i, num); 335 } else { 336 for (i = 1; i < num; i++) 337 trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i], 338 i, num); 339 } 340 } 341 342 static void hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, 343 int num, bool is_special) 344 { 345 int i; 346 347 if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) 348 return; 349 350 trace_hclge_pf_cmd_get(hw, desc, 0, num); 351 352 if (!is_special) { 353 for (i = 1; i < num; i++) 354 trace_hclge_pf_cmd_get(hw, &desc[i], i, num); 355 } else { 356 for (i = 1; i < num; i++) 357 trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i], 358 i, num); 359 } 360 } 361 362 static const struct hclge_comm_cmq_ops hclge_cmq_ops = { 363 .trace_cmd_send = hclge_trace_cmd_send, 364 .trace_cmd_get = hclge_trace_cmd_get, 365 }; 366 367 static int hclge_mac_update_stats_defective(struct hclge_dev *hdev) 368 { 369 #define HCLGE_MAC_CMD_NUM 21 370 371 u64 *data = (u64 *)(&hdev->mac_stats); 372 struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; 373 __le64 *desc_data; 374 u32 data_size; 375 int ret; 376 u32 i; 377 378 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); 379 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); 380 if (ret) { 381 dev_err(&hdev->pdev->dev, 382 "Get MAC pkt stats fail, status = %d.\n", ret); 383 384 return ret; 385 } 386 387 /* The first desc has a 64-bit header, so data size need to minus 1 */ 388 data_size = sizeof(desc) / (sizeof(u64)) - 1; 389 390 desc_data = (__le64 *)(&desc[0].data[0]); 391 for (i = 0; i < data_size; i++) { 392 /* data memory is continuous becase only the first desc has a 393 * header in this command 394 */ 395 *data += le64_to_cpu(*desc_data); 396 data++; 397 desc_data++; 398 } 399 400 return 0; 401 } 402 403 static int hclge_mac_update_stats_complete(struct hclge_dev *hdev) 404 { 405 #define HCLGE_REG_NUM_PER_DESC 4 406 407 u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num; 408 u64 *data = (u64 *)(&hdev->mac_stats); 409 struct hclge_desc *desc; 410 __le64 *desc_data; 411 u32 data_size; 412 u32 desc_num; 413 int ret; 414 u32 i; 415 416 /* The first desc has a 64-bit header, so need to consider it */ 417 desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1; 418 419 /* This may be called inside atomic sections, 420 * so GFP_ATOMIC is more suitable here 421 */ 422 desc = kzalloc_objs(struct hclge_desc, desc_num, GFP_ATOMIC); 423 if (!desc) 424 return -ENOMEM; 425 426 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true); 427 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); 428 if (ret) { 429 kfree(desc); 430 return ret; 431 } 432 433 data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num); 434 435 desc_data = (__le64 *)(&desc[0].data[0]); 436 for (i = 0; i < data_size; i++) { 437 /* data memory is continuous becase only the first desc has a 438 * header in this command 439 */ 440 *data += le64_to_cpu(*desc_data); 441 data++; 442 desc_data++; 443 } 444 445 kfree(desc); 446 447 return 0; 448 } 449 450 static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num) 451 { 452 struct hclge_desc desc; 453 int ret; 454 455 /* Driver needs total register number of both valid registers and 456 * reserved registers, but the old firmware only returns number 457 * of valid registers in device V2. To be compatible with these 458 * devices, driver uses a fixed value. 459 */ 460 if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) { 461 *reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; 462 return 0; 463 } 464 465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true); 466 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 467 if (ret) { 468 dev_err(&hdev->pdev->dev, 469 "failed to query mac statistic reg number, ret = %d\n", 470 ret); 471 return ret; 472 } 473 474 *reg_num = le32_to_cpu(desc.data[0]); 475 if (*reg_num == 0) { 476 dev_err(&hdev->pdev->dev, 477 "mac statistic reg number is invalid!\n"); 478 return -ENODATA; 479 } 480 481 return 0; 482 } 483 484 int hclge_mac_update_stats(struct hclge_dev *hdev) 485 { 486 /* The firmware supports the new statistics acquisition method */ 487 if (hdev->ae_dev->dev_specs.mac_stats_num) 488 return hclge_mac_update_stats_complete(hdev); 489 else 490 return hclge_mac_update_stats_defective(hdev); 491 } 492 493 static int hclge_comm_get_count(struct hclge_dev *hdev, 494 const struct hclge_comm_stats_str strs[], 495 u32 size) 496 { 497 int count = 0; 498 u32 i; 499 500 for (i = 0; i < size; i++) 501 if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num) 502 count++; 503 504 return count; 505 } 506 507 static u64 *hclge_comm_get_stats(struct hclge_dev *hdev, 508 const struct hclge_comm_stats_str strs[], 509 int size, u64 *data) 510 { 511 u64 *buf = data; 512 int i; 513 514 for (i = 0; i < size; i++) { 515 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 516 continue; 517 518 *buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset); 519 buf++; 520 } 521 522 return buf; 523 } 524 525 static void hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset, 526 const struct hclge_comm_stats_str strs[], 527 int size, u8 **data) 528 { 529 int i; 530 531 if (stringset != ETH_SS_STATS) 532 return; 533 534 for (i = 0; i < size; i++) { 535 if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num) 536 continue; 537 538 ethtool_puts(data, strs[i].desc); 539 } 540 } 541 542 static void hclge_update_stats_for_all(struct hclge_dev *hdev) 543 { 544 struct hnae3_handle *handle; 545 int status; 546 547 handle = &hdev->vport[0].nic; 548 if (handle->client) { 549 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 550 if (status) { 551 dev_err(&hdev->pdev->dev, 552 "Update TQPS stats fail, status = %d.\n", 553 status); 554 } 555 } 556 557 hclge_update_fec_stats(hdev); 558 559 status = hclge_mac_update_stats(hdev); 560 if (status) 561 dev_err(&hdev->pdev->dev, 562 "Update MAC stats fail, status = %d.\n", status); 563 } 564 565 static void hclge_update_stats(struct hnae3_handle *handle) 566 { 567 struct hclge_vport *vport = hclge_get_vport(handle); 568 struct hclge_dev *hdev = vport->back; 569 int status; 570 571 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) 572 return; 573 574 status = hclge_mac_update_stats(hdev); 575 if (status) 576 dev_err(&hdev->pdev->dev, 577 "Update MAC stats fail, status = %d.\n", 578 status); 579 580 status = hclge_comm_tqps_update_stats(handle, &hdev->hw.hw); 581 if (status) 582 dev_err(&hdev->pdev->dev, 583 "Update TQPS stats fail, status = %d.\n", 584 status); 585 586 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); 587 } 588 589 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) 590 { 591 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \ 592 HNAE3_SUPPORT_PHY_LOOPBACK | \ 593 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \ 594 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \ 595 HNAE3_SUPPORT_EXTERNAL_LOOPBACK) 596 597 struct hclge_vport *vport = hclge_get_vport(handle); 598 struct hclge_dev *hdev = vport->back; 599 int count = 0; 600 601 /* Loopback test support rules: 602 * mac: only GE mode support 603 * serdes: all mac mode will support include GE/XGE/LGE/CGE 604 * phy: only support when phy device exist on board 605 */ 606 if (stringset == ETH_SS_TEST) { 607 /* clear loopback bit flags at first */ 608 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); 609 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 || 610 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || 611 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || 612 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { 613 count += 1; 614 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK; 615 } 616 617 if (hdev->ae_dev->dev_specs.hilink_version != 618 HCLGE_HILINK_H60) { 619 count += 1; 620 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK; 621 } 622 623 count += 1; 624 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK; 625 count += 1; 626 handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK; 627 628 if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv && 629 hdev->hw.mac.phydev->drv->set_loopback) || 630 hnae3_dev_phy_imp_supported(hdev)) { 631 count += 1; 632 handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK; 633 } 634 } else if (stringset == ETH_SS_STATS) { 635 count = hclge_comm_get_count(hdev, g_mac_stats_string, 636 ARRAY_SIZE(g_mac_stats_string)) + 637 hclge_comm_tqps_get_sset_count(handle); 638 } 639 640 return count; 641 } 642 643 static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset, 644 u8 **data) 645 { 646 struct hclge_vport *vport = hclge_get_vport(handle); 647 struct hclge_dev *hdev = vport->back; 648 const char *str; 649 int size; 650 651 if (stringset == ETH_SS_STATS) { 652 size = ARRAY_SIZE(g_mac_stats_string); 653 hclge_comm_get_strings(hdev, stringset, g_mac_stats_string, 654 size, data); 655 hclge_comm_tqps_get_strings(handle, data); 656 } else if (stringset == ETH_SS_TEST) { 657 if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) { 658 str = hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL]; 659 ethtool_puts(data, str); 660 } 661 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) { 662 str = hns3_nic_test_strs[HNAE3_LOOP_APP]; 663 ethtool_puts(data, str); 664 } 665 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) { 666 str = hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES]; 667 ethtool_puts(data, str); 668 } 669 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) { 670 str = hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES]; 671 ethtool_puts(data, str); 672 } 673 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { 674 str = hns3_nic_test_strs[HNAE3_LOOP_PHY]; 675 ethtool_puts(data, str); 676 } 677 } 678 } 679 680 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) 681 { 682 struct hclge_vport *vport = hclge_get_vport(handle); 683 struct hclge_dev *hdev = vport->back; 684 u64 *p; 685 686 p = hclge_comm_get_stats(hdev, g_mac_stats_string, 687 ARRAY_SIZE(g_mac_stats_string), data); 688 p = hclge_comm_tqps_get_stats(handle, p); 689 } 690 691 static void hclge_get_mac_stat(struct hnae3_handle *handle, 692 struct hns3_mac_stats *mac_stats) 693 { 694 struct hclge_vport *vport = hclge_get_vport(handle); 695 struct hclge_dev *hdev = vport->back; 696 697 hclge_update_stats(handle); 698 699 mac_stats->tx_pause_cnt = hdev->mac_stats.mac_tx_mac_pause_num; 700 mac_stats->rx_pause_cnt = hdev->mac_stats.mac_rx_mac_pause_num; 701 } 702 703 static int hclge_parse_func_status(struct hclge_dev *hdev, 704 struct hclge_func_status_cmd *status) 705 { 706 #define HCLGE_MAC_ID_MASK 0xF 707 708 if (!(status->pf_state & HCLGE_PF_STATE_DONE)) 709 return -EINVAL; 710 711 /* Set the pf to main pf */ 712 if (status->pf_state & HCLGE_PF_STATE_MAIN) 713 hdev->flag |= HCLGE_FLAG_MAIN; 714 else 715 hdev->flag &= ~HCLGE_FLAG_MAIN; 716 717 hdev->hw.mac.mac_id = status->mac_id & HCLGE_MAC_ID_MASK; 718 return 0; 719 } 720 721 static int hclge_query_function_status(struct hclge_dev *hdev) 722 { 723 #define HCLGE_QUERY_MAX_CNT 5 724 725 struct hclge_func_status_cmd *req; 726 struct hclge_desc desc; 727 int timeout = 0; 728 int ret; 729 730 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); 731 req = (struct hclge_func_status_cmd *)desc.data; 732 733 do { 734 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 735 if (ret) { 736 dev_err(&hdev->pdev->dev, 737 "query function status failed %d.\n", ret); 738 return ret; 739 } 740 741 /* Check pf reset is done */ 742 if (req->pf_state) 743 break; 744 usleep_range(1000, 2000); 745 } while (timeout++ < HCLGE_QUERY_MAX_CNT); 746 747 return hclge_parse_func_status(hdev, req); 748 } 749 750 static int hclge_query_pf_resource(struct hclge_dev *hdev) 751 { 752 struct hclge_pf_res_cmd *req; 753 struct hclge_desc desc; 754 int ret; 755 756 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); 757 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 758 if (ret) { 759 dev_err(&hdev->pdev->dev, 760 "query pf resource failed %d.\n", ret); 761 return ret; 762 } 763 764 req = (struct hclge_pf_res_cmd *)desc.data; 765 hdev->num_tqps = le16_to_cpu(req->tqp_num) + 766 le16_to_cpu(req->ext_tqp_num); 767 hdev->pkt_buf_size = le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; 768 769 if (req->tx_buf_size) 770 hdev->tx_buf_size = 771 le16_to_cpu(req->tx_buf_size) << HCLGE_BUF_UNIT_S; 772 else 773 hdev->tx_buf_size = HCLGE_DEFAULT_TX_BUF; 774 775 hdev->tx_buf_size = roundup(hdev->tx_buf_size, HCLGE_BUF_SIZE_UNIT); 776 777 if (req->dv_buf_size) 778 hdev->dv_buf_size = 779 le16_to_cpu(req->dv_buf_size) << HCLGE_BUF_UNIT_S; 780 else 781 hdev->dv_buf_size = HCLGE_DEFAULT_DV; 782 783 hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT); 784 785 hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); 786 if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) { 787 dev_err(&hdev->pdev->dev, 788 "only %u msi resources available, not enough for pf(min:2).\n", 789 hdev->num_nic_msi); 790 return -EINVAL; 791 } 792 793 if (hnae3_dev_roce_supported(hdev)) { 794 hdev->num_roce_msi = 795 le16_to_cpu(req->pf_intr_vector_number_roce); 796 797 /* PF should have NIC vectors and Roce vectors, 798 * NIC vectors are queued before Roce vectors. 799 */ 800 hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi; 801 } else { 802 hdev->num_msi = hdev->num_nic_msi; 803 } 804 805 return 0; 806 } 807 808 static int hclge_parse_speed(u8 speed_cmd, u32 *speed) 809 { 810 switch (speed_cmd) { 811 case HCLGE_FW_MAC_SPEED_10M: 812 *speed = HCLGE_MAC_SPEED_10M; 813 break; 814 case HCLGE_FW_MAC_SPEED_100M: 815 *speed = HCLGE_MAC_SPEED_100M; 816 break; 817 case HCLGE_FW_MAC_SPEED_1G: 818 *speed = HCLGE_MAC_SPEED_1G; 819 break; 820 case HCLGE_FW_MAC_SPEED_10G: 821 *speed = HCLGE_MAC_SPEED_10G; 822 break; 823 case HCLGE_FW_MAC_SPEED_25G: 824 *speed = HCLGE_MAC_SPEED_25G; 825 break; 826 case HCLGE_FW_MAC_SPEED_40G: 827 *speed = HCLGE_MAC_SPEED_40G; 828 break; 829 case HCLGE_FW_MAC_SPEED_50G: 830 *speed = HCLGE_MAC_SPEED_50G; 831 break; 832 case HCLGE_FW_MAC_SPEED_100G: 833 *speed = HCLGE_MAC_SPEED_100G; 834 break; 835 case HCLGE_FW_MAC_SPEED_200G: 836 *speed = HCLGE_MAC_SPEED_200G; 837 break; 838 default: 839 return -EINVAL; 840 } 841 842 return 0; 843 } 844 845 static const struct hclge_speed_bit_map speed_bit_map[] = { 846 {HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT}, 847 {HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT}, 848 {HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT}, 849 {HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT}, 850 {HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT}, 851 {HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT}, 852 {HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BITS}, 853 {HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BITS}, 854 {HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BITS}, 855 }; 856 857 static int hclge_get_speed_bit(u32 speed, u32 *speed_bit) 858 { 859 u16 i; 860 861 for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) { 862 if (speed == speed_bit_map[i].speed) { 863 *speed_bit = speed_bit_map[i].speed_bit; 864 return 0; 865 } 866 } 867 868 return -EINVAL; 869 } 870 871 static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed) 872 { 873 struct hclge_vport *vport = hclge_get_vport(handle); 874 struct hclge_dev *hdev = vport->back; 875 u32 speed_ability = hdev->hw.mac.speed_ability; 876 u32 speed_bit = 0; 877 int ret; 878 879 ret = hclge_get_speed_bit(speed, &speed_bit); 880 if (ret) 881 return ret; 882 883 if (speed_bit & speed_ability) 884 return 0; 885 886 return -EINVAL; 887 } 888 889 static void hclge_update_fec_support(struct hclge_mac *mac) 890 { 891 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported); 892 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported); 893 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported); 894 linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 895 896 if (mac->fec_ability & BIT(HNAE3_FEC_BASER)) 897 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 898 mac->supported); 899 if (mac->fec_ability & BIT(HNAE3_FEC_RS)) 900 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 901 mac->supported); 902 if (mac->fec_ability & BIT(HNAE3_FEC_LLRS)) 903 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 904 mac->supported); 905 if (mac->fec_ability & BIT(HNAE3_FEC_NONE)) 906 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 907 mac->supported); 908 } 909 910 static const struct hclge_link_mode_bmap hclge_sr_link_mode_bmap[] = { 911 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT}, 912 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT}, 913 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT}, 914 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT}, 915 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseSR_Full_BIT}, 916 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT}, 917 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT}, 918 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 919 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 920 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT}, 921 }; 922 923 static const struct hclge_link_mode_bmap hclge_lr_link_mode_bmap[] = { 924 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT}, 925 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT}, 926 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT}, 927 {HCLGE_SUPPORT_100G_R4_BIT, 928 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT}, 929 {HCLGE_SUPPORT_100G_R2_BIT, 930 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT}, 931 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 932 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 933 {HCLGE_SUPPORT_200G_R4_BIT, 934 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT}, 935 }; 936 937 static const struct hclge_link_mode_bmap hclge_cr_link_mode_bmap[] = { 938 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT}, 939 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT}, 940 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT}, 941 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT}, 942 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseCR_Full_BIT}, 943 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT}, 944 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT}, 945 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 946 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 947 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT}, 948 }; 949 950 static const struct hclge_link_mode_bmap hclge_kr_link_mode_bmap[] = { 951 {HCLGE_SUPPORT_1G_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT}, 952 {HCLGE_SUPPORT_10G_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT}, 953 {HCLGE_SUPPORT_25G_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT}, 954 {HCLGE_SUPPORT_40G_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT}, 955 {HCLGE_SUPPORT_50G_R2_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT}, 956 {HCLGE_SUPPORT_50G_R1_BIT, ETHTOOL_LINK_MODE_50000baseKR_Full_BIT}, 957 {HCLGE_SUPPORT_100G_R4_BIT, ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT}, 958 {HCLGE_SUPPORT_100G_R2_BIT, ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT}, 959 {HCLGE_SUPPORT_200G_R4_EXT_BIT, 960 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 961 {HCLGE_SUPPORT_200G_R4_BIT, ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT}, 962 }; 963 964 static void hclge_convert_setting_sr(u16 speed_ability, 965 unsigned long *link_mode) 966 { 967 int i; 968 969 for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { 970 if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit) 971 linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode, 972 link_mode); 973 } 974 } 975 976 static void hclge_convert_setting_lr(u16 speed_ability, 977 unsigned long *link_mode) 978 { 979 int i; 980 981 for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { 982 if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit) 983 linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode, 984 link_mode); 985 } 986 } 987 988 static void hclge_convert_setting_cr(u16 speed_ability, 989 unsigned long *link_mode) 990 { 991 int i; 992 993 for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { 994 if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit) 995 linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode, 996 link_mode); 997 } 998 } 999 1000 static void hclge_convert_setting_kr(u16 speed_ability, 1001 unsigned long *link_mode) 1002 { 1003 int i; 1004 1005 for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { 1006 if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit) 1007 linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode, 1008 link_mode); 1009 } 1010 } 1011 1012 static void hclge_convert_setting_fec(struct hclge_mac *mac) 1013 { 1014 /* If firmware has reported fec_ability, don't need to convert by speed */ 1015 if (mac->fec_ability) 1016 goto out; 1017 1018 switch (mac->speed) { 1019 case HCLGE_MAC_SPEED_10G: 1020 case HCLGE_MAC_SPEED_40G: 1021 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) | 1022 BIT(HNAE3_FEC_NONE); 1023 break; 1024 case HCLGE_MAC_SPEED_25G: 1025 case HCLGE_MAC_SPEED_50G: 1026 mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) | 1027 BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); 1028 break; 1029 case HCLGE_MAC_SPEED_100G: 1030 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1031 BIT(HNAE3_FEC_NONE); 1032 break; 1033 case HCLGE_MAC_SPEED_200G: 1034 mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) | 1035 BIT(HNAE3_FEC_LLRS); 1036 break; 1037 default: 1038 mac->fec_ability = 0; 1039 break; 1040 } 1041 1042 out: 1043 hclge_update_fec_support(mac); 1044 } 1045 1046 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, 1047 u16 speed_ability) 1048 { 1049 struct hclge_mac *mac = &hdev->hw.mac; 1050 1051 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1052 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1053 mac->supported); 1054 1055 hclge_convert_setting_sr(speed_ability, mac->supported); 1056 hclge_convert_setting_lr(speed_ability, mac->supported); 1057 hclge_convert_setting_cr(speed_ability, mac->supported); 1058 if (hnae3_dev_fec_supported(hdev)) 1059 hclge_convert_setting_fec(mac); 1060 1061 if (hnae3_dev_pause_supported(hdev)) 1062 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1063 1064 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported); 1065 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1066 } 1067 1068 static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev, 1069 u16 speed_ability) 1070 { 1071 struct hclge_mac *mac = &hdev->hw.mac; 1072 1073 hclge_convert_setting_kr(speed_ability, mac->supported); 1074 if (hnae3_dev_fec_supported(hdev)) 1075 hclge_convert_setting_fec(mac); 1076 1077 if (hnae3_dev_pause_supported(hdev)) 1078 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported); 1079 1080 linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported); 1081 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported); 1082 } 1083 1084 static void hclge_parse_copper_link_mode(struct hclge_dev *hdev, 1085 u16 speed_ability) 1086 { 1087 unsigned long *supported = hdev->hw.mac.supported; 1088 1089 /* default to support all speed for GE port */ 1090 if (!speed_ability) 1091 speed_ability = HCLGE_SUPPORT_GE; 1092 1093 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1094 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1095 supported); 1096 1097 if (speed_ability & HCLGE_SUPPORT_100M_BIT) { 1098 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1099 supported); 1100 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1101 supported); 1102 } 1103 1104 if (speed_ability & HCLGE_SUPPORT_10M_BIT) { 1105 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported); 1106 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported); 1107 } 1108 1109 if (hnae3_dev_pause_supported(hdev)) { 1110 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); 1111 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported); 1112 } 1113 1114 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported); 1115 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported); 1116 } 1117 1118 static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability) 1119 { 1120 u8 media_type = hdev->hw.mac.media_type; 1121 1122 if (media_type == HNAE3_MEDIA_TYPE_FIBER) 1123 hclge_parse_fiber_link_mode(hdev, speed_ability); 1124 else if (media_type == HNAE3_MEDIA_TYPE_COPPER) 1125 hclge_parse_copper_link_mode(hdev, speed_ability); 1126 else if (media_type == HNAE3_MEDIA_TYPE_BACKPLANE) 1127 hclge_parse_backplane_link_mode(hdev, speed_ability); 1128 } 1129 1130 static u32 hclge_get_max_speed(u16 speed_ability) 1131 { 1132 if (speed_ability & HCLGE_SUPPORT_200G_BITS) 1133 return HCLGE_MAC_SPEED_200G; 1134 1135 if (speed_ability & HCLGE_SUPPORT_100G_BITS) 1136 return HCLGE_MAC_SPEED_100G; 1137 1138 if (speed_ability & HCLGE_SUPPORT_50G_BITS) 1139 return HCLGE_MAC_SPEED_50G; 1140 1141 if (speed_ability & HCLGE_SUPPORT_40G_BIT) 1142 return HCLGE_MAC_SPEED_40G; 1143 1144 if (speed_ability & HCLGE_SUPPORT_25G_BIT) 1145 return HCLGE_MAC_SPEED_25G; 1146 1147 if (speed_ability & HCLGE_SUPPORT_10G_BIT) 1148 return HCLGE_MAC_SPEED_10G; 1149 1150 if (speed_ability & HCLGE_SUPPORT_1G_BIT) 1151 return HCLGE_MAC_SPEED_1G; 1152 1153 if (speed_ability & HCLGE_SUPPORT_100M_BIT) 1154 return HCLGE_MAC_SPEED_100M; 1155 1156 if (speed_ability & HCLGE_SUPPORT_10M_BIT) 1157 return HCLGE_MAC_SPEED_10M; 1158 1159 return HCLGE_MAC_SPEED_1G; 1160 } 1161 1162 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) 1163 { 1164 #define HCLGE_TX_SPARE_SIZE_UNIT 4096 1165 #define SPEED_ABILITY_EXT_SHIFT 8 1166 1167 struct hclge_cfg_param_cmd *req; 1168 u64 mac_addr_tmp_high; 1169 u16 speed_ability_ext; 1170 u64 mac_addr_tmp; 1171 unsigned int i; 1172 1173 req = (struct hclge_cfg_param_cmd *)desc[0].data; 1174 1175 /* get the configuration */ 1176 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1177 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); 1178 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), 1179 HCLGE_CFG_TQP_DESC_N_M, 1180 HCLGE_CFG_TQP_DESC_N_S); 1181 1182 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), 1183 HCLGE_CFG_PHY_ADDR_M, 1184 HCLGE_CFG_PHY_ADDR_S); 1185 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), 1186 HCLGE_CFG_MEDIA_TP_M, 1187 HCLGE_CFG_MEDIA_TP_S); 1188 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), 1189 HCLGE_CFG_RX_BUF_LEN_M, 1190 HCLGE_CFG_RX_BUF_LEN_S); 1191 /* get mac_address */ 1192 mac_addr_tmp = __le32_to_cpu(req->param[2]); 1193 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), 1194 HCLGE_CFG_MAC_ADDR_H_M, 1195 HCLGE_CFG_MAC_ADDR_H_S); 1196 1197 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 1198 1199 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), 1200 HCLGE_CFG_DEFAULT_SPEED_M, 1201 HCLGE_CFG_DEFAULT_SPEED_S); 1202 cfg->vf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), 1203 HCLGE_CFG_RSS_SIZE_M, 1204 HCLGE_CFG_RSS_SIZE_S); 1205 1206 for (i = 0; i < ETH_ALEN; i++) 1207 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 1208 1209 req = (struct hclge_cfg_param_cmd *)desc[1].data; 1210 cfg->numa_node_map = __le32_to_cpu(req->param[0]); 1211 1212 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), 1213 HCLGE_CFG_SPEED_ABILITY_M, 1214 HCLGE_CFG_SPEED_ABILITY_S); 1215 speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]), 1216 HCLGE_CFG_SPEED_ABILITY_EXT_M, 1217 HCLGE_CFG_SPEED_ABILITY_EXT_S); 1218 cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT; 1219 1220 cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]), 1221 HCLGE_CFG_VLAN_FLTR_CAP_M, 1222 HCLGE_CFG_VLAN_FLTR_CAP_S); 1223 1224 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]), 1225 HCLGE_CFG_UMV_TBL_SPACE_M, 1226 HCLGE_CFG_UMV_TBL_SPACE_S); 1227 1228 cfg->pf_rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[2]), 1229 HCLGE_CFG_PF_RSS_SIZE_M, 1230 HCLGE_CFG_PF_RSS_SIZE_S); 1231 1232 /* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a 1233 * power of 2, instead of reading out directly. This would 1234 * be more flexible for future changes and expansions. 1235 * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, 1236 * it does not make sense if PF's field is 0. In this case, PF and VF 1237 * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S. 1238 */ 1239 cfg->pf_rss_size_max = cfg->pf_rss_size_max ? 1240 1U << cfg->pf_rss_size_max : 1241 cfg->vf_rss_size_max; 1242 1243 /* The unit of the tx spare buffer size queried from configuration 1244 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is 1245 * needed here. 1246 */ 1247 cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]), 1248 HCLGE_CFG_TX_SPARE_BUF_SIZE_M, 1249 HCLGE_CFG_TX_SPARE_BUF_SIZE_S); 1250 cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT; 1251 } 1252 1253 /* hclge_get_cfg: query the static parameter from flash 1254 * @hdev: pointer to struct hclge_dev 1255 * @hcfg: the config structure to be getted 1256 */ 1257 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) 1258 { 1259 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; 1260 struct hclge_cfg_param_cmd *req; 1261 unsigned int i; 1262 int ret; 1263 1264 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { 1265 u32 offset = 0; 1266 1267 req = (struct hclge_cfg_param_cmd *)desc[i].data; 1268 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, 1269 true); 1270 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, 1271 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); 1272 /* Len should be united by 4 bytes when send to hardware */ 1273 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, 1274 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); 1275 req->offset = cpu_to_le32(offset); 1276 } 1277 1278 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); 1279 if (ret) { 1280 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); 1281 return ret; 1282 } 1283 1284 hclge_parse_cfg(hcfg, desc); 1285 1286 return 0; 1287 } 1288 1289 static void hclge_set_default_dev_specs(struct hclge_dev *hdev) 1290 { 1291 #define HCLGE_MAX_NON_TSO_BD_NUM 8U 1292 1293 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1294 1295 ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1296 ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1297 ae_dev->dev_specs.rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1298 ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE; 1299 ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL; 1300 ae_dev->dev_specs.max_frm_size = HCLGE_MAC_MAX_FRAME; 1301 ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM; 1302 ae_dev->dev_specs.umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1303 ae_dev->dev_specs.tnl_num = 0; 1304 } 1305 1306 static void hclge_parse_dev_specs(struct hclge_dev *hdev, 1307 struct hclge_desc *desc) 1308 { 1309 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1310 struct hclge_dev_specs_0_cmd *req0; 1311 struct hclge_dev_specs_1_cmd *req1; 1312 1313 req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data; 1314 req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data; 1315 1316 ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num; 1317 ae_dev->dev_specs.rss_ind_tbl_size = 1318 le16_to_cpu(req0->rss_ind_tbl_size); 1319 ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max); 1320 ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size); 1321 ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate); 1322 ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num); 1323 ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl); 1324 ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); 1325 ae_dev->dev_specs.umv_size = le16_to_cpu(req1->umv_size); 1326 ae_dev->dev_specs.mc_mac_size = le16_to_cpu(req1->mc_mac_size); 1327 ae_dev->dev_specs.tnl_num = req1->tnl_num; 1328 ae_dev->dev_specs.hilink_version = req1->hilink_version; 1329 } 1330 1331 static void hclge_check_dev_specs(struct hclge_dev *hdev) 1332 { 1333 struct hnae3_dev_specs *dev_specs = &hdev->ae_dev->dev_specs; 1334 1335 if (!dev_specs->max_non_tso_bd_num) 1336 dev_specs->max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM; 1337 if (!dev_specs->rss_ind_tbl_size) 1338 dev_specs->rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE; 1339 if (!dev_specs->rss_key_size) 1340 dev_specs->rss_key_size = HCLGE_COMM_RSS_KEY_SIZE; 1341 if (!dev_specs->max_tm_rate) 1342 dev_specs->max_tm_rate = HCLGE_ETHER_MAX_RATE; 1343 if (!dev_specs->max_qset_num) 1344 dev_specs->max_qset_num = HCLGE_MAX_QSET_NUM; 1345 if (!dev_specs->max_int_gl) 1346 dev_specs->max_int_gl = HCLGE_DEF_MAX_INT_GL; 1347 if (!dev_specs->max_frm_size) 1348 dev_specs->max_frm_size = HCLGE_MAC_MAX_FRAME; 1349 if (!dev_specs->umv_size) 1350 dev_specs->umv_size = HCLGE_DEFAULT_UMV_SPACE_PER_PF; 1351 } 1352 1353 static int hclge_query_mac_stats_num(struct hclge_dev *hdev) 1354 { 1355 u32 reg_num = 0; 1356 int ret; 1357 1358 ret = hclge_mac_query_reg_num(hdev, ®_num); 1359 if (ret && ret != -EOPNOTSUPP) 1360 return ret; 1361 1362 hdev->ae_dev->dev_specs.mac_stats_num = reg_num; 1363 return 0; 1364 } 1365 1366 static int hclge_query_dev_specs(struct hclge_dev *hdev) 1367 { 1368 struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; 1369 int ret; 1370 int i; 1371 1372 ret = hclge_query_mac_stats_num(hdev); 1373 if (ret) 1374 return ret; 1375 1376 /* set default specifications as devices lower than version V3 do not 1377 * support querying specifications from firmware. 1378 */ 1379 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 1380 hclge_set_default_dev_specs(hdev); 1381 return 0; 1382 } 1383 1384 for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 1385 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, 1386 true); 1387 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 1388 } 1389 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true); 1390 1391 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); 1392 if (ret) 1393 return ret; 1394 1395 hclge_parse_dev_specs(hdev, desc); 1396 hclge_check_dev_specs(hdev); 1397 1398 return 0; 1399 } 1400 1401 static int hclge_get_cap(struct hclge_dev *hdev) 1402 { 1403 int ret; 1404 1405 ret = hclge_query_function_status(hdev); 1406 if (ret) { 1407 dev_err(&hdev->pdev->dev, 1408 "query function status error %d.\n", ret); 1409 return ret; 1410 } 1411 1412 /* get pf resource */ 1413 return hclge_query_pf_resource(hdev); 1414 } 1415 1416 static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev) 1417 { 1418 #define HCLGE_MIN_TX_DESC 64 1419 #define HCLGE_MIN_RX_DESC 64 1420 1421 if (!is_kdump_kernel()) 1422 return; 1423 1424 dev_info(&hdev->pdev->dev, 1425 "Running kdump kernel. Using minimal resources\n"); 1426 1427 /* minimal queue pairs equals to the number of vports */ 1428 hdev->num_tqps = hdev->num_req_vfs + 1; 1429 hdev->num_tx_desc = HCLGE_MIN_TX_DESC; 1430 hdev->num_rx_desc = HCLGE_MIN_RX_DESC; 1431 } 1432 1433 static void hclge_init_tc_config(struct hclge_dev *hdev) 1434 { 1435 unsigned int i; 1436 1437 if (hdev->tc_max > HNAE3_MAX_TC || 1438 hdev->tc_max < 1) { 1439 dev_warn(&hdev->pdev->dev, "TC num = %u.\n", 1440 hdev->tc_max); 1441 hdev->tc_max = 1; 1442 } 1443 1444 /* Dev does not support DCB */ 1445 if (!hnae3_dev_dcb_supported(hdev)) { 1446 hdev->tc_max = 1; 1447 hdev->pfc_max = 0; 1448 } else { 1449 hdev->pfc_max = hdev->tc_max; 1450 } 1451 1452 hdev->tm_info.num_tc = 1; 1453 1454 /* Currently not support uncontiuous tc */ 1455 for (i = 0; i < hdev->tm_info.num_tc; i++) 1456 hnae3_set_bit(hdev->hw_tc_map, i, 1); 1457 1458 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; 1459 } 1460 1461 static int hclge_configure(struct hclge_dev *hdev) 1462 { 1463 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1464 struct hclge_cfg cfg; 1465 int ret; 1466 1467 ret = hclge_get_cfg(hdev, &cfg); 1468 if (ret) 1469 return ret; 1470 1471 hdev->base_tqp_pid = 0; 1472 hdev->vf_rss_size_max = cfg.vf_rss_size_max; 1473 hdev->pf_rss_size_max = cfg.pf_rss_size_max; 1474 hdev->rx_buf_len = cfg.rx_buf_len; 1475 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); 1476 hdev->hw.mac.media_type = cfg.media_type; 1477 hdev->hw.mac.phy_addr = cfg.phy_addr; 1478 hdev->num_tx_desc = cfg.tqp_desc_num; 1479 hdev->num_rx_desc = cfg.tqp_desc_num; 1480 hdev->tm_info.num_pg = 1; 1481 hdev->tc_max = cfg.tc_num; 1482 hdev->tm_info.hw_pfc_map = 0; 1483 if (cfg.umv_space) 1484 hdev->wanted_umv_size = cfg.umv_space; 1485 else 1486 hdev->wanted_umv_size = hdev->ae_dev->dev_specs.umv_size; 1487 hdev->tx_spare_buf_size = cfg.tx_spare_buf_size; 1488 hdev->gro_en = true; 1489 if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF) 1490 set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps); 1491 1492 if (hnae3_ae_dev_fd_supported(hdev->ae_dev)) { 1493 hdev->fd_en = true; 1494 hdev->fd_active_type = HCLGE_FD_RULE_NONE; 1495 } 1496 1497 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); 1498 if (ret) { 1499 dev_err(&hdev->pdev->dev, "failed to parse speed %u, ret = %d\n", 1500 cfg.default_speed, ret); 1501 return ret; 1502 } 1503 hdev->hw.mac.req_speed = hdev->hw.mac.speed; 1504 hdev->hw.mac.req_autoneg = AUTONEG_ENABLE; 1505 hdev->hw.mac.req_duplex = DUPLEX_FULL; 1506 1507 /* When lane_num is 0, the firmware will automatically 1508 * select the appropriate lane_num based on the speed. 1509 */ 1510 hdev->hw.mac.req_lane_num = 0; 1511 1512 hclge_parse_link_mode(hdev, cfg.speed_ability); 1513 1514 hdev->hw.mac.max_speed = hclge_get_max_speed(cfg.speed_ability); 1515 1516 hclge_init_tc_config(hdev); 1517 hclge_init_kdump_kernel_config(hdev); 1518 1519 return ret; 1520 } 1521 1522 static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min, 1523 u16 tso_mss_max) 1524 { 1525 struct hclge_cfg_tso_status_cmd *req; 1526 struct hclge_desc desc; 1527 1528 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); 1529 1530 req = (struct hclge_cfg_tso_status_cmd *)desc.data; 1531 req->tso_mss_min = cpu_to_le16(tso_mss_min); 1532 req->tso_mss_max = cpu_to_le16(tso_mss_max); 1533 1534 return hclge_cmd_send(&hdev->hw, &desc, 1); 1535 } 1536 1537 static int hclge_config_gro(struct hclge_dev *hdev) 1538 { 1539 struct hclge_cfg_gro_status_cmd *req; 1540 struct hclge_desc desc; 1541 int ret; 1542 1543 if (!hnae3_ae_dev_gro_supported(hdev->ae_dev)) 1544 return 0; 1545 1546 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false); 1547 req = (struct hclge_cfg_gro_status_cmd *)desc.data; 1548 1549 req->gro_en = hdev->gro_en ? 1 : 0; 1550 1551 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1552 if (ret) 1553 dev_err(&hdev->pdev->dev, 1554 "GRO hardware config cmd failed, ret = %d\n", ret); 1555 1556 return ret; 1557 } 1558 1559 static int hclge_alloc_tqps(struct hclge_dev *hdev) 1560 { 1561 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 1562 struct hclge_comm_tqp *tqp; 1563 int i; 1564 1565 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, 1566 sizeof(struct hclge_comm_tqp), GFP_KERNEL); 1567 if (!hdev->htqp) 1568 return -ENOMEM; 1569 1570 tqp = hdev->htqp; 1571 1572 for (i = 0; i < hdev->num_tqps; i++) { 1573 tqp->dev = &hdev->pdev->dev; 1574 tqp->index = i; 1575 1576 tqp->q.ae_algo = &ae_algo; 1577 tqp->q.buf_size = hdev->rx_buf_len; 1578 tqp->q.tx_desc_num = hdev->num_tx_desc; 1579 tqp->q.rx_desc_num = hdev->num_rx_desc; 1580 1581 /* need an extended offset to configure queues >= 1582 * HCLGE_TQP_MAX_SIZE_DEV_V2 1583 */ 1584 if (i < HCLGE_TQP_MAX_SIZE_DEV_V2) 1585 tqp->q.io_base = hdev->hw.hw.io_base + 1586 HCLGE_TQP_REG_OFFSET + 1587 i * HCLGE_TQP_REG_SIZE; 1588 else 1589 tqp->q.io_base = hdev->hw.hw.io_base + 1590 HCLGE_TQP_REG_OFFSET + 1591 HCLGE_TQP_EXT_REG_OFFSET + 1592 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) * 1593 HCLGE_TQP_REG_SIZE; 1594 1595 /* when device supports tx push and has device memory, 1596 * the queue can execute push mode or doorbell mode on 1597 * device memory. 1598 */ 1599 if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps)) 1600 tqp->q.mem_base = hdev->hw.hw.mem_base + 1601 HCLGE_TQP_MEM_OFFSET(hdev, i); 1602 1603 tqp++; 1604 } 1605 1606 return 0; 1607 } 1608 1609 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, 1610 u16 tqp_pid, u16 tqp_vid, bool is_pf) 1611 { 1612 struct hclge_tqp_map_cmd *req; 1613 struct hclge_desc desc; 1614 int ret; 1615 1616 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); 1617 1618 req = (struct hclge_tqp_map_cmd *)desc.data; 1619 req->tqp_id = cpu_to_le16(tqp_pid); 1620 req->tqp_vf = func_id; 1621 req->tqp_flag = 1U << HCLGE_TQP_MAP_EN_B; 1622 if (!is_pf) 1623 req->tqp_flag |= 1U << HCLGE_TQP_MAP_TYPE_B; 1624 req->tqp_vid = cpu_to_le16(tqp_vid); 1625 1626 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1627 if (ret) 1628 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret); 1629 1630 return ret; 1631 } 1632 1633 static int hclge_assign_tqp(struct hclge_vport *vport, u16 num_tqps) 1634 { 1635 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 1636 struct hclge_dev *hdev = vport->back; 1637 int i, alloced; 1638 1639 for (i = 0, alloced = 0; i < hdev->num_tqps && 1640 alloced < num_tqps; i++) { 1641 if (!hdev->htqp[i].alloced) { 1642 hdev->htqp[i].q.handle = &vport->nic; 1643 hdev->htqp[i].q.tqp_index = alloced; 1644 hdev->htqp[i].q.tx_desc_num = kinfo->num_tx_desc; 1645 hdev->htqp[i].q.rx_desc_num = kinfo->num_rx_desc; 1646 kinfo->tqp[alloced] = &hdev->htqp[i].q; 1647 hdev->htqp[i].alloced = true; 1648 alloced++; 1649 } 1650 } 1651 vport->alloc_tqps = alloced; 1652 kinfo->rss_size = min_t(u16, hdev->pf_rss_size_max, 1653 vport->alloc_tqps / hdev->tm_info.num_tc); 1654 1655 /* ensure one to one mapping between irq and queue at default */ 1656 kinfo->rss_size = min_t(u16, kinfo->rss_size, 1657 (hdev->num_nic_msi - 1) / hdev->tm_info.num_tc); 1658 1659 return 0; 1660 } 1661 1662 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps, 1663 u16 num_tx_desc, u16 num_rx_desc) 1664 1665 { 1666 struct hnae3_handle *nic = &vport->nic; 1667 struct hnae3_knic_private_info *kinfo = &nic->kinfo; 1668 struct hclge_dev *hdev = vport->back; 1669 int ret; 1670 1671 kinfo->num_tx_desc = num_tx_desc; 1672 kinfo->num_rx_desc = num_rx_desc; 1673 1674 kinfo->rx_buf_len = hdev->rx_buf_len; 1675 kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size; 1676 1677 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps, 1678 sizeof(struct hnae3_queue *), GFP_KERNEL); 1679 if (!kinfo->tqp) 1680 return -ENOMEM; 1681 1682 ret = hclge_assign_tqp(vport, num_tqps); 1683 if (ret) 1684 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); 1685 1686 return ret; 1687 } 1688 1689 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, 1690 struct hclge_vport *vport) 1691 { 1692 struct hnae3_handle *nic = &vport->nic; 1693 struct hnae3_knic_private_info *kinfo; 1694 u16 i; 1695 1696 kinfo = &nic->kinfo; 1697 for (i = 0; i < vport->alloc_tqps; i++) { 1698 struct hclge_comm_tqp *q = 1699 container_of(kinfo->tqp[i], struct hclge_comm_tqp, q); 1700 bool is_pf; 1701 int ret; 1702 1703 is_pf = !(vport->vport_id); 1704 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, 1705 i, is_pf); 1706 if (ret) 1707 return ret; 1708 } 1709 1710 return 0; 1711 } 1712 1713 static int hclge_map_tqp(struct hclge_dev *hdev) 1714 { 1715 struct hclge_vport *vport = hdev->vport; 1716 u16 i, num_vport; 1717 1718 num_vport = hdev->num_req_vfs + 1; 1719 for (i = 0; i < num_vport; i++) { 1720 int ret; 1721 1722 ret = hclge_map_tqp_to_vport(hdev, vport); 1723 if (ret) 1724 return ret; 1725 1726 vport++; 1727 } 1728 1729 return 0; 1730 } 1731 1732 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) 1733 { 1734 struct hnae3_handle *nic = &vport->nic; 1735 struct hclge_dev *hdev = vport->back; 1736 int ret; 1737 1738 nic->pdev = hdev->pdev; 1739 nic->ae_algo = &ae_algo; 1740 bitmap_copy(nic->numa_node_mask.bits, hdev->numa_node_mask.bits, 1741 MAX_NUMNODES); 1742 nic->kinfo.io_base = hdev->hw.hw.io_base; 1743 1744 ret = hclge_knic_setup(vport, num_tqps, 1745 hdev->num_tx_desc, hdev->num_rx_desc); 1746 if (ret) 1747 dev_err(&hdev->pdev->dev, "knic setup failed %d\n", ret); 1748 1749 return ret; 1750 } 1751 1752 static int hclge_alloc_vport(struct hclge_dev *hdev) 1753 { 1754 struct pci_dev *pdev = hdev->pdev; 1755 struct hclge_vport *vport; 1756 u32 tqp_main_vport; 1757 u32 tqp_per_vport; 1758 int num_vport, i; 1759 int ret; 1760 1761 /* We need to alloc a vport for main NIC of PF */ 1762 num_vport = hdev->num_req_vfs + 1; 1763 1764 if (hdev->num_tqps < num_vport) { 1765 dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)", 1766 hdev->num_tqps, num_vport); 1767 return -EINVAL; 1768 } 1769 1770 /* Alloc the same number of TQPs for every vport */ 1771 tqp_per_vport = hdev->num_tqps / num_vport; 1772 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; 1773 1774 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), 1775 GFP_KERNEL); 1776 if (!vport) 1777 return -ENOMEM; 1778 1779 hdev->vport = vport; 1780 hdev->num_alloc_vport = num_vport; 1781 1782 if (IS_ENABLED(CONFIG_PCI_IOV)) 1783 hdev->num_alloc_vfs = hdev->num_req_vfs; 1784 1785 for (i = 0; i < num_vport; i++) { 1786 vport->back = hdev; 1787 vport->vport_id = i; 1788 vport->vf_info.link_state = IFLA_VF_LINK_STATE_AUTO; 1789 vport->mps = HCLGE_MAC_DEFAULT_FRAME; 1790 vport->port_base_vlan_cfg.state = HNAE3_PORT_BASE_VLAN_DISABLE; 1791 vport->port_base_vlan_cfg.tbl_sta = true; 1792 vport->rxvlan_cfg.rx_vlan_offload_en = true; 1793 vport->req_vlan_fltr_en = true; 1794 INIT_LIST_HEAD(&vport->vlan_list); 1795 INIT_LIST_HEAD(&vport->uc_mac_list); 1796 INIT_LIST_HEAD(&vport->mc_mac_list); 1797 spin_lock_init(&vport->mac_list_lock); 1798 1799 if (i == 0) 1800 ret = hclge_vport_setup(vport, tqp_main_vport); 1801 else 1802 ret = hclge_vport_setup(vport, tqp_per_vport); 1803 if (ret) { 1804 dev_err(&pdev->dev, 1805 "vport setup failed for vport %d, %d\n", 1806 i, ret); 1807 return ret; 1808 } 1809 1810 vport++; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, 1817 struct hclge_pkt_buf_alloc *buf_alloc) 1818 { 1819 /* TX buffer size is unit by 128 byte */ 1820 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 1821 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) 1822 struct hclge_tx_buff_alloc_cmd *req; 1823 struct hclge_desc desc; 1824 int ret; 1825 u8 i; 1826 1827 req = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1828 1829 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); 1830 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1831 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 1832 1833 req->tx_pkt_buff[i] = 1834 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | 1835 HCLGE_BUF_SIZE_UPDATE_EN_MSK); 1836 } 1837 1838 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1839 if (ret) 1840 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", 1841 ret); 1842 1843 return ret; 1844 } 1845 1846 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, 1847 struct hclge_pkt_buf_alloc *buf_alloc) 1848 { 1849 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); 1850 1851 if (ret) 1852 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret); 1853 1854 return ret; 1855 } 1856 1857 static u32 hclge_get_tc_num(struct hclge_dev *hdev) 1858 { 1859 unsigned int i; 1860 u32 cnt = 0; 1861 1862 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1863 if (hdev->hw_tc_map & BIT(i)) 1864 cnt++; 1865 return cnt; 1866 } 1867 1868 /* Get the number of pfc enabled TCs, which have private buffer */ 1869 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, 1870 struct hclge_pkt_buf_alloc *buf_alloc) 1871 { 1872 struct hclge_priv_buf *priv; 1873 unsigned int i; 1874 int cnt = 0; 1875 1876 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1877 priv = &buf_alloc->priv_buf[i]; 1878 if ((hdev->tm_info.hw_pfc_map & BIT(i)) && 1879 priv->enable) 1880 cnt++; 1881 } 1882 1883 return cnt; 1884 } 1885 1886 /* Get the number of pfc disabled TCs, which have private buffer */ 1887 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, 1888 struct hclge_pkt_buf_alloc *buf_alloc) 1889 { 1890 struct hclge_priv_buf *priv; 1891 unsigned int i; 1892 int cnt = 0; 1893 1894 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1895 priv = &buf_alloc->priv_buf[i]; 1896 if (hdev->hw_tc_map & BIT(i) && 1897 !(hdev->tm_info.hw_pfc_map & BIT(i)) && 1898 priv->enable) 1899 cnt++; 1900 } 1901 1902 return cnt; 1903 } 1904 1905 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1906 { 1907 struct hclge_priv_buf *priv; 1908 u32 rx_priv = 0; 1909 int i; 1910 1911 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1912 priv = &buf_alloc->priv_buf[i]; 1913 if (priv->enable) 1914 rx_priv += priv->buf_size; 1915 } 1916 return rx_priv; 1917 } 1918 1919 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) 1920 { 1921 u32 i, total_tx_size = 0; 1922 1923 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1924 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 1925 1926 return total_tx_size; 1927 } 1928 1929 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, 1930 struct hclge_pkt_buf_alloc *buf_alloc, 1931 u32 rx_all) 1932 { 1933 u32 shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 1934 u32 tc_num = hclge_get_tc_num(hdev); 1935 u32 shared_buf, aligned_mps; 1936 u32 rx_priv; 1937 int i; 1938 1939 aligned_mps = roundup(hdev->mps, HCLGE_BUF_SIZE_UNIT); 1940 1941 if (hnae3_dev_dcb_supported(hdev)) 1942 shared_buf_min = HCLGE_BUF_MUL_BY * aligned_mps + 1943 hdev->dv_buf_size; 1944 else 1945 shared_buf_min = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF 1946 + hdev->dv_buf_size; 1947 1948 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 1949 shared_std = roundup(max_t(u32, shared_buf_min, shared_buf_tc), 1950 HCLGE_BUF_SIZE_UNIT); 1951 1952 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); 1953 if (rx_all < rx_priv + shared_std) 1954 return false; 1955 1956 shared_buf = rounddown(rx_all - rx_priv, HCLGE_BUF_SIZE_UNIT); 1957 buf_alloc->s_buf.buf_size = shared_buf; 1958 if (hnae3_dev_dcb_supported(hdev)) { 1959 buf_alloc->s_buf.self.high = shared_buf - hdev->dv_buf_size; 1960 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 1961 - roundup(aligned_mps / HCLGE_BUF_DIV_BY, 1962 HCLGE_BUF_SIZE_UNIT); 1963 } else { 1964 buf_alloc->s_buf.self.high = aligned_mps + 1965 HCLGE_NON_DCB_ADDITIONAL_BUF; 1966 buf_alloc->s_buf.self.low = aligned_mps; 1967 } 1968 1969 if (hnae3_dev_dcb_supported(hdev)) { 1970 hi_thrd = shared_buf - hdev->dv_buf_size; 1971 1972 if (tc_num <= NEED_RESERVE_TC_NUM) 1973 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 1974 / BUF_MAX_PERCENT; 1975 1976 if (tc_num) 1977 hi_thrd = hi_thrd / tc_num; 1978 1979 hi_thrd = max_t(u32, hi_thrd, HCLGE_BUF_MUL_BY * aligned_mps); 1980 hi_thrd = rounddown(hi_thrd, HCLGE_BUF_SIZE_UNIT); 1981 lo_thrd = hi_thrd - aligned_mps / HCLGE_BUF_DIV_BY; 1982 } else { 1983 hi_thrd = aligned_mps + HCLGE_NON_DCB_ADDITIONAL_BUF; 1984 lo_thrd = aligned_mps; 1985 } 1986 1987 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 1988 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 1989 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 1990 } 1991 1992 return true; 1993 } 1994 1995 static int hclge_tx_buffer_calc(struct hclge_dev *hdev, 1996 struct hclge_pkt_buf_alloc *buf_alloc) 1997 { 1998 u32 i, total_size; 1999 2000 total_size = hdev->pkt_buf_size; 2001 2002 /* alloc tx buffer for all enabled tc */ 2003 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2004 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2005 2006 if (hdev->hw_tc_map & BIT(i)) { 2007 if (total_size < hdev->tx_buf_size) 2008 return -ENOMEM; 2009 2010 priv->tx_buf_size = hdev->tx_buf_size; 2011 } else { 2012 priv->tx_buf_size = 0; 2013 } 2014 2015 total_size -= priv->tx_buf_size; 2016 } 2017 2018 return 0; 2019 } 2020 2021 static bool hclge_rx_buf_calc_all(struct hclge_dev *hdev, bool max, 2022 struct hclge_pkt_buf_alloc *buf_alloc) 2023 { 2024 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2025 u32 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT); 2026 unsigned int i; 2027 2028 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2029 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2030 2031 priv->enable = 0; 2032 priv->wl.low = 0; 2033 priv->wl.high = 0; 2034 priv->buf_size = 0; 2035 2036 if (!(hdev->hw_tc_map & BIT(i))) 2037 continue; 2038 2039 priv->enable = 1; 2040 2041 if (hdev->tm_info.hw_pfc_map & BIT(i)) { 2042 priv->wl.low = max ? aligned_mps : HCLGE_BUF_SIZE_UNIT; 2043 priv->wl.high = roundup(priv->wl.low + aligned_mps, 2044 HCLGE_BUF_SIZE_UNIT); 2045 } else { 2046 priv->wl.low = 0; 2047 priv->wl.high = max ? (aligned_mps * HCLGE_BUF_MUL_BY) : 2048 aligned_mps; 2049 } 2050 2051 priv->buf_size = priv->wl.high + hdev->dv_buf_size; 2052 } 2053 2054 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2055 } 2056 2057 static bool hclge_drop_nopfc_buf_till_fit(struct hclge_dev *hdev, 2058 struct hclge_pkt_buf_alloc *buf_alloc) 2059 { 2060 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2061 int no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); 2062 int i; 2063 2064 /* let the last to be cleared first */ 2065 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2066 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2067 unsigned int mask = BIT((unsigned int)i); 2068 2069 if (hdev->hw_tc_map & mask && 2070 !(hdev->tm_info.hw_pfc_map & mask)) { 2071 /* Clear the no pfc TC private buffer */ 2072 priv->wl.low = 0; 2073 priv->wl.high = 0; 2074 priv->buf_size = 0; 2075 priv->enable = 0; 2076 no_pfc_priv_num--; 2077 } 2078 2079 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2080 no_pfc_priv_num == 0) 2081 break; 2082 } 2083 2084 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2085 } 2086 2087 static bool hclge_drop_pfc_buf_till_fit(struct hclge_dev *hdev, 2088 struct hclge_pkt_buf_alloc *buf_alloc) 2089 { 2090 u32 rx_all = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2091 int pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); 2092 int i; 2093 2094 /* let the last to be cleared first */ 2095 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { 2096 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2097 unsigned int mask = BIT((unsigned int)i); 2098 2099 if (hdev->hw_tc_map & mask && 2100 hdev->tm_info.hw_pfc_map & mask) { 2101 /* Reduce the number of pfc TC with private buffer */ 2102 priv->wl.low = 0; 2103 priv->enable = 0; 2104 priv->wl.high = 0; 2105 priv->buf_size = 0; 2106 pfc_priv_num--; 2107 } 2108 2109 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || 2110 pfc_priv_num == 0) 2111 break; 2112 } 2113 2114 return hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all); 2115 } 2116 2117 static bool hclge_only_alloc_priv_buff(struct hclge_dev *hdev, 2118 struct hclge_pkt_buf_alloc *buf_alloc) 2119 { 2120 #define COMPENSATE_BUFFER 0x3C00 2121 #define COMPENSATE_HALF_MPS_NUM 5 2122 #define PRIV_WL_GAP 0x1800 2123 2124 u32 rx_priv = hdev->pkt_buf_size - hclge_get_tx_buff_alloced(buf_alloc); 2125 u32 tc_num = hclge_get_tc_num(hdev); 2126 u32 half_mps = hdev->mps >> 1; 2127 u32 min_rx_priv; 2128 unsigned int i; 2129 2130 if (tc_num) 2131 rx_priv = rx_priv / tc_num; 2132 2133 if (tc_num <= NEED_RESERVE_TC_NUM) 2134 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 2135 2136 min_rx_priv = hdev->dv_buf_size + COMPENSATE_BUFFER + 2137 COMPENSATE_HALF_MPS_NUM * half_mps; 2138 min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT); 2139 rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT); 2140 if (rx_priv < min_rx_priv) 2141 return false; 2142 2143 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2144 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2145 2146 priv->enable = 0; 2147 priv->wl.low = 0; 2148 priv->wl.high = 0; 2149 priv->buf_size = 0; 2150 2151 if (!(hdev->hw_tc_map & BIT(i))) 2152 continue; 2153 2154 priv->enable = 1; 2155 priv->buf_size = rx_priv; 2156 priv->wl.high = rx_priv - hdev->dv_buf_size; 2157 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 2158 } 2159 2160 buf_alloc->s_buf.buf_size = 0; 2161 2162 return true; 2163 } 2164 2165 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs 2166 * @hdev: pointer to struct hclge_dev 2167 * @buf_alloc: pointer to buffer calculation data 2168 * @return: 0: calculate successful, negative: fail 2169 */ 2170 static int hclge_rx_buffer_calc(struct hclge_dev *hdev, 2171 struct hclge_pkt_buf_alloc *buf_alloc) 2172 { 2173 /* When DCB is not supported, rx private buffer is not allocated. */ 2174 if (!hnae3_dev_dcb_supported(hdev)) { 2175 u32 rx_all = hdev->pkt_buf_size; 2176 2177 rx_all -= hclge_get_tx_buff_alloced(buf_alloc); 2178 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) 2179 return -ENOMEM; 2180 2181 return 0; 2182 } 2183 2184 if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) 2185 return 0; 2186 2187 if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) 2188 return 0; 2189 2190 /* try to decrease the buffer size */ 2191 if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) 2192 return 0; 2193 2194 if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) 2195 return 0; 2196 2197 if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) 2198 return 0; 2199 2200 return -ENOMEM; 2201 } 2202 2203 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, 2204 struct hclge_pkt_buf_alloc *buf_alloc) 2205 { 2206 struct hclge_rx_priv_buff_cmd *req; 2207 struct hclge_desc desc; 2208 int ret; 2209 int i; 2210 2211 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); 2212 req = (struct hclge_rx_priv_buff_cmd *)desc.data; 2213 2214 /* Alloc private buffer TCs */ 2215 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 2216 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; 2217 2218 req->buf_num[i] = 2219 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); 2220 req->buf_num[i] |= 2221 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); 2222 } 2223 2224 req->shared_buf = 2225 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | 2226 (1 << HCLGE_TC0_PRI_BUF_EN_B)); 2227 2228 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2229 if (ret) 2230 dev_err(&hdev->pdev->dev, 2231 "rx private buffer alloc cmd failed %d\n", ret); 2232 2233 return ret; 2234 } 2235 2236 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, 2237 struct hclge_pkt_buf_alloc *buf_alloc) 2238 { 2239 struct hclge_rx_priv_wl_buf *req; 2240 struct hclge_priv_buf *priv; 2241 struct hclge_desc desc[2]; 2242 int i, j; 2243 int ret; 2244 2245 for (i = 0; i < 2; i++) { 2246 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, 2247 false); 2248 req = (struct hclge_rx_priv_wl_buf *)desc[i].data; 2249 2250 /* The first descriptor set the NEXT bit to 1 */ 2251 if (i == 0) 2252 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2253 else 2254 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2255 2256 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2257 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; 2258 2259 priv = &buf_alloc->priv_buf[idx]; 2260 req->tc_wl[j].high = 2261 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); 2262 req->tc_wl[j].high |= 2263 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2264 req->tc_wl[j].low = 2265 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); 2266 req->tc_wl[j].low |= 2267 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2268 } 2269 } 2270 2271 /* Send 2 descriptor at one time */ 2272 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2273 if (ret) 2274 dev_err(&hdev->pdev->dev, 2275 "rx private waterline config cmd failed %d\n", 2276 ret); 2277 return ret; 2278 } 2279 2280 static int hclge_common_thrd_config(struct hclge_dev *hdev, 2281 struct hclge_pkt_buf_alloc *buf_alloc) 2282 { 2283 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; 2284 struct hclge_rx_com_thrd *req; 2285 struct hclge_desc desc[2]; 2286 struct hclge_tc_thrd *tc; 2287 int i, j; 2288 int ret; 2289 2290 for (i = 0; i < 2; i++) { 2291 hclge_cmd_setup_basic_desc(&desc[i], 2292 HCLGE_OPC_RX_COM_THRD_ALLOC, false); 2293 req = (struct hclge_rx_com_thrd *)desc[i].data; 2294 2295 /* The first descriptor set the NEXT bit to 1 */ 2296 if (i == 0) 2297 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2298 else 2299 desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2300 2301 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { 2302 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; 2303 2304 req->com_thrd[j].high = 2305 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); 2306 req->com_thrd[j].high |= 2307 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2308 req->com_thrd[j].low = 2309 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); 2310 req->com_thrd[j].low |= 2311 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2312 } 2313 } 2314 2315 /* Send 2 descriptors at one time */ 2316 ret = hclge_cmd_send(&hdev->hw, desc, 2); 2317 if (ret) 2318 dev_err(&hdev->pdev->dev, 2319 "common threshold config cmd failed %d\n", ret); 2320 return ret; 2321 } 2322 2323 static int hclge_common_wl_config(struct hclge_dev *hdev, 2324 struct hclge_pkt_buf_alloc *buf_alloc) 2325 { 2326 struct hclge_shared_buf *buf = &buf_alloc->s_buf; 2327 struct hclge_rx_com_wl *req; 2328 struct hclge_desc desc; 2329 int ret; 2330 2331 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); 2332 2333 req = (struct hclge_rx_com_wl *)desc.data; 2334 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); 2335 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2336 2337 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); 2338 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); 2339 2340 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2341 if (ret) 2342 dev_err(&hdev->pdev->dev, 2343 "common waterline config cmd failed %d\n", ret); 2344 2345 return ret; 2346 } 2347 2348 int hclge_buffer_alloc(struct hclge_dev *hdev) 2349 { 2350 struct hclge_pkt_buf_alloc *pkt_buf; 2351 int ret; 2352 2353 pkt_buf = kzalloc_obj(*pkt_buf); 2354 if (!pkt_buf) 2355 return -ENOMEM; 2356 2357 ret = hclge_tx_buffer_calc(hdev, pkt_buf); 2358 if (ret) { 2359 dev_err(&hdev->pdev->dev, 2360 "could not calc tx buffer size for all TCs %d\n", ret); 2361 goto out; 2362 } 2363 2364 ret = hclge_tx_buffer_alloc(hdev, pkt_buf); 2365 if (ret) { 2366 dev_err(&hdev->pdev->dev, 2367 "could not alloc tx buffers %d\n", ret); 2368 goto out; 2369 } 2370 2371 ret = hclge_rx_buffer_calc(hdev, pkt_buf); 2372 if (ret) { 2373 dev_err(&hdev->pdev->dev, 2374 "could not calc rx priv buffer size for all TCs %d\n", 2375 ret); 2376 goto out; 2377 } 2378 2379 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); 2380 if (ret) { 2381 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", 2382 ret); 2383 goto out; 2384 } 2385 2386 if (hnae3_dev_dcb_supported(hdev)) { 2387 ret = hclge_rx_priv_wl_config(hdev, pkt_buf); 2388 if (ret) { 2389 dev_err(&hdev->pdev->dev, 2390 "could not configure rx private waterline %d\n", 2391 ret); 2392 goto out; 2393 } 2394 2395 ret = hclge_common_thrd_config(hdev, pkt_buf); 2396 if (ret) { 2397 dev_err(&hdev->pdev->dev, 2398 "could not configure common threshold %d\n", 2399 ret); 2400 goto out; 2401 } 2402 } 2403 2404 ret = hclge_common_wl_config(hdev, pkt_buf); 2405 if (ret) 2406 dev_err(&hdev->pdev->dev, 2407 "could not configure common waterline %d\n", ret); 2408 2409 out: 2410 kfree(pkt_buf); 2411 return ret; 2412 } 2413 2414 static int hclge_init_roce_base_info(struct hclge_vport *vport) 2415 { 2416 struct hnae3_handle *roce = &vport->roce; 2417 struct hnae3_handle *nic = &vport->nic; 2418 struct hclge_dev *hdev = vport->back; 2419 2420 roce->rinfo.num_vectors = vport->back->num_roce_msi; 2421 2422 if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi) 2423 return -EINVAL; 2424 2425 roce->rinfo.base_vector = hdev->num_nic_msi; 2426 2427 roce->rinfo.netdev = nic->kinfo.netdev; 2428 roce->rinfo.roce_io_base = hdev->hw.hw.io_base; 2429 roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base; 2430 2431 roce->pdev = nic->pdev; 2432 roce->ae_algo = nic->ae_algo; 2433 bitmap_copy(roce->numa_node_mask.bits, nic->numa_node_mask.bits, 2434 MAX_NUMNODES); 2435 2436 return 0; 2437 } 2438 2439 static int hclge_init_msi(struct hclge_dev *hdev) 2440 { 2441 struct pci_dev *pdev = hdev->pdev; 2442 int vectors; 2443 int i; 2444 2445 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM, 2446 hdev->num_msi, 2447 PCI_IRQ_MSI | PCI_IRQ_MSIX); 2448 if (vectors < 0) { 2449 dev_err(&pdev->dev, 2450 "failed(%d) to allocate MSI/MSI-X vectors\n", 2451 vectors); 2452 return vectors; 2453 } 2454 if (vectors < hdev->num_msi) 2455 dev_warn(&hdev->pdev->dev, 2456 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n", 2457 hdev->num_msi, vectors); 2458 2459 hdev->num_msi = vectors; 2460 hdev->num_msi_left = vectors; 2461 2462 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, 2463 sizeof(u16), GFP_KERNEL); 2464 if (!hdev->vector_status) { 2465 pci_free_irq_vectors(pdev); 2466 return -ENOMEM; 2467 } 2468 2469 for (i = 0; i < hdev->num_msi; i++) 2470 hdev->vector_status[i] = HCLGE_INVALID_VPORT; 2471 2472 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, 2473 sizeof(int), GFP_KERNEL); 2474 if (!hdev->vector_irq) { 2475 pci_free_irq_vectors(pdev); 2476 return -ENOMEM; 2477 } 2478 2479 return 0; 2480 } 2481 2482 static u8 hclge_check_speed_dup(u8 duplex, int speed) 2483 { 2484 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M)) 2485 duplex = HCLGE_MAC_FULL; 2486 2487 return duplex; 2488 } 2489 2490 static struct hclge_mac_speed_map hclge_mac_speed_map_to_fw[] = { 2491 {HCLGE_MAC_SPEED_10M, HCLGE_FW_MAC_SPEED_10M}, 2492 {HCLGE_MAC_SPEED_100M, HCLGE_FW_MAC_SPEED_100M}, 2493 {HCLGE_MAC_SPEED_1G, HCLGE_FW_MAC_SPEED_1G}, 2494 {HCLGE_MAC_SPEED_10G, HCLGE_FW_MAC_SPEED_10G}, 2495 {HCLGE_MAC_SPEED_25G, HCLGE_FW_MAC_SPEED_25G}, 2496 {HCLGE_MAC_SPEED_40G, HCLGE_FW_MAC_SPEED_40G}, 2497 {HCLGE_MAC_SPEED_50G, HCLGE_FW_MAC_SPEED_50G}, 2498 {HCLGE_MAC_SPEED_100G, HCLGE_FW_MAC_SPEED_100G}, 2499 {HCLGE_MAC_SPEED_200G, HCLGE_FW_MAC_SPEED_200G}, 2500 }; 2501 2502 static int hclge_convert_to_fw_speed(u32 speed_drv, u32 *speed_fw) 2503 { 2504 u16 i; 2505 2506 for (i = 0; i < ARRAY_SIZE(hclge_mac_speed_map_to_fw); i++) { 2507 if (hclge_mac_speed_map_to_fw[i].speed_drv == speed_drv) { 2508 *speed_fw = hclge_mac_speed_map_to_fw[i].speed_fw; 2509 return 0; 2510 } 2511 } 2512 2513 return -EINVAL; 2514 } 2515 2516 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, 2517 u8 duplex, u8 lane_num) 2518 { 2519 struct hclge_config_mac_speed_dup_cmd *req; 2520 struct hclge_desc desc; 2521 u32 speed_fw; 2522 int ret; 2523 2524 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 2525 2526 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); 2527 2528 if (duplex) 2529 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, 1); 2530 2531 ret = hclge_convert_to_fw_speed(speed, &speed_fw); 2532 if (ret) { 2533 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); 2534 return ret; 2535 } 2536 2537 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, HCLGE_CFG_SPEED_S, 2538 speed_fw); 2539 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, 2540 1); 2541 req->lane_num = lane_num; 2542 2543 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2544 if (ret) { 2545 dev_err(&hdev->pdev->dev, 2546 "mac speed/duplex config cmd failed %d.\n", ret); 2547 return ret; 2548 } 2549 2550 return 0; 2551 } 2552 2553 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex, u8 lane_num) 2554 { 2555 struct hclge_mac *mac = &hdev->hw.mac; 2556 int ret; 2557 2558 duplex = hclge_check_speed_dup(duplex, speed); 2559 if (!mac->support_autoneg && mac->speed == (u32)speed && 2560 mac->duplex == duplex && (mac->lane_num == lane_num || lane_num == 0)) 2561 return 0; 2562 2563 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num); 2564 if (ret) 2565 return ret; 2566 2567 hdev->hw.mac.speed = speed; 2568 hdev->hw.mac.duplex = duplex; 2569 if (!lane_num) 2570 hdev->hw.mac.lane_num = lane_num; 2571 2572 return 0; 2573 } 2574 2575 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, 2576 u8 duplex, u8 lane_num) 2577 { 2578 struct hclge_vport *vport = hclge_get_vport(handle); 2579 struct hclge_dev *hdev = vport->back; 2580 int ret; 2581 2582 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num); 2583 2584 if (ret) 2585 return ret; 2586 2587 hdev->hw.mac.req_lane_num = lane_num; 2588 if (speed != SPEED_UNKNOWN) 2589 hdev->hw.mac.req_speed = (u32)speed; 2590 if (duplex != DUPLEX_UNKNOWN) 2591 hdev->hw.mac.req_duplex = duplex; 2592 2593 return 0; 2594 } 2595 2596 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) 2597 { 2598 struct hclge_config_auto_neg_cmd *req; 2599 struct hclge_desc desc; 2600 u32 flag = 0; 2601 int ret; 2602 2603 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); 2604 2605 req = (struct hclge_config_auto_neg_cmd *)desc.data; 2606 if (enable) 2607 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, 1U); 2608 req->cfg_an_cmd_flag = cpu_to_le32(flag); 2609 2610 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2611 if (ret) 2612 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", 2613 ret); 2614 2615 return ret; 2616 } 2617 2618 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) 2619 { 2620 struct hclge_vport *vport = hclge_get_vport(handle); 2621 struct hclge_dev *hdev = vport->back; 2622 int ret; 2623 2624 if (!hdev->hw.mac.support_autoneg) { 2625 if (enable) { 2626 dev_err(&hdev->pdev->dev, 2627 "autoneg is not supported by current port\n"); 2628 return -EOPNOTSUPP; 2629 } else { 2630 return 0; 2631 } 2632 } 2633 2634 ret = hclge_set_autoneg_en(hdev, enable); 2635 if (!ret) 2636 hdev->hw.mac.req_autoneg = enable; 2637 return ret; 2638 } 2639 2640 static int hclge_get_autoneg(struct hnae3_handle *handle) 2641 { 2642 struct hclge_vport *vport = hclge_get_vport(handle); 2643 struct hclge_dev *hdev = vport->back; 2644 struct phy_device *phydev = hdev->hw.mac.phydev; 2645 2646 if (phydev) 2647 return phydev->autoneg; 2648 2649 return hdev->hw.mac.autoneg; 2650 } 2651 2652 static int hclge_restart_autoneg(struct hnae3_handle *handle) 2653 { 2654 struct hclge_vport *vport = hclge_get_vport(handle); 2655 struct hclge_dev *hdev = vport->back; 2656 int ret; 2657 2658 dev_dbg(&hdev->pdev->dev, "restart autoneg\n"); 2659 2660 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 2661 if (ret) 2662 return ret; 2663 return hclge_notify_client(hdev, HNAE3_UP_CLIENT); 2664 } 2665 2666 static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt) 2667 { 2668 struct hclge_vport *vport = hclge_get_vport(handle); 2669 struct hclge_dev *hdev = vport->back; 2670 2671 if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) 2672 return hclge_set_autoneg_en(hdev, !halt); 2673 2674 return 0; 2675 } 2676 2677 static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev, 2678 struct hclge_desc *desc, u32 desc_len) 2679 { 2680 u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2; 2681 u32 desc_index = 0; 2682 u32 data_index = 0; 2683 u32 i; 2684 2685 for (i = 0; i < lane_size; i++) { 2686 if (data_index >= HCLGE_DESC_DATA_LEN) { 2687 desc_index++; 2688 data_index = 0; 2689 } 2690 2691 if (desc_index >= desc_len) 2692 return; 2693 2694 hdev->fec_stats.per_lanes[i] += 2695 le32_to_cpu(desc[desc_index].data[data_index]); 2696 data_index++; 2697 } 2698 } 2699 2700 static void hclge_parse_fec_stats(struct hclge_dev *hdev, 2701 struct hclge_desc *desc, u32 desc_len) 2702 { 2703 struct hclge_query_fec_stats_cmd *req; 2704 2705 req = (struct hclge_query_fec_stats_cmd *)desc[0].data; 2706 2707 hdev->fec_stats.base_r_lane_num = req->base_r_lane_num; 2708 hdev->fec_stats.rs_corr_blocks += 2709 le32_to_cpu(req->rs_fec_corr_blocks); 2710 hdev->fec_stats.rs_uncorr_blocks += 2711 le32_to_cpu(req->rs_fec_uncorr_blocks); 2712 hdev->fec_stats.rs_error_blocks += 2713 le32_to_cpu(req->rs_fec_error_blocks); 2714 hdev->fec_stats.base_r_corr_blocks += 2715 le32_to_cpu(req->base_r_fec_corr_blocks); 2716 hdev->fec_stats.base_r_uncorr_blocks += 2717 le32_to_cpu(req->base_r_fec_uncorr_blocks); 2718 2719 hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1); 2720 } 2721 2722 static int hclge_update_fec_stats_hw(struct hclge_dev *hdev) 2723 { 2724 struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM]; 2725 int ret; 2726 u32 i; 2727 2728 for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) { 2729 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, 2730 true); 2731 if (i != (HCLGE_FEC_STATS_CMD_NUM - 1)) 2732 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 2733 } 2734 2735 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); 2736 if (ret) 2737 return ret; 2738 2739 hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM); 2740 2741 return 0; 2742 } 2743 2744 static void hclge_update_fec_stats(struct hclge_dev *hdev) 2745 { 2746 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 2747 int ret; 2748 2749 if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || 2750 test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state)) 2751 return; 2752 2753 ret = hclge_update_fec_stats_hw(hdev); 2754 if (ret) 2755 dev_err(&hdev->pdev->dev, 2756 "failed to update fec stats, ret = %d\n", ret); 2757 2758 clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state); 2759 } 2760 2761 static void hclge_get_fec_stats_total(struct hclge_dev *hdev, 2762 struct ethtool_fec_stats *fec_stats) 2763 { 2764 fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks; 2765 fec_stats->uncorrectable_blocks.total = 2766 hdev->fec_stats.rs_uncorr_blocks; 2767 } 2768 2769 static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev, 2770 struct ethtool_fec_stats *fec_stats) 2771 { 2772 u32 i; 2773 2774 if (hdev->fec_stats.base_r_lane_num == 0 || 2775 hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) { 2776 dev_err(&hdev->pdev->dev, 2777 "fec stats lane number(%llu) is invalid\n", 2778 hdev->fec_stats.base_r_lane_num); 2779 return; 2780 } 2781 2782 for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) { 2783 fec_stats->corrected_blocks.lanes[i] = 2784 hdev->fec_stats.base_r_corr_per_lanes[i]; 2785 fec_stats->uncorrectable_blocks.lanes[i] = 2786 hdev->fec_stats.base_r_uncorr_per_lanes[i]; 2787 } 2788 } 2789 2790 static void hclge_comm_get_fec_stats(struct hclge_dev *hdev, 2791 struct ethtool_fec_stats *fec_stats) 2792 { 2793 u32 fec_mode = hdev->hw.mac.fec_mode; 2794 2795 switch (fec_mode) { 2796 case BIT(HNAE3_FEC_RS): 2797 case BIT(HNAE3_FEC_LLRS): 2798 hclge_get_fec_stats_total(hdev, fec_stats); 2799 break; 2800 case BIT(HNAE3_FEC_BASER): 2801 hclge_get_fec_stats_lanes(hdev, fec_stats); 2802 break; 2803 default: 2804 dev_err(&hdev->pdev->dev, 2805 "fec stats is not supported by current fec mode(0x%x)\n", 2806 fec_mode); 2807 break; 2808 } 2809 } 2810 2811 static void hclge_get_fec_stats(struct hnae3_handle *handle, 2812 struct ethtool_fec_stats *fec_stats) 2813 { 2814 struct hclge_vport *vport = hclge_get_vport(handle); 2815 struct hclge_dev *hdev = vport->back; 2816 u32 fec_mode = hdev->hw.mac.fec_mode; 2817 2818 if (fec_mode == BIT(HNAE3_FEC_NONE) || 2819 fec_mode == BIT(HNAE3_FEC_AUTO) || 2820 fec_mode == BIT(HNAE3_FEC_USER_DEF)) 2821 return; 2822 2823 hclge_update_fec_stats(hdev); 2824 2825 hclge_comm_get_fec_stats(hdev, fec_stats); 2826 } 2827 2828 static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode) 2829 { 2830 struct hclge_config_fec_cmd *req; 2831 struct hclge_desc desc; 2832 int ret; 2833 2834 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_FEC_MODE, false); 2835 2836 req = (struct hclge_config_fec_cmd *)desc.data; 2837 if (fec_mode & BIT(HNAE3_FEC_AUTO)) 2838 hnae3_set_bit(req->fec_mode, HCLGE_MAC_CFG_FEC_AUTO_EN_B, 1); 2839 if (fec_mode & BIT(HNAE3_FEC_RS)) 2840 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2841 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS); 2842 if (fec_mode & BIT(HNAE3_FEC_LLRS)) 2843 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2844 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS); 2845 if (fec_mode & BIT(HNAE3_FEC_BASER)) 2846 hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M, 2847 HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER); 2848 2849 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2850 if (ret) 2851 dev_err(&hdev->pdev->dev, "set fec mode failed %d.\n", ret); 2852 2853 return ret; 2854 } 2855 2856 static int hclge_set_fec(struct hnae3_handle *handle, u32 fec_mode) 2857 { 2858 struct hclge_vport *vport = hclge_get_vport(handle); 2859 struct hclge_dev *hdev = vport->back; 2860 struct hclge_mac *mac = &hdev->hw.mac; 2861 int ret; 2862 2863 if (fec_mode && !(mac->fec_ability & fec_mode)) { 2864 dev_err(&hdev->pdev->dev, "unsupported fec mode\n"); 2865 return -EINVAL; 2866 } 2867 2868 ret = hclge_set_fec_hw(hdev, fec_mode); 2869 if (ret) 2870 return ret; 2871 2872 mac->user_fec_mode = fec_mode | BIT(HNAE3_FEC_USER_DEF); 2873 return 0; 2874 } 2875 2876 static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability, 2877 u8 *fec_mode) 2878 { 2879 struct hclge_vport *vport = hclge_get_vport(handle); 2880 struct hclge_dev *hdev = vport->back; 2881 struct hclge_mac *mac = &hdev->hw.mac; 2882 2883 if (fec_ability) 2884 *fec_ability = mac->fec_ability; 2885 if (fec_mode) 2886 *fec_mode = mac->fec_mode; 2887 } 2888 2889 static int hclge_mac_init(struct hclge_dev *hdev) 2890 { 2891 struct hclge_mac *mac = &hdev->hw.mac; 2892 int ret; 2893 2894 hdev->support_sfp_query = true; 2895 2896 if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 2897 hdev->hw.mac.duplex = HCLGE_MAC_FULL; 2898 2899 mac->link = 0; 2900 2901 if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) { 2902 ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); 2903 if (ret) 2904 return ret; 2905 } 2906 2907 ret = hclge_set_mac_mtu(hdev, hdev->mps); 2908 if (ret) { 2909 dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); 2910 return ret; 2911 } 2912 2913 ret = hclge_set_default_loopback(hdev); 2914 if (ret) 2915 return ret; 2916 2917 ret = hclge_buffer_alloc(hdev); 2918 if (ret) 2919 dev_err(&hdev->pdev->dev, 2920 "allocate buffer fail, ret=%d\n", ret); 2921 2922 return ret; 2923 } 2924 2925 static void hclge_mbx_task_schedule(struct hclge_dev *hdev) 2926 { 2927 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2928 !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) { 2929 hdev->last_mbx_scheduled = jiffies; 2930 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2931 } 2932 } 2933 2934 static void hclge_reset_task_schedule(struct hclge_dev *hdev) 2935 { 2936 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2937 test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) && 2938 !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) { 2939 hdev->last_rst_scheduled = jiffies; 2940 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2941 } 2942 } 2943 2944 static void hclge_errhand_task_schedule(struct hclge_dev *hdev) 2945 { 2946 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2947 !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 2948 mod_delayed_work(hclge_wq, &hdev->service_task, 0); 2949 } 2950 2951 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time) 2952 { 2953 if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) && 2954 !test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 2955 mod_delayed_work(hclge_wq, &hdev->service_task, delay_time); 2956 } 2957 2958 static int hclge_get_mac_link_status(struct hclge_dev *hdev, int *link_status) 2959 { 2960 struct hclge_link_status_cmd *req; 2961 struct hclge_desc desc; 2962 int ret; 2963 2964 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); 2965 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2966 if (ret) { 2967 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", 2968 ret); 2969 return ret; 2970 } 2971 2972 req = (struct hclge_link_status_cmd *)desc.data; 2973 *link_status = (req->status & HCLGE_LINK_STATUS_UP_M) > 0 ? 2974 HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 2975 2976 return 0; 2977 } 2978 2979 static int hclge_get_mac_phy_link(struct hclge_dev *hdev, int *link_status) 2980 { 2981 struct phy_device *phydev = hdev->hw.mac.phydev; 2982 2983 *link_status = HCLGE_LINK_STATUS_DOWN; 2984 2985 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) 2986 return 0; 2987 2988 if (phydev && (phydev->state != PHY_RUNNING || !phydev->link)) 2989 return 0; 2990 2991 return hclge_get_mac_link_status(hdev, link_status); 2992 } 2993 2994 static void hclge_push_link_status(struct hclge_dev *hdev) 2995 { 2996 struct hclge_vport *vport; 2997 int ret; 2998 u16 i; 2999 3000 for (i = 0; i < pci_num_vf(hdev->pdev); i++) { 3001 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 3002 3003 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) || 3004 vport->vf_info.link_state != IFLA_VF_LINK_STATE_AUTO) 3005 continue; 3006 3007 ret = hclge_push_vf_link_status(vport); 3008 if (ret) { 3009 dev_err(&hdev->pdev->dev, 3010 "failed to push link status to vf%u, ret = %d\n", 3011 i, ret); 3012 } 3013 } 3014 } 3015 3016 static void hclge_update_link_status(struct hclge_dev *hdev) 3017 { 3018 struct hnae3_handle *handle = &hdev->vport[0].nic; 3019 struct hnae3_client *client = hdev->nic_client; 3020 int state; 3021 int ret; 3022 3023 if (!client) 3024 return; 3025 3026 if (test_and_set_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state)) 3027 return; 3028 3029 ret = hclge_get_mac_phy_link(hdev, &state); 3030 if (ret) { 3031 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3032 return; 3033 } 3034 3035 if (state != hdev->hw.mac.link) { 3036 hdev->hw.mac.link = state; 3037 if (state == HCLGE_LINK_STATUS_UP) 3038 hclge_update_port_info(hdev); 3039 3040 client->ops->link_status_change(handle, state); 3041 hclge_config_mac_tnl_int(hdev, state); 3042 3043 if (test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state)) { 3044 struct hnae3_handle *rhandle = &hdev->vport[0].roce; 3045 struct hnae3_client *rclient = hdev->roce_client; 3046 3047 if (rclient && rclient->ops->link_status_change) 3048 rclient->ops->link_status_change(rhandle, 3049 state); 3050 } 3051 3052 hclge_push_link_status(hdev); 3053 } 3054 3055 clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 3056 } 3057 3058 static void hclge_update_speed_advertising(struct hclge_mac *mac) 3059 { 3060 u32 speed_ability; 3061 3062 if (hclge_get_speed_bit(mac->speed, &speed_ability)) 3063 return; 3064 3065 switch (mac->module_type) { 3066 case HNAE3_MODULE_TYPE_FIBRE_LR: 3067 hclge_convert_setting_lr(speed_ability, mac->advertising); 3068 break; 3069 case HNAE3_MODULE_TYPE_FIBRE_SR: 3070 case HNAE3_MODULE_TYPE_AOC: 3071 hclge_convert_setting_sr(speed_ability, mac->advertising); 3072 break; 3073 case HNAE3_MODULE_TYPE_CR: 3074 hclge_convert_setting_cr(speed_ability, mac->advertising); 3075 break; 3076 case HNAE3_MODULE_TYPE_KR: 3077 hclge_convert_setting_kr(speed_ability, mac->advertising); 3078 break; 3079 default: 3080 break; 3081 } 3082 } 3083 3084 static void hclge_update_fec_advertising(struct hclge_mac *mac) 3085 { 3086 if (mac->fec_mode & BIT(HNAE3_FEC_RS)) 3087 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 3088 mac->advertising); 3089 else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS)) 3090 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 3091 mac->advertising); 3092 else if (mac->fec_mode & BIT(HNAE3_FEC_BASER)) 3093 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 3094 mac->advertising); 3095 else 3096 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 3097 mac->advertising); 3098 } 3099 3100 static void hclge_update_pause_advertising(struct hclge_dev *hdev) 3101 { 3102 struct hclge_mac *mac = &hdev->hw.mac; 3103 bool rx_en, tx_en; 3104 3105 switch (hdev->fc_mode_last_time) { 3106 case HCLGE_FC_RX_PAUSE: 3107 rx_en = true; 3108 tx_en = false; 3109 break; 3110 case HCLGE_FC_TX_PAUSE: 3111 rx_en = false; 3112 tx_en = true; 3113 break; 3114 case HCLGE_FC_FULL: 3115 rx_en = true; 3116 tx_en = true; 3117 break; 3118 default: 3119 rx_en = false; 3120 tx_en = false; 3121 break; 3122 } 3123 3124 linkmode_set_pause(mac->advertising, tx_en, rx_en); 3125 } 3126 3127 static void hclge_update_advertising(struct hclge_dev *hdev) 3128 { 3129 struct hclge_mac *mac = &hdev->hw.mac; 3130 3131 linkmode_zero(mac->advertising); 3132 hclge_update_speed_advertising(mac); 3133 hclge_update_fec_advertising(mac); 3134 hclge_update_pause_advertising(hdev); 3135 } 3136 3137 static void hclge_update_port_capability(struct hclge_dev *hdev, 3138 struct hclge_mac *mac) 3139 { 3140 if (hnae3_dev_fec_supported(hdev)) 3141 hclge_convert_setting_fec(mac); 3142 3143 /* firmware can not identify back plane type, the media type 3144 * read from configuration can help deal it 3145 */ 3146 if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE && 3147 mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN) 3148 mac->module_type = HNAE3_MODULE_TYPE_KR; 3149 else if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3150 mac->module_type = HNAE3_MODULE_TYPE_TP; 3151 3152 if (mac->support_autoneg) { 3153 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mac->supported); 3154 linkmode_copy(mac->advertising, mac->supported); 3155 } else { 3156 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3157 mac->supported); 3158 hclge_update_advertising(hdev); 3159 } 3160 } 3161 3162 static int hclge_get_sfp_speed(struct hclge_dev *hdev, u32 *speed) 3163 { 3164 struct hclge_sfp_info_cmd *resp; 3165 struct hclge_desc desc; 3166 int ret; 3167 3168 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3169 resp = (struct hclge_sfp_info_cmd *)desc.data; 3170 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3171 if (ret == -EOPNOTSUPP) { 3172 dev_warn(&hdev->pdev->dev, 3173 "IMP do not support get SFP speed %d\n", ret); 3174 return ret; 3175 } else if (ret) { 3176 dev_err(&hdev->pdev->dev, "get sfp speed failed %d\n", ret); 3177 return ret; 3178 } 3179 3180 *speed = le32_to_cpu(resp->speed); 3181 3182 return 0; 3183 } 3184 3185 static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac) 3186 { 3187 struct hclge_sfp_info_cmd *resp; 3188 struct hclge_desc desc; 3189 int ret; 3190 3191 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_INFO, true); 3192 resp = (struct hclge_sfp_info_cmd *)desc.data; 3193 3194 resp->query_type = QUERY_ACTIVE_SPEED; 3195 3196 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3197 if (ret == -EOPNOTSUPP) { 3198 dev_warn(&hdev->pdev->dev, 3199 "IMP does not support get SFP info %d\n", ret); 3200 return ret; 3201 } else if (ret) { 3202 dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); 3203 return ret; 3204 } 3205 3206 /* In some case, mac speed get from IMP may be 0, it shouldn't be 3207 * set to mac->speed. 3208 */ 3209 if (!le32_to_cpu(resp->speed)) 3210 return 0; 3211 3212 mac->speed = le32_to_cpu(resp->speed); 3213 /* if resp->speed_ability is 0, it means it's an old version 3214 * firmware, do not update these params 3215 */ 3216 if (resp->speed_ability) { 3217 mac->module_type = le32_to_cpu(resp->module_type); 3218 mac->speed_ability = le32_to_cpu(resp->speed_ability); 3219 mac->autoneg = resp->autoneg; 3220 mac->support_autoneg = resp->autoneg_ability; 3221 mac->speed_type = QUERY_ACTIVE_SPEED; 3222 mac->lane_num = resp->lane_num; 3223 if (!resp->active_fec) 3224 mac->fec_mode = 0; 3225 else 3226 mac->fec_mode = BIT(resp->active_fec); 3227 mac->fec_ability = resp->fec_ability; 3228 } else { 3229 mac->speed_type = QUERY_SFP_SPEED; 3230 } 3231 3232 return 0; 3233 } 3234 3235 static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle, 3236 struct ethtool_link_ksettings *cmd) 3237 { 3238 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3239 struct hclge_vport *vport = hclge_get_vport(handle); 3240 struct hclge_phy_link_ksetting_0_cmd *req0; 3241 struct hclge_phy_link_ksetting_1_cmd *req1; 3242 u32 supported, advertising, lp_advertising; 3243 struct hclge_dev *hdev = vport->back; 3244 int ret; 3245 3246 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3247 true); 3248 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3249 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3250 true); 3251 3252 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3253 if (ret) { 3254 dev_err(&hdev->pdev->dev, 3255 "failed to get phy link ksetting, ret = %d.\n", ret); 3256 return ret; 3257 } 3258 3259 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3260 cmd->base.autoneg = req0->autoneg; 3261 cmd->base.speed = le32_to_cpu(req0->speed); 3262 cmd->base.duplex = req0->duplex; 3263 cmd->base.port = req0->port; 3264 cmd->base.transceiver = req0->transceiver; 3265 cmd->base.phy_address = req0->phy_address; 3266 cmd->base.eth_tp_mdix = req0->eth_tp_mdix; 3267 cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl; 3268 supported = le32_to_cpu(req0->supported); 3269 advertising = le32_to_cpu(req0->advertising); 3270 lp_advertising = le32_to_cpu(req0->lp_advertising); 3271 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3272 supported); 3273 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3274 advertising); 3275 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising, 3276 lp_advertising); 3277 3278 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3279 cmd->base.master_slave_cfg = req1->master_slave_cfg; 3280 cmd->base.master_slave_state = req1->master_slave_state; 3281 3282 return 0; 3283 } 3284 3285 static int 3286 hclge_ethtool_ksettings_set(struct hnae3_handle *handle, 3287 const struct ethtool_link_ksettings *cmd) 3288 { 3289 struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM]; 3290 struct hclge_vport *vport = hclge_get_vport(handle); 3291 struct hclge_phy_link_ksetting_0_cmd *req0; 3292 struct hclge_phy_link_ksetting_1_cmd *req1; 3293 struct hclge_dev *hdev = vport->back; 3294 u32 advertising; 3295 int ret; 3296 3297 if (cmd->base.autoneg == AUTONEG_DISABLE && 3298 ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) || 3299 (cmd->base.duplex != DUPLEX_HALF && 3300 cmd->base.duplex != DUPLEX_FULL))) 3301 return -EINVAL; 3302 3303 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING, 3304 false); 3305 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 3306 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING, 3307 false); 3308 3309 req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data; 3310 req0->autoneg = cmd->base.autoneg; 3311 req0->speed = cpu_to_le32(cmd->base.speed); 3312 req0->duplex = cmd->base.duplex; 3313 ethtool_convert_link_mode_to_legacy_u32(&advertising, 3314 cmd->link_modes.advertising); 3315 req0->advertising = cpu_to_le32(advertising); 3316 req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl; 3317 3318 req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data; 3319 req1->master_slave_cfg = cmd->base.master_slave_cfg; 3320 3321 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); 3322 if (ret) { 3323 dev_err(&hdev->pdev->dev, 3324 "failed to set phy link ksettings, ret = %d.\n", ret); 3325 return ret; 3326 } 3327 3328 linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising); 3329 return 0; 3330 } 3331 3332 static int 3333 hclge_set_phy_link_ksettings(struct hnae3_handle *handle, 3334 const struct ethtool_link_ksettings *cmd) 3335 { 3336 struct hclge_vport *vport = hclge_get_vport(handle); 3337 struct hclge_dev *hdev = vport->back; 3338 int ret = -ENODEV; 3339 3340 if (hnae3_dev_phy_imp_supported(hdev)) { 3341 ret = hclge_ethtool_ksettings_set(handle, cmd); 3342 } else if (handle->netdev->phydev) { 3343 if (cmd->base.speed == SPEED_1000 && 3344 cmd->base.autoneg == AUTONEG_DISABLE) 3345 return -EINVAL; 3346 ret = phy_ethtool_ksettings_set(handle->netdev->phydev, cmd); 3347 } 3348 if (ret) 3349 return ret; 3350 3351 hdev->hw.mac.req_autoneg = cmd->base.autoneg; 3352 if (cmd->base.speed != SPEED_UNKNOWN) 3353 hdev->hw.mac.req_speed = cmd->base.speed; 3354 if (cmd->base.duplex != DUPLEX_UNKNOWN) 3355 hdev->hw.mac.req_duplex = cmd->base.duplex; 3356 3357 return 0; 3358 } 3359 3360 static int hclge_update_tp_port_info(struct hclge_dev *hdev) 3361 { 3362 struct ethtool_link_ksettings cmd; 3363 int ret; 3364 3365 if (!hnae3_dev_phy_imp_supported(hdev)) 3366 return 0; 3367 3368 ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd); 3369 if (ret) 3370 return ret; 3371 3372 hdev->hw.mac.autoneg = cmd.base.autoneg; 3373 hdev->hw.mac.speed = cmd.base.speed; 3374 hdev->hw.mac.duplex = cmd.base.duplex; 3375 linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising); 3376 3377 return 0; 3378 } 3379 3380 static int hclge_tp_port_init(struct hclge_dev *hdev) 3381 { 3382 struct ethtool_link_ksettings cmd; 3383 3384 if (!hnae3_dev_phy_imp_supported(hdev)) 3385 return 0; 3386 3387 cmd.base.autoneg = hdev->hw.mac.req_autoneg; 3388 cmd.base.speed = hdev->hw.mac.req_speed; 3389 cmd.base.duplex = hdev->hw.mac.req_duplex; 3390 linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising); 3391 3392 return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd); 3393 } 3394 3395 static int hclge_update_port_info(struct hclge_dev *hdev) 3396 { 3397 struct hclge_mac *mac = &hdev->hw.mac; 3398 u32 speed; 3399 int ret; 3400 3401 /* get the port info from SFP cmd if not copper port */ 3402 if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER) 3403 return hclge_update_tp_port_info(hdev); 3404 3405 /* if IMP does not support get SFP/qSFP info, return directly */ 3406 if (!hdev->support_sfp_query) 3407 return 0; 3408 3409 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3410 speed = mac->speed; 3411 ret = hclge_get_sfp_info(hdev, mac); 3412 } else { 3413 speed = HCLGE_MAC_SPEED_UNKNOWN; 3414 ret = hclge_get_sfp_speed(hdev, &speed); 3415 } 3416 3417 if (ret == -EOPNOTSUPP) { 3418 hdev->support_sfp_query = false; 3419 return ret; 3420 } else if (ret) { 3421 return ret; 3422 } 3423 3424 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 3425 if (mac->speed_type == QUERY_ACTIVE_SPEED) { 3426 hclge_update_port_capability(hdev, mac); 3427 if (mac->speed != speed) 3428 (void)hclge_tm_port_shaper_cfg(hdev); 3429 return 0; 3430 } 3431 return hclge_cfg_mac_speed_dup(hdev, mac->speed, 3432 HCLGE_MAC_FULL, mac->lane_num); 3433 } else { 3434 if (speed == HCLGE_MAC_SPEED_UNKNOWN) 3435 return 0; /* do nothing if no SFP */ 3436 3437 /* must config full duplex for SFP */ 3438 return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0); 3439 } 3440 } 3441 3442 static int hclge_get_status(struct hnae3_handle *handle) 3443 { 3444 struct hclge_vport *vport = hclge_get_vport(handle); 3445 struct hclge_dev *hdev = vport->back; 3446 3447 hclge_update_link_status(hdev); 3448 3449 return hdev->hw.mac.link; 3450 } 3451 3452 struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf) 3453 { 3454 if (!pci_num_vf(hdev->pdev)) { 3455 dev_err(&hdev->pdev->dev, 3456 "SRIOV is disabled, can not get vport(%d) info.\n", vf); 3457 return NULL; 3458 } 3459 3460 if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) { 3461 dev_err(&hdev->pdev->dev, 3462 "vf id(%d) is out of range(0 <= vfid < %d)\n", 3463 vf, pci_num_vf(hdev->pdev)); 3464 return NULL; 3465 } 3466 3467 /* VF start from 1 in vport */ 3468 vf += HCLGE_VF_VPORT_START_NUM; 3469 return &hdev->vport[vf]; 3470 } 3471 3472 static int hclge_get_vf_config(struct hnae3_handle *handle, int vf, 3473 struct ifla_vf_info *ivf) 3474 { 3475 struct hclge_vport *vport = hclge_get_vport(handle); 3476 struct hclge_dev *hdev = vport->back; 3477 3478 vport = hclge_get_vf_vport(hdev, vf); 3479 if (!vport) 3480 return -EINVAL; 3481 3482 ivf->vf = vf; 3483 ivf->linkstate = vport->vf_info.link_state; 3484 ivf->spoofchk = vport->vf_info.spoofchk; 3485 ivf->trusted = vport->vf_info.trusted; 3486 ivf->min_tx_rate = 0; 3487 ivf->max_tx_rate = vport->vf_info.max_tx_rate; 3488 ivf->vlan = vport->port_base_vlan_cfg.vlan_info.vlan_tag; 3489 ivf->vlan_proto = htons(vport->port_base_vlan_cfg.vlan_info.vlan_proto); 3490 ivf->qos = vport->port_base_vlan_cfg.vlan_info.qos; 3491 ether_addr_copy(ivf->mac, vport->vf_info.mac); 3492 3493 return 0; 3494 } 3495 3496 static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf, 3497 int link_state) 3498 { 3499 struct hclge_vport *vport = hclge_get_vport(handle); 3500 struct hclge_dev *hdev = vport->back; 3501 int link_state_old; 3502 int ret; 3503 3504 vport = hclge_get_vf_vport(hdev, vf); 3505 if (!vport) 3506 return -EINVAL; 3507 3508 link_state_old = vport->vf_info.link_state; 3509 vport->vf_info.link_state = link_state; 3510 3511 /* return success directly if the VF is unalive, VF will 3512 * query link state itself when it starts work. 3513 */ 3514 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 3515 return 0; 3516 3517 ret = hclge_push_vf_link_status(vport); 3518 if (ret) { 3519 vport->vf_info.link_state = link_state_old; 3520 dev_err(&hdev->pdev->dev, 3521 "failed to push vf%d link status, ret = %d\n", vf, ret); 3522 } 3523 3524 return ret; 3525 } 3526 3527 static int hclge_set_pfc_storm_para(struct hclge_dev *hdev, 3528 struct hnae3_pfc_storm_para *para) 3529 { 3530 struct hclge_pfc_storm_para_cmd *para_cmd; 3531 struct hclge_desc desc; 3532 int ret; 3533 3534 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) 3535 return -EOPNOTSUPP; 3536 3537 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PAUSE_STORM_PARA, 3538 false); 3539 para_cmd = (struct hclge_pfc_storm_para_cmd *)desc.data; 3540 para_cmd->dir = cpu_to_le32(para->dir); 3541 para_cmd->enable = cpu_to_le32(para->enable); 3542 para_cmd->period_ms = cpu_to_le32(para->period_ms); 3543 para_cmd->times = cpu_to_le32(para->times); 3544 para_cmd->recovery_period_ms = cpu_to_le32(para->recovery_period_ms); 3545 3546 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3547 if (ret) 3548 dev_err(&hdev->pdev->dev, 3549 "failed to set pfc storm para, ret = %d\n", ret); 3550 return ret; 3551 } 3552 3553 static int hclge_get_pfc_storm_para(struct hclge_dev *hdev, 3554 struct hnae3_pfc_storm_para *para) 3555 { 3556 struct hclge_pfc_storm_para_cmd *para_cmd; 3557 struct hclge_desc desc; 3558 int ret; 3559 3560 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) 3561 return -EOPNOTSUPP; 3562 3563 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PAUSE_STORM_PARA, true); 3564 para_cmd = (struct hclge_pfc_storm_para_cmd *)desc.data; 3565 para_cmd->dir = cpu_to_le32(para->dir); 3566 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 3567 if (ret) { 3568 dev_err(&hdev->pdev->dev, 3569 "failed to get pfc storm para, ret = %d\n", ret); 3570 return ret; 3571 } 3572 3573 para->enable = le32_to_cpu(para_cmd->enable); 3574 para->period_ms = le32_to_cpu(para_cmd->period_ms); 3575 para->times = le32_to_cpu(para_cmd->times); 3576 para->recovery_period_ms = le32_to_cpu(para_cmd->recovery_period_ms); 3577 3578 return 0; 3579 } 3580 3581 static int hclge_enable_pfc_storm_prevent(struct hclge_dev *hdev, 3582 int dir, bool enable) 3583 { 3584 struct hnae3_pfc_storm_para para = {0}; 3585 int ret; 3586 3587 para.dir = dir; 3588 ret = hclge_get_pfc_storm_para(hdev, ¶); 3589 if (ret) 3590 return ret; 3591 3592 para.enable = enable; 3593 return hclge_set_pfc_storm_para(hdev, ¶); 3594 } 3595 3596 static int hclge_set_pfc_prevention_tout(struct hnae3_handle *h, u16 times) 3597 { 3598 struct hclge_vport *vport = hclge_get_vport(h); 3599 struct hclge_dev *hdev = vport->back; 3600 struct hnae3_pfc_storm_para para; 3601 int ret; 3602 3603 if (times > HCLGE_MAX_PFC_PREVENTION_TOUT) { 3604 dev_err(&hdev->pdev->dev, 3605 "times %u should be no more than %u!\n", 3606 times, HCLGE_MAX_PFC_PREVENTION_TOUT); 3607 return -EINVAL; 3608 } 3609 3610 para.dir = HCLGE_DIR_TX; 3611 ret = hclge_get_pfc_storm_para(hdev, ¶); 3612 if (ret) 3613 return ret; 3614 3615 para.enable = times ? 1 : 0; 3616 para.times = (u32)times; 3617 ret = hclge_set_pfc_storm_para(hdev, ¶); 3618 if (ret) 3619 return ret; 3620 3621 hdev->pfc_prevention_tout = times; 3622 3623 return 0; 3624 } 3625 3626 static int hclge_get_pfc_prevention_tout(struct hnae3_handle *h, u16 *times) 3627 { 3628 struct hclge_vport *vport = hclge_get_vport(h); 3629 struct hclge_dev *hdev = vport->back; 3630 struct hnae3_pfc_storm_para para; 3631 int ret; 3632 3633 para.dir = HCLGE_DIR_TX; 3634 ret = hclge_get_pfc_storm_para(hdev, ¶); 3635 if (ret) 3636 return ret; 3637 3638 *times = para.enable ? (u16)para.times : 0; 3639 3640 return 0; 3641 } 3642 3643 static void hclge_set_reset_pending(struct hclge_dev *hdev, 3644 enum hnae3_reset_type reset_type) 3645 { 3646 /* When an incorrect reset type is executed, the get_reset_level 3647 * function generates the HNAE3_NONE_RESET flag. As a result, this 3648 * type do not need to pending. 3649 */ 3650 if (reset_type != HNAE3_NONE_RESET) 3651 set_bit(reset_type, &hdev->reset_pending); 3652 } 3653 3654 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 3655 { 3656 u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg; 3657 3658 /* fetch the events from their corresponding regs */ 3659 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); 3660 msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 3661 hw_err_src_reg = hclge_read_dev(&hdev->hw, 3662 HCLGE_RAS_PF_OTHER_INT_STS_REG); 3663 3664 /* Assumption: If by any chance reset and mailbox events are reported 3665 * together then we will only process reset event in this go and will 3666 * defer the processing of the mailbox events. Since, we would have not 3667 * cleared RX CMDQ event this time we would receive again another 3668 * interrupt from H/W just for the mailbox. 3669 * 3670 * check for vector0 reset event sources 3671 */ 3672 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) { 3673 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n"); 3674 hclge_set_reset_pending(hdev, HNAE3_IMP_RESET); 3675 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3676 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 3677 hdev->rst_stats.imp_rst_cnt++; 3678 return HCLGE_VECTOR0_EVENT_RST; 3679 } 3680 3681 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) { 3682 dev_info(&hdev->pdev->dev, "global reset interrupt\n"); 3683 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 3684 hclge_set_reset_pending(hdev, HNAE3_GLOBAL_RESET); 3685 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 3686 hdev->rst_stats.global_rst_cnt++; 3687 return HCLGE_VECTOR0_EVENT_RST; 3688 } 3689 3690 /* check for vector0 msix event and hardware error event source */ 3691 if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK || 3692 hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK) 3693 return HCLGE_VECTOR0_EVENT_ERR; 3694 3695 /* check for vector0 ptp event source */ 3696 if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) { 3697 *clearval = msix_src_reg; 3698 return HCLGE_VECTOR0_EVENT_PTP; 3699 } 3700 3701 /* check for vector0 mailbox(=CMDQ RX) event source */ 3702 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { 3703 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); 3704 *clearval = cmdq_src_reg; 3705 return HCLGE_VECTOR0_EVENT_MBX; 3706 } 3707 3708 /* print other vector0 event source */ 3709 dev_info(&hdev->pdev->dev, 3710 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n", 3711 cmdq_src_reg, hw_err_src_reg, msix_src_reg); 3712 3713 return HCLGE_VECTOR0_EVENT_OTHER; 3714 } 3715 3716 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, 3717 u32 regclr) 3718 { 3719 #define HCLGE_IMP_RESET_DELAY 5 3720 3721 switch (event_type) { 3722 case HCLGE_VECTOR0_EVENT_PTP: 3723 case HCLGE_VECTOR0_EVENT_RST: 3724 if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) 3725 mdelay(HCLGE_IMP_RESET_DELAY); 3726 3727 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); 3728 break; 3729 case HCLGE_VECTOR0_EVENT_MBX: 3730 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); 3731 break; 3732 default: 3733 break; 3734 } 3735 } 3736 3737 static void hclge_clear_all_event_cause(struct hclge_dev *hdev) 3738 { 3739 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, 3740 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | 3741 BIT(HCLGE_VECTOR0_CORERESET_INT_B) | 3742 BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); 3743 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); 3744 } 3745 3746 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) 3747 { 3748 writel(enable ? 1 : 0, vector->addr); 3749 } 3750 3751 static irqreturn_t hclge_misc_irq_handle(int irq, void *data) 3752 { 3753 struct hclge_dev *hdev = data; 3754 unsigned long flags; 3755 u32 clearval = 0; 3756 u32 event_cause; 3757 3758 hclge_enable_vector(&hdev->misc_vector, false); 3759 event_cause = hclge_check_event_cause(hdev, &clearval); 3760 3761 /* vector 0 interrupt is shared with reset and mailbox source events. */ 3762 switch (event_cause) { 3763 case HCLGE_VECTOR0_EVENT_ERR: 3764 hclge_errhand_task_schedule(hdev); 3765 break; 3766 case HCLGE_VECTOR0_EVENT_RST: 3767 hclge_reset_task_schedule(hdev); 3768 break; 3769 case HCLGE_VECTOR0_EVENT_PTP: 3770 spin_lock_irqsave(&hdev->ptp->lock, flags); 3771 hclge_ptp_clean_tx_hwts(hdev); 3772 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 3773 break; 3774 case HCLGE_VECTOR0_EVENT_MBX: 3775 /* If we are here then, 3776 * 1. Either we are not handling any mbx task and we are not 3777 * scheduled as well 3778 * OR 3779 * 2. We could be handling a mbx task but nothing more is 3780 * scheduled. 3781 * In both cases, we should schedule mbx task as there are more 3782 * mbx messages reported by this interrupt. 3783 */ 3784 hclge_mbx_task_schedule(hdev); 3785 break; 3786 default: 3787 dev_warn(&hdev->pdev->dev, 3788 "received unknown or unhandled event of vector0\n"); 3789 break; 3790 } 3791 3792 hclge_clear_event_cause(hdev, event_cause, clearval); 3793 3794 /* Enable interrupt if it is not caused by reset event or error event */ 3795 if (event_cause == HCLGE_VECTOR0_EVENT_PTP || 3796 event_cause == HCLGE_VECTOR0_EVENT_MBX || 3797 event_cause == HCLGE_VECTOR0_EVENT_OTHER) 3798 hclge_enable_vector(&hdev->misc_vector, true); 3799 3800 return IRQ_HANDLED; 3801 } 3802 3803 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) 3804 { 3805 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { 3806 dev_warn(&hdev->pdev->dev, 3807 "vector(vector_id %d) has been freed.\n", vector_id); 3808 return; 3809 } 3810 3811 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; 3812 hdev->num_msi_left += 1; 3813 hdev->num_msi_used -= 1; 3814 } 3815 3816 static void hclge_get_misc_vector(struct hclge_dev *hdev) 3817 { 3818 struct hclge_misc_vector *vector = &hdev->misc_vector; 3819 3820 vector->vector_irq = pci_irq_vector(hdev->pdev, 0); 3821 3822 vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; 3823 hdev->vector_status[0] = 0; 3824 3825 hdev->num_msi_left -= 1; 3826 hdev->num_msi_used += 1; 3827 } 3828 3829 static int hclge_misc_irq_init(struct hclge_dev *hdev) 3830 { 3831 int ret; 3832 3833 hclge_get_misc_vector(hdev); 3834 3835 /* this would be explicitly freed in the end */ 3836 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s", 3837 HCLGE_NAME, pci_name(hdev->pdev)); 3838 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, 3839 IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev); 3840 if (ret) { 3841 hclge_free_vector(hdev, 0); 3842 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", 3843 hdev->misc_vector.vector_irq); 3844 } 3845 3846 return ret; 3847 } 3848 3849 static void hclge_misc_irq_uninit(struct hclge_dev *hdev) 3850 { 3851 free_irq(hdev->misc_vector.vector_irq, hdev); 3852 hclge_free_vector(hdev, 0); 3853 } 3854 3855 int hclge_notify_client(struct hclge_dev *hdev, 3856 enum hnae3_reset_notify_type type) 3857 { 3858 struct hnae3_handle *handle = &hdev->vport[0].nic; 3859 struct hnae3_client *client = hdev->nic_client; 3860 int ret; 3861 3862 if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client) 3863 return 0; 3864 3865 if (!client->ops->reset_notify) 3866 return -EOPNOTSUPP; 3867 3868 ret = client->ops->reset_notify(handle, type); 3869 if (ret) 3870 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n", 3871 type, ret); 3872 3873 return ret; 3874 } 3875 3876 static int hclge_notify_roce_client(struct hclge_dev *hdev, 3877 enum hnae3_reset_notify_type type) 3878 { 3879 struct hnae3_handle *handle = &hdev->vport[0].roce; 3880 struct hnae3_client *client = hdev->roce_client; 3881 int ret; 3882 3883 if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client) 3884 return 0; 3885 3886 if (!client->ops->reset_notify) 3887 return -EOPNOTSUPP; 3888 3889 ret = client->ops->reset_notify(handle, type); 3890 if (ret) 3891 dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)", 3892 type, ret); 3893 3894 return ret; 3895 } 3896 3897 static int hclge_reset_wait(struct hclge_dev *hdev) 3898 { 3899 #define HCLGE_RESET_WATI_MS 100 3900 #define HCLGE_RESET_WAIT_CNT 350 3901 3902 u32 val, reg, reg_bit; 3903 u32 cnt = 0; 3904 3905 switch (hdev->reset_type) { 3906 case HNAE3_IMP_RESET: 3907 reg = HCLGE_GLOBAL_RESET_REG; 3908 reg_bit = HCLGE_IMP_RESET_BIT; 3909 break; 3910 case HNAE3_GLOBAL_RESET: 3911 reg = HCLGE_GLOBAL_RESET_REG; 3912 reg_bit = HCLGE_GLOBAL_RESET_BIT; 3913 break; 3914 case HNAE3_FUNC_RESET: 3915 reg = HCLGE_FUN_RST_ING; 3916 reg_bit = HCLGE_FUN_RST_ING_B; 3917 break; 3918 default: 3919 dev_err(&hdev->pdev->dev, 3920 "Wait for unsupported reset type: %d\n", 3921 hdev->reset_type); 3922 return -EINVAL; 3923 } 3924 3925 val = hclge_read_dev(&hdev->hw, reg); 3926 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { 3927 msleep(HCLGE_RESET_WATI_MS); 3928 val = hclge_read_dev(&hdev->hw, reg); 3929 cnt++; 3930 } 3931 3932 if (cnt >= HCLGE_RESET_WAIT_CNT) { 3933 dev_warn(&hdev->pdev->dev, 3934 "Wait for reset timeout: %d\n", hdev->reset_type); 3935 return -EBUSY; 3936 } 3937 3938 return 0; 3939 } 3940 3941 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset) 3942 { 3943 struct hclge_vf_rst_cmd *req; 3944 struct hclge_desc desc; 3945 3946 req = (struct hclge_vf_rst_cmd *)desc.data; 3947 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false); 3948 req->dest_vfid = func_id; 3949 3950 if (reset) 3951 req->vf_rst = 0x1; 3952 3953 return hclge_cmd_send(&hdev->hw, &desc, 1); 3954 } 3955 3956 static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset) 3957 { 3958 int i; 3959 3960 for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) { 3961 struct hclge_vport *vport = &hdev->vport[i]; 3962 int ret; 3963 3964 /* Send cmd to set/clear VF's FUNC_RST_ING */ 3965 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset); 3966 if (ret) { 3967 dev_err(&hdev->pdev->dev, 3968 "set vf(%u) rst failed %d!\n", 3969 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3970 ret); 3971 return ret; 3972 } 3973 3974 if (!reset || 3975 !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state)) 3976 continue; 3977 3978 if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) && 3979 hdev->reset_type == HNAE3_FUNC_RESET) { 3980 set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, 3981 &vport->need_notify); 3982 continue; 3983 } 3984 3985 /* Inform VF to process the reset. 3986 * hclge_inform_reset_assert_to_vf may fail if VF 3987 * driver is not loaded. 3988 */ 3989 ret = hclge_inform_reset_assert_to_vf(vport); 3990 if (ret) 3991 dev_warn(&hdev->pdev->dev, 3992 "inform reset to vf(%u) failed %d!\n", 3993 vport->vport_id - HCLGE_VF_VPORT_START_NUM, 3994 ret); 3995 } 3996 3997 return 0; 3998 } 3999 4000 static void hclge_mailbox_service_task(struct hclge_dev *hdev) 4001 { 4002 if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) || 4003 test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) || 4004 test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) 4005 return; 4006 4007 if (time_is_before_jiffies(hdev->last_mbx_scheduled + 4008 HCLGE_MBX_SCHED_TIMEOUT)) 4009 dev_warn(&hdev->pdev->dev, 4010 "mbx service task is scheduled after %ums on cpu%u!\n", 4011 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled), 4012 smp_processor_id()); 4013 4014 hclge_mbx_handler(hdev); 4015 4016 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 4017 } 4018 4019 static void hclge_func_reset_sync_vf(struct hclge_dev *hdev) 4020 { 4021 struct hclge_pf_rst_sync_cmd *req; 4022 struct hclge_desc desc; 4023 int cnt = 0; 4024 int ret; 4025 4026 req = (struct hclge_pf_rst_sync_cmd *)desc.data; 4027 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_VF_RST_RDY, true); 4028 4029 do { 4030 /* vf need to down netdev by mbx during PF or FLR reset */ 4031 hclge_mailbox_service_task(hdev); 4032 4033 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4034 /* for compatible with old firmware, wait 4035 * 100 ms for VF to stop IO 4036 */ 4037 if (ret == -EOPNOTSUPP) { 4038 msleep(HCLGE_RESET_SYNC_TIME); 4039 return; 4040 } else if (ret) { 4041 dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n", 4042 ret); 4043 return; 4044 } else if (req->all_vf_ready) { 4045 return; 4046 } 4047 msleep(HCLGE_PF_RESET_SYNC_TIME); 4048 hclge_comm_cmd_reuse_desc(&desc, true); 4049 } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT); 4050 4051 dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n"); 4052 } 4053 4054 void hclge_report_hw_error(struct hclge_dev *hdev, 4055 enum hnae3_hw_error_type type) 4056 { 4057 struct hnae3_client *client = hdev->nic_client; 4058 4059 if (!client || !client->ops->process_hw_error || 4060 !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state)) 4061 return; 4062 4063 client->ops->process_hw_error(&hdev->vport[0].nic, type); 4064 } 4065 4066 static void hclge_handle_imp_error(struct hclge_dev *hdev) 4067 { 4068 u32 reg_val; 4069 4070 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4071 if (reg_val & BIT(HCLGE_VECTOR0_IMP_RD_POISON_B)) { 4072 hclge_report_hw_error(hdev, HNAE3_IMP_RD_POISON_ERROR); 4073 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_RD_POISON_B); 4074 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4075 } 4076 4077 if (reg_val & BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)) { 4078 hclge_report_hw_error(hdev, HNAE3_CMDQ_ECC_ERROR); 4079 reg_val &= ~BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B); 4080 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val); 4081 } 4082 } 4083 4084 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) 4085 { 4086 struct hclge_desc desc; 4087 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; 4088 int ret; 4089 4090 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 4091 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); 4092 req->fun_reset_vfid = func_id; 4093 4094 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4095 if (ret) 4096 dev_err(&hdev->pdev->dev, 4097 "send function reset cmd fail, status =%d\n", ret); 4098 4099 return ret; 4100 } 4101 4102 static void hclge_do_reset(struct hclge_dev *hdev) 4103 { 4104 struct hnae3_handle *handle = &hdev->vport[0].nic; 4105 struct pci_dev *pdev = hdev->pdev; 4106 u32 val; 4107 4108 if (hclge_get_hw_reset_stat(handle)) { 4109 dev_info(&pdev->dev, "hardware reset not finish\n"); 4110 dev_info(&pdev->dev, "func_rst_reg:0x%x, global_rst_reg:0x%x\n", 4111 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING), 4112 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 4113 return; 4114 } 4115 4116 switch (hdev->reset_type) { 4117 case HNAE3_IMP_RESET: 4118 dev_info(&pdev->dev, "IMP reset requested\n"); 4119 val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4120 hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1); 4121 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val); 4122 break; 4123 case HNAE3_GLOBAL_RESET: 4124 dev_info(&pdev->dev, "global reset requested\n"); 4125 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); 4126 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); 4127 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); 4128 break; 4129 case HNAE3_FUNC_RESET: 4130 dev_info(&pdev->dev, "PF reset requested\n"); 4131 /* schedule again to check later */ 4132 hclge_set_reset_pending(hdev, HNAE3_FUNC_RESET); 4133 hclge_reset_task_schedule(hdev); 4134 break; 4135 default: 4136 dev_warn(&pdev->dev, 4137 "unsupported reset type: %d\n", hdev->reset_type); 4138 break; 4139 } 4140 } 4141 4142 static enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev, 4143 unsigned long *addr) 4144 { 4145 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; 4146 struct hclge_dev *hdev = ae_dev->priv; 4147 4148 /* return the highest priority reset level amongst all */ 4149 if (test_bit(HNAE3_IMP_RESET, addr)) { 4150 rst_level = HNAE3_IMP_RESET; 4151 clear_bit(HNAE3_IMP_RESET, addr); 4152 clear_bit(HNAE3_GLOBAL_RESET, addr); 4153 clear_bit(HNAE3_FUNC_RESET, addr); 4154 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) { 4155 rst_level = HNAE3_GLOBAL_RESET; 4156 clear_bit(HNAE3_GLOBAL_RESET, addr); 4157 clear_bit(HNAE3_FUNC_RESET, addr); 4158 } else if (test_bit(HNAE3_FUNC_RESET, addr)) { 4159 rst_level = HNAE3_FUNC_RESET; 4160 clear_bit(HNAE3_FUNC_RESET, addr); 4161 } else if (test_bit(HNAE3_FLR_RESET, addr)) { 4162 rst_level = HNAE3_FLR_RESET; 4163 clear_bit(HNAE3_FLR_RESET, addr); 4164 } 4165 4166 clear_bit(HNAE3_NONE_RESET, addr); 4167 4168 if (hdev->reset_type != HNAE3_NONE_RESET && 4169 rst_level < hdev->reset_type) 4170 return HNAE3_NONE_RESET; 4171 4172 return rst_level; 4173 } 4174 4175 static void hclge_clear_reset_cause(struct hclge_dev *hdev) 4176 { 4177 u32 clearval = 0; 4178 4179 switch (hdev->reset_type) { 4180 case HNAE3_IMP_RESET: 4181 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); 4182 break; 4183 case HNAE3_GLOBAL_RESET: 4184 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); 4185 break; 4186 default: 4187 break; 4188 } 4189 4190 if (!clearval) 4191 return; 4192 4193 /* For revision 0x20, the reset interrupt source 4194 * can only be cleared after hardware reset done 4195 */ 4196 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 4197 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, 4198 clearval); 4199 4200 hclge_enable_vector(&hdev->misc_vector, true); 4201 } 4202 4203 static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable) 4204 { 4205 u32 reg_val; 4206 4207 reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG); 4208 if (enable) 4209 reg_val |= HCLGE_COMM_NIC_SW_RST_RDY; 4210 else 4211 reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY; 4212 4213 hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val); 4214 } 4215 4216 static int hclge_func_reset_notify_vf(struct hclge_dev *hdev) 4217 { 4218 int ret; 4219 4220 ret = hclge_set_all_vf_rst(hdev, true); 4221 if (ret) 4222 return ret; 4223 4224 hclge_func_reset_sync_vf(hdev); 4225 4226 return 0; 4227 } 4228 4229 static int hclge_reset_prepare_wait(struct hclge_dev *hdev) 4230 { 4231 u32 reg_val; 4232 int ret = 0; 4233 4234 switch (hdev->reset_type) { 4235 case HNAE3_FUNC_RESET: 4236 ret = hclge_func_reset_notify_vf(hdev); 4237 if (ret) 4238 return ret; 4239 4240 ret = hclge_func_reset_cmd(hdev, 0); 4241 if (ret) { 4242 dev_err(&hdev->pdev->dev, 4243 "asserting function reset fail %d!\n", ret); 4244 return ret; 4245 } 4246 4247 /* After performaning pf reset, it is not necessary to do the 4248 * mailbox handling or send any command to firmware, because 4249 * any mailbox handling or command to firmware is only valid 4250 * after hclge_comm_cmd_init is called. 4251 */ 4252 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 4253 hdev->rst_stats.pf_rst_cnt++; 4254 break; 4255 case HNAE3_FLR_RESET: 4256 ret = hclge_func_reset_notify_vf(hdev); 4257 if (ret) 4258 return ret; 4259 break; 4260 case HNAE3_IMP_RESET: 4261 hclge_handle_imp_error(hdev); 4262 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG); 4263 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, 4264 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val); 4265 break; 4266 default: 4267 break; 4268 } 4269 4270 /* inform hardware that preparatory work is done */ 4271 msleep(HCLGE_RESET_SYNC_TIME); 4272 hclge_reset_handshake(hdev, true); 4273 dev_info(&hdev->pdev->dev, "prepare wait ok\n"); 4274 4275 return ret; 4276 } 4277 4278 static void hclge_show_rst_info(struct hclge_dev *hdev) 4279 { 4280 char *buf; 4281 4282 buf = kzalloc(HCLGE_DBG_RESET_INFO_LEN, GFP_KERNEL); 4283 if (!buf) 4284 return; 4285 4286 hclge_dbg_dump_rst_info(hdev, buf, HCLGE_DBG_RESET_INFO_LEN); 4287 4288 dev_info(&hdev->pdev->dev, "dump reset info:\n%s", buf); 4289 4290 kfree(buf); 4291 } 4292 4293 static bool hclge_reset_err_handle(struct hclge_dev *hdev) 4294 { 4295 #define MAX_RESET_FAIL_CNT 5 4296 4297 if (hdev->reset_pending) { 4298 dev_info(&hdev->pdev->dev, "Reset pending %lu\n", 4299 hdev->reset_pending); 4300 return true; 4301 } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) & 4302 HCLGE_RESET_INT_M) { 4303 dev_info(&hdev->pdev->dev, 4304 "reset failed because new reset interrupt\n"); 4305 hclge_clear_reset_cause(hdev); 4306 return false; 4307 } else if (hdev->rst_stats.reset_fail_cnt < MAX_RESET_FAIL_CNT) { 4308 hdev->rst_stats.reset_fail_cnt++; 4309 hclge_set_reset_pending(hdev, hdev->reset_type); 4310 dev_info(&hdev->pdev->dev, 4311 "re-schedule reset task(%u)\n", 4312 hdev->rst_stats.reset_fail_cnt); 4313 return true; 4314 } 4315 4316 hclge_clear_reset_cause(hdev); 4317 4318 /* recover the handshake status when reset fail */ 4319 hclge_reset_handshake(hdev, true); 4320 4321 dev_err(&hdev->pdev->dev, "Reset fail!\n"); 4322 4323 hclge_show_rst_info(hdev); 4324 4325 set_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4326 4327 return false; 4328 } 4329 4330 static void hclge_update_reset_level(struct hclge_dev *hdev) 4331 { 4332 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4333 enum hnae3_reset_type reset_level; 4334 4335 /* reset request will not be set during reset, so clear 4336 * pending reset request to avoid unnecessary reset 4337 * caused by the same reason. 4338 */ 4339 hclge_get_reset_level(ae_dev, &hdev->reset_request); 4340 4341 /* if default_reset_request has a higher level reset request, 4342 * it should be handled as soon as possible. since some errors 4343 * need this kind of reset to fix. 4344 */ 4345 reset_level = hclge_get_reset_level(ae_dev, 4346 &hdev->default_reset_request); 4347 if (reset_level != HNAE3_NONE_RESET) 4348 set_bit(reset_level, &hdev->reset_request); 4349 } 4350 4351 static int hclge_set_rst_done(struct hclge_dev *hdev) 4352 { 4353 struct hclge_pf_rst_done_cmd *req; 4354 struct hclge_desc desc; 4355 int ret; 4356 4357 req = (struct hclge_pf_rst_done_cmd *)desc.data; 4358 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PF_RST_DONE, false); 4359 req->pf_rst_done |= HCLGE_PF_RESET_DONE_BIT; 4360 4361 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 4362 /* To be compatible with the old firmware, which does not support 4363 * command HCLGE_OPC_PF_RST_DONE, just print a warning and 4364 * return success 4365 */ 4366 if (ret == -EOPNOTSUPP) { 4367 dev_warn(&hdev->pdev->dev, 4368 "current firmware does not support command(0x%x)!\n", 4369 HCLGE_OPC_PF_RST_DONE); 4370 return 0; 4371 } else if (ret) { 4372 dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n", 4373 ret); 4374 } 4375 4376 return ret; 4377 } 4378 4379 static int hclge_reset_prepare_up(struct hclge_dev *hdev) 4380 { 4381 int ret = 0; 4382 4383 switch (hdev->reset_type) { 4384 case HNAE3_FUNC_RESET: 4385 case HNAE3_FLR_RESET: 4386 ret = hclge_set_all_vf_rst(hdev, false); 4387 break; 4388 case HNAE3_GLOBAL_RESET: 4389 case HNAE3_IMP_RESET: 4390 ret = hclge_set_rst_done(hdev); 4391 break; 4392 default: 4393 break; 4394 } 4395 4396 /* clear up the handshake status after re-initialize done */ 4397 hclge_reset_handshake(hdev, false); 4398 4399 return ret; 4400 } 4401 4402 static int hclge_reset_stack(struct hclge_dev *hdev) 4403 { 4404 int ret; 4405 4406 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); 4407 if (ret) 4408 return ret; 4409 4410 ret = hclge_reset_ae_dev(hdev->ae_dev); 4411 if (ret) 4412 return ret; 4413 4414 return hclge_notify_client(hdev, HNAE3_INIT_CLIENT); 4415 } 4416 4417 static int hclge_reset_prepare(struct hclge_dev *hdev) 4418 { 4419 int ret; 4420 4421 hdev->rst_stats.reset_cnt++; 4422 /* perform reset of the stack & ae device for a client */ 4423 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT); 4424 if (ret) 4425 return ret; 4426 4427 rtnl_lock(); 4428 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 4429 rtnl_unlock(); 4430 if (ret) 4431 return ret; 4432 4433 return hclge_reset_prepare_wait(hdev); 4434 } 4435 4436 static void hclge_restore_pfc_storm_prevention_tout(struct hclge_dev *hdev) 4437 { 4438 struct hnae3_handle *handle = &hdev->vport[0].nic; 4439 int ret; 4440 4441 ret = hclge_enable_pfc_storm_prevent(hdev, HCLGE_DIR_RX, false); 4442 if (ret == -EOPNOTSUPP) 4443 return; 4444 else if (ret) 4445 dev_warn(&hdev->pdev->dev, 4446 "failed to disable rx pfc storm prevent, ret = %d\n", 4447 ret); 4448 4449 ret = hclge_set_pfc_prevention_tout(handle, hdev->pfc_prevention_tout); 4450 if (ret) 4451 dev_warn(&hdev->pdev->dev, 4452 "failed to set tx pfc storm prevent, ret = %d\n", 4453 ret); 4454 } 4455 4456 static int hclge_reset_rebuild(struct hclge_dev *hdev) 4457 { 4458 int ret; 4459 4460 hdev->rst_stats.hw_reset_done_cnt++; 4461 4462 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT); 4463 if (ret) 4464 return ret; 4465 4466 rtnl_lock(); 4467 ret = hclge_reset_stack(hdev); 4468 rtnl_unlock(); 4469 if (ret) 4470 return ret; 4471 4472 hclge_clear_reset_cause(hdev); 4473 4474 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT); 4475 /* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1 4476 * times 4477 */ 4478 if (ret && 4479 hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1) 4480 return ret; 4481 4482 ret = hclge_reset_prepare_up(hdev); 4483 if (ret) 4484 return ret; 4485 4486 rtnl_lock(); 4487 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT); 4488 rtnl_unlock(); 4489 if (ret) 4490 return ret; 4491 4492 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT); 4493 if (ret) 4494 return ret; 4495 4496 hdev->last_reset_time = jiffies; 4497 hdev->rst_stats.reset_fail_cnt = 0; 4498 hdev->rst_stats.reset_done_cnt++; 4499 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 4500 4501 hclge_update_reset_level(hdev); 4502 4503 return 0; 4504 } 4505 4506 static void hclge_reset(struct hclge_dev *hdev) 4507 { 4508 if (hclge_reset_prepare(hdev)) 4509 goto err_reset; 4510 4511 if (hclge_reset_wait(hdev)) 4512 goto err_reset; 4513 4514 if (hclge_reset_rebuild(hdev)) 4515 goto err_reset; 4516 4517 return; 4518 4519 err_reset: 4520 if (hclge_reset_err_handle(hdev)) 4521 hclge_reset_task_schedule(hdev); 4522 } 4523 4524 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle) 4525 { 4526 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev); 4527 struct hclge_dev *hdev = ae_dev->priv; 4528 4529 /* We might end up getting called broadly because of 2 below cases: 4530 * 1. Recoverable error was conveyed through APEI and only way to bring 4531 * normalcy is to reset. 4532 * 2. A new reset request from the stack due to timeout 4533 * 4534 * check if this is a new reset request and we are not here just because 4535 * last reset attempt did not succeed and watchdog hit us again. We will 4536 * know this if last reset request did not occur very recently (watchdog 4537 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) 4538 * In case of new request we reset the "reset level" to PF reset. 4539 * And if it is a repeat reset request of the most recent one then we 4540 * want to make sure we throttle the reset request. Therefore, we will 4541 * not allow it again before 3*HZ times. 4542 */ 4543 4544 if (time_before(jiffies, (hdev->last_reset_time + 4545 HCLGE_RESET_INTERVAL))) { 4546 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 4547 return; 4548 } 4549 4550 if (hdev->default_reset_request) { 4551 hdev->reset_level = 4552 hclge_get_reset_level(ae_dev, 4553 &hdev->default_reset_request); 4554 } else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ))) { 4555 hdev->reset_level = HNAE3_FUNC_RESET; 4556 } 4557 4558 dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n", 4559 hdev->reset_level); 4560 4561 /* request reset & schedule reset task */ 4562 set_bit(hdev->reset_level, &hdev->reset_request); 4563 hclge_reset_task_schedule(hdev); 4564 4565 if (hdev->reset_level < HNAE3_GLOBAL_RESET) 4566 hdev->reset_level++; 4567 } 4568 4569 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev, 4570 enum hnae3_reset_type rst_type) 4571 { 4572 #define HCLGE_SUPPORT_RESET_TYPE \ 4573 (BIT(HNAE3_FLR_RESET) | BIT(HNAE3_FUNC_RESET) | \ 4574 BIT(HNAE3_GLOBAL_RESET) | BIT(HNAE3_IMP_RESET)) 4575 4576 struct hclge_dev *hdev = ae_dev->priv; 4577 4578 if (!(BIT(rst_type) & HCLGE_SUPPORT_RESET_TYPE)) { 4579 /* To prevent reset triggered by hclge_reset_event */ 4580 set_bit(HNAE3_NONE_RESET, &hdev->default_reset_request); 4581 dev_warn(&hdev->pdev->dev, "unsupported reset type %d\n", 4582 rst_type); 4583 return; 4584 } 4585 4586 set_bit(rst_type, &hdev->default_reset_request); 4587 } 4588 4589 static void hclge_reset_timer(struct timer_list *t) 4590 { 4591 struct hclge_dev *hdev = timer_container_of(hdev, t, reset_timer); 4592 4593 /* if default_reset_request has no value, it means that this reset 4594 * request has already be handled, so just return here 4595 */ 4596 if (!hdev->default_reset_request) 4597 return; 4598 4599 dev_info(&hdev->pdev->dev, 4600 "triggering reset in reset timer\n"); 4601 hclge_reset_event(hdev->pdev, NULL); 4602 } 4603 4604 static void hclge_reset_subtask(struct hclge_dev *hdev) 4605 { 4606 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4607 4608 /* check if there is any ongoing reset in the hardware. This status can 4609 * be checked from reset_pending. If there is then, we need to wait for 4610 * hardware to complete reset. 4611 * a. If we are able to figure out in reasonable time that hardware 4612 * has fully resetted then, we can proceed with driver, client 4613 * reset. 4614 * b. else, we can come back later to check this status so re-sched 4615 * now. 4616 */ 4617 hdev->last_reset_time = jiffies; 4618 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending); 4619 if (hdev->reset_type != HNAE3_NONE_RESET) 4620 hclge_reset(hdev); 4621 4622 /* check if we got any *new* reset requests to be honored */ 4623 hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request); 4624 if (hdev->reset_type != HNAE3_NONE_RESET) 4625 hclge_do_reset(hdev); 4626 4627 hdev->reset_type = HNAE3_NONE_RESET; 4628 } 4629 4630 static void hclge_handle_err_reset_request(struct hclge_dev *hdev) 4631 { 4632 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4633 enum hnae3_reset_type reset_type; 4634 4635 if (ae_dev->hw_err_reset_req) { 4636 reset_type = hclge_get_reset_level(ae_dev, 4637 &ae_dev->hw_err_reset_req); 4638 hclge_set_def_reset_request(ae_dev, reset_type); 4639 } 4640 4641 if (hdev->default_reset_request && ae_dev->ops->reset_event) 4642 ae_dev->ops->reset_event(hdev->pdev, NULL); 4643 4644 /* enable interrupt after error handling complete */ 4645 hclge_enable_vector(&hdev->misc_vector, true); 4646 } 4647 4648 static void hclge_handle_err_recovery(struct hclge_dev *hdev) 4649 { 4650 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4651 4652 ae_dev->hw_err_reset_req = 0; 4653 4654 if (hclge_find_error_source(hdev)) { 4655 hclge_handle_error_info_log(ae_dev); 4656 hclge_handle_mac_tnl(hdev); 4657 hclge_handle_vf_queue_err_ras(hdev); 4658 } 4659 4660 hclge_handle_err_reset_request(hdev); 4661 } 4662 4663 static void hclge_misc_err_recovery(struct hclge_dev *hdev) 4664 { 4665 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev); 4666 struct device *dev = &hdev->pdev->dev; 4667 u32 msix_sts_reg; 4668 4669 msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS); 4670 if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) { 4671 if (hclge_handle_hw_msix_error 4672 (hdev, &hdev->default_reset_request)) 4673 dev_info(dev, "received msix interrupt 0x%x\n", 4674 msix_sts_reg); 4675 } 4676 4677 hclge_handle_hw_ras_error(ae_dev); 4678 4679 hclge_handle_err_reset_request(hdev); 4680 } 4681 4682 static void hclge_errhand_service_task(struct hclge_dev *hdev) 4683 { 4684 if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state)) 4685 return; 4686 4687 if (hnae3_dev_ras_imp_supported(hdev)) 4688 hclge_handle_err_recovery(hdev); 4689 else 4690 hclge_misc_err_recovery(hdev); 4691 } 4692 4693 static void hclge_reset_service_task(struct hclge_dev *hdev) 4694 { 4695 if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) 4696 return; 4697 4698 if (time_is_before_jiffies(hdev->last_rst_scheduled + 4699 HCLGE_RESET_SCHED_TIMEOUT)) 4700 dev_warn(&hdev->pdev->dev, 4701 "reset service task is scheduled after %ums on cpu%u!\n", 4702 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled), 4703 smp_processor_id()); 4704 4705 down(&hdev->reset_sem); 4706 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4707 4708 hclge_reset_subtask(hdev); 4709 4710 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 4711 up(&hdev->reset_sem); 4712 } 4713 4714 static void hclge_update_vport_alive(struct hclge_dev *hdev) 4715 { 4716 #define HCLGE_ALIVE_SECONDS_NORMAL 8 4717 4718 unsigned long alive_time = HCLGE_ALIVE_SECONDS_NORMAL * HZ; 4719 int i; 4720 4721 /* start from vport 1 for PF is always alive */ 4722 for (i = 1; i < hdev->num_alloc_vport; i++) { 4723 struct hclge_vport *vport = &hdev->vport[i]; 4724 4725 if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) || 4726 !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 4727 continue; 4728 if (time_after(jiffies, vport->last_active_jiffies + 4729 alive_time)) { 4730 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 4731 dev_warn(&hdev->pdev->dev, 4732 "VF %u heartbeat timeout\n", 4733 i - HCLGE_VF_VPORT_START_NUM); 4734 } 4735 } 4736 } 4737 4738 static void hclge_periodic_service_task(struct hclge_dev *hdev) 4739 { 4740 unsigned long delta = round_jiffies_relative(HZ); 4741 4742 if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) 4743 return; 4744 4745 /* Always handle the link updating to make sure link state is 4746 * updated when it is triggered by mbx. 4747 */ 4748 hclge_update_link_status(hdev); 4749 hclge_sync_mac_table(hdev); 4750 hclge_sync_promisc_mode(hdev); 4751 hclge_sync_fd_table(hdev); 4752 4753 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) { 4754 delta = jiffies - hdev->last_serv_processed; 4755 4756 if (delta < round_jiffies_relative(HZ)) { 4757 delta = round_jiffies_relative(HZ) - delta; 4758 goto out; 4759 } 4760 } 4761 4762 hdev->serv_processed_cnt++; 4763 hclge_update_vport_alive(hdev); 4764 4765 if (test_bit(HCLGE_STATE_DOWN, &hdev->state)) { 4766 hdev->last_serv_processed = jiffies; 4767 goto out; 4768 } 4769 4770 if (!(hdev->serv_processed_cnt % HCLGE_STATS_TIMER_INTERVAL)) 4771 hclge_update_stats_for_all(hdev); 4772 4773 hclge_update_port_info(hdev); 4774 hclge_sync_vlan_filter(hdev); 4775 4776 if (!(hdev->serv_processed_cnt % HCLGE_ARFS_EXPIRE_INTERVAL)) 4777 hclge_rfs_filter_expire(hdev); 4778 4779 hdev->last_serv_processed = jiffies; 4780 4781 out: 4782 hclge_task_schedule(hdev, delta); 4783 } 4784 4785 static void hclge_ptp_service_task(struct hclge_dev *hdev) 4786 { 4787 unsigned long flags; 4788 4789 if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) || 4790 !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) || 4791 !time_is_before_jiffies(hdev->ptp->tx_start + HZ)) 4792 return; 4793 4794 /* to prevent concurrence with the irq handler */ 4795 spin_lock_irqsave(&hdev->ptp->lock, flags); 4796 4797 /* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq 4798 * handler may handle it just before spin_lock_irqsave(). 4799 */ 4800 if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) 4801 hclge_ptp_clean_tx_hwts(hdev); 4802 4803 spin_unlock_irqrestore(&hdev->ptp->lock, flags); 4804 } 4805 4806 static void hclge_service_task(struct work_struct *work) 4807 { 4808 struct hclge_dev *hdev = 4809 container_of(work, struct hclge_dev, service_task.work); 4810 4811 hclge_errhand_service_task(hdev); 4812 hclge_reset_service_task(hdev); 4813 hclge_ptp_service_task(hdev); 4814 hclge_mailbox_service_task(hdev); 4815 hclge_periodic_service_task(hdev); 4816 4817 /* Handle error recovery, reset and mbx again in case periodical task 4818 * delays the handling by calling hclge_task_schedule() in 4819 * hclge_periodic_service_task(). 4820 */ 4821 hclge_errhand_service_task(hdev); 4822 hclge_reset_service_task(hdev); 4823 hclge_mailbox_service_task(hdev); 4824 } 4825 4826 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) 4827 { 4828 /* VF handle has no client */ 4829 if (!handle->client) 4830 return container_of(handle, struct hclge_vport, nic); 4831 else if (handle->client->type == HNAE3_CLIENT_ROCE) 4832 return container_of(handle, struct hclge_vport, roce); 4833 else 4834 return container_of(handle, struct hclge_vport, nic); 4835 } 4836 4837 static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx, 4838 struct hnae3_vector_info *vector_info) 4839 { 4840 #define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 64 4841 4842 vector_info->vector = pci_irq_vector(hdev->pdev, idx); 4843 4844 /* need an extend offset to config vector >= 64 */ 4845 if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2) 4846 vector_info->io_addr = hdev->hw.hw.io_base + 4847 HCLGE_VECTOR_REG_BASE + 4848 (idx - 1) * HCLGE_VECTOR_REG_OFFSET; 4849 else 4850 vector_info->io_addr = hdev->hw.hw.io_base + 4851 HCLGE_VECTOR_EXT_REG_BASE + 4852 (idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4853 HCLGE_VECTOR_REG_OFFSET_H + 4854 (idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 * 4855 HCLGE_VECTOR_REG_OFFSET; 4856 4857 hdev->vector_status[idx] = hdev->vport[0].vport_id; 4858 hdev->vector_irq[idx] = vector_info->vector; 4859 } 4860 4861 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, 4862 struct hnae3_vector_info *vector_info) 4863 { 4864 struct hclge_vport *vport = hclge_get_vport(handle); 4865 struct hnae3_vector_info *vector = vector_info; 4866 struct hclge_dev *hdev = vport->back; 4867 int alloc = 0; 4868 u16 i = 0; 4869 u16 j; 4870 4871 vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num); 4872 vector_num = min(hdev->num_msi_left, vector_num); 4873 4874 for (j = 0; j < vector_num; j++) { 4875 while (++i < hdev->num_nic_msi) { 4876 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { 4877 hclge_get_vector_info(hdev, i, vector); 4878 vector++; 4879 alloc++; 4880 4881 break; 4882 } 4883 } 4884 } 4885 hdev->num_msi_left -= alloc; 4886 hdev->num_msi_used += alloc; 4887 4888 return alloc; 4889 } 4890 4891 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) 4892 { 4893 int i; 4894 4895 for (i = 0; i < hdev->num_msi; i++) 4896 if (vector == hdev->vector_irq[i]) 4897 return i; 4898 4899 return -EINVAL; 4900 } 4901 4902 static int hclge_put_vector(struct hnae3_handle *handle, int vector) 4903 { 4904 struct hclge_vport *vport = hclge_get_vport(handle); 4905 struct hclge_dev *hdev = vport->back; 4906 int vector_id; 4907 4908 vector_id = hclge_get_vector_index(hdev, vector); 4909 if (vector_id < 0) { 4910 dev_err(&hdev->pdev->dev, 4911 "Get vector index fail. vector = %d\n", vector); 4912 return vector_id; 4913 } 4914 4915 hclge_free_vector(hdev, vector_id); 4916 4917 return 0; 4918 } 4919 4920 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, 4921 u8 *key, u8 *hfunc) 4922 { 4923 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4924 struct hclge_vport *vport = hclge_get_vport(handle); 4925 struct hclge_comm_rss_cfg *rss_cfg = &vport->back->rss_cfg; 4926 4927 hclge_comm_get_rss_hash_info(rss_cfg, key, hfunc); 4928 4929 hclge_comm_get_rss_indir_tbl(rss_cfg, indir, 4930 ae_dev->dev_specs.rss_ind_tbl_size); 4931 4932 return 0; 4933 } 4934 4935 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, 4936 const u8 *key, const u8 hfunc) 4937 { 4938 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 4939 struct hclge_vport *vport = hclge_get_vport(handle); 4940 struct hclge_dev *hdev = vport->back; 4941 struct hclge_comm_rss_cfg *rss_cfg = &hdev->rss_cfg; 4942 int ret, i; 4943 4944 ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc); 4945 if (ret) { 4946 dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc); 4947 return ret; 4948 } 4949 4950 /* Update the shadow RSS table with user specified qids */ 4951 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 4952 rss_cfg->rss_indirection_tbl[i] = indir[i]; 4953 4954 /* Update the hardware */ 4955 return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw, 4956 rss_cfg->rss_indirection_tbl); 4957 } 4958 4959 static int hclge_set_rss_tuple(struct hnae3_handle *handle, 4960 const struct ethtool_rxfh_fields *nfc) 4961 { 4962 struct hclge_vport *vport = hclge_get_vport(handle); 4963 struct hclge_dev *hdev = vport->back; 4964 int ret; 4965 4966 ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw, 4967 &hdev->rss_cfg, nfc); 4968 if (ret) { 4969 dev_err(&hdev->pdev->dev, 4970 "failed to set rss tuple, ret = %d.\n", ret); 4971 return ret; 4972 } 4973 4974 return 0; 4975 } 4976 4977 static int hclge_get_rss_tuple(struct hnae3_handle *handle, 4978 struct ethtool_rxfh_fields *nfc) 4979 { 4980 struct hclge_vport *vport = hclge_get_vport(handle); 4981 u8 tuple_sets; 4982 int ret; 4983 4984 nfc->data = 0; 4985 4986 ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type, 4987 &tuple_sets); 4988 if (ret || !tuple_sets) 4989 return ret; 4990 4991 nfc->data = hclge_comm_convert_rss_tuple(tuple_sets); 4992 4993 return 0; 4994 } 4995 4996 static int hclge_get_tc_size(struct hnae3_handle *handle) 4997 { 4998 struct hclge_vport *vport = hclge_get_vport(handle); 4999 struct hclge_dev *hdev = vport->back; 5000 5001 return hdev->pf_rss_size_max; 5002 } 5003 5004 static int hclge_init_rss_tc_mode(struct hclge_dev *hdev) 5005 { 5006 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 5007 struct hclge_vport *vport = hdev->vport; 5008 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 5009 u16 tc_valid[HCLGE_MAX_TC_NUM] = {0}; 5010 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 5011 struct hnae3_tc_info *tc_info; 5012 u16 roundup_size; 5013 u16 rss_size; 5014 int i; 5015 5016 tc_info = &vport->nic.kinfo.tc_info; 5017 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 5018 rss_size = tc_info->tqp_count[i]; 5019 tc_valid[i] = 0; 5020 5021 if (!(hdev->hw_tc_map & BIT(i))) 5022 continue; 5023 5024 /* tc_size set to hardware is the log2 of roundup power of two 5025 * of rss_size, the acutal queue size is limited by indirection 5026 * table. 5027 */ 5028 if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size || 5029 rss_size == 0) { 5030 dev_err(&hdev->pdev->dev, 5031 "Configure rss tc size failed, invalid TC_SIZE = %u\n", 5032 rss_size); 5033 return -EINVAL; 5034 } 5035 5036 roundup_size = roundup_pow_of_two(rss_size); 5037 roundup_size = ilog2(roundup_size); 5038 5039 tc_valid[i] = 1; 5040 tc_size[i] = roundup_size; 5041 tc_offset[i] = tc_info->tqp_offset[i]; 5042 } 5043 5044 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 5045 tc_size); 5046 } 5047 5048 int hclge_rss_init_hw(struct hclge_dev *hdev) 5049 { 5050 u16 *rss_indir = hdev->rss_cfg.rss_indirection_tbl; 5051 u8 *key = hdev->rss_cfg.rss_hash_key; 5052 u8 hfunc = hdev->rss_cfg.rss_algo; 5053 int ret; 5054 5055 ret = hclge_comm_set_rss_indir_table(hdev->ae_dev, &hdev->hw.hw, 5056 rss_indir); 5057 if (ret) 5058 return ret; 5059 5060 ret = hclge_comm_set_rss_algo_key(&hdev->hw.hw, hfunc, key); 5061 if (ret) 5062 return ret; 5063 5064 ret = hclge_comm_set_rss_input_tuple(&hdev->hw.hw, &hdev->rss_cfg); 5065 if (ret) 5066 return ret; 5067 5068 return hclge_init_rss_tc_mode(hdev); 5069 } 5070 5071 int hclge_bind_ring_with_vector(struct hclge_vport *vport, 5072 int vector_id, bool en, 5073 struct hnae3_ring_chain_node *ring_chain) 5074 { 5075 struct hclge_dev *hdev = vport->back; 5076 struct hnae3_ring_chain_node *node; 5077 struct hclge_desc desc; 5078 struct hclge_ctrl_vector_chain_cmd *req = 5079 (struct hclge_ctrl_vector_chain_cmd *)desc.data; 5080 enum hclge_comm_cmd_status status; 5081 enum hclge_opcode_type op; 5082 u16 tqp_type_and_id; 5083 int i; 5084 5085 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; 5086 hclge_cmd_setup_basic_desc(&desc, op, false); 5087 req->int_vector_id_l = hnae3_get_field(vector_id, 5088 HCLGE_VECTOR_ID_L_M, 5089 HCLGE_VECTOR_ID_L_S); 5090 req->int_vector_id_h = hnae3_get_field(vector_id, 5091 HCLGE_VECTOR_ID_H_M, 5092 HCLGE_VECTOR_ID_H_S); 5093 5094 i = 0; 5095 for (node = ring_chain; node; node = node->next) { 5096 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); 5097 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, 5098 HCLGE_INT_TYPE_S, 5099 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); 5100 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, 5101 HCLGE_TQP_ID_S, node->tqp_index); 5102 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, 5103 HCLGE_INT_GL_IDX_S, 5104 hnae3_get_field(node->int_gl_idx, 5105 HNAE3_RING_GL_IDX_M, 5106 HNAE3_RING_GL_IDX_S)); 5107 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); 5108 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { 5109 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; 5110 req->vfid = vport->vport_id; 5111 5112 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5113 if (status) { 5114 dev_err(&hdev->pdev->dev, 5115 "Map TQP fail, status is %d.\n", 5116 status); 5117 return -EIO; 5118 } 5119 i = 0; 5120 5121 hclge_cmd_setup_basic_desc(&desc, 5122 op, 5123 false); 5124 req->int_vector_id_l = 5125 hnae3_get_field(vector_id, 5126 HCLGE_VECTOR_ID_L_M, 5127 HCLGE_VECTOR_ID_L_S); 5128 req->int_vector_id_h = 5129 hnae3_get_field(vector_id, 5130 HCLGE_VECTOR_ID_H_M, 5131 HCLGE_VECTOR_ID_H_S); 5132 } 5133 } 5134 5135 if (i > 0) { 5136 req->int_cause_num = i; 5137 req->vfid = vport->vport_id; 5138 status = hclge_cmd_send(&hdev->hw, &desc, 1); 5139 if (status) { 5140 dev_err(&hdev->pdev->dev, 5141 "Map TQP fail, status is %d.\n", status); 5142 return -EIO; 5143 } 5144 } 5145 5146 return 0; 5147 } 5148 5149 static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector, 5150 struct hnae3_ring_chain_node *ring_chain) 5151 { 5152 struct hclge_vport *vport = hclge_get_vport(handle); 5153 struct hclge_dev *hdev = vport->back; 5154 int vector_id; 5155 5156 vector_id = hclge_get_vector_index(hdev, vector); 5157 if (vector_id < 0) { 5158 dev_err(&hdev->pdev->dev, 5159 "failed to get vector index. vector=%d\n", vector); 5160 return vector_id; 5161 } 5162 5163 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); 5164 } 5165 5166 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector, 5167 struct hnae3_ring_chain_node *ring_chain) 5168 { 5169 struct hclge_vport *vport = hclge_get_vport(handle); 5170 struct hclge_dev *hdev = vport->back; 5171 int vector_id, ret; 5172 5173 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 5174 return 0; 5175 5176 vector_id = hclge_get_vector_index(hdev, vector); 5177 if (vector_id < 0) { 5178 dev_err(&handle->pdev->dev, 5179 "Get vector index fail. ret =%d\n", vector_id); 5180 return vector_id; 5181 } 5182 5183 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); 5184 if (ret) 5185 dev_err(&handle->pdev->dev, 5186 "Unmap ring from vector fail. vectorid=%d, ret =%d\n", 5187 vector_id, ret); 5188 5189 return ret; 5190 } 5191 5192 static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, u8 vf_id, 5193 bool en_uc, bool en_mc, bool en_bc) 5194 { 5195 struct hclge_vport *vport = &hdev->vport[vf_id]; 5196 struct hnae3_handle *handle = &vport->nic; 5197 struct hclge_promisc_cfg_cmd *req; 5198 struct hclge_desc desc; 5199 bool uc_tx_en = en_uc; 5200 u8 promisc_cfg = 0; 5201 int ret; 5202 5203 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); 5204 5205 req = (struct hclge_promisc_cfg_cmd *)desc.data; 5206 req->vf_id = vf_id; 5207 5208 if (test_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags)) 5209 uc_tx_en = false; 5210 5211 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_RX_EN, en_uc ? 1 : 0); 5212 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_RX_EN, en_mc ? 1 : 0); 5213 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_RX_EN, en_bc ? 1 : 0); 5214 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_UC_TX_EN, uc_tx_en ? 1 : 0); 5215 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_MC_TX_EN, en_mc ? 1 : 0); 5216 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_BC_TX_EN, en_bc ? 1 : 0); 5217 req->extend_promisc = promisc_cfg; 5218 5219 /* to be compatible with DEVICE_VERSION_V1/2 */ 5220 promisc_cfg = 0; 5221 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_UC, en_uc ? 1 : 0); 5222 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_MC, en_mc ? 1 : 0); 5223 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_EN_BC, en_bc ? 1 : 0); 5224 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_TX_EN, 1); 5225 hnae3_set_bit(promisc_cfg, HCLGE_PROMISC_RX_EN, 1); 5226 req->promisc = promisc_cfg; 5227 5228 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5229 if (ret) 5230 dev_err(&hdev->pdev->dev, 5231 "failed to set vport %u promisc mode, ret = %d.\n", 5232 vf_id, ret); 5233 5234 return ret; 5235 } 5236 5237 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, 5238 bool en_mc_pmc, bool en_bc_pmc) 5239 { 5240 return hclge_cmd_set_promisc_mode(vport->back, vport->vport_id, 5241 en_uc_pmc, en_mc_pmc, en_bc_pmc); 5242 } 5243 5244 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, 5245 bool en_mc_pmc) 5246 { 5247 struct hclge_vport *vport = hclge_get_vport(handle); 5248 struct hclge_dev *hdev = vport->back; 5249 bool en_bc_pmc = true; 5250 5251 /* For device whose version below V2, if broadcast promisc enabled, 5252 * vlan filter is always bypassed. So broadcast promisc should be 5253 * disabled until user enable promisc mode 5254 */ 5255 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 5256 en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false; 5257 5258 return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc, 5259 en_bc_pmc); 5260 } 5261 5262 static void hclge_request_update_promisc_mode(struct hnae3_handle *handle) 5263 { 5264 struct hclge_vport *vport = hclge_get_vport(handle); 5265 5266 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5267 } 5268 5269 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle) 5270 { 5271 struct hclge_vport *vport = hclge_get_vport(handle); 5272 struct hclge_dev *hdev = vport->back; 5273 5274 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) || 5275 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING); 5276 } 5277 5278 static bool hclge_get_cmdq_stat(struct hnae3_handle *handle) 5279 { 5280 struct hclge_vport *vport = hclge_get_vport(handle); 5281 struct hclge_dev *hdev = vport->back; 5282 5283 return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 5284 } 5285 5286 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle) 5287 { 5288 struct hclge_vport *vport = hclge_get_vport(handle); 5289 struct hclge_dev *hdev = vport->back; 5290 5291 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 5292 } 5293 5294 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle) 5295 { 5296 struct hclge_vport *vport = hclge_get_vport(handle); 5297 struct hclge_dev *hdev = vport->back; 5298 5299 return hdev->rst_stats.hw_reset_done_cnt; 5300 } 5301 5302 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) 5303 { 5304 #define HCLGE_LINK_STATUS_WAIT_CNT 3 5305 5306 struct hclge_desc desc; 5307 struct hclge_config_mac_mode_cmd *req = 5308 (struct hclge_config_mac_mode_cmd *)desc.data; 5309 u32 loop_en = 0; 5310 int ret; 5311 5312 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); 5313 5314 if (enable) { 5315 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, 1U); 5316 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, 1U); 5317 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, 1U); 5318 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, 1U); 5319 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, 1U); 5320 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, 1U); 5321 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, 1U); 5322 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, 1U); 5323 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, 1U); 5324 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, 1U); 5325 } 5326 5327 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 5328 5329 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5330 if (ret) { 5331 dev_err(&hdev->pdev->dev, 5332 "mac enable fail, ret =%d.\n", ret); 5333 return; 5334 } 5335 5336 if (!enable) 5337 hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN, 5338 HCLGE_LINK_STATUS_WAIT_CNT); 5339 } 5340 5341 u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id, 5342 u8 vf_id, u8 network_port_id) 5343 { 5344 u32 port_number = 0; 5345 5346 if (port_type == HOST_PORT) { 5347 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S, 5348 pf_id); 5349 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S, 5350 vf_id); 5351 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT); 5352 } else { 5353 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M, 5354 HCLGE_NETWORK_PORT_ID_S, network_port_id); 5355 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT); 5356 } 5357 5358 return port_number; 5359 } 5360 5361 static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid, 5362 u8 switch_param, u8 param_mask) 5363 { 5364 struct hclge_mac_vlan_switch_cmd *req; 5365 struct hclge_desc desc; 5366 u32 func_id; 5367 int ret; 5368 5369 func_id = hclge_get_port_number(HOST_PORT, 0, vfid, 0); 5370 req = (struct hclge_mac_vlan_switch_cmd *)desc.data; 5371 5372 /* read current config parameter */ 5373 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_SWITCH_PARAM, 5374 true); 5375 req->roce_sel = HCLGE_MAC_VLAN_NIC_SEL; 5376 req->func_id = cpu_to_le32(func_id); 5377 5378 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5379 if (ret) { 5380 dev_err(&hdev->pdev->dev, 5381 "read mac vlan switch parameter fail, ret = %d\n", ret); 5382 return ret; 5383 } 5384 5385 /* modify and write new config parameter */ 5386 hclge_comm_cmd_reuse_desc(&desc, false); 5387 req->switch_param = (req->switch_param & param_mask) | switch_param; 5388 req->param_mask = param_mask; 5389 5390 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5391 if (ret) 5392 dev_err(&hdev->pdev->dev, 5393 "set mac vlan switch parameter fail, ret = %d\n", ret); 5394 return ret; 5395 } 5396 5397 static void hclge_phy_link_status_wait(struct hclge_dev *hdev, 5398 int link_ret) 5399 { 5400 #define HCLGE_PHY_LINK_STATUS_NUM 200 5401 5402 struct phy_device *phydev = hdev->hw.mac.phydev; 5403 int i = 0; 5404 int ret; 5405 5406 do { 5407 ret = phy_read_status(phydev); 5408 if (ret) { 5409 dev_err(&hdev->pdev->dev, 5410 "phy update link status fail, ret = %d\n", ret); 5411 return; 5412 } 5413 5414 if (phydev->link == link_ret) 5415 break; 5416 5417 msleep(HCLGE_LINK_STATUS_MS); 5418 } while (++i < HCLGE_PHY_LINK_STATUS_NUM); 5419 } 5420 5421 static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret, 5422 int wait_cnt) 5423 { 5424 int link_status; 5425 int i = 0; 5426 int ret; 5427 5428 do { 5429 ret = hclge_get_mac_link_status(hdev, &link_status); 5430 if (ret) 5431 return ret; 5432 if (link_status == link_ret) 5433 return 0; 5434 5435 msleep(HCLGE_LINK_STATUS_MS); 5436 } while (++i < wait_cnt); 5437 return -EBUSY; 5438 } 5439 5440 static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en, 5441 bool is_phy) 5442 { 5443 #define HCLGE_MAC_LINK_STATUS_NUM 100 5444 5445 int link_ret; 5446 5447 link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN; 5448 5449 if (is_phy) 5450 hclge_phy_link_status_wait(hdev, link_ret); 5451 5452 return hclge_mac_link_status_wait(hdev, link_ret, 5453 HCLGE_MAC_LINK_STATUS_NUM); 5454 } 5455 5456 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en) 5457 { 5458 struct hclge_config_mac_mode_cmd *req; 5459 struct hclge_desc desc; 5460 u32 loop_en; 5461 int ret; 5462 5463 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; 5464 /* 1 Read out the MAC mode config at first */ 5465 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 5466 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5467 if (ret) { 5468 dev_err(&hdev->pdev->dev, 5469 "mac loopback get fail, ret =%d.\n", ret); 5470 return ret; 5471 } 5472 5473 /* 2 Then setup the loopback flag */ 5474 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 5475 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); 5476 5477 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); 5478 5479 /* 3 Config mac work mode with loopback flag 5480 * and its original configure parameters 5481 */ 5482 hclge_comm_cmd_reuse_desc(&desc, false); 5483 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5484 if (ret) 5485 dev_err(&hdev->pdev->dev, 5486 "mac loopback set fail, ret =%d.\n", ret); 5487 return ret; 5488 } 5489 5490 static int hclge_cfg_common_loopback_cmd_send(struct hclge_dev *hdev, bool en, 5491 enum hnae3_loop loop_mode) 5492 { 5493 struct hclge_common_lb_cmd *req; 5494 struct hclge_desc desc; 5495 u8 loop_mode_b; 5496 int ret; 5497 5498 req = (struct hclge_common_lb_cmd *)desc.data; 5499 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false); 5500 5501 switch (loop_mode) { 5502 case HNAE3_LOOP_SERIAL_SERDES: 5503 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 5504 break; 5505 case HNAE3_LOOP_PARALLEL_SERDES: 5506 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B; 5507 break; 5508 case HNAE3_LOOP_PHY: 5509 loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B; 5510 break; 5511 default: 5512 dev_err(&hdev->pdev->dev, 5513 "unsupported loopback mode %d\n", loop_mode); 5514 return -ENOTSUPP; 5515 } 5516 5517 req->mask = loop_mode_b; 5518 if (en) 5519 req->enable = loop_mode_b; 5520 5521 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5522 if (ret) 5523 dev_err(&hdev->pdev->dev, 5524 "failed to send loopback cmd, loop_mode = %d, ret = %d\n", 5525 loop_mode, ret); 5526 5527 return ret; 5528 } 5529 5530 static int hclge_cfg_common_loopback_wait(struct hclge_dev *hdev) 5531 { 5532 #define HCLGE_COMMON_LB_RETRY_MS 10 5533 #define HCLGE_COMMON_LB_RETRY_NUM 100 5534 5535 struct hclge_common_lb_cmd *req; 5536 struct hclge_desc desc; 5537 u32 i = 0; 5538 int ret; 5539 5540 req = (struct hclge_common_lb_cmd *)desc.data; 5541 5542 do { 5543 msleep(HCLGE_COMMON_LB_RETRY_MS); 5544 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, 5545 true); 5546 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 5547 if (ret) { 5548 dev_err(&hdev->pdev->dev, 5549 "failed to get loopback done status, ret = %d\n", 5550 ret); 5551 return ret; 5552 } 5553 } while (++i < HCLGE_COMMON_LB_RETRY_NUM && 5554 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B)); 5555 5556 if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) { 5557 dev_err(&hdev->pdev->dev, "wait loopback timeout\n"); 5558 return -EBUSY; 5559 } else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) { 5560 dev_err(&hdev->pdev->dev, "failed to do loopback test\n"); 5561 return -EIO; 5562 } 5563 5564 return 0; 5565 } 5566 5567 static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en, 5568 enum hnae3_loop loop_mode) 5569 { 5570 int ret; 5571 5572 ret = hclge_cfg_common_loopback_cmd_send(hdev, en, loop_mode); 5573 if (ret) 5574 return ret; 5575 5576 return hclge_cfg_common_loopback_wait(hdev); 5577 } 5578 5579 static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en, 5580 enum hnae3_loop loop_mode) 5581 { 5582 int ret; 5583 5584 ret = hclge_cfg_common_loopback(hdev, en, loop_mode); 5585 if (ret) 5586 return ret; 5587 5588 hclge_cfg_mac_mode(hdev, en); 5589 5590 ret = hclge_mac_phy_link_status_wait(hdev, en, false); 5591 if (ret) 5592 dev_err(&hdev->pdev->dev, 5593 "serdes loopback config mac mode timeout\n"); 5594 5595 return ret; 5596 } 5597 5598 static int hclge_enable_phy_loopback(struct hclge_dev *hdev, 5599 struct phy_device *phydev) 5600 { 5601 int ret; 5602 5603 if (!phydev->suspended) { 5604 ret = phy_suspend(phydev); 5605 if (ret) 5606 return ret; 5607 } 5608 5609 ret = phy_resume(phydev); 5610 if (ret) 5611 return ret; 5612 5613 return phy_loopback(phydev, true, 0); 5614 } 5615 5616 static int hclge_disable_phy_loopback(struct hclge_dev *hdev, 5617 struct phy_device *phydev) 5618 { 5619 int ret; 5620 5621 ret = phy_loopback(phydev, false, 0); 5622 if (ret) 5623 return ret; 5624 5625 return phy_suspend(phydev); 5626 } 5627 5628 static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en) 5629 { 5630 struct phy_device *phydev = hdev->hw.mac.phydev; 5631 int ret; 5632 5633 if (!phydev) { 5634 if (hnae3_dev_phy_imp_supported(hdev)) 5635 return hclge_set_common_loopback(hdev, en, 5636 HNAE3_LOOP_PHY); 5637 return -ENOTSUPP; 5638 } 5639 5640 if (en) 5641 ret = hclge_enable_phy_loopback(hdev, phydev); 5642 else 5643 ret = hclge_disable_phy_loopback(hdev, phydev); 5644 if (ret) { 5645 dev_err(&hdev->pdev->dev, 5646 "set phy loopback fail, ret = %d\n", ret); 5647 return ret; 5648 } 5649 5650 hclge_cfg_mac_mode(hdev, en); 5651 5652 ret = hclge_mac_phy_link_status_wait(hdev, en, true); 5653 if (ret) 5654 dev_err(&hdev->pdev->dev, 5655 "phy loopback config mac mode timeout\n"); 5656 5657 return ret; 5658 } 5659 5660 static int hclge_tqp_enable_cmd_send(struct hclge_dev *hdev, u16 tqp_id, 5661 u16 stream_id, bool enable) 5662 { 5663 struct hclge_desc desc; 5664 struct hclge_cfg_com_tqp_queue_cmd *req = 5665 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; 5666 5667 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); 5668 req->tqp_id = cpu_to_le16(tqp_id); 5669 req->stream_id = cpu_to_le16(stream_id); 5670 if (enable) 5671 req->enable |= 1U << HCLGE_TQP_ENABLE_B; 5672 5673 return hclge_cmd_send(&hdev->hw, &desc, 1); 5674 } 5675 5676 static int hclge_tqp_enable(struct hnae3_handle *handle, bool enable) 5677 { 5678 struct hclge_vport *vport = hclge_get_vport(handle); 5679 struct hclge_dev *hdev = vport->back; 5680 int ret; 5681 u16 i; 5682 5683 for (i = 0; i < handle->kinfo.num_tqps; i++) { 5684 ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable); 5685 if (ret) 5686 return ret; 5687 } 5688 return 0; 5689 } 5690 5691 static int hclge_set_loopback(struct hnae3_handle *handle, 5692 enum hnae3_loop loop_mode, bool en) 5693 { 5694 struct hclge_vport *vport = hclge_get_vport(handle); 5695 struct hclge_dev *hdev = vport->back; 5696 int ret = 0; 5697 5698 /* Loopback can be enabled in three places: SSU, MAC, and serdes. By 5699 * default, SSU loopback is enabled, so if the SMAC and the DMAC are 5700 * the same, the packets are looped back in the SSU. If SSU loopback 5701 * is disabled, packets can reach MAC even if SMAC is the same as DMAC. 5702 */ 5703 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) { 5704 u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B); 5705 5706 ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param, 5707 HCLGE_SWITCH_ALW_LPBK_MASK); 5708 if (ret) 5709 return ret; 5710 } 5711 5712 switch (loop_mode) { 5713 case HNAE3_LOOP_APP: 5714 ret = hclge_set_app_loopback(hdev, en); 5715 break; 5716 case HNAE3_LOOP_SERIAL_SERDES: 5717 case HNAE3_LOOP_PARALLEL_SERDES: 5718 ret = hclge_set_common_loopback(hdev, en, loop_mode); 5719 break; 5720 case HNAE3_LOOP_PHY: 5721 ret = hclge_set_phy_loopback(hdev, en); 5722 break; 5723 case HNAE3_LOOP_EXTERNAL: 5724 break; 5725 default: 5726 ret = -ENOTSUPP; 5727 dev_err(&hdev->pdev->dev, 5728 "loop_mode %d is not supported\n", loop_mode); 5729 break; 5730 } 5731 5732 if (ret) 5733 return ret; 5734 5735 ret = hclge_tqp_enable(handle, en); 5736 if (ret) 5737 dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n", 5738 str_enable_disable(en), ret); 5739 5740 return ret; 5741 } 5742 5743 static int hclge_set_default_loopback(struct hclge_dev *hdev) 5744 { 5745 int ret; 5746 5747 ret = hclge_set_app_loopback(hdev, false); 5748 if (ret) 5749 return ret; 5750 5751 ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES); 5752 if (ret) 5753 return ret; 5754 5755 return hclge_cfg_common_loopback(hdev, false, 5756 HNAE3_LOOP_PARALLEL_SERDES); 5757 } 5758 5759 static void hclge_flush_link_update(struct hclge_dev *hdev) 5760 { 5761 #define HCLGE_FLUSH_LINK_TIMEOUT 100000 5762 5763 unsigned long last = hdev->serv_processed_cnt; 5764 int i = 0; 5765 5766 while (test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state) && 5767 i++ < HCLGE_FLUSH_LINK_TIMEOUT && 5768 last == hdev->serv_processed_cnt) 5769 usleep_range(1, 1); 5770 } 5771 5772 static void hclge_set_timer_task(struct hnae3_handle *handle, bool enable) 5773 { 5774 struct hclge_vport *vport = hclge_get_vport(handle); 5775 struct hclge_dev *hdev = vport->back; 5776 5777 if (enable) { 5778 hclge_task_schedule(hdev, 0); 5779 } else { 5780 /* Set the DOWN flag here to disable link updating */ 5781 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5782 5783 smp_mb__after_atomic(); /* flush memory to make sure DOWN is seen by service task */ 5784 hclge_flush_link_update(hdev); 5785 } 5786 } 5787 5788 static int hclge_ae_start(struct hnae3_handle *handle) 5789 { 5790 struct hclge_vport *vport = hclge_get_vport(handle); 5791 struct hclge_dev *hdev = vport->back; 5792 5793 /* mac enable */ 5794 hclge_cfg_mac_mode(hdev, true); 5795 clear_bit(HCLGE_STATE_DOWN, &hdev->state); 5796 hdev->hw.mac.link = 0; 5797 5798 /* reset tqp stats */ 5799 hclge_comm_reset_tqp_stats(handle); 5800 5801 hclge_mac_start_phy(hdev); 5802 5803 return 0; 5804 } 5805 5806 static void hclge_ae_stop(struct hnae3_handle *handle) 5807 { 5808 struct hclge_vport *vport = hclge_get_vport(handle); 5809 struct hclge_dev *hdev = vport->back; 5810 5811 set_bit(HCLGE_STATE_DOWN, &hdev->state); 5812 spin_lock_bh(&hdev->fd_rule_lock); 5813 hclge_clear_arfs_rules(hdev); 5814 spin_unlock_bh(&hdev->fd_rule_lock); 5815 5816 /* If it is not PF reset or FLR, the firmware will disable the MAC, 5817 * so it only need to stop phy here. 5818 */ 5819 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { 5820 hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE, 5821 HCLGE_PFC_DISABLE); 5822 if (hdev->reset_type != HNAE3_FUNC_RESET && 5823 hdev->reset_type != HNAE3_FLR_RESET) { 5824 hclge_mac_stop_phy(hdev); 5825 hclge_update_link_status(hdev); 5826 return; 5827 } 5828 } 5829 5830 hclge_reset_tqp(handle); 5831 5832 hclge_config_mac_tnl_int(hdev, false); 5833 5834 /* Mac disable */ 5835 hclge_cfg_mac_mode(hdev, false); 5836 5837 hclge_mac_stop_phy(hdev); 5838 5839 /* reset tqp stats */ 5840 hclge_comm_reset_tqp_stats(handle); 5841 hclge_update_link_status(hdev); 5842 } 5843 5844 int hclge_vport_start(struct hclge_vport *vport) 5845 { 5846 struct hclge_dev *hdev = vport->back; 5847 5848 set_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 5849 set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 5850 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 5851 vport->last_active_jiffies = jiffies; 5852 vport->need_notify = 0; 5853 5854 if (test_bit(vport->vport_id, hdev->vport_config_block)) { 5855 if (vport->vport_id) { 5856 hclge_restore_mac_table_common(vport); 5857 hclge_restore_vport_vlan_table(vport); 5858 } else { 5859 hclge_restore_hw_table(hdev); 5860 } 5861 } 5862 5863 clear_bit(vport->vport_id, hdev->vport_config_block); 5864 5865 return 0; 5866 } 5867 5868 void hclge_vport_stop(struct hclge_vport *vport) 5869 { 5870 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 5871 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 5872 vport->need_notify = 0; 5873 } 5874 5875 static int hclge_client_start(struct hnae3_handle *handle) 5876 { 5877 struct hclge_vport *vport = hclge_get_vport(handle); 5878 5879 return hclge_vport_start(vport); 5880 } 5881 5882 static void hclge_client_stop(struct hnae3_handle *handle) 5883 { 5884 struct hclge_vport *vport = hclge_get_vport(handle); 5885 5886 hclge_vport_stop(vport); 5887 } 5888 5889 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, 5890 u16 cmdq_resp, u8 resp_code, 5891 enum hclge_mac_vlan_tbl_opcode op) 5892 { 5893 struct hclge_dev *hdev = vport->back; 5894 5895 if (cmdq_resp) { 5896 dev_err(&hdev->pdev->dev, 5897 "cmdq execute failed for get_mac_vlan_cmd_status,status=%u.\n", 5898 cmdq_resp); 5899 return -EIO; 5900 } 5901 5902 if (op == HCLGE_MAC_VLAN_ADD) { 5903 if (!resp_code || resp_code == 1) 5904 return 0; 5905 else if (resp_code == HCLGE_ADD_UC_OVERFLOW || 5906 resp_code == HCLGE_ADD_MC_OVERFLOW) 5907 return -ENOSPC; 5908 5909 dev_err(&hdev->pdev->dev, 5910 "add mac addr failed for undefined, code=%u.\n", 5911 resp_code); 5912 return -EIO; 5913 } else if (op == HCLGE_MAC_VLAN_REMOVE) { 5914 if (!resp_code) { 5915 return 0; 5916 } else if (resp_code == 1) { 5917 dev_dbg(&hdev->pdev->dev, 5918 "remove mac addr failed for miss.\n"); 5919 return -ENOENT; 5920 } 5921 5922 dev_err(&hdev->pdev->dev, 5923 "remove mac addr failed for undefined, code=%u.\n", 5924 resp_code); 5925 return -EIO; 5926 } else if (op == HCLGE_MAC_VLAN_LKUP) { 5927 if (!resp_code) { 5928 return 0; 5929 } else if (resp_code == 1) { 5930 dev_dbg(&hdev->pdev->dev, 5931 "lookup mac addr failed for miss.\n"); 5932 return -ENOENT; 5933 } 5934 5935 dev_err(&hdev->pdev->dev, 5936 "lookup mac addr failed for undefined, code=%u.\n", 5937 resp_code); 5938 return -EIO; 5939 } 5940 5941 dev_err(&hdev->pdev->dev, 5942 "unknown opcode for get_mac_vlan_cmd_status, opcode=%d.\n", op); 5943 5944 return -EINVAL; 5945 } 5946 5947 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) 5948 { 5949 #define HCLGE_VF_NUM_IN_FIRST_DESC 192 5950 5951 unsigned int word_num; 5952 unsigned int bit_num; 5953 5954 if (vfid > 255 || vfid < 0) 5955 return -EIO; 5956 5957 if (vfid >= 0 && vfid < HCLGE_VF_NUM_IN_FIRST_DESC) { 5958 word_num = vfid / 32; 5959 bit_num = vfid % 32; 5960 if (clr) 5961 desc[1].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 5962 else 5963 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); 5964 } else { 5965 word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32; 5966 bit_num = vfid % 32; 5967 if (clr) 5968 desc[2].data[word_num] &= cpu_to_le32(~(1U << bit_num)); 5969 else 5970 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); 5971 } 5972 5973 return 0; 5974 } 5975 5976 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) 5977 { 5978 #define HCLGE_DESC_NUMBER 3 5979 #define HCLGE_FUNC_NUMBER_PER_DESC 6 5980 int i, j; 5981 5982 for (i = 1; i < HCLGE_DESC_NUMBER; i++) 5983 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) 5984 if (desc[i].data[j]) 5985 return false; 5986 5987 return true; 5988 } 5989 5990 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, 5991 const u8 *addr, bool is_mc) 5992 { 5993 const unsigned char *mac_addr = addr; 5994 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | 5995 (mac_addr[0]) | (mac_addr[1] << 8); 5996 u32 low_val = mac_addr[4] | (mac_addr[5] << 8); 5997 5998 hnae3_set_bit(new_req->flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 5999 if (is_mc) { 6000 hnae3_set_bit(new_req->entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); 6001 hnae3_set_bit(new_req->mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1); 6002 } 6003 6004 new_req->mac_addr_hi32 = cpu_to_le32(high_val); 6005 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); 6006 } 6007 6008 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, 6009 struct hclge_mac_vlan_tbl_entry_cmd *req) 6010 { 6011 struct hclge_dev *hdev = vport->back; 6012 struct hclge_desc desc; 6013 u8 resp_code; 6014 u16 retval; 6015 int ret; 6016 6017 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); 6018 6019 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 6020 6021 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6022 if (ret) { 6023 dev_err(&hdev->pdev->dev, 6024 "del mac addr failed for cmd_send, ret =%d.\n", 6025 ret); 6026 return ret; 6027 } 6028 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 6029 retval = le16_to_cpu(desc.retval); 6030 6031 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 6032 HCLGE_MAC_VLAN_REMOVE); 6033 } 6034 6035 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, 6036 struct hclge_mac_vlan_tbl_entry_cmd *req, 6037 struct hclge_desc *desc, 6038 bool is_mc) 6039 { 6040 struct hclge_dev *hdev = vport->back; 6041 u8 resp_code; 6042 u16 retval; 6043 int ret; 6044 6045 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); 6046 if (is_mc) { 6047 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 6048 memcpy(desc[0].data, 6049 req, 6050 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 6051 hclge_cmd_setup_basic_desc(&desc[1], 6052 HCLGE_OPC_MAC_VLAN_ADD, 6053 true); 6054 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 6055 hclge_cmd_setup_basic_desc(&desc[2], 6056 HCLGE_OPC_MAC_VLAN_ADD, 6057 true); 6058 ret = hclge_cmd_send(&hdev->hw, desc, 3); 6059 } else { 6060 memcpy(desc[0].data, 6061 req, 6062 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 6063 ret = hclge_cmd_send(&hdev->hw, desc, 1); 6064 } 6065 if (ret) { 6066 dev_err(&hdev->pdev->dev, 6067 "lookup mac addr failed for cmd_send, ret =%d.\n", 6068 ret); 6069 return ret; 6070 } 6071 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; 6072 retval = le16_to_cpu(desc[0].retval); 6073 6074 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, 6075 HCLGE_MAC_VLAN_LKUP); 6076 } 6077 6078 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, 6079 struct hclge_mac_vlan_tbl_entry_cmd *req, 6080 struct hclge_desc *mc_desc) 6081 { 6082 struct hclge_dev *hdev = vport->back; 6083 int cfg_status; 6084 u8 resp_code; 6085 u16 retval; 6086 int ret; 6087 6088 if (!mc_desc) { 6089 struct hclge_desc desc; 6090 6091 hclge_cmd_setup_basic_desc(&desc, 6092 HCLGE_OPC_MAC_VLAN_ADD, 6093 false); 6094 memcpy(desc.data, req, 6095 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 6096 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6097 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 6098 retval = le16_to_cpu(desc.retval); 6099 6100 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 6101 resp_code, 6102 HCLGE_MAC_VLAN_ADD); 6103 } else { 6104 hclge_comm_cmd_reuse_desc(&mc_desc[0], false); 6105 mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 6106 hclge_comm_cmd_reuse_desc(&mc_desc[1], false); 6107 mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 6108 hclge_comm_cmd_reuse_desc(&mc_desc[2], false); 6109 mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT); 6110 memcpy(mc_desc[0].data, req, 6111 sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); 6112 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); 6113 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; 6114 retval = le16_to_cpu(mc_desc[0].retval); 6115 6116 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, 6117 resp_code, 6118 HCLGE_MAC_VLAN_ADD); 6119 } 6120 6121 if (ret) { 6122 dev_err(&hdev->pdev->dev, 6123 "add mac addr failed for cmd_send, ret =%d.\n", 6124 ret); 6125 return ret; 6126 } 6127 6128 return cfg_status; 6129 } 6130 6131 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size, 6132 u16 *allocated_size) 6133 { 6134 struct hclge_umv_spc_alc_cmd *req; 6135 struct hclge_desc desc; 6136 int ret; 6137 6138 req = (struct hclge_umv_spc_alc_cmd *)desc.data; 6139 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false); 6140 6141 req->space_size = cpu_to_le32(space_size); 6142 6143 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 6144 if (ret) { 6145 dev_err(&hdev->pdev->dev, "failed to set umv space, ret = %d\n", 6146 ret); 6147 return ret; 6148 } 6149 6150 *allocated_size = le32_to_cpu(desc.data[1]); 6151 6152 return 0; 6153 } 6154 6155 static int hclge_init_umv_space(struct hclge_dev *hdev) 6156 { 6157 u16 allocated_size = 0; 6158 int ret; 6159 6160 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size); 6161 if (ret) 6162 return ret; 6163 6164 if (allocated_size < hdev->wanted_umv_size) 6165 dev_warn(&hdev->pdev->dev, 6166 "failed to alloc umv space, want %u, get %u\n", 6167 hdev->wanted_umv_size, allocated_size); 6168 6169 hdev->max_umv_size = allocated_size; 6170 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_alloc_vport + 1); 6171 hdev->share_umv_size = hdev->priv_umv_size + 6172 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 6173 6174 if (hdev->ae_dev->dev_specs.mc_mac_size) 6175 set_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, hdev->ae_dev->caps); 6176 6177 return 0; 6178 } 6179 6180 static void hclge_reset_umv_space(struct hclge_dev *hdev) 6181 { 6182 struct hclge_vport *vport; 6183 int i; 6184 6185 for (i = 0; i < hdev->num_alloc_vport; i++) { 6186 vport = &hdev->vport[i]; 6187 vport->used_umv_num = 0; 6188 } 6189 6190 mutex_lock(&hdev->vport_lock); 6191 hdev->share_umv_size = hdev->priv_umv_size + 6192 hdev->max_umv_size % (hdev->num_alloc_vport + 1); 6193 mutex_unlock(&hdev->vport_lock); 6194 6195 hdev->used_mc_mac_num = 0; 6196 } 6197 6198 static bool hclge_is_umv_space_full(struct hclge_vport *vport, bool need_lock) 6199 { 6200 struct hclge_dev *hdev = vport->back; 6201 bool is_full; 6202 6203 if (need_lock) 6204 mutex_lock(&hdev->vport_lock); 6205 6206 is_full = (vport->used_umv_num >= hdev->priv_umv_size && 6207 hdev->share_umv_size == 0); 6208 6209 if (need_lock) 6210 mutex_unlock(&hdev->vport_lock); 6211 6212 return is_full; 6213 } 6214 6215 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free) 6216 { 6217 struct hclge_dev *hdev = vport->back; 6218 6219 if (is_free) { 6220 if (vport->used_umv_num > hdev->priv_umv_size) 6221 hdev->share_umv_size++; 6222 6223 if (vport->used_umv_num > 0) 6224 vport->used_umv_num--; 6225 } else { 6226 if (vport->used_umv_num >= hdev->priv_umv_size && 6227 hdev->share_umv_size > 0) 6228 hdev->share_umv_size--; 6229 vport->used_umv_num++; 6230 } 6231 } 6232 6233 static struct hclge_mac_node *hclge_find_mac_node(struct list_head *list, 6234 const u8 *mac_addr) 6235 { 6236 struct hclge_mac_node *mac_node, *tmp; 6237 6238 list_for_each_entry_safe(mac_node, tmp, list, node) 6239 if (ether_addr_equal(mac_addr, mac_node->mac_addr)) 6240 return mac_node; 6241 6242 return NULL; 6243 } 6244 6245 static void hclge_update_mac_node(struct hclge_mac_node *mac_node, 6246 enum HCLGE_MAC_NODE_STATE state) 6247 { 6248 switch (state) { 6249 /* from set_rx_mode or tmp_add_list */ 6250 case HCLGE_MAC_TO_ADD: 6251 if (mac_node->state == HCLGE_MAC_TO_DEL) 6252 mac_node->state = HCLGE_MAC_ACTIVE; 6253 break; 6254 /* only from set_rx_mode */ 6255 case HCLGE_MAC_TO_DEL: 6256 if (mac_node->state == HCLGE_MAC_TO_ADD) { 6257 list_del(&mac_node->node); 6258 kfree(mac_node); 6259 } else { 6260 mac_node->state = HCLGE_MAC_TO_DEL; 6261 } 6262 break; 6263 /* only from tmp_add_list, the mac_node->state won't be 6264 * ACTIVE. 6265 */ 6266 case HCLGE_MAC_ACTIVE: 6267 if (mac_node->state == HCLGE_MAC_TO_ADD) 6268 mac_node->state = HCLGE_MAC_ACTIVE; 6269 6270 break; 6271 } 6272 } 6273 6274 int hclge_update_mac_list(struct hclge_vport *vport, 6275 enum HCLGE_MAC_NODE_STATE state, 6276 enum HCLGE_MAC_ADDR_TYPE mac_type, 6277 const unsigned char *addr) 6278 { 6279 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6280 struct hclge_dev *hdev = vport->back; 6281 struct hclge_mac_node *mac_node; 6282 struct list_head *list; 6283 6284 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6285 &vport->uc_mac_list : &vport->mc_mac_list; 6286 6287 spin_lock_bh(&vport->mac_list_lock); 6288 6289 /* if the mac addr is already in the mac list, no need to add a new 6290 * one into it, just check the mac addr state, convert it to a new 6291 * state, or just remove it, or do nothing. 6292 */ 6293 mac_node = hclge_find_mac_node(list, addr); 6294 if (mac_node) { 6295 hclge_update_mac_node(mac_node, state); 6296 spin_unlock_bh(&vport->mac_list_lock); 6297 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 6298 return 0; 6299 } 6300 6301 /* if this address is never added, unnecessary to delete */ 6302 if (state == HCLGE_MAC_TO_DEL) { 6303 spin_unlock_bh(&vport->mac_list_lock); 6304 hnae3_format_mac_addr(format_mac_addr, addr); 6305 dev_err(&hdev->pdev->dev, 6306 "failed to delete address %s from mac list\n", 6307 format_mac_addr); 6308 return -ENOENT; 6309 } 6310 6311 mac_node = kzalloc_obj(*mac_node, GFP_ATOMIC); 6312 if (!mac_node) { 6313 spin_unlock_bh(&vport->mac_list_lock); 6314 return -ENOMEM; 6315 } 6316 6317 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 6318 6319 mac_node->state = state; 6320 ether_addr_copy(mac_node->mac_addr, addr); 6321 list_add_tail(&mac_node->node, list); 6322 6323 spin_unlock_bh(&vport->mac_list_lock); 6324 6325 return 0; 6326 } 6327 6328 static int hclge_add_uc_addr(struct hnae3_handle *handle, 6329 const unsigned char *addr) 6330 { 6331 struct hclge_vport *vport = hclge_get_vport(handle); 6332 6333 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_UC, 6334 addr); 6335 } 6336 6337 int hclge_add_uc_addr_common(struct hclge_vport *vport, 6338 const unsigned char *addr) 6339 { 6340 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6341 struct hclge_dev *hdev = vport->back; 6342 struct hclge_mac_vlan_tbl_entry_cmd req; 6343 struct hclge_desc desc; 6344 u16 egress_port = 0; 6345 int ret; 6346 6347 /* mac addr check */ 6348 if (is_zero_ether_addr(addr) || 6349 is_broadcast_ether_addr(addr) || 6350 is_multicast_ether_addr(addr)) { 6351 hnae3_format_mac_addr(format_mac_addr, addr); 6352 dev_err(&hdev->pdev->dev, 6353 "Set_uc mac err! invalid mac:%s. is_zero:%d,is_br=%d,is_mul=%d\n", 6354 format_mac_addr, is_zero_ether_addr(addr), 6355 is_broadcast_ether_addr(addr), 6356 is_multicast_ether_addr(addr)); 6357 return -EINVAL; 6358 } 6359 6360 memset(&req, 0, sizeof(req)); 6361 6362 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, 6363 HCLGE_MAC_EPORT_VFID_S, vport->vport_id); 6364 6365 req.egress_port = cpu_to_le16(egress_port); 6366 6367 hclge_prepare_mac_addr(&req, addr, false); 6368 6369 /* Lookup the mac address in the mac_vlan table, and add 6370 * it if the entry is inexistent. Repeated unicast entry 6371 * is not allowed in the mac vlan table. 6372 */ 6373 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); 6374 if (ret == -ENOENT) { 6375 mutex_lock(&hdev->vport_lock); 6376 if (!hclge_is_umv_space_full(vport, false)) { 6377 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL); 6378 if (!ret) 6379 hclge_update_umv_space(vport, false); 6380 mutex_unlock(&hdev->vport_lock); 6381 return ret; 6382 } 6383 mutex_unlock(&hdev->vport_lock); 6384 6385 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE)) 6386 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n", 6387 hdev->priv_umv_size); 6388 6389 return -ENOSPC; 6390 } 6391 6392 /* check if we just hit the duplicate */ 6393 if (!ret) 6394 return -EEXIST; 6395 6396 return ret; 6397 } 6398 6399 static int hclge_rm_uc_addr(struct hnae3_handle *handle, 6400 const unsigned char *addr) 6401 { 6402 struct hclge_vport *vport = hclge_get_vport(handle); 6403 6404 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_UC, 6405 addr); 6406 } 6407 6408 int hclge_rm_uc_addr_common(struct hclge_vport *vport, 6409 const unsigned char *addr) 6410 { 6411 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6412 struct hclge_dev *hdev = vport->back; 6413 struct hclge_mac_vlan_tbl_entry_cmd req; 6414 int ret; 6415 6416 /* mac addr check */ 6417 if (is_zero_ether_addr(addr) || 6418 is_broadcast_ether_addr(addr) || 6419 is_multicast_ether_addr(addr)) { 6420 hnae3_format_mac_addr(format_mac_addr, addr); 6421 dev_dbg(&hdev->pdev->dev, "Remove mac err! invalid mac:%s.\n", 6422 format_mac_addr); 6423 return -EINVAL; 6424 } 6425 6426 memset(&req, 0, sizeof(req)); 6427 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); 6428 hclge_prepare_mac_addr(&req, addr, false); 6429 ret = hclge_remove_mac_vlan_tbl(vport, &req); 6430 if (!ret || ret == -ENOENT) { 6431 mutex_lock(&hdev->vport_lock); 6432 hclge_update_umv_space(vport, true); 6433 mutex_unlock(&hdev->vport_lock); 6434 return 0; 6435 } 6436 6437 return ret; 6438 } 6439 6440 static int hclge_add_mc_addr(struct hnae3_handle *handle, 6441 const unsigned char *addr) 6442 { 6443 struct hclge_vport *vport = hclge_get_vport(handle); 6444 6445 return hclge_update_mac_list(vport, HCLGE_MAC_TO_ADD, HCLGE_MAC_ADDR_MC, 6446 addr); 6447 } 6448 6449 int hclge_add_mc_addr_common(struct hclge_vport *vport, 6450 const unsigned char *addr) 6451 { 6452 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6453 struct hclge_dev *hdev = vport->back; 6454 struct hclge_mac_vlan_tbl_entry_cmd req; 6455 struct hclge_desc desc[3]; 6456 bool is_new_addr = false; 6457 int status; 6458 6459 /* mac addr check */ 6460 if (!is_multicast_ether_addr(addr)) { 6461 hnae3_format_mac_addr(format_mac_addr, addr); 6462 dev_err(&hdev->pdev->dev, 6463 "Add mc mac err! invalid mac:%s.\n", 6464 format_mac_addr); 6465 return -EINVAL; 6466 } 6467 memset(&req, 0, sizeof(req)); 6468 hclge_prepare_mac_addr(&req, addr, true); 6469 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 6470 if (status) { 6471 if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) && 6472 hdev->used_mc_mac_num >= 6473 hdev->ae_dev->dev_specs.mc_mac_size) 6474 goto err_no_space; 6475 6476 is_new_addr = true; 6477 6478 /* This mac addr do not exist, add new entry for it */ 6479 memset(desc[0].data, 0, sizeof(desc[0].data)); 6480 memset(desc[1].data, 0, sizeof(desc[0].data)); 6481 memset(desc[2].data, 0, sizeof(desc[0].data)); 6482 } 6483 status = hclge_update_desc_vfid(desc, vport->vport_id, false); 6484 if (status) 6485 return status; 6486 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 6487 if (status == -ENOSPC) 6488 goto err_no_space; 6489 else if (!status && is_new_addr) 6490 hdev->used_mc_mac_num++; 6491 6492 return status; 6493 6494 err_no_space: 6495 /* if already overflow, not to print each time */ 6496 if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) { 6497 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 6498 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n"); 6499 } 6500 6501 return -ENOSPC; 6502 } 6503 6504 static int hclge_rm_mc_addr(struct hnae3_handle *handle, 6505 const unsigned char *addr) 6506 { 6507 struct hclge_vport *vport = hclge_get_vport(handle); 6508 6509 return hclge_update_mac_list(vport, HCLGE_MAC_TO_DEL, HCLGE_MAC_ADDR_MC, 6510 addr); 6511 } 6512 6513 int hclge_rm_mc_addr_common(struct hclge_vport *vport, 6514 const unsigned char *addr) 6515 { 6516 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6517 struct hclge_dev *hdev = vport->back; 6518 struct hclge_mac_vlan_tbl_entry_cmd req; 6519 enum hclge_comm_cmd_status status; 6520 struct hclge_desc desc[3]; 6521 6522 /* mac addr check */ 6523 if (!is_multicast_ether_addr(addr)) { 6524 hnae3_format_mac_addr(format_mac_addr, addr); 6525 dev_dbg(&hdev->pdev->dev, 6526 "Remove mc mac err! invalid mac:%s.\n", 6527 format_mac_addr); 6528 return -EINVAL; 6529 } 6530 6531 memset(&req, 0, sizeof(req)); 6532 hclge_prepare_mac_addr(&req, addr, true); 6533 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); 6534 if (!status) { 6535 /* This mac addr exist, remove this handle's VFID for it */ 6536 status = hclge_update_desc_vfid(desc, vport->vport_id, true); 6537 if (status) 6538 return status; 6539 6540 if (hclge_is_all_function_id_zero(desc)) { 6541 /* All the vfid is zero, so need to delete this entry */ 6542 status = hclge_remove_mac_vlan_tbl(vport, &req); 6543 if (!status) 6544 hdev->used_mc_mac_num--; 6545 } else { 6546 /* Not all the vfid is zero, update the vfid */ 6547 status = hclge_add_mac_vlan_tbl(vport, &req, desc); 6548 } 6549 } else if (status == -ENOENT) { 6550 status = 0; 6551 } 6552 6553 return status; 6554 } 6555 6556 static void hclge_sync_vport_mac_list(struct hclge_vport *vport, 6557 struct list_head *list, 6558 enum HCLGE_MAC_ADDR_TYPE mac_type) 6559 { 6560 int (*sync)(struct hclge_vport *vport, const unsigned char *addr); 6561 struct hclge_mac_node *mac_node, *tmp; 6562 int ret; 6563 6564 if (mac_type == HCLGE_MAC_ADDR_UC) 6565 sync = hclge_add_uc_addr_common; 6566 else 6567 sync = hclge_add_mc_addr_common; 6568 6569 list_for_each_entry_safe(mac_node, tmp, list, node) { 6570 ret = sync(vport, mac_node->mac_addr); 6571 if (!ret) { 6572 mac_node->state = HCLGE_MAC_ACTIVE; 6573 } else { 6574 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 6575 &vport->state); 6576 6577 /* If one unicast mac address is existing in hardware, 6578 * we need to try whether other unicast mac addresses 6579 * are new addresses that can be added. 6580 * Multicast mac address can be reusable, even though 6581 * there is no space to add new multicast mac address, 6582 * we should check whether other mac addresses are 6583 * existing in hardware for reuse. 6584 */ 6585 if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) || 6586 (mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC)) 6587 break; 6588 } 6589 } 6590 } 6591 6592 static void hclge_unsync_vport_mac_list(struct hclge_vport *vport, 6593 struct list_head *list, 6594 enum HCLGE_MAC_ADDR_TYPE mac_type) 6595 { 6596 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 6597 struct hclge_mac_node *mac_node, *tmp; 6598 int ret; 6599 6600 if (mac_type == HCLGE_MAC_ADDR_UC) 6601 unsync = hclge_rm_uc_addr_common; 6602 else 6603 unsync = hclge_rm_mc_addr_common; 6604 6605 list_for_each_entry_safe(mac_node, tmp, list, node) { 6606 ret = unsync(vport, mac_node->mac_addr); 6607 if (!ret || ret == -ENOENT) { 6608 list_del(&mac_node->node); 6609 kfree(mac_node); 6610 } else { 6611 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, 6612 &vport->state); 6613 break; 6614 } 6615 } 6616 } 6617 6618 static bool hclge_sync_from_add_list(struct list_head *add_list, 6619 struct list_head *mac_list) 6620 { 6621 struct hclge_mac_node *mac_node, *tmp, *new_node; 6622 bool all_added = true; 6623 6624 list_for_each_entry_safe(mac_node, tmp, add_list, node) { 6625 if (mac_node->state == HCLGE_MAC_TO_ADD) 6626 all_added = false; 6627 6628 /* if the mac address from tmp_add_list is not in the 6629 * uc/mc_mac_list, it means have received a TO_DEL request 6630 * during the time window of adding the mac address into mac 6631 * table. if mac_node state is ACTIVE, then change it to TO_DEL, 6632 * then it will be removed at next time. else it must be TO_ADD, 6633 * this address hasn't been added into mac table, 6634 * so just remove the mac node. 6635 */ 6636 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 6637 if (new_node) { 6638 hclge_update_mac_node(new_node, mac_node->state); 6639 list_del(&mac_node->node); 6640 kfree(mac_node); 6641 } else if (mac_node->state == HCLGE_MAC_ACTIVE) { 6642 mac_node->state = HCLGE_MAC_TO_DEL; 6643 list_move_tail(&mac_node->node, mac_list); 6644 } else { 6645 list_del(&mac_node->node); 6646 kfree(mac_node); 6647 } 6648 } 6649 6650 return all_added; 6651 } 6652 6653 static void hclge_sync_from_del_list(struct list_head *del_list, 6654 struct list_head *mac_list) 6655 { 6656 struct hclge_mac_node *mac_node, *tmp, *new_node; 6657 6658 list_for_each_entry_safe(mac_node, tmp, del_list, node) { 6659 new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr); 6660 if (new_node) { 6661 /* If the mac addr exists in the mac list, it means 6662 * received a new TO_ADD request during the time window 6663 * of configuring the mac address. For the mac node 6664 * state is TO_ADD, and the address is already in the 6665 * in the hardware(due to delete fail), so we just need 6666 * to change the mac node state to ACTIVE. 6667 */ 6668 new_node->state = HCLGE_MAC_ACTIVE; 6669 list_del(&mac_node->node); 6670 kfree(mac_node); 6671 } else { 6672 list_move_tail(&mac_node->node, mac_list); 6673 } 6674 } 6675 } 6676 6677 static void hclge_update_overflow_flags(struct hclge_vport *vport, 6678 enum HCLGE_MAC_ADDR_TYPE mac_type, 6679 bool is_all_added) 6680 { 6681 if (mac_type == HCLGE_MAC_ADDR_UC) { 6682 if (is_all_added) 6683 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_UPE; 6684 else if (hclge_is_umv_space_full(vport, true)) 6685 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_UPE; 6686 } else { 6687 if (is_all_added) 6688 vport->overflow_promisc_flags &= ~HNAE3_OVERFLOW_MPE; 6689 else 6690 vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE; 6691 } 6692 } 6693 6694 static void hclge_sync_vport_mac_table(struct hclge_vport *vport, 6695 enum HCLGE_MAC_ADDR_TYPE mac_type) 6696 { 6697 struct hclge_mac_node *mac_node, *tmp, *new_node; 6698 struct list_head tmp_add_list, tmp_del_list; 6699 struct list_head *list; 6700 bool all_added; 6701 6702 INIT_LIST_HEAD(&tmp_add_list); 6703 INIT_LIST_HEAD(&tmp_del_list); 6704 6705 /* move the mac addr to the tmp_add_list and tmp_del_list, then 6706 * we can add/delete these mac addr outside the spin lock 6707 */ 6708 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6709 &vport->uc_mac_list : &vport->mc_mac_list; 6710 6711 spin_lock_bh(&vport->mac_list_lock); 6712 6713 list_for_each_entry_safe(mac_node, tmp, list, node) { 6714 switch (mac_node->state) { 6715 case HCLGE_MAC_TO_DEL: 6716 list_move_tail(&mac_node->node, &tmp_del_list); 6717 break; 6718 case HCLGE_MAC_TO_ADD: 6719 new_node = kzalloc_obj(*new_node, GFP_ATOMIC); 6720 if (!new_node) 6721 goto stop_traverse; 6722 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr); 6723 new_node->state = mac_node->state; 6724 list_add_tail(&new_node->node, &tmp_add_list); 6725 break; 6726 default: 6727 break; 6728 } 6729 } 6730 6731 stop_traverse: 6732 spin_unlock_bh(&vport->mac_list_lock); 6733 6734 /* delete first, in order to get max mac table space for adding */ 6735 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 6736 hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type); 6737 6738 /* if some mac addresses were added/deleted fail, move back to the 6739 * mac_list, and retry at next time. 6740 */ 6741 spin_lock_bh(&vport->mac_list_lock); 6742 6743 hclge_sync_from_del_list(&tmp_del_list, list); 6744 all_added = hclge_sync_from_add_list(&tmp_add_list, list); 6745 6746 spin_unlock_bh(&vport->mac_list_lock); 6747 6748 hclge_update_overflow_flags(vport, mac_type, all_added); 6749 } 6750 6751 static bool hclge_need_sync_mac_table(struct hclge_vport *vport) 6752 { 6753 struct hclge_dev *hdev = vport->back; 6754 6755 if (test_bit(vport->vport_id, hdev->vport_config_block)) 6756 return false; 6757 6758 if (test_and_clear_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state)) 6759 return true; 6760 6761 return false; 6762 } 6763 6764 static void hclge_sync_mac_table(struct hclge_dev *hdev) 6765 { 6766 int i; 6767 6768 for (i = 0; i < hdev->num_alloc_vport; i++) { 6769 struct hclge_vport *vport = &hdev->vport[i]; 6770 6771 if (!hclge_need_sync_mac_table(vport)) 6772 continue; 6773 6774 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_UC); 6775 hclge_sync_vport_mac_table(vport, HCLGE_MAC_ADDR_MC); 6776 } 6777 } 6778 6779 static void hclge_build_del_list(struct list_head *list, 6780 bool is_del_list, 6781 struct list_head *tmp_del_list) 6782 { 6783 struct hclge_mac_node *mac_cfg, *tmp; 6784 6785 list_for_each_entry_safe(mac_cfg, tmp, list, node) { 6786 switch (mac_cfg->state) { 6787 case HCLGE_MAC_TO_DEL: 6788 case HCLGE_MAC_ACTIVE: 6789 list_move_tail(&mac_cfg->node, tmp_del_list); 6790 break; 6791 case HCLGE_MAC_TO_ADD: 6792 if (is_del_list) { 6793 list_del(&mac_cfg->node); 6794 kfree(mac_cfg); 6795 } 6796 break; 6797 } 6798 } 6799 } 6800 6801 static void hclge_unsync_del_list(struct hclge_vport *vport, 6802 int (*unsync)(struct hclge_vport *vport, 6803 const unsigned char *addr), 6804 bool is_del_list, 6805 struct list_head *tmp_del_list) 6806 { 6807 struct hclge_mac_node *mac_cfg, *tmp; 6808 int ret; 6809 6810 list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) { 6811 ret = unsync(vport, mac_cfg->mac_addr); 6812 if (!ret || ret == -ENOENT) { 6813 /* clear all mac addr from hardware, but remain these 6814 * mac addr in the mac list, and restore them after 6815 * vf reset finished. 6816 */ 6817 if (!is_del_list && 6818 mac_cfg->state == HCLGE_MAC_ACTIVE) { 6819 mac_cfg->state = HCLGE_MAC_TO_ADD; 6820 } else { 6821 list_del(&mac_cfg->node); 6822 kfree(mac_cfg); 6823 } 6824 } else if (is_del_list) { 6825 mac_cfg->state = HCLGE_MAC_TO_DEL; 6826 } 6827 } 6828 } 6829 6830 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, 6831 enum HCLGE_MAC_ADDR_TYPE mac_type) 6832 { 6833 int (*unsync)(struct hclge_vport *vport, const unsigned char *addr); 6834 struct hclge_dev *hdev = vport->back; 6835 struct list_head tmp_del_list, *list; 6836 6837 if (mac_type == HCLGE_MAC_ADDR_UC) { 6838 list = &vport->uc_mac_list; 6839 unsync = hclge_rm_uc_addr_common; 6840 } else { 6841 list = &vport->mc_mac_list; 6842 unsync = hclge_rm_mc_addr_common; 6843 } 6844 6845 INIT_LIST_HEAD(&tmp_del_list); 6846 6847 if (!is_del_list) 6848 set_bit(vport->vport_id, hdev->vport_config_block); 6849 6850 spin_lock_bh(&vport->mac_list_lock); 6851 6852 hclge_build_del_list(list, is_del_list, &tmp_del_list); 6853 6854 spin_unlock_bh(&vport->mac_list_lock); 6855 6856 hclge_unsync_del_list(vport, unsync, is_del_list, &tmp_del_list); 6857 6858 spin_lock_bh(&vport->mac_list_lock); 6859 6860 hclge_sync_from_del_list(&tmp_del_list, list); 6861 6862 spin_unlock_bh(&vport->mac_list_lock); 6863 } 6864 6865 /* remove all mac address when uninitailize */ 6866 static void hclge_uninit_vport_mac_list(struct hclge_vport *vport, 6867 enum HCLGE_MAC_ADDR_TYPE mac_type) 6868 { 6869 struct hclge_mac_node *mac_node, *tmp; 6870 struct hclge_dev *hdev = vport->back; 6871 struct list_head tmp_del_list, *list; 6872 6873 INIT_LIST_HEAD(&tmp_del_list); 6874 6875 list = (mac_type == HCLGE_MAC_ADDR_UC) ? 6876 &vport->uc_mac_list : &vport->mc_mac_list; 6877 6878 spin_lock_bh(&vport->mac_list_lock); 6879 6880 list_for_each_entry_safe(mac_node, tmp, list, node) { 6881 switch (mac_node->state) { 6882 case HCLGE_MAC_TO_DEL: 6883 case HCLGE_MAC_ACTIVE: 6884 list_move_tail(&mac_node->node, &tmp_del_list); 6885 break; 6886 case HCLGE_MAC_TO_ADD: 6887 list_del(&mac_node->node); 6888 kfree(mac_node); 6889 break; 6890 } 6891 } 6892 6893 spin_unlock_bh(&vport->mac_list_lock); 6894 6895 hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type); 6896 6897 if (!list_empty(&tmp_del_list)) 6898 dev_warn(&hdev->pdev->dev, 6899 "uninit %s mac list for vport %u not completely.\n", 6900 mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc", 6901 vport->vport_id); 6902 6903 list_for_each_entry_safe(mac_node, tmp, &tmp_del_list, node) { 6904 list_del(&mac_node->node); 6905 kfree(mac_node); 6906 } 6907 } 6908 6909 static void hclge_uninit_mac_table(struct hclge_dev *hdev) 6910 { 6911 struct hclge_vport *vport; 6912 int i; 6913 6914 for (i = 0; i < hdev->num_alloc_vport; i++) { 6915 vport = &hdev->vport[i]; 6916 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_UC); 6917 hclge_uninit_vport_mac_list(vport, HCLGE_MAC_ADDR_MC); 6918 } 6919 } 6920 6921 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, 6922 u16 cmdq_resp, u8 resp_code) 6923 { 6924 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 6925 #define HCLGE_ETHERTYPE_ALREADY_ADD 1 6926 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 6927 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 6928 6929 int return_status; 6930 6931 if (cmdq_resp) { 6932 dev_err(&hdev->pdev->dev, 6933 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 6934 cmdq_resp); 6935 return -EIO; 6936 } 6937 6938 switch (resp_code) { 6939 case HCLGE_ETHERTYPE_SUCCESS_ADD: 6940 case HCLGE_ETHERTYPE_ALREADY_ADD: 6941 return_status = 0; 6942 break; 6943 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: 6944 dev_err(&hdev->pdev->dev, 6945 "add mac ethertype failed for manager table overflow.\n"); 6946 return_status = -EIO; 6947 break; 6948 case HCLGE_ETHERTYPE_KEY_CONFLICT: 6949 dev_err(&hdev->pdev->dev, 6950 "add mac ethertype failed for key conflict.\n"); 6951 return_status = -EIO; 6952 break; 6953 default: 6954 dev_err(&hdev->pdev->dev, 6955 "add mac ethertype failed for undefined, code=%u.\n", 6956 resp_code); 6957 return_status = -EIO; 6958 } 6959 6960 return return_status; 6961 } 6962 6963 static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf, 6964 u8 *mac_addr) 6965 { 6966 struct hclge_vport *vport = hclge_get_vport(handle); 6967 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 6968 struct hclge_dev *hdev = vport->back; 6969 6970 vport = hclge_get_vf_vport(hdev, vf); 6971 if (!vport) 6972 return -EINVAL; 6973 6974 hnae3_format_mac_addr(format_mac_addr, mac_addr); 6975 if (ether_addr_equal(mac_addr, vport->vf_info.mac)) { 6976 dev_info(&hdev->pdev->dev, 6977 "Specified MAC(=%s) is same as before, no change committed!\n", 6978 format_mac_addr); 6979 return 0; 6980 } 6981 6982 ether_addr_copy(vport->vf_info.mac, mac_addr); 6983 6984 /* there is a timewindow for PF to know VF unalive, it may 6985 * cause send mailbox fail, but it doesn't matter, VF will 6986 * query it when reinit. 6987 */ 6988 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) { 6989 dev_info(&hdev->pdev->dev, 6990 "MAC of VF %d has been set to %s, and it will be reinitialized!\n", 6991 vf, format_mac_addr); 6992 (void)hclge_inform_reset_assert_to_vf(vport); 6993 return 0; 6994 } 6995 6996 dev_info(&hdev->pdev->dev, 6997 "MAC of VF %d has been set to %s, will be active after VF reset\n", 6998 vf, format_mac_addr); 6999 return 0; 7000 } 7001 7002 static int hclge_add_mgr_tbl(struct hclge_dev *hdev, 7003 const struct hclge_mac_mgr_tbl_entry_cmd *req) 7004 { 7005 struct hclge_desc desc; 7006 u8 resp_code; 7007 u16 retval; 7008 int ret; 7009 7010 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); 7011 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); 7012 7013 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7014 if (ret) { 7015 dev_err(&hdev->pdev->dev, 7016 "add mac ethertype failed for cmd_send, ret =%d.\n", 7017 ret); 7018 return ret; 7019 } 7020 7021 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; 7022 retval = le16_to_cpu(desc.retval); 7023 7024 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); 7025 } 7026 7027 static int init_mgr_tbl(struct hclge_dev *hdev) 7028 { 7029 int ret; 7030 u32 i; 7031 7032 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { 7033 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); 7034 if (ret) { 7035 dev_err(&hdev->pdev->dev, 7036 "add mac ethertype failed, ret =%d.\n", 7037 ret); 7038 return ret; 7039 } 7040 } 7041 7042 return 0; 7043 } 7044 7045 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) 7046 { 7047 struct hclge_vport *vport = hclge_get_vport(handle); 7048 struct hclge_dev *hdev = vport->back; 7049 7050 ether_addr_copy(p, hdev->hw.mac.mac_addr); 7051 } 7052 7053 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, 7054 const u8 *old_addr, const u8 *new_addr) 7055 { 7056 struct list_head *list = &vport->uc_mac_list; 7057 struct hclge_mac_node *old_node, *new_node; 7058 7059 new_node = hclge_find_mac_node(list, new_addr); 7060 if (!new_node) { 7061 new_node = kzalloc_obj(*new_node, GFP_ATOMIC); 7062 if (!new_node) 7063 return -ENOMEM; 7064 7065 new_node->state = HCLGE_MAC_TO_ADD; 7066 ether_addr_copy(new_node->mac_addr, new_addr); 7067 list_add(&new_node->node, list); 7068 } else { 7069 if (new_node->state == HCLGE_MAC_TO_DEL) 7070 new_node->state = HCLGE_MAC_ACTIVE; 7071 7072 /* make sure the new addr is in the list head, avoid dev 7073 * addr may be not re-added into mac table for the umv space 7074 * limitation after global/imp reset which will clear mac 7075 * table by hardware. 7076 */ 7077 list_move(&new_node->node, list); 7078 } 7079 7080 if (old_addr && !ether_addr_equal(old_addr, new_addr)) { 7081 old_node = hclge_find_mac_node(list, old_addr); 7082 if (old_node) { 7083 if (old_node->state == HCLGE_MAC_TO_ADD) { 7084 list_del(&old_node->node); 7085 kfree(old_node); 7086 } else { 7087 old_node->state = HCLGE_MAC_TO_DEL; 7088 } 7089 } 7090 } 7091 7092 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 7093 7094 return 0; 7095 } 7096 7097 static int hclge_set_mac_addr(struct hnae3_handle *handle, const void *p, 7098 bool is_first) 7099 { 7100 const unsigned char *new_addr = (const unsigned char *)p; 7101 struct hclge_vport *vport = hclge_get_vport(handle); 7102 char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN]; 7103 struct hclge_dev *hdev = vport->back; 7104 unsigned char *old_addr = NULL; 7105 int ret; 7106 7107 /* mac addr check */ 7108 if (is_zero_ether_addr(new_addr) || 7109 is_broadcast_ether_addr(new_addr) || 7110 is_multicast_ether_addr(new_addr)) { 7111 hnae3_format_mac_addr(format_mac_addr, new_addr); 7112 dev_err(&hdev->pdev->dev, 7113 "change uc mac err! invalid mac: %s.\n", 7114 format_mac_addr); 7115 return -EINVAL; 7116 } 7117 7118 ret = hclge_pause_addr_cfg(hdev, new_addr); 7119 if (ret) { 7120 dev_err(&hdev->pdev->dev, 7121 "failed to configure mac pause address, ret = %d\n", 7122 ret); 7123 return ret; 7124 } 7125 7126 if (!is_first) 7127 old_addr = hdev->hw.mac.mac_addr; 7128 7129 spin_lock_bh(&vport->mac_list_lock); 7130 ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr); 7131 if (ret) { 7132 hnae3_format_mac_addr(format_mac_addr, new_addr); 7133 dev_err(&hdev->pdev->dev, 7134 "failed to change the mac addr:%s, ret = %d\n", 7135 format_mac_addr, ret); 7136 spin_unlock_bh(&vport->mac_list_lock); 7137 7138 if (!is_first) 7139 hclge_pause_addr_cfg(hdev, old_addr); 7140 7141 return ret; 7142 } 7143 /* we must update dev addr with spin lock protect, preventing dev addr 7144 * being removed by set_rx_mode path. 7145 */ 7146 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); 7147 spin_unlock_bh(&vport->mac_list_lock); 7148 7149 hclge_task_schedule(hdev, 0); 7150 7151 return 0; 7152 } 7153 7154 static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd) 7155 { 7156 struct mii_ioctl_data *data = if_mii(ifr); 7157 7158 if (!hnae3_dev_phy_imp_supported(hdev)) 7159 return -EOPNOTSUPP; 7160 7161 switch (cmd) { 7162 case SIOCGMIIPHY: 7163 data->phy_id = hdev->hw.mac.phy_addr; 7164 /* this command reads phy id and register at the same time */ 7165 fallthrough; 7166 case SIOCGMIIREG: 7167 return hclge_read_phy_reg(hdev, data->reg_num, &data->val_out); 7168 7169 case SIOCSMIIREG: 7170 return hclge_write_phy_reg(hdev, data->reg_num, data->val_in); 7171 default: 7172 return -EOPNOTSUPP; 7173 } 7174 } 7175 7176 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr, 7177 int cmd) 7178 { 7179 struct hclge_vport *vport = hclge_get_vport(handle); 7180 struct hclge_dev *hdev = vport->back; 7181 7182 if (!hdev->hw.mac.phydev) 7183 return hclge_mii_ioctl(hdev, ifr, cmd); 7184 7185 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd); 7186 } 7187 7188 static int hclge_set_port_vlan_filter_bypass(struct hclge_dev *hdev, u8 vf_id, 7189 bool bypass_en) 7190 { 7191 struct hclge_port_vlan_filter_bypass_cmd *req; 7192 struct hclge_desc desc; 7193 int ret; 7194 7195 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, false); 7196 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 7197 req->vf_id = vf_id; 7198 hnae3_set_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B, 7199 bypass_en ? 1 : 0); 7200 7201 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7202 if (ret) 7203 dev_err(&hdev->pdev->dev, 7204 "failed to set vport%u port vlan filter bypass state, ret = %d.\n", 7205 vf_id, ret); 7206 7207 return ret; 7208 } 7209 7210 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, 7211 u8 fe_type, bool filter_en, u8 vf_id) 7212 { 7213 struct hclge_vlan_filter_ctrl_cmd *req; 7214 struct hclge_desc desc; 7215 int ret; 7216 7217 /* read current vlan filter parameter */ 7218 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 7219 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 7220 req->vlan_type = vlan_type; 7221 req->vf_id = vf_id; 7222 7223 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7224 if (ret) { 7225 dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n", 7226 vf_id, ret); 7227 return ret; 7228 } 7229 7230 /* modify and write new config parameter */ 7231 hclge_comm_cmd_reuse_desc(&desc, false); 7232 req->vlan_fe = filter_en ? 7233 (req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type); 7234 7235 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7236 if (ret) 7237 dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n", 7238 vf_id, ret); 7239 7240 return ret; 7241 } 7242 7243 static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable) 7244 { 7245 struct hclge_dev *hdev = vport->back; 7246 struct hnae3_ae_dev *ae_dev = hdev->ae_dev; 7247 int ret; 7248 7249 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 7250 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7251 HCLGE_FILTER_FE_EGRESS_V1_B, 7252 enable, vport->vport_id); 7253 7254 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7255 HCLGE_FILTER_FE_EGRESS, enable, 7256 vport->vport_id); 7257 if (ret) 7258 return ret; 7259 7260 if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) { 7261 ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id, 7262 !enable); 7263 } else if (!vport->vport_id) { 7264 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps)) 7265 enable = false; 7266 7267 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 7268 HCLGE_FILTER_FE_INGRESS, 7269 enable, 0); 7270 } 7271 7272 return ret; 7273 } 7274 7275 static bool hclge_need_enable_vport_vlan_filter(struct hclge_vport *vport) 7276 { 7277 struct hnae3_handle *handle = &vport->nic; 7278 struct hclge_vport_vlan_cfg *vlan, *tmp; 7279 struct hclge_dev *hdev = vport->back; 7280 7281 if (vport->vport_id) { 7282 if (vport->port_base_vlan_cfg.state != 7283 HNAE3_PORT_BASE_VLAN_DISABLE) 7284 return true; 7285 7286 if (vport->vf_info.trusted && vport->vf_info.request_uc_en) 7287 return false; 7288 } else if (handle->netdev_flags & HNAE3_USER_UPE) { 7289 return false; 7290 } 7291 7292 if (!vport->req_vlan_fltr_en) 7293 return false; 7294 7295 /* compatible with former device, always enable vlan filter */ 7296 if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 7297 return true; 7298 7299 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) 7300 if (vlan->vlan_id != 0) 7301 return true; 7302 7303 return false; 7304 } 7305 7306 static int __hclge_enable_vport_vlan_filter(struct hclge_vport *vport, 7307 bool request_en) 7308 { 7309 bool need_en; 7310 int ret; 7311 7312 need_en = hclge_need_enable_vport_vlan_filter(vport); 7313 if (need_en == vport->cur_vlan_fltr_en) 7314 return 0; 7315 7316 ret = hclge_set_vport_vlan_filter(vport, need_en); 7317 if (ret) 7318 return ret; 7319 7320 vport->cur_vlan_fltr_en = need_en; 7321 7322 return 0; 7323 } 7324 7325 int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en) 7326 { 7327 struct hclge_dev *hdev = vport->back; 7328 int ret; 7329 7330 mutex_lock(&hdev->vport_lock); 7331 vport->req_vlan_fltr_en = request_en; 7332 ret = __hclge_enable_vport_vlan_filter(vport, request_en); 7333 mutex_unlock(&hdev->vport_lock); 7334 7335 return ret; 7336 } 7337 7338 static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) 7339 { 7340 struct hclge_vport *vport = hclge_get_vport(handle); 7341 7342 return hclge_enable_vport_vlan_filter(vport, enable); 7343 } 7344 7345 static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid, 7346 bool is_kill, u16 vlan, 7347 struct hclge_desc *desc) 7348 { 7349 struct hclge_vlan_filter_vf_cfg_cmd *req0; 7350 struct hclge_vlan_filter_vf_cfg_cmd *req1; 7351 u8 vf_byte_val; 7352 u8 vf_byte_off; 7353 int ret; 7354 7355 hclge_cmd_setup_basic_desc(&desc[0], 7356 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 7357 hclge_cmd_setup_basic_desc(&desc[1], 7358 HCLGE_OPC_VLAN_FILTER_VF_CFG, false); 7359 7360 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 7361 7362 vf_byte_off = vfid / 8; 7363 vf_byte_val = 1 << (vfid % 8); 7364 7365 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 7366 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; 7367 7368 req0->vlan_id = cpu_to_le16(vlan); 7369 req0->vlan_cfg = is_kill; 7370 7371 if (vf_byte_off < HCLGE_MAX_VF_BYTES) 7372 req0->vf_bitmap[vf_byte_off] = vf_byte_val; 7373 else 7374 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; 7375 7376 ret = hclge_cmd_send(&hdev->hw, desc, 2); 7377 if (ret) { 7378 dev_err(&hdev->pdev->dev, 7379 "Send vf vlan command fail, ret =%d.\n", 7380 ret); 7381 return ret; 7382 } 7383 7384 return 0; 7385 } 7386 7387 static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid, 7388 bool is_kill, struct hclge_desc *desc) 7389 { 7390 struct hclge_vlan_filter_vf_cfg_cmd *req; 7391 7392 req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; 7393 7394 if (!is_kill) { 7395 #define HCLGE_VF_VLAN_NO_ENTRY 2 7396 if (!req->resp_code || req->resp_code == 1) 7397 return 0; 7398 7399 if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { 7400 set_bit(vfid, hdev->vf_vlan_full); 7401 dev_warn(&hdev->pdev->dev, 7402 "vf vlan table is full, vf vlan filter is disabled\n"); 7403 return 0; 7404 } 7405 7406 dev_err(&hdev->pdev->dev, 7407 "Add vf vlan filter fail, ret =%u.\n", 7408 req->resp_code); 7409 } else { 7410 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1 7411 if (!req->resp_code) 7412 return 0; 7413 7414 /* vf vlan filter is disabled when vf vlan table is full, 7415 * then new vlan id will not be added into vf vlan table. 7416 * Just return 0 without warning, avoid massive verbose 7417 * print logs when unload. 7418 */ 7419 if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) 7420 return 0; 7421 7422 dev_err(&hdev->pdev->dev, 7423 "Kill vf vlan filter fail, ret =%u.\n", 7424 req->resp_code); 7425 } 7426 7427 return -EIO; 7428 } 7429 7430 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid, 7431 bool is_kill, u16 vlan) 7432 { 7433 struct hclge_vport *vport = &hdev->vport[vfid]; 7434 struct hclge_desc desc[2]; 7435 int ret; 7436 7437 /* if vf vlan table is full, firmware will close vf vlan filter, it 7438 * is unable and unnecessary to add new vlan id to vf vlan filter. 7439 * If spoof check is enable, and vf vlan is full, it shouldn't add 7440 * new vlan, because tx packets with these vlan id will be dropped. 7441 */ 7442 if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) { 7443 if (vport->vf_info.spoofchk && vlan) { 7444 dev_err(&hdev->pdev->dev, 7445 "Can't add vlan due to spoof check is on and vf vlan table is full\n"); 7446 return -EPERM; 7447 } 7448 return 0; 7449 } 7450 7451 ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc); 7452 if (ret) 7453 return ret; 7454 7455 return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc); 7456 } 7457 7458 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, 7459 u16 vlan_id, bool is_kill) 7460 { 7461 struct hclge_vlan_filter_pf_cfg_cmd *req; 7462 struct hclge_desc desc; 7463 u8 vlan_offset_byte_val; 7464 u8 vlan_offset_byte; 7465 u8 vlan_offset_160; 7466 int ret; 7467 7468 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); 7469 7470 vlan_offset_160 = vlan_id / HCLGE_VLAN_ID_OFFSET_STEP; 7471 vlan_offset_byte = (vlan_id % HCLGE_VLAN_ID_OFFSET_STEP) / 7472 HCLGE_VLAN_BYTE_SIZE; 7473 vlan_offset_byte_val = 1 << (vlan_id % HCLGE_VLAN_BYTE_SIZE); 7474 7475 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; 7476 req->vlan_offset = vlan_offset_160; 7477 req->vlan_cfg = is_kill; 7478 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 7479 7480 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 7481 if (ret) 7482 dev_err(&hdev->pdev->dev, 7483 "port vlan command, send fail, ret =%d.\n", ret); 7484 return ret; 7485 } 7486 7487 static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id, 7488 u16 vlan_id, bool is_kill) 7489 { 7490 /* vlan 0 may be added twice when 8021q module is enabled */ 7491 if (!is_kill && !vlan_id && 7492 test_bit(vport_id, hdev->vlan_table[vlan_id])) 7493 return false; 7494 7495 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { 7496 dev_warn(&hdev->pdev->dev, 7497 "Add port vlan failed, vport %u is already in vlan %u\n", 7498 vport_id, vlan_id); 7499 return false; 7500 } 7501 7502 if (is_kill && 7503 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { 7504 dev_warn(&hdev->pdev->dev, 7505 "Delete port vlan failed, vport %u is not in vlan %u\n", 7506 vport_id, vlan_id); 7507 return false; 7508 } 7509 7510 return true; 7511 } 7512 7513 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, 7514 u16 vport_id, u16 vlan_id, 7515 bool is_kill) 7516 { 7517 u16 vport_idx, vport_num = 0; 7518 int ret; 7519 7520 if (is_kill && !vlan_id) 7521 return 0; 7522 7523 if (vlan_id >= VLAN_N_VID) 7524 return -EINVAL; 7525 7526 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id); 7527 if (ret) { 7528 dev_err(&hdev->pdev->dev, 7529 "Set %u vport vlan filter config fail, ret =%d.\n", 7530 vport_id, ret); 7531 return ret; 7532 } 7533 7534 if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill)) 7535 return 0; 7536 7537 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM) 7538 vport_num++; 7539 7540 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) 7541 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, 7542 is_kill); 7543 7544 return ret; 7545 } 7546 7547 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) 7548 { 7549 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; 7550 struct hclge_vport_vtag_tx_cfg_cmd *req; 7551 struct hclge_dev *hdev = vport->back; 7552 struct hclge_desc desc; 7553 u16 bmap_index; 7554 int status; 7555 7556 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); 7557 7558 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 7559 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); 7560 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); 7561 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, 7562 vcfg->accept_tag1 ? 1 : 0); 7563 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, 7564 vcfg->accept_untag1 ? 1 : 0); 7565 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, 7566 vcfg->accept_tag2 ? 1 : 0); 7567 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, 7568 vcfg->accept_untag2 ? 1 : 0); 7569 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, 7570 vcfg->insert_tag1_en ? 1 : 0); 7571 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, 7572 vcfg->insert_tag2_en ? 1 : 0); 7573 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_TAG_SHIFT_MODE_EN_B, 7574 vcfg->tag_shift_mode_en ? 1 : 0); 7575 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); 7576 7577 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 7578 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 7579 HCLGE_VF_NUM_PER_BYTE; 7580 req->vf_bitmap[bmap_index] = 7581 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 7582 7583 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7584 if (status) 7585 dev_err(&hdev->pdev->dev, 7586 "Send port txvlan cfg command fail, ret =%d\n", 7587 status); 7588 7589 return status; 7590 } 7591 7592 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) 7593 { 7594 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; 7595 struct hclge_vport_vtag_rx_cfg_cmd *req; 7596 struct hclge_dev *hdev = vport->back; 7597 struct hclge_desc desc; 7598 u16 bmap_index; 7599 int status; 7600 7601 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); 7602 7603 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 7604 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, 7605 vcfg->strip_tag1_en ? 1 : 0); 7606 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, 7607 vcfg->strip_tag2_en ? 1 : 0); 7608 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, 7609 vcfg->vlan1_vlan_prionly ? 1 : 0); 7610 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, 7611 vcfg->vlan2_vlan_prionly ? 1 : 0); 7612 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG1_EN_B, 7613 vcfg->strip_tag1_discard_en ? 1 : 0); 7614 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_DISCARD_TAG2_EN_B, 7615 vcfg->strip_tag2_discard_en ? 1 : 0); 7616 7617 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; 7618 bmap_index = vport->vport_id % HCLGE_VF_NUM_PER_CMD / 7619 HCLGE_VF_NUM_PER_BYTE; 7620 req->vf_bitmap[bmap_index] = 7621 1U << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); 7622 7623 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7624 if (status) 7625 dev_err(&hdev->pdev->dev, 7626 "Send port rxvlan cfg command fail, ret =%d\n", 7627 status); 7628 7629 return status; 7630 } 7631 7632 static int hclge_vlan_offload_cfg(struct hclge_vport *vport, 7633 u16 port_base_vlan_state, 7634 u16 vlan_tag, u8 qos) 7635 { 7636 int ret; 7637 7638 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7639 vport->txvlan_cfg.accept_tag1 = true; 7640 vport->txvlan_cfg.insert_tag1_en = false; 7641 vport->txvlan_cfg.default_tag1 = 0; 7642 } else { 7643 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(vport->nic.pdev); 7644 7645 vport->txvlan_cfg.accept_tag1 = 7646 ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3; 7647 vport->txvlan_cfg.insert_tag1_en = true; 7648 vport->txvlan_cfg.default_tag1 = (qos << VLAN_PRIO_SHIFT) | 7649 vlan_tag; 7650 } 7651 7652 vport->txvlan_cfg.accept_untag1 = true; 7653 7654 /* accept_tag2 and accept_untag2 are not supported on 7655 * pdev revision(0x20), new revision support them, 7656 * this two fields can not be configured by user. 7657 */ 7658 vport->txvlan_cfg.accept_tag2 = true; 7659 vport->txvlan_cfg.accept_untag2 = true; 7660 vport->txvlan_cfg.insert_tag2_en = false; 7661 vport->txvlan_cfg.default_tag2 = 0; 7662 vport->txvlan_cfg.tag_shift_mode_en = true; 7663 7664 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7665 vport->rxvlan_cfg.strip_tag1_en = false; 7666 vport->rxvlan_cfg.strip_tag2_en = 7667 vport->rxvlan_cfg.rx_vlan_offload_en; 7668 vport->rxvlan_cfg.strip_tag2_discard_en = false; 7669 } else { 7670 vport->rxvlan_cfg.strip_tag1_en = 7671 vport->rxvlan_cfg.rx_vlan_offload_en; 7672 vport->rxvlan_cfg.strip_tag2_en = true; 7673 vport->rxvlan_cfg.strip_tag2_discard_en = true; 7674 } 7675 7676 vport->rxvlan_cfg.strip_tag1_discard_en = false; 7677 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 7678 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 7679 7680 ret = hclge_set_vlan_tx_offload_cfg(vport); 7681 if (ret) 7682 return ret; 7683 7684 return hclge_set_vlan_rx_offload_cfg(vport); 7685 } 7686 7687 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) 7688 { 7689 struct hclge_rx_vlan_type_cfg_cmd *rx_req; 7690 struct hclge_tx_vlan_type_cfg_cmd *tx_req; 7691 struct hclge_desc desc; 7692 int status; 7693 7694 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); 7695 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; 7696 rx_req->ot_fst_vlan_type = 7697 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); 7698 rx_req->ot_sec_vlan_type = 7699 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); 7700 rx_req->in_fst_vlan_type = 7701 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); 7702 rx_req->in_sec_vlan_type = 7703 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); 7704 7705 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7706 if (status) { 7707 dev_err(&hdev->pdev->dev, 7708 "Send rxvlan protocol type command fail, ret =%d\n", 7709 status); 7710 return status; 7711 } 7712 7713 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); 7714 7715 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data; 7716 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); 7717 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); 7718 7719 status = hclge_cmd_send(&hdev->hw, &desc, 1); 7720 if (status) 7721 dev_err(&hdev->pdev->dev, 7722 "Send txvlan protocol type command fail, ret =%d\n", 7723 status); 7724 7725 return status; 7726 } 7727 7728 static int hclge_init_vlan_filter(struct hclge_dev *hdev) 7729 { 7730 struct hclge_vport *vport; 7731 bool enable = true; 7732 int ret; 7733 int i; 7734 7735 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 7736 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7737 HCLGE_FILTER_FE_EGRESS_V1_B, 7738 true, 0); 7739 7740 /* for revision 0x21, vf vlan filter is per function */ 7741 for (i = 0; i < hdev->num_alloc_vport; i++) { 7742 vport = &hdev->vport[i]; 7743 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 7744 HCLGE_FILTER_FE_EGRESS, true, 7745 vport->vport_id); 7746 if (ret) 7747 return ret; 7748 vport->cur_vlan_fltr_en = true; 7749 } 7750 7751 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) && 7752 !test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 7753 enable = false; 7754 7755 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, 7756 HCLGE_FILTER_FE_INGRESS, enable, 0); 7757 } 7758 7759 static int hclge_init_vlan_type(struct hclge_dev *hdev) 7760 { 7761 hdev->vlan_type_cfg.rx_in_fst_vlan_type = ETH_P_8021Q; 7762 hdev->vlan_type_cfg.rx_in_sec_vlan_type = ETH_P_8021Q; 7763 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = ETH_P_8021Q; 7764 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = ETH_P_8021Q; 7765 hdev->vlan_type_cfg.tx_ot_vlan_type = ETH_P_8021Q; 7766 hdev->vlan_type_cfg.tx_in_vlan_type = ETH_P_8021Q; 7767 7768 return hclge_set_vlan_protocol_type(hdev); 7769 } 7770 7771 static int hclge_init_vport_vlan_offload(struct hclge_dev *hdev) 7772 { 7773 struct hclge_port_base_vlan_config *cfg; 7774 struct hclge_vport *vport; 7775 int ret; 7776 int i; 7777 7778 for (i = 0; i < hdev->num_alloc_vport; i++) { 7779 vport = &hdev->vport[i]; 7780 cfg = &vport->port_base_vlan_cfg; 7781 7782 ret = hclge_vlan_offload_cfg(vport, cfg->state, 7783 cfg->vlan_info.vlan_tag, 7784 cfg->vlan_info.qos); 7785 if (ret) 7786 return ret; 7787 } 7788 return 0; 7789 } 7790 7791 static int hclge_init_vlan_config(struct hclge_dev *hdev) 7792 { 7793 struct hnae3_handle *handle = &hdev->vport[0].nic; 7794 int ret; 7795 7796 ret = hclge_init_vlan_filter(hdev); 7797 if (ret) 7798 return ret; 7799 7800 ret = hclge_init_vlan_type(hdev); 7801 if (ret) 7802 return ret; 7803 7804 ret = hclge_init_vport_vlan_offload(hdev); 7805 if (ret) 7806 return ret; 7807 7808 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); 7809 } 7810 7811 static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 7812 bool writen_to_tbl) 7813 { 7814 struct hclge_vport_vlan_cfg *vlan, *tmp; 7815 struct hclge_dev *hdev = vport->back; 7816 7817 mutex_lock(&hdev->vport_lock); 7818 7819 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7820 if (vlan->vlan_id == vlan_id) { 7821 mutex_unlock(&hdev->vport_lock); 7822 return; 7823 } 7824 } 7825 7826 vlan = kzalloc_obj(*vlan); 7827 if (!vlan) { 7828 mutex_unlock(&hdev->vport_lock); 7829 return; 7830 } 7831 7832 vlan->hd_tbl_status = writen_to_tbl; 7833 vlan->vlan_id = vlan_id; 7834 7835 list_add_tail(&vlan->node, &vport->vlan_list); 7836 mutex_unlock(&hdev->vport_lock); 7837 } 7838 7839 static int hclge_add_vport_all_vlan_table(struct hclge_vport *vport) 7840 { 7841 struct hclge_vport_vlan_cfg *vlan, *tmp; 7842 struct hclge_dev *hdev = vport->back; 7843 int ret; 7844 7845 mutex_lock(&hdev->vport_lock); 7846 7847 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7848 if (!vlan->hd_tbl_status) { 7849 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7850 vport->vport_id, 7851 vlan->vlan_id, false); 7852 if (ret) { 7853 dev_err(&hdev->pdev->dev, 7854 "restore vport vlan list failed, ret=%d\n", 7855 ret); 7856 7857 mutex_unlock(&hdev->vport_lock); 7858 return ret; 7859 } 7860 } 7861 vlan->hd_tbl_status = true; 7862 } 7863 7864 mutex_unlock(&hdev->vport_lock); 7865 7866 return 0; 7867 } 7868 7869 static void hclge_rm_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id, 7870 bool is_write_tbl) 7871 { 7872 struct hclge_vport_vlan_cfg *vlan, *tmp; 7873 struct hclge_dev *hdev = vport->back; 7874 7875 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7876 if (vlan->vlan_id == vlan_id) { 7877 if (is_write_tbl && vlan->hd_tbl_status) 7878 hclge_set_vlan_filter_hw(hdev, 7879 htons(ETH_P_8021Q), 7880 vport->vport_id, 7881 vlan_id, 7882 true); 7883 7884 list_del(&vlan->node); 7885 kfree(vlan); 7886 break; 7887 } 7888 } 7889 } 7890 7891 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list) 7892 { 7893 struct hclge_vport_vlan_cfg *vlan, *tmp; 7894 struct hclge_dev *hdev = vport->back; 7895 7896 mutex_lock(&hdev->vport_lock); 7897 7898 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7899 if (vlan->hd_tbl_status) 7900 hclge_set_vlan_filter_hw(hdev, 7901 htons(ETH_P_8021Q), 7902 vport->vport_id, 7903 vlan->vlan_id, 7904 true); 7905 7906 vlan->hd_tbl_status = false; 7907 if (is_del_list) { 7908 list_del(&vlan->node); 7909 kfree(vlan); 7910 } 7911 } 7912 clear_bit(vport->vport_id, hdev->vf_vlan_full); 7913 mutex_unlock(&hdev->vport_lock); 7914 } 7915 7916 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev) 7917 { 7918 struct hclge_vport_vlan_cfg *vlan, *tmp; 7919 struct hclge_vport *vport; 7920 int i; 7921 7922 mutex_lock(&hdev->vport_lock); 7923 7924 for (i = 0; i < hdev->num_alloc_vport; i++) { 7925 vport = &hdev->vport[i]; 7926 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7927 list_del(&vlan->node); 7928 kfree(vlan); 7929 } 7930 } 7931 7932 mutex_unlock(&hdev->vport_lock); 7933 } 7934 7935 void hclge_restore_vport_port_base_vlan_config(struct hclge_dev *hdev) 7936 { 7937 struct hclge_vlan_info *vlan_info; 7938 struct hclge_vport *vport; 7939 u16 vlan_proto; 7940 u16 vlan_id; 7941 u16 state; 7942 int vf_id; 7943 int ret; 7944 7945 /* PF should restore all vfs port base vlan */ 7946 for (vf_id = 0; vf_id < hdev->num_alloc_vfs; vf_id++) { 7947 vport = &hdev->vport[vf_id + HCLGE_VF_VPORT_START_NUM]; 7948 vlan_info = vport->port_base_vlan_cfg.tbl_sta ? 7949 &vport->port_base_vlan_cfg.vlan_info : 7950 &vport->port_base_vlan_cfg.old_vlan_info; 7951 7952 vlan_id = vlan_info->vlan_tag; 7953 vlan_proto = vlan_info->vlan_proto; 7954 state = vport->port_base_vlan_cfg.state; 7955 7956 if (state != HNAE3_PORT_BASE_VLAN_DISABLE) { 7957 clear_bit(vport->vport_id, hdev->vlan_table[vlan_id]); 7958 ret = hclge_set_vlan_filter_hw(hdev, htons(vlan_proto), 7959 vport->vport_id, 7960 vlan_id, false); 7961 vport->port_base_vlan_cfg.tbl_sta = ret == 0; 7962 } 7963 } 7964 } 7965 7966 void hclge_restore_vport_vlan_table(struct hclge_vport *vport) 7967 { 7968 struct hclge_vport_vlan_cfg *vlan, *tmp; 7969 struct hclge_dev *hdev = vport->back; 7970 int ret; 7971 7972 mutex_lock(&hdev->vport_lock); 7973 7974 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 7975 list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) { 7976 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 7977 vport->vport_id, 7978 vlan->vlan_id, false); 7979 if (ret) 7980 break; 7981 vlan->hd_tbl_status = true; 7982 } 7983 } 7984 7985 mutex_unlock(&hdev->vport_lock); 7986 } 7987 7988 /* For global reset and imp reset, hardware will clear the mac table, 7989 * so we change the mac address state from ACTIVE to TO_ADD, then they 7990 * can be restored in the service task after reset complete. Furtherly, 7991 * the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to 7992 * be restored after reset, so just remove these mac nodes from mac_list. 7993 */ 7994 static void hclge_mac_node_convert_for_reset(struct list_head *list) 7995 { 7996 struct hclge_mac_node *mac_node, *tmp; 7997 7998 list_for_each_entry_safe(mac_node, tmp, list, node) { 7999 if (mac_node->state == HCLGE_MAC_ACTIVE) { 8000 mac_node->state = HCLGE_MAC_TO_ADD; 8001 } else if (mac_node->state == HCLGE_MAC_TO_DEL) { 8002 list_del(&mac_node->node); 8003 kfree(mac_node); 8004 } 8005 } 8006 } 8007 8008 void hclge_restore_mac_table_common(struct hclge_vport *vport) 8009 { 8010 spin_lock_bh(&vport->mac_list_lock); 8011 8012 hclge_mac_node_convert_for_reset(&vport->uc_mac_list); 8013 hclge_mac_node_convert_for_reset(&vport->mc_mac_list); 8014 set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state); 8015 8016 spin_unlock_bh(&vport->mac_list_lock); 8017 } 8018 8019 static void hclge_restore_hw_table(struct hclge_dev *hdev) 8020 { 8021 struct hclge_vport *vport = &hdev->vport[0]; 8022 struct hnae3_handle *handle = &vport->nic; 8023 8024 hclge_restore_mac_table_common(vport); 8025 hclge_restore_vport_port_base_vlan_config(hdev); 8026 hclge_restore_vport_vlan_table(vport); 8027 set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state); 8028 hclge_restore_fd_entries(handle); 8029 } 8030 8031 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) 8032 { 8033 struct hclge_vport *vport = hclge_get_vport(handle); 8034 8035 if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) { 8036 vport->rxvlan_cfg.strip_tag1_en = false; 8037 vport->rxvlan_cfg.strip_tag2_en = enable; 8038 vport->rxvlan_cfg.strip_tag2_discard_en = false; 8039 } else { 8040 vport->rxvlan_cfg.strip_tag1_en = enable; 8041 vport->rxvlan_cfg.strip_tag2_en = true; 8042 vport->rxvlan_cfg.strip_tag2_discard_en = true; 8043 } 8044 8045 vport->rxvlan_cfg.strip_tag1_discard_en = false; 8046 vport->rxvlan_cfg.vlan1_vlan_prionly = false; 8047 vport->rxvlan_cfg.vlan2_vlan_prionly = false; 8048 vport->rxvlan_cfg.rx_vlan_offload_en = enable; 8049 8050 return hclge_set_vlan_rx_offload_cfg(vport); 8051 } 8052 8053 static void hclge_set_vport_vlan_fltr_change(struct hclge_vport *vport) 8054 { 8055 struct hclge_dev *hdev = vport->back; 8056 8057 if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps)) 8058 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, &vport->state); 8059 } 8060 8061 static int hclge_update_vlan_filter_entries(struct hclge_vport *vport, 8062 u16 port_base_vlan_state, 8063 struct hclge_vlan_info *new_info, 8064 struct hclge_vlan_info *old_info) 8065 { 8066 struct hclge_dev *hdev = vport->back; 8067 int ret; 8068 8069 if (port_base_vlan_state == HNAE3_PORT_BASE_VLAN_ENABLE) { 8070 hclge_rm_vport_all_vlan_table(vport, false); 8071 /* force clear VLAN 0 */ 8072 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, true, 0); 8073 if (ret) 8074 return ret; 8075 return hclge_set_vlan_filter_hw(hdev, 8076 htons(new_info->vlan_proto), 8077 vport->vport_id, 8078 new_info->vlan_tag, 8079 false); 8080 } 8081 8082 vport->port_base_vlan_cfg.tbl_sta = false; 8083 8084 /* force add VLAN 0 */ 8085 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, false, 0); 8086 if (ret) 8087 return ret; 8088 8089 ret = hclge_set_vlan_filter_hw(hdev, htons(old_info->vlan_proto), 8090 vport->vport_id, old_info->vlan_tag, 8091 true); 8092 if (ret) 8093 return ret; 8094 8095 return hclge_add_vport_all_vlan_table(vport); 8096 } 8097 8098 static bool hclge_need_update_vlan_filter(const struct hclge_vlan_info *new_cfg, 8099 const struct hclge_vlan_info *old_cfg) 8100 { 8101 if (new_cfg->vlan_tag != old_cfg->vlan_tag) 8102 return true; 8103 8104 if (new_cfg->vlan_tag == 0 && (new_cfg->qos == 0 || old_cfg->qos == 0)) 8105 return true; 8106 8107 return false; 8108 } 8109 8110 static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport, 8111 struct hclge_vlan_info *new_info, 8112 struct hclge_vlan_info *old_info) 8113 { 8114 struct hclge_dev *hdev = vport->back; 8115 int ret; 8116 8117 /* add new VLAN tag */ 8118 ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto), 8119 vport->vport_id, new_info->vlan_tag, 8120 false); 8121 if (ret) 8122 return ret; 8123 8124 vport->port_base_vlan_cfg.tbl_sta = false; 8125 /* remove old VLAN tag */ 8126 if (old_info->vlan_tag == 0) 8127 ret = hclge_set_vf_vlan_common(hdev, vport->vport_id, 8128 true, 0); 8129 else 8130 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 8131 vport->vport_id, 8132 old_info->vlan_tag, true); 8133 if (ret) 8134 dev_err(&hdev->pdev->dev, 8135 "failed to clear vport%u port base vlan %u, ret = %d.\n", 8136 vport->vport_id, old_info->vlan_tag, ret); 8137 8138 return ret; 8139 } 8140 8141 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, 8142 struct hclge_vlan_info *vlan_info) 8143 { 8144 struct hnae3_handle *nic = &vport->nic; 8145 struct hclge_vlan_info *old_vlan_info; 8146 int ret; 8147 8148 old_vlan_info = &vport->port_base_vlan_cfg.vlan_info; 8149 8150 ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag, 8151 vlan_info->qos); 8152 if (ret) 8153 return ret; 8154 8155 if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info)) 8156 goto out; 8157 8158 if (state == HNAE3_PORT_BASE_VLAN_MODIFY) 8159 ret = hclge_modify_port_base_vlan_tag(vport, vlan_info, 8160 old_vlan_info); 8161 else 8162 ret = hclge_update_vlan_filter_entries(vport, state, vlan_info, 8163 old_vlan_info); 8164 if (ret) 8165 return ret; 8166 8167 out: 8168 vport->port_base_vlan_cfg.state = state; 8169 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) 8170 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE; 8171 else 8172 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE; 8173 8174 vport->port_base_vlan_cfg.old_vlan_info = *old_vlan_info; 8175 vport->port_base_vlan_cfg.vlan_info = *vlan_info; 8176 vport->port_base_vlan_cfg.tbl_sta = true; 8177 hclge_set_vport_vlan_fltr_change(vport); 8178 8179 return 0; 8180 } 8181 8182 static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport, 8183 enum hnae3_port_base_vlan_state state, 8184 u16 vlan, u8 qos) 8185 { 8186 if (state == HNAE3_PORT_BASE_VLAN_DISABLE) { 8187 if (!vlan && !qos) 8188 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 8189 8190 return HNAE3_PORT_BASE_VLAN_ENABLE; 8191 } 8192 8193 if (!vlan && !qos) 8194 return HNAE3_PORT_BASE_VLAN_DISABLE; 8195 8196 if (vport->port_base_vlan_cfg.vlan_info.vlan_tag == vlan && 8197 vport->port_base_vlan_cfg.vlan_info.qos == qos) 8198 return HNAE3_PORT_BASE_VLAN_NOCHANGE; 8199 8200 return HNAE3_PORT_BASE_VLAN_MODIFY; 8201 } 8202 8203 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, 8204 u16 vlan, u8 qos, __be16 proto) 8205 { 8206 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 8207 struct hclge_vport *vport = hclge_get_vport(handle); 8208 struct hclge_dev *hdev = vport->back; 8209 struct hclge_vlan_info vlan_info; 8210 u16 state; 8211 int ret; 8212 8213 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 8214 return -EOPNOTSUPP; 8215 8216 vport = hclge_get_vf_vport(hdev, vfid); 8217 if (!vport) 8218 return -EINVAL; 8219 8220 /* qos is a 3 bits value, so can not be bigger than 7 */ 8221 if (vlan > VLAN_N_VID - 1 || qos > 7) 8222 return -EINVAL; 8223 if (proto != htons(ETH_P_8021Q)) 8224 return -EPROTONOSUPPORT; 8225 8226 state = hclge_get_port_base_vlan_state(vport, 8227 vport->port_base_vlan_cfg.state, 8228 vlan, qos); 8229 if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE) 8230 return 0; 8231 8232 vlan_info.vlan_tag = vlan; 8233 vlan_info.qos = qos; 8234 vlan_info.vlan_proto = ntohs(proto); 8235 8236 ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info); 8237 if (ret) { 8238 dev_err(&hdev->pdev->dev, 8239 "failed to update port base vlan for vf %d, ret = %d\n", 8240 vfid, ret); 8241 return ret; 8242 } 8243 8244 /* there is a timewindow for PF to know VF unalive, it may 8245 * cause send mailbox fail, but it doesn't matter, VF will 8246 * query it when reinit. 8247 * for DEVICE_VERSION_V3, vf doesn't need to know about the port based 8248 * VLAN state. 8249 */ 8250 if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) { 8251 if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) 8252 (void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0], 8253 vport->vport_id, 8254 state, 8255 &vlan_info); 8256 else 8257 set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, 8258 &vport->need_notify); 8259 } 8260 return 0; 8261 } 8262 8263 static void hclge_clear_vf_vlan(struct hclge_dev *hdev) 8264 { 8265 struct hclge_vlan_info *vlan_info; 8266 struct hclge_vport *vport; 8267 int ret; 8268 int vf; 8269 8270 /* clear port base vlan for all vf */ 8271 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 8272 vport = &hdev->vport[vf]; 8273 vlan_info = &vport->port_base_vlan_cfg.vlan_info; 8274 8275 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 8276 vport->vport_id, 8277 vlan_info->vlan_tag, true); 8278 if (ret) 8279 dev_err(&hdev->pdev->dev, 8280 "failed to clear vf vlan for vf%d, ret = %d\n", 8281 vf - HCLGE_VF_VPORT_START_NUM, ret); 8282 } 8283 } 8284 8285 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, 8286 u16 vlan_id, bool is_kill) 8287 { 8288 struct hclge_vport *vport = hclge_get_vport(handle); 8289 struct hclge_dev *hdev = vport->back; 8290 bool writen_to_tbl = false; 8291 int ret = 0; 8292 8293 if (vlan_id >= VLAN_N_VID) 8294 return -EINVAL; 8295 8296 /* When device is resetting or reset failed, firmware is unable to 8297 * handle mailbox. Just record the vlan id, and remove it after 8298 * reset finished. 8299 */ 8300 mutex_lock(&hdev->vport_lock); 8301 if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8302 test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) { 8303 set_bit(vlan_id, vport->vlan_del_fail_bmap); 8304 mutex_unlock(&hdev->vport_lock); 8305 return -EBUSY; 8306 } else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) { 8307 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 8308 } 8309 mutex_unlock(&hdev->vport_lock); 8310 8311 /* when port base vlan enabled, we use port base vlan as the vlan 8312 * filter entry. In this case, we don't update vlan filter table 8313 * when user add new vlan or remove exist vlan, just update the vport 8314 * vlan list. The vlan id in vlan list will be writen in vlan filter 8315 * table until port base vlan disabled 8316 */ 8317 if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) { 8318 ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, 8319 vlan_id, is_kill); 8320 writen_to_tbl = true; 8321 } 8322 8323 if (!ret) { 8324 if (!is_kill) { 8325 hclge_add_vport_vlan_table(vport, vlan_id, 8326 writen_to_tbl); 8327 } else if (is_kill && vlan_id != 0) { 8328 mutex_lock(&hdev->vport_lock); 8329 hclge_rm_vport_vlan_table(vport, vlan_id, false); 8330 mutex_unlock(&hdev->vport_lock); 8331 } 8332 } else if (is_kill) { 8333 /* when remove hw vlan filter failed, record the vlan id, 8334 * and try to remove it from hw later, to be consistence 8335 * with stack 8336 */ 8337 mutex_lock(&hdev->vport_lock); 8338 set_bit(vlan_id, vport->vlan_del_fail_bmap); 8339 mutex_unlock(&hdev->vport_lock); 8340 } 8341 8342 hclge_set_vport_vlan_fltr_change(vport); 8343 8344 return ret; 8345 } 8346 8347 static void hclge_sync_vlan_fltr_state(struct hclge_dev *hdev) 8348 { 8349 struct hclge_vport *vport; 8350 int ret; 8351 u16 i; 8352 8353 for (i = 0; i < hdev->num_alloc_vport; i++) { 8354 vport = &hdev->vport[i]; 8355 if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 8356 &vport->state)) 8357 continue; 8358 8359 mutex_lock(&hdev->vport_lock); 8360 ret = __hclge_enable_vport_vlan_filter(vport, 8361 vport->req_vlan_fltr_en); 8362 if (ret) { 8363 dev_err(&hdev->pdev->dev, 8364 "failed to sync vlan filter state for vport%u, ret = %d\n", 8365 vport->vport_id, ret); 8366 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 8367 &vport->state); 8368 mutex_unlock(&hdev->vport_lock); 8369 return; 8370 } 8371 mutex_unlock(&hdev->vport_lock); 8372 } 8373 } 8374 8375 static void hclge_sync_vlan_filter(struct hclge_dev *hdev) 8376 { 8377 #define HCLGE_MAX_SYNC_COUNT 60 8378 8379 int i, ret, sync_cnt = 0; 8380 u16 vlan_id; 8381 8382 mutex_lock(&hdev->vport_lock); 8383 /* start from vport 1 for PF is always alive */ 8384 for (i = 0; i < hdev->num_alloc_vport; i++) { 8385 struct hclge_vport *vport = &hdev->vport[i]; 8386 8387 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 8388 VLAN_N_VID); 8389 while (vlan_id != VLAN_N_VID) { 8390 ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q), 8391 vport->vport_id, vlan_id, 8392 true); 8393 if (ret && ret != -EINVAL) { 8394 mutex_unlock(&hdev->vport_lock); 8395 return; 8396 } 8397 8398 clear_bit(vlan_id, vport->vlan_del_fail_bmap); 8399 hclge_rm_vport_vlan_table(vport, vlan_id, false); 8400 hclge_set_vport_vlan_fltr_change(vport); 8401 8402 sync_cnt++; 8403 if (sync_cnt >= HCLGE_MAX_SYNC_COUNT) { 8404 mutex_unlock(&hdev->vport_lock); 8405 return; 8406 } 8407 8408 vlan_id = find_first_bit(vport->vlan_del_fail_bmap, 8409 VLAN_N_VID); 8410 } 8411 } 8412 mutex_unlock(&hdev->vport_lock); 8413 8414 hclge_sync_vlan_fltr_state(hdev); 8415 } 8416 8417 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps) 8418 { 8419 struct hclge_config_max_frm_size_cmd *req; 8420 struct hclge_desc desc; 8421 8422 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); 8423 8424 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 8425 req->max_frm_size = cpu_to_le16(new_mps); 8426 req->min_frm_size = HCLGE_MAC_MIN_FRAME; 8427 8428 return hclge_cmd_send(&hdev->hw, &desc, 1); 8429 } 8430 8431 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) 8432 { 8433 struct hclge_vport *vport = hclge_get_vport(handle); 8434 8435 return hclge_set_vport_mtu(vport, new_mtu); 8436 } 8437 8438 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu) 8439 { 8440 struct hclge_dev *hdev = vport->back; 8441 int i, max_frm_size, ret; 8442 8443 /* HW supprt 2 layer vlan */ 8444 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 8445 if (max_frm_size < HCLGE_MAC_MIN_FRAME || 8446 max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) 8447 return -EINVAL; 8448 8449 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); 8450 mutex_lock(&hdev->vport_lock); 8451 /* VF's mps must fit within hdev->mps */ 8452 if (vport->vport_id && (u32)max_frm_size > hdev->mps) { 8453 mutex_unlock(&hdev->vport_lock); 8454 return -EINVAL; 8455 } else if (vport->vport_id) { 8456 vport->mps = max_frm_size; 8457 mutex_unlock(&hdev->vport_lock); 8458 return 0; 8459 } 8460 8461 /* PF's mps must be greater then VF's mps */ 8462 for (i = 1; i < hdev->num_alloc_vport; i++) 8463 if ((u32)max_frm_size < hdev->vport[i].mps) { 8464 dev_err(&hdev->pdev->dev, 8465 "failed to set pf mtu for less than vport %d, mps = %u.\n", 8466 i, hdev->vport[i].mps); 8467 mutex_unlock(&hdev->vport_lock); 8468 return -EINVAL; 8469 } 8470 8471 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); 8472 8473 ret = hclge_set_mac_mtu(hdev, max_frm_size); 8474 if (ret) { 8475 dev_err(&hdev->pdev->dev, 8476 "Change mtu fail, ret =%d\n", ret); 8477 goto out; 8478 } 8479 8480 hdev->mps = max_frm_size; 8481 vport->mps = max_frm_size; 8482 8483 ret = hclge_buffer_alloc(hdev); 8484 if (ret) 8485 dev_err(&hdev->pdev->dev, 8486 "Allocate buffer fail, ret =%d\n", ret); 8487 8488 out: 8489 hclge_notify_client(hdev, HNAE3_UP_CLIENT); 8490 mutex_unlock(&hdev->vport_lock); 8491 return ret; 8492 } 8493 8494 static int hclge_reset_tqp_cmd_send(struct hclge_dev *hdev, u16 queue_id, 8495 bool enable) 8496 { 8497 struct hclge_reset_tqp_queue_cmd *req; 8498 struct hclge_desc desc; 8499 int ret; 8500 8501 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); 8502 8503 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 8504 req->tqp_id = cpu_to_le16(queue_id); 8505 if (enable) 8506 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, 1U); 8507 8508 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8509 if (ret) { 8510 dev_err(&hdev->pdev->dev, 8511 "Send tqp reset cmd error, status =%d\n", ret); 8512 return ret; 8513 } 8514 8515 return 0; 8516 } 8517 8518 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id, 8519 u8 *reset_status) 8520 { 8521 struct hclge_reset_tqp_queue_cmd *req; 8522 struct hclge_desc desc; 8523 int ret; 8524 8525 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); 8526 8527 req = (struct hclge_reset_tqp_queue_cmd *)desc.data; 8528 req->tqp_id = cpu_to_le16(queue_id); 8529 8530 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8531 if (ret) { 8532 dev_err(&hdev->pdev->dev, 8533 "Get reset status error, status =%d\n", ret); 8534 return ret; 8535 } 8536 8537 *reset_status = hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); 8538 8539 return 0; 8540 } 8541 8542 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id) 8543 { 8544 struct hclge_comm_tqp *tqp; 8545 struct hnae3_queue *queue; 8546 8547 queue = handle->kinfo.tqp[queue_id]; 8548 tqp = container_of(queue, struct hclge_comm_tqp, q); 8549 8550 return tqp->index; 8551 } 8552 8553 static int hclge_reset_tqp_cmd(struct hnae3_handle *handle) 8554 { 8555 struct hclge_vport *vport = hclge_get_vport(handle); 8556 struct hclge_dev *hdev = vport->back; 8557 u16 reset_try_times = 0; 8558 u8 reset_status; 8559 u16 queue_gid; 8560 int ret; 8561 u16 i; 8562 8563 for (i = 0; i < handle->kinfo.num_tqps; i++) { 8564 queue_gid = hclge_covert_handle_qid_global(handle, i); 8565 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true); 8566 if (ret) { 8567 dev_err(&hdev->pdev->dev, 8568 "failed to send reset tqp cmd, ret = %d\n", 8569 ret); 8570 return ret; 8571 } 8572 8573 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { 8574 ret = hclge_get_reset_status(hdev, queue_gid, 8575 &reset_status); 8576 if (ret) 8577 return ret; 8578 8579 if (reset_status) 8580 break; 8581 8582 /* Wait for tqp hw reset */ 8583 usleep_range(1000, 1200); 8584 } 8585 8586 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { 8587 dev_err(&hdev->pdev->dev, 8588 "wait for tqp hw reset timeout\n"); 8589 return -ETIME; 8590 } 8591 8592 ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false); 8593 if (ret) { 8594 dev_err(&hdev->pdev->dev, 8595 "failed to deassert soft reset, ret = %d\n", 8596 ret); 8597 return ret; 8598 } 8599 reset_try_times = 0; 8600 } 8601 return 0; 8602 } 8603 8604 static int hclge_reset_rcb(struct hnae3_handle *handle) 8605 { 8606 #define HCLGE_RESET_RCB_NOT_SUPPORT 0U 8607 #define HCLGE_RESET_RCB_SUCCESS 1U 8608 8609 struct hclge_vport *vport = hclge_get_vport(handle); 8610 struct hclge_dev *hdev = vport->back; 8611 struct hclge_reset_cmd *req; 8612 struct hclge_desc desc; 8613 u8 return_status; 8614 u16 queue_gid; 8615 int ret; 8616 8617 queue_gid = hclge_covert_handle_qid_global(handle, 0); 8618 8619 req = (struct hclge_reset_cmd *)desc.data; 8620 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); 8621 hnae3_set_bit(req->fun_reset_rcb, HCLGE_CFG_RESET_RCB_B, 1); 8622 req->fun_reset_rcb_vqid_start = cpu_to_le16(queue_gid); 8623 req->fun_reset_rcb_vqid_num = cpu_to_le16(handle->kinfo.num_tqps); 8624 8625 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8626 if (ret) { 8627 dev_err(&hdev->pdev->dev, 8628 "failed to send rcb reset cmd, ret = %d\n", ret); 8629 return ret; 8630 } 8631 8632 return_status = req->fun_reset_rcb_return_status; 8633 if (return_status == HCLGE_RESET_RCB_SUCCESS) 8634 return 0; 8635 8636 if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) { 8637 dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n", 8638 return_status); 8639 return -EIO; 8640 } 8641 8642 /* if reset rcb cmd is unsupported, we need to send reset tqp cmd 8643 * again to reset all tqps 8644 */ 8645 return hclge_reset_tqp_cmd(handle); 8646 } 8647 8648 int hclge_reset_tqp(struct hnae3_handle *handle) 8649 { 8650 struct hclge_vport *vport = hclge_get_vport(handle); 8651 struct hclge_dev *hdev = vport->back; 8652 int ret; 8653 8654 /* only need to disable PF's tqp */ 8655 if (!vport->vport_id) { 8656 ret = hclge_tqp_enable(handle, false); 8657 if (ret) { 8658 dev_err(&hdev->pdev->dev, 8659 "failed to disable tqp, ret = %d\n", ret); 8660 return ret; 8661 } 8662 } 8663 8664 return hclge_reset_rcb(handle); 8665 } 8666 8667 static u32 hclge_get_fw_version(struct hnae3_handle *handle) 8668 { 8669 struct hclge_vport *vport = hclge_get_vport(handle); 8670 struct hclge_dev *hdev = vport->back; 8671 8672 return hdev->fw_version; 8673 } 8674 8675 int hclge_query_scc_version(struct hclge_dev *hdev, u32 *scc_version) 8676 { 8677 struct hclge_comm_query_scc_cmd *resp; 8678 struct hclge_desc desc; 8679 int ret; 8680 8681 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_SCC_VER, 1); 8682 resp = (struct hclge_comm_query_scc_cmd *)desc.data; 8683 8684 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 8685 if (ret) 8686 return ret; 8687 8688 *scc_version = le32_to_cpu(resp->scc_version); 8689 8690 return 0; 8691 } 8692 8693 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 8694 { 8695 struct phy_device *phydev = hdev->hw.mac.phydev; 8696 8697 if (!phydev) 8698 return; 8699 8700 phy_set_asym_pause(phydev, rx_en, tx_en); 8701 } 8702 8703 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) 8704 { 8705 int ret; 8706 8707 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) 8708 return 0; 8709 8710 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); 8711 if (ret) 8712 dev_err(&hdev->pdev->dev, 8713 "configure pauseparam error, ret = %d.\n", ret); 8714 8715 return ret; 8716 } 8717 8718 int hclge_cfg_flowctrl(struct hclge_dev *hdev) 8719 { 8720 struct phy_device *phydev = hdev->hw.mac.phydev; 8721 u16 remote_advertising = 0; 8722 u16 local_advertising; 8723 u32 rx_pause, tx_pause; 8724 u8 flowctl; 8725 8726 if (!phydev->link) 8727 return 0; 8728 8729 if (!phydev->autoneg) 8730 return hclge_mac_pause_setup_hw(hdev); 8731 8732 local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising); 8733 8734 if (phydev->pause) 8735 remote_advertising = LPA_PAUSE_CAP; 8736 8737 if (phydev->asym_pause) 8738 remote_advertising |= LPA_PAUSE_ASYM; 8739 8740 flowctl = mii_resolve_flowctrl_fdx(local_advertising, 8741 remote_advertising); 8742 tx_pause = flowctl & FLOW_CTRL_TX; 8743 rx_pause = flowctl & FLOW_CTRL_RX; 8744 8745 if (phydev->duplex == HCLGE_MAC_HALF) { 8746 tx_pause = 0; 8747 rx_pause = 0; 8748 } 8749 8750 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); 8751 } 8752 8753 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, 8754 u32 *rx_en, u32 *tx_en) 8755 { 8756 struct hclge_vport *vport = hclge_get_vport(handle); 8757 struct hclge_dev *hdev = vport->back; 8758 u8 media_type = hdev->hw.mac.media_type; 8759 8760 *auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ? 8761 hclge_get_autoneg(handle) : 0; 8762 8763 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 8764 *rx_en = 0; 8765 *tx_en = 0; 8766 return; 8767 } 8768 8769 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { 8770 *rx_en = 1; 8771 *tx_en = 0; 8772 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { 8773 *tx_en = 1; 8774 *rx_en = 0; 8775 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { 8776 *rx_en = 1; 8777 *tx_en = 1; 8778 } else { 8779 *rx_en = 0; 8780 *tx_en = 0; 8781 } 8782 } 8783 8784 static void hclge_record_user_pauseparam(struct hclge_dev *hdev, 8785 u32 rx_en, u32 tx_en) 8786 { 8787 if (rx_en && tx_en) 8788 hdev->fc_mode_last_time = HCLGE_FC_FULL; 8789 else if (rx_en && !tx_en) 8790 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; 8791 else if (!rx_en && tx_en) 8792 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; 8793 else 8794 hdev->fc_mode_last_time = HCLGE_FC_NONE; 8795 8796 hdev->tm_info.fc_mode = hdev->fc_mode_last_time; 8797 } 8798 8799 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, 8800 u32 rx_en, u32 tx_en) 8801 { 8802 struct hclge_vport *vport = hclge_get_vport(handle); 8803 struct hclge_dev *hdev = vport->back; 8804 struct phy_device *phydev = hdev->hw.mac.phydev; 8805 u32 fc_autoneg; 8806 8807 if (phydev || hnae3_dev_phy_imp_supported(hdev)) { 8808 fc_autoneg = hclge_get_autoneg(handle); 8809 if (auto_neg != fc_autoneg) { 8810 dev_info(&hdev->pdev->dev, 8811 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); 8812 return -EOPNOTSUPP; 8813 } 8814 } 8815 8816 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { 8817 dev_info(&hdev->pdev->dev, 8818 "Priority flow control enabled. Cannot set link flow control.\n"); 8819 return -EOPNOTSUPP; 8820 } 8821 8822 hclge_set_flowctrl_adv(hdev, rx_en, tx_en); 8823 8824 hclge_record_user_pauseparam(hdev, rx_en, tx_en); 8825 8826 if (!auto_neg || hnae3_dev_phy_imp_supported(hdev)) 8827 return hclge_cfg_pauseparam(hdev, rx_en, tx_en); 8828 8829 if (phydev) 8830 return phy_start_aneg(phydev); 8831 8832 return -EOPNOTSUPP; 8833 } 8834 8835 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, 8836 u8 *auto_neg, u32 *speed, u8 *duplex, u32 *lane_num) 8837 { 8838 struct hclge_vport *vport = hclge_get_vport(handle); 8839 struct hclge_dev *hdev = vport->back; 8840 8841 if (speed) 8842 *speed = hdev->hw.mac.speed; 8843 if (duplex) 8844 *duplex = hdev->hw.mac.duplex; 8845 if (auto_neg) 8846 *auto_neg = hdev->hw.mac.autoneg; 8847 if (lane_num) 8848 *lane_num = hdev->hw.mac.lane_num; 8849 } 8850 8851 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type, 8852 u8 *module_type) 8853 { 8854 struct hclge_vport *vport = hclge_get_vport(handle); 8855 struct hclge_dev *hdev = vport->back; 8856 8857 /* When nic is down, the service task is not running, doesn't update 8858 * the port information per second. Query the port information before 8859 * return the media type, ensure getting the correct media information. 8860 */ 8861 hclge_update_port_info(hdev); 8862 8863 if (media_type) 8864 *media_type = hdev->hw.mac.media_type; 8865 8866 if (module_type) 8867 *module_type = hdev->hw.mac.module_type; 8868 } 8869 8870 static void hclge_get_mdix_mode(struct hnae3_handle *handle, 8871 u8 *tp_mdix_ctrl, u8 *tp_mdix) 8872 { 8873 struct hclge_vport *vport = hclge_get_vport(handle); 8874 struct hclge_dev *hdev = vport->back; 8875 struct phy_device *phydev = hdev->hw.mac.phydev; 8876 int mdix_ctrl, mdix, is_resolved; 8877 unsigned int retval; 8878 8879 if (!phydev) { 8880 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 8881 *tp_mdix = ETH_TP_MDI_INVALID; 8882 return; 8883 } 8884 8885 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); 8886 8887 retval = phy_read(phydev, HCLGE_PHY_CSC_REG); 8888 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, 8889 HCLGE_PHY_MDIX_CTRL_S); 8890 8891 retval = phy_read(phydev, HCLGE_PHY_CSS_REG); 8892 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); 8893 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); 8894 8895 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); 8896 8897 switch (mdix_ctrl) { 8898 case 0x0: 8899 *tp_mdix_ctrl = ETH_TP_MDI; 8900 break; 8901 case 0x1: 8902 *tp_mdix_ctrl = ETH_TP_MDI_X; 8903 break; 8904 case 0x3: 8905 *tp_mdix_ctrl = ETH_TP_MDI_AUTO; 8906 break; 8907 default: 8908 *tp_mdix_ctrl = ETH_TP_MDI_INVALID; 8909 break; 8910 } 8911 8912 if (!is_resolved) 8913 *tp_mdix = ETH_TP_MDI_INVALID; 8914 else if (mdix) 8915 *tp_mdix = ETH_TP_MDI_X; 8916 else 8917 *tp_mdix = ETH_TP_MDI; 8918 } 8919 8920 static void hclge_info_show(struct hclge_dev *hdev) 8921 { 8922 struct hnae3_handle *handle = &hdev->vport->nic; 8923 struct device *dev = &hdev->pdev->dev; 8924 8925 dev_info(dev, "PF info begin:\n"); 8926 8927 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps); 8928 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc); 8929 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc); 8930 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport); 8931 dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs); 8932 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map); 8933 dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size); 8934 dev_info(dev, "TX buffer size for each TC: %u\n", hdev->tx_buf_size); 8935 dev_info(dev, "DV buffer size for each TC: %u\n", hdev->dv_buf_size); 8936 dev_info(dev, "This is %s PF\n", 8937 hdev->flag & HCLGE_FLAG_MAIN ? "main" : "not main"); 8938 dev_info(dev, "DCB %s\n", 8939 str_enable_disable(handle->kinfo.tc_info.dcb_ets_active)); 8940 dev_info(dev, "MQPRIO %s\n", 8941 str_enable_disable(handle->kinfo.tc_info.mqprio_active)); 8942 dev_info(dev, "Default tx spare buffer size: %u\n", 8943 hdev->tx_spare_buf_size); 8944 8945 dev_info(dev, "PF info end.\n"); 8946 } 8947 8948 static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, 8949 struct hclge_vport *vport) 8950 { 8951 struct hnae3_client *client = vport->nic.client; 8952 struct hclge_dev *hdev = ae_dev->priv; 8953 u32 rst_cnt = hdev->rst_stats.reset_cnt; 8954 int ret; 8955 8956 ret = client->ops->init_instance(&vport->nic); 8957 if (ret) 8958 return ret; 8959 8960 set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8961 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 8962 rst_cnt != hdev->rst_stats.reset_cnt) { 8963 ret = -EBUSY; 8964 goto init_nic_err; 8965 } 8966 8967 /* Enable nic hw error interrupts */ 8968 ret = hclge_config_nic_hw_error(hdev, true); 8969 if (ret) { 8970 dev_err(&ae_dev->pdev->dev, 8971 "fail(%d) to enable hw error interrupts\n", ret); 8972 goto init_nic_err; 8973 } 8974 8975 hnae3_set_client_init_flag(client, ae_dev, 1); 8976 8977 if (netif_msg_drv(&hdev->vport->nic)) 8978 hclge_info_show(hdev); 8979 8980 return ret; 8981 8982 init_nic_err: 8983 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 8984 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 8985 msleep(HCLGE_WAIT_RESET_DONE); 8986 8987 client->ops->uninit_instance(&vport->nic, 0); 8988 8989 return ret; 8990 } 8991 8992 static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev, 8993 struct hclge_vport *vport) 8994 { 8995 struct hclge_dev *hdev = ae_dev->priv; 8996 struct hnae3_client *client; 8997 u32 rst_cnt; 8998 int ret; 8999 9000 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client || 9001 !hdev->nic_client) 9002 return 0; 9003 9004 client = hdev->roce_client; 9005 ret = hclge_init_roce_base_info(vport); 9006 if (ret) 9007 return ret; 9008 9009 rst_cnt = hdev->rst_stats.reset_cnt; 9010 ret = client->ops->init_instance(&vport->roce); 9011 if (ret) 9012 return ret; 9013 9014 set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 9015 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 9016 rst_cnt != hdev->rst_stats.reset_cnt) { 9017 ret = -EBUSY; 9018 goto init_roce_err; 9019 } 9020 9021 /* Enable roce ras interrupts */ 9022 ret = hclge_config_rocee_ras_interrupt(hdev, true); 9023 if (ret) { 9024 dev_err(&ae_dev->pdev->dev, 9025 "fail(%d) to enable roce ras interrupts\n", ret); 9026 goto init_roce_err; 9027 } 9028 9029 hnae3_set_client_init_flag(client, ae_dev, 1); 9030 9031 return 0; 9032 9033 init_roce_err: 9034 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 9035 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 9036 msleep(HCLGE_WAIT_RESET_DONE); 9037 9038 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 9039 9040 return ret; 9041 } 9042 9043 static int hclge_init_client_instance(struct hnae3_client *client, 9044 struct hnae3_ae_dev *ae_dev) 9045 { 9046 struct hclge_dev *hdev = ae_dev->priv; 9047 struct hclge_vport *vport = &hdev->vport[0]; 9048 int ret; 9049 9050 switch (client->type) { 9051 case HNAE3_CLIENT_KNIC: 9052 hdev->nic_client = client; 9053 vport->nic.client = client; 9054 ret = hclge_init_nic_client_instance(ae_dev, vport); 9055 if (ret) 9056 goto clear_nic; 9057 9058 ret = hclge_init_roce_client_instance(ae_dev, vport); 9059 if (ret) 9060 goto clear_roce; 9061 9062 break; 9063 case HNAE3_CLIENT_ROCE: 9064 if (hnae3_dev_roce_supported(hdev)) { 9065 hdev->roce_client = client; 9066 vport->roce.client = client; 9067 } 9068 9069 ret = hclge_init_roce_client_instance(ae_dev, vport); 9070 if (ret) 9071 goto clear_roce; 9072 9073 break; 9074 default: 9075 return -EINVAL; 9076 } 9077 9078 return 0; 9079 9080 clear_nic: 9081 hdev->nic_client = NULL; 9082 vport->nic.client = NULL; 9083 return ret; 9084 clear_roce: 9085 hdev->roce_client = NULL; 9086 vport->roce.client = NULL; 9087 return ret; 9088 } 9089 9090 static bool hclge_uninit_need_wait(struct hclge_dev *hdev) 9091 { 9092 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || 9093 test_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state); 9094 } 9095 9096 static void hclge_uninit_client_instance(struct hnae3_client *client, 9097 struct hnae3_ae_dev *ae_dev) 9098 { 9099 struct hclge_dev *hdev = ae_dev->priv; 9100 struct hclge_vport *vport = &hdev->vport[0]; 9101 9102 if (hdev->roce_client) { 9103 clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state); 9104 while (hclge_uninit_need_wait(hdev)) 9105 msleep(HCLGE_WAIT_RESET_DONE); 9106 9107 hdev->roce_client->ops->uninit_instance(&vport->roce, 0); 9108 hdev->roce_client = NULL; 9109 vport->roce.client = NULL; 9110 } 9111 if (client->type == HNAE3_CLIENT_ROCE) 9112 return; 9113 if (hdev->nic_client && client->ops->uninit_instance) { 9114 clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); 9115 while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 9116 msleep(HCLGE_WAIT_RESET_DONE); 9117 9118 client->ops->uninit_instance(&vport->nic, 0); 9119 hdev->nic_client = NULL; 9120 vport->nic.client = NULL; 9121 } 9122 } 9123 9124 static int hclge_dev_mem_map(struct hclge_dev *hdev) 9125 { 9126 struct pci_dev *pdev = hdev->pdev; 9127 struct hclge_hw *hw = &hdev->hw; 9128 9129 /* for device does not have device memory, return directly */ 9130 if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR))) 9131 return 0; 9132 9133 hw->hw.mem_base = 9134 devm_ioremap_wc(&pdev->dev, 9135 pci_resource_start(pdev, HCLGE_MEM_BAR), 9136 pci_resource_len(pdev, HCLGE_MEM_BAR)); 9137 if (!hw->hw.mem_base) { 9138 dev_err(&pdev->dev, "failed to map device memory\n"); 9139 return -EFAULT; 9140 } 9141 9142 return 0; 9143 } 9144 9145 static int hclge_pci_init(struct hclge_dev *hdev) 9146 { 9147 struct pci_dev *pdev = hdev->pdev; 9148 struct hclge_hw *hw; 9149 int ret; 9150 9151 ret = pci_enable_device(pdev); 9152 if (ret) { 9153 dev_err(&pdev->dev, "failed to enable PCI device\n"); 9154 return ret; 9155 } 9156 9157 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 9158 if (ret) { 9159 dev_err(&pdev->dev, "can't set consistent PCI DMA\n"); 9160 goto err_disable_device; 9161 } 9162 9163 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); 9164 if (ret) { 9165 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); 9166 goto err_disable_device; 9167 } 9168 9169 pci_set_master(pdev); 9170 hw = &hdev->hw; 9171 hw->hw.io_base = pcim_iomap(pdev, 2, 0); 9172 if (!hw->hw.io_base) { 9173 dev_err(&pdev->dev, "Can't map configuration register space\n"); 9174 ret = -ENOMEM; 9175 goto err_release_regions; 9176 } 9177 9178 ret = hclge_dev_mem_map(hdev); 9179 if (ret) 9180 goto err_unmap_io_base; 9181 9182 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); 9183 9184 return 0; 9185 9186 err_unmap_io_base: 9187 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9188 err_release_regions: 9189 pci_release_regions(pdev); 9190 err_disable_device: 9191 pci_disable_device(pdev); 9192 9193 return ret; 9194 } 9195 9196 static void hclge_pci_uninit(struct hclge_dev *hdev) 9197 { 9198 struct pci_dev *pdev = hdev->pdev; 9199 9200 if (hdev->hw.hw.mem_base) 9201 devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base); 9202 9203 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9204 pci_free_irq_vectors(pdev); 9205 pci_release_regions(pdev); 9206 pci_disable_device(pdev); 9207 } 9208 9209 static void hclge_state_init(struct hclge_dev *hdev) 9210 { 9211 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); 9212 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9213 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); 9214 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9215 clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state); 9216 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); 9217 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); 9218 } 9219 9220 static void hclge_state_uninit(struct hclge_dev *hdev) 9221 { 9222 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9223 set_bit(HCLGE_STATE_REMOVING, &hdev->state); 9224 9225 if (hdev->reset_timer.function) 9226 timer_delete_sync(&hdev->reset_timer); 9227 if (hdev->service_task.work.func) 9228 cancel_delayed_work_sync(&hdev->service_task); 9229 } 9230 9231 static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev, 9232 enum hnae3_reset_type rst_type) 9233 { 9234 #define HCLGE_RESET_RETRY_WAIT_MS 500 9235 #define HCLGE_RESET_RETRY_CNT 5 9236 9237 struct hclge_dev *hdev = ae_dev->priv; 9238 int retry_cnt = 0; 9239 int ret; 9240 9241 while (retry_cnt++ < HCLGE_RESET_RETRY_CNT) { 9242 down(&hdev->reset_sem); 9243 set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9244 hdev->reset_type = rst_type; 9245 ret = hclge_reset_prepare(hdev); 9246 if (!ret && !hdev->reset_pending) 9247 break; 9248 9249 dev_err(&hdev->pdev->dev, 9250 "failed to prepare to reset, ret=%d, reset_pending:0x%lx, retry_cnt:%d\n", 9251 ret, hdev->reset_pending, retry_cnt); 9252 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); 9253 up(&hdev->reset_sem); 9254 msleep(HCLGE_RESET_RETRY_WAIT_MS); 9255 } 9256 9257 /* disable misc vector before reset done */ 9258 hclge_enable_vector(&hdev->misc_vector, false); 9259 set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state); 9260 9261 if (hdev->reset_type == HNAE3_FLR_RESET) 9262 hdev->rst_stats.flr_rst_cnt++; 9263 } 9264 9265 static void hclge_reset_done(struct hnae3_ae_dev *ae_dev) 9266 { 9267 struct hclge_dev *hdev = ae_dev->priv; 9268 int ret; 9269 9270 hclge_enable_vector(&hdev->misc_vector, true); 9271 9272 ret = hclge_reset_rebuild(hdev); 9273 if (ret) 9274 dev_err(&hdev->pdev->dev, "fail to rebuild, ret=%d\n", ret); 9275 9276 hdev->reset_type = HNAE3_NONE_RESET; 9277 if (test_and_clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) 9278 up(&hdev->reset_sem); 9279 } 9280 9281 static void hclge_clear_resetting_state(struct hclge_dev *hdev) 9282 { 9283 u16 i; 9284 9285 for (i = 0; i < hdev->num_alloc_vport; i++) { 9286 struct hclge_vport *vport = &hdev->vport[i]; 9287 int ret; 9288 9289 /* Send cmd to clear vport's FUNC_RST_ING */ 9290 ret = hclge_set_vf_rst(hdev, vport->vport_id, false); 9291 if (ret) 9292 dev_warn(&hdev->pdev->dev, 9293 "clear vport(%u) rst failed %d!\n", 9294 vport->vport_id, ret); 9295 } 9296 } 9297 9298 static int hclge_clear_hw_resource(struct hclge_dev *hdev) 9299 { 9300 struct hclge_desc desc; 9301 int ret; 9302 9303 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_HW_RESOURCE, false); 9304 9305 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9306 /* This new command is only supported by new firmware, it will 9307 * fail with older firmware. Error value -EOPNOSUPP can only be 9308 * returned by older firmware running this command, to keep code 9309 * backward compatible we will override this value and return 9310 * success. 9311 */ 9312 if (ret && ret != -EOPNOTSUPP) { 9313 dev_err(&hdev->pdev->dev, 9314 "failed to clear hw resource, ret = %d\n", ret); 9315 return ret; 9316 } 9317 return 0; 9318 } 9319 9320 static void hclge_init_rxd_adv_layout(struct hclge_dev *hdev) 9321 { 9322 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 9323 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 1); 9324 } 9325 9326 static void hclge_uninit_rxd_adv_layout(struct hclge_dev *hdev) 9327 { 9328 if (hnae3_ae_dev_rxd_adv_layout_supported(hdev->ae_dev)) 9329 hclge_write_dev(&hdev->hw, HCLGE_RXD_ADV_LAYOUT_EN_REG, 0); 9330 } 9331 9332 static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle) 9333 { 9334 struct hclge_vport *vport = hclge_get_vport(handle); 9335 9336 return &vport->back->hw.mac.wol; 9337 } 9338 9339 static int hclge_get_wol_supported_mode(struct hclge_dev *hdev, 9340 u32 *wol_supported) 9341 { 9342 struct hclge_query_wol_supported_cmd *wol_supported_cmd; 9343 struct hclge_desc desc; 9344 int ret; 9345 9346 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE, 9347 true); 9348 wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data; 9349 9350 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9351 if (ret) { 9352 dev_err(&hdev->pdev->dev, 9353 "failed to query wol supported, ret = %d\n", ret); 9354 return ret; 9355 } 9356 9357 *wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode); 9358 9359 return 0; 9360 } 9361 9362 static int hclge_set_wol_cfg(struct hclge_dev *hdev, 9363 struct hclge_wol_info *wol_info) 9364 { 9365 struct hclge_wol_cfg_cmd *wol_cfg_cmd; 9366 struct hclge_desc desc; 9367 int ret; 9368 9369 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false); 9370 wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data; 9371 wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode); 9372 wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size; 9373 memcpy(wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX); 9374 9375 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 9376 if (ret) 9377 dev_err(&hdev->pdev->dev, 9378 "failed to set wol config, ret = %d\n", ret); 9379 9380 return ret; 9381 } 9382 9383 static int hclge_update_wol(struct hclge_dev *hdev) 9384 { 9385 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 9386 9387 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 9388 return 0; 9389 9390 return hclge_set_wol_cfg(hdev, wol_info); 9391 } 9392 9393 static int hclge_init_wol(struct hclge_dev *hdev) 9394 { 9395 struct hclge_wol_info *wol_info = &hdev->hw.mac.wol; 9396 int ret; 9397 9398 if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) 9399 return 0; 9400 9401 memset(wol_info, 0, sizeof(struct hclge_wol_info)); 9402 ret = hclge_get_wol_supported_mode(hdev, 9403 &wol_info->wol_support_mode); 9404 if (ret) { 9405 wol_info->wol_support_mode = 0; 9406 return ret; 9407 } 9408 9409 return hclge_update_wol(hdev); 9410 } 9411 9412 static void hclge_init_pfc_prevention_tout(struct hclge_dev *hdev) 9413 { 9414 struct hnae3_handle *handle = &hdev->vport[0].nic; 9415 u16 times; 9416 int ret; 9417 9418 ret = hclge_enable_pfc_storm_prevent(hdev, HCLGE_DIR_RX, false); 9419 if (ret == -EOPNOTSUPP) 9420 return; 9421 else if (ret) 9422 dev_warn(&hdev->pdev->dev, 9423 "failed to disable rx pfc storm prevent, ret = %d\n", 9424 ret); 9425 9426 ret = hclge_get_pfc_prevention_tout(handle, ×); 9427 if (ret) { 9428 dev_warn(&hdev->pdev->dev, 9429 "failed to get tx pfc prevention timeout, ret = %d\n", 9430 ret); 9431 times = HCLGE_DEFAULT_PFC_PREVENTION_TOUT; 9432 } 9433 9434 hdev->pfc_prevention_tout = times; 9435 hdev->pfc_prevention_tout_default = times; 9436 } 9437 9438 static void hclge_get_wol(struct hnae3_handle *handle, 9439 struct ethtool_wolinfo *wol) 9440 { 9441 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 9442 9443 wol->supported = wol_info->wol_support_mode; 9444 wol->wolopts = wol_info->wol_current_mode; 9445 if (wol_info->wol_current_mode & WAKE_MAGICSECURE) 9446 memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX); 9447 } 9448 9449 static int hclge_set_wol(struct hnae3_handle *handle, 9450 struct ethtool_wolinfo *wol) 9451 { 9452 struct hclge_wol_info *wol_info = hclge_get_wol_info(handle); 9453 struct hclge_vport *vport = hclge_get_vport(handle); 9454 u32 wol_mode; 9455 int ret; 9456 9457 wol_mode = wol->wolopts; 9458 if (wol_mode & ~wol_info->wol_support_mode) 9459 return -EINVAL; 9460 9461 wol_info->wol_current_mode = wol_mode; 9462 if (wol_mode & WAKE_MAGICSECURE) { 9463 memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX); 9464 wol_info->wol_sopass_size = SOPASS_MAX; 9465 } else { 9466 wol_info->wol_sopass_size = 0; 9467 } 9468 9469 ret = hclge_set_wol_cfg(vport->back, wol_info); 9470 if (ret) 9471 wol_info->wol_current_mode = 0; 9472 9473 return ret; 9474 } 9475 9476 static int hclge_set_autoneg_speed_dup(struct hclge_dev *hdev) 9477 { 9478 int ret; 9479 9480 if (hdev->hw.mac.support_autoneg) { 9481 ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.req_autoneg); 9482 if (ret) 9483 return ret; 9484 } 9485 9486 if (!hdev->hw.mac.req_autoneg) { 9487 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed, 9488 hdev->hw.mac.req_duplex, 9489 hdev->hw.mac.req_lane_num); 9490 if (ret) 9491 return ret; 9492 } 9493 9494 return 0; 9495 } 9496 9497 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) 9498 { 9499 struct pci_dev *pdev = ae_dev->pdev; 9500 struct hclge_dev *hdev; 9501 int ret; 9502 9503 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); 9504 if (!hdev) 9505 return -ENOMEM; 9506 9507 hdev->pdev = pdev; 9508 hdev->ae_dev = ae_dev; 9509 hdev->reset_type = HNAE3_NONE_RESET; 9510 hdev->reset_level = HNAE3_FUNC_RESET; 9511 ae_dev->priv = hdev; 9512 9513 /* HW supprt 2 layer vlan */ 9514 hdev->mps = ETH_FRAME_LEN + ETH_FCS_LEN + 2 * VLAN_HLEN; 9515 9516 mutex_init(&hdev->vport_lock); 9517 spin_lock_init(&hdev->fd_rule_lock); 9518 sema_init(&hdev->reset_sem, 1); 9519 9520 ret = hclge_pci_init(hdev); 9521 if (ret) 9522 goto out; 9523 9524 /* Firmware command queue initialize */ 9525 ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw); 9526 if (ret) 9527 goto err_pci_uninit; 9528 9529 /* Firmware command initialize */ 9530 hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops); 9531 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 9532 true, hdev->reset_pending); 9533 if (ret) 9534 goto err_cmd_uninit; 9535 9536 ret = hclge_clear_hw_resource(hdev); 9537 if (ret) 9538 goto err_cmd_uninit; 9539 9540 ret = hclge_get_cap(hdev); 9541 if (ret) 9542 goto err_cmd_uninit; 9543 9544 ret = hclge_query_dev_specs(hdev); 9545 if (ret) { 9546 dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n", 9547 ret); 9548 goto err_cmd_uninit; 9549 } 9550 9551 ret = hclge_configure(hdev); 9552 if (ret) { 9553 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); 9554 goto err_cmd_uninit; 9555 } 9556 9557 ret = hclge_init_msi(hdev); 9558 if (ret) { 9559 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); 9560 goto err_cmd_uninit; 9561 } 9562 9563 ret = hclge_misc_irq_init(hdev); 9564 if (ret) 9565 goto err_msi_uninit; 9566 9567 ret = hclge_alloc_tqps(hdev); 9568 if (ret) { 9569 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); 9570 goto err_msi_irq_uninit; 9571 } 9572 9573 ret = hclge_alloc_vport(hdev); 9574 if (ret) 9575 goto err_msi_irq_uninit; 9576 9577 ret = hclge_map_tqp(hdev); 9578 if (ret) 9579 goto err_msi_irq_uninit; 9580 9581 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { 9582 clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps); 9583 if (hnae3_dev_phy_imp_supported(hdev)) 9584 ret = hclge_update_tp_port_info(hdev); 9585 else 9586 ret = hclge_mac_mdio_config(hdev); 9587 9588 if (ret) 9589 goto err_msi_irq_uninit; 9590 } 9591 9592 ret = hclge_init_umv_space(hdev); 9593 if (ret) 9594 goto err_mdiobus_unreg; 9595 9596 ret = hclge_mac_init(hdev); 9597 if (ret) { 9598 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 9599 goto err_mdiobus_unreg; 9600 } 9601 9602 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 9603 if (ret) { 9604 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 9605 goto err_mdiobus_unreg; 9606 } 9607 9608 ret = hclge_config_gro(hdev); 9609 if (ret) 9610 goto err_mdiobus_unreg; 9611 9612 ret = hclge_init_vlan_config(hdev); 9613 if (ret) { 9614 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 9615 goto err_mdiobus_unreg; 9616 } 9617 9618 ret = hclge_tm_schd_init(hdev); 9619 if (ret) { 9620 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); 9621 goto err_mdiobus_unreg; 9622 } 9623 9624 ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev, 9625 &hdev->rss_cfg); 9626 if (ret) { 9627 dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret); 9628 goto err_mdiobus_unreg; 9629 } 9630 9631 ret = hclge_rss_init_hw(hdev); 9632 if (ret) { 9633 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 9634 goto err_mdiobus_unreg; 9635 } 9636 9637 ret = init_mgr_tbl(hdev); 9638 if (ret) { 9639 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); 9640 goto err_mdiobus_unreg; 9641 } 9642 9643 ret = hclge_init_fd_config(hdev); 9644 if (ret) { 9645 dev_err(&pdev->dev, 9646 "fd table init fail, ret=%d\n", ret); 9647 goto err_mdiobus_unreg; 9648 } 9649 9650 ret = hclge_ptp_init(hdev); 9651 if (ret) 9652 goto err_mdiobus_unreg; 9653 9654 ret = hclge_update_port_info(hdev); 9655 if (ret) 9656 goto err_ptp_uninit; 9657 9658 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_COPPER) 9659 hdev->hw.mac.req_autoneg = hdev->hw.mac.autoneg; 9660 9661 ret = hclge_set_autoneg_speed_dup(hdev); 9662 if (ret) { 9663 dev_err(&pdev->dev, 9664 "failed to set autoneg speed duplex, ret = %d\n", ret); 9665 goto err_ptp_uninit; 9666 } 9667 9668 INIT_KFIFO(hdev->mac_tnl_log); 9669 9670 hclge_dcb_ops_set(hdev); 9671 9672 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0); 9673 INIT_DELAYED_WORK(&hdev->service_task, hclge_service_task); 9674 9675 hclge_clear_all_event_cause(hdev); 9676 hclge_clear_resetting_state(hdev); 9677 9678 /* Log and clear the hw errors those already occurred */ 9679 if (hnae3_dev_ras_imp_supported(hdev)) 9680 hclge_handle_occurred_error(hdev); 9681 else 9682 hclge_handle_all_hns_hw_errors(ae_dev); 9683 9684 /* request delayed reset for the error recovery because an immediate 9685 * global reset on a PF affecting pending initialization of other PFs 9686 */ 9687 if (ae_dev->hw_err_reset_req) { 9688 enum hnae3_reset_type reset_level; 9689 9690 reset_level = hclge_get_reset_level(ae_dev, 9691 &ae_dev->hw_err_reset_req); 9692 hclge_set_def_reset_request(ae_dev, reset_level); 9693 mod_timer(&hdev->reset_timer, jiffies + HCLGE_RESET_INTERVAL); 9694 } 9695 9696 hclge_init_rxd_adv_layout(hdev); 9697 9698 ret = hclge_init_wol(hdev); 9699 if (ret) 9700 dev_warn(&pdev->dev, 9701 "failed to wake on lan init, ret = %d\n", ret); 9702 9703 hclge_init_pfc_prevention_tout(hdev); 9704 9705 ret = hclge_devlink_init(hdev); 9706 if (ret) 9707 goto err_ptp_uninit; 9708 9709 hclge_state_init(hdev); 9710 hdev->last_reset_time = jiffies; 9711 9712 /* Enable MISC vector(vector0) */ 9713 enable_irq(hdev->misc_vector.vector_irq); 9714 hclge_enable_vector(&hdev->misc_vector, true); 9715 9716 dev_info(&hdev->pdev->dev, "%s driver initialization finished.\n", 9717 HCLGE_DRIVER_NAME); 9718 9719 hclge_task_schedule(hdev, round_jiffies_relative(HZ)); 9720 return 0; 9721 9722 err_ptp_uninit: 9723 hclge_ptp_uninit(hdev); 9724 err_mdiobus_unreg: 9725 if (hdev->hw.mac.phydev) 9726 mdiobus_unregister(hdev->hw.mac.mdio_bus); 9727 err_msi_irq_uninit: 9728 hclge_misc_irq_uninit(hdev); 9729 err_msi_uninit: 9730 pci_free_irq_vectors(pdev); 9731 err_cmd_uninit: 9732 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 9733 err_pci_uninit: 9734 pcim_iounmap(pdev, hdev->hw.hw.io_base); 9735 pci_release_regions(pdev); 9736 pci_disable_device(pdev); 9737 out: 9738 mutex_destroy(&hdev->vport_lock); 9739 return ret; 9740 } 9741 9742 static void hclge_stats_clear(struct hclge_dev *hdev) 9743 { 9744 memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats)); 9745 memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats)); 9746 } 9747 9748 static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 9749 { 9750 return hclge_config_switch_param(hdev, vf, enable, 9751 HCLGE_SWITCH_ANTI_SPOOF_MASK); 9752 } 9753 9754 static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable) 9755 { 9756 return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, 9757 HCLGE_FILTER_FE_NIC_INGRESS_B, 9758 enable, vf); 9759 } 9760 9761 static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable) 9762 { 9763 int ret; 9764 9765 ret = hclge_set_mac_spoofchk(hdev, vf, enable); 9766 if (ret) { 9767 dev_err(&hdev->pdev->dev, 9768 "Set vf %d mac spoof check %s failed, ret=%d\n", 9769 vf, str_on_off(enable), ret); 9770 return ret; 9771 } 9772 9773 ret = hclge_set_vlan_spoofchk(hdev, vf, enable); 9774 if (ret) 9775 dev_err(&hdev->pdev->dev, 9776 "Set vf %d vlan spoof check %s failed, ret=%d\n", 9777 vf, str_on_off(enable), ret); 9778 9779 return ret; 9780 } 9781 9782 static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf, 9783 bool enable) 9784 { 9785 struct hclge_vport *vport = hclge_get_vport(handle); 9786 struct hclge_dev *hdev = vport->back; 9787 u32 new_spoofchk = enable ? 1 : 0; 9788 int ret; 9789 9790 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9791 return -EOPNOTSUPP; 9792 9793 vport = hclge_get_vf_vport(hdev, vf); 9794 if (!vport) 9795 return -EINVAL; 9796 9797 if (vport->vf_info.spoofchk == new_spoofchk) 9798 return 0; 9799 9800 if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full)) 9801 dev_warn(&hdev->pdev->dev, 9802 "vf %d vlan table is full, enable spoof check may cause its packet send fail\n", 9803 vf); 9804 else if (enable && hclge_is_umv_space_full(vport, true)) 9805 dev_warn(&hdev->pdev->dev, 9806 "vf %d mac table is full, enable spoof check may cause its packet send fail\n", 9807 vf); 9808 9809 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable); 9810 if (ret) 9811 return ret; 9812 9813 vport->vf_info.spoofchk = new_spoofchk; 9814 return 0; 9815 } 9816 9817 static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev) 9818 { 9819 struct hclge_vport *vport = hdev->vport; 9820 int ret; 9821 int i; 9822 9823 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2) 9824 return 0; 9825 9826 /* resume the vf spoof check state after reset */ 9827 for (i = 0; i < hdev->num_alloc_vport; i++) { 9828 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, 9829 vport->vf_info.spoofchk); 9830 if (ret) 9831 return ret; 9832 9833 vport++; 9834 } 9835 9836 return 0; 9837 } 9838 9839 static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable) 9840 { 9841 struct hclge_vport *vport = hclge_get_vport(handle); 9842 struct hclge_dev *hdev = vport->back; 9843 u32 new_trusted = enable ? 1 : 0; 9844 9845 vport = hclge_get_vf_vport(hdev, vf); 9846 if (!vport) 9847 return -EINVAL; 9848 9849 if (vport->vf_info.trusted == new_trusted) 9850 return 0; 9851 9852 vport->vf_info.trusted = new_trusted; 9853 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 9854 hclge_task_schedule(hdev, 0); 9855 9856 return 0; 9857 } 9858 9859 static void hclge_reset_vf_rate(struct hclge_dev *hdev) 9860 { 9861 int ret; 9862 int vf; 9863 9864 /* reset vf rate to default value */ 9865 for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) { 9866 struct hclge_vport *vport = &hdev->vport[vf]; 9867 9868 vport->vf_info.max_tx_rate = 0; 9869 ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); 9870 if (ret) 9871 dev_err(&hdev->pdev->dev, 9872 "vf%d failed to reset to default, ret=%d\n", 9873 vf - HCLGE_VF_VPORT_START_NUM, ret); 9874 } 9875 } 9876 9877 static int hclge_vf_rate_param_check(struct hclge_dev *hdev, 9878 int min_tx_rate, int max_tx_rate) 9879 { 9880 if (min_tx_rate != 0 || 9881 max_tx_rate < 0 || (u32)max_tx_rate > hdev->hw.mac.max_speed) { 9882 dev_err(&hdev->pdev->dev, 9883 "min_tx_rate:%d [0], max_tx_rate:%d [0, %u]\n", 9884 min_tx_rate, max_tx_rate, hdev->hw.mac.max_speed); 9885 return -EINVAL; 9886 } 9887 9888 return 0; 9889 } 9890 9891 static int hclge_set_vf_rate(struct hnae3_handle *handle, int vf, 9892 int min_tx_rate, int max_tx_rate, bool force) 9893 { 9894 struct hclge_vport *vport = hclge_get_vport(handle); 9895 struct hclge_dev *hdev = vport->back; 9896 int ret; 9897 9898 ret = hclge_vf_rate_param_check(hdev, min_tx_rate, max_tx_rate); 9899 if (ret) 9900 return ret; 9901 9902 vport = hclge_get_vf_vport(hdev, vf); 9903 if (!vport) 9904 return -EINVAL; 9905 9906 if (!force && (u32)max_tx_rate == vport->vf_info.max_tx_rate) 9907 return 0; 9908 9909 ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); 9910 if (ret) 9911 return ret; 9912 9913 vport->vf_info.max_tx_rate = max_tx_rate; 9914 9915 return 0; 9916 } 9917 9918 static int hclge_resume_vf_rate(struct hclge_dev *hdev) 9919 { 9920 struct hnae3_handle *handle = &hdev->vport->nic; 9921 struct hclge_vport *vport; 9922 int ret; 9923 int vf; 9924 9925 /* resume the vf max_tx_rate after reset */ 9926 for (vf = 0; vf < pci_num_vf(hdev->pdev); vf++) { 9927 vport = hclge_get_vf_vport(hdev, vf); 9928 if (!vport) 9929 return -EINVAL; 9930 9931 /* zero means max rate, after reset, firmware already set it to 9932 * max rate, so just continue. 9933 */ 9934 if (!vport->vf_info.max_tx_rate) 9935 continue; 9936 9937 ret = hclge_set_vf_rate(handle, vf, 0, 9938 vport->vf_info.max_tx_rate, true); 9939 if (ret) { 9940 dev_err(&hdev->pdev->dev, 9941 "vf%d failed to resume tx_rate:%u, ret=%d\n", 9942 vf, vport->vf_info.max_tx_rate, ret); 9943 return ret; 9944 } 9945 } 9946 9947 return 0; 9948 } 9949 9950 static void hclge_reset_vport_state(struct hclge_dev *hdev) 9951 { 9952 struct hclge_vport *vport = hdev->vport; 9953 int i; 9954 9955 for (i = 0; i < hdev->num_alloc_vport; i++) { 9956 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 9957 vport++; 9958 } 9959 } 9960 9961 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) 9962 { 9963 struct hclge_dev *hdev = ae_dev->priv; 9964 struct pci_dev *pdev = ae_dev->pdev; 9965 int ret; 9966 9967 set_bit(HCLGE_STATE_DOWN, &hdev->state); 9968 9969 hclge_stats_clear(hdev); 9970 /* NOTE: pf reset needn't to clear or restore pf and vf table entry. 9971 * so here should not clean table in memory. 9972 */ 9973 if (hdev->reset_type == HNAE3_IMP_RESET || 9974 hdev->reset_type == HNAE3_GLOBAL_RESET) { 9975 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); 9976 memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full)); 9977 bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport); 9978 hclge_reset_umv_space(hdev); 9979 } 9980 9981 ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version, 9982 true, hdev->reset_pending); 9983 if (ret) { 9984 dev_err(&pdev->dev, "Cmd queue init failed\n"); 9985 return ret; 9986 } 9987 9988 ret = hclge_map_tqp(hdev); 9989 if (ret) { 9990 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); 9991 return ret; 9992 } 9993 9994 ret = hclge_mac_init(hdev); 9995 if (ret) { 9996 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); 9997 return ret; 9998 } 9999 10000 ret = hclge_set_autoneg_speed_dup(hdev); 10001 if (ret) { 10002 dev_err(&pdev->dev, 10003 "failed to set autoneg speed duplex, ret = %d\n", ret); 10004 return ret; 10005 } 10006 10007 ret = hclge_tp_port_init(hdev); 10008 if (ret) { 10009 dev_err(&pdev->dev, "failed to init tp port, ret = %d\n", 10010 ret); 10011 return ret; 10012 } 10013 10014 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); 10015 if (ret) { 10016 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); 10017 return ret; 10018 } 10019 10020 ret = hclge_config_gro(hdev); 10021 if (ret) 10022 return ret; 10023 10024 ret = hclge_init_vlan_config(hdev); 10025 if (ret) { 10026 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); 10027 return ret; 10028 } 10029 10030 hclge_reset_tc_config(hdev); 10031 10032 ret = hclge_tm_init_hw(hdev, true); 10033 if (ret) { 10034 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); 10035 return ret; 10036 } 10037 10038 ret = hclge_rss_init_hw(hdev); 10039 if (ret) { 10040 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); 10041 return ret; 10042 } 10043 10044 ret = init_mgr_tbl(hdev); 10045 if (ret) { 10046 dev_err(&pdev->dev, 10047 "failed to reinit manager table, ret = %d\n", ret); 10048 return ret; 10049 } 10050 10051 ret = hclge_init_fd_config(hdev); 10052 if (ret) { 10053 dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret); 10054 return ret; 10055 } 10056 10057 ret = hclge_ptp_init(hdev); 10058 if (ret) 10059 return ret; 10060 10061 /* Log and clear the hw errors those already occurred */ 10062 if (hnae3_dev_ras_imp_supported(hdev)) 10063 hclge_handle_occurred_error(hdev); 10064 else 10065 hclge_handle_all_hns_hw_errors(ae_dev); 10066 10067 /* Re-enable the hw error interrupts because 10068 * the interrupts get disabled on global reset. 10069 */ 10070 ret = hclge_config_nic_hw_error(hdev, true); 10071 if (ret) { 10072 dev_err(&pdev->dev, 10073 "fail(%d) to re-enable NIC hw error interrupts\n", 10074 ret); 10075 return ret; 10076 } 10077 10078 if (hdev->roce_client) { 10079 ret = hclge_config_rocee_ras_interrupt(hdev, true); 10080 if (ret) { 10081 dev_err(&pdev->dev, 10082 "fail(%d) to re-enable roce ras interrupts\n", 10083 ret); 10084 return ret; 10085 } 10086 } 10087 10088 hclge_reset_vport_state(hdev); 10089 ret = hclge_reset_vport_spoofchk(hdev); 10090 if (ret) 10091 return ret; 10092 10093 ret = hclge_resume_vf_rate(hdev); 10094 if (ret) 10095 return ret; 10096 10097 hclge_init_rxd_adv_layout(hdev); 10098 10099 ret = hclge_update_wol(hdev); 10100 if (ret) 10101 dev_warn(&pdev->dev, 10102 "failed to update wol config, ret = %d\n", ret); 10103 10104 hclge_restore_pfc_storm_prevention_tout(hdev); 10105 10106 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", 10107 HCLGE_DRIVER_NAME); 10108 10109 return 0; 10110 } 10111 10112 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) 10113 { 10114 struct hclge_dev *hdev = ae_dev->priv; 10115 struct hclge_mac *mac = &hdev->hw.mac; 10116 10117 hclge_reset_vf_rate(hdev); 10118 hclge_clear_vf_vlan(hdev); 10119 hclge_state_uninit(hdev); 10120 hclge_ptp_uninit(hdev); 10121 hclge_uninit_rxd_adv_layout(hdev); 10122 hclge_uninit_mac_table(hdev); 10123 hclge_del_all_fd_entries(hdev); 10124 10125 if (mac->phydev) 10126 mdiobus_unregister(mac->mdio_bus); 10127 10128 /* Disable MISC vector(vector0) */ 10129 hclge_enable_vector(&hdev->misc_vector, false); 10130 disable_irq(hdev->misc_vector.vector_irq); 10131 10132 /* Disable all hw interrupts */ 10133 hclge_config_mac_tnl_int(hdev, false); 10134 hclge_config_nic_hw_error(hdev, false); 10135 hclge_config_rocee_ras_interrupt(hdev, false); 10136 10137 /* Restore hw default values for the next initialization */ 10138 hclge_set_pfc_prevention_tout(&hdev->vport->nic, 10139 hdev->pfc_prevention_tout_default); 10140 10141 hclge_comm_cmd_uninit(hdev->ae_dev, &hdev->hw.hw); 10142 hclge_misc_irq_uninit(hdev); 10143 hclge_devlink_uninit(hdev); 10144 hclge_pci_uninit(hdev); 10145 hclge_uninit_vport_vlan_table(hdev); 10146 mutex_destroy(&hdev->vport_lock); 10147 ae_dev->priv = NULL; 10148 } 10149 10150 static u32 hclge_get_max_channels(struct hnae3_handle *handle) 10151 { 10152 struct hclge_vport *vport = hclge_get_vport(handle); 10153 struct hclge_dev *hdev = vport->back; 10154 10155 return min_t(u32, hdev->pf_rss_size_max, vport->alloc_tqps); 10156 } 10157 10158 static void hclge_get_channels(struct hnae3_handle *handle, 10159 struct ethtool_channels *ch) 10160 { 10161 ch->max_combined = hclge_get_max_channels(handle); 10162 ch->other_count = 1; 10163 ch->max_other = 1; 10164 ch->combined_count = handle->kinfo.rss_size; 10165 } 10166 10167 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, 10168 u16 *alloc_tqps, u16 *max_rss_size) 10169 { 10170 struct hclge_vport *vport = hclge_get_vport(handle); 10171 struct hclge_dev *hdev = vport->back; 10172 10173 *alloc_tqps = vport->alloc_tqps; 10174 *max_rss_size = hdev->pf_rss_size_max; 10175 } 10176 10177 static int hclge_set_rss_tc_mode_cfg(struct hnae3_handle *handle) 10178 { 10179 struct hclge_vport *vport = hclge_get_vport(handle); 10180 u16 tc_offset[HCLGE_MAX_TC_NUM] = {0}; 10181 struct hclge_dev *hdev = vport->back; 10182 u16 tc_size[HCLGE_MAX_TC_NUM] = {0}; 10183 u16 tc_valid[HCLGE_MAX_TC_NUM]; 10184 u16 roundup_size; 10185 unsigned int i; 10186 10187 roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size); 10188 roundup_size = ilog2(roundup_size); 10189 /* Set the RSS TC mode according to the new RSS size */ 10190 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { 10191 tc_valid[i] = 0; 10192 10193 if (!(hdev->hw_tc_map & BIT(i))) 10194 continue; 10195 10196 tc_valid[i] = 1; 10197 tc_size[i] = roundup_size; 10198 tc_offset[i] = vport->nic.kinfo.rss_size * i; 10199 } 10200 10201 return hclge_comm_set_rss_tc_mode(&hdev->hw.hw, tc_offset, tc_valid, 10202 tc_size); 10203 } 10204 10205 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num, 10206 bool rxfh_configured) 10207 { 10208 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); 10209 struct hclge_vport *vport = hclge_get_vport(handle); 10210 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; 10211 struct hclge_dev *hdev = vport->back; 10212 u16 cur_rss_size = kinfo->rss_size; 10213 u16 cur_tqps = kinfo->num_tqps; 10214 u32 *rss_indir; 10215 unsigned int i; 10216 int ret; 10217 10218 kinfo->req_rss_size = new_tqps_num; 10219 10220 ret = hclge_tm_vport_map_update(hdev); 10221 if (ret) { 10222 dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret); 10223 return ret; 10224 } 10225 10226 ret = hclge_set_rss_tc_mode_cfg(handle); 10227 if (ret) 10228 return ret; 10229 10230 /* RSS indirection table has been configured by user */ 10231 if (rxfh_configured) 10232 goto out; 10233 10234 /* Reinitializes the rss indirect table according to the new RSS size */ 10235 rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32), 10236 GFP_KERNEL); 10237 if (!rss_indir) 10238 return -ENOMEM; 10239 10240 for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) 10241 rss_indir[i] = i % kinfo->rss_size; 10242 10243 ret = hclge_set_rss(handle, rss_indir, NULL, 0); 10244 if (ret) 10245 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", 10246 ret); 10247 10248 kfree(rss_indir); 10249 10250 out: 10251 if (!ret) 10252 dev_info(&hdev->pdev->dev, 10253 "Channels changed, rss_size from %u to %u, tqps from %u to %u", 10254 cur_rss_size, kinfo->rss_size, 10255 cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc); 10256 10257 return ret; 10258 } 10259 10260 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) 10261 { 10262 struct hclge_set_led_state_cmd *req; 10263 struct hclge_desc desc; 10264 int ret; 10265 10266 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); 10267 10268 req = (struct hclge_set_led_state_cmd *)desc.data; 10269 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, 10270 HCLGE_LED_LOCATE_STATE_S, locate_led_status); 10271 10272 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10273 if (ret) 10274 dev_err(&hdev->pdev->dev, 10275 "Send set led state cmd error, ret =%d\n", ret); 10276 10277 return ret; 10278 } 10279 10280 enum hclge_led_status { 10281 HCLGE_LED_OFF, 10282 HCLGE_LED_ON, 10283 HCLGE_LED_NO_CHANGE = 0xFF, 10284 }; 10285 10286 static int hclge_set_led_id(struct hnae3_handle *handle, 10287 enum ethtool_phys_id_state status) 10288 { 10289 struct hclge_vport *vport = hclge_get_vport(handle); 10290 struct hclge_dev *hdev = vport->back; 10291 10292 switch (status) { 10293 case ETHTOOL_ID_ACTIVE: 10294 return hclge_set_led_status(hdev, HCLGE_LED_ON); 10295 case ETHTOOL_ID_INACTIVE: 10296 return hclge_set_led_status(hdev, HCLGE_LED_OFF); 10297 default: 10298 return -EINVAL; 10299 } 10300 } 10301 10302 static void hclge_get_link_mode(struct hnae3_handle *handle, 10303 unsigned long *supported, 10304 unsigned long *advertising) 10305 { 10306 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); 10307 struct hclge_vport *vport = hclge_get_vport(handle); 10308 struct hclge_dev *hdev = vport->back; 10309 unsigned int idx = 0; 10310 10311 for (; idx < size; idx++) { 10312 supported[idx] = hdev->hw.mac.supported[idx]; 10313 advertising[idx] = hdev->hw.mac.advertising[idx]; 10314 } 10315 } 10316 10317 static int hclge_gro_en(struct hnae3_handle *handle, bool enable) 10318 { 10319 struct hclge_vport *vport = hclge_get_vport(handle); 10320 struct hclge_dev *hdev = vport->back; 10321 bool gro_en_old = hdev->gro_en; 10322 int ret; 10323 10324 hdev->gro_en = enable; 10325 ret = hclge_config_gro(hdev); 10326 if (ret) 10327 hdev->gro_en = gro_en_old; 10328 10329 return ret; 10330 } 10331 10332 static int hclge_sync_vport_promisc_mode(struct hclge_vport *vport) 10333 { 10334 struct hnae3_handle *handle = &vport->nic; 10335 struct hclge_dev *hdev = vport->back; 10336 bool uc_en = false; 10337 bool mc_en = false; 10338 u8 tmp_flags; 10339 bool bc_en; 10340 int ret; 10341 10342 if (vport->last_promisc_flags != vport->overflow_promisc_flags) { 10343 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 10344 vport->last_promisc_flags = vport->overflow_promisc_flags; 10345 } 10346 10347 if (!test_and_clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 10348 &vport->state)) 10349 return 0; 10350 10351 /* for PF */ 10352 if (!vport->vport_id) { 10353 tmp_flags = handle->netdev_flags | vport->last_promisc_flags; 10354 ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE, 10355 tmp_flags & HNAE3_MPE); 10356 if (!ret) 10357 set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE, 10358 &vport->state); 10359 else 10360 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, 10361 &vport->state); 10362 return ret; 10363 } 10364 10365 /* for VF */ 10366 if (vport->vf_info.trusted) { 10367 uc_en = vport->vf_info.request_uc_en > 0 || 10368 vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE; 10369 mc_en = vport->vf_info.request_mc_en > 0 || 10370 vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE; 10371 } 10372 bc_en = vport->vf_info.request_bc_en > 0; 10373 10374 ret = hclge_cmd_set_promisc_mode(hdev, vport->vport_id, uc_en, 10375 mc_en, bc_en); 10376 if (ret) { 10377 set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state); 10378 return ret; 10379 } 10380 hclge_set_vport_vlan_fltr_change(vport); 10381 10382 return 0; 10383 } 10384 10385 static void hclge_sync_promisc_mode(struct hclge_dev *hdev) 10386 { 10387 struct hclge_vport *vport; 10388 int ret; 10389 u16 i; 10390 10391 for (i = 0; i < hdev->num_alloc_vport; i++) { 10392 vport = &hdev->vport[i]; 10393 10394 ret = hclge_sync_vport_promisc_mode(vport); 10395 if (ret) 10396 return; 10397 } 10398 } 10399 10400 static bool hclge_module_existed(struct hclge_dev *hdev) 10401 { 10402 struct hclge_desc desc; 10403 u32 existed; 10404 int ret; 10405 10406 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true); 10407 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10408 if (ret) { 10409 dev_err(&hdev->pdev->dev, 10410 "failed to get SFP exist state, ret = %d\n", ret); 10411 return false; 10412 } 10413 10414 existed = le32_to_cpu(desc.data[0]); 10415 10416 return existed != 0; 10417 } 10418 10419 /* need 6 bds(total 140 bytes) in one reading 10420 * return the number of bytes actually read, 0 means read failed. 10421 */ 10422 static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset, 10423 u32 len, u8 *data) 10424 { 10425 struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM]; 10426 struct hclge_sfp_info_bd0_cmd *sfp_info_bd0; 10427 u16 read_len; 10428 u16 copy_len; 10429 int ret; 10430 int i; 10431 10432 /* setup all 6 bds to read module eeprom info. */ 10433 for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 10434 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM, 10435 true); 10436 10437 /* bd0~bd4 need next flag */ 10438 if (i < HCLGE_SFP_INFO_CMD_NUM - 1) 10439 desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); 10440 } 10441 10442 /* setup bd0, this bd contains offset and read length. */ 10443 sfp_info_bd0 = (struct hclge_sfp_info_bd0_cmd *)desc[0].data; 10444 sfp_info_bd0->offset = cpu_to_le16((u16)offset); 10445 read_len = min_t(u16, len, HCLGE_SFP_INFO_MAX_LEN); 10446 sfp_info_bd0->read_len = cpu_to_le16(read_len); 10447 10448 ret = hclge_cmd_send(&hdev->hw, desc, i); 10449 if (ret) { 10450 dev_err(&hdev->pdev->dev, 10451 "failed to get SFP eeprom info, ret = %d\n", ret); 10452 return 0; 10453 } 10454 10455 /* copy sfp info from bd0 to out buffer. */ 10456 copy_len = min_t(u16, len, HCLGE_SFP_INFO_BD0_LEN); 10457 memcpy(data, sfp_info_bd0->data, copy_len); 10458 read_len = copy_len; 10459 10460 /* copy sfp info from bd1~bd5 to out buffer if needed. */ 10461 for (i = 1; i < HCLGE_SFP_INFO_CMD_NUM; i++) { 10462 if (read_len >= len) 10463 return read_len; 10464 10465 copy_len = min_t(u16, len - read_len, HCLGE_SFP_INFO_BDX_LEN); 10466 memcpy(data + read_len, desc[i].data, copy_len); 10467 read_len += copy_len; 10468 } 10469 10470 return read_len; 10471 } 10472 10473 static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset, 10474 u32 len, u8 *data) 10475 { 10476 struct hclge_vport *vport = hclge_get_vport(handle); 10477 struct hclge_dev *hdev = vport->back; 10478 u32 read_len = 0; 10479 u16 data_len; 10480 10481 if (hdev->hw.mac.media_type != HNAE3_MEDIA_TYPE_FIBER) 10482 return -EOPNOTSUPP; 10483 10484 if (!hclge_module_existed(hdev)) 10485 return -ENXIO; 10486 10487 while (read_len < len) { 10488 data_len = hclge_get_sfp_eeprom_info(hdev, 10489 offset + read_len, 10490 len - read_len, 10491 data + read_len); 10492 if (!data_len) 10493 return -EIO; 10494 10495 read_len += data_len; 10496 } 10497 10498 return 0; 10499 } 10500 10501 static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle, 10502 u32 *status_code) 10503 { 10504 struct hclge_vport *vport = hclge_get_vport(handle); 10505 struct hclge_dev *hdev = vport->back; 10506 struct hclge_desc desc; 10507 int ret; 10508 10509 if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) 10510 return -EOPNOTSUPP; 10511 10512 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true); 10513 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 10514 if (ret) { 10515 dev_err(&hdev->pdev->dev, 10516 "failed to query link diagnosis info, ret = %d\n", ret); 10517 return ret; 10518 } 10519 10520 *status_code = le32_to_cpu(desc.data[0]); 10521 return 0; 10522 } 10523 10524 /* After disable sriov, VF still has some config and info need clean, 10525 * which configured by PF. 10526 */ 10527 static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid) 10528 { 10529 struct hclge_dev *hdev = vport->back; 10530 struct hclge_vlan_info vlan_info; 10531 int ret; 10532 10533 clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state); 10534 clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state); 10535 vport->need_notify = 0; 10536 vport->mps = 0; 10537 10538 /* after disable sriov, clean VF rate configured by PF */ 10539 ret = hclge_tm_qs_shaper_cfg(vport, 0); 10540 if (ret) 10541 dev_err(&hdev->pdev->dev, 10542 "failed to clean vf%d rate config, ret = %d\n", 10543 vfid, ret); 10544 10545 vlan_info.vlan_tag = 0; 10546 vlan_info.qos = 0; 10547 vlan_info.vlan_proto = ETH_P_8021Q; 10548 ret = hclge_update_port_base_vlan_cfg(vport, 10549 HNAE3_PORT_BASE_VLAN_DISABLE, 10550 &vlan_info); 10551 if (ret) 10552 dev_err(&hdev->pdev->dev, 10553 "failed to clean vf%d port base vlan, ret = %d\n", 10554 vfid, ret); 10555 10556 ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false); 10557 if (ret) 10558 dev_err(&hdev->pdev->dev, 10559 "failed to clean vf%d spoof config, ret = %d\n", 10560 vfid, ret); 10561 10562 memset(&vport->vf_info, 0, sizeof(vport->vf_info)); 10563 } 10564 10565 static void hclge_clean_vport_config(struct hnae3_ae_dev *ae_dev, int num_vfs) 10566 { 10567 struct hclge_dev *hdev = ae_dev->priv; 10568 struct hclge_vport *vport; 10569 int i; 10570 10571 for (i = 0; i < num_vfs; i++) { 10572 vport = &hdev->vport[i + HCLGE_VF_VPORT_START_NUM]; 10573 10574 hclge_clear_vport_vf_info(vport, i); 10575 } 10576 } 10577 10578 static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode, 10579 u8 *priority) 10580 { 10581 struct hclge_vport *vport = hclge_get_vport(h); 10582 10583 if (dscp >= HNAE3_MAX_DSCP) 10584 return -EINVAL; 10585 10586 if (tc_mode) 10587 *tc_mode = vport->nic.kinfo.tc_map_mode; 10588 if (priority) 10589 *priority = vport->nic.kinfo.dscp_prio[dscp] == HNAE3_PRIO_ID_INVALID ? 0 : 10590 vport->nic.kinfo.dscp_prio[dscp]; 10591 10592 return 0; 10593 } 10594 10595 static const struct hnae3_ae_ops hclge_ops = { 10596 .init_ae_dev = hclge_init_ae_dev, 10597 .uninit_ae_dev = hclge_uninit_ae_dev, 10598 .reset_prepare = hclge_reset_prepare_general, 10599 .reset_done = hclge_reset_done, 10600 .init_client_instance = hclge_init_client_instance, 10601 .uninit_client_instance = hclge_uninit_client_instance, 10602 .map_ring_to_vector = hclge_map_ring_to_vector, 10603 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, 10604 .get_vector = hclge_get_vector, 10605 .put_vector = hclge_put_vector, 10606 .set_promisc_mode = hclge_set_promisc_mode, 10607 .request_update_promisc_mode = hclge_request_update_promisc_mode, 10608 .set_loopback = hclge_set_loopback, 10609 .start = hclge_ae_start, 10610 .stop = hclge_ae_stop, 10611 .client_start = hclge_client_start, 10612 .client_stop = hclge_client_stop, 10613 .get_status = hclge_get_status, 10614 .get_ksettings_an_result = hclge_get_ksettings_an_result, 10615 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, 10616 .get_media_type = hclge_get_media_type, 10617 .check_port_speed = hclge_check_port_speed, 10618 .get_fec_stats = hclge_get_fec_stats, 10619 .get_fec = hclge_get_fec, 10620 .set_fec = hclge_set_fec, 10621 .get_rss_key_size = hclge_comm_get_rss_key_size, 10622 .get_rss = hclge_get_rss, 10623 .set_rss = hclge_set_rss, 10624 .set_rss_tuple = hclge_set_rss_tuple, 10625 .get_rss_tuple = hclge_get_rss_tuple, 10626 .get_tc_size = hclge_get_tc_size, 10627 .get_mac_addr = hclge_get_mac_addr, 10628 .set_mac_addr = hclge_set_mac_addr, 10629 .do_ioctl = hclge_do_ioctl, 10630 .add_uc_addr = hclge_add_uc_addr, 10631 .rm_uc_addr = hclge_rm_uc_addr, 10632 .add_mc_addr = hclge_add_mc_addr, 10633 .rm_mc_addr = hclge_rm_mc_addr, 10634 .set_autoneg = hclge_set_autoneg, 10635 .get_autoneg = hclge_get_autoneg, 10636 .restart_autoneg = hclge_restart_autoneg, 10637 .halt_autoneg = hclge_halt_autoneg, 10638 .get_pauseparam = hclge_get_pauseparam, 10639 .set_pauseparam = hclge_set_pauseparam, 10640 .set_mtu = hclge_set_mtu, 10641 .reset_queue = hclge_reset_tqp, 10642 .get_stats = hclge_get_stats, 10643 .get_mac_stats = hclge_get_mac_stat, 10644 .update_stats = hclge_update_stats, 10645 .get_strings = hclge_get_strings, 10646 .get_sset_count = hclge_get_sset_count, 10647 .get_fw_version = hclge_get_fw_version, 10648 .get_mdix_mode = hclge_get_mdix_mode, 10649 .enable_vlan_filter = hclge_enable_vlan_filter, 10650 .set_vlan_filter = hclge_set_vlan_filter, 10651 .set_vf_vlan_filter = hclge_set_vf_vlan_filter, 10652 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, 10653 .reset_event = hclge_reset_event, 10654 .get_reset_level = hclge_get_reset_level, 10655 .set_default_reset_request = hclge_set_def_reset_request, 10656 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, 10657 .set_channels = hclge_set_channels, 10658 .get_channels = hclge_get_channels, 10659 .get_regs_len = hclge_get_regs_len, 10660 .get_regs = hclge_get_regs, 10661 .set_led_id = hclge_set_led_id, 10662 .get_link_mode = hclge_get_link_mode, 10663 .add_fd_entry = hclge_add_fd_entry, 10664 .del_fd_entry = hclge_del_fd_entry, 10665 .get_fd_rule_cnt = hclge_get_fd_rule_cnt, 10666 .get_fd_rule_info = hclge_get_fd_rule_info, 10667 .get_fd_all_rules = hclge_get_all_rules, 10668 .enable_fd = hclge_enable_fd, 10669 .add_arfs_entry = hclge_add_fd_entry_by_arfs, 10670 .dbg_get_read_func = hclge_dbg_get_read_func, 10671 .handle_hw_ras_error = hclge_handle_hw_ras_error, 10672 .get_hw_reset_stat = hclge_get_hw_reset_stat, 10673 .ae_dev_resetting = hclge_ae_dev_resetting, 10674 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt, 10675 .set_gro_en = hclge_gro_en, 10676 .get_global_queue_id = hclge_covert_handle_qid_global, 10677 .set_timer_task = hclge_set_timer_task, 10678 .mac_connect_phy = hclge_mac_connect_phy, 10679 .mac_disconnect_phy = hclge_mac_disconnect_phy, 10680 .get_vf_config = hclge_get_vf_config, 10681 .set_vf_link_state = hclge_set_vf_link_state, 10682 .set_vf_spoofchk = hclge_set_vf_spoofchk, 10683 .set_vf_trust = hclge_set_vf_trust, 10684 .set_vf_rate = hclge_set_vf_rate, 10685 .set_vf_mac = hclge_set_vf_mac, 10686 .get_module_eeprom = hclge_get_module_eeprom, 10687 .get_cmdq_stat = hclge_get_cmdq_stat, 10688 .add_cls_flower = hclge_add_cls_flower, 10689 .del_cls_flower = hclge_del_cls_flower, 10690 .cls_flower_active = hclge_is_cls_flower_active, 10691 .get_phy_link_ksettings = hclge_get_phy_link_ksettings, 10692 .set_phy_link_ksettings = hclge_set_phy_link_ksettings, 10693 .set_tx_hwts_info = hclge_ptp_set_tx_info, 10694 .get_rx_hwts = hclge_ptp_get_rx_hwts, 10695 .get_ts_info = hclge_ptp_get_ts_info, 10696 .get_link_diagnosis_info = hclge_get_link_diagnosis_info, 10697 .clean_vf_config = hclge_clean_vport_config, 10698 .get_dscp_prio = hclge_get_dscp_prio, 10699 .get_wol = hclge_get_wol, 10700 .set_wol = hclge_set_wol, 10701 .hwtstamp_get = hclge_ptp_get_cfg, 10702 .hwtstamp_set = hclge_ptp_set_cfg, 10703 .set_pfc_prevention_tout = hclge_set_pfc_prevention_tout, 10704 .get_pfc_prevention_tout = hclge_get_pfc_prevention_tout, 10705 }; 10706 10707 static struct hnae3_ae_algo ae_algo = { 10708 .ops = &hclge_ops, 10709 .pdev_id_table = ae_algo_pci_tbl, 10710 }; 10711 10712 static int __init hclge_init(void) 10713 { 10714 pr_debug("%s is initializing\n", HCLGE_NAME); 10715 10716 hclge_wq = alloc_workqueue("%s", WQ_UNBOUND, 0, 10717 HCLGE_NAME); 10718 if (!hclge_wq) { 10719 pr_err("%s: failed to create workqueue\n", HCLGE_NAME); 10720 return -ENOMEM; 10721 } 10722 10723 hnae3_register_ae_algo(&ae_algo); 10724 10725 return 0; 10726 } 10727 10728 static void __exit hclge_exit(void) 10729 { 10730 hnae3_acquire_unload_lock(); 10731 hnae3_unregister_ae_algo_prepare(&ae_algo); 10732 hnae3_unregister_ae_algo(&ae_algo); 10733 destroy_workqueue(hclge_wq); 10734 hnae3_release_unload_lock(); 10735 } 10736 module_init(hclge_init); 10737 module_exit(hclge_exit); 10738 10739 MODULE_LICENSE("GPL"); 10740 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 10741 MODULE_DESCRIPTION("HCLGE Driver"); 10742 MODULE_VERSION(HCLGE_MOD_VERSION); 10743