1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SC16IS7xx tty serial driver - common code
4 *
5 * Copyright (C) 2014 GridPoint
6 * Author: Jon Ringle <jringle@gridpoint.com>
7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
8 */
9
10 #undef DEFAULT_SYMBOL_NAMESPACE
11 #define DEFAULT_SYMBOL_NAMESPACE "SERIAL_NXP_SC16IS7XX"
12
13 #include <linux/bits.h>
14 #include <linux/cleanup.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/export.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/idr.h>
22 #include <linux/kthread.h>
23 #include <linux/module.h>
24 #include <linux/property.h>
25 #include <linux/regmap.h>
26 #include <linux/sched.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial.h>
29 #include <linux/string.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/uaccess.h>
33 #include <linux/units.h>
34
35 #include "sc16is7xx.h"
36
37 #define SC16IS7XX_MAX_DEVS 8
38
39 /* SC16IS7XX register definitions */
40 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
41 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
42 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
43 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
44 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
45 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
46 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
47 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
48 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
49 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
50 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
51 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
52 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction - only on 75x/76x */
53 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State - only on 75x/76x */
54 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable - only on 75x/76x */
55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control - only on 75x/76x */
56 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
57
58 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
59 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
60 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
61
62 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
63 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
64 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
65
66 /* Enhanced Register set: Only if (LCR == 0xBF) */
67 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
68 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
69 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
70 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
71 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
72
73 /* IER register bits */
74 #define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */
75 #define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register interrupt */
76 #define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status interrupt */
77 #define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status interrupt */
78
79 /* IER register bits - write only if (EFR[4] == 1) */
80 #define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */
81 #define SC16IS7XX_IER_XOFFI_BIT BIT(5) /* Enable Xoff interrupt */
82 #define SC16IS7XX_IER_RTSI_BIT BIT(6) /* Enable nRTS interrupt */
83 #define SC16IS7XX_IER_CTSI_BIT BIT(7) /* Enable nCTS interrupt */
84
85 /* FCR register bits */
86 #define SC16IS7XX_FCR_FIFO_BIT BIT(0) /* Enable FIFO */
87 #define SC16IS7XX_FCR_RXRESET_BIT BIT(1) /* Reset RX FIFO */
88 #define SC16IS7XX_FCR_TXRESET_BIT BIT(2) /* Reset TX FIFO */
89 #define SC16IS7XX_FCR_RXLVLL_BIT BIT(6) /* RX Trigger level LSB */
90 #define SC16IS7XX_FCR_RXLVLH_BIT BIT(7) /* RX Trigger level MSB */
91
92 /* FCR register bits - write only if (EFR[4] == 1) */
93 #define SC16IS7XX_FCR_TXLVLL_BIT BIT(4) /* TX Trigger level LSB */
94 #define SC16IS7XX_FCR_TXLVLH_BIT BIT(5) /* TX Trigger level MSB */
95
96 /* IIR register bits */
97 #define SC16IS7XX_IIR_NO_INT_BIT 0x01 /* No interrupts pending */
98 #define SC16IS7XX_IIR_ID_MASK GENMASK(5, 1) /* Mask for the interrupt ID */
99 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
100 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
101 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
102 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
103 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
104 * - only on 75x/76x
105 */
106 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
107 * - only on 75x/76x
108 */
109 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
110 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state from active
111 * (LOW) to inactive (HIGH)
112 */
113 /* LCR register bits */
114 #define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */
115 #define SC16IS7XX_LCR_LENGTH1_BIT BIT(1) /* Word length bit 1
116 *
117 * Word length bits table:
118 * 00 -> 5 bit words
119 * 01 -> 6 bit words
120 * 10 -> 7 bit words
121 * 11 -> 8 bit words
122 */
123 #define SC16IS7XX_LCR_STOPLEN_BIT BIT(2) /* STOP length bit
124 *
125 * STOP length bit table:
126 * 0 -> 1 stop bit
127 * 1 -> 1-1.5 stop bits if word length is 5,
128 * 2 stop bits otherwise
129 */
130 #define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */
131 #define SC16IS7XX_LCR_EVENPARITY_BIT BIT(4) /* Even parity bit enable */
132 #define SC16IS7XX_LCR_FORCEPARITY_BIT BIT(5) /* 9-bit multidrop parity */
133 #define SC16IS7XX_LCR_TXBREAK_BIT BIT(6) /* TX break enable */
134 #define SC16IS7XX_LCR_DLAB_BIT BIT(7) /* Divisor Latch enable */
135 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
136 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
137 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
138 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
139 #define SC16IS7XX_LCR_REG_SET_SPECIAL SC16IS7XX_LCR_DLAB_BIT /* Special reg set */
140 #define SC16IS7XX_LCR_REG_SET_ENHANCED 0xBF /* Enhanced reg set */
141
142 /* MCR register bits */
143 #define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement - only on 75x/76x */
144 #define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */
145 #define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR registers enable */
146 #define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */
147 #define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any
148 * - write enabled if (EFR[4] == 1)
149 */
150 #define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode
151 * - write enabled if (EFR[4] == 1)
152 */
153 #define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4
154 * - write enabled if (EFR[4] == 1)
155 */
156
157 /* LSR register bits */
158 #define SC16IS7XX_LSR_DR_BIT BIT(0) /* Receiver data ready */
159 #define SC16IS7XX_LSR_OE_BIT BIT(1) /* Overrun Error */
160 #define SC16IS7XX_LSR_PE_BIT BIT(2) /* Parity Error */
161 #define SC16IS7XX_LSR_FE_BIT BIT(3) /* Frame Error */
162 #define SC16IS7XX_LSR_BI_BIT BIT(4) /* Break Interrupt */
163 #define SC16IS7XX_LSR_BRK_ERROR_MASK \
164 (SC16IS7XX_LSR_OE_BIT | \
165 SC16IS7XX_LSR_PE_BIT | \
166 SC16IS7XX_LSR_FE_BIT | \
167 SC16IS7XX_LSR_BI_BIT)
168
169 #define SC16IS7XX_LSR_THRE_BIT BIT(5) /* TX holding register empty */
170 #define SC16IS7XX_LSR_TEMT_BIT BIT(6) /* Transmitter empty */
171 #define SC16IS7XX_LSR_FIFOE_BIT BIT(7) /* Fifo Error */
172
173 /* MSR register bits */
174 #define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */
175 #define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready or (IO4)
176 * - only on 75x/76x
177 */
178 #define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator or (IO7)
179 * - only on 75x/76x
180 */
181 #define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect or (IO6)
182 * - only on 75x/76x
183 */
184 #define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */
185 #define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4) - only on 75x/76x */
186 #define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7) - only on 75x/76x */
187 #define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6) - only on 75x/76x */
188
189 /*
190 * TCR register bits
191 * TCR trigger levels are available from 0 to 60 characters with a granularity
192 * of four.
193 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
194 * no built-in hardware check to make sure this condition is met. Also, the TCR
195 * must be programmed with this condition before auto RTS or software flow
196 * control is enabled to avoid spurious operation of the device.
197 */
198 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
199 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
200
201 /*
202 * TLR register bits
203 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
204 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
205 * trigger levels. Trigger levels from 4 characters to 60 characters are
206 * available with a granularity of four.
207 *
208 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the
209 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
210 * the trigger level defined in FCR is discarded. This applies to both transmit
211 * FIFO and receive FIFO trigger level setting.
212 *
213 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
214 * default state, that is, '00'.
215 */
216 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
217 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
218
219 /* IOControl register bits (Only 75x/76x) */
220 #define SC16IS7XX_IOCONTROL_LATCH_BIT BIT(0) /* Enable input latching */
221 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT BIT(1) /* Enable GPIO[7:4] as modem A pins */
222 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT BIT(2) /* Enable GPIO[3:0] as modem B pins */
223 #define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */
224
225 /* EFCR register bits */
226 #define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop mode (RS485) */
227 #define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */
228 #define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */
229 #define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */
230 #define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */
231 #define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode
232 * 0 = rate up to 115.2 kbit/s - Only 75x/76x
233 * 1 = rate up to 1.152 Mbit/s - Only 76x
234 */
235
236 /* EFR register bits */
237 #define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */
238 #define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */
239 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */
240 #define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions and writing to
241 * IER[7:4], FCR[5:4], MCR[7:5]
242 */
243 #define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3)
244 #define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2)
245 /*
246 * SWFLOW bits 3 & 2 table:
247 * 00 -> no transmitter flow control
248 * 01 -> transmitter generates XON2 and XOFF2
249 * 10 -> transmitter generates XON1 and XOFF1
250 * 11 -> transmitter generates XON1, XON2,
251 * XOFF1 and XOFF2
252 */
253 #define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1)
254 #define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0)
255 /*
256 * SWFLOW bits 1 & 0 table:
257 * 00 -> no received flow control
258 * 01 -> receiver compares XON2 and XOFF2
259 * 10 -> receiver compares XON1 and XOFF1
260 * 11 -> receiver compares XON1, XON2,
261 * XOFF1 and XOFF2
262 */
263 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
264 SC16IS7XX_EFR_AUTOCTS_BIT | \
265 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
266 SC16IS7XX_EFR_SWFLOW3_BIT | \
267 SC16IS7XX_EFR_SWFLOW2_BIT | \
268 SC16IS7XX_EFR_SWFLOW1_BIT | \
269 SC16IS7XX_EFR_SWFLOW0_BIT)
270
271
272 /* Misc definitions */
273 #define SC16IS7XX_FIFO_SIZE (64)
274 #define SC16IS7XX_GPIOS_PER_BANK 4
275
276 #define SC16IS7XX_POLL_PERIOD_MS 10
277 #define SC16IS7XX_RECONF_MD BIT(0)
278 #define SC16IS7XX_RECONF_IER BIT(1)
279 #define SC16IS7XX_RECONF_RS485 BIT(2)
280
281 struct sc16is7xx_one_config {
282 unsigned int flags;
283 u8 ier_mask;
284 u8 ier_val;
285 };
286
287 struct sc16is7xx_one {
288 struct uart_port port;
289 struct regmap *regmap;
290 struct mutex lock; /* For registers sharing same address space. */
291 struct kthread_work tx_work;
292 struct kthread_work reg_work;
293 struct kthread_delayed_work ms_work;
294 struct sc16is7xx_one_config config;
295 unsigned char buf[SC16IS7XX_FIFO_SIZE]; /* Rx buffer. */
296 unsigned int old_mctrl;
297 u8 old_lcr; /* Value before EFR access. */
298 bool irda_mode;
299 };
300
301 struct sc16is7xx_port {
302 const struct sc16is7xx_devtype *devtype;
303 struct clk *clk;
304 #ifdef CONFIG_GPIOLIB
305 struct gpio_chip gpio;
306 unsigned long gpio_valid_mask;
307 #endif
308 u8 mctrl_mask;
309 struct kthread_worker kworker;
310 struct task_struct *kworker_task;
311 struct kthread_delayed_work poll_work;
312 bool polling;
313 struct sc16is7xx_one p[];
314 };
315
316 static DEFINE_IDA(sc16is7xx_lines);
317
318 static struct uart_driver sc16is7xx_uart = {
319 .owner = THIS_MODULE,
320 .driver_name = KBUILD_MODNAME,
321 .dev_name = "ttySC",
322 .nr = SC16IS7XX_MAX_DEVS,
323 };
324
325 #define to_sc16is7xx_one(p) container_of((p), struct sc16is7xx_one, port)
326
sc16is7xx_port_read(struct uart_port * port,u8 reg)327 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
328 {
329 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
330 unsigned int val = 0;
331
332 regmap_read(one->regmap, reg, &val);
333
334 return val;
335 }
336
sc16is7xx_port_write(struct uart_port * port,u8 reg,u8 val)337 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
338 {
339 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
340
341 regmap_write(one->regmap, reg, val);
342 }
343
sc16is7xx_fifo_read(struct uart_port * port,u8 * rxbuf,unsigned int rxlen)344 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen)
345 {
346 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
347
348 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen);
349 }
350
sc16is7xx_fifo_write(struct uart_port * port,u8 * txbuf,u8 to_send)351 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send)
352 {
353 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
354
355 /*
356 * Don't send zero-length data, at least on SPI it confuses the chip
357 * delivering wrong TXLVL data.
358 */
359 if (unlikely(!to_send))
360 return;
361
362 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send);
363 }
364
sc16is7xx_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)365 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
366 u8 mask, u8 val)
367 {
368 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
369
370 regmap_update_bits(one->regmap, reg, mask, val);
371 }
372
sc16is7xx_power(struct uart_port * port,int on)373 static void sc16is7xx_power(struct uart_port *port, int on)
374 {
375 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
376 SC16IS7XX_IER_SLEEP_BIT,
377 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
378 }
379
380 /*
381 * In an amazing feat of design, the enhanced register set shares the
382 * addresses 0x02 and 0x04-0x07 with the general register set.
383 * The special register set also shares the addresses 0x00-0x01 with the
384 * general register set.
385 *
386 * Access to the enhanced or special register set is enabled by writing a magic
387 * value to the Line Control Register (LCR). When enhanced register set access
388 * is enabled, for example, any interrupt firing during this time will see the
389 * EFR where it expects the IIR to be, leading to
390 * "Unexpected interrupt" messages.
391 *
392 * Prevent this possibility by claiming a mutex when access to the enhanced
393 * or special register set is enabled, and claiming the same mutex from within
394 * the interrupt handler. This is similar to disabling the interrupt, but that
395 * doesn't work because the bulk of the interrupt processing is run as a
396 * workqueue job in thread context.
397 */
sc16is7xx_regs_lock(struct uart_port * port,u8 register_set)398 static void sc16is7xx_regs_lock(struct uart_port *port, u8 register_set)
399 {
400 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
401
402 mutex_lock(&one->lock);
403
404 /* Backup content of LCR. */
405 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
406
407 /* Enable access to the desired register set */
408 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, register_set);
409
410 /* Disable cache updates when writing to non-general registers */
411 regcache_cache_bypass(one->regmap, true);
412 }
413
sc16is7xx_regs_unlock(struct uart_port * port)414 static void sc16is7xx_regs_unlock(struct uart_port *port)
415 {
416 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
417
418 /* Re-enable cache updates when writing to general registers */
419 regcache_cache_bypass(one->regmap, false);
420
421 /* Restore original content of LCR */
422 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr);
423
424 mutex_unlock(&one->lock);
425 }
426
sc16is7xx_ier_clear(struct uart_port * port,u8 bit)427 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
428 {
429 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
430 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
431
432 lockdep_assert_held_once(&port->lock);
433
434 one->config.flags |= SC16IS7XX_RECONF_IER;
435 one->config.ier_mask |= bit;
436 one->config.ier_val &= ~bit;
437 kthread_queue_work(&s->kworker, &one->reg_work);
438 }
439
sc16is7xx_ier_set(struct uart_port * port,u8 bit)440 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
441 {
442 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
443 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
444
445 lockdep_assert_held_once(&port->lock);
446
447 one->config.flags |= SC16IS7XX_RECONF_IER;
448 one->config.ier_mask |= bit;
449 one->config.ier_val |= bit;
450 kthread_queue_work(&s->kworker, &one->reg_work);
451 }
452
sc16is7xx_stop_tx(struct uart_port * port)453 static void sc16is7xx_stop_tx(struct uart_port *port)
454 {
455 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
456 }
457
sc16is7xx_stop_rx(struct uart_port * port)458 static void sc16is7xx_stop_rx(struct uart_port *port)
459 {
460 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
461 }
462
463 const struct sc16is7xx_devtype sc16is74x_devtype = {
464 .name = "SC16IS74X",
465 .nr_gpio = 0,
466 .nr_uart = 1,
467 };
468 EXPORT_SYMBOL_GPL(sc16is74x_devtype);
469
470 const struct sc16is7xx_devtype sc16is750_devtype = {
471 .name = "SC16IS750",
472 .nr_gpio = 8,
473 .nr_uart = 1,
474 };
475 EXPORT_SYMBOL_GPL(sc16is750_devtype);
476
477 const struct sc16is7xx_devtype sc16is752_devtype = {
478 .name = "SC16IS752",
479 .nr_gpio = 8,
480 .nr_uart = 2,
481 };
482 EXPORT_SYMBOL_GPL(sc16is752_devtype);
483
484 const struct sc16is7xx_devtype sc16is760_devtype = {
485 .name = "SC16IS760",
486 .nr_gpio = 8,
487 .nr_uart = 1,
488 };
489 EXPORT_SYMBOL_GPL(sc16is760_devtype);
490
491 const struct sc16is7xx_devtype sc16is762_devtype = {
492 .name = "SC16IS762",
493 .nr_gpio = 8,
494 .nr_uart = 2,
495 };
496 EXPORT_SYMBOL_GPL(sc16is762_devtype);
497
sc16is7xx_regmap_volatile(struct device * dev,unsigned int reg)498 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
499 {
500 switch (reg) {
501 case SC16IS7XX_RHR_REG: /* Shared address space with THR & DLL */
502 case SC16IS7XX_IIR_REG: /* Shared address space with FCR & EFR */
503 case SC16IS7XX_LSR_REG: /* Shared address space with XON2 */
504 case SC16IS7XX_MSR_REG: /* Shared address space with TCR & XOFF1 */
505 case SC16IS7XX_SPR_REG: /* Shared address space with TLR & XOFF2 */
506 case SC16IS7XX_TXLVL_REG:
507 case SC16IS7XX_RXLVL_REG:
508 case SC16IS7XX_IOSTATE_REG:
509 case SC16IS7XX_IOCONTROL_REG:
510 return true;
511 default:
512 return false;
513 }
514 }
515
sc16is7xx_regmap_precious(struct device * dev,unsigned int reg)516 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
517 {
518 switch (reg) {
519 case SC16IS7XX_RHR_REG:
520 return true;
521 default:
522 return false;
523 }
524 }
525
sc16is7xx_regmap_noinc(struct device * dev,unsigned int reg)526 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
527 {
528 return reg == SC16IS7XX_RHR_REG;
529 }
530
531 /*
532 * Configure programmable baud rate generator (divisor) according to the
533 * desired baud rate.
534 *
535 * From the datasheet, the divisor is computed according to:
536 *
537 * XTAL1 input frequency
538 * -----------------------
539 * prescaler
540 * divisor = ---------------------------
541 * baud-rate x sampling-rate
542 */
sc16is7xx_set_baud(struct uart_port * port,int baud)543 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
544 {
545 unsigned int prescaler = 1;
546 unsigned long clk = port->uartclk, div = clk / 16 / baud;
547
548 if (div >= BIT(16)) {
549 prescaler = 4;
550 div /= prescaler;
551 }
552
553 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */
554 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
555 SC16IS7XX_MCR_CLKSEL_BIT,
556 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
557
558 /* Access special register set (DLL/DLH) */
559 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_SPECIAL);
560
561 /* Write the new divisor */
562 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
563 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
564
565 /* Restore access to general register set */
566 sc16is7xx_regs_unlock(port);
567
568 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
569 }
570
sc16is7xx_handle_rx(struct uart_port * port,unsigned int rxlen,unsigned int iir)571 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
572 unsigned int iir)
573 {
574 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
575 unsigned int lsr = 0, bytes_read, i;
576 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC);
577 u8 ch, flag;
578
579 if (unlikely(rxlen >= sizeof(one->buf))) {
580 dev_warn_ratelimited(port->dev,
581 "ttySC%i: Possible RX FIFO overrun: %d\n",
582 port->line, rxlen);
583 port->icount.buf_overrun++;
584 /* Ensure sanity of RX level */
585 rxlen = sizeof(one->buf);
586 }
587
588 while (rxlen) {
589 /* Only read lsr if there are possible errors in FIFO */
590 if (read_lsr) {
591 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
592 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
593 read_lsr = false; /* No errors left in FIFO */
594 } else
595 lsr = 0;
596
597 if (read_lsr) {
598 one->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
599 bytes_read = 1;
600 } else {
601 sc16is7xx_fifo_read(port, one->buf, rxlen);
602 bytes_read = rxlen;
603 }
604
605 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
606
607 port->icount.rx++;
608 flag = TTY_NORMAL;
609
610 if (unlikely(lsr)) {
611 if (lsr & SC16IS7XX_LSR_BI_BIT) {
612 port->icount.brk++;
613 if (uart_handle_break(port))
614 continue;
615 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
616 port->icount.parity++;
617 else if (lsr & SC16IS7XX_LSR_FE_BIT)
618 port->icount.frame++;
619 else if (lsr & SC16IS7XX_LSR_OE_BIT)
620 port->icount.overrun++;
621
622 lsr &= port->read_status_mask;
623 if (lsr & SC16IS7XX_LSR_BI_BIT)
624 flag = TTY_BREAK;
625 else if (lsr & SC16IS7XX_LSR_PE_BIT)
626 flag = TTY_PARITY;
627 else if (lsr & SC16IS7XX_LSR_FE_BIT)
628 flag = TTY_FRAME;
629 else if (lsr & SC16IS7XX_LSR_OE_BIT)
630 flag = TTY_OVERRUN;
631 }
632
633 for (i = 0; i < bytes_read; ++i) {
634 ch = one->buf[i];
635 if (uart_handle_sysrq_char(port, ch))
636 continue;
637
638 if (lsr & port->ignore_status_mask)
639 continue;
640
641 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
642 flag);
643 }
644 rxlen -= bytes_read;
645 }
646
647 tty_flip_buffer_push(&port->state->port);
648 }
649
sc16is7xx_handle_tx(struct uart_port * port)650 static void sc16is7xx_handle_tx(struct uart_port *port)
651 {
652 struct tty_port *tport = &port->state->port;
653 unsigned long flags;
654 unsigned int txlen;
655 unsigned char *tail;
656
657 if (unlikely(port->x_char)) {
658 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
659 port->icount.tx++;
660 port->x_char = 0;
661 return;
662 }
663
664 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
665 uart_port_lock_irqsave(port, &flags);
666 sc16is7xx_stop_tx(port);
667 uart_port_unlock_irqrestore(port, flags);
668 return;
669 }
670
671 /* Limit to space available in TX FIFO */
672 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
673 if (txlen > SC16IS7XX_FIFO_SIZE) {
674 dev_err_ratelimited(port->dev,
675 "chip reports %d free bytes in TX fifo, but it only has %d",
676 txlen, SC16IS7XX_FIFO_SIZE);
677 txlen = 0;
678 }
679
680 txlen = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen);
681 sc16is7xx_fifo_write(port, tail, txlen);
682 uart_xmit_advance(port, txlen);
683
684 uart_port_lock_irqsave(port, &flags);
685 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
686 uart_write_wakeup(port);
687
688 if (kfifo_is_empty(&tport->xmit_fifo))
689 sc16is7xx_stop_tx(port);
690 else
691 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
692 uart_port_unlock_irqrestore(port, flags);
693 }
694
sc16is7xx_get_hwmctrl(struct uart_port * port)695 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
696 {
697 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
698 unsigned int mctrl = 0;
699
700 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
701 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
702 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;
703 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;
704 return mctrl;
705 }
706
sc16is7xx_update_mlines(struct sc16is7xx_one * one)707 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
708 {
709 struct uart_port *port = &one->port;
710 unsigned long flags;
711 unsigned int status, changed;
712
713 /* Lock required as MSR address is shared with TCR and XOFF1. */
714 lockdep_assert_held_once(&one->lock);
715
716 status = sc16is7xx_get_hwmctrl(port);
717 changed = status ^ one->old_mctrl;
718
719 if (changed == 0)
720 return;
721
722 one->old_mctrl = status;
723
724 uart_port_lock_irqsave(port, &flags);
725 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
726 port->icount.rng++;
727 if (changed & TIOCM_DSR)
728 port->icount.dsr++;
729 if (changed & TIOCM_CAR)
730 uart_handle_dcd_change(port, status & TIOCM_CAR);
731 if (changed & TIOCM_CTS)
732 uart_handle_cts_change(port, status & TIOCM_CTS);
733
734 wake_up_interruptible(&port->state->port.delta_msr_wait);
735 uart_port_unlock_irqrestore(port, flags);
736 }
737
sc16is7xx_port_irq(struct sc16is7xx_port * s,int portno)738 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
739 {
740 unsigned int iir, rxlen;
741 struct uart_port *port = &s->p[portno].port;
742 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
743
744 guard(mutex)(&one->lock);
745
746 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
747 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
748 return false;
749
750 iir &= SC16IS7XX_IIR_ID_MASK;
751
752 switch (iir) {
753 case SC16IS7XX_IIR_RDI_SRC:
754 case SC16IS7XX_IIR_RLSE_SRC:
755 case SC16IS7XX_IIR_RTOI_SRC:
756 case SC16IS7XX_IIR_XOFFI_SRC:
757 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
758
759 /*
760 * There is a silicon bug that makes the chip report a
761 * time-out interrupt but no data in the FIFO. This is
762 * described in errata section 18.1.4.
763 *
764 * When this happens, read one byte from the FIFO to
765 * clear the interrupt.
766 */
767 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
768 rxlen = 1;
769
770 if (rxlen)
771 sc16is7xx_handle_rx(port, rxlen, iir);
772 break;
773 /* CTSRTS interrupt comes only when CTS goes inactive */
774 case SC16IS7XX_IIR_CTSRTS_SRC:
775 case SC16IS7XX_IIR_MSI_SRC:
776 sc16is7xx_update_mlines(one);
777 break;
778 case SC16IS7XX_IIR_THRI_SRC:
779 sc16is7xx_handle_tx(port);
780 break;
781 default:
782 dev_err_ratelimited(port->dev,
783 "ttySC%i: Unexpected interrupt: %x",
784 port->line, iir);
785 break;
786 }
787
788 return true;
789 }
790
sc16is7xx_irq(int irq,void * dev_id)791 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
792 {
793 struct sc16is7xx_port *s = dev_id;
794 bool keep_polling;
795
796 do {
797 int i;
798
799 keep_polling = false;
800
801 for (i = 0; i < s->devtype->nr_uart; ++i)
802 keep_polling |= sc16is7xx_port_irq(s, i);
803 } while (keep_polling);
804
805 return IRQ_HANDLED;
806 }
807
sc16is7xx_poll_proc(struct kthread_work * ws)808 static void sc16is7xx_poll_proc(struct kthread_work *ws)
809 {
810 struct sc16is7xx_port *s = container_of(ws, struct sc16is7xx_port, poll_work.work);
811
812 /* Reuse standard IRQ handler. Interrupt ID is unused in this context. */
813 sc16is7xx_irq(0, s);
814
815 /* Setup delay based on SC16IS7XX_POLL_PERIOD_MS */
816 kthread_queue_delayed_work(&s->kworker, &s->poll_work,
817 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS));
818 }
819
sc16is7xx_tx_proc(struct kthread_work * ws)820 static void sc16is7xx_tx_proc(struct kthread_work *ws)
821 {
822 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, tx_work);
823 struct uart_port *port = &one->port;
824
825 if ((port->rs485.flags & SER_RS485_ENABLED) &&
826 (port->rs485.delay_rts_before_send > 0))
827 msleep(port->rs485.delay_rts_before_send);
828
829 guard(mutex)(&one->lock);
830 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
831 SC16IS7XX_IER_THRI_BIT,
832 SC16IS7XX_IER_THRI_BIT);
833 sc16is7xx_handle_tx(port);
834 }
835
sc16is7xx_reconf_rs485(struct uart_port * port)836 static void sc16is7xx_reconf_rs485(struct uart_port *port)
837 {
838 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
839 SC16IS7XX_EFCR_RTS_INVERT_BIT;
840 u32 efcr = 0;
841 struct serial_rs485 *rs485 = &port->rs485;
842 unsigned long irqflags;
843
844 uart_port_lock_irqsave(port, &irqflags);
845 if (rs485->flags & SER_RS485_ENABLED) {
846 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
847
848 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
849 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
850 }
851 uart_port_unlock_irqrestore(port, irqflags);
852
853 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
854 }
855
sc16is7xx_reg_proc(struct kthread_work * ws)856 static void sc16is7xx_reg_proc(struct kthread_work *ws)
857 {
858 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, reg_work);
859 struct sc16is7xx_one_config config;
860 unsigned long irqflags;
861
862 uart_port_lock_irqsave(&one->port, &irqflags);
863 config = one->config;
864 memset(&one->config, 0, sizeof(one->config));
865 uart_port_unlock_irqrestore(&one->port, irqflags);
866
867 if (config.flags & SC16IS7XX_RECONF_MD) {
868 u8 mcr = 0;
869
870 /* Device ignores RTS setting when hardware flow is enabled */
871 if (one->port.mctrl & TIOCM_RTS)
872 mcr |= SC16IS7XX_MCR_RTS_BIT;
873
874 if (one->port.mctrl & TIOCM_DTR)
875 mcr |= SC16IS7XX_MCR_DTR_BIT;
876
877 if (one->port.mctrl & TIOCM_LOOP)
878 mcr |= SC16IS7XX_MCR_LOOP_BIT;
879 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
880 SC16IS7XX_MCR_RTS_BIT |
881 SC16IS7XX_MCR_DTR_BIT |
882 SC16IS7XX_MCR_LOOP_BIT,
883 mcr);
884 }
885
886 if (config.flags & SC16IS7XX_RECONF_IER)
887 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
888 config.ier_mask, config.ier_val);
889
890 if (config.flags & SC16IS7XX_RECONF_RS485)
891 sc16is7xx_reconf_rs485(&one->port);
892 }
893
sc16is7xx_ms_proc(struct kthread_work * ws)894 static void sc16is7xx_ms_proc(struct kthread_work *ws)
895 {
896 struct sc16is7xx_one *one = container_of(ws, struct sc16is7xx_one, ms_work.work);
897 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
898
899 if (one->port.state) {
900 scoped_guard(mutex, &one->lock)
901 sc16is7xx_update_mlines(one);
902
903 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
904 }
905 }
906
sc16is7xx_enable_ms(struct uart_port * port)907 static void sc16is7xx_enable_ms(struct uart_port *port)
908 {
909 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
910 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
911
912 lockdep_assert_held_once(&port->lock);
913
914 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
915 }
916
sc16is7xx_start_tx(struct uart_port * port)917 static void sc16is7xx_start_tx(struct uart_port *port)
918 {
919 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
920 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
921
922 kthread_queue_work(&s->kworker, &one->tx_work);
923 }
924
sc16is7xx_throttle(struct uart_port * port)925 static void sc16is7xx_throttle(struct uart_port *port)
926 {
927 unsigned long flags;
928
929 /*
930 * Hardware flow control is enabled and thus the device ignores RTS
931 * value set in MCR register. Stop reading data from RX FIFO so the
932 * AutoRTS feature will de-activate RTS output.
933 */
934 uart_port_lock_irqsave(port, &flags);
935 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
936 uart_port_unlock_irqrestore(port, flags);
937 }
938
sc16is7xx_unthrottle(struct uart_port * port)939 static void sc16is7xx_unthrottle(struct uart_port *port)
940 {
941 unsigned long flags;
942
943 uart_port_lock_irqsave(port, &flags);
944 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
945 uart_port_unlock_irqrestore(port, flags);
946 }
947
sc16is7xx_tx_empty(struct uart_port * port)948 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
949 {
950 unsigned int lsr;
951
952 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
953
954 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
955 }
956
sc16is7xx_get_mctrl(struct uart_port * port)957 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
958 {
959 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
960
961 /* Called with port lock taken so we can only return cached value */
962 return one->old_mctrl;
963 }
964
sc16is7xx_set_mctrl(struct uart_port * port,unsigned int mctrl)965 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
966 {
967 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
968 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
969
970 one->config.flags |= SC16IS7XX_RECONF_MD;
971 kthread_queue_work(&s->kworker, &one->reg_work);
972 }
973
sc16is7xx_break_ctl(struct uart_port * port,int break_state)974 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
975 {
976 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
977 SC16IS7XX_LCR_TXBREAK_BIT,
978 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
979 }
980
sc16is7xx_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)981 static void sc16is7xx_set_termios(struct uart_port *port,
982 struct ktermios *termios,
983 const struct ktermios *old)
984 {
985 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
986 unsigned int lcr, flow = 0;
987 int baud;
988 unsigned long flags;
989
990 kthread_cancel_delayed_work_sync(&one->ms_work);
991
992 /* Mask termios capabilities we don't support */
993 termios->c_cflag &= ~CMSPAR;
994
995 /* Word size */
996 switch (termios->c_cflag & CSIZE) {
997 case CS5:
998 lcr = SC16IS7XX_LCR_WORD_LEN_5;
999 break;
1000 case CS6:
1001 lcr = SC16IS7XX_LCR_WORD_LEN_6;
1002 break;
1003 case CS7:
1004 lcr = SC16IS7XX_LCR_WORD_LEN_7;
1005 break;
1006 case CS8:
1007 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1008 break;
1009 default:
1010 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1011 termios->c_cflag &= ~CSIZE;
1012 termios->c_cflag |= CS8;
1013 break;
1014 }
1015
1016 /* Parity */
1017 if (termios->c_cflag & PARENB) {
1018 lcr |= SC16IS7XX_LCR_PARITY_BIT;
1019 if (!(termios->c_cflag & PARODD))
1020 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1021 }
1022
1023 /* Stop bits */
1024 if (termios->c_cflag & CSTOPB)
1025 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1026
1027 /* Set read status mask */
1028 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1029 if (termios->c_iflag & INPCK)
1030 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1031 SC16IS7XX_LSR_FE_BIT;
1032 if (termios->c_iflag & (BRKINT | PARMRK))
1033 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1034
1035 /* Set status ignore mask */
1036 port->ignore_status_mask = 0;
1037 if (termios->c_iflag & IGNBRK)
1038 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1039 if (!(termios->c_cflag & CREAD))
1040 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1041
1042 /* Configure flow control */
1043 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1044 if (termios->c_cflag & CRTSCTS) {
1045 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1046 SC16IS7XX_EFR_AUTORTS_BIT;
1047 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1048 }
1049 if (termios->c_iflag & IXON)
1050 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1051 if (termios->c_iflag & IXOFF)
1052 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1053
1054 /* Update LCR register */
1055 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1056
1057 /* Update EFR registers */
1058 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_ENHANCED);
1059 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1060 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1061 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1062 SC16IS7XX_EFR_FLOWCTRL_BITS, flow);
1063 sc16is7xx_regs_unlock(port);
1064
1065 /* Get baud rate generator configuration */
1066 baud = uart_get_baud_rate(port, termios, old,
1067 port->uartclk / 16 / 4 / 0xffff,
1068 port->uartclk / 16);
1069
1070 /* Setup baudrate generator */
1071 baud = sc16is7xx_set_baud(port, baud);
1072
1073 uart_port_lock_irqsave(port, &flags);
1074
1075 /* Update timeout according to new baud rate */
1076 uart_update_timeout(port, termios->c_cflag, baud);
1077
1078 if (UART_ENABLE_MS(port, termios->c_cflag))
1079 sc16is7xx_enable_ms(port);
1080
1081 uart_port_unlock_irqrestore(port, flags);
1082 }
1083
sc16is7xx_config_rs485(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1084 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1085 struct serial_rs485 *rs485)
1086 {
1087 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1088 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
1089
1090 if (rs485->flags & SER_RS485_ENABLED) {
1091 /*
1092 * RTS signal is handled by HW, it's timing can't be influenced.
1093 * However, it's sometimes useful to delay TX even without RTS
1094 * control therefore we try to handle .delay_rts_before_send.
1095 */
1096 if (rs485->delay_rts_after_send)
1097 return -EINVAL;
1098 }
1099
1100 one->config.flags |= SC16IS7XX_RECONF_RS485;
1101 kthread_queue_work(&s->kworker, &one->reg_work);
1102
1103 return 0;
1104 }
1105
sc16is7xx_startup(struct uart_port * port)1106 static int sc16is7xx_startup(struct uart_port *port)
1107 {
1108 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
1109 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1110 unsigned int val;
1111 unsigned long flags;
1112
1113 sc16is7xx_power(port, 1);
1114
1115 /* Reset FIFOs */
1116 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1117 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1118 udelay(5);
1119 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1120 SC16IS7XX_FCR_FIFO_BIT);
1121
1122 /* Enable TCR/TLR */
1123 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1124 SC16IS7XX_MCR_TCRTLR_BIT,
1125 SC16IS7XX_MCR_TCRTLR_BIT);
1126
1127 /* Configure flow control levels */
1128 /* Flow control halt level 48, resume level 24 */
1129 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1130 SC16IS7XX_TCR_RX_RESUME(24) |
1131 SC16IS7XX_TCR_RX_HALT(48));
1132
1133 /* Disable TCR/TLR access */
1134 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, SC16IS7XX_MCR_TCRTLR_BIT, 0);
1135
1136 /* Now, initialize the UART */
1137 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1138
1139 /* Enable IrDA mode if requested in DT */
1140 /* This bit must be written with LCR[7] = 0 */
1141 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1142 SC16IS7XX_MCR_IRDA_BIT,
1143 one->irda_mode ? SC16IS7XX_MCR_IRDA_BIT : 0);
1144
1145 /* Enable the Rx and Tx FIFO */
1146 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1147 SC16IS7XX_EFCR_RXDISABLE_BIT |
1148 SC16IS7XX_EFCR_TXDISABLE_BIT,
1149 0);
1150
1151 /* Enable RX, CTS change and modem lines interrupts */
1152 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1153 SC16IS7XX_IER_MSI_BIT;
1154 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1155
1156 /* Enable modem status polling */
1157 uart_port_lock_irqsave(port, &flags);
1158 sc16is7xx_enable_ms(port);
1159 uart_port_unlock_irqrestore(port, flags);
1160
1161 if (s->polling)
1162 kthread_queue_delayed_work(&s->kworker, &s->poll_work,
1163 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS));
1164
1165 return 0;
1166 }
1167
sc16is7xx_shutdown(struct uart_port * port)1168 static void sc16is7xx_shutdown(struct uart_port *port)
1169 {
1170 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1171 struct sc16is7xx_one *one = to_sc16is7xx_one(port);
1172
1173 kthread_cancel_delayed_work_sync(&one->ms_work);
1174
1175 /* Disable all interrupts */
1176 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1177 /* Disable TX/RX */
1178 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1179 SC16IS7XX_EFCR_RXDISABLE_BIT |
1180 SC16IS7XX_EFCR_TXDISABLE_BIT,
1181 SC16IS7XX_EFCR_RXDISABLE_BIT |
1182 SC16IS7XX_EFCR_TXDISABLE_BIT);
1183
1184 sc16is7xx_power(port, 0);
1185
1186 if (s->polling)
1187 kthread_cancel_delayed_work_sync(&s->poll_work);
1188
1189 kthread_flush_worker(&s->kworker);
1190 }
1191
sc16is7xx_type(struct uart_port * port)1192 static const char *sc16is7xx_type(struct uart_port *port)
1193 {
1194 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1195
1196 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1197 }
1198
sc16is7xx_request_port(struct uart_port * port)1199 static int sc16is7xx_request_port(struct uart_port *port)
1200 {
1201 /* Do nothing */
1202 return 0;
1203 }
1204
sc16is7xx_config_port(struct uart_port * port,int flags)1205 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1206 {
1207 if (flags & UART_CONFIG_TYPE)
1208 port->type = PORT_SC16IS7XX;
1209 }
1210
sc16is7xx_verify_port(struct uart_port * port,struct serial_struct * s)1211 static int sc16is7xx_verify_port(struct uart_port *port,
1212 struct serial_struct *s)
1213 {
1214 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1215 return -EINVAL;
1216 if (s->irq != port->irq)
1217 return -EINVAL;
1218
1219 return 0;
1220 }
1221
sc16is7xx_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1222 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1223 unsigned int oldstate)
1224 {
1225 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1226 }
1227
sc16is7xx_null_void(struct uart_port * port)1228 static void sc16is7xx_null_void(struct uart_port *port)
1229 {
1230 /* Do nothing */
1231 }
1232
1233 static const struct uart_ops sc16is7xx_ops = {
1234 .tx_empty = sc16is7xx_tx_empty,
1235 .set_mctrl = sc16is7xx_set_mctrl,
1236 .get_mctrl = sc16is7xx_get_mctrl,
1237 .stop_tx = sc16is7xx_stop_tx,
1238 .start_tx = sc16is7xx_start_tx,
1239 .throttle = sc16is7xx_throttle,
1240 .unthrottle = sc16is7xx_unthrottle,
1241 .stop_rx = sc16is7xx_stop_rx,
1242 .enable_ms = sc16is7xx_enable_ms,
1243 .break_ctl = sc16is7xx_break_ctl,
1244 .startup = sc16is7xx_startup,
1245 .shutdown = sc16is7xx_shutdown,
1246 .set_termios = sc16is7xx_set_termios,
1247 .type = sc16is7xx_type,
1248 .request_port = sc16is7xx_request_port,
1249 .release_port = sc16is7xx_null_void,
1250 .config_port = sc16is7xx_config_port,
1251 .verify_port = sc16is7xx_verify_port,
1252 .pm = sc16is7xx_pm,
1253 };
1254
1255 #ifdef CONFIG_GPIOLIB
sc16is7xx_gpio_get(struct gpio_chip * chip,unsigned offset)1256 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1257 {
1258 unsigned int val;
1259 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1260 struct uart_port *port = &s->p[0].port;
1261
1262 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1263
1264 return !!(val & BIT(offset));
1265 }
1266
sc16is7xx_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1267 static int sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
1268 int val)
1269 {
1270 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1271 struct uart_port *port = &s->p[0].port;
1272
1273 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1274 val ? BIT(offset) : 0);
1275
1276 return 0;
1277 }
1278
sc16is7xx_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1279 static int sc16is7xx_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1280 {
1281 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1282 struct uart_port *port = &s->p[0].port;
1283 unsigned int val;
1284
1285 val = sc16is7xx_port_read(port, SC16IS7XX_IODIR_REG);
1286
1287 return val & BIT(offset) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1288 }
1289
sc16is7xx_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1290 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1291 unsigned offset)
1292 {
1293 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1294 struct uart_port *port = &s->p[0].port;
1295
1296 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1297
1298 return 0;
1299 }
1300
sc16is7xx_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)1301 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1302 unsigned offset, int val)
1303 {
1304 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1305 struct uart_port *port = &s->p[0].port;
1306 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1307
1308 if (val)
1309 state |= BIT(offset);
1310 else
1311 state &= ~BIT(offset);
1312
1313 /*
1314 * If we write IOSTATE first, and then IODIR, the output value is not
1315 * transferred to the corresponding I/O pin.
1316 * The datasheet states that each register bit will be transferred to
1317 * the corresponding I/O pin programmed as output when writing to
1318 * IOSTATE. Therefore, configure direction first with IODIR, and then
1319 * set value after with IOSTATE.
1320 */
1321 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1322 BIT(offset));
1323 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1324
1325 return 0;
1326 }
1327
sc16is7xx_gpio_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1328 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
1329 unsigned long *valid_mask,
1330 unsigned int ngpios)
1331 {
1332 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1333
1334 *valid_mask = s->gpio_valid_mask;
1335
1336 return 0;
1337 }
1338
sc16is7xx_setup_gpio_chip(struct sc16is7xx_port * s)1339 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
1340 {
1341 struct device *dev = s->p[0].port.dev;
1342
1343 if (!s->devtype->nr_gpio)
1344 return 0;
1345
1346 switch (s->mctrl_mask) {
1347 case 0:
1348 s->gpio_valid_mask = GENMASK(7, 0);
1349 break;
1350 case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
1351 s->gpio_valid_mask = GENMASK(3, 0);
1352 break;
1353 case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
1354 s->gpio_valid_mask = GENMASK(7, 4);
1355 break;
1356 default:
1357 break;
1358 }
1359
1360 if (s->gpio_valid_mask == 0)
1361 return 0;
1362
1363 s->gpio.owner = THIS_MODULE;
1364 s->gpio.parent = dev;
1365 s->gpio.label = dev_name(dev);
1366 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask;
1367 s->gpio.get_direction = sc16is7xx_gpio_get_direction;
1368 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1369 s->gpio.get = sc16is7xx_gpio_get;
1370 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1371 s->gpio.set = sc16is7xx_gpio_set;
1372 s->gpio.base = -1;
1373 s->gpio.ngpio = s->devtype->nr_gpio;
1374 s->gpio.can_sleep = 1;
1375
1376 return gpiochip_add_data(&s->gpio, s);
1377 }
1378 #endif
1379
sc16is7xx_setup_irda_ports(struct sc16is7xx_port * s)1380 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s)
1381 {
1382 int i;
1383 int ret;
1384 int count;
1385 u32 irda_port[SC16IS7XX_MAX_PORTS];
1386 struct device *dev = s->p[0].port.dev;
1387
1388 count = device_property_count_u32(dev, "irda-mode-ports");
1389 if (count < 0 || count > ARRAY_SIZE(irda_port))
1390 return;
1391
1392 ret = device_property_read_u32_array(dev, "irda-mode-ports",
1393 irda_port, count);
1394 if (ret)
1395 return;
1396
1397 for (i = 0; i < count; i++) {
1398 if (irda_port[i] < s->devtype->nr_uart)
1399 s->p[irda_port[i]].irda_mode = true;
1400 }
1401 }
1402
1403 /*
1404 * Configure ports designated to operate as modem control lines.
1405 */
sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port * s,struct regmap * regmap)1406 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
1407 struct regmap *regmap)
1408 {
1409 int i;
1410 int ret;
1411 int count;
1412 u32 mctrl_port[SC16IS7XX_MAX_PORTS];
1413 struct device *dev = s->p[0].port.dev;
1414
1415 count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
1416 if (count < 0 || count > ARRAY_SIZE(mctrl_port))
1417 return 0;
1418
1419 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
1420 mctrl_port, count);
1421 if (ret)
1422 return ret;
1423
1424 s->mctrl_mask = 0;
1425
1426 for (i = 0; i < count; i++) {
1427 /* Use GPIO lines as modem control lines */
1428 if (mctrl_port[i] == 0)
1429 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
1430 else if (mctrl_port[i] == 1)
1431 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
1432 }
1433
1434 if (s->mctrl_mask)
1435 regmap_update_bits(
1436 regmap,
1437 SC16IS7XX_IOCONTROL_REG,
1438 SC16IS7XX_IOCONTROL_MODEM_A_BIT |
1439 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);
1440
1441 return 0;
1442 }
1443
1444 static const struct serial_rs485 sc16is7xx_rs485_supported = {
1445 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
1446 .delay_rts_before_send = 1,
1447 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */
1448 };
1449
1450 /* Reset device, purging any pending irq / data */
sc16is7xx_reset(struct device * dev,struct regmap * regmap)1451 static int sc16is7xx_reset(struct device *dev, struct regmap *regmap)
1452 {
1453 struct gpio_desc *reset_gpio;
1454
1455 /* Assert reset GPIO if defined and valid. */
1456 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1457 if (IS_ERR(reset_gpio))
1458 return dev_err_probe(dev, PTR_ERR(reset_gpio), "Failed to get reset GPIO\n");
1459
1460 if (reset_gpio) {
1461 /* The minimum reset pulse width is 3 us. */
1462 fsleep(5);
1463 gpiod_set_value_cansleep(reset_gpio, 0); /* Deassert GPIO */
1464 } else {
1465 /* Software reset */
1466 regmap_write(regmap, SC16IS7XX_IOCONTROL_REG,
1467 SC16IS7XX_IOCONTROL_SRESET_BIT);
1468 }
1469
1470 return 0;
1471 }
1472
sc16is7xx_setup_channel(struct sc16is7xx_one * one,int i,bool * port_registered)1473 static int sc16is7xx_setup_channel(struct sc16is7xx_one *one, int i,
1474 bool *port_registered)
1475 {
1476 struct uart_port *port = &one->port;
1477 int ret;
1478
1479 ret = ida_alloc_max(&sc16is7xx_lines, SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL);
1480 if (ret < 0)
1481 return ret;
1482
1483 port->line = ret;
1484
1485 /* Initialize port data */
1486 port->type = PORT_SC16IS7XX;
1487 port->fifosize = SC16IS7XX_FIFO_SIZE;
1488 port->flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1489 port->iotype = UPIO_BUS;
1490 port->rs485_config = sc16is7xx_config_rs485;
1491 port->rs485_supported = sc16is7xx_rs485_supported;
1492 port->ops = &sc16is7xx_ops;
1493 one->old_mctrl = 0;
1494
1495 mutex_init(&one->lock);
1496
1497 ret = uart_get_rs485_mode(port);
1498 if (ret)
1499 return ret;
1500
1501 /* Enable access to general register set */
1502 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 0x00);
1503
1504 /* Disable all interrupts */
1505 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1506 /* Disable TX/RX */
1507 sc16is7xx_port_write(port, SC16IS7XX_EFCR_REG,
1508 SC16IS7XX_EFCR_RXDISABLE_BIT |
1509 SC16IS7XX_EFCR_TXDISABLE_BIT);
1510
1511 /* Initialize kthread work structs */
1512 kthread_init_work(&one->tx_work, sc16is7xx_tx_proc);
1513 kthread_init_work(&one->reg_work, sc16is7xx_reg_proc);
1514 kthread_init_delayed_work(&one->ms_work, sc16is7xx_ms_proc);
1515
1516 /* Register port */
1517 ret = uart_add_one_port(&sc16is7xx_uart, port);
1518 if (ret)
1519 return ret;
1520
1521 *port_registered = true;
1522
1523 sc16is7xx_regs_lock(port, SC16IS7XX_LCR_REG_SET_ENHANCED);
1524 /* Enable write access to enhanced features */
1525 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
1526 SC16IS7XX_EFR_ENABLE_BIT);
1527 sc16is7xx_regs_unlock(port);
1528
1529 /* Go to suspend mode */
1530 sc16is7xx_power(port, 0);
1531
1532 return 0;
1533 }
1534
sc16is7xx_probe(struct device * dev,const struct sc16is7xx_devtype * devtype,struct regmap * regmaps[],int irq)1535 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype,
1536 struct regmap *regmaps[], int irq)
1537 {
1538 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1539 unsigned int val;
1540 u32 uartclk = 0;
1541 int i, ret;
1542 struct sc16is7xx_port *s;
1543 bool port_registered[SC16IS7XX_MAX_PORTS];
1544
1545 for (i = 0; i < devtype->nr_uart; i++)
1546 if (IS_ERR(regmaps[i]))
1547 return PTR_ERR(regmaps[i]);
1548
1549 /*
1550 * This device does not have an identification register that would
1551 * tell us if we are really connected to the correct device.
1552 * The best we can do is to check if communication is at all possible.
1553 *
1554 * Note: regmap[0] is used in the probe function to access registers
1555 * common to all channels/ports, as it is guaranteed to be present on
1556 * all variants.
1557 */
1558 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
1559 if (ret < 0)
1560 return -EPROBE_DEFER;
1561
1562 /* Alloc port structure */
1563 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1564 if (!s)
1565 return -ENOMEM;
1566
1567 /* Always ask for fixed clock rate from a property. */
1568 device_property_read_u32(dev, "clock-frequency", &uartclk);
1569
1570 s->polling = (irq <= 0);
1571 if (s->polling)
1572 dev_dbg(dev,
1573 "No interrupt pin definition, falling back to polling mode\n");
1574
1575 s->clk = devm_clk_get_optional(dev, NULL);
1576 if (IS_ERR(s->clk))
1577 return PTR_ERR(s->clk);
1578
1579 ret = clk_prepare_enable(s->clk);
1580 if (ret)
1581 return ret;
1582
1583 freq = clk_get_rate(s->clk);
1584 if (freq == 0) {
1585 if (uartclk)
1586 freq = uartclk;
1587 if (pfreq)
1588 freq = *pfreq;
1589 if (freq)
1590 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1591 else
1592 return -EINVAL;
1593 }
1594
1595 s->devtype = devtype;
1596 dev_set_drvdata(dev, s);
1597
1598 kthread_init_worker(&s->kworker);
1599 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1600 "sc16is7xx");
1601 if (IS_ERR(s->kworker_task)) {
1602 ret = PTR_ERR(s->kworker_task);
1603 goto out_clk;
1604 }
1605 sched_set_fifo(s->kworker_task);
1606
1607 ret = sc16is7xx_reset(dev, regmaps[0]);
1608 if (ret)
1609 goto out_kthread;
1610
1611 /* Mark each port line and status as uninitialised. */
1612 for (i = 0; i < devtype->nr_uart; ++i) {
1613 s->p[i].port.line = SC16IS7XX_MAX_DEVS;
1614 port_registered[i] = false;
1615 }
1616
1617 for (i = 0; i < devtype->nr_uart; ++i) {
1618 s->p[i].port.dev = dev;
1619 s->p[i].port.irq = irq;
1620 s->p[i].port.uartclk = freq;
1621 s->p[i].regmap = regmaps[i];
1622
1623 ret = sc16is7xx_setup_channel(&s->p[i], i, &port_registered[i]);
1624 if (ret)
1625 goto out_ports;
1626 }
1627
1628 sc16is7xx_setup_irda_ports(s);
1629
1630 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
1631 if (ret)
1632 goto out_ports;
1633
1634 #ifdef CONFIG_GPIOLIB
1635 ret = sc16is7xx_setup_gpio_chip(s);
1636 if (ret)
1637 goto out_ports;
1638 #endif
1639
1640 if (s->polling) {
1641 /* Initialize kernel thread for polling */
1642 kthread_init_delayed_work(&s->poll_work, sc16is7xx_poll_proc);
1643 return 0;
1644 }
1645
1646 /*
1647 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1648 * If that succeeds, we can allow sharing the interrupt as well.
1649 * In case the interrupt controller doesn't support that, we fall
1650 * back to a non-shared falling-edge trigger.
1651 */
1652 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1653 IRQF_TRIGGER_LOW | IRQF_SHARED |
1654 IRQF_ONESHOT,
1655 dev_name(dev), s);
1656 if (!ret)
1657 return 0;
1658
1659 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1660 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1661 dev_name(dev), s);
1662 if (!ret)
1663 return 0;
1664
1665 #ifdef CONFIG_GPIOLIB
1666 if (s->gpio_valid_mask)
1667 gpiochip_remove(&s->gpio);
1668 #endif
1669
1670 out_ports:
1671 for (i = 0; i < devtype->nr_uart; i++) {
1672 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS)
1673 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1674 if (port_registered[i])
1675 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1676 }
1677
1678 out_kthread:
1679 kthread_stop(s->kworker_task);
1680
1681 out_clk:
1682 clk_disable_unprepare(s->clk);
1683
1684 return ret;
1685 }
1686 EXPORT_SYMBOL_GPL(sc16is7xx_probe);
1687
sc16is7xx_remove(struct device * dev)1688 void sc16is7xx_remove(struct device *dev)
1689 {
1690 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1691 int i;
1692
1693 #ifdef CONFIG_GPIOLIB
1694 if (s->gpio_valid_mask)
1695 gpiochip_remove(&s->gpio);
1696 #endif
1697
1698 for (i = 0; i < s->devtype->nr_uart; i++) {
1699 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1700 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1701 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1702 sc16is7xx_power(&s->p[i].port, 0);
1703 }
1704
1705 if (s->polling)
1706 kthread_cancel_delayed_work_sync(&s->poll_work);
1707
1708 kthread_flush_worker(&s->kworker);
1709 kthread_stop(s->kworker_task);
1710
1711 clk_disable_unprepare(s->clk);
1712 }
1713 EXPORT_SYMBOL_GPL(sc16is7xx_remove);
1714
1715 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1716 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1717 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1718 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1719 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1720 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1721 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1722 { }
1723 };
1724 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids);
1725 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1726
1727 const struct regmap_config sc16is7xx_regcfg = {
1728 .reg_bits = 5,
1729 .pad_bits = 3,
1730 .val_bits = 8,
1731 .cache_type = REGCACHE_MAPLE,
1732 .volatile_reg = sc16is7xx_regmap_volatile,
1733 .precious_reg = sc16is7xx_regmap_precious,
1734 .writeable_noinc_reg = sc16is7xx_regmap_noinc,
1735 .readable_noinc_reg = sc16is7xx_regmap_noinc,
1736 .max_raw_read = SC16IS7XX_FIFO_SIZE,
1737 .max_raw_write = SC16IS7XX_FIFO_SIZE,
1738 .max_register = SC16IS7XX_EFCR_REG,
1739 };
1740 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg);
1741
sc16is7xx_regmap_name(u8 port_id)1742 const char *sc16is7xx_regmap_name(u8 port_id)
1743 {
1744 switch (port_id) {
1745 case 0: return "port0";
1746 case 1: return "port1";
1747 default:
1748 WARN_ON(true);
1749 return NULL;
1750 }
1751 }
1752 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name);
1753
sc16is7xx_regmap_port_mask(unsigned int port_id)1754 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
1755 {
1756 /* CH1,CH0 are at bits 2:1. */
1757 return port_id << 1;
1758 }
1759 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask);
1760
sc16is7xx_init(void)1761 static int __init sc16is7xx_init(void)
1762 {
1763 return uart_register_driver(&sc16is7xx_uart);
1764 }
1765 module_init(sc16is7xx_init);
1766
sc16is7xx_exit(void)1767 static void __exit sc16is7xx_exit(void)
1768 {
1769 uart_unregister_driver(&sc16is7xx_uart);
1770 }
1771 module_exit(sc16is7xx_exit);
1772
1773 MODULE_LICENSE("GPL");
1774 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1775 MODULE_DESCRIPTION(KBUILD_MODNAME " tty serial core driver");
1776