1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Alexander Stein 6 */ 7 8#include <dt-bindings/net/ti-dp83867.h> 9 10/delete-node/ &encoder_rpc; 11 12/ { 13 memory@80000000 { 14 device_type = "memory"; 15 /* 16 * DRAM base addr, minimal size : 1024 MiB DRAM 17 * should be corrected by bootloader 18 */ 19 reg = <0x00000000 0x80000000 0 0x40000000>; 20 }; 21 22 clk_xtal25: clk-xtal25 { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <25000000>; 26 }; 27 28 reg_tqma8xxs_3v3: regulator-3v3 { 29 compatible = "regulator-fixed"; 30 regulator-name = "3V3"; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 regulator-always-on; 34 }; 35 36 reg_lvds0: regulator-lvds0 { 37 compatible = "regulator-fixed"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_lvds0>; 40 regulator-name = "LCD0_VDD_EN"; 41 regulator-min-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>; 43 gpio = <&lsio_gpio1 3 GPIO_ACTIVE_HIGH>; 44 enable-active-high; 45 }; 46 47 reg_lvds1: regulator-lvds1 { 48 compatible = "regulator-fixed"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_lvds1>; 51 regulator-name = "LCD1_VDD_EN"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 gpio = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; 55 enable-active-high; 56 }; 57 58 reg_sdvmmc: regulator-sdvmmc { 59 compatible = "regulator-fixed"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_sdvmmc>; 62 regulator-name = "SD1_VMMC"; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 status = "disabled"; 68 }; 69 70 reg_vmmc: regulator-vmmc { 71 compatible = "regulator-fixed"; 72 regulator-name = "MMC0_3V3"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-always-on; 76 }; 77 78 reg_vqmmc: regulator-vqmmc { 79 compatible = "regulator-fixed"; 80 regulator-name = "MMC0_1V8"; 81 regulator-min-microvolt = <1800000>; 82 regulator-max-microvolt = <1800000>; 83 regulator-always-on; 84 }; 85 86 reserved-memory { 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges; 90 91 /* 92 * global autoconfigured region for contiguous allocations 93 * must not exceed memory size and region 94 */ 95 linux,cma { 96 compatible = "shared-dma-pool"; 97 reusable; 98 size = <0 0x20000000>; 99 alloc-ranges = <0 0x96000000 0 0x30000000>; 100 linux,cma-default; 101 }; 102 103 decoder_boot: decoder-boot@84000000 { 104 reg = <0 0x84000000 0 0x2000000>; 105 no-map; 106 }; 107 108 encoder_boot: encoder-boot@86000000 { 109 reg = <0 0x86000000 0 0x200000>; 110 no-map; 111 }; 112 113 m4_reserved: m4@88000000 { 114 no-map; 115 reg = <0 0x88000000 0 0x8000000>; 116 status = "disabled"; 117 }; 118 119 vdev0vring0: vdev0vring0@90000000 { 120 compatible = "shared-dma-pool"; 121 reg = <0 0x90000000 0 0x8000>; 122 no-map; 123 status = "disabled"; 124 }; 125 126 vdev0vring1: vdev0vring1@90008000 { 127 compatible = "shared-dma-pool"; 128 reg = <0 0x90008000 0 0x8000>; 129 no-map; 130 status = "disabled"; 131 }; 132 133 vdev1vring0: vdev1vring0@90010000 { 134 compatible = "shared-dma-pool"; 135 reg = <0 0x90010000 0 0x8000>; 136 no-map; 137 status = "disabled"; 138 }; 139 140 vdev1vring1: vdev1vring1@90018000 { 141 compatible = "shared-dma-pool"; 142 reg = <0 0x90018000 0 0x8000>; 143 no-map; 144 status = "disabled"; 145 }; 146 147 rsc_table: rsc-table@900ff000 { 148 reg = <0 0x900ff000 0 0x1000>; 149 no-map; 150 status = "disabled"; 151 }; 152 153 vdevbuffer: vdevbuffer@90400000 { 154 compatible = "shared-dma-pool"; 155 reg = <0 0x90400000 0 0x100000>; 156 no-map; 157 status = "disabled"; 158 }; 159 160 decoder_rpc: decoder-rpc@92000000 { 161 reg = <0 0x92000000 0 0x100000>; 162 no-map; 163 }; 164 165 encoder_rpc: encoder-rpc@92100000 { 166 reg = <0 0x92100000 0 0x700000>; 167 no-map; 168 }; 169 }; 170 171}; 172 173/* TQMa8XxS only uses industrial grade, reduce trip points accordingly */ 174&cpu_alert0 { 175 temperature = <95000>; 176}; 177 178&cpu_crit0 { 179 temperature = <100000>; 180}; 181/* end of temperature grade adjustments */ 182 183&fec1 { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_fec1>; 186 phy-mode = "rgmii-id"; 187 phy-handle = <ðphy0>; 188 fsl,magic-packet; 189 mac-address = [ 00 00 00 00 00 00 ]; 190 191 mdio { 192 #address-cells = <1>; 193 #size-cells = <0>; 194 195 ethphy0: ethernet-phy@0 { 196 compatible = "ethernet-phy-ieee802.3-c22"; 197 reg = <0>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_ethphy0>; 200 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 201 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 202 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 203 ti,dp83867-rxctrl-strap-quirk; 204 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 205 reset-gpios = <&lsio_gpio3 22 GPIO_ACTIVE_LOW>; 206 reset-assert-us = <500000>; 207 reset-deassert-us = <50000>; 208 enet-phy-lane-no-swap; 209 interrupt-parent = <&lsio_gpio1>; 210 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 211 }; 212 213 ethphy3: ethernet-phy@3 { 214 compatible = "ethernet-phy-ieee802.3-c22"; 215 reg = <3>; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_ethphy1>; 218 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 219 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; 220 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 221 ti,dp83867-rxctrl-strap-quirk; 222 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 223 reset-gpios = <&lsio_gpio0 24 GPIO_ACTIVE_LOW>; 224 reset-assert-us = <500000>; 225 reset-deassert-us = <50000>; 226 enet-phy-lane-no-swap; 227 interrupt-parent = <&lsio_gpio1>; 228 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 229 }; 230 }; 231}; 232 233&fec2 { 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_fec2>; 236 phy-mode = "rgmii-id"; 237 phy-handle = <ðphy3>; 238 fsl,magic-packet; 239 mac-address = [ 00 00 00 00 00 00 ]; 240}; 241 242&flexcan2 { 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_can1>; 245}; 246 247&flexcan3 { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&pinctrl_can2>; 250}; 251 252&flexspi0 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_flexspi0>; 255 status = "okay"; 256 257 flash0: flash@0 { 258 compatible = "jedec,spi-nor"; 259 reg = <0>; 260 spi-max-frequency = <66000000>; 261 spi-tx-bus-width = <1>; 262 spi-rx-bus-width = <4>; 263 264 partitions { 265 compatible = "fixed-partitions"; 266 #address-cells = <1>; 267 #size-cells = <1>; 268 }; 269 }; 270}; 271 272&lsio_gpio0 { 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_smarc_fangpio>, <&pinctrl_smarc_mngtpio>; 275 276 gpio-line-names = "", "", "", "", 277 "", "", "", "", 278 "", "", "", "", 279 "LID", "SLEEP", "CHARGING#", "CHGPRSNT#", 280 "BATLOW#", "", "", "", 281 "", "SMARC_GPIO6", "SMARC_GPIO5", "", 282 "PHY3 RST#", "", "", "SPI0_CS0", 283 "", "SPI0_CS1", "", ""; 284}; 285 286&lsio_gpio1 { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&pinctrl_smarc_gpio>; 289 290 gpio-line-names = "LCD1_BLKT_EN", "LCD1_VDD_EN", "LCD0_BLKT_EN", "LCD0_VDD_EN", 291 "SMARC_GPIO0", "SMARC_GPIO1", "SMARC_GPIO2", "", 292 "SMARC_GPIO3", "SMARC_GPIO8", "SMARC_GPIO7", "SMARC_GPIO10", 293 "SMARC_GPIO9", "SMARC_GPIO4", "", "", 294 "", "", "", "", 295 "", "", "", "", 296 "", "", "", "", 297 "", "", "", ""; 298}; 299 300&lsio_gpio2 { 301 gpio-line-names = "RTC_INT#", "", "", "", 302 "", "", "", "", 303 "", "", "", "", 304 "", "", "", "", 305 "", "", "", "", 306 "", "", "", "", 307 "", "", "", "", 308 "", "", "", ""; 309}; 310 311&lsio_gpio3 { 312 gpio-line-names = "", "", "", "", 313 "", "", "", "", 314 "", "", "", "", 315 "", "", "", "", 316 "", "", "", "", 317 "", "", "PHY0_RST#", "", 318 "", "", "", "", 319 "", "", "", ""; 320}; 321 322&lsio_gpio4 { 323 gpio-line-names = "PCIE_PERST#", "", "PCIE_WAKE#", "USB_OTG1_PWR", 324 "", "", "", "", 325 "", "", "", "", 326 "", "", "", "", 327 "", "", "", "SDIO_PWR_EN", 328 "", "SDIO_WP", "SDIO_CD#", "", 329 "", "", "", "", 330 "", "", "", ""; 331}; 332 333&i2c0 { 334 clock-frequency = <100000>; 335 pinctrl-names = "default", "gpio"; 336 pinctrl-0 = <&pinctrl_lpi2c0>; 337 pinctrl-1 = <&pinctrl_lpi2c0_gpio>; 338 scl-gpios = <&lsio_gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 339 sda-gpios = <&lsio_gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 340 status = "okay"; 341 342 /* NXP SE97BTP with temperature sensor + eeprom */ 343 sensor0: temperature-sensor@1b { 344 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 345 reg = <0x1b>; 346 }; 347 348 eeprom0: eeprom@50 { 349 compatible = "atmel,24c64"; 350 reg = <0x50>; 351 pagesize = <32>; 352 vcc-supply = <®_tqma8xxs_3v3>; 353 }; 354 355 rtc1: rtc@51 { 356 compatible = "nxp,pcf85063a"; 357 reg = <0x51>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_rtc>; 360 quartz-load-femtofarads = <7000>; 361 interrupt-parent = <&lsio_gpio2>; 362 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 363 }; 364 365 eeprom1: eeprom@53 { 366 compatible = "nxp,se97b", "atmel,24c02"; 367 reg = <0x53>; 368 pagesize = <16>; 369 read-only; 370 vcc-supply = <®_tqma8xxs_3v3>; 371 }; 372 373 pcieclk: clock-generator@6a { 374 compatible = "renesas,9fgv0241"; 375 reg = <0x6a>; 376 clocks = <&clk_xtal25>; 377 #clock-cells = <1>; 378 }; 379}; 380 381&lpspi1 { 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_spi1>; 384 cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>; 385}; 386 387&lpuart0 { 388 pinctrl-names = "default"; 389 pinctrl-0 = <&pinctrl_lpuart0>; 390}; 391 392&lpuart3 { 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_lpuart3>; 395}; 396 397&mu_m0 { 398 status = "okay"; 399}; 400 401&mu1_m0 { 402 status = "okay"; 403}; 404 405&sai1 { 406 assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 407 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 408 <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 409 <&sai1_lpcg 0>; 410 assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&pinctrl_sai1>; 413 status = "okay"; 414}; 415 416&thermal_zones { 417 pmic0_thermal: pmic0-thermal { 418 polling-delay-passive = <250>; 419 polling-delay = <2000>; 420 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 421 422 trips { 423 pmic_alert0: trip0 { 424 temperature = <110000>; 425 hysteresis = <2000>; 426 type = "passive"; 427 }; 428 429 pmic_crit0: trip1 { 430 temperature = <125000>; 431 hysteresis = <2000>; 432 type = "critical"; 433 }; 434 }; 435 436 cooling-maps { 437 map0 { 438 trip = <&pmic_alert0>; 439 cooling-device = 440 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 441 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 442 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 443 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 444 }; 445 }; 446 }; 447}; 448 449&usdhc1 { 450 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 451 pinctrl-0 = <&pinctrl_usdhc1>; 452 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 453 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 454 vmmc-supply = <®_vmmc>; 455 vqmmc-supply = <®_vqmmc>; 456 bus-width = <8>; 457 non-removable; 458 no-sd; 459 no-sdio; 460 status = "okay"; 461}; 462 463&usdhc2 { 464 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 465 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 466 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 467 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 468 bus-width = <4>; 469 /* NOTE: CD / WP and VMMC support depends on mainboard */ 470}; 471 472&vpu { 473 compatible = "nxp,imx8qxp-vpu"; 474 status = "okay"; 475}; 476 477&vpu_core0 { 478 memory-region = <&decoder_boot>, <&decoder_rpc>; 479 status = "okay"; 480}; 481 482&vpu_core1 { 483 memory-region = <&encoder_boot>, <&encoder_rpc>; 484 status = "okay"; 485}; 486 487&iomuxc { 488 pinctrl_backlight_lvds0: backlight-lvds0grp { 489 fsl,pins = <IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021>; 490 }; 491 492 pinctrl_backlight_lvds1: backlight-lvds1grp { 493 fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021>; 494 }; 495 496 pinctrl_can1: can1grp { 497 fsl,pins = <IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021>, 498 <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021>; 499 }; 500 501 pinctrl_can2: can2grp { 502 fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021>, 503 <IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021>; 504 }; 505 506 pinctrl_ethphy0: ethphy0grp { 507 fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 0x00000040>, 508 <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000040>; 509 }; 510 511 pinctrl_ethphy1: ethphy1grp { 512 fsl,pins = <IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 0x00000040>, 513 <IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 0x00000040>; 514 }; 515 516 pinctrl_fec1: fec1grp { 517 fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000041>, 518 <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>, 519 <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000040>, 520 <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000040>, 521 <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000040>, 522 <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000040>, 523 <IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000040>, 524 <IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000040>, 525 <IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>, 526 <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>, 527 <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>, 528 <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>, 529 <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>, 530 <IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>; 531 }; 532 533 pinctrl_fec2: fec2grp { 534 fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000040>, 535 <IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000040>, 536 <IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000040>, 537 <IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000040>, 538 <IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000040>, 539 <IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000040>, 540 <IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000040>, 541 <IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000040>, 542 <IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000040>, 543 <IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000040>, 544 <IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000040>, 545 <IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000040>; 546 }; 547 548 pinctrl_flexspi0: flexspi0grp { 549 fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0000004d>, 550 <IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0000004d>, 551 <IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0000004d>, 552 <IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0000004d>, 553 <IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0000004d>, 554 <IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0000004d>, 555 <IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0000004d>, 556 <IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0000004d>, 557 <IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0000004d>, 558 <IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0000004d>, 559 <IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0000004d>, 560 <IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0000004d>, 561 <IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0000004d>, 562 <IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0000004d>; 563 }; 564 565 pinctrl_smarc_gpio: smarcgpiogrp { 566 fsl,pins = /* SMARC_GPIO0 / CAM0_PWR# */ 567 <IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 0x00000021>, 568 /* SMARC_GPIO1 / CAM1_PWR# */ 569 <IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 0x00000021>, 570 /* SMARC_GPIO2 / CAM0_RST# */ 571 <IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 0x00000021>, 572 /* SMARC_GPIO3 / CAM1_RST# */ 573 <IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x00000021>, 574 /* SMARC_GPIO4 / HDA_RST# */ 575 <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 0x00000021>, 576 /* SMARC_GPIO7 */ 577 <IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0x00000021>, 578 /* SMARC_GPIO8 */ 579 <IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0x00000021>, 580 /* SMARC_GPIO9 */ 581 <IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 0x00000021>, 582 /* SMARC_GPIO10 */ 583 <IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 0x00000021>; 584 }; 585 586 pinctrl_smarc_fangpio: smarcfangpiogrp { 587 fsl,pins = /* SMARC_GPIO5 */ 588 <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x00000021>, 589 /* SMARC_GPIO6 */ 590 <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x00000021>; 591 }; 592 593 pinctrl_smarc_mngtpio: smarcmngtgpiogrp { 594 fsl,pins = /* SMARC BATLOW# */ 595 <IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x00000021>, 596 /* SMARC SLEEP */ 597 <IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 0x00000021>, 598 /* SMARC CHGPRSNT# */ 599 <IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 0x00000021>, 600 /* SMARC CHARGING# */ 601 <IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 0x00000021>, 602 /* SMARC LID */ 603 <IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 0x00000021>; 604 }; 605 606 pinctrl_lvds0: lbdpanel0grp { 607 fsl,pins = /* LCD PWR */ 608 <IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x00000021>; 609 }; 610 611 pinctrl_lvds1: lbdpanel1grp { 612 fsl,pins = /* LCD PWR */ 613 <IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x00000021>; 614 }; 615 616 pinctrl_lpi2c0: lpi2c0grp { 617 fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021>, 618 <IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021>; 619 }; 620 621 pinctrl_lpi2c0_gpio: lpi2c0gpiogrp { 622 fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0x00000021>, 623 <IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0x00000021>; 624 }; 625 626 pinctrl_lpuart0: lpuart0grp { 627 fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>, 628 <IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020>, 629 <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>, 630 <IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020>; 631 }; 632 633 pinctrl_lpuart3: lpuart3grp { 634 fsl,pins = <IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX 0x06000020>, 635 <IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX 0x06000020>; 636 }; 637 638 pinctrl_i2c0_mipi_lvds0: mipi-lvds0-i2c0grp { 639 fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0x06000021>, 640 <IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0x06000021>; 641 }; 642 643 pinctrl_i2c0_gpio_mipi_lvds0: mipi-lvds0-i2c0-gpiogrp { 644 fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 0x0000021>, 645 <IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 0x0000021>; 646 }; 647 648 pinctrl_pcieb: pcieagrp { 649 fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>, 650 <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>, 651 <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>; 652 }; 653 654 pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp { 655 fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000021>; 656 }; 657 658 pinctrl_pwm_mipi_lvds1: mipi-lvds1-pwmgrp { 659 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000021>; 660 }; 661 662 pinctrl_rtc: rtcgrp { 663 fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000021>; 664 }; 665 666 pinctrl_usdhc1: usdhc1grp { 667 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>, 668 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>, 669 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>, 670 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>, 671 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>, 672 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>, 673 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>, 674 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>, 675 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>, 676 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>, 677 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040>; 678 }; 679 680 pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { 681 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 682 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>, 683 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>, 684 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>, 685 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>, 686 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>, 687 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>, 688 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>, 689 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>, 690 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>, 691 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>; 692 }; 693 694 pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { 695 fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 696 <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>, 697 <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>, 698 <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>, 699 <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>, 700 <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>, 701 <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>, 702 <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>, 703 <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>, 704 <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>, 705 <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041>; 706 }; 707 708 pinctrl_sdvmmc: sdvmmcgrp { 709 fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021>; 710 }; 711 712 pinctrl_spi1: spi1grp { 713 fsl,pins = /* PD + PDRV Low + INOUT - MEK has 0x0600004c */ 714 <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI 0x06000041>, 715 <IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO 0x06000041>, 716 <IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK 0x06000041>, 717 <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x00000021>, 718 <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x00000021>; 719 }; 720 721 pinctrl_sai1: sai1grp { 722 fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x06000040>, 723 <IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040>, 724 <IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040>, 725 <IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000040>, 726 <IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000040>; 727 }; 728 729 pinctrl_usbotg1: usbotg1grp { 730 fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>, 731 <IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>; 732 }; 733 734 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 735 fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021>, 736 <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021>; 737 }; 738 739 pinctrl_usdhc2: usdhc2grp { 740 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, 741 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>, 742 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>, 743 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>, 744 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>, 745 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>, 746 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 747 }; 748 749 pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { 750 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, 751 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, 752 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, 753 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, 754 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, 755 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, 756 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>; 757 }; 758 759 pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { 760 fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, 761 <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, 762 <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, 763 <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, 764 <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, 765 <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, 766 <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>; 767 }; 768}; 769