1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2021 Analog Devices, Inc.
4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/regmap.h>
9 #include <linux/spi/spi.h>
10
11 #include <linux/iio/iio.h>
12
13 #include "adxl367.h"
14
15 #define ADXL367_SPI_WRITE_COMMAND 0x0A
16 #define ADXL367_SPI_READ_COMMAND 0x0B
17 #define ADXL367_SPI_FIFO_COMMAND 0x0D
18
19 struct adxl367_spi_state {
20 struct spi_device *spi;
21
22 struct spi_message reg_write_msg;
23 struct spi_transfer reg_write_xfer[2];
24
25 struct spi_message reg_read_msg;
26 struct spi_transfer reg_read_xfer[2];
27
28 struct spi_message fifo_msg;
29 struct spi_transfer fifo_xfer[2];
30
31 /*
32 * DMA (thus cache coherency maintenance) may require the
33 * transfer buffers live in their own cache lines.
34 */
35 u8 reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN);
36 u8 reg_read_tx_buf[2];
37 u8 fifo_tx_buf[1];
38 };
39
adxl367_read_fifo(void * context,__be16 * fifo_buf,unsigned int fifo_entries)40 static int adxl367_read_fifo(void *context, __be16 *fifo_buf,
41 unsigned int fifo_entries)
42 {
43 struct adxl367_spi_state *st = context;
44
45 st->fifo_xfer[1].rx_buf = fifo_buf;
46 st->fifo_xfer[1].len = fifo_entries * sizeof(*fifo_buf);
47
48 return spi_sync(st->spi, &st->fifo_msg);
49 }
50
adxl367_read(void * context,const void * reg_buf,size_t reg_size,void * val_buf,size_t val_size)51 static int adxl367_read(void *context, const void *reg_buf, size_t reg_size,
52 void *val_buf, size_t val_size)
53 {
54 struct adxl367_spi_state *st = context;
55 u8 reg = ((const u8 *)reg_buf)[0];
56
57 st->reg_read_tx_buf[1] = reg;
58 st->reg_read_xfer[1].rx_buf = val_buf;
59 st->reg_read_xfer[1].len = val_size;
60
61 return spi_sync(st->spi, &st->reg_read_msg);
62 }
63
adxl367_write(void * context,const void * val_buf,size_t val_size)64 static int adxl367_write(void *context, const void *val_buf, size_t val_size)
65 {
66 struct adxl367_spi_state *st = context;
67
68 st->reg_write_xfer[1].tx_buf = val_buf;
69 st->reg_write_xfer[1].len = val_size;
70
71 return spi_sync(st->spi, &st->reg_write_msg);
72 }
73
74 static const struct regmap_bus adxl367_spi_regmap_bus = {
75 .read = adxl367_read,
76 .write = adxl367_write,
77 };
78
79 static const struct regmap_config adxl367_spi_regmap_config = {
80 .reg_bits = 8,
81 .val_bits = 8,
82 };
83
84 static const struct adxl367_ops adxl367_spi_ops = {
85 .read_fifo = adxl367_read_fifo,
86 };
87
adxl367_spi_probe(struct spi_device * spi)88 static int adxl367_spi_probe(struct spi_device *spi)
89 {
90 struct adxl367_spi_state *st;
91 struct regmap *regmap;
92
93 st = devm_kzalloc(&spi->dev, sizeof(*st), GFP_KERNEL);
94 if (!st)
95 return -ENOMEM;
96
97 st->spi = spi;
98
99 /*
100 * Xfer: [XFR1] [ XFR2 ]
101 * Master: 0x0A ADDR DATA0 DATA1 ... DATAN
102 * Slave: .... ..........................
103 */
104 st->reg_write_tx_buf[0] = ADXL367_SPI_WRITE_COMMAND;
105 st->reg_write_xfer[0].tx_buf = st->reg_write_tx_buf;
106 st->reg_write_xfer[0].len = sizeof(st->reg_write_tx_buf);
107 spi_message_init_with_transfers(&st->reg_write_msg,
108 st->reg_write_xfer, 2);
109
110 /*
111 * Xfer: [ XFR1 ] [ XFR2 ]
112 * Master: 0x0B ADDR .....................
113 * Slave: ......... DATA0 DATA1 ... DATAN
114 */
115 st->reg_read_tx_buf[0] = ADXL367_SPI_READ_COMMAND;
116 st->reg_read_xfer[0].tx_buf = st->reg_read_tx_buf;
117 st->reg_read_xfer[0].len = sizeof(st->reg_read_tx_buf);
118 spi_message_init_with_transfers(&st->reg_read_msg,
119 st->reg_read_xfer, 2);
120
121 /*
122 * Xfer: [XFR1] [ XFR2 ]
123 * Master: 0x0D .....................
124 * Slave: .... DATA0 DATA1 ... DATAN
125 */
126 st->fifo_tx_buf[0] = ADXL367_SPI_FIFO_COMMAND;
127 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;
128 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);
129 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, 2);
130
131 regmap = devm_regmap_init(&spi->dev, &adxl367_spi_regmap_bus, st,
132 &adxl367_spi_regmap_config);
133 if (IS_ERR(regmap))
134 return PTR_ERR(regmap);
135
136 return adxl367_probe(&spi->dev, &adxl367_spi_ops, st, regmap, spi->irq);
137 }
138
139 static const struct spi_device_id adxl367_spi_id[] = {
140 { .name = "adxl367" },
141 { }
142 };
143 MODULE_DEVICE_TABLE(spi, adxl367_spi_id);
144
145 static const struct of_device_id adxl367_of_match[] = {
146 { .compatible = "adi,adxl367" },
147 { }
148 };
149 MODULE_DEVICE_TABLE(of, adxl367_of_match);
150
151 static struct spi_driver adxl367_spi_driver = {
152 .driver = {
153 .name = "adxl367_spi",
154 .of_match_table = adxl367_of_match,
155 },
156 .probe = adxl367_spi_probe,
157 .id_table = adxl367_spi_id,
158 };
159
160 module_spi_driver(adxl367_spi_driver);
161
162 MODULE_IMPORT_NS("IIO_ADXL367");
163 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
164 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer SPI driver");
165 MODULE_LICENSE("GPL");
166