1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2014, The Linux Foundation. All rights reserved. 3 */ 4 #include <linux/bits.h> 5 #include <linux/clk.h> 6 #include <linux/delay.h> 7 #include <linux/interrupt.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/platform_device.h> 14 #include <linux/watchdog.h> 15 16 enum wdt_reg { 17 WDT_RST, 18 WDT_EN, 19 WDT_STS, 20 WDT_BARK_TIME, 21 WDT_BITE_TIME, 22 }; 23 24 #define QCOM_WDT_ENABLE BIT(0) 25 26 static const u32 reg_offset_data_apcs_tmr[] = { 27 [WDT_RST] = 0x38, 28 [WDT_EN] = 0x40, 29 [WDT_STS] = 0x44, 30 [WDT_BARK_TIME] = 0x4C, 31 [WDT_BITE_TIME] = 0x5C, 32 }; 33 34 static const u32 reg_offset_data_kpss[] = { 35 [WDT_RST] = 0x4, 36 [WDT_EN] = 0x8, 37 [WDT_STS] = 0xC, 38 [WDT_BARK_TIME] = 0x10, 39 [WDT_BITE_TIME] = 0x14, 40 }; 41 42 struct qcom_wdt_match_data { 43 const u32 *offset; 44 bool pretimeout; 45 u32 max_tick_count; 46 u32 wdt_reason_val; 47 }; 48 49 struct qcom_wdt { 50 struct watchdog_device wdd; 51 unsigned long rate; 52 void __iomem *base; 53 const u32 *layout; 54 }; 55 56 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) 57 { 58 return wdt->base + wdt->layout[reg]; 59 } 60 61 static inline 62 struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd) 63 { 64 return container_of(wdd, struct qcom_wdt, wdd); 65 } 66 67 static irqreturn_t qcom_wdt_isr(int irq, void *arg) 68 { 69 struct watchdog_device *wdd = arg; 70 71 watchdog_notify_pretimeout(wdd); 72 73 return IRQ_HANDLED; 74 } 75 76 static int qcom_wdt_start(struct watchdog_device *wdd) 77 { 78 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 79 unsigned int bark = wdd->timeout - wdd->pretimeout; 80 81 writel(0, wdt_addr(wdt, WDT_EN)); 82 writel(1, wdt_addr(wdt, WDT_RST)); 83 writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); 84 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); 85 writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN)); 86 return 0; 87 } 88 89 static int qcom_wdt_stop(struct watchdog_device *wdd) 90 { 91 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 92 93 writel(0, wdt_addr(wdt, WDT_EN)); 94 return 0; 95 } 96 97 static int qcom_wdt_ping(struct watchdog_device *wdd) 98 { 99 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 100 101 writel(1, wdt_addr(wdt, WDT_RST)); 102 return 0; 103 } 104 105 static int qcom_wdt_set_timeout(struct watchdog_device *wdd, 106 unsigned int timeout) 107 { 108 wdd->timeout = timeout; 109 return qcom_wdt_start(wdd); 110 } 111 112 static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd, 113 unsigned int timeout) 114 { 115 wdd->pretimeout = timeout; 116 return qcom_wdt_start(wdd); 117 } 118 119 static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action, 120 void *data) 121 { 122 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 123 u32 timeout; 124 125 /* 126 * Trigger watchdog bite: 127 * Setup BITE_TIME to be 128ms, and enable WDT. 128 */ 129 timeout = 128 * wdt->rate / 1000; 130 131 writel(0, wdt_addr(wdt, WDT_EN)); 132 writel(1, wdt_addr(wdt, WDT_RST)); 133 writel(timeout, wdt_addr(wdt, WDT_BARK_TIME)); 134 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME)); 135 writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN)); 136 137 /* 138 * Actually make sure the above sequence hits hardware before sleeping. 139 */ 140 wmb(); 141 142 mdelay(150); 143 return 0; 144 } 145 146 static int qcom_wdt_is_running(struct watchdog_device *wdd) 147 { 148 struct qcom_wdt *wdt = to_qcom_wdt(wdd); 149 150 return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE); 151 } 152 153 static const struct watchdog_ops qcom_wdt_ops = { 154 .start = qcom_wdt_start, 155 .stop = qcom_wdt_stop, 156 .ping = qcom_wdt_ping, 157 .set_timeout = qcom_wdt_set_timeout, 158 .set_pretimeout = qcom_wdt_set_pretimeout, 159 .restart = qcom_wdt_restart, 160 .owner = THIS_MODULE, 161 }; 162 163 static const struct watchdog_info qcom_wdt_info = { 164 .options = WDIOF_KEEPALIVEPING 165 | WDIOF_MAGICCLOSE 166 | WDIOF_SETTIMEOUT 167 | WDIOF_CARDRESET, 168 .identity = KBUILD_MODNAME, 169 }; 170 171 static const struct watchdog_info qcom_wdt_pt_info = { 172 .options = WDIOF_KEEPALIVEPING 173 | WDIOF_MAGICCLOSE 174 | WDIOF_SETTIMEOUT 175 | WDIOF_PRETIMEOUT 176 | WDIOF_CARDRESET, 177 .identity = KBUILD_MODNAME, 178 }; 179 180 static const struct qcom_wdt_match_data match_data_apcs_tmr = { 181 .offset = reg_offset_data_apcs_tmr, 182 .pretimeout = false, 183 .max_tick_count = 0x10000000U, 184 }; 185 186 static const struct qcom_wdt_match_data match_data_ipq5424 = { 187 .offset = reg_offset_data_kpss, 188 .pretimeout = true, 189 .max_tick_count = 0xFFFFFU, 190 .wdt_reason_val = 5, 191 }; 192 193 static const struct qcom_wdt_match_data match_data_kpss = { 194 .offset = reg_offset_data_kpss, 195 .pretimeout = true, 196 .max_tick_count = 0xFFFFFU, 197 }; 198 199 static int qcom_wdt_get_bootstatus(struct device *dev, struct qcom_wdt *wdt, 200 u32 val) 201 { 202 struct device_node *imem; 203 struct resource res; 204 void __iomem *addr; 205 int ret; 206 207 imem = of_parse_phandle(dev->of_node, "sram", 0); 208 if (!imem) { 209 /* Read the EXPIRED_STATUS bit as a fallback */ 210 if (readl(wdt_addr(wdt, WDT_STS)) & 1) 211 wdt->wdd.bootstatus = WDIOF_CARDRESET; 212 213 return 0; 214 } 215 216 ret = of_address_to_resource(imem, 0, &res); 217 of_node_put(imem); 218 if (ret) 219 return ret; 220 221 addr = ioremap(res.start, resource_size(&res)); 222 if (!addr) 223 return -ENOMEM; 224 225 if (readl(addr) == val) 226 wdt->wdd.bootstatus = WDIOF_CARDRESET; 227 228 iounmap(addr); 229 230 return 0; 231 } 232 233 static int qcom_wdt_probe(struct platform_device *pdev) 234 { 235 struct device *dev = &pdev->dev; 236 struct qcom_wdt *wdt; 237 struct resource *res; 238 struct device_node *np = dev->of_node; 239 const struct qcom_wdt_match_data *data; 240 u32 percpu_offset; 241 int irq, ret; 242 struct clk *clk; 243 244 data = of_device_get_match_data(dev); 245 if (!data) { 246 dev_err(dev, "Unsupported QCOM WDT module\n"); 247 return -ENODEV; 248 } 249 250 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); 251 if (!wdt) 252 return -ENOMEM; 253 254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 255 if (!res) 256 return -ENOMEM; 257 258 /* We use CPU0's DGT for the watchdog */ 259 if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) 260 percpu_offset = 0; 261 262 res->start += percpu_offset; 263 res->end += percpu_offset; 264 265 wdt->base = devm_ioremap_resource(dev, res); 266 if (IS_ERR(wdt->base)) 267 return PTR_ERR(wdt->base); 268 269 clk = devm_clk_get_enabled(dev, NULL); 270 if (IS_ERR(clk)) { 271 dev_err(dev, "failed to get input clock\n"); 272 return PTR_ERR(clk); 273 } 274 275 /* 276 * We use the clock rate to calculate the max timeout, so ensure it's 277 * not zero to avoid a divide-by-zero exception. 278 * 279 * WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such 280 * that it would bite before a second elapses it's usefulness is 281 * limited. Bail if this is the case. 282 */ 283 wdt->rate = clk_get_rate(clk); 284 if (wdt->rate == 0 || 285 wdt->rate > data->max_tick_count) { 286 dev_err(dev, "invalid clock rate\n"); 287 return -EINVAL; 288 } 289 290 /* check if there is pretimeout support */ 291 irq = platform_get_irq_optional(pdev, 0); 292 if (data->pretimeout && irq > 0) { 293 ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0, 294 "wdt_bark", &wdt->wdd); 295 if (ret) 296 return ret; 297 298 wdt->wdd.info = &qcom_wdt_pt_info; 299 wdt->wdd.pretimeout = 1; 300 } else { 301 if (irq == -EPROBE_DEFER) 302 return -EPROBE_DEFER; 303 304 wdt->wdd.info = &qcom_wdt_info; 305 } 306 307 wdt->wdd.ops = &qcom_wdt_ops; 308 wdt->wdd.min_timeout = 1; 309 wdt->wdd.max_timeout = data->max_tick_count / wdt->rate; 310 wdt->wdd.parent = dev; 311 wdt->layout = data->offset; 312 313 ret = qcom_wdt_get_bootstatus(dev, wdt, data->wdt_reason_val); 314 if (ret) 315 dev_err(dev, "failed to get the bootstatus, %d\n", ret); 316 317 /* 318 * If 'timeout-sec' unspecified in devicetree, assume a 30 second 319 * default, unless the max timeout is less than 30 seconds, then use 320 * the max instead. 321 */ 322 wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U); 323 watchdog_init_timeout(&wdt->wdd, 0, dev); 324 325 /* 326 * If WDT is already running, call WDT start which 327 * will stop the WDT, set timeouts as bootloader 328 * might use different ones and set running bit 329 * to inform the WDT subsystem to ping the WDT 330 */ 331 if (qcom_wdt_is_running(&wdt->wdd)) { 332 qcom_wdt_start(&wdt->wdd); 333 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); 334 } 335 336 ret = devm_watchdog_register_device(dev, &wdt->wdd); 337 if (ret) 338 return ret; 339 340 platform_set_drvdata(pdev, wdt); 341 return 0; 342 } 343 344 static int __maybe_unused qcom_wdt_suspend(struct device *dev) 345 { 346 struct qcom_wdt *wdt = dev_get_drvdata(dev); 347 348 if (watchdog_active(&wdt->wdd)) 349 qcom_wdt_stop(&wdt->wdd); 350 351 return 0; 352 } 353 354 static int __maybe_unused qcom_wdt_resume(struct device *dev) 355 { 356 struct qcom_wdt *wdt = dev_get_drvdata(dev); 357 358 if (watchdog_active(&wdt->wdd)) 359 qcom_wdt_start(&wdt->wdd); 360 361 return 0; 362 } 363 364 static const struct dev_pm_ops qcom_wdt_pm_ops = { 365 SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume) 366 }; 367 368 static const struct of_device_id qcom_wdt_of_table[] = { 369 { .compatible = "qcom,apss-wdt-ipq5424", .data = &match_data_ipq5424 }, 370 { .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr }, 371 { .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr }, 372 { .compatible = "qcom,kpss-wdt", .data = &match_data_kpss }, 373 { }, 374 }; 375 MODULE_DEVICE_TABLE(of, qcom_wdt_of_table); 376 377 static struct platform_driver qcom_watchdog_driver = { 378 .probe = qcom_wdt_probe, 379 .driver = { 380 .name = KBUILD_MODNAME, 381 .of_match_table = qcom_wdt_of_table, 382 .pm = &qcom_wdt_pm_ops, 383 }, 384 }; 385 module_platform_driver(qcom_watchdog_driver); 386 387 MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver"); 388 MODULE_LICENSE("GPL v2"); 389