| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_reg.h | 37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
47 #define FN(reg_name, field) FD(reg_name##__##field) argument
58 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
61 #define REG_SET(reg_name, initial_val, field, val) \ argument
85 #define REG_UPDATE_N(reg_name, n, ...)\ argument
88 #define REG_UPDATE(reg_name, field, val) \ argument
111 #define REG_GET(reg_name, field, val) \ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
| H A D | hw_factory_dcn32.c | 59 #define REG(reg_name)\ argument
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
65 #define REGI(reg_name, block, id)\ argument
69 #define SF(reg_name, field_name, post_fix)\ argument
101 #define SF_DDC(reg_name, field_name, post_fix)\ argument
169 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
| H A D | hw_factory_dcn30.c | 66 #define REG(reg_name)\ argument
69 #define SF_HPD(reg_name, field_name, post_fix)\ argument
72 #define REGI(reg_name, block, id)\ argument
76 #define SF(reg_name, field_name, post_fix)\ argument
109 #define SF_DDC(reg_name, field_name, post_fix)\ argument
165 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_factory_dcn21.c | 57 #define REG(reg_name)\ argument
60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 #define REGI(reg_name, block, id)\ argument
67 #define SF(reg_name, field_name, post_fix)\ argument
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
139 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_factory_dcn20.c | 59 #define REG(reg_name)\ argument
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
65 #define REGI(reg_name, block, id)\ argument
69 #define SF(reg_name, field_name, post_fix)\ argument
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
158 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/ |
| H A D | hw_factory_dcn401.c | 39 #define REG(reg_name)\ argument
42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
45 #define REGI(reg_name, block, id)\ argument
49 #define SF(reg_name, field_name, post_fix)\ argument
81 #define SF_DDC(reg_name, field_name, post_fix)\ argument
161 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
| H A D | hw_factory_dcn315.c | 63 #define REG(reg_name)\ argument
66 #define SF_HPD(reg_name, field_name, post_fix)\ argument
69 #define REGI(reg_name, block, id)\ argument
73 #define SF(reg_name, field_name, post_fix)\ argument
105 #define SF_DDC(reg_name, field_name, post_fix)\ argument
157 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_factory_dce120.c | 46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
60 #define REG(reg_name)\ argument
63 #define REGI(reg_name, block, id)\ argument
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/ |
| H A D | dcn60_resource.c | 110 #define SR(reg_name)\ argument
113 #define SR_ARR(reg_name, id)\ argument
116 #define SR_ARR_INIT(reg_name, id, value)\ argument
119 #define SRI(reg_name, block, id)\ argument
123 #define SRI_ARR(reg_name, block, id)\ argument
127 #define SRI_ARR_DDC(reg_name, block, id)\ argument
134 #define SRI_ARR_US(reg_name, block, id)\ argument
137 #define SR_ARR_I2C(reg_name, id) \ argument
140 #define SRI_ARR_I2C(reg_name, block, id)\ argument
144 #define SRI_ARR_DME(reg_name, block, id, offset)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_factory_dcn10.c | 47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
57 #define REG(reg_name)\ argument
60 #define REGI(reg_name, block, id)\ argument
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 121 #define SR(reg_name)\ argument
124 #define SR_ARR(reg_name, id)\ argument
127 #define SR_ARR_INIT(reg_name, id, value)\ argument
130 #define SRI(reg_name, block, id)\ argument
134 #define SRI_ARR(reg_name, block, id)\ argument
138 #define SR_ARR_I2C(reg_name, id) \ argument
141 #define SRI_ARR_I2C(reg_name, block, id)\ argument
145 #define SRI_ARR_DME(reg_name, block, id, offset)\ argument
149 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
153 #define SRI2(reg_name, block, id)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 103 #define SR(reg_name)\ argument
106 #define SR_ARR(reg_name, id)\ argument
109 #define SR_ARR_INIT(reg_name, id, value)\ argument
112 #define SRI(reg_name, block, id)\ argument
116 #define SRI_ARR(reg_name, block, id)\ argument
123 #define SRI_ARR_US(reg_name, block, id)\ argument
126 #define SR_ARR_I2C(reg_name, id) \ argument
129 #define SRI_ARR_I2C(reg_name, block, id)\ argument
133 #define SRI_ARR_DME(reg_name, block, id, offset)\ argument
137 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/ |
| H A D | dcn42_resource.c | 117 #define SR(reg_name) \ argument
120 #define SR_ARR(reg_name, id) \ argument
123 #define SR_ARR_INIT(reg_name, id, value) \ argument
126 #define SRI(reg_name, block, id) \ argument
130 #define SRI_ARR(reg_name, block, id) \ argument
137 #define SRI_ARR_US(reg_name, block, id) \ argument
140 #define SR_ARR_I2C(reg_name, id) \ argument
143 #define SRI_ARR_I2C(reg_name, block, id) \ argument
147 #define SRI_ARR_DME(reg_name, block, id, offset) \ argument
151 #define SRI_ARR_ALPHABET(reg_name, block, index, id) \ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
| H A D | hw_factory_dce110.c | 42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
45 #define REG(reg_name)\ argument
48 #define REGI(reg_name, block, id)\ argument
79 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/ |
| H A D | dcn42b_resource.c | 182 #define SR(reg_name) \ argument
185 #define SR_ARR(reg_name, id) \ argument
188 #define SR_ARR_INIT(reg_name, id, value) \ argument
191 #define SRI(reg_name, block, id) \ argument
195 #define SRI_ARR(reg_name, block, id) \ argument
202 #define SRI_ARR_US(reg_name, block, id) \ argument
205 #define SR_ARR_I2C(reg_name, id) \ argument
208 #define SRI_ARR_I2C(reg_name, block, id) \ argument
212 #define SRI_ARR_ALPHABET(reg_name, block, index, id) \ argument
216 #define SRI2(reg_name, block, id) \ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 120 #define SR(reg_name)\ argument
124 #define SR_ARR(reg_name, id) \ argument
127 #define SR_ARR_INIT(reg_name, id, value) \ argument
130 #define SRI(reg_name, block, id)\ argument
134 #define SRI_ARR(reg_name, block, id)\ argument
138 #define SR_ARR_I2C(reg_name, id) \ argument
141 #define SRI_ARR_I2C(reg_name, block, id)\ argument
145 #define SRI_ARR_DME(reg_name, block, id, offset)\ argument
149 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
153 #define SRI2(reg_name, block, id)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 135 #define SR(reg_name)\ argument
139 #define SR_ARR(reg_name, id) \ argument
142 #define SR_ARR_INIT(reg_name, id, value) \ argument
145 #define SRI(reg_name, block, id)\ argument
149 #define SRI_ARR(reg_name, block, id)\ argument
153 #define SR_ARR_I2C(reg_name, id) \ argument
156 #define SRI_ARR_I2C(reg_name, block, id)\ argument
160 #define SRI_ARR_DME(reg_name, block, id, offset)\ argument
164 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
168 #define SRI2(reg_name, block, id)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 115 #define SR(reg_name)\ argument
119 #define SR_ARR(reg_name, id) \ argument
122 #define SR_ARR_INIT(reg_name, id, value) \ argument
125 #define SRI(reg_name, block, id)\ argument
129 #define SRI_ARR(reg_name, block, id)\ argument
133 #define SR_ARR_I2C(reg_name, id) \ argument
136 #define SRI_ARR_I2C(reg_name, block, id)\ argument
140 #define SRI_ARR_DME(reg_name, block, id, offset)\ argument
144 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
148 #define SRI2(reg_name, block, id)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 126 #define SR(reg_name)\ argument
129 #define SR_ARR(reg_name, id) \ argument
132 #define SR_ARR_INIT(reg_name, id, value) \ argument
135 #define SRI(reg_name, block, id)\ argument
139 #define SRI_ARR(reg_name, block, id)\ argument
143 #define SR_ARR_I2C(reg_name, id) \ argument
146 #define SRI_ARR_I2C(reg_name, block, id)\ argument
150 #define SRI_ARR_DME(reg_name, block, id, offset)\ argument
154 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ argument
158 #define SRI2(reg_name, block, id)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 172 #define NBIO_SR(reg_name)\ argument
181 #define SR(reg_name)\ argument
184 #define SF(reg_name, field_name, post_fix)\ argument
187 #define SRI(reg_name, block, id)\ argument
190 #define SRI2(reg_name, block, id)\ argument
193 #define SRII(reg_name, block, id)\ argument
197 #define DCCG_SRII(reg_name, block, id)\ argument
201 #define VUPDATE_SRII(reg_name, block, id)\ argument
205 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
209 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 176 #define NBIO_SR(reg_name)\ argument
185 #define SR(reg_name)\ argument
188 #define SF(reg_name, field_name, post_fix)\ argument
191 #define SRI(reg_name, block, id)\ argument
194 #define SRI2(reg_name, block, id)\ argument
197 #define SRII(reg_name, block, id)\ argument
201 #define DCCG_SRII(reg_name, block, id)\ argument
205 #define VUPDATE_SRII(reg_name, block, id)\ argument
209 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
213 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_panel_cntl.h | 32 #define DCE_PANEL_CNTL_SR(reg_name, block)\ argument
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\ argument
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
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| /linux/drivers/media/i2c/ccs/ |
| H A D | ccs-reg-access.h | 33 #define ccs_read(sensor, reg_name, val) \ argument
36 #define ccs_write(sensor, reg_name, val) \ argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 149 #define SR(reg_name)\ argument
153 #define SRI(reg_name, block, id)\ argument
157 #define SRI2(reg_name, block, id)\ argument
161 #define SRIR(var_name, reg_name, block, id)\ argument
165 #define SRII(reg_name, block, id)\ argument
169 #define SRII_MPC_RMU(reg_name, block, id)\ argument
173 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
177 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
180 #define DCCG_SRII(reg_name, block, id)\ argument
184 #define VUPDATE_SRII(reg_name, block, id)\ argument
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 132 #define SR(reg_name)\ argument
136 #define SRI(reg_name, block, id)\ argument
140 #define SRI2(reg_name, block, id)\ argument
144 #define SRIR(var_name, reg_name, block, id)\ argument
148 #define SRII(reg_name, block, id)\ argument
152 #define SRII_MPC_RMU(reg_name, block, id)\ argument
156 #define SRII_DWB(reg_name, temp_name, block, id)\ argument
160 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
163 #define DCCG_SRII(reg_name, block, id)\ argument
167 #define VUPDATE_SRII(reg_name, block, id)\ argument
[all …]
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