1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 #include <linux/fs.h> 10 #include <linux/hex.h> 11 #include <linux/uaccess.h> 12 #include <linux/string.h> 13 #include <linux/pci.h> 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/mutex.h> 17 #include <linux/if_ether.h> 18 #include <linux/ctype.h> 19 #include <linux/dmi.h> 20 #include <linux/of.h> 21 22 #define PHUB_STATUS 0x00 /* Status Register offset */ 23 #define PHUB_CONTROL 0x04 /* Control Register offset */ 24 #define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */ 25 #define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */ 26 #define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */ 27 #define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address 28 offset */ 29 #define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address 30 offset */ 31 #define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset 32 (Intel EG20T PCH)*/ 33 #define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address 34 offset(LAPIS Semicon ML7213) 35 */ 36 #define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address 37 offset(LAPIS Semicon ML7223) 38 */ 39 40 /* MAX number of INT_REDUCE_CONTROL registers */ 41 #define MAX_NUM_INT_REDUCE_CONTROL_REG 128 42 #define PCI_DEVICE_ID_PCH1_PHUB 0x8801 43 #define PCH_MINOR_NOS 1 44 #define CLKCFG_CAN_50MHZ 0x12000000 45 #define CLKCFG_CANCLK_MASK 0xFF000000 46 #define CLKCFG_UART_MASK 0xFFFFFF 47 48 /* CM-iTC */ 49 #define CLKCFG_UART_48MHZ (1 << 16) 50 #define CLKCFG_UART_25MHZ (2 << 16) 51 #define CLKCFG_BAUDDIV (2 << 20) 52 #define CLKCFG_PLL2VCO (8 << 9) 53 #define CLKCFG_UARTCLKSEL (1 << 18) 54 55 /* Macros for ML7213 */ 56 #define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A 57 58 /* Macros for ML7223 */ 59 #define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */ 60 #define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */ 61 62 /* Macros for ML7831 */ 63 #define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801 64 65 /* SROM ACCESS Macro */ 66 #define PCH_WORD_ADDR_MASK (~((1 << 2) - 1)) 67 68 /* Registers address offset */ 69 #define PCH_PHUB_ID_REG 0x0000 70 #define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004 71 #define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008 72 #define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C 73 #define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010 74 #define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014 75 #define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018 76 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020 77 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024 78 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028 79 #define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C 80 #define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040 81 #define CLKCFG_REG_OFFSET 0x500 82 #define FUNCSEL_REG_OFFSET 0x508 83 84 #define PCH_PHUB_OROM_SIZE 15360 85 86 /** 87 * struct pch_phub_reg - PHUB register structure 88 * @phub_id_reg: PHUB_ID register val 89 * @q_pri_val_reg: QUEUE_PRI_VAL register val 90 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val 91 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val 92 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val 93 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val 94 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val 95 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val 96 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val 97 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val 98 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val 99 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val 100 * @clkcfg_reg: CLK CFG register val 101 * @funcsel_reg: Function select register value 102 * @pch_phub_base_address: Register base address 103 * @pch_phub_extrom_base_address: external rom base address 104 * @pch_mac_start_address: MAC address area start address 105 * @pch_opt_rom_start_address: Option ROM start address 106 * @ioh_type: Save IOH type 107 * @pdev: pointer to pci device struct 108 */ 109 struct pch_phub_reg { 110 u32 phub_id_reg; 111 u32 q_pri_val_reg; 112 u32 rc_q_maxsize_reg; 113 u32 bri_q_maxsize_reg; 114 u32 comp_resp_timeout_reg; 115 u32 bus_slave_control_reg; 116 u32 deadlock_avoid_type_reg; 117 u32 intpin_reg_wpermit_reg0; 118 u32 intpin_reg_wpermit_reg1; 119 u32 intpin_reg_wpermit_reg2; 120 u32 intpin_reg_wpermit_reg3; 121 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG]; 122 u32 clkcfg_reg; 123 u32 funcsel_reg; 124 void __iomem *pch_phub_base_address; 125 void __iomem *pch_phub_extrom_base_address; 126 u32 pch_mac_start_address; 127 u32 pch_opt_rom_start_address; 128 int ioh_type; 129 struct pci_dev *pdev; 130 }; 131 132 /* SROM SPEC for MAC address assignment offset */ 133 static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa}; 134 135 static DEFINE_MUTEX(pch_phub_mutex); 136 137 /** 138 * pch_phub_read_modify_write_reg() - Reading modifying and writing register 139 * @chip: Pointer to the PHUB register structure 140 * @reg_addr_offset: Register offset address value. 141 * @data: Writing value. 142 * @mask: Mask value. 143 */ 144 static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip, 145 unsigned int reg_addr_offset, 146 unsigned int data, unsigned int mask) 147 { 148 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; 149 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); 150 } 151 152 /** 153 * pch_phub_read_serial_rom() - Reading Serial ROM 154 * @chip: Pointer to the PHUB register structure 155 * @offset_address: Serial ROM offset address to read. 156 * @data: Read buffer for specified Serial ROM value. 157 */ 158 static void pch_phub_read_serial_rom(struct pch_phub_reg *chip, 159 unsigned int offset_address, u8 *data) 160 { 161 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 162 offset_address; 163 164 *data = ioread8(mem_addr); 165 } 166 167 /** 168 * pch_phub_write_serial_rom() - Writing Serial ROM 169 * @chip: Pointer to the PHUB register structure 170 * @offset_address: Serial ROM offset address. 171 * @data: Serial ROM value to write. 172 */ 173 static int pch_phub_write_serial_rom(struct pch_phub_reg *chip, 174 unsigned int offset_address, u8 data) 175 { 176 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 177 (offset_address & PCH_WORD_ADDR_MASK); 178 int i; 179 unsigned int word_data; 180 unsigned int pos; 181 unsigned int mask; 182 pos = (offset_address % 4) * 8; 183 mask = ~(0xFF << pos); 184 185 iowrite32(PCH_PHUB_ROM_WRITE_ENABLE, 186 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 187 188 word_data = ioread32(mem_addr); 189 iowrite32((word_data & mask) | (u32)data << pos, mem_addr); 190 191 i = 0; 192 while (ioread8(chip->pch_phub_extrom_base_address + 193 PHUB_STATUS) != 0x00) { 194 msleep(1); 195 if (i == PHUB_TIMEOUT) 196 return -ETIMEDOUT; 197 i++; 198 } 199 200 iowrite32(PCH_PHUB_ROM_WRITE_DISABLE, 201 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 202 203 return 0; 204 } 205 206 /** 207 * pch_phub_read_serial_rom_val() - Read Serial ROM value 208 * @chip: Pointer to the PHUB register structure 209 * @offset_address: Serial ROM address offset value. 210 * @data: Serial ROM value to read. 211 */ 212 static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip, 213 unsigned int offset_address, u8 *data) 214 { 215 unsigned int mem_addr; 216 217 mem_addr = chip->pch_mac_start_address + 218 pch_phub_mac_offset[offset_address]; 219 220 pch_phub_read_serial_rom(chip, mem_addr, data); 221 } 222 223 /** 224 * pch_phub_write_serial_rom_val() - writing Serial ROM value 225 * @chip: Pointer to the PHUB register structure 226 * @offset_address: Serial ROM address offset value. 227 * @data: Serial ROM value. 228 */ 229 static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip, 230 unsigned int offset_address, u8 data) 231 { 232 int retval; 233 unsigned int mem_addr; 234 235 mem_addr = chip->pch_mac_start_address + 236 pch_phub_mac_offset[offset_address]; 237 238 retval = pch_phub_write_serial_rom(chip, mem_addr, data); 239 240 return retval; 241 } 242 243 /* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration 244 * for Gigabit Ethernet MAC address 245 */ 246 static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip) 247 { 248 int retval; 249 250 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc); 251 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10); 252 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01); 253 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02); 254 255 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00); 256 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00); 257 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00); 258 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80); 259 260 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc); 261 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10); 262 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01); 263 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18); 264 265 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc); 266 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10); 267 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01); 268 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19); 269 270 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc); 271 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10); 272 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01); 273 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a); 274 275 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01); 276 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00); 277 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00); 278 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00); 279 280 return retval; 281 } 282 283 /* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration 284 * for Gigabit Ethernet MAC address 285 */ 286 static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip) 287 { 288 int retval; 289 u32 offset_addr; 290 291 offset_addr = 0x200; 292 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc); 293 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00); 294 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40); 295 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02); 296 297 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00); 298 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00); 299 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00); 300 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80); 301 302 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc); 303 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00); 304 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40); 305 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18); 306 307 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc); 308 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00); 309 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40); 310 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19); 311 312 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc); 313 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00); 314 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40); 315 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a); 316 317 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01); 318 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00); 319 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00); 320 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00); 321 322 return retval; 323 } 324 325 /** 326 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address 327 * @chip: Pointer to the PHUB register structure 328 * @data: Buffer of the Gigabit Ethernet MAC address value. 329 */ 330 static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 331 { 332 int i; 333 for (i = 0; i < ETH_ALEN; i++) 334 pch_phub_read_serial_rom_val(chip, i, &data[i]); 335 } 336 337 /** 338 * pch_phub_write_gbe_mac_addr() - Write MAC address 339 * @chip: Pointer to the PHUB register structure 340 * @data: Gigabit Ethernet MAC address value. 341 */ 342 static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 343 { 344 int retval; 345 int i; 346 347 if ((chip->ioh_type == 1) || (chip->ioh_type == 5)) /* EG20T or ML7831*/ 348 retval = pch_phub_gbe_serial_rom_conf(chip); 349 else /* ML7223 */ 350 retval = pch_phub_gbe_serial_rom_conf_mp(chip); 351 if (retval) 352 return retval; 353 354 for (i = 0; i < ETH_ALEN; i++) { 355 retval = pch_phub_write_serial_rom_val(chip, i, data[i]); 356 if (retval) 357 return retval; 358 } 359 360 return retval; 361 } 362 363 static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj, 364 const struct bin_attribute *attr, char *buf, 365 loff_t off, size_t count) 366 { 367 unsigned int rom_signature; 368 unsigned char rom_length; 369 unsigned int tmp; 370 unsigned int addr_offset; 371 unsigned int orom_size; 372 int ret; 373 int err; 374 ssize_t rom_size; 375 376 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj)); 377 378 ret = mutex_lock_interruptible(&pch_phub_mutex); 379 if (ret) { 380 err = -ERESTARTSYS; 381 goto return_err_nomutex; 382 } 383 384 /* Get Rom signature */ 385 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 386 if (!chip->pch_phub_extrom_base_address) { 387 err = -ENODATA; 388 goto exrom_map_err; 389 } 390 391 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address, 392 (unsigned char *)&rom_signature); 393 rom_signature &= 0xff; 394 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1, 395 (unsigned char *)&tmp); 396 rom_signature |= (tmp & 0xff) << 8; 397 if (rom_signature == 0xAA55) { 398 pch_phub_read_serial_rom(chip, 399 chip->pch_opt_rom_start_address + 2, 400 &rom_length); 401 orom_size = rom_length * 512; 402 if (orom_size < off) { 403 addr_offset = 0; 404 goto return_ok; 405 } 406 if (orom_size < count) { 407 addr_offset = 0; 408 goto return_ok; 409 } 410 411 for (addr_offset = 0; addr_offset < count; addr_offset++) { 412 pch_phub_read_serial_rom(chip, 413 chip->pch_opt_rom_start_address + addr_offset + off, 414 &buf[addr_offset]); 415 } 416 } else { 417 err = -ENODATA; 418 goto return_err; 419 } 420 return_ok: 421 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 422 mutex_unlock(&pch_phub_mutex); 423 return addr_offset; 424 425 return_err: 426 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 427 exrom_map_err: 428 mutex_unlock(&pch_phub_mutex); 429 return_err_nomutex: 430 return err; 431 } 432 433 static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj, 434 const struct bin_attribute *attr, 435 char *buf, loff_t off, size_t count) 436 { 437 int err; 438 unsigned int addr_offset; 439 int ret; 440 ssize_t rom_size; 441 struct pch_phub_reg *chip = dev_get_drvdata(kobj_to_dev(kobj)); 442 443 ret = mutex_lock_interruptible(&pch_phub_mutex); 444 if (ret) 445 return -ERESTARTSYS; 446 447 if (off > PCH_PHUB_OROM_SIZE) { 448 addr_offset = 0; 449 goto return_ok; 450 } 451 if (count > PCH_PHUB_OROM_SIZE) { 452 addr_offset = 0; 453 goto return_ok; 454 } 455 456 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 457 if (!chip->pch_phub_extrom_base_address) { 458 err = -ENOMEM; 459 goto exrom_map_err; 460 } 461 462 for (addr_offset = 0; addr_offset < count; addr_offset++) { 463 if (PCH_PHUB_OROM_SIZE < off + addr_offset) 464 goto return_ok; 465 466 ret = pch_phub_write_serial_rom(chip, 467 chip->pch_opt_rom_start_address + addr_offset + off, 468 buf[addr_offset]); 469 if (ret) { 470 err = ret; 471 goto return_err; 472 } 473 } 474 475 return_ok: 476 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 477 mutex_unlock(&pch_phub_mutex); 478 return addr_offset; 479 480 return_err: 481 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 482 483 exrom_map_err: 484 mutex_unlock(&pch_phub_mutex); 485 return err; 486 } 487 488 static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr, 489 char *buf) 490 { 491 u8 mac[8]; 492 struct pch_phub_reg *chip = dev_get_drvdata(dev); 493 ssize_t rom_size; 494 495 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 496 if (!chip->pch_phub_extrom_base_address) 497 return -ENOMEM; 498 499 pch_phub_read_gbe_mac_addr(chip, mac); 500 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 501 502 return sprintf(buf, "%pM\n", mac); 503 } 504 505 static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr, 506 const char *buf, size_t count) 507 { 508 u8 mac[ETH_ALEN]; 509 ssize_t rom_size; 510 struct pch_phub_reg *chip = dev_get_drvdata(dev); 511 int ret; 512 513 if (!mac_pton(buf, mac)) 514 return -EINVAL; 515 516 chip->pch_phub_extrom_base_address = pci_map_rom(chip->pdev, &rom_size); 517 if (!chip->pch_phub_extrom_base_address) 518 return -ENOMEM; 519 520 ret = pch_phub_write_gbe_mac_addr(chip, mac); 521 pci_unmap_rom(chip->pdev, chip->pch_phub_extrom_base_address); 522 if (ret) 523 return ret; 524 525 return count; 526 } 527 528 static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac); 529 530 static const struct bin_attribute pch_bin_attr = { 531 .attr = { 532 .name = "pch_firmware", 533 .mode = S_IRUGO | S_IWUSR, 534 }, 535 .size = PCH_PHUB_OROM_SIZE + 1, 536 .read = pch_phub_bin_read, 537 .write = pch_phub_bin_write, 538 }; 539 540 enum { 541 PCH_EG20T, 542 PCH_ML7213, 543 PCH_ML7223M, 544 PCH_ML7223N, 545 PCH_ML7831, 546 }; 547 548 static int pch_phub_probe(struct pci_dev *pdev, 549 const struct pci_device_id *id) 550 { 551 int ret; 552 struct pch_phub_reg *chip; 553 554 chip = kzalloc_obj(struct pch_phub_reg); 555 if (chip == NULL) 556 return -ENOMEM; 557 558 ret = pci_enable_device(pdev); 559 if (ret) { 560 dev_err(&pdev->dev, 561 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret); 562 goto err_pci_enable_dev; 563 } 564 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__, 565 ret); 566 567 ret = pci_request_regions(pdev, KBUILD_MODNAME); 568 if (ret) { 569 dev_err(&pdev->dev, 570 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret); 571 goto err_req_regions; 572 } 573 dev_dbg(&pdev->dev, "%s : " 574 "pci_request_regions returns %d\n", __func__, ret); 575 576 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0); 577 578 579 if (chip->pch_phub_base_address == NULL) { 580 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); 581 ret = -ENOMEM; 582 goto err_pci_iomap; 583 } 584 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value " 585 "in pch_phub_base_address variable is %p\n", __func__, 586 chip->pch_phub_base_address); 587 588 chip->pdev = pdev; /* Save pci device struct */ 589 590 if (id->driver_data == PCH_EG20T) { /* EG20T PCH */ 591 const char *board_name; 592 unsigned int prefetch = 0x000affaa; 593 594 if (pdev->dev.of_node) 595 of_property_read_u32(pdev->dev.of_node, 596 "intel,eg20t-prefetch", 597 &prefetch); 598 599 ret = sysfs_create_file(&pdev->dev.kobj, 600 &dev_attr_pch_mac.attr); 601 if (ret) 602 goto err_sysfs_create; 603 604 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 605 if (ret) 606 goto exit_bin_attr; 607 608 pch_phub_read_modify_write_reg(chip, 609 (unsigned int)CLKCFG_REG_OFFSET, 610 CLKCFG_CAN_50MHZ, 611 CLKCFG_CANCLK_MASK); 612 613 /* quirk for CM-iTC board */ 614 board_name = dmi_get_system_info(DMI_BOARD_NAME); 615 if (board_name && strstr(board_name, "CM-iTC")) 616 pch_phub_read_modify_write_reg(chip, 617 (unsigned int)CLKCFG_REG_OFFSET, 618 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV | 619 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL, 620 CLKCFG_UART_MASK); 621 622 /* set the prefech value */ 623 iowrite32(prefetch, chip->pch_phub_base_address + 0x14); 624 /* set the interrupt delay value */ 625 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 626 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 627 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 628 629 /* quirk for MIPS Boston platform */ 630 if (pdev->dev.of_node) { 631 if (of_machine_is_compatible("img,boston")) { 632 pch_phub_read_modify_write_reg(chip, 633 (unsigned int)CLKCFG_REG_OFFSET, 634 CLKCFG_UART_25MHZ, 635 CLKCFG_UART_MASK); 636 } 637 } 638 } else if (id->driver_data == PCH_ML7213) { /* ML7213 IOH */ 639 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 640 if (ret) 641 goto err_sysfs_create; 642 /* set the prefech value 643 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a 644 * Device4(SDIO #0,1,2):f 645 * Device6(SATA 2):f 646 * Device8(USB OHCI #0/ USB EHCI #0):a 647 */ 648 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14); 649 chip->pch_opt_rom_start_address =\ 650 PCH_PHUB_ROM_START_ADDR_ML7213; 651 } else if (id->driver_data == PCH_ML7223M) { /* ML7223 IOH Bus-m*/ 652 /* set the prefech value 653 * Device8(GbE) 654 */ 655 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14); 656 /* set the interrupt delay value */ 657 iowrite32(0x25, chip->pch_phub_base_address + 0x140); 658 chip->pch_opt_rom_start_address =\ 659 PCH_PHUB_ROM_START_ADDR_ML7223; 660 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 661 } else if (id->driver_data == PCH_ML7223N) { /* ML7223 IOH Bus-n*/ 662 ret = sysfs_create_file(&pdev->dev.kobj, 663 &dev_attr_pch_mac.attr); 664 if (ret) 665 goto err_sysfs_create; 666 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 667 if (ret) 668 goto exit_bin_attr; 669 /* set the prefech value 670 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a 671 * Device4(SDIO #0,1):f 672 * Device6(SATA 2):f 673 */ 674 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14); 675 chip->pch_opt_rom_start_address =\ 676 PCH_PHUB_ROM_START_ADDR_ML7223; 677 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 678 } else if (id->driver_data == PCH_ML7831) { /* ML7831 */ 679 ret = sysfs_create_file(&pdev->dev.kobj, 680 &dev_attr_pch_mac.attr); 681 if (ret) 682 goto err_sysfs_create; 683 684 ret = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 685 if (ret) 686 goto exit_bin_attr; 687 688 /* set the prefech value */ 689 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 690 /* set the interrupt delay value */ 691 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 692 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 693 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 694 } 695 696 chip->ioh_type = id->driver_data; 697 pci_set_drvdata(pdev, chip); 698 699 return 0; 700 exit_bin_attr: 701 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 702 703 err_sysfs_create: 704 pci_iounmap(pdev, chip->pch_phub_base_address); 705 err_pci_iomap: 706 pci_release_regions(pdev); 707 err_req_regions: 708 pci_disable_device(pdev); 709 err_pci_enable_dev: 710 kfree(chip); 711 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret); 712 return ret; 713 } 714 715 static void pch_phub_remove(struct pci_dev *pdev) 716 { 717 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 718 719 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 720 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr); 721 pci_iounmap(pdev, chip->pch_phub_base_address); 722 pci_release_regions(pdev); 723 pci_disable_device(pdev); 724 kfree(chip); 725 } 726 727 static int __maybe_unused pch_phub_suspend(struct device *dev_d) 728 { 729 device_wakeup_disable(dev_d); 730 731 return 0; 732 } 733 734 static int __maybe_unused pch_phub_resume(struct device *dev_d) 735 { 736 device_wakeup_disable(dev_d); 737 738 return 0; 739 } 740 741 static const struct pci_device_id pch_phub_pcidev_id[] = { 742 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), .driver_data = PCH_EG20T }, 743 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), .driver_data = PCH_ML7213 }, 744 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), .driver_data = PCH_ML7223M }, 745 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), .driver_data = PCH_ML7223N }, 746 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), .driver_data = PCH_ML7831 }, 747 { } 748 }; 749 MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id); 750 751 static SIMPLE_DEV_PM_OPS(pch_phub_pm_ops, pch_phub_suspend, pch_phub_resume); 752 753 static struct pci_driver pch_phub_driver = { 754 .name = "pch_phub", 755 .id_table = pch_phub_pcidev_id, 756 .probe = pch_phub_probe, 757 .remove = pch_phub_remove, 758 .driver.pm = &pch_phub_pm_ops, 759 }; 760 761 module_pci_driver(pch_phub_driver); 762 763 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB"); 764 MODULE_LICENSE("GPL"); 765