xref: /linux/drivers/gpu/drm/amd/include/asic_reg/umc/umc_12_0_0_offset.h (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 /*
2  * Copyright (C) 2023  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _umc_12_0_0_OFFSET_HEADER
22 #define _umc_12_0_0_OFFSET_HEADER
23 
24 #define regUMCCH0_OdEccCntSel                                                   0x032c
25 #define regUMCCH0_OdEccCntSel_BASE_IDX                                          0
26 #define regUMCCH0_OdEccErrCnt                                                   0x032d
27 #define regUMCCH0_OdEccErrCnt_BASE_IDX                                          0
28 #define regMCA_UMC_UMC0_MCUMC_STATUST0                                          0x03c2
29 #define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX                                 0
30 #define regMCA_UMC_UMC0_MCUMC_ADDRT0                                            0x03c4
31 #define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX                                   0
32 
33 #endif
34