1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017 exceet electronics GmbH 4 * 5 * Authors: 6 * Frieder Schrempf <frieder.schrempf@exceet.de> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #include <linux/device.h> 11 #include <linux/kernel.h> 12 #include <linux/mtd/spinand.h> 13 #include <linux/units.h> 14 #include <linux/delay.h> 15 16 #define SPINAND_MFR_WINBOND 0xEF 17 18 #define WINBOND_CFG_HFREQ BIT(0) 19 #define WINBOND_CFG_BUF_READ BIT(3) 20 21 #define W25N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4) 22 #define W25W35NXXJW_STATUS_ECC_MULT_UNCOR (3 << 4) 23 24 #define W25N0XJW_SR4 0xD0 25 #define W25N0XJW_SR4_HS BIT(2) 26 27 #define W35N01JW_VCR_IO_MODE_REG 0x00 28 #define W35N01JW_VCR_IO_MODE_SINGLE_SDR 0xFF 29 #define W35N01JW_VCR_IO_MODE_OCTAL_SDR 0xDF 30 #define W35N01JW_VCR_IO_MODE_OCTAL_DDR_DS 0xE7 31 #define W35N01JW_VCR_IO_MODE_OCTAL_DDR 0xC7 32 #define W35N01JW_VCR_DUMMY_CLOCK_REG 0x01 33 34 /* 35 * Winbond chips ignore the address bytes during continuous reads, and 36 * because the dummy cycles are enough they indicate dropping the 37 * address cycles from the continuous read from cache variants. This is 38 * very poorly supported by SPI controller drivers which are "wired" to 39 * always at least provide the column. Keep using address cycles, but 40 * reduce the number of dummy cycles accordingly. 41 */ 42 #define WINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(ndummy, buf, len, freq) \ 43 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \ 44 SPI_MEM_OP_ADDR(1, 0, 1), \ 45 SPI_MEM_OP_DUMMY(ndummy - 1, 1), \ 46 SPI_MEM_OP_DATA_IN(len, buf, 1), \ 47 SPI_MEM_OP_MAX_FREQ(freq)) 48 49 #define WINBOND_CONT_READ_FROM_CACHE_1S_1D_1D_OP(ndummy, buf, len, freq) \ 50 SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \ 51 SPI_MEM_DTR_OP_ADDR(2, 0, 1), \ 52 SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \ 53 SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \ 54 SPI_MEM_OP_MAX_FREQ(freq)) 55 56 #define WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(ndummy, buf, len, freq) \ 57 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \ 58 SPI_MEM_OP_ADDR(1, 0, 1), \ 59 SPI_MEM_OP_DUMMY(ndummy - 1, 1), \ 60 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 61 SPI_MEM_OP_MAX_FREQ(freq)) 62 63 #define WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(ndummy, buf, len, freq) \ 64 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \ 65 SPI_MEM_OP_ADDR(1, 0, 2), \ 66 SPI_MEM_OP_DUMMY(ndummy - 1, 2), \ 67 SPI_MEM_OP_DATA_IN(len, buf, 2), \ 68 SPI_MEM_OP_MAX_FREQ(freq)) 69 70 #define WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(ndummy, buf, len, freq) \ 71 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \ 72 SPI_MEM_DTR_OP_ADDR(1, 0, 2), \ 73 SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 2), \ 74 SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \ 75 SPI_MEM_OP_MAX_FREQ(freq)) 76 77 #define WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(ndummy, buf, len, freq) \ 78 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \ 79 SPI_MEM_OP_ADDR(1, 0, 1), \ 80 SPI_MEM_OP_DUMMY(ndummy - 1, 1), \ 81 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 82 SPI_MEM_OP_MAX_FREQ(freq)) 83 84 #define WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(ndummy, buf, len, freq) \ 85 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \ 86 SPI_MEM_DTR_OP_ADDR(1, 0, 1), \ 87 SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 1), \ 88 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ 89 SPI_MEM_OP_MAX_FREQ(freq)) 90 91 #define WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(ndummy, buf, len, freq) \ 92 SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \ 93 SPI_MEM_OP_ADDR(1, 0, 4), \ 94 SPI_MEM_OP_DUMMY(ndummy - 1, 4), \ 95 SPI_MEM_OP_DATA_IN(len, buf, 4), \ 96 SPI_MEM_OP_MAX_FREQ(freq)) 97 98 #define WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(ndummy, buf, len, freq) \ 99 SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \ 100 SPI_MEM_DTR_OP_ADDR(1, 0, 4), \ 101 SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 4), \ 102 SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \ 103 SPI_MEM_OP_MAX_FREQ(freq)) 104 105 #define WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(ndummy, buf, len, freq) \ 106 SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \ 107 SPI_MEM_OP_ADDR(1, 0, 1), \ 108 SPI_MEM_OP_DUMMY(ndummy - 1, 1), \ 109 SPI_MEM_OP_DATA_IN(len, buf, 8), \ 110 SPI_MEM_OP_MAX_FREQ(freq)) 111 112 #define WINBOND_CONT_READ_FROM_CACHE_1S_1D_8D_OP(ndummy, buf, len, freq) \ 113 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \ 114 SPI_MEM_DTR_OP_ADDR(1, 0, 1), \ 115 SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 1), \ 116 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \ 117 SPI_MEM_OP_MAX_FREQ(freq)) 118 119 #define WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(ndummy, buf, len, freq) \ 120 SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \ 121 SPI_MEM_OP_ADDR(1, 0, 8), \ 122 SPI_MEM_OP_DUMMY(ndummy - 1, 8), \ 123 SPI_MEM_OP_DATA_IN(len, buf, 8), \ 124 SPI_MEM_OP_MAX_FREQ(freq)) 125 126 #define WINBOND_CONT_READ_FROM_CACHE_8D_8D_8D_OP(ndummy, buf, len, freq) \ 127 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9d, 8), \ 128 SPI_MEM_DTR_OP_ADDR(2, 0, 8), \ 129 SPI_MEM_DTR_OP_DUMMY(ndummy - 2, 8), \ 130 SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \ 131 SPI_MEM_OP_MAX_FREQ(freq)) 132 133 /* 134 * "X2" in the core is equivalent to "dual output" in the datasheets, 135 * "X4" in the core is equivalent to "quad output" in the datasheets. 136 * Quad and octal capable chips feature an absolute maximum frequency of 166MHz. 137 */ 138 139 static SPINAND_OP_VARIANTS(read_cache_octal_variants, 140 SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(0, 24, NULL, 0, 120 * HZ_PER_MHZ), 141 SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(0, 16, NULL, 0, 86 * HZ_PER_MHZ), 142 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(0, 3, NULL, 0, 120 * HZ_PER_MHZ), 143 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(0, 2, NULL, 0, 105 * HZ_PER_MHZ), 144 SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 20, NULL, 0, 0), 145 SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 16, NULL, 0, 162 * HZ_PER_MHZ), 146 SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 12, NULL, 0, 124 * HZ_PER_MHZ), 147 SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 8, NULL, 0, 86 * HZ_PER_MHZ), 148 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(0, 2, NULL, 0, 0), 149 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(0, 1, NULL, 0, 133 * HZ_PER_MHZ), 150 SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0), 151 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0)); 152 153 static SPINAND_OP_VARIANTS(cont_read_cache_octal_variants, 154 WINBOND_CONT_READ_FROM_CACHE_8D_8D_8D_OP(24, NULL, 0, 120 * HZ_PER_MHZ), 155 WINBOND_CONT_READ_FROM_CACHE_8D_8D_8D_OP(16, NULL, 0, 86 * HZ_PER_MHZ), 156 WINBOND_CONT_READ_FROM_CACHE_1S_1D_8D_OP(3, NULL, 0, 120 * HZ_PER_MHZ), 157 WINBOND_CONT_READ_FROM_CACHE_1S_1D_8D_OP(2, NULL, 0, 105 * HZ_PER_MHZ), 158 WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(20, NULL, 0, 0), 159 WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(16, NULL, 0, 162 * HZ_PER_MHZ), 160 WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(12, NULL, 0, 124 * HZ_PER_MHZ), 161 WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(8, NULL, 0, 86 * HZ_PER_MHZ), 162 WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(2, NULL, 0, 0), 163 WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(1, NULL, 0, 133 * HZ_PER_MHZ), 164 WINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(1, NULL, 0, 0)); 165 166 static SPINAND_OP_VARIANTS(write_cache_octal_variants, 167 SPINAND_PROG_LOAD_8D_8D_8D_OP(true, 0, NULL, 0), 168 SPINAND_PROG_LOAD_1S_8S_8S_OP(true, 0, NULL, 0), 169 SPINAND_PROG_LOAD_1S_1S_8S_OP(0, NULL, 0), 170 SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0)); 171 172 static SPINAND_OP_VARIANTS(update_cache_octal_variants, 173 SPINAND_PROG_LOAD_8D_8D_8D_OP(false, 0, NULL, 0), 174 SPINAND_PROG_LOAD_1S_8S_8S_OP(false, 0, NULL, 0), 175 SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); 176 177 static SPINAND_OP_VARIANTS(read_cache_dual_quad_dtr_variants, 178 SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(0, 8, NULL, 0, 80 * HZ_PER_MHZ), 179 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ), 180 SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 4, NULL, 0, 0), 181 SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0, 104 * HZ_PER_MHZ), 182 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0), 183 SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(0, 4, NULL, 0, 80 * HZ_PER_MHZ), 184 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ), 185 SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(0, 2, NULL, 0, 0), 186 SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(0, 1, NULL, 0, 104 * HZ_PER_MHZ), 187 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0, 0), 188 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ), 189 SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0), 190 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 54 * HZ_PER_MHZ)); 191 192 static SPINAND_OP_VARIANTS(cont_read_cache_dual_quad_dtr_variants, 193 WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(11, NULL, 0, 80 * HZ_PER_MHZ), 194 WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(5, NULL, 0, 80 * HZ_PER_MHZ), 195 WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(7, NULL, 0, 0), 196 WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(6, NULL, 0, 104 * HZ_PER_MHZ), 197 WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(4, NULL, 0, 0), 198 WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(6, NULL, 0, 80 * HZ_PER_MHZ), 199 /* The 1S_1D_2D variant would require 4.5 dummy bytes, this is not possible */ 200 WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(5, NULL, 0, 0), 201 WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(4, NULL, 0, 104 * HZ_PER_MHZ), 202 WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(4, NULL, 0, 0), 203 /* The 1S_1D_1D variant would require 4.5 dummy bytes, this is not possible */ 204 WINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(4, NULL, 0, 0)); 205 206 static SPINAND_OP_VARIANTS(read_cache_variants, 207 SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0, 0), 208 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0), 209 SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(0, 1, NULL, 0, 0), 210 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0, 0), 211 SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0), 212 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0)); 213 214 static SPINAND_OP_VARIANTS(write_cache_variants, 215 SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0), 216 SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0)); 217 218 static SPINAND_OP_VARIANTS(update_cache_variants, 219 SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0), 220 SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0)); 221 222 #define SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, buf) \ 223 SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), \ 224 SPI_MEM_OP_ADDR(3, reg, 1), \ 225 SPI_MEM_OP_NO_DUMMY, \ 226 SPI_MEM_OP_DATA_OUT(1, buf, 1)) 227 228 #define SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, buf) \ 229 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x81, 8), \ 230 SPI_MEM_DTR_OP_ADDR(4, reg << 8, 8), \ 231 SPI_MEM_OP_NO_DUMMY, \ 232 SPI_MEM_DTR_OP_DATA_OUT(2, buf, 8)) 233 234 static SPINAND_OP_VARIANTS(winbond_w35_ops, 235 SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(0, NULL), 236 SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(0, NULL)); 237 238 static struct spi_mem_op 239 spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, void *valptr) 240 { 241 return (spinand->bus_iface == SSDR) ? 242 (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr) : 243 (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, valptr); 244 } 245 246 #define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \ 247 SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), \ 248 SPI_MEM_OP_NO_ADDR, \ 249 SPI_MEM_OP_NO_DUMMY, \ 250 SPI_MEM_OP_DATA_OUT(1, buf, 1)) 251 252 static SPINAND_OP_VARIANTS(winbond_w25_ops, 253 SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(NULL)); 254 255 static struct spi_mem_op 256 spinand_fill_winbond_select_target_op(struct spinand_device *spinand, void *valptr) 257 { 258 WARN_ON_ONCE(spinand->bus_iface != SSDR); 259 260 return (struct spi_mem_op)SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(valptr); 261 } 262 263 static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, 264 struct mtd_oob_region *region) 265 { 266 if (section > 3) 267 return -ERANGE; 268 269 region->offset = (16 * section) + 8; 270 region->length = 8; 271 272 return 0; 273 } 274 275 static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section, 276 struct mtd_oob_region *region) 277 { 278 if (section > 3) 279 return -ERANGE; 280 281 region->offset = (16 * section) + 2; 282 region->length = 6; 283 284 return 0; 285 } 286 287 static const struct mtd_ooblayout_ops w25m02gv_ooblayout = { 288 .ecc = w25m02gv_ooblayout_ecc, 289 .free = w25m02gv_ooblayout_free, 290 }; 291 292 static int w25m02gv_select_target(struct spinand_device *spinand, 293 unsigned int target) 294 { 295 struct spi_mem_op op = SPINAND_OP(spinand, winbond_select_target, 296 spinand->scratchbuf); 297 298 *spinand->scratchbuf = target; 299 return spi_mem_exec_op(spinand->spimem, &op); 300 } 301 302 static int w25n01kv_ooblayout_ecc(struct mtd_info *mtd, int section, 303 struct mtd_oob_region *region) 304 { 305 if (section > 3) 306 return -ERANGE; 307 308 region->offset = 64 + (8 * section); 309 region->length = 7; 310 311 return 0; 312 } 313 314 static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section, 315 struct mtd_oob_region *region) 316 { 317 if (section > 3) 318 return -ERANGE; 319 320 region->offset = 64 + (16 * section); 321 region->length = 13; 322 323 return 0; 324 } 325 326 static int w25n02kv_ooblayout_free(struct mtd_info *mtd, int section, 327 struct mtd_oob_region *region) 328 { 329 if (section > 3) 330 return -ERANGE; 331 332 region->offset = (16 * section) + 2; 333 region->length = 14; 334 335 return 0; 336 } 337 338 static const struct mtd_ooblayout_ops w25n01kv_ooblayout = { 339 .ecc = w25n01kv_ooblayout_ecc, 340 .free = w25n02kv_ooblayout_free, 341 }; 342 343 static const struct mtd_ooblayout_ops w25n02kv_ooblayout = { 344 .ecc = w25n02kv_ooblayout_ecc, 345 .free = w25n02kv_ooblayout_free, 346 }; 347 348 static int w25n01jw_ooblayout_ecc(struct mtd_info *mtd, int section, 349 struct mtd_oob_region *region) 350 { 351 if (section > 3) 352 return -ERANGE; 353 354 region->offset = (16 * section) + 12; 355 region->length = 4; 356 357 return 0; 358 } 359 360 static int w25n01jw_ooblayout_free(struct mtd_info *mtd, int section, 361 struct mtd_oob_region *region) 362 { 363 if (section > 3) 364 return -ERANGE; 365 366 region->offset = (16 * section); 367 region->length = 12; 368 369 /* Extract BBM */ 370 if (!section) { 371 region->offset += 2; 372 region->length -= 2; 373 } 374 375 return 0; 376 } 377 378 static int w35n01jw_ooblayout_ecc(struct mtd_info *mtd, int section, 379 struct mtd_oob_region *region) 380 { 381 if (section > 7) 382 return -ERANGE; 383 384 region->offset = (16 * section) + 12; 385 region->length = 4; 386 387 return 0; 388 } 389 390 static int w35n01jw_ooblayout_free(struct mtd_info *mtd, int section, 391 struct mtd_oob_region *region) 392 { 393 if (section > 7) 394 return -ERANGE; 395 396 region->offset = 16 * section; 397 region->length = 12; 398 399 /* Extract BBM */ 400 if (!section) { 401 region->offset += 2; 402 region->length -= 2; 403 } 404 405 return 0; 406 } 407 408 static const struct mtd_ooblayout_ops w25n01jw_ooblayout = { 409 .ecc = w25n01jw_ooblayout_ecc, 410 .free = w25n01jw_ooblayout_free, 411 }; 412 413 static const struct mtd_ooblayout_ops w35n01jw_ooblayout = { 414 .ecc = w35n01jw_ooblayout_ecc, 415 .free = w35n01jw_ooblayout_free, 416 }; 417 418 static int w25n02kv_ecc_get_status(struct spinand_device *spinand, 419 u8 status) 420 { 421 struct nand_device *nand = spinand_to_nand(spinand); 422 u8 mbf = 0; 423 struct spi_mem_op op = SPINAND_OP(spinand, get_feature, 424 0x30, spinand->scratchbuf); 425 426 switch (status & STATUS_ECC_MASK) { 427 case STATUS_ECC_NO_BITFLIPS: 428 return 0; 429 430 case STATUS_ECC_UNCOR_ERROR: 431 return -EBADMSG; 432 433 case STATUS_ECC_HAS_BITFLIPS: 434 case W25N04KV_STATUS_ECC_5_8_BITFLIPS: 435 /* 436 * Let's try to retrieve the real maximum number of bitflips 437 * in order to avoid forcing the wear-leveling layer to move 438 * data around if it's not necessary. 439 */ 440 if (spi_mem_exec_op(spinand->spimem, &op)) 441 return nanddev_get_ecc_conf(nand)->strength; 442 443 mbf = *(spinand->scratchbuf) >> 4; 444 445 if (WARN_ON(mbf > nanddev_get_ecc_conf(nand)->strength || !mbf)) 446 return nanddev_get_ecc_conf(nand)->strength; 447 448 return mbf; 449 450 default: 451 break; 452 } 453 454 return -EINVAL; 455 } 456 457 static int w25w35nxxjw_ecc_get_status(struct spinand_device *spinand, u8 status) 458 { 459 switch (status & STATUS_ECC_MASK) { 460 case STATUS_ECC_NO_BITFLIPS: 461 return 0; 462 463 case STATUS_ECC_HAS_BITFLIPS: 464 return 1; 465 466 case STATUS_ECC_UNCOR_ERROR: 467 case W25W35NXXJW_STATUS_ECC_MULT_UNCOR: 468 return -EBADMSG; 469 470 default: 471 break; 472 } 473 474 return -EINVAL; 475 } 476 477 static int w25n0xjw_set_sr4_hs(struct spinand_device *spinand, bool enable) 478 { 479 int ret; 480 u8 sr4; 481 482 ret = spinand_read_reg_op(spinand, W25N0XJW_SR4, &sr4); 483 if (ret) 484 return ret; 485 486 if (enable) 487 sr4 |= W25N0XJW_SR4_HS; 488 else 489 sr4 &= ~W25N0XJW_SR4_HS; 490 491 return spinand_write_reg_op(spinand, W25N0XJW_SR4, sr4); 492 } 493 494 /* 495 * SDR dual and quad I/O operations over 104MHz require the HS bit to 496 * enable a few more dummy cycles. 497 */ 498 static bool w25n0xjw_op_needs_hs(const struct spi_mem_op *op) 499 { 500 if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) 501 return false; 502 else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1) 503 return false; 504 else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ) 505 return false; 506 507 return true; 508 } 509 510 static int w25n0xjw_hs_cfg(struct spinand_device *spinand, 511 enum spinand_bus_interface iface) 512 { 513 const struct spi_mem_op *op; 514 515 if (iface != SSDR) 516 return -EOPNOTSUPP; 517 518 /* 519 * At this stage, we do not yet know the continuous read template, nor 520 * if there is going to be one. Let's assume the continuous read 521 * template will be selected with the same heuristics as the buffered 522 * read variant, as there cannot be a HS configuration mismatch between 523 * them. 524 */ 525 op = spinand->op_templates->read_cache; 526 527 return w25n0xjw_set_sr4_hs(spinand, w25n0xjw_op_needs_hs(op)); 528 } 529 530 static int w25n0xjw_set_cont_read(struct spinand_device *spinand, bool enable) 531 { 532 u8 mask = enable ? 0 : WINBOND_CFG_BUF_READ; 533 534 return spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ, mask); 535 } 536 537 static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val) 538 { 539 struct spi_mem_op op = SPINAND_OP(spinand, winbond_write_vcr, 540 reg, spinand->scratchbuf); 541 int ret; 542 543 *spinand->scratchbuf = val; 544 545 ret = spinand_write_enable_op(spinand); 546 if (ret) 547 return ret; 548 549 ret = spi_mem_exec_op(spinand->spimem, &op); 550 if (ret) 551 return ret; 552 553 /* 554 * Write VCR operation doesn't set the busy bit in SR, which means we 555 * cannot perform a status poll. Minimum time of 50ns is needed to 556 * complete the write. 557 */ 558 ndelay(50); 559 560 return 0; 561 } 562 563 static int w35n0xjw_vcr_cfg(struct spinand_device *spinand, 564 enum spinand_bus_interface iface) 565 { 566 const struct spi_mem_op *ref_op; 567 unsigned int dummy_cycles; 568 bool dtr, single; 569 u8 io_mode; 570 int ret; 571 572 switch (iface) { 573 case SSDR: 574 ref_op = spinand->ssdr_op_templates.read_cache; 575 break; 576 case ODTR: 577 ref_op = spinand->odtr_op_templates.read_cache; 578 break; 579 default: 580 return -EOPNOTSUPP; 581 } 582 583 dummy_cycles = ((ref_op->dummy.nbytes * 8) / ref_op->dummy.buswidth) / 584 (ref_op->dummy.dtr ? 2 : 1); 585 switch (dummy_cycles) { 586 case 8: 587 case 12: 588 case 16: 589 case 20: 590 case 24: 591 case 28: 592 break; 593 default: 594 return -EINVAL; 595 } 596 597 ret = w35n0xjw_write_vcr(spinand, W35N01JW_VCR_DUMMY_CLOCK_REG, dummy_cycles); 598 if (ret) 599 return ret; 600 601 single = (ref_op->cmd.buswidth == 1 && 602 ref_op->addr.buswidth == 1 && 603 ref_op->data.buswidth == 1); 604 dtr = (ref_op->cmd.dtr && ref_op->addr.dtr && ref_op->data.dtr); 605 if (single && !dtr) 606 io_mode = W35N01JW_VCR_IO_MODE_SINGLE_SDR; 607 else if (!single && !dtr) 608 io_mode = W35N01JW_VCR_IO_MODE_OCTAL_SDR; 609 else if (!single && dtr) 610 io_mode = W35N01JW_VCR_IO_MODE_OCTAL_DDR; 611 else 612 return -EINVAL; 613 614 ret = w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode); 615 if (ret) 616 return ret; 617 618 return 0; 619 } 620 621 static int w35n0xjw_set_cont_read(struct spinand_device *spinand, bool enable) 622 { 623 const struct spi_mem_op *cont_op = spinand->op_templates->cont_read_cache; 624 u8 mask = enable ? 0 : WINBOND_CFG_BUF_READ; 625 626 if (cont_op && enable && spinand_op_is_odtr(cont_op) && 627 cont_op->max_freq >= 90 * HZ_PER_MHZ) 628 mask |= WINBOND_CFG_HFREQ; 629 630 return spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ | WINBOND_CFG_HFREQ, mask); 631 } 632 633 static const struct spinand_info winbond_spinand_table[] = { 634 /* 512M-bit densities */ 635 SPINAND_INFO("W25N512GW", /* 1.8V */ 636 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x20), 637 NAND_MEMORG(1, 2048, 64, 64, 512, 10, 1, 1, 1), 638 NAND_ECCREQ(1, 512), 639 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 640 &write_cache_variants, 641 &update_cache_variants), 642 0, 643 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), 644 /* 1G-bit densities */ 645 SPINAND_INFO("W25N01GV", /* 3.3V */ 646 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21), 647 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 648 NAND_ECCREQ(1, 512), 649 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 650 &write_cache_variants, 651 &update_cache_variants), 652 0, 653 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), 654 SPINAND_INFO("W25N01GW", /* 1.8V */ 655 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x21), 656 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 657 NAND_ECCREQ(1, 512), 658 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 659 &write_cache_variants, 660 &update_cache_variants), 661 0, 662 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), 663 SPINAND_INFO("W25N01JW", /* high-speed 1.8V */ 664 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21), 665 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 666 NAND_ECCREQ(1, 512), 667 SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants, 668 &write_cache_variants, 669 &update_cache_variants, 670 &cont_read_cache_dual_quad_dtr_variants), 671 SPINAND_HAS_QE_BIT, 672 SPINAND_ECCINFO(&w25n01jw_ooblayout, w25w35nxxjw_ecc_get_status), 673 SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg), 674 SPINAND_CONT_READ(w25n0xjw_set_cont_read)), 675 SPINAND_INFO("W25N01KV", /* 3.3V */ 676 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21), 677 NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1), 678 NAND_ECCREQ(4, 512), 679 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 680 &write_cache_variants, 681 &update_cache_variants), 682 0, 683 SPINAND_ECCINFO(&w25n01kv_ooblayout, w25n02kv_ecc_get_status)), 684 SPINAND_INFO("W35N01JW", /* 1.8V */ 685 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdc, 0x21), 686 NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 1, 1), 687 NAND_ECCREQ(1, 512), 688 SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_octal_variants, 689 &write_cache_octal_variants, 690 &update_cache_octal_variants, 691 &cont_read_cache_octal_variants), 692 0, 693 SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), 694 SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), 695 SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), 696 SPINAND_CONT_READ(w35n0xjw_set_cont_read)), 697 /* 2G-bit densities */ 698 SPINAND_INFO("W25M02GV", /* 2x1G-bit 3.3V */ 699 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21), 700 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2), 701 NAND_ECCREQ(1, 512), 702 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 703 &write_cache_variants, 704 &update_cache_variants), 705 0, 706 SPINAND_INFO_VENDOR_OPS(&winbond_w25_ops), 707 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL), 708 SPINAND_SELECT_TARGET(w25m02gv_select_target)), 709 SPINAND_INFO("W25N02JW", /* high-speed 1.8V */ 710 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22), 711 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1), 712 NAND_ECCREQ(1, 512), 713 SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants, 714 &write_cache_variants, 715 &update_cache_variants, 716 &cont_read_cache_dual_quad_dtr_variants), 717 SPINAND_HAS_QE_BIT, 718 SPINAND_ECCINFO(&w25m02gv_ooblayout, w25w35nxxjw_ecc_get_status), 719 SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg), 720 SPINAND_CONT_READ(w25n0xjw_set_cont_read)), 721 SPINAND_INFO("W25N02KV", /* 3.3V */ 722 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22), 723 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), 724 NAND_ECCREQ(8, 512), 725 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 726 &write_cache_variants, 727 &update_cache_variants), 728 0, 729 SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)), 730 SPINAND_INFO("W25N02KW", /* 1.8V */ 731 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x22), 732 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), 733 NAND_ECCREQ(8, 512), 734 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 735 &write_cache_variants, 736 &update_cache_variants), 737 0, 738 SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)), 739 SPINAND_INFO("W35N02JW", /* 1.8V */ 740 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x22), 741 NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 2, 1), 742 NAND_ECCREQ(1, 512), 743 SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_octal_variants, 744 &write_cache_octal_variants, 745 &update_cache_octal_variants, 746 &cont_read_cache_octal_variants), 747 SPINAND_ODTR_PACKED_PAGE_READ, 748 SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), 749 SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), 750 SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), 751 SPINAND_CONT_READ(w35n0xjw_set_cont_read)), 752 /* 4G-bit densities */ 753 SPINAND_INFO("W25N04KV", /* 3.3V */ 754 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23), 755 NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1), 756 NAND_ECCREQ(8, 512), 757 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 758 &write_cache_variants, 759 &update_cache_variants), 760 0, 761 SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)), 762 SPINAND_INFO("W25N04KW", /* 1.8V */ 763 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x23), 764 NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1), 765 NAND_ECCREQ(8, 512), 766 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 767 &write_cache_variants, 768 &update_cache_variants), 769 0, 770 SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)), 771 SPINAND_INFO("W35N04JW", /* 1.8V */ 772 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x23), 773 NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 4, 1), 774 NAND_ECCREQ(1, 512), 775 SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_octal_variants, 776 &write_cache_octal_variants, 777 &update_cache_octal_variants, 778 &cont_read_cache_octal_variants), 779 SPINAND_ODTR_PACKED_PAGE_READ, 780 SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops), 781 SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status), 782 SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg), 783 SPINAND_CONT_READ(w35n0xjw_set_cont_read)), 784 }; 785 786 static int winbond_spinand_init(struct spinand_device *spinand) 787 { 788 struct nand_device *nand = spinand_to_nand(spinand); 789 unsigned int i; 790 791 /* 792 * Make sure all dies are in buffer read mode and not continuous read 793 * mode. 794 */ 795 for (i = 0; i < nand->memorg.ntargets; i++) { 796 spinand_select_target(spinand, i); 797 spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ, 798 WINBOND_CFG_BUF_READ); 799 } 800 801 return 0; 802 } 803 804 static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { 805 .init = winbond_spinand_init, 806 }; 807 808 const struct spinand_manufacturer winbond_spinand_manufacturer = { 809 .id = SPINAND_MFR_WINBOND, 810 .name = "Winbond", 811 .chips = winbond_spinand_table, 812 .nchips = ARRAY_SIZE(winbond_spinand_table), 813 .ops = &winbond_spinand_manuf_ops, 814 }; 815