1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3 /*
4 Copyright (c) 2001, 2002 by D-Link Corporation
5 Written by Edward Peng.<edward_peng@dlink.com.tw>
6 Created 03-May-2001, base on Linux' sundance.c.
7
8 */
9
10 #include "dl2k.h"
11 #include <linux/dma-mapping.h>
12
13 #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
14 #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
15 #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
16 #define dr32(reg) ioread32(ioaddr + (reg))
17 #define dr16(reg) ioread16(ioaddr + (reg))
18 #define dr8(reg) ioread8(ioaddr + (reg))
19
20 #define MAX_UNITS 8
21 static int mtu[MAX_UNITS];
22 static int vlan[MAX_UNITS];
23 static int jumbo[MAX_UNITS];
24 static char *media[MAX_UNITS];
25 static int tx_flow=-1;
26 static int rx_flow=-1;
27 static int copy_thresh;
28 static int rx_coalesce=10; /* Rx frame count each interrupt */
29 static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
30 static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
31
32
33 MODULE_AUTHOR ("Edward Peng");
34 MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
35 MODULE_LICENSE("GPL");
36 module_param_array(mtu, int, NULL, 0);
37 module_param_array(media, charp, NULL, 0);
38 module_param_array(vlan, int, NULL, 0);
39 module_param_array(jumbo, int, NULL, 0);
40 module_param(tx_flow, int, 0);
41 module_param(rx_flow, int, 0);
42 module_param(copy_thresh, int, 0);
43 module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
44 module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
45 module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
46
47
48 /* Enable the default interrupts */
49 #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
50 UpdateStats | LinkEvent)
51
dl2k_enable_int(struct netdev_private * np)52 static void dl2k_enable_int(struct netdev_private *np)
53 {
54 void __iomem *ioaddr = np->ioaddr;
55
56 dw16(IntEnable, DEFAULT_INTR);
57 }
58
59 static const int max_intrloop = 50;
60 static const int multicast_filter_limit = 0x40;
61
62 static int rio_open (struct net_device *dev);
63 static void rio_timer (struct timer_list *t);
64 static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue);
65 static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
66 static irqreturn_t rio_interrupt (int irq, void *dev_instance);
67 static void rio_free_tx (struct net_device *dev, int irq);
68 static void tx_error (struct net_device *dev, int tx_status);
69 static int receive_packet (struct net_device *dev);
70 static void rio_error (struct net_device *dev, int int_status);
71 static void set_multicast (struct net_device *dev);
72 static struct net_device_stats *get_stats (struct net_device *dev);
73 static int clear_stats (struct net_device *dev);
74 static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
75 static int rio_close (struct net_device *dev);
76 static int find_miiphy (struct net_device *dev);
77 static int parse_eeprom (struct net_device *dev);
78 static int read_eeprom (struct netdev_private *, int eep_addr);
79 static int mii_wait_link (struct net_device *dev, int wait);
80 static int mii_set_media (struct net_device *dev);
81 static int mii_get_media (struct net_device *dev);
82 static int mii_set_media_pcs (struct net_device *dev);
83 static int mii_get_media_pcs (struct net_device *dev);
84 static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
85 static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
86 u16 data);
87
88 static const struct ethtool_ops ethtool_ops;
89
90 static const struct net_device_ops netdev_ops = {
91 .ndo_open = rio_open,
92 .ndo_start_xmit = start_xmit,
93 .ndo_stop = rio_close,
94 .ndo_get_stats = get_stats,
95 .ndo_validate_addr = eth_validate_addr,
96 .ndo_set_mac_address = eth_mac_addr,
97 .ndo_set_rx_mode = set_multicast,
98 .ndo_eth_ioctl = rio_ioctl,
99 .ndo_tx_timeout = rio_tx_timeout,
100 };
101
102 static int
rio_probe1(struct pci_dev * pdev,const struct pci_device_id * ent)103 rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
104 {
105 struct net_device *dev;
106 struct netdev_private *np;
107 static int card_idx;
108 int chip_idx = ent->driver_data;
109 int err, irq;
110 void __iomem *ioaddr;
111 void *ring_space;
112 dma_addr_t ring_dma;
113
114 err = pci_enable_device (pdev);
115 if (err)
116 return err;
117
118 irq = pdev->irq;
119 err = pci_request_regions (pdev, "dl2k");
120 if (err)
121 goto err_out_disable;
122
123 pci_set_master (pdev);
124
125 err = -ENOMEM;
126
127 dev = alloc_etherdev (sizeof (*np));
128 if (!dev)
129 goto err_out_res;
130 SET_NETDEV_DEV(dev, &pdev->dev);
131
132 np = netdev_priv(dev);
133
134 /* IO registers range. */
135 ioaddr = pci_iomap(pdev, 0, 0);
136 if (!ioaddr)
137 goto err_out_dev;
138 np->eeprom_addr = ioaddr;
139
140 #ifdef MEM_MAPPING
141 /* MM registers range. */
142 ioaddr = pci_iomap(pdev, 1, 0);
143 if (!ioaddr)
144 goto err_out_iounmap;
145 #endif
146 np->ioaddr = ioaddr;
147 np->chip_id = chip_idx;
148 np->pdev = pdev;
149
150 spin_lock_init(&np->stats_lock);
151 spin_lock_init (&np->tx_lock);
152 spin_lock_init (&np->rx_lock);
153
154 /* Parse manual configuration */
155 np->an_enable = 1;
156 np->tx_coalesce = 1;
157 if (card_idx < MAX_UNITS) {
158 if (media[card_idx] != NULL) {
159 np->an_enable = 0;
160 if (strcmp (media[card_idx], "auto") == 0 ||
161 strcmp (media[card_idx], "autosense") == 0 ||
162 strcmp (media[card_idx], "0") == 0 ) {
163 np->an_enable = 2;
164 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
165 strcmp (media[card_idx], "4") == 0) {
166 np->speed = 100;
167 np->full_duplex = 1;
168 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
169 strcmp (media[card_idx], "3") == 0) {
170 np->speed = 100;
171 np->full_duplex = 0;
172 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
173 strcmp (media[card_idx], "2") == 0) {
174 np->speed = 10;
175 np->full_duplex = 1;
176 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
177 strcmp (media[card_idx], "1") == 0) {
178 np->speed = 10;
179 np->full_duplex = 0;
180 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
181 strcmp (media[card_idx], "6") == 0) {
182 np->speed=1000;
183 np->full_duplex=1;
184 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
185 strcmp (media[card_idx], "5") == 0) {
186 np->speed = 1000;
187 np->full_duplex = 0;
188 } else {
189 np->an_enable = 1;
190 }
191 }
192 if (jumbo[card_idx] != 0) {
193 np->jumbo = 1;
194 dev->mtu = MAX_JUMBO;
195 } else {
196 np->jumbo = 0;
197 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
198 dev->mtu = mtu[card_idx];
199 }
200 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
201 vlan[card_idx] : 0;
202 if (rx_coalesce > 0 && rx_timeout > 0) {
203 np->rx_coalesce = rx_coalesce;
204 np->rx_timeout = rx_timeout;
205 np->coalesce = 1;
206 }
207 np->tx_flow = (tx_flow == 0) ? 0 : 1;
208 np->rx_flow = (rx_flow == 0) ? 0 : 1;
209
210 if (tx_coalesce < 1)
211 tx_coalesce = 1;
212 else if (tx_coalesce > TX_RING_SIZE-1)
213 tx_coalesce = TX_RING_SIZE - 1;
214 }
215 dev->netdev_ops = &netdev_ops;
216 dev->watchdog_timeo = TX_TIMEOUT;
217 dev->ethtool_ops = ðtool_ops;
218 #if 0
219 dev->features = NETIF_F_IP_CSUM;
220 #endif
221 /* MTU range: 68 - 1536 or 8000 */
222 dev->min_mtu = ETH_MIN_MTU;
223 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
224
225 pci_set_drvdata (pdev, dev);
226
227 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE, &ring_dma,
228 GFP_KERNEL);
229 if (!ring_space)
230 goto err_out_iounmap;
231 np->tx_ring = ring_space;
232 np->tx_ring_dma = ring_dma;
233
234 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE, &ring_dma,
235 GFP_KERNEL);
236 if (!ring_space)
237 goto err_out_unmap_tx;
238 np->rx_ring = ring_space;
239 np->rx_ring_dma = ring_dma;
240
241 /* Parse eeprom data */
242 parse_eeprom (dev);
243
244 /* Find PHY address */
245 err = find_miiphy (dev);
246 if (err)
247 goto err_out_unmap_rx;
248
249 /* Fiber device? */
250 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
251 np->link_status = 0;
252 /* Set media and reset PHY */
253 if (np->phy_media) {
254 /* default Auto-Negotiation for fiber deivices */
255 if (np->an_enable == 2) {
256 np->an_enable = 1;
257 }
258 } else {
259 /* Auto-Negotiation is mandatory for 1000BASE-T,
260 IEEE 802.3ab Annex 28D page 14 */
261 if (np->speed == 1000)
262 np->an_enable = 1;
263 }
264
265 err = register_netdev (dev);
266 if (err)
267 goto err_out_unmap_rx;
268
269 card_idx++;
270
271 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
272 dev->name, np->name, dev->dev_addr, irq);
273 if (tx_coalesce > 1)
274 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
275 tx_coalesce);
276 if (np->coalesce)
277 printk(KERN_INFO
278 "rx_coalesce:\t%d packets\n"
279 "rx_timeout: \t%d ns\n",
280 np->rx_coalesce, np->rx_timeout*640);
281 if (np->vlan)
282 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
283 return 0;
284
285 err_out_unmap_rx:
286 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
287 np->rx_ring_dma);
288 err_out_unmap_tx:
289 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
290 np->tx_ring_dma);
291 err_out_iounmap:
292 #ifdef MEM_MAPPING
293 pci_iounmap(pdev, np->ioaddr);
294 #endif
295 pci_iounmap(pdev, np->eeprom_addr);
296 err_out_dev:
297 free_netdev (dev);
298 err_out_res:
299 pci_release_regions (pdev);
300 err_out_disable:
301 pci_disable_device (pdev);
302 return err;
303 }
304
305 static int
find_miiphy(struct net_device * dev)306 find_miiphy (struct net_device *dev)
307 {
308 struct netdev_private *np = netdev_priv(dev);
309 int i, phy_found = 0;
310
311 np->phy_addr = 1;
312
313 for (i = 31; i >= 0; i--) {
314 int mii_status = mii_read (dev, i, 1);
315 if (mii_status != 0xffff && mii_status != 0x0000) {
316 np->phy_addr = i;
317 phy_found++;
318 }
319 }
320 if (!phy_found) {
321 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
322 return -ENODEV;
323 }
324 return 0;
325 }
326
327 static int
parse_eeprom(struct net_device * dev)328 parse_eeprom (struct net_device *dev)
329 {
330 struct netdev_private *np = netdev_priv(dev);
331 void __iomem *ioaddr = np->ioaddr;
332 int i, j;
333 u8 sromdata[256];
334 u8 *psib;
335 u32 crc;
336 PSROM_t psrom = (PSROM_t) sromdata;
337
338 int cid, next;
339
340 for (i = 0; i < 128; i++)
341 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
342
343 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
344 /* Check CRC */
345 crc = ~ether_crc_le (256 - 4, sromdata);
346 if (psrom->crc != cpu_to_le32(crc)) {
347 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
348 dev->name);
349 return -1;
350 }
351 }
352
353 /* Set MAC address */
354 eth_hw_addr_set(dev, psrom->mac_addr);
355
356 if (np->chip_id == CHIP_IP1000A) {
357 np->led_mode = le16_to_cpu(psrom->led_mode);
358 return 0;
359 }
360
361 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
362 return 0;
363 }
364
365 /* Parse Software Information Block */
366 i = 0x30;
367 psib = (u8 *) sromdata;
368 do {
369 cid = psib[i++];
370 next = psib[i++];
371 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
372 printk (KERN_ERR "Cell data error\n");
373 return -1;
374 }
375 switch (cid) {
376 case 0: /* Format version */
377 break;
378 case 1: /* End of cell */
379 return 0;
380 case 2: /* Duplex Polarity */
381 np->duplex_polarity = psib[i];
382 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
383 break;
384 case 3: /* Wake Polarity */
385 np->wake_polarity = psib[i];
386 break;
387 case 9: /* Adapter description */
388 j = (next - i > 255) ? 255 : next - i;
389 memcpy (np->name, &(psib[i]), j);
390 break;
391 case 4:
392 case 5:
393 case 6:
394 case 7:
395 case 8: /* Reversed */
396 break;
397 default: /* Unknown cell */
398 return -1;
399 }
400 i = next;
401 } while (1);
402
403 return 0;
404 }
405
rio_set_led_mode(struct net_device * dev)406 static void rio_set_led_mode(struct net_device *dev)
407 {
408 struct netdev_private *np = netdev_priv(dev);
409 void __iomem *ioaddr = np->ioaddr;
410 u32 mode;
411
412 if (np->chip_id != CHIP_IP1000A)
413 return;
414
415 mode = dr32(ASICCtrl);
416 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
417
418 if (np->led_mode & 0x01)
419 mode |= IPG_AC_LED_MODE;
420 if (np->led_mode & 0x02)
421 mode |= IPG_AC_LED_MODE_BIT_1;
422 if (np->led_mode & 0x08)
423 mode |= IPG_AC_LED_SPEED;
424
425 dw32(ASICCtrl, mode);
426 }
427
desc_to_dma(struct netdev_desc * desc)428 static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
429 {
430 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
431 }
432
free_list(struct net_device * dev)433 static void free_list(struct net_device *dev)
434 {
435 struct netdev_private *np = netdev_priv(dev);
436 struct sk_buff *skb;
437 int i;
438
439 /* Free all the skbuffs in the queue. */
440 for (i = 0; i < RX_RING_SIZE; i++) {
441 skb = np->rx_skbuff[i];
442 if (skb) {
443 dma_unmap_single(&np->pdev->dev,
444 desc_to_dma(&np->rx_ring[i]),
445 skb->len, DMA_FROM_DEVICE);
446 dev_kfree_skb(skb);
447 np->rx_skbuff[i] = NULL;
448 }
449 np->rx_ring[i].status = 0;
450 np->rx_ring[i].fraginfo = 0;
451 }
452 for (i = 0; i < TX_RING_SIZE; i++) {
453 skb = np->tx_skbuff[i];
454 if (skb) {
455 dma_unmap_single(&np->pdev->dev,
456 desc_to_dma(&np->tx_ring[i]),
457 skb->len, DMA_TO_DEVICE);
458 dev_kfree_skb(skb);
459 np->tx_skbuff[i] = NULL;
460 }
461 }
462 }
463
rio_reset_ring(struct netdev_private * np)464 static void rio_reset_ring(struct netdev_private *np)
465 {
466 int i;
467
468 np->cur_rx = 0;
469 np->cur_tx = 0;
470 np->old_rx = 0;
471 np->old_tx = 0;
472
473 for (i = 0; i < TX_RING_SIZE; i++)
474 np->tx_ring[i].status = cpu_to_le64(TFDDone);
475
476 for (i = 0; i < RX_RING_SIZE; i++)
477 np->rx_ring[i].status = 0;
478 }
479
480 /* allocate and initialize Tx and Rx descriptors */
alloc_list(struct net_device * dev)481 static int alloc_list(struct net_device *dev)
482 {
483 struct netdev_private *np = netdev_priv(dev);
484 int i;
485
486 rio_reset_ring(np);
487 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
488
489 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
490 for (i = 0; i < TX_RING_SIZE; i++) {
491 np->tx_skbuff[i] = NULL;
492 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
493 ((i + 1) % TX_RING_SIZE) *
494 sizeof(struct netdev_desc));
495 }
496
497 /* Initialize Rx descriptors & allocate buffers */
498 for (i = 0; i < RX_RING_SIZE; i++) {
499 /* Allocated fixed size of skbuff */
500 struct sk_buff *skb;
501
502 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
503 np->rx_skbuff[i] = skb;
504 if (!skb) {
505 free_list(dev);
506 return -ENOMEM;
507 }
508
509 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
510 ((i + 1) % RX_RING_SIZE) *
511 sizeof(struct netdev_desc));
512 /* Rubicon now supports 40 bits of addressing space. */
513 np->rx_ring[i].fraginfo =
514 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
515 np->rx_buf_sz, DMA_FROM_DEVICE));
516 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
517 }
518
519 return 0;
520 }
521
rio_hw_init(struct net_device * dev)522 static void rio_hw_init(struct net_device *dev)
523 {
524 struct netdev_private *np = netdev_priv(dev);
525 void __iomem *ioaddr = np->ioaddr;
526 int i;
527 u16 macctrl;
528
529 /* Reset all logic functions */
530 dw16(ASICCtrl + 2,
531 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
532 mdelay(10);
533
534 rio_set_led_mode(dev);
535
536 /* DebugCtrl bit 4, 5, 9 must set */
537 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
538
539 if (np->chip_id == CHIP_IP1000A &&
540 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
541 /* PHY magic taken from ipg driver, undocumented registers */
542 mii_write(dev, np->phy_addr, 31, 0x0001);
543 mii_write(dev, np->phy_addr, 27, 0x01e0);
544 mii_write(dev, np->phy_addr, 31, 0x0002);
545 mii_write(dev, np->phy_addr, 27, 0xeb8e);
546 mii_write(dev, np->phy_addr, 31, 0x0000);
547 mii_write(dev, np->phy_addr, 30, 0x005e);
548 /* advertise 1000BASE-T half & full duplex, prefer MASTER */
549 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
550 }
551
552 if (np->phy_media)
553 mii_set_media_pcs(dev);
554 else
555 mii_set_media(dev);
556
557 /* Jumbo frame */
558 if (np->jumbo != 0)
559 dw16(MaxFrameSize, MAX_JUMBO+14);
560
561 /* Set RFDListPtr */
562 dw32(RFDListPtr0, np->rx_ring_dma);
563 dw32(RFDListPtr1, 0);
564
565 /* Set station address */
566 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
567 * too. However, it doesn't work on IP1000A so we use 16-bit access.
568 */
569 for (i = 0; i < 3; i++)
570 dw16(StationAddr0 + 2 * i, get_unaligned_le16(&dev->dev_addr[2 * i]));
571
572 set_multicast (dev);
573 if (np->coalesce) {
574 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
575 }
576 /* Set RIO to poll every N*320nsec. */
577 dw8(RxDMAPollPeriod, 0x20);
578 dw8(TxDMAPollPeriod, 0xff);
579 dw8(RxDMABurstThresh, 0x30);
580 dw8(RxDMAUrgentThresh, 0x30);
581 dw32(RmonStatMask, 0x0007ffff);
582 /* clear statistics */
583 clear_stats (dev);
584
585 /* VLAN supported */
586 if (np->vlan) {
587 /* priority field in RxDMAIntCtrl */
588 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
589 /* VLANId */
590 dw16(VLANId, np->vlan);
591 /* Length/Type should be 0x8100 */
592 dw32(VLANTag, 0x8100 << 16 | np->vlan);
593 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
594 VLAN information tagged by TFC' VID, CFI fields. */
595 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
596 }
597
598 /* Start Tx/Rx */
599 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
600
601 macctrl = 0;
602 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
603 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
604 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
605 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
606 dw16(MACCtrl, macctrl);
607 }
608
rio_hw_stop(struct net_device * dev)609 static void rio_hw_stop(struct net_device *dev)
610 {
611 struct netdev_private *np = netdev_priv(dev);
612 void __iomem *ioaddr = np->ioaddr;
613
614 /* Disable interrupts */
615 dw16(IntEnable, 0);
616
617 /* Stop Tx and Rx logics */
618 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
619 }
620
rio_open(struct net_device * dev)621 static int rio_open(struct net_device *dev)
622 {
623 struct netdev_private *np = netdev_priv(dev);
624 const int irq = np->pdev->irq;
625 int i;
626
627 i = alloc_list(dev);
628 if (i)
629 return i;
630
631 rio_hw_init(dev);
632
633 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
634 if (i) {
635 rio_hw_stop(dev);
636 free_list(dev);
637 return i;
638 }
639
640 timer_setup(&np->timer, rio_timer, 0);
641 np->timer.expires = jiffies + 1 * HZ;
642 add_timer(&np->timer);
643
644 netif_start_queue (dev);
645
646 dl2k_enable_int(np);
647 return 0;
648 }
649
650 static void
rio_timer(struct timer_list * t)651 rio_timer (struct timer_list *t)
652 {
653 struct netdev_private *np = timer_container_of(np, t, timer);
654 struct net_device *dev = pci_get_drvdata(np->pdev);
655 unsigned int entry;
656 int next_tick = 1*HZ;
657 unsigned long flags;
658
659 spin_lock_irqsave(&np->rx_lock, flags);
660 /* Recover rx ring exhausted error */
661 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
662 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
663 /* Re-allocate skbuffs to fill the descriptor ring */
664 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
665 struct sk_buff *skb;
666 entry = np->old_rx % RX_RING_SIZE;
667 /* Dropped packets don't need to re-allocate */
668 if (np->rx_skbuff[entry] == NULL) {
669 skb = netdev_alloc_skb_ip_align(dev,
670 np->rx_buf_sz);
671 if (skb == NULL) {
672 np->rx_ring[entry].fraginfo = 0;
673 printk (KERN_INFO
674 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
675 dev->name, entry);
676 break;
677 }
678 np->rx_skbuff[entry] = skb;
679 np->rx_ring[entry].fraginfo =
680 cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
681 np->rx_buf_sz, DMA_FROM_DEVICE));
682 }
683 np->rx_ring[entry].fraginfo |=
684 cpu_to_le64((u64)np->rx_buf_sz << 48);
685 np->rx_ring[entry].status = 0;
686 } /* end for */
687 } /* end if */
688 spin_unlock_irqrestore (&np->rx_lock, flags);
689 np->timer.expires = jiffies + next_tick;
690 add_timer(&np->timer);
691 }
692
693 static void
rio_tx_timeout(struct net_device * dev,unsigned int txqueue)694 rio_tx_timeout (struct net_device *dev, unsigned int txqueue)
695 {
696 struct netdev_private *np = netdev_priv(dev);
697 void __iomem *ioaddr = np->ioaddr;
698
699 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
700 dev->name, dr32(TxStatus));
701 rio_free_tx(dev, 0);
702 dev->if_port = 0;
703 netif_trans_update(dev); /* prevent tx timeout */
704 }
705
706 static netdev_tx_t
start_xmit(struct sk_buff * skb,struct net_device * dev)707 start_xmit (struct sk_buff *skb, struct net_device *dev)
708 {
709 struct netdev_private *np = netdev_priv(dev);
710 void __iomem *ioaddr = np->ioaddr;
711 struct netdev_desc *txdesc;
712 unsigned entry;
713 u64 tfc_vlan_tag = 0;
714
715 if (np->link_status == 0) { /* Link Down */
716 dev_kfree_skb(skb);
717 return NETDEV_TX_OK;
718 }
719 entry = np->cur_tx % TX_RING_SIZE;
720 np->tx_skbuff[entry] = skb;
721 txdesc = &np->tx_ring[entry];
722
723 #if 0
724 if (skb->ip_summed == CHECKSUM_PARTIAL) {
725 txdesc->status |=
726 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
727 IPChecksumEnable);
728 }
729 #endif
730 if (np->vlan) {
731 tfc_vlan_tag = VLANTagInsert |
732 ((u64)np->vlan << 32) |
733 ((u64)skb->priority << 45);
734 }
735 txdesc->fraginfo = cpu_to_le64 (dma_map_single(&np->pdev->dev, skb->data,
736 skb->len, DMA_TO_DEVICE));
737 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
738
739 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
740 * Work around: Always use 1 descriptor in 10Mbps mode */
741 if (entry % np->tx_coalesce == 0 || np->speed == 10)
742 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
743 WordAlignDisable |
744 TxDMAIndicate |
745 (1 << FragCountShift));
746 else
747 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
748 WordAlignDisable |
749 (1 << FragCountShift));
750
751 /* TxDMAPollNow */
752 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
753 /* Schedule ISR */
754 dw32(CountDown, 10000);
755 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
756 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
757 < TX_QUEUE_LEN - 1 && np->speed != 10) {
758 /* do nothing */
759 } else if (!netif_queue_stopped(dev)) {
760 netif_stop_queue (dev);
761 }
762
763 /* The first TFDListPtr */
764 if (!dr32(TFDListPtr0)) {
765 dw32(TFDListPtr0, np->tx_ring_dma +
766 entry * sizeof (struct netdev_desc));
767 dw32(TFDListPtr1, 0);
768 }
769
770 return NETDEV_TX_OK;
771 }
772
773 static irqreturn_t
rio_interrupt(int irq,void * dev_instance)774 rio_interrupt (int irq, void *dev_instance)
775 {
776 struct net_device *dev = dev_instance;
777 struct netdev_private *np = netdev_priv(dev);
778 void __iomem *ioaddr = np->ioaddr;
779 unsigned int_status;
780 int cnt = max_intrloop;
781 int handled = 0;
782
783 while (1) {
784 int_status = dr16(IntStatus);
785 dw16(IntStatus, int_status);
786 int_status &= DEFAULT_INTR;
787 if (int_status == 0 || --cnt < 0)
788 break;
789 handled = 1;
790 /* Processing received packets */
791 if (int_status & RxDMAComplete)
792 receive_packet (dev);
793 /* TxDMAComplete interrupt */
794 if ((int_status & (TxDMAComplete|IntRequested))) {
795 int tx_status;
796 tx_status = dr32(TxStatus);
797 if (tx_status & 0x01)
798 tx_error (dev, tx_status);
799 /* Free used tx skbuffs */
800 rio_free_tx (dev, 1);
801 }
802
803 /* Handle uncommon events */
804 if (int_status &
805 (HostError | LinkEvent | UpdateStats))
806 rio_error (dev, int_status);
807 }
808 if (np->cur_tx != np->old_tx)
809 dw32(CountDown, 100);
810 return IRQ_RETVAL(handled);
811 }
812
813 static void
rio_free_tx(struct net_device * dev,int irq)814 rio_free_tx (struct net_device *dev, int irq)
815 {
816 struct netdev_private *np = netdev_priv(dev);
817 int entry = np->old_tx % TX_RING_SIZE;
818 unsigned long flag = 0;
819
820 if (irq)
821 spin_lock(&np->tx_lock);
822 else
823 spin_lock_irqsave(&np->tx_lock, flag);
824
825 /* Free used tx skbuffs */
826 while (entry != np->cur_tx) {
827 struct sk_buff *skb;
828
829 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
830 break;
831 skb = np->tx_skbuff[entry];
832 dma_unmap_single(&np->pdev->dev,
833 desc_to_dma(&np->tx_ring[entry]), skb->len,
834 DMA_TO_DEVICE);
835 if (irq)
836 dev_consume_skb_irq(skb);
837 else
838 dev_kfree_skb(skb);
839
840 np->tx_skbuff[entry] = NULL;
841 entry = (entry + 1) % TX_RING_SIZE;
842 }
843 if (irq)
844 spin_unlock(&np->tx_lock);
845 else
846 spin_unlock_irqrestore(&np->tx_lock, flag);
847 np->old_tx = entry;
848
849 /* If the ring is no longer full, clear tx_full and
850 call netif_wake_queue() */
851
852 if (netif_queue_stopped(dev) &&
853 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
854 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
855 netif_wake_queue (dev);
856 }
857 }
858
859 static void
tx_error(struct net_device * dev,int tx_status)860 tx_error (struct net_device *dev, int tx_status)
861 {
862 struct netdev_private *np = netdev_priv(dev);
863 void __iomem *ioaddr = np->ioaddr;
864 int frame_id;
865 int i;
866
867 frame_id = (tx_status & 0xffff0000);
868 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
869 dev->name, tx_status, frame_id);
870 /* Ttransmit Underrun */
871 if (tx_status & 0x10) {
872 dev->stats.tx_fifo_errors++;
873 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
874 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
875 dw16(ASICCtrl + 2,
876 TxReset | DMAReset | FIFOReset | NetworkReset);
877 /* Wait for ResetBusy bit clear */
878 for (i = 50; i > 0; i--) {
879 if (!(dr16(ASICCtrl + 2) & ResetBusy))
880 break;
881 mdelay (1);
882 }
883 rio_set_led_mode(dev);
884 rio_free_tx (dev, 1);
885 /* Reset TFDListPtr */
886 dw32(TFDListPtr0, np->tx_ring_dma +
887 np->old_tx * sizeof (struct netdev_desc));
888 dw32(TFDListPtr1, 0);
889
890 /* Let TxStartThresh stay default value */
891 }
892 /* Late Collision */
893 if (tx_status & 0x04) {
894 dev->stats.tx_fifo_errors++;
895 /* TxReset and clear FIFO */
896 dw16(ASICCtrl + 2, TxReset | FIFOReset);
897 /* Wait reset done */
898 for (i = 50; i > 0; i--) {
899 if (!(dr16(ASICCtrl + 2) & ResetBusy))
900 break;
901 mdelay (1);
902 }
903 rio_set_led_mode(dev);
904 /* Let TxStartThresh stay default value */
905 }
906
907 spin_lock(&np->stats_lock);
908 /* Maximum Collisions */
909 if (tx_status & 0x08)
910 dev->stats.collisions++;
911
912 dev->stats.tx_errors++;
913 spin_unlock(&np->stats_lock);
914
915 /* Restart the Tx */
916 dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
917 }
918
919 static int
receive_packet(struct net_device * dev)920 receive_packet (struct net_device *dev)
921 {
922 struct netdev_private *np = netdev_priv(dev);
923 int entry = np->cur_rx % RX_RING_SIZE;
924 int cnt = 30;
925
926 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
927 while (1) {
928 struct netdev_desc *desc = &np->rx_ring[entry];
929 int pkt_len;
930 u64 frame_status;
931
932 if (!(desc->status & cpu_to_le64(RFDDone)) ||
933 !(desc->status & cpu_to_le64(FrameStart)) ||
934 !(desc->status & cpu_to_le64(FrameEnd)))
935 break;
936
937 /* Chip omits the CRC. */
938 frame_status = le64_to_cpu(desc->status);
939 pkt_len = frame_status & 0xffff;
940 if (--cnt < 0)
941 break;
942 /* Update rx error statistics, drop packet. */
943 if (frame_status & RFS_Errors) {
944 dev->stats.rx_errors++;
945 if (frame_status & (RxRuntFrame | RxLengthError))
946 dev->stats.rx_length_errors++;
947 if (frame_status & RxFCSError)
948 dev->stats.rx_crc_errors++;
949 if (frame_status & RxAlignmentError && np->speed != 1000)
950 dev->stats.rx_frame_errors++;
951 if (frame_status & RxFIFOOverrun)
952 dev->stats.rx_fifo_errors++;
953 } else {
954 struct sk_buff *skb;
955
956 /* Small skbuffs for short packets */
957 if (pkt_len > copy_thresh) {
958 dma_unmap_single(&np->pdev->dev,
959 desc_to_dma(desc),
960 np->rx_buf_sz,
961 DMA_FROM_DEVICE);
962 skb_put (skb = np->rx_skbuff[entry], pkt_len);
963 np->rx_skbuff[entry] = NULL;
964 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
965 dma_sync_single_for_cpu(&np->pdev->dev,
966 desc_to_dma(desc),
967 np->rx_buf_sz,
968 DMA_FROM_DEVICE);
969 skb_copy_to_linear_data (skb,
970 np->rx_skbuff[entry]->data,
971 pkt_len);
972 skb_put (skb, pkt_len);
973 dma_sync_single_for_device(&np->pdev->dev,
974 desc_to_dma(desc),
975 np->rx_buf_sz,
976 DMA_FROM_DEVICE);
977 }
978 skb->protocol = eth_type_trans (skb, dev);
979 #if 0
980 /* Checksum done by hw, but csum value unavailable. */
981 if (np->pdev->pci_rev_id >= 0x0c &&
982 !(frame_status & (TCPError | UDPError | IPError))) {
983 skb->ip_summed = CHECKSUM_UNNECESSARY;
984 }
985 #endif
986 netif_rx (skb);
987 }
988 entry = (entry + 1) % RX_RING_SIZE;
989 }
990 spin_lock(&np->rx_lock);
991 np->cur_rx = entry;
992 /* Re-allocate skbuffs to fill the descriptor ring */
993 entry = np->old_rx;
994 while (entry != np->cur_rx) {
995 struct sk_buff *skb;
996 /* Dropped packets don't need to re-allocate */
997 if (np->rx_skbuff[entry] == NULL) {
998 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
999 if (skb == NULL) {
1000 np->rx_ring[entry].fraginfo = 0;
1001 printk (KERN_INFO
1002 "%s: receive_packet: "
1003 "Unable to re-allocate Rx skbuff.#%d\n",
1004 dev->name, entry);
1005 break;
1006 }
1007 np->rx_skbuff[entry] = skb;
1008 np->rx_ring[entry].fraginfo =
1009 cpu_to_le64(dma_map_single(&np->pdev->dev, skb->data,
1010 np->rx_buf_sz, DMA_FROM_DEVICE));
1011 }
1012 np->rx_ring[entry].fraginfo |=
1013 cpu_to_le64((u64)np->rx_buf_sz << 48);
1014 np->rx_ring[entry].status = 0;
1015 entry = (entry + 1) % RX_RING_SIZE;
1016 }
1017 np->old_rx = entry;
1018 spin_unlock(&np->rx_lock);
1019 return 0;
1020 }
1021
1022 static void
rio_error(struct net_device * dev,int int_status)1023 rio_error (struct net_device *dev, int int_status)
1024 {
1025 struct netdev_private *np = netdev_priv(dev);
1026 void __iomem *ioaddr = np->ioaddr;
1027 u16 macctrl;
1028
1029 /* Link change event */
1030 if (int_status & LinkEvent) {
1031 if (mii_wait_link (dev, 10) == 0) {
1032 printk (KERN_INFO "%s: Link up\n", dev->name);
1033 if (np->phy_media)
1034 mii_get_media_pcs (dev);
1035 else
1036 mii_get_media (dev);
1037 if (np->speed == 1000)
1038 np->tx_coalesce = tx_coalesce;
1039 else
1040 np->tx_coalesce = 1;
1041 macctrl = 0;
1042 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
1043 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
1044 macctrl |= (np->tx_flow) ?
1045 TxFlowControlEnable : 0;
1046 macctrl |= (np->rx_flow) ?
1047 RxFlowControlEnable : 0;
1048 dw16(MACCtrl, macctrl);
1049 np->link_status = 1;
1050 netif_carrier_on(dev);
1051 } else {
1052 printk (KERN_INFO "%s: Link off\n", dev->name);
1053 np->link_status = 0;
1054 netif_carrier_off(dev);
1055 }
1056 }
1057
1058 /* UpdateStats statistics registers */
1059 if (int_status & UpdateStats) {
1060 get_stats (dev);
1061 }
1062
1063 /* PCI Error, a catastronphic error related to the bus interface
1064 occurs, set GlobalReset and HostReset to reset. */
1065 if (int_status & HostError) {
1066 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1067 dev->name, int_status);
1068 dw16(ASICCtrl + 2, GlobalReset | HostReset);
1069 mdelay (500);
1070 rio_set_led_mode(dev);
1071 }
1072 }
1073
1074 static struct net_device_stats *
get_stats(struct net_device * dev)1075 get_stats (struct net_device *dev)
1076 {
1077 struct netdev_private *np = netdev_priv(dev);
1078 void __iomem *ioaddr = np->ioaddr;
1079 #ifdef MEM_MAPPING
1080 int i;
1081 #endif
1082 unsigned int stat_reg;
1083 unsigned long flags;
1084
1085 spin_lock_irqsave(&np->stats_lock, flags);
1086 /* All statistics registers need to be acknowledged,
1087 else statistic overflow could cause problems */
1088
1089 dev->stats.rx_packets += dr32(FramesRcvOk);
1090 dev->stats.tx_packets += dr32(FramesXmtOk);
1091 dev->stats.rx_bytes += dr32(OctetRcvOk);
1092 dev->stats.tx_bytes += dr32(OctetXmtOk);
1093
1094 dev->stats.multicast = dr32(McstFramesRcvdOk);
1095 dev->stats.collisions += dr32(SingleColFrames)
1096 + dr32(MultiColFrames);
1097
1098 /* detailed tx errors */
1099 stat_reg = dr16(FramesAbortXSColls);
1100 dev->stats.tx_aborted_errors += stat_reg;
1101 dev->stats.tx_errors += stat_reg;
1102
1103 stat_reg = dr16(CarrierSenseErrors);
1104 dev->stats.tx_carrier_errors += stat_reg;
1105 dev->stats.tx_errors += stat_reg;
1106
1107 /* Clear all other statistic register. */
1108 dr32(McstOctetXmtOk);
1109 dr16(BcstFramesXmtdOk);
1110 dr32(McstFramesXmtdOk);
1111 dr16(BcstFramesRcvdOk);
1112 dr16(MacControlFramesRcvd);
1113 dr16(FrameTooLongErrors);
1114 dr16(InRangeLengthErrors);
1115 dr16(FramesCheckSeqErrors);
1116 dr16(FramesLostRxErrors);
1117 dr32(McstOctetXmtOk);
1118 dr32(BcstOctetXmtOk);
1119 dr32(McstFramesXmtdOk);
1120 dr32(FramesWDeferredXmt);
1121 dr32(LateCollisions);
1122 dr16(BcstFramesXmtdOk);
1123 dr16(MacControlFramesXmtd);
1124 dr16(FramesWEXDeferal);
1125
1126 #ifdef MEM_MAPPING
1127 for (i = 0x100; i <= 0x150; i += 4)
1128 dr32(i);
1129 #endif
1130 dr16(TxJumboFrames);
1131 dr16(RxJumboFrames);
1132 dr16(TCPCheckSumErrors);
1133 dr16(UDPCheckSumErrors);
1134 dr16(IPCheckSumErrors);
1135
1136 spin_unlock_irqrestore(&np->stats_lock, flags);
1137
1138 return &dev->stats;
1139 }
1140
1141 static int
clear_stats(struct net_device * dev)1142 clear_stats (struct net_device *dev)
1143 {
1144 struct netdev_private *np = netdev_priv(dev);
1145 void __iomem *ioaddr = np->ioaddr;
1146 #ifdef MEM_MAPPING
1147 int i;
1148 #endif
1149
1150 /* All statistics registers need to be acknowledged,
1151 else statistic overflow could cause problems */
1152 dr32(FramesRcvOk);
1153 dr32(FramesXmtOk);
1154 dr32(OctetRcvOk);
1155 dr32(OctetXmtOk);
1156
1157 dr32(McstFramesRcvdOk);
1158 dr32(SingleColFrames);
1159 dr32(MultiColFrames);
1160 dr32(LateCollisions);
1161 /* detailed rx errors */
1162 dr16(FrameTooLongErrors);
1163 dr16(InRangeLengthErrors);
1164 dr16(FramesCheckSeqErrors);
1165 dr16(FramesLostRxErrors);
1166
1167 /* detailed tx errors */
1168 dr16(FramesAbortXSColls);
1169 dr16(CarrierSenseErrors);
1170
1171 /* Clear all other statistic register. */
1172 dr32(McstOctetXmtOk);
1173 dr16(BcstFramesXmtdOk);
1174 dr32(McstFramesXmtdOk);
1175 dr16(BcstFramesRcvdOk);
1176 dr16(MacControlFramesRcvd);
1177 dr32(McstOctetXmtOk);
1178 dr32(BcstOctetXmtOk);
1179 dr32(McstFramesXmtdOk);
1180 dr32(FramesWDeferredXmt);
1181 dr16(BcstFramesXmtdOk);
1182 dr16(MacControlFramesXmtd);
1183 dr16(FramesWEXDeferal);
1184 #ifdef MEM_MAPPING
1185 for (i = 0x100; i <= 0x150; i += 4)
1186 dr32(i);
1187 #endif
1188 dr16(TxJumboFrames);
1189 dr16(RxJumboFrames);
1190 dr16(TCPCheckSumErrors);
1191 dr16(UDPCheckSumErrors);
1192 dr16(IPCheckSumErrors);
1193 return 0;
1194 }
1195
1196 static void
set_multicast(struct net_device * dev)1197 set_multicast (struct net_device *dev)
1198 {
1199 struct netdev_private *np = netdev_priv(dev);
1200 void __iomem *ioaddr = np->ioaddr;
1201 u32 hash_table[2];
1202 u16 rx_mode = 0;
1203
1204 hash_table[0] = hash_table[1] = 0;
1205 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1206 hash_table[1] |= 0x02000000;
1207 if (dev->flags & IFF_PROMISC) {
1208 /* Receive all frames promiscuously. */
1209 rx_mode = ReceiveAllFrames;
1210 } else if ((dev->flags & IFF_ALLMULTI) ||
1211 (netdev_mc_count(dev) > multicast_filter_limit)) {
1212 /* Receive broadcast and multicast frames */
1213 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1214 } else if (!netdev_mc_empty(dev)) {
1215 struct netdev_hw_addr *ha;
1216 /* Receive broadcast frames and multicast frames filtering
1217 by Hashtable */
1218 rx_mode =
1219 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1220 netdev_for_each_mc_addr(ha, dev) {
1221 int bit, index = 0;
1222 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1223 /* The inverted high significant 6 bits of CRC are
1224 used as an index to hashtable */
1225 for (bit = 0; bit < 6; bit++)
1226 if (crc & (1 << (31 - bit)))
1227 index |= (1 << bit);
1228 hash_table[index / 32] |= (1 << (index % 32));
1229 }
1230 } else {
1231 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1232 }
1233 if (np->vlan) {
1234 /* ReceiveVLANMatch field in ReceiveMode */
1235 rx_mode |= ReceiveVLANMatch;
1236 }
1237
1238 dw32(HashTable0, hash_table[0]);
1239 dw32(HashTable1, hash_table[1]);
1240 dw16(ReceiveMode, rx_mode);
1241 }
1242
rio_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1243 static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1244 {
1245 struct netdev_private *np = netdev_priv(dev);
1246
1247 strscpy(info->driver, "dl2k", sizeof(info->driver));
1248 strscpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1249 }
1250
rio_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)1251 static int rio_get_link_ksettings(struct net_device *dev,
1252 struct ethtool_link_ksettings *cmd)
1253 {
1254 struct netdev_private *np = netdev_priv(dev);
1255 u32 supported, advertising;
1256
1257 if (np->phy_media) {
1258 /* fiber device */
1259 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1260 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1261 cmd->base.port = PORT_FIBRE;
1262 } else {
1263 /* copper device */
1264 supported = SUPPORTED_10baseT_Half |
1265 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1266 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1267 SUPPORTED_Autoneg | SUPPORTED_MII;
1268 advertising = ADVERTISED_10baseT_Half |
1269 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1270 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
1271 ADVERTISED_Autoneg | ADVERTISED_MII;
1272 cmd->base.port = PORT_MII;
1273 }
1274 if (np->link_status) {
1275 cmd->base.speed = np->speed;
1276 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1277 } else {
1278 cmd->base.speed = SPEED_UNKNOWN;
1279 cmd->base.duplex = DUPLEX_UNKNOWN;
1280 }
1281 if (np->an_enable)
1282 cmd->base.autoneg = AUTONEG_ENABLE;
1283 else
1284 cmd->base.autoneg = AUTONEG_DISABLE;
1285
1286 cmd->base.phy_address = np->phy_addr;
1287
1288 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1289 supported);
1290 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1291 advertising);
1292
1293 return 0;
1294 }
1295
rio_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)1296 static int rio_set_link_ksettings(struct net_device *dev,
1297 const struct ethtool_link_ksettings *cmd)
1298 {
1299 struct netdev_private *np = netdev_priv(dev);
1300 u32 speed = cmd->base.speed;
1301 u8 duplex = cmd->base.duplex;
1302
1303 netif_carrier_off(dev);
1304 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1305 if (np->an_enable) {
1306 return 0;
1307 } else {
1308 np->an_enable = 1;
1309 mii_set_media(dev);
1310 return 0;
1311 }
1312 } else {
1313 np->an_enable = 0;
1314 if (np->speed == 1000) {
1315 speed = SPEED_100;
1316 duplex = DUPLEX_FULL;
1317 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1318 }
1319 switch (speed) {
1320 case SPEED_10:
1321 np->speed = 10;
1322 np->full_duplex = (duplex == DUPLEX_FULL);
1323 break;
1324 case SPEED_100:
1325 np->speed = 100;
1326 np->full_duplex = (duplex == DUPLEX_FULL);
1327 break;
1328 case SPEED_1000: /* not supported */
1329 default:
1330 return -EINVAL;
1331 }
1332 mii_set_media(dev);
1333 }
1334 return 0;
1335 }
1336
rio_get_link(struct net_device * dev)1337 static u32 rio_get_link(struct net_device *dev)
1338 {
1339 struct netdev_private *np = netdev_priv(dev);
1340 return np->link_status;
1341 }
1342
1343 static const struct ethtool_ops ethtool_ops = {
1344 .get_drvinfo = rio_get_drvinfo,
1345 .get_link = rio_get_link,
1346 .get_link_ksettings = rio_get_link_ksettings,
1347 .set_link_ksettings = rio_set_link_ksettings,
1348 };
1349
1350 static int
rio_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)1351 rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1352 {
1353 int phy_addr;
1354 struct netdev_private *np = netdev_priv(dev);
1355 struct mii_ioctl_data *miidata = if_mii(rq);
1356
1357 phy_addr = np->phy_addr;
1358 switch (cmd) {
1359 case SIOCGMIIPHY:
1360 miidata->phy_id = phy_addr;
1361 break;
1362 case SIOCGMIIREG:
1363 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
1364 break;
1365 case SIOCSMIIREG:
1366 if (!capable(CAP_NET_ADMIN))
1367 return -EPERM;
1368 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
1369 break;
1370 default:
1371 return -EOPNOTSUPP;
1372 }
1373 return 0;
1374 }
1375
1376 #define EEP_READ 0x0200
1377 #define EEP_BUSY 0x8000
1378 /* Read the EEPROM word */
1379 /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
read_eeprom(struct netdev_private * np,int eep_addr)1380 static int read_eeprom(struct netdev_private *np, int eep_addr)
1381 {
1382 void __iomem *ioaddr = np->eeprom_addr;
1383 int i = 1000;
1384
1385 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
1386 while (i-- > 0) {
1387 if (!(dr16(EepromCtrl) & EEP_BUSY))
1388 return dr16(EepromData);
1389 }
1390 return 0;
1391 }
1392
1393 enum phy_ctrl_bits {
1394 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1395 MII_DUPLEX = 0x08,
1396 };
1397
1398 #define mii_delay() dr8(PhyCtrl)
1399 static void
mii_sendbit(struct net_device * dev,u32 data)1400 mii_sendbit (struct net_device *dev, u32 data)
1401 {
1402 struct netdev_private *np = netdev_priv(dev);
1403 void __iomem *ioaddr = np->ioaddr;
1404
1405 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
1406 dw8(PhyCtrl, data);
1407 mii_delay ();
1408 dw8(PhyCtrl, data | MII_CLK);
1409 mii_delay ();
1410 }
1411
1412 static int
mii_getbit(struct net_device * dev)1413 mii_getbit (struct net_device *dev)
1414 {
1415 struct netdev_private *np = netdev_priv(dev);
1416 void __iomem *ioaddr = np->ioaddr;
1417 u8 data;
1418
1419 data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
1420 dw8(PhyCtrl, data);
1421 mii_delay ();
1422 dw8(PhyCtrl, data | MII_CLK);
1423 mii_delay ();
1424 return (dr8(PhyCtrl) >> 1) & 1;
1425 }
1426
1427 static void
mii_send_bits(struct net_device * dev,u32 data,int len)1428 mii_send_bits (struct net_device *dev, u32 data, int len)
1429 {
1430 int i;
1431
1432 for (i = len - 1; i >= 0; i--) {
1433 mii_sendbit (dev, data & (1 << i));
1434 }
1435 }
1436
1437 static int
mii_read(struct net_device * dev,int phy_addr,int reg_num)1438 mii_read (struct net_device *dev, int phy_addr, int reg_num)
1439 {
1440 u32 cmd;
1441 int i;
1442 u32 retval = 0;
1443
1444 /* Preamble */
1445 mii_send_bits (dev, 0xffffffff, 32);
1446 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1447 /* ST,OP = 0110'b for read operation */
1448 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1449 mii_send_bits (dev, cmd, 14);
1450 /* Turnaround */
1451 if (mii_getbit (dev))
1452 goto err_out;
1453 /* Read data */
1454 for (i = 0; i < 16; i++) {
1455 retval |= mii_getbit (dev);
1456 retval <<= 1;
1457 }
1458 /* End cycle */
1459 mii_getbit (dev);
1460 return (retval >> 1) & 0xffff;
1461
1462 err_out:
1463 return 0;
1464 }
1465 static int
mii_write(struct net_device * dev,int phy_addr,int reg_num,u16 data)1466 mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1467 {
1468 u32 cmd;
1469
1470 /* Preamble */
1471 mii_send_bits (dev, 0xffffffff, 32);
1472 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1473 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1474 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1475 mii_send_bits (dev, cmd, 32);
1476 /* End cycle */
1477 mii_getbit (dev);
1478 return 0;
1479 }
1480 static int
mii_wait_link(struct net_device * dev,int wait)1481 mii_wait_link (struct net_device *dev, int wait)
1482 {
1483 __u16 bmsr;
1484 int phy_addr;
1485 struct netdev_private *np;
1486
1487 np = netdev_priv(dev);
1488 phy_addr = np->phy_addr;
1489
1490 do {
1491 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1492 if (bmsr & BMSR_LSTATUS)
1493 return 0;
1494 mdelay (1);
1495 } while (--wait > 0);
1496 return -1;
1497 }
1498 static int
mii_get_media(struct net_device * dev)1499 mii_get_media (struct net_device *dev)
1500 {
1501 __u16 negotiate;
1502 __u16 bmsr;
1503 __u16 mscr;
1504 __u16 mssr;
1505 int phy_addr;
1506 struct netdev_private *np;
1507
1508 np = netdev_priv(dev);
1509 phy_addr = np->phy_addr;
1510
1511 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1512 if (np->an_enable) {
1513 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1514 /* Auto-Negotiation not completed */
1515 return -1;
1516 }
1517 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1518 mii_read (dev, phy_addr, MII_LPA);
1519 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1520 mssr = mii_read (dev, phy_addr, MII_STAT1000);
1521 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
1522 np->speed = 1000;
1523 np->full_duplex = 1;
1524 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1525 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
1526 np->speed = 1000;
1527 np->full_duplex = 0;
1528 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1529 } else if (negotiate & ADVERTISE_100FULL) {
1530 np->speed = 100;
1531 np->full_duplex = 1;
1532 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1533 } else if (negotiate & ADVERTISE_100HALF) {
1534 np->speed = 100;
1535 np->full_duplex = 0;
1536 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1537 } else if (negotiate & ADVERTISE_10FULL) {
1538 np->speed = 10;
1539 np->full_duplex = 1;
1540 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1541 } else if (negotiate & ADVERTISE_10HALF) {
1542 np->speed = 10;
1543 np->full_duplex = 0;
1544 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1545 }
1546 if (negotiate & ADVERTISE_PAUSE_CAP) {
1547 np->tx_flow &= 1;
1548 np->rx_flow &= 1;
1549 } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
1550 np->tx_flow = 0;
1551 np->rx_flow &= 1;
1552 }
1553 /* else tx_flow, rx_flow = user select */
1554 } else {
1555 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1556 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1557 case BMCR_SPEED1000:
1558 printk (KERN_INFO "Operating at 1000 Mbps, ");
1559 break;
1560 case BMCR_SPEED100:
1561 printk (KERN_INFO "Operating at 100 Mbps, ");
1562 break;
1563 case 0:
1564 printk (KERN_INFO "Operating at 10 Mbps, ");
1565 }
1566 if (bmcr & BMCR_FULLDPLX) {
1567 printk (KERN_CONT "Full duplex\n");
1568 } else {
1569 printk (KERN_CONT "Half duplex\n");
1570 }
1571 }
1572 if (np->tx_flow)
1573 printk(KERN_INFO "Enable Tx Flow Control\n");
1574 else
1575 printk(KERN_INFO "Disable Tx Flow Control\n");
1576 if (np->rx_flow)
1577 printk(KERN_INFO "Enable Rx Flow Control\n");
1578 else
1579 printk(KERN_INFO "Disable Rx Flow Control\n");
1580
1581 return 0;
1582 }
1583
1584 static int
mii_set_media(struct net_device * dev)1585 mii_set_media (struct net_device *dev)
1586 {
1587 __u16 pscr;
1588 __u16 bmcr;
1589 __u16 bmsr;
1590 __u16 anar;
1591 int phy_addr;
1592 struct netdev_private *np;
1593 np = netdev_priv(dev);
1594 phy_addr = np->phy_addr;
1595
1596 /* Does user set speed? */
1597 if (np->an_enable) {
1598 /* Advertise capabilities */
1599 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1600 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1601 ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1602 ADVERTISE_100HALF | ADVERTISE_10HALF |
1603 ADVERTISE_100BASE4);
1604 if (bmsr & BMSR_100FULL)
1605 anar |= ADVERTISE_100FULL;
1606 if (bmsr & BMSR_100HALF)
1607 anar |= ADVERTISE_100HALF;
1608 if (bmsr & BMSR_100BASE4)
1609 anar |= ADVERTISE_100BASE4;
1610 if (bmsr & BMSR_10FULL)
1611 anar |= ADVERTISE_10FULL;
1612 if (bmsr & BMSR_10HALF)
1613 anar |= ADVERTISE_10HALF;
1614 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1615 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1616
1617 /* Enable Auto crossover */
1618 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1619 pscr |= 3 << 5; /* 11'b */
1620 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1621
1622 /* Soft reset PHY */
1623 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1624 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1625 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1626 mdelay(1);
1627 } else {
1628 /* Force speed setting */
1629 /* 1) Disable Auto crossover */
1630 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1631 pscr &= ~(3 << 5);
1632 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1633
1634 /* 2) PHY Reset */
1635 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1636 bmcr |= BMCR_RESET;
1637 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1638
1639 /* 3) Power Down */
1640 bmcr = 0x1940; /* must be 0x1940 */
1641 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1642 mdelay (100); /* wait a certain time */
1643
1644 /* 4) Advertise nothing */
1645 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1646
1647 /* 5) Set media and Power Up */
1648 bmcr = BMCR_PDOWN;
1649 if (np->speed == 100) {
1650 bmcr |= BMCR_SPEED100;
1651 printk (KERN_INFO "Manual 100 Mbps, ");
1652 } else if (np->speed == 10) {
1653 printk (KERN_INFO "Manual 10 Mbps, ");
1654 }
1655 if (np->full_duplex) {
1656 bmcr |= BMCR_FULLDPLX;
1657 printk (KERN_CONT "Full duplex\n");
1658 } else {
1659 printk (KERN_CONT "Half duplex\n");
1660 }
1661 #if 0
1662 /* Set 1000BaseT Master/Slave setting */
1663 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1664 mscr |= MII_MSCR_CFG_ENABLE;
1665 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1666 #endif
1667 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1668 mdelay(10);
1669 }
1670 return 0;
1671 }
1672
1673 static int
mii_get_media_pcs(struct net_device * dev)1674 mii_get_media_pcs (struct net_device *dev)
1675 {
1676 __u16 negotiate;
1677 __u16 bmsr;
1678 int phy_addr;
1679 struct netdev_private *np;
1680
1681 np = netdev_priv(dev);
1682 phy_addr = np->phy_addr;
1683
1684 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1685 if (np->an_enable) {
1686 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1687 /* Auto-Negotiation not completed */
1688 return -1;
1689 }
1690 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1691 mii_read (dev, phy_addr, PCS_ANLPAR);
1692 np->speed = 1000;
1693 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1694 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1695 np->full_duplex = 1;
1696 } else {
1697 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1698 np->full_duplex = 0;
1699 }
1700 if (negotiate & PCS_ANAR_PAUSE) {
1701 np->tx_flow &= 1;
1702 np->rx_flow &= 1;
1703 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1704 np->tx_flow = 0;
1705 np->rx_flow &= 1;
1706 }
1707 /* else tx_flow, rx_flow = user select */
1708 } else {
1709 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1710 printk (KERN_INFO "Operating at 1000 Mbps, ");
1711 if (bmcr & BMCR_FULLDPLX) {
1712 printk (KERN_CONT "Full duplex\n");
1713 } else {
1714 printk (KERN_CONT "Half duplex\n");
1715 }
1716 }
1717 if (np->tx_flow)
1718 printk(KERN_INFO "Enable Tx Flow Control\n");
1719 else
1720 printk(KERN_INFO "Disable Tx Flow Control\n");
1721 if (np->rx_flow)
1722 printk(KERN_INFO "Enable Rx Flow Control\n");
1723 else
1724 printk(KERN_INFO "Disable Rx Flow Control\n");
1725
1726 return 0;
1727 }
1728
1729 static int
mii_set_media_pcs(struct net_device * dev)1730 mii_set_media_pcs (struct net_device *dev)
1731 {
1732 __u16 bmcr;
1733 __u16 esr;
1734 __u16 anar;
1735 int phy_addr;
1736 struct netdev_private *np;
1737 np = netdev_priv(dev);
1738 phy_addr = np->phy_addr;
1739
1740 /* Auto-Negotiation? */
1741 if (np->an_enable) {
1742 /* Advertise capabilities */
1743 esr = mii_read (dev, phy_addr, PCS_ESR);
1744 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1745 ~PCS_ANAR_HALF_DUPLEX &
1746 ~PCS_ANAR_FULL_DUPLEX;
1747 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1748 anar |= PCS_ANAR_HALF_DUPLEX;
1749 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1750 anar |= PCS_ANAR_FULL_DUPLEX;
1751 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1752 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1753
1754 /* Soft reset PHY */
1755 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1756 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1757 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1758 mdelay(1);
1759 } else {
1760 /* Force speed setting */
1761 /* PHY Reset */
1762 bmcr = BMCR_RESET;
1763 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1764 mdelay(10);
1765 if (np->full_duplex) {
1766 bmcr = BMCR_FULLDPLX;
1767 printk (KERN_INFO "Manual full duplex\n");
1768 } else {
1769 bmcr = 0;
1770 printk (KERN_INFO "Manual half duplex\n");
1771 }
1772 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1773 mdelay(10);
1774
1775 /* Advertise nothing */
1776 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1777 }
1778 return 0;
1779 }
1780
1781
1782 static int
rio_close(struct net_device * dev)1783 rio_close (struct net_device *dev)
1784 {
1785 struct netdev_private *np = netdev_priv(dev);
1786 struct pci_dev *pdev = np->pdev;
1787
1788 netif_stop_queue (dev);
1789
1790 rio_hw_stop(dev);
1791
1792 free_irq(pdev->irq, dev);
1793 timer_delete_sync(&np->timer);
1794
1795 free_list(dev);
1796
1797 return 0;
1798 }
1799
1800 static void
rio_remove1(struct pci_dev * pdev)1801 rio_remove1 (struct pci_dev *pdev)
1802 {
1803 struct net_device *dev = pci_get_drvdata (pdev);
1804
1805 if (dev) {
1806 struct netdev_private *np = netdev_priv(dev);
1807
1808 unregister_netdev (dev);
1809 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE, np->rx_ring,
1810 np->rx_ring_dma);
1811 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE, np->tx_ring,
1812 np->tx_ring_dma);
1813 #ifdef MEM_MAPPING
1814 pci_iounmap(pdev, np->ioaddr);
1815 #endif
1816 pci_iounmap(pdev, np->eeprom_addr);
1817 free_netdev (dev);
1818 pci_release_regions (pdev);
1819 pci_disable_device (pdev);
1820 }
1821 }
1822
1823 #ifdef CONFIG_PM_SLEEP
rio_suspend(struct device * device)1824 static int rio_suspend(struct device *device)
1825 {
1826 struct net_device *dev = dev_get_drvdata(device);
1827 struct netdev_private *np = netdev_priv(dev);
1828
1829 if (!netif_running(dev))
1830 return 0;
1831
1832 netif_device_detach(dev);
1833 timer_delete_sync(&np->timer);
1834 rio_hw_stop(dev);
1835
1836 return 0;
1837 }
1838
rio_resume(struct device * device)1839 static int rio_resume(struct device *device)
1840 {
1841 struct net_device *dev = dev_get_drvdata(device);
1842 struct netdev_private *np = netdev_priv(dev);
1843
1844 if (!netif_running(dev))
1845 return 0;
1846
1847 rio_reset_ring(np);
1848 rio_hw_init(dev);
1849 np->timer.expires = jiffies + 1 * HZ;
1850 add_timer(&np->timer);
1851 netif_device_attach(dev);
1852 dl2k_enable_int(np);
1853
1854 return 0;
1855 }
1856
1857 static DEFINE_SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
1858 #define RIO_PM_OPS (&rio_pm_ops)
1859
1860 #else
1861
1862 #define RIO_PM_OPS NULL
1863
1864 #endif /* CONFIG_PM_SLEEP */
1865
1866 static struct pci_driver rio_driver = {
1867 .name = "dl2k",
1868 .id_table = rio_pci_tbl,
1869 .probe = rio_probe1,
1870 .remove = rio_remove1,
1871 .driver.pm = RIO_PM_OPS,
1872 };
1873
1874 module_pci_driver(rio_driver);
1875
1876 /* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */
1877