1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * APDS-9306/APDS-9306-065 Ambient Light Sensor
4 * I2C Address: 0x52
5 * Datasheet: https://docs.broadcom.com/doc/AV02-4755EN
6 *
7 * Copyright (C) 2024 Subhajit Ghosh <subhajit.ghosh@tweaklogic.com>
8 */
9
10 #include <linux/bits.h>
11 #include <linux/cleanup.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
16 #include <linux/minmax.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/types.h>
24 #include <linux/units.h>
25
26 #include <linux/iio/iio.h>
27 #include <linux/iio/iio-gts-helper.h>
28 #include <linux/iio/events.h>
29 #include <linux/iio/sysfs.h>
30
31 #include <linux/unaligned.h>
32
33 #define APDS9306_MAIN_CTRL_REG 0x00
34 #define APDS9306_ALS_MEAS_RATE_REG 0x04
35 #define APDS9306_ALS_GAIN_REG 0x05
36 #define APDS9306_PART_ID_REG 0x06
37 #define APDS9306_MAIN_STATUS_REG 0x07
38 #define APDS9306_CLEAR_DATA_0_REG 0x0A
39 #define APDS9306_CLEAR_DATA_1_REG 0x0B
40 #define APDS9306_CLEAR_DATA_2_REG 0x0C
41 #define APDS9306_ALS_DATA_0_REG 0x0D
42 #define APDS9306_ALS_DATA_1_REG 0x0E
43 #define APDS9306_ALS_DATA_2_REG 0x0F
44 #define APDS9306_INT_CFG_REG 0x19
45 #define APDS9306_INT_PERSISTENCE_REG 0x1A
46 #define APDS9306_ALS_THRES_UP_0_REG 0x21
47 #define APDS9306_ALS_THRES_UP_1_REG 0x22
48 #define APDS9306_ALS_THRES_UP_2_REG 0x23
49 #define APDS9306_ALS_THRES_LOW_0_REG 0x24
50 #define APDS9306_ALS_THRES_LOW_1_REG 0x25
51 #define APDS9306_ALS_THRES_LOW_2_REG 0x26
52 #define APDS9306_ALS_THRES_VAR_REG 0x27
53
54 #define APDS9306_ALS_INT_STAT_MASK BIT(4)
55 #define APDS9306_ALS_DATA_STAT_MASK BIT(3)
56
57 #define APDS9306_ALS_THRES_VAL_MAX (BIT(20) - 1)
58 #define APDS9306_ALS_THRES_VAR_NUM_VALS 8
59 #define APDS9306_ALS_PERSIST_NUM_VALS 16
60 #define APDS9306_ALS_READ_DATA_DELAY_US (20 * USEC_PER_MSEC)
61 #define APDS9306_NUM_REPEAT_RATES 7
62 #define APDS9306_INT_SRC_CLEAR 0
63 #define APDS9306_INT_SRC_ALS 1
64 #define APDS9306_SAMP_FREQ_10HZ 0
65
66 /**
67 * struct part_id_gts_multiplier - Part no. and corresponding gts multiplier
68 *
69 * GTS (Gain Time Scale) are helper functions for Light sensors which along
70 * with hardware gains also has gains associated with Integration times.
71 *
72 * There are two variants of the device with slightly different characteristics,
73 * they have same ADC count for different Lux levels as mentioned in the
74 * datasheet. This multiplier array is used to store the derived Lux per count
75 * value for the two variants to be used by the GTS helper functions.
76 *
77 * @part_id: Part ID of the device
78 * @max_scale_int: Multiplier for iio_init_iio_gts()
79 * @max_scale_nano: Multiplier for iio_init_iio_gts()
80 */
81 struct part_id_gts_multiplier {
82 int part_id;
83 int max_scale_int;
84 int max_scale_nano;
85 };
86
87 /*
88 * As per the datasheet, at HW Gain = 3x, Integration time 100mS (32x),
89 * typical 2000 ADC counts are observed for 49.8 uW per sq cm (340.134 lux)
90 * for apds9306 and 43 uW per sq cm (293.69 lux) for apds9306-065.
91 * Assuming lux per count is linear across all integration time ranges.
92 *
93 * Lux = (raw + offset) * scale; offset can be any value by userspace.
94 * HG = Hardware Gain; ITG = Gain by changing integration time.
95 * Scale table by IIO GTS Helpers = (1 / HG) * (1 / ITG) * Multiplier.
96 *
97 * The Lux values provided in the datasheet are at ITG=32x and HG=3x,
98 * at typical 2000 count for both variants of the device.
99 *
100 * Lux per ADC count at 3x and 32x for apds9306 = 340.134 / 2000
101 * Lux per ADC count at 3x and 32x for apds9306-065 = 293.69 / 2000
102 *
103 * The Multiplier for the scale table provided to userspace:
104 * IIO GTS scale Multiplier for apds9306 = (340.134 / 2000) * 32 * 3 = 16.326432
105 * and for apds9306-065 = (293.69 / 2000) * 32 * 3 = 14.09712
106 */
107 static const struct part_id_gts_multiplier apds9306_gts_mul[] = {
108 {
109 .part_id = 0xB1,
110 .max_scale_int = 16,
111 .max_scale_nano = 326432000,
112 }, {
113 .part_id = 0xB3,
114 .max_scale_int = 14,
115 .max_scale_nano = 97120000,
116 },
117 };
118
119 static const int apds9306_repeat_rate_freq[APDS9306_NUM_REPEAT_RATES][2] = {
120 { 40, 0 },
121 { 20, 0 },
122 { 10, 0 },
123 { 5, 0 },
124 { 2, 0 },
125 { 1, 0 },
126 { 0, 500000 },
127 };
128
129 static const int apds9306_repeat_rate_period[APDS9306_NUM_REPEAT_RATES] = {
130 25000, 50000, 100000, 200000, 500000, 1000000, 2000000,
131 };
132
133 /**
134 * struct apds9306_regfields - apds9306 regmap fields definitions
135 *
136 * @sw_reset: Software reset regfield
137 * @en: Enable regfield
138 * @intg_time: Resolution regfield
139 * @repeat_rate: Measurement Rate regfield
140 * @gain: Hardware gain regfield
141 * @int_src: Interrupt channel regfield
142 * @int_thresh_var_en: Interrupt variance threshold regfield
143 * @int_en: Interrupt enable regfield
144 * @int_persist_val: Interrupt persistence regfield
145 * @int_thresh_var_val: Interrupt threshold variance value regfield
146 */
147 struct apds9306_regfields {
148 struct regmap_field *sw_reset;
149 struct regmap_field *en;
150 struct regmap_field *intg_time;
151 struct regmap_field *repeat_rate;
152 struct regmap_field *gain;
153 struct regmap_field *int_src;
154 struct regmap_field *int_thresh_var_en;
155 struct regmap_field *int_en;
156 struct regmap_field *int_persist_val;
157 struct regmap_field *int_thresh_var_val;
158 };
159
160 /**
161 * struct apds9306_data - apds9306 private data and registers definitions
162 *
163 * @dev: Pointer to the device structure
164 * @gts: IIO Gain Time Scale structure
165 * @mutex: Lock for protecting adc reads, device settings changes where
166 * some calculations are required before or after setting or
167 * getting the raw settings values from regmap writes or reads
168 * respectively.
169 * @regmap: Regmap structure pointer
170 * @rf: Regmap register fields structure
171 * @read_data_available: Flag set by IRQ handler for ADC data available
172 */
173 struct apds9306_data {
174 struct device *dev;
175 struct iio_gts gts;
176
177 struct mutex mutex;
178
179 struct regmap *regmap;
180 struct apds9306_regfields rf;
181
182 int read_data_available;
183 };
184
185 /*
186 * Available scales with gain 1x - 18x, timings 3.125, 25, 50, 100, 200, 400 ms
187 * Time impacts to gain: 1x, 8x, 16x, 32x, 64x, 128x
188 */
189 #define APDS9306_GSEL_1X 0x00
190 #define APDS9306_GSEL_3X 0x01
191 #define APDS9306_GSEL_6X 0x02
192 #define APDS9306_GSEL_9X 0x03
193 #define APDS9306_GSEL_18X 0x04
194
195 static const struct iio_gain_sel_pair apds9306_gains[] = {
196 GAIN_SCALE_GAIN(1, APDS9306_GSEL_1X),
197 GAIN_SCALE_GAIN(3, APDS9306_GSEL_3X),
198 GAIN_SCALE_GAIN(6, APDS9306_GSEL_6X),
199 GAIN_SCALE_GAIN(9, APDS9306_GSEL_9X),
200 GAIN_SCALE_GAIN(18, APDS9306_GSEL_18X),
201 };
202
203 #define APDS9306_MEAS_MODE_400MS 0x00
204 #define APDS9306_MEAS_MODE_200MS 0x01
205 #define APDS9306_MEAS_MODE_100MS 0x02
206 #define APDS9306_MEAS_MODE_50MS 0x03
207 #define APDS9306_MEAS_MODE_25MS 0x04
208 #define APDS9306_MEAS_MODE_3125US 0x05
209
210 static const struct iio_itime_sel_mul apds9306_itimes[] = {
211 GAIN_SCALE_ITIME_US(400000, APDS9306_MEAS_MODE_400MS, BIT(7)),
212 GAIN_SCALE_ITIME_US(200000, APDS9306_MEAS_MODE_200MS, BIT(6)),
213 GAIN_SCALE_ITIME_US(100000, APDS9306_MEAS_MODE_100MS, BIT(5)),
214 GAIN_SCALE_ITIME_US(50000, APDS9306_MEAS_MODE_50MS, BIT(4)),
215 GAIN_SCALE_ITIME_US(25000, APDS9306_MEAS_MODE_25MS, BIT(3)),
216 GAIN_SCALE_ITIME_US(3125, APDS9306_MEAS_MODE_3125US, BIT(0)),
217 };
218
219 static const struct iio_event_spec apds9306_event_spec[] = {
220 {
221 .type = IIO_EV_TYPE_THRESH,
222 .dir = IIO_EV_DIR_RISING,
223 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE),
224 }, {
225 .type = IIO_EV_TYPE_THRESH,
226 .dir = IIO_EV_DIR_FALLING,
227 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE),
228 }, {
229 .type = IIO_EV_TYPE_THRESH,
230 .dir = IIO_EV_DIR_EITHER,
231 .mask_shared_by_all = BIT(IIO_EV_INFO_PERIOD),
232 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
233 }, {
234 .type = IIO_EV_TYPE_THRESH_ADAPTIVE,
235 .mask_shared_by_all = BIT(IIO_EV_INFO_VALUE) |
236 BIT(IIO_EV_INFO_ENABLE),
237 },
238 };
239
240 static const struct iio_chan_spec apds9306_channels_with_events[] = {
241 {
242 .type = IIO_LIGHT,
243 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) |
244 BIT(IIO_CHAN_INFO_SAMP_FREQ),
245 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME) |
246 BIT(IIO_CHAN_INFO_SAMP_FREQ),
247 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
248 BIT(IIO_CHAN_INFO_SCALE),
249 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
250 .event_spec = apds9306_event_spec,
251 .num_event_specs = ARRAY_SIZE(apds9306_event_spec),
252 }, {
253 .type = IIO_INTENSITY,
254 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) |
255 BIT(IIO_CHAN_INFO_SAMP_FREQ),
256 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME) |
257 BIT(IIO_CHAN_INFO_SAMP_FREQ),
258 .channel2 = IIO_MOD_LIGHT_CLEAR,
259 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
260 .modified = 1,
261 .event_spec = apds9306_event_spec,
262 .num_event_specs = ARRAY_SIZE(apds9306_event_spec),
263 },
264 };
265
266 static const struct iio_chan_spec apds9306_channels_without_events[] = {
267 {
268 .type = IIO_LIGHT,
269 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) |
270 BIT(IIO_CHAN_INFO_SAMP_FREQ),
271 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME) |
272 BIT(IIO_CHAN_INFO_SAMP_FREQ),
273 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
274 BIT(IIO_CHAN_INFO_SCALE),
275 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
276 }, {
277 .type = IIO_INTENSITY,
278 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_INT_TIME) |
279 BIT(IIO_CHAN_INFO_SAMP_FREQ),
280 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_INT_TIME) |
281 BIT(IIO_CHAN_INFO_SAMP_FREQ),
282 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
283 .modified = 1,
284 .channel2 = IIO_MOD_LIGHT_CLEAR,
285 },
286 };
287
288 /* INT_PERSISTENCE available */
289 static IIO_CONST_ATTR(thresh_either_period_available, "[0 1 15]");
290
291 /* ALS_THRESH_VAR available */
292 static IIO_CONST_ATTR(thresh_adaptive_either_values_available, "[0 1 7]");
293
294 static struct attribute *apds9306_event_attributes[] = {
295 &iio_const_attr_thresh_either_period_available.dev_attr.attr,
296 &iio_const_attr_thresh_adaptive_either_values_available.dev_attr.attr,
297 NULL
298 };
299
300 static const struct attribute_group apds9306_event_attr_group = {
301 .attrs = apds9306_event_attributes,
302 };
303
304 static const struct regmap_range apds9306_readable_ranges[] = {
305 regmap_reg_range(APDS9306_MAIN_CTRL_REG, APDS9306_ALS_THRES_VAR_REG)
306 };
307
308 static const struct regmap_range apds9306_writable_ranges[] = {
309 regmap_reg_range(APDS9306_MAIN_CTRL_REG, APDS9306_ALS_GAIN_REG),
310 regmap_reg_range(APDS9306_INT_CFG_REG, APDS9306_ALS_THRES_VAR_REG)
311 };
312
313 static const struct regmap_range apds9306_volatile_ranges[] = {
314 regmap_reg_range(APDS9306_MAIN_STATUS_REG, APDS9306_MAIN_STATUS_REG),
315 regmap_reg_range(APDS9306_CLEAR_DATA_0_REG, APDS9306_ALS_DATA_2_REG)
316 };
317
318 static const struct regmap_range apds9306_precious_ranges[] = {
319 regmap_reg_range(APDS9306_MAIN_STATUS_REG, APDS9306_MAIN_STATUS_REG)
320 };
321
322 static const struct regmap_access_table apds9306_readable_table = {
323 .yes_ranges = apds9306_readable_ranges,
324 .n_yes_ranges = ARRAY_SIZE(apds9306_readable_ranges)
325 };
326
327 static const struct regmap_access_table apds9306_writable_table = {
328 .yes_ranges = apds9306_writable_ranges,
329 .n_yes_ranges = ARRAY_SIZE(apds9306_writable_ranges)
330 };
331
332 static const struct regmap_access_table apds9306_volatile_table = {
333 .yes_ranges = apds9306_volatile_ranges,
334 .n_yes_ranges = ARRAY_SIZE(apds9306_volatile_ranges)
335 };
336
337 static const struct regmap_access_table apds9306_precious_table = {
338 .yes_ranges = apds9306_precious_ranges,
339 .n_yes_ranges = ARRAY_SIZE(apds9306_precious_ranges)
340 };
341
342 static const struct regmap_config apds9306_regmap = {
343 .name = "apds9306_regmap",
344 .reg_bits = 8,
345 .val_bits = 8,
346 .rd_table = &apds9306_readable_table,
347 .wr_table = &apds9306_writable_table,
348 .volatile_table = &apds9306_volatile_table,
349 .precious_table = &apds9306_precious_table,
350 .max_register = APDS9306_ALS_THRES_VAR_REG,
351 .cache_type = REGCACHE_MAPLE,
352 };
353
354 static const struct reg_field apds9306_rf_sw_reset =
355 REG_FIELD(APDS9306_MAIN_CTRL_REG, 4, 4);
356
357 static const struct reg_field apds9306_rf_en =
358 REG_FIELD(APDS9306_MAIN_CTRL_REG, 1, 1);
359
360 static const struct reg_field apds9306_rf_intg_time =
361 REG_FIELD(APDS9306_ALS_MEAS_RATE_REG, 4, 6);
362
363 static const struct reg_field apds9306_rf_repeat_rate =
364 REG_FIELD(APDS9306_ALS_MEAS_RATE_REG, 0, 2);
365
366 static const struct reg_field apds9306_rf_gain =
367 REG_FIELD(APDS9306_ALS_GAIN_REG, 0, 2);
368
369 static const struct reg_field apds9306_rf_int_src =
370 REG_FIELD(APDS9306_INT_CFG_REG, 4, 5);
371
372 static const struct reg_field apds9306_rf_int_thresh_var_en =
373 REG_FIELD(APDS9306_INT_CFG_REG, 3, 3);
374
375 static const struct reg_field apds9306_rf_int_en =
376 REG_FIELD(APDS9306_INT_CFG_REG, 2, 2);
377
378 static const struct reg_field apds9306_rf_int_persist_val =
379 REG_FIELD(APDS9306_INT_PERSISTENCE_REG, 4, 7);
380
381 static const struct reg_field apds9306_rf_int_thresh_var_val =
382 REG_FIELD(APDS9306_ALS_THRES_VAR_REG, 0, 2);
383
apds9306_regfield_init(struct apds9306_data * data)384 static int apds9306_regfield_init(struct apds9306_data *data)
385 {
386 struct device *dev = data->dev;
387 struct regmap *regmap = data->regmap;
388 struct regmap_field *tmp;
389 struct apds9306_regfields *rf = &data->rf;
390
391 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_sw_reset);
392 if (IS_ERR(tmp))
393 return PTR_ERR(tmp);
394 rf->sw_reset = tmp;
395
396 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_en);
397 if (IS_ERR(tmp))
398 return PTR_ERR(tmp);
399 rf->en = tmp;
400
401 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_intg_time);
402 if (IS_ERR(tmp))
403 return PTR_ERR(tmp);
404 rf->intg_time = tmp;
405
406 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_repeat_rate);
407 if (IS_ERR(tmp))
408 return PTR_ERR(tmp);
409 rf->repeat_rate = tmp;
410
411 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_gain);
412 if (IS_ERR(tmp))
413 return PTR_ERR(tmp);
414 rf->gain = tmp;
415
416 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_int_src);
417 if (IS_ERR(tmp))
418 return PTR_ERR(tmp);
419 rf->int_src = tmp;
420
421 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_int_thresh_var_en);
422 if (IS_ERR(tmp))
423 return PTR_ERR(tmp);
424 rf->int_thresh_var_en = tmp;
425
426 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_int_en);
427 if (IS_ERR(tmp))
428 return PTR_ERR(tmp);
429 rf->int_en = tmp;
430
431 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_int_persist_val);
432 if (IS_ERR(tmp))
433 return PTR_ERR(tmp);
434 rf->int_persist_val = tmp;
435
436 tmp = devm_regmap_field_alloc(dev, regmap, apds9306_rf_int_thresh_var_val);
437 if (IS_ERR(tmp))
438 return PTR_ERR(tmp);
439 rf->int_thresh_var_val = tmp;
440
441 return 0;
442 }
443
apds9306_power_state(struct apds9306_data * data,bool state)444 static int apds9306_power_state(struct apds9306_data *data, bool state)
445 {
446 struct apds9306_regfields *rf = &data->rf;
447 int ret;
448
449 /* Reset not included as it causes ugly I2C bus error */
450 if (state) {
451 ret = regmap_field_write(rf->en, 1);
452 if (ret)
453 return ret;
454 /* 5ms wake up time */
455 fsleep(5000);
456 return 0;
457 }
458
459 return regmap_field_write(rf->en, 0);
460 }
461
apds9306_read_data(struct apds9306_data * data,int * val,int reg)462 static int apds9306_read_data(struct apds9306_data *data, int *val, int reg)
463 {
464 struct device *dev = data->dev;
465 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
466 struct apds9306_regfields *rf = &data->rf;
467 u64 ev_code;
468 int ret, delay, intg_time, intg_time_idx, repeat_rate_idx, int_src;
469 int status = 0;
470 u8 buff[3];
471
472 ret = pm_runtime_resume_and_get(data->dev);
473 if (ret)
474 return ret;
475
476 ret = regmap_field_read(rf->intg_time, &intg_time_idx);
477 if (ret)
478 return ret;
479
480 ret = regmap_field_read(rf->repeat_rate, &repeat_rate_idx);
481 if (ret)
482 return ret;
483
484 ret = regmap_field_read(rf->int_src, &int_src);
485 if (ret)
486 return ret;
487
488 intg_time = iio_gts_find_int_time_by_sel(&data->gts, intg_time_idx);
489 if (intg_time < 0)
490 return intg_time;
491
492 /* Whichever is greater - integration time period or sampling period. */
493 delay = max(intg_time, apds9306_repeat_rate_period[repeat_rate_idx]);
494
495 /*
496 * Clear stale data flag that might have been set by the interrupt
497 * handler if it got data available flag set in the status reg.
498 */
499 data->read_data_available = 0;
500
501 /*
502 * If this function runs parallel with the interrupt handler, either
503 * this reads and clears the status registers or the interrupt handler
504 * does. The interrupt handler sets a flag for read data available
505 * in our private structure which we read here.
506 */
507 ret = regmap_read_poll_timeout(data->regmap, APDS9306_MAIN_STATUS_REG,
508 status, data->read_data_available ||
509 (status & (APDS9306_ALS_DATA_STAT_MASK |
510 APDS9306_ALS_INT_STAT_MASK)),
511 APDS9306_ALS_READ_DATA_DELAY_US, delay * 2);
512 if (ret)
513 return ret;
514
515 /* If we reach here before the interrupt handler we push an event */
516 if ((status & APDS9306_ALS_INT_STAT_MASK)) {
517 if (int_src == APDS9306_INT_SRC_ALS)
518 ev_code = IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
519 IIO_EV_TYPE_THRESH,
520 IIO_EV_DIR_EITHER);
521 else
522 ev_code = IIO_MOD_EVENT_CODE(IIO_INTENSITY, 0,
523 IIO_MOD_LIGHT_CLEAR,
524 IIO_EV_TYPE_THRESH,
525 IIO_EV_DIR_EITHER);
526
527 iio_push_event(indio_dev, ev_code, iio_get_time_ns(indio_dev));
528 }
529
530 ret = regmap_bulk_read(data->regmap, reg, buff, sizeof(buff));
531 if (ret) {
532 dev_err_ratelimited(dev, "read data failed\n");
533 return ret;
534 }
535
536 *val = get_unaligned_le24(&buff);
537
538 pm_runtime_put_autosuspend(data->dev);
539
540 return 0;
541 }
542
apds9306_intg_time_get(struct apds9306_data * data,int * val2)543 static int apds9306_intg_time_get(struct apds9306_data *data, int *val2)
544 {
545 struct apds9306_regfields *rf = &data->rf;
546 int ret, intg_time_idx;
547
548 ret = regmap_field_read(rf->intg_time, &intg_time_idx);
549 if (ret)
550 return ret;
551
552 ret = iio_gts_find_int_time_by_sel(&data->gts, intg_time_idx);
553 if (ret < 0)
554 return ret;
555
556 *val2 = ret;
557
558 return 0;
559 }
560
apds9306_intg_time_set(struct apds9306_data * data,int val2)561 static int apds9306_intg_time_set(struct apds9306_data *data, int val2)
562 {
563 struct device *dev = data->dev;
564 struct apds9306_regfields *rf = &data->rf;
565 int ret, intg_old, gain_old, gain_new, gain_new_closest, intg_time_idx;
566 int gain_idx;
567 bool ok;
568
569 if (!iio_gts_valid_time(&data->gts, val2)) {
570 dev_err_ratelimited(dev, "Unsupported integration time %u\n", val2);
571 return -EINVAL;
572 }
573
574 ret = regmap_field_read(rf->intg_time, &intg_time_idx);
575 if (ret)
576 return ret;
577
578 ret = regmap_field_read(rf->gain, &gain_idx);
579 if (ret)
580 return ret;
581
582 intg_old = iio_gts_find_int_time_by_sel(&data->gts, intg_time_idx);
583 if (intg_old < 0)
584 return intg_old;
585
586 if (intg_old == val2)
587 return 0;
588
589 gain_old = iio_gts_find_gain_by_sel(&data->gts, gain_idx);
590 if (gain_old < 0)
591 return gain_old;
592
593 iio_gts_find_new_gain_by_old_gain_time(&data->gts, gain_old, intg_old,
594 val2, &gain_new);
595
596 if (gain_new < 0) {
597 dev_err_ratelimited(dev, "Unsupported gain with time\n");
598 return gain_new;
599 }
600
601 gain_new_closest = iio_find_closest_gain_low(&data->gts, gain_new, &ok);
602 if (gain_new_closest < 0) {
603 gain_new_closest = iio_gts_get_min_gain(&data->gts);
604 if (gain_new_closest < 0)
605 return gain_new_closest;
606 }
607 if (!ok)
608 dev_dbg(dev, "Unable to find optimum gain, setting minimum");
609
610 ret = iio_gts_find_sel_by_int_time(&data->gts, val2);
611 if (ret < 0)
612 return ret;
613
614 ret = regmap_field_write(rf->intg_time, ret);
615 if (ret)
616 return ret;
617
618 ret = iio_gts_find_sel_by_gain(&data->gts, gain_new_closest);
619 if (ret < 0)
620 return ret;
621
622 return regmap_field_write(rf->gain, ret);
623 }
624
apds9306_sampling_freq_get(struct apds9306_data * data,int * val,int * val2)625 static int apds9306_sampling_freq_get(struct apds9306_data *data, int *val,
626 int *val2)
627 {
628 struct apds9306_regfields *rf = &data->rf;
629 int ret, repeat_rate_idx;
630
631 ret = regmap_field_read(rf->repeat_rate, &repeat_rate_idx);
632 if (ret)
633 return ret;
634
635 if (repeat_rate_idx >= ARRAY_SIZE(apds9306_repeat_rate_freq))
636 return -EINVAL;
637
638 *val = apds9306_repeat_rate_freq[repeat_rate_idx][0];
639 *val2 = apds9306_repeat_rate_freq[repeat_rate_idx][1];
640
641 return 0;
642 }
643
apds9306_sampling_freq_set(struct apds9306_data * data,int val,int val2)644 static int apds9306_sampling_freq_set(struct apds9306_data *data, int val,
645 int val2)
646 {
647 struct apds9306_regfields *rf = &data->rf;
648 int i;
649
650 for (i = 0; i < ARRAY_SIZE(apds9306_repeat_rate_freq); i++) {
651 if (apds9306_repeat_rate_freq[i][0] == val &&
652 apds9306_repeat_rate_freq[i][1] == val2)
653 return regmap_field_write(rf->repeat_rate, i);
654 }
655
656 return -EINVAL;
657 }
658
apds9306_scale_get(struct apds9306_data * data,int * val,int * val2)659 static int apds9306_scale_get(struct apds9306_data *data, int *val, int *val2)
660 {
661 struct apds9306_regfields *rf = &data->rf;
662 int gain, intg, ret, intg_time_idx, gain_idx;
663
664 ret = regmap_field_read(rf->gain, &gain_idx);
665 if (ret)
666 return ret;
667
668 ret = regmap_field_read(rf->intg_time, &intg_time_idx);
669 if (ret)
670 return ret;
671
672 gain = iio_gts_find_gain_by_sel(&data->gts, gain_idx);
673 if (gain < 0)
674 return gain;
675
676 intg = iio_gts_find_int_time_by_sel(&data->gts, intg_time_idx);
677 if (intg < 0)
678 return intg;
679
680 return iio_gts_get_scale(&data->gts, gain, intg, val, val2);
681 }
682
apds9306_scale_set(struct apds9306_data * data,int val,int val2)683 static int apds9306_scale_set(struct apds9306_data *data, int val, int val2)
684 {
685 struct apds9306_regfields *rf = &data->rf;
686 int i, ret, time_sel, gain_sel, intg_time_idx;
687
688 ret = regmap_field_read(rf->intg_time, &intg_time_idx);
689 if (ret)
690 return ret;
691
692 ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts,
693 intg_time_idx, val, val2, &gain_sel);
694 if (ret) {
695 for (i = 0; i < data->gts.num_itime; i++) {
696 time_sel = data->gts.itime_table[i].sel;
697
698 if (time_sel == intg_time_idx)
699 continue;
700
701 ret = iio_gts_find_gain_sel_for_scale_using_time(&data->gts,
702 time_sel, val, val2, &gain_sel);
703 if (!ret)
704 break;
705 }
706 if (ret)
707 return -EINVAL;
708
709 ret = regmap_field_write(rf->intg_time, time_sel);
710 if (ret)
711 return ret;
712 }
713
714 return regmap_field_write(rf->gain, gain_sel);
715 }
716
apds9306_event_period_get(struct apds9306_data * data,int * val)717 static int apds9306_event_period_get(struct apds9306_data *data, int *val)
718 {
719 struct apds9306_regfields *rf = &data->rf;
720 int period, ret;
721
722 ret = regmap_field_read(rf->int_persist_val, &period);
723 if (ret)
724 return ret;
725
726 if (!in_range(period, 0, APDS9306_ALS_PERSIST_NUM_VALS))
727 return -EINVAL;
728
729 *val = period;
730
731 return ret;
732 }
733
apds9306_event_period_set(struct apds9306_data * data,int val)734 static int apds9306_event_period_set(struct apds9306_data *data, int val)
735 {
736 struct apds9306_regfields *rf = &data->rf;
737
738 if (!in_range(val, 0, APDS9306_ALS_PERSIST_NUM_VALS))
739 return -EINVAL;
740
741 return regmap_field_write(rf->int_persist_val, val);
742 }
743
apds9306_get_thresh_reg(int dir)744 static int apds9306_get_thresh_reg(int dir)
745 {
746 if (dir == IIO_EV_DIR_RISING)
747 return APDS9306_ALS_THRES_UP_0_REG;
748 else if (dir == IIO_EV_DIR_FALLING)
749 return APDS9306_ALS_THRES_LOW_0_REG;
750 else
751 return -EINVAL;
752 }
753
apds9306_event_thresh_get(struct apds9306_data * data,int dir,int * val)754 static int apds9306_event_thresh_get(struct apds9306_data *data, int dir,
755 int *val)
756 {
757 int reg, ret;
758 u8 buff[3];
759
760 reg = apds9306_get_thresh_reg(dir);
761 if (reg < 0)
762 return reg;
763
764 ret = regmap_bulk_read(data->regmap, reg, buff, sizeof(buff));
765 if (ret)
766 return ret;
767
768 *val = get_unaligned_le24(&buff);
769
770 return 0;
771 }
772
apds9306_event_thresh_set(struct apds9306_data * data,int dir,int val)773 static int apds9306_event_thresh_set(struct apds9306_data *data, int dir,
774 int val)
775 {
776 int reg;
777 u8 buff[3];
778
779 reg = apds9306_get_thresh_reg(dir);
780 if (reg < 0)
781 return reg;
782
783 if (!in_range(val, 0, APDS9306_ALS_THRES_VAL_MAX))
784 return -EINVAL;
785
786 put_unaligned_le24(val, buff);
787
788 return regmap_bulk_write(data->regmap, reg, buff, sizeof(buff));
789 }
790
apds9306_event_thresh_adaptive_get(struct apds9306_data * data,int * val)791 static int apds9306_event_thresh_adaptive_get(struct apds9306_data *data, int *val)
792 {
793 struct apds9306_regfields *rf = &data->rf;
794 int thr_adpt, ret;
795
796 ret = regmap_field_read(rf->int_thresh_var_val, &thr_adpt);
797 if (ret)
798 return ret;
799
800 if (!in_range(thr_adpt, 0, APDS9306_ALS_THRES_VAR_NUM_VALS))
801 return -EINVAL;
802
803 *val = thr_adpt;
804
805 return ret;
806 }
807
apds9306_event_thresh_adaptive_set(struct apds9306_data * data,int val)808 static int apds9306_event_thresh_adaptive_set(struct apds9306_data *data, int val)
809 {
810 struct apds9306_regfields *rf = &data->rf;
811
812 if (!in_range(val, 0, APDS9306_ALS_THRES_VAR_NUM_VALS))
813 return -EINVAL;
814
815 return regmap_field_write(rf->int_thresh_var_val, val);
816 }
817
apds9306_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)818 static int apds9306_read_raw(struct iio_dev *indio_dev,
819 struct iio_chan_spec const *chan, int *val,
820 int *val2, long mask)
821 {
822 struct apds9306_data *data = iio_priv(indio_dev);
823 int ret, reg;
824
825 switch (mask) {
826 case IIO_CHAN_INFO_RAW:
827 if (chan->channel2 == IIO_MOD_LIGHT_CLEAR)
828 reg = APDS9306_CLEAR_DATA_0_REG;
829 else
830 reg = APDS9306_ALS_DATA_0_REG;
831 /*
832 * Changing device parameters during adc operation, resets
833 * the ADC which has to avoided.
834 */
835 if (!iio_device_claim_direct(indio_dev))
836 return -EBUSY;
837 ret = apds9306_read_data(data, val, reg);
838 iio_device_release_direct(indio_dev);
839 if (ret)
840 return ret;
841
842 return IIO_VAL_INT;
843 case IIO_CHAN_INFO_INT_TIME:
844 ret = apds9306_intg_time_get(data, val2);
845 if (ret)
846 return ret;
847 *val = 0;
848
849 return IIO_VAL_INT_PLUS_MICRO;
850 case IIO_CHAN_INFO_SAMP_FREQ:
851 ret = apds9306_sampling_freq_get(data, val, val2);
852 if (ret)
853 return ret;
854
855 return IIO_VAL_INT_PLUS_MICRO;
856 case IIO_CHAN_INFO_SCALE:
857 ret = apds9306_scale_get(data, val, val2);
858 if (ret)
859 return ret;
860
861 return IIO_VAL_INT_PLUS_NANO;
862 default:
863 return -EINVAL;
864 }
865 };
866
apds9306_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)867 static int apds9306_read_avail(struct iio_dev *indio_dev,
868 struct iio_chan_spec const *chan,
869 const int **vals, int *type, int *length,
870 long mask)
871 {
872 struct apds9306_data *data = iio_priv(indio_dev);
873
874 switch (mask) {
875 case IIO_CHAN_INFO_INT_TIME:
876 return iio_gts_avail_times(&data->gts, vals, type, length);
877 case IIO_CHAN_INFO_SCALE:
878 return iio_gts_all_avail_scales(&data->gts, vals, type, length);
879 case IIO_CHAN_INFO_SAMP_FREQ:
880 *length = ARRAY_SIZE(apds9306_repeat_rate_freq) * 2;
881 *vals = (const int *)apds9306_repeat_rate_freq;
882 *type = IIO_VAL_INT_PLUS_MICRO;
883
884 return IIO_AVAIL_LIST;
885 default:
886 return -EINVAL;
887 }
888 }
889
apds9306_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)890 static int apds9306_write_raw_get_fmt(struct iio_dev *indio_dev,
891 struct iio_chan_spec const *chan,
892 long mask)
893 {
894 switch (mask) {
895 case IIO_CHAN_INFO_SCALE:
896 return IIO_VAL_INT_PLUS_NANO;
897 case IIO_CHAN_INFO_INT_TIME:
898 return IIO_VAL_INT_PLUS_MICRO;
899 case IIO_CHAN_INFO_SAMP_FREQ:
900 return IIO_VAL_INT_PLUS_MICRO;
901 default:
902 return -EINVAL;
903 }
904 }
905
apds9306_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)906 static int apds9306_write_raw(struct iio_dev *indio_dev,
907 struct iio_chan_spec const *chan, int val,
908 int val2, long mask)
909 {
910 struct apds9306_data *data = iio_priv(indio_dev);
911
912 guard(mutex)(&data->mutex);
913
914 switch (mask) {
915 case IIO_CHAN_INFO_INT_TIME:
916 if (val)
917 return -EINVAL;
918 return apds9306_intg_time_set(data, val2);
919 case IIO_CHAN_INFO_SCALE:
920 return apds9306_scale_set(data, val, val2);
921 case IIO_CHAN_INFO_SAMP_FREQ:
922 return apds9306_sampling_freq_set(data, val, val2);
923 default:
924 return -EINVAL;
925 }
926 }
927
apds9306_irq_handler(int irq,void * priv)928 static irqreturn_t apds9306_irq_handler(int irq, void *priv)
929 {
930 struct iio_dev *indio_dev = priv;
931 struct apds9306_data *data = iio_priv(indio_dev);
932 struct apds9306_regfields *rf = &data->rf;
933 u64 ev_code;
934 int ret, status, int_src;
935
936 /*
937 * The interrupt line is released and the interrupt flag is
938 * cleared as a result of reading the status register. All the
939 * status flags are cleared as a result of this read.
940 */
941 ret = regmap_read(data->regmap, APDS9306_MAIN_STATUS_REG, &status);
942 if (ret < 0) {
943 dev_err_ratelimited(data->dev, "status reg read failed\n");
944 return IRQ_HANDLED;
945 }
946
947 ret = regmap_field_read(rf->int_src, &int_src);
948 if (ret)
949 return ret;
950
951 if ((status & APDS9306_ALS_INT_STAT_MASK)) {
952 if (int_src == APDS9306_INT_SRC_ALS)
953 ev_code = IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
954 IIO_EV_TYPE_THRESH,
955 IIO_EV_DIR_EITHER);
956 else
957 ev_code = IIO_MOD_EVENT_CODE(IIO_INTENSITY, 0,
958 IIO_MOD_LIGHT_CLEAR,
959 IIO_EV_TYPE_THRESH,
960 IIO_EV_DIR_EITHER);
961
962 iio_push_event(indio_dev, ev_code, iio_get_time_ns(indio_dev));
963 }
964
965 /*
966 * If a one-shot read through sysfs is underway at the same time
967 * as this interrupt handler is executing and a read data available
968 * flag was set, this flag is set to inform read_poll_timeout()
969 * to exit.
970 */
971 if ((status & APDS9306_ALS_DATA_STAT_MASK))
972 data->read_data_available = 1;
973
974 return IRQ_HANDLED;
975 }
976
apds9306_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)977 static int apds9306_read_event(struct iio_dev *indio_dev,
978 const struct iio_chan_spec *chan,
979 enum iio_event_type type,
980 enum iio_event_direction dir,
981 enum iio_event_info info,
982 int *val, int *val2)
983 {
984 struct apds9306_data *data = iio_priv(indio_dev);
985 int ret;
986
987 switch (type) {
988 case IIO_EV_TYPE_THRESH:
989 if (dir == IIO_EV_DIR_EITHER && info == IIO_EV_INFO_PERIOD)
990 ret = apds9306_event_period_get(data, val);
991 else
992 ret = apds9306_event_thresh_get(data, dir, val);
993 if (ret)
994 return ret;
995
996 return IIO_VAL_INT;
997 case IIO_EV_TYPE_THRESH_ADAPTIVE:
998 ret = apds9306_event_thresh_adaptive_get(data, val);
999 if (ret)
1000 return ret;
1001
1002 return IIO_VAL_INT;
1003 default:
1004 return -EINVAL;
1005 }
1006 }
1007
apds9306_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1008 static int apds9306_write_event(struct iio_dev *indio_dev,
1009 const struct iio_chan_spec *chan,
1010 enum iio_event_type type,
1011 enum iio_event_direction dir,
1012 enum iio_event_info info,
1013 int val, int val2)
1014 {
1015 struct apds9306_data *data = iio_priv(indio_dev);
1016
1017 switch (type) {
1018 case IIO_EV_TYPE_THRESH:
1019 if (dir == IIO_EV_DIR_EITHER && info == IIO_EV_INFO_PERIOD)
1020 return apds9306_event_period_set(data, val);
1021
1022 return apds9306_event_thresh_set(data, dir, val);
1023 case IIO_EV_TYPE_THRESH_ADAPTIVE:
1024 return apds9306_event_thresh_adaptive_set(data, val);
1025 default:
1026 return -EINVAL;
1027 }
1028 }
1029
apds9306_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1030 static int apds9306_read_event_config(struct iio_dev *indio_dev,
1031 const struct iio_chan_spec *chan,
1032 enum iio_event_type type,
1033 enum iio_event_direction dir)
1034 {
1035 struct apds9306_data *data = iio_priv(indio_dev);
1036 struct apds9306_regfields *rf = &data->rf;
1037 int int_en, int_src, ret;
1038
1039 switch (type) {
1040 case IIO_EV_TYPE_THRESH: {
1041 guard(mutex)(&data->mutex);
1042
1043 ret = regmap_field_read(rf->int_src, &int_src);
1044 if (ret)
1045 return ret;
1046
1047 ret = regmap_field_read(rf->int_en, &int_en);
1048 if (ret)
1049 return ret;
1050
1051 if (chan->type == IIO_LIGHT)
1052 return int_en && (int_src == APDS9306_INT_SRC_ALS);
1053
1054 if (chan->type == IIO_INTENSITY)
1055 return int_en && (int_src == APDS9306_INT_SRC_CLEAR);
1056
1057 return -EINVAL;
1058 }
1059 case IIO_EV_TYPE_THRESH_ADAPTIVE:
1060 ret = regmap_field_read(rf->int_thresh_var_en, &int_en);
1061 if (ret)
1062 return ret;
1063
1064 return int_en;
1065 default:
1066 return -EINVAL;
1067 }
1068 }
1069
apds9306_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1070 static int apds9306_write_event_config(struct iio_dev *indio_dev,
1071 const struct iio_chan_spec *chan,
1072 enum iio_event_type type,
1073 enum iio_event_direction dir,
1074 bool state)
1075 {
1076 struct apds9306_data *data = iio_priv(indio_dev);
1077 struct apds9306_regfields *rf = &data->rf;
1078 int ret, enabled;
1079
1080 switch (type) {
1081 case IIO_EV_TYPE_THRESH: {
1082 guard(mutex)(&data->mutex);
1083
1084 ret = regmap_field_read(rf->int_en, &enabled);
1085 if (ret)
1086 return ret;
1087
1088 /*
1089 * If interrupt is enabled, the channel is set before enabling
1090 * the interrupt. In case of disable, no need to switch
1091 * channels. In case of different channel is selected while
1092 * interrupt in on, just change the channel.
1093 */
1094 if (state) {
1095 if (chan->type == IIO_LIGHT)
1096 ret = regmap_field_write(rf->int_src, 1);
1097 else if (chan->type == IIO_INTENSITY)
1098 ret = regmap_field_write(rf->int_src, 0);
1099 else
1100 return -EINVAL;
1101
1102 if (ret)
1103 return ret;
1104
1105 if (enabled)
1106 return 0;
1107
1108 ret = regmap_field_write(rf->int_en, 1);
1109 if (ret)
1110 return ret;
1111
1112 return pm_runtime_resume_and_get(data->dev);
1113 } else {
1114 if (!enabled)
1115 return 0;
1116
1117 ret = regmap_field_write(rf->int_en, 0);
1118 if (ret)
1119 return ret;
1120
1121 pm_runtime_put_autosuspend(data->dev);
1122
1123 return 0;
1124 }
1125 }
1126 case IIO_EV_TYPE_THRESH_ADAPTIVE:
1127 return regmap_field_write(rf->int_thresh_var_en, state);
1128 default:
1129 return -EINVAL;
1130 }
1131 }
1132
1133 static const struct iio_info apds9306_info_no_events = {
1134 .read_avail = apds9306_read_avail,
1135 .read_raw = apds9306_read_raw,
1136 .write_raw = apds9306_write_raw,
1137 .write_raw_get_fmt = apds9306_write_raw_get_fmt,
1138 };
1139
1140 static const struct iio_info apds9306_info = {
1141 .read_avail = apds9306_read_avail,
1142 .read_raw = apds9306_read_raw,
1143 .write_raw = apds9306_write_raw,
1144 .write_raw_get_fmt = apds9306_write_raw_get_fmt,
1145 .read_event_value = apds9306_read_event,
1146 .write_event_value = apds9306_write_event,
1147 .read_event_config = apds9306_read_event_config,
1148 .write_event_config = apds9306_write_event_config,
1149 .event_attrs = &apds9306_event_attr_group,
1150 };
1151
apds9306_init_iio_gts(struct apds9306_data * data)1152 static int apds9306_init_iio_gts(struct apds9306_data *data)
1153 {
1154 int i, ret, part_id;
1155
1156 ret = regmap_read(data->regmap, APDS9306_PART_ID_REG, &part_id);
1157 if (ret)
1158 return ret;
1159
1160 for (i = 0; i < ARRAY_SIZE(apds9306_gts_mul); i++)
1161 if (part_id == apds9306_gts_mul[i].part_id)
1162 break;
1163
1164 if (i == ARRAY_SIZE(apds9306_gts_mul))
1165 return -ENOENT;
1166
1167 return devm_iio_init_iio_gts(data->dev,
1168 apds9306_gts_mul[i].max_scale_int,
1169 apds9306_gts_mul[i].max_scale_nano,
1170 apds9306_gains, ARRAY_SIZE(apds9306_gains),
1171 apds9306_itimes, ARRAY_SIZE(apds9306_itimes),
1172 &data->gts);
1173 }
1174
apds9306_powerdown(void * ptr)1175 static void apds9306_powerdown(void *ptr)
1176 {
1177 struct apds9306_data *data = ptr;
1178 struct apds9306_regfields *rf = &data->rf;
1179 int ret;
1180
1181 ret = regmap_field_write(rf->int_thresh_var_en, 0);
1182 if (ret)
1183 return;
1184
1185 ret = regmap_field_write(rf->int_en, 0);
1186 if (ret)
1187 return;
1188
1189 apds9306_power_state(data, false);
1190 }
1191
apds9306_device_init(struct apds9306_data * data)1192 static int apds9306_device_init(struct apds9306_data *data)
1193 {
1194 struct apds9306_regfields *rf = &data->rf;
1195 int ret;
1196
1197 ret = apds9306_init_iio_gts(data);
1198 if (ret)
1199 return ret;
1200
1201 ret = regmap_field_write(rf->intg_time, APDS9306_MEAS_MODE_100MS);
1202 if (ret)
1203 return ret;
1204
1205 ret = regmap_field_write(rf->repeat_rate, APDS9306_SAMP_FREQ_10HZ);
1206 if (ret)
1207 return ret;
1208
1209 ret = regmap_field_write(rf->gain, APDS9306_GSEL_3X);
1210 if (ret)
1211 return ret;
1212
1213 ret = regmap_field_write(rf->int_src, APDS9306_INT_SRC_ALS);
1214 if (ret)
1215 return ret;
1216
1217 ret = regmap_field_write(rf->int_en, 0);
1218 if (ret)
1219 return ret;
1220
1221 return regmap_field_write(rf->int_thresh_var_en, 0);
1222 }
1223
apds9306_pm_init(struct apds9306_data * data)1224 static int apds9306_pm_init(struct apds9306_data *data)
1225 {
1226 struct device *dev = data->dev;
1227 int ret;
1228
1229 ret = apds9306_power_state(data, true);
1230 if (ret)
1231 return ret;
1232
1233 ret = pm_runtime_set_active(dev);
1234 if (ret)
1235 return ret;
1236
1237 ret = devm_pm_runtime_enable(dev);
1238 if (ret)
1239 return ret;
1240
1241 pm_runtime_set_autosuspend_delay(dev, 5000);
1242 pm_runtime_use_autosuspend(dev);
1243 pm_runtime_get(dev);
1244
1245 return 0;
1246 }
1247
apds9306_probe(struct i2c_client * client)1248 static int apds9306_probe(struct i2c_client *client)
1249 {
1250 struct device *dev = &client->dev;
1251 struct apds9306_data *data;
1252 struct iio_dev *indio_dev;
1253 int ret;
1254
1255 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1256 if (!indio_dev)
1257 return -ENOMEM;
1258
1259 data = iio_priv(indio_dev);
1260
1261 mutex_init(&data->mutex);
1262
1263 data->regmap = devm_regmap_init_i2c(client, &apds9306_regmap);
1264 if (IS_ERR(data->regmap))
1265 return dev_err_probe(dev, PTR_ERR(data->regmap),
1266 "regmap initialization failed\n");
1267
1268 data->dev = dev;
1269 i2c_set_clientdata(client, indio_dev);
1270
1271 ret = apds9306_regfield_init(data);
1272 if (ret)
1273 return dev_err_probe(dev, ret, "regfield initialization failed\n");
1274
1275 ret = devm_regulator_get_enable(dev, "vdd");
1276 if (ret)
1277 return dev_err_probe(dev, ret, "Failed to enable regulator\n");
1278
1279 indio_dev->name = "apds9306";
1280 indio_dev->modes = INDIO_DIRECT_MODE;
1281 if (client->irq) {
1282 indio_dev->info = &apds9306_info;
1283 indio_dev->channels = apds9306_channels_with_events;
1284 indio_dev->num_channels = ARRAY_SIZE(apds9306_channels_with_events);
1285 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1286 apds9306_irq_handler, IRQF_ONESHOT,
1287 "apds9306_event", indio_dev);
1288 if (ret)
1289 return dev_err_probe(dev, ret,
1290 "failed to assign interrupt.\n");
1291 } else {
1292 indio_dev->info = &apds9306_info_no_events;
1293 indio_dev->channels = apds9306_channels_without_events;
1294 indio_dev->num_channels =
1295 ARRAY_SIZE(apds9306_channels_without_events);
1296 }
1297
1298 ret = apds9306_pm_init(data);
1299 if (ret)
1300 return dev_err_probe(dev, ret, "failed pm init\n");
1301
1302 ret = apds9306_device_init(data);
1303 if (ret)
1304 return dev_err_probe(dev, ret, "failed to init device\n");
1305
1306 ret = devm_add_action_or_reset(dev, apds9306_powerdown, data);
1307 if (ret)
1308 return ret;
1309
1310 ret = devm_iio_device_register(dev, indio_dev);
1311 if (ret)
1312 return dev_err_probe(dev, ret, "failed iio device registration\n");
1313
1314 pm_runtime_put_autosuspend(dev);
1315
1316 return 0;
1317 }
1318
apds9306_runtime_suspend(struct device * dev)1319 static int apds9306_runtime_suspend(struct device *dev)
1320 {
1321 struct apds9306_data *data = iio_priv(dev_get_drvdata(dev));
1322
1323 return apds9306_power_state(data, false);
1324 }
1325
apds9306_runtime_resume(struct device * dev)1326 static int apds9306_runtime_resume(struct device *dev)
1327 {
1328 struct apds9306_data *data = iio_priv(dev_get_drvdata(dev));
1329
1330 return apds9306_power_state(data, true);
1331 }
1332
1333 static DEFINE_RUNTIME_DEV_PM_OPS(apds9306_pm_ops,
1334 apds9306_runtime_suspend,
1335 apds9306_runtime_resume,
1336 NULL);
1337
1338 static const struct of_device_id apds9306_of_match[] = {
1339 { .compatible = "avago,apds9306" },
1340 { }
1341 };
1342 MODULE_DEVICE_TABLE(of, apds9306_of_match);
1343
1344 static struct i2c_driver apds9306_driver = {
1345 .driver = {
1346 .name = "apds9306",
1347 .pm = pm_ptr(&apds9306_pm_ops),
1348 .of_match_table = apds9306_of_match,
1349 },
1350 .probe = apds9306_probe,
1351 };
1352 module_i2c_driver(apds9306_driver);
1353
1354 MODULE_AUTHOR("Subhajit Ghosh <subhajit.ghosh@tweaklogic.com>");
1355 MODULE_DESCRIPTION("APDS9306 Ambient Light Sensor driver");
1356 MODULE_LICENSE("GPL");
1357 MODULE_IMPORT_NS("IIO_GTS_HELPER");
1358