1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 /* FILE POLICY AND INTENDED USAGE: 27 * This file manages link detection states and receiver states by using various 28 * link protocols. It also provides helper functions to interpret certain 29 * capabilities or status based on the states it manages or retrieve them 30 * directly from connected receivers. 31 */ 32 33 #include "link_dpms.h" 34 #include "link_detection.h" 35 #include "link_hwss.h" 36 #include "protocols/link_edp_panel_control.h" 37 #include "protocols/link_ddc.h" 38 #include "protocols/link_hpd.h" 39 #include "protocols/link_dpcd.h" 40 #include "protocols/link_dp_capability.h" 41 #include "protocols/link_dp_dpia.h" 42 #include "protocols/link_dp_phy.h" 43 #include "protocols/link_dp_training.h" 44 #include "protocols/link_hdmi_frl.h" 45 #include "protocols/link_dp_dpia_bw.h" 46 #include "accessories/link_dp_trace.h" 47 48 #include "link_enc_cfg.h" 49 #include "dm_helpers.h" 50 #include "clk_mgr.h" 51 52 // Offset DPCD 050Eh == 0x5A 53 #define MST_HUB_ID_0x5A 0x5A 54 55 #define DC_LOGGER \ 56 link->ctx->logger 57 #define DC_LOGGER_INIT(logger) 58 59 #define LINK_INFO(...) \ 60 DC_LOG_HW_HOTPLUG( \ 61 __VA_ARGS__) 62 /* 63 * Some receivers fail to train on first try and are good 64 * on subsequent tries. 2 retries should be plenty. If we 65 * don't have a successful training then we don't expect to 66 * ever get one. 67 */ 68 #define LINK_TRAINING_MAX_VERIFY_RETRY 2 69 70 static const u8 DP_SINK_BRANCH_DEV_NAME_7580[] = "7580\x80u"; 71 72 static const u8 dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR"; 73 74 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal) 75 { 76 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE; 77 78 switch (sink_signal) { 79 case SIGNAL_TYPE_DVI_SINGLE_LINK: 80 case SIGNAL_TYPE_DVI_DUAL_LINK: 81 case SIGNAL_TYPE_HDMI_TYPE_A: 82 case SIGNAL_TYPE_HDMI_FRL: 83 case SIGNAL_TYPE_LVDS: 84 case SIGNAL_TYPE_RGB: 85 transaction_type = DDC_TRANSACTION_TYPE_I2C; 86 break; 87 88 case SIGNAL_TYPE_DISPLAY_PORT: 89 case SIGNAL_TYPE_EDP: 90 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 91 break; 92 93 case SIGNAL_TYPE_DISPLAY_PORT_MST: 94 /* MST does not use I2COverAux, but there is the 95 * SPECIAL use case for "immediate dwnstrm device 96 * access" (EPR#370830). 97 */ 98 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 99 break; 100 101 default: 102 break; 103 } 104 105 return transaction_type; 106 } 107 108 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder, 109 struct graphics_object_id downstream) 110 { 111 if (downstream.type == OBJECT_TYPE_CONNECTOR) { 112 switch (downstream.id) { 113 case CONNECTOR_ID_SINGLE_LINK_DVII: 114 switch (encoder.id) { 115 case ENCODER_ID_INTERNAL_DAC1: 116 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 117 case ENCODER_ID_INTERNAL_DAC2: 118 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 119 return SIGNAL_TYPE_RGB; 120 default: 121 return SIGNAL_TYPE_DVI_SINGLE_LINK; 122 } 123 break; 124 case CONNECTOR_ID_DUAL_LINK_DVII: 125 { 126 switch (encoder.id) { 127 case ENCODER_ID_INTERNAL_DAC1: 128 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 129 case ENCODER_ID_INTERNAL_DAC2: 130 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 131 return SIGNAL_TYPE_RGB; 132 default: 133 return SIGNAL_TYPE_DVI_DUAL_LINK; 134 } 135 } 136 break; 137 case CONNECTOR_ID_SINGLE_LINK_DVID: 138 return SIGNAL_TYPE_DVI_SINGLE_LINK; 139 case CONNECTOR_ID_DUAL_LINK_DVID: 140 return SIGNAL_TYPE_DVI_DUAL_LINK; 141 case CONNECTOR_ID_VGA: 142 return SIGNAL_TYPE_RGB; 143 case CONNECTOR_ID_HDMI_TYPE_A: 144 return SIGNAL_TYPE_HDMI_TYPE_A; 145 case CONNECTOR_ID_LVDS: 146 return SIGNAL_TYPE_LVDS; 147 case CONNECTOR_ID_DISPLAY_PORT: 148 case CONNECTOR_ID_USBC: 149 return SIGNAL_TYPE_DISPLAY_PORT; 150 case CONNECTOR_ID_EDP: 151 return SIGNAL_TYPE_EDP; 152 default: 153 return SIGNAL_TYPE_NONE; 154 } 155 } 156 157 return SIGNAL_TYPE_NONE; 158 } 159 160 /* 161 * @brief 162 * Detect output sink type 163 */ 164 static enum signal_type link_detect_sink_signal_type(struct dc_link *link, 165 enum dc_detect_reason reason) 166 { 167 enum signal_type result; 168 struct audio_support *aud_support; 169 struct graphics_object_id enc_id; 170 171 /* External DP bridges should use DP signal regardless of connector type. */ 172 if (link->ext_enc_id.id) 173 return SIGNAL_TYPE_DISPLAY_PORT; 174 175 if (link->is_dig_mapping_flexible) 176 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN}; 177 else 178 enc_id = link->link_enc->id; 179 result = get_basic_signal_type(enc_id, link->link_id); 180 181 /* Use basic signal type for link without physical connector. */ 182 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 183 return result; 184 185 /* 186 * Internal digital encoder will detect only dongles 187 * that require digital signal 188 */ 189 190 /* 191 * Detection mechanism is different 192 * for different native connectors. 193 * LVDS connector supports only LVDS signal; 194 * PCIE is a bus slot, the actual connector needs to be detected first; 195 * eDP connector supports only eDP signal; 196 * HDMI should check straps for audio 197 */ 198 switch (link->link_id.id) { 199 case CONNECTOR_ID_HDMI_TYPE_A: 200 /* 201 * check audio support: 202 * if native HDMI is not supported, switch to DVI 203 */ 204 aud_support = &link->dc->res_pool->audio_support; 205 206 if (!aud_support->hdmi_audio_native) 207 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 208 break; 209 case CONNECTOR_ID_DISPLAY_PORT: 210 case CONNECTOR_ID_USBC: 211 /* 212 * DP HPD short pulse. Passive DP dongle will not 213 * have short pulse 214 */ 215 if (reason != DETECT_REASON_HPDRX) { 216 /* 217 * Check whether DP signal detected: if not - 218 * we assume signal is DVI; it could be corrected 219 * to HDMI after dongle detection 220 */ 221 if (!dm_helpers_is_dp_sink_present(link)) 222 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 223 } 224 break; 225 case CONNECTOR_ID_PCIE: 226 /* ZAZTODO implement PCIE add-on card detection */ 227 break; 228 default: 229 break; 230 } 231 232 return result; 233 } 234 235 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type, 236 struct audio_support *audio_support) 237 { 238 enum signal_type signal = SIGNAL_TYPE_NONE; 239 240 switch (dongle_type) { 241 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 242 if (audio_support->hdmi_audio_on_dongle) 243 signal = SIGNAL_TYPE_HDMI_TYPE_A; 244 else 245 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 246 break; 247 case DISPLAY_DONGLE_DP_DVI_DONGLE: 248 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 249 break; 250 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 251 if (audio_support->hdmi_audio_native) 252 signal = SIGNAL_TYPE_HDMI_TYPE_A; 253 else 254 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 255 break; 256 default: 257 signal = SIGNAL_TYPE_NONE; 258 break; 259 } 260 261 return signal; 262 } 263 264 static void read_scdc_caps(struct ddc_service *ddc_service, 265 struct dc_sink *sink) 266 { 267 uint8_t slave_address = HDMI_SCDC_ADDRESS; 268 uint8_t offset = HDMI_SCDC_MANUFACTURER_OUI; 269 270 if (ddc_service->link->local_sink && 271 !ddc_service->link->local_sink->edid_caps.scdc_present) 272 return; 273 274 link_query_ddc_data(ddc_service, slave_address, &offset, 275 sizeof(offset), sink->scdc_caps.manufacturer_OUI.byte, 276 sizeof(sink->scdc_caps.manufacturer_OUI.byte)); 277 278 offset = HDMI_SCDC_DEVICE_ID; 279 280 link_query_ddc_data(ddc_service, slave_address, &offset, 281 sizeof(offset), &(sink->scdc_caps.device_id.byte), 282 sizeof(sink->scdc_caps.device_id.byte)); 283 } 284 285 static bool i2c_read( 286 struct ddc_service *ddc, 287 uint32_t address, 288 uint8_t *buffer, 289 uint32_t len) 290 { 291 uint8_t offs_data = 0; 292 struct i2c_payload payloads[2] = { 293 { 294 .write = true, 295 .address = (uint8_t)address, 296 .length = 1, 297 .data = &offs_data }, 298 { 299 .write = false, 300 .address = (uint8_t)address, 301 .length = len, 302 .data = buffer } }; 303 304 struct i2c_command command = { 305 .payloads = payloads, 306 .number_of_payloads = 2, 307 .engine = DDC_I2C_COMMAND_ENGINE, 308 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz }; 309 310 return dm_helpers_submit_i2c( 311 ddc->ctx, 312 ddc->link, 313 &command); 314 } 315 316 enum { 317 DP_SINK_CAP_SIZE = 318 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1 319 }; 320 321 static void query_dp_dual_mode_adaptor( 322 struct ddc_service *ddc, 323 struct display_sink_capability *sink_cap) 324 { 325 uint8_t i; 326 bool is_valid_hdmi_signature; 327 enum display_dongle_type *dongle = &sink_cap->dongle_type; 328 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE]; 329 bool is_type2_dongle = false; 330 int retry_count = 2; 331 struct dp_hdmi_dongle_signature_data *dongle_signature; 332 struct dc_link *link = ddc->link; 333 334 /* Assume we have no valid DP passive dongle connected */ 335 *dongle = DISPLAY_DONGLE_NONE; 336 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; 337 338 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/ 339 if (!i2c_read( 340 ddc, 341 DP_HDMI_DONGLE_ADDRESS, 342 type2_dongle_buf, 343 sizeof(type2_dongle_buf))) { 344 /* Passive HDMI dongles can sometimes fail here without retrying*/ 345 while (retry_count > 0) { 346 if (i2c_read(ddc, 347 DP_HDMI_DONGLE_ADDRESS, 348 type2_dongle_buf, 349 sizeof(type2_dongle_buf))) 350 break; 351 retry_count--; 352 } 353 if (retry_count == 0) { 354 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 355 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; 356 357 CONN_DATA_DETECT(link, type2_dongle_buf, sizeof(type2_dongle_buf), 358 "DP-DVI passive dongle %dMhz: ", 359 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 360 return; 361 } 362 } 363 364 /* Check if Type 2 dongle.*/ 365 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID) 366 is_type2_dongle = true; 367 368 dongle_signature = 369 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf; 370 371 is_valid_hdmi_signature = true; 372 373 /* Check EOT */ 374 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) { 375 is_valid_hdmi_signature = false; 376 } 377 378 /* Check signature */ 379 for (i = 0; i < sizeof(dongle_signature->id); ++i) { 380 /* If its not the right signature, 381 * skip mismatch in subversion byte.*/ 382 if (dongle_signature->id[i] != 383 dp_hdmi_dongle_signature_str[i] && i != 3) { 384 385 if (is_type2_dongle) { 386 is_valid_hdmi_signature = false; 387 break; 388 } 389 390 } 391 } 392 if (is_valid_hdmi_signature) 393 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK; 394 395 if (is_type2_dongle) { 396 uint32_t max_tmds_clk = 397 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK]; 398 399 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2; 400 401 if (0 == max_tmds_clk || 402 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK || 403 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) { 404 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; 405 406 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 407 sizeof(type2_dongle_buf), 408 "DP-DVI passive dongle %dMhz: ", 409 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); 410 } else { 411 if (is_valid_hdmi_signature == true) { 412 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 413 414 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 415 sizeof(type2_dongle_buf), 416 "Type 2 DP-HDMI passive dongle %dMhz: ", 417 max_tmds_clk); 418 } else { 419 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 420 421 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 422 sizeof(type2_dongle_buf), 423 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ", 424 max_tmds_clk); 425 426 } 427 428 /* Multiply by 1000 to convert to kHz. */ 429 sink_cap->max_hdmi_pixel_clock = 430 max_tmds_clk * 1000; 431 } 432 sink_cap->is_dongle_type_one = false; 433 434 } else { 435 if (is_valid_hdmi_signature == true) { 436 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE; 437 438 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 439 sizeof(type2_dongle_buf), 440 "Type 1 DP-HDMI passive dongle %dMhz: ", 441 sink_cap->max_hdmi_pixel_clock / 1000); 442 } else { 443 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE; 444 445 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, 446 sizeof(type2_dongle_buf), 447 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ", 448 sink_cap->max_hdmi_pixel_clock / 1000); 449 } 450 sink_cap->is_dongle_type_one = true; 451 } 452 453 return; 454 } 455 456 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc, 457 struct display_sink_capability *sink_cap, 458 struct audio_support *audio_support) 459 { 460 query_dp_dual_mode_adaptor(ddc, sink_cap); 461 462 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type, 463 audio_support); 464 } 465 466 static void link_disconnect_sink(struct dc_link *link) 467 { 468 if (link->local_sink) { 469 dc_sink_release(link->local_sink); 470 link->local_sink = NULL; 471 } 472 473 link->dpcd_sink_count = 0; 474 //link->dpcd_caps.dpcd_rev.raw = 0; 475 } 476 477 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link) 478 { 479 dc_sink_release(link->local_sink); 480 link->local_sink = prev_sink; 481 } 482 483 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link) 484 { 485 struct hdcp_protection_message msg22; 486 struct hdcp_protection_message msg14; 487 488 memset(&msg22, 0, sizeof(struct hdcp_protection_message)); 489 memset(&msg14, 0, sizeof(struct hdcp_protection_message)); 490 memset(link->hdcp_caps.rx_caps.raw, 0, 491 sizeof(link->hdcp_caps.rx_caps.raw)); 492 493 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 494 link->ddc->transaction_type == 495 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) || 496 link->connector_signal == SIGNAL_TYPE_EDP) { 497 msg22.data = link->hdcp_caps.rx_caps.raw; 498 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw); 499 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS; 500 } else { 501 msg22.data = &link->hdcp_caps.rx_caps.fields.version; 502 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version); 503 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION; 504 } 505 msg22.version = HDCP_VERSION_22; 506 msg22.link = HDCP_LINK_PRIMARY; 507 msg22.max_retries = 5; 508 dc_process_hdcp_msg(signal, link, &msg22); 509 510 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 511 msg14.data = &link->hdcp_caps.bcaps.raw; 512 msg14.length = sizeof(link->hdcp_caps.bcaps.raw); 513 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS; 514 msg14.version = HDCP_VERSION_14; 515 msg14.link = HDCP_LINK_PRIMARY; 516 msg14.max_retries = 5; 517 518 dc_process_hdcp_msg(signal, link, &msg14); 519 } 520 521 } 522 static void read_current_link_settings_on_detect(struct dc_link *link) 523 { 524 union lane_count_set lane_count_set = {0}; 525 uint8_t link_bw_set = 0; 526 uint8_t link_rate_set = 0; 527 uint32_t read_dpcd_retry_cnt = 10; 528 enum dc_status status = DC_ERROR_UNEXPECTED; 529 unsigned int i; 530 union max_down_spread max_down_spread = {0}; 531 532 // Read DPCD 00101h to find out the number of lanes currently set 533 for (i = 0; i < read_dpcd_retry_cnt; i++) { 534 status = core_link_read_dpcd(link, 535 DP_LANE_COUNT_SET, 536 &lane_count_set.raw, 537 sizeof(lane_count_set)); 538 /* First DPCD read after VDD ON can fail if the particular board 539 * does not have HPD pin wired correctly. So if DPCD read fails, 540 * which it should never happen, retry a few times. Target worst 541 * case scenario of 80 ms. 542 */ 543 if (status == DC_OK) { 544 link->cur_link_settings.lane_count = 545 lane_count_set.bits.LANE_COUNT_SET; 546 break; 547 } 548 549 msleep(8); 550 } 551 552 // Read DPCD 00100h to find if standard link rates are set 553 core_link_read_dpcd(link, DP_LINK_BW_SET, 554 &link_bw_set, sizeof(link_bw_set)); 555 556 if (link_bw_set == 0) { 557 if (link->connector_signal == SIGNAL_TYPE_EDP) { 558 /* If standard link rates are not being used, 559 * Read DPCD 00115h to find the edp link rate set used 560 */ 561 core_link_read_dpcd(link, DP_LINK_RATE_SET, 562 &link_rate_set, sizeof(link_rate_set)); 563 564 // edp_supported_link_rates_count = 0 for DP 565 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 566 link->cur_link_settings.link_rate = 567 link->dpcd_caps.edp_supported_link_rates[link_rate_set]; 568 link->cur_link_settings.link_rate_set = link_rate_set; 569 link->cur_link_settings.use_link_rate_set = true; 570 } 571 } else { 572 // Link Rate not found. Seamless boot may not work. 573 ASSERT(false); 574 } 575 } else { 576 link->cur_link_settings.link_rate = link_bw_set; 577 link->cur_link_settings.use_link_rate_set = false; 578 } 579 // Read DPCD 00003h to find the max down spread. 580 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD, 581 &max_down_spread.raw, sizeof(max_down_spread)); 582 link->cur_link_settings.link_spread = 583 max_down_spread.bits.MAX_DOWN_SPREAD ? 584 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 585 } 586 587 static bool detect_dp(struct dc_link *link, 588 struct display_sink_capability *sink_caps, 589 enum dc_detect_reason reason) 590 { 591 struct audio_support *audio_support = &link->dc->res_pool->audio_support; 592 593 sink_caps->signal = link_detect_sink_signal_type(link, reason); 594 sink_caps->transaction_type = 595 get_ddc_transaction_type(sink_caps->signal); 596 597 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 598 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; 599 if (!detect_dp_sink_caps(link)) { 600 return false; 601 } 602 603 if (is_dp_branch_device(link)) 604 /* DP SST branch */ 605 link->type = dc_connection_sst_branch; 606 } else { 607 if (link->dc->debug.disable_dp_plus_plus_wa && 608 link->link_enc->features.flags.bits.IS_UHBR20_CAPABLE) 609 return false; 610 611 /* DP passive dongles */ 612 sink_caps->signal = dp_passive_dongle_detection(link->ddc, 613 sink_caps, 614 audio_support); 615 link->dpcd_caps.dongle_type = sink_caps->dongle_type; 616 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one; 617 link->dpcd_caps.dpcd_rev.raw = 0; 618 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0; 619 } 620 621 if (link->ext_enc_id.id) { 622 /* Fix number of connected sinks reported by external DP bridge */ 623 link->dpcd_caps.sink_count.bits.SINK_COUNT = 1; 624 /* NUTMEG requires that we use HBR, doesn't work with RBR. */ 625 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_00001A) 626 link->preferred_link_setting.link_rate = LINK_RATE_HIGH; 627 } 628 629 return true; 630 } 631 632 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid) 633 { 634 if (old_edid == NULL || new_edid == NULL) 635 return false; 636 637 if (old_edid->length != new_edid->length) 638 return false; 639 640 if (new_edid->length == 0) 641 return false; 642 643 return (memcmp(old_edid->raw_edid, 644 new_edid->raw_edid, new_edid->length) == 0); 645 } 646 647 static bool wait_for_entering_dp_alt_mode(struct dc_link *link) 648 { 649 650 /** 651 * something is terribly wrong if time out is > 200ms. (5Hz) 652 * 500 microseconds * 400 tries us 200 ms 653 **/ 654 unsigned int sleep_time_in_microseconds = 500; 655 unsigned int tries_allowed = 400; 656 bool is_in_alt_mode; 657 unsigned long long enter_timestamp; 658 unsigned long long finish_timestamp; 659 unsigned long long time_taken_in_ns; 660 unsigned int tries_taken; 661 662 /** 663 * this function will only exist if we are on dcn21 (is_in_alt_mode is a 664 * function pointer, so checking to see if it is equal to 0 is the same 665 * as checking to see if it is null 666 **/ 667 if (!link->link_enc->funcs->is_in_alt_mode) 668 return true; 669 670 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc); 671 DC_LOG_DC("DP Alt mode state on HPD: %d Link=%d\n", is_in_alt_mode, link->link_index); 672 673 if (is_in_alt_mode) 674 return true; 675 676 enter_timestamp = dm_get_timestamp(link->ctx); 677 678 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) { 679 udelay(sleep_time_in_microseconds); 680 /* ask the link if alt mode is enabled, if so return ok */ 681 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) { 682 finish_timestamp = dm_get_timestamp(link->ctx); 683 time_taken_in_ns = 684 dm_get_elapse_time_in_ns(link->ctx, 685 finish_timestamp, 686 enter_timestamp); 687 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n", 688 div_u64(time_taken_in_ns, 1000000)); 689 return true; 690 } 691 } 692 finish_timestamp = dm_get_timestamp(link->ctx); 693 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, 694 enter_timestamp); 695 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n", 696 div_u64(time_taken_in_ns, 1000000)); 697 return false; 698 } 699 700 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link) 701 { 702 /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock 703 * reports DSC support. 704 */ 705 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 706 link->type == dc_connection_mst_branch && 707 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 708 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 && 709 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 710 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) 711 link->wa_flags.dpia_mst_dsc_always_on = true; 712 713 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 714 link->type == dc_connection_mst_branch && 715 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && 716 link->dpcd_caps.branch_vendor_specific_data[2] == MST_HUB_ID_0x5A && 717 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && 718 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) { 719 link->wa_flags.dpia_mst_dsc_always_on = true; 720 } 721 } 722 723 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link) 724 { 725 /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */ 726 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 727 link->wa_flags.dpia_mst_dsc_always_on = false; 728 } 729 730 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason) 731 { 732 LINK_INFO("link=%d, mst branch is now Connected\n", 733 link->link_index); 734 735 link->type = dc_connection_mst_branch; 736 apply_dpia_mst_dsc_always_on_wa(link); 737 738 dm_helpers_dp_update_branch_info(link->ctx, link); 739 if (dm_helpers_dp_mst_start_top_mgr(link->ctx, 740 link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) { 741 link_disconnect_sink(link); 742 } else { 743 link->type = dc_connection_sst_branch; 744 } 745 746 return link->type == dc_connection_mst_branch; 747 } 748 749 bool link_reset_cur_dp_mst_topology(struct dc_link *link) 750 { 751 LINK_INFO("link=%d, mst branch is now Disconnected\n", 752 link->link_index); 753 754 revert_dpia_mst_dsc_always_on_wa(link); 755 return dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); 756 } 757 758 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc, 759 enum dc_detect_reason reason) 760 { 761 int i; 762 bool can_apply_seamless_boot = false; 763 764 for (i = 0; i < dc->current_state->stream_count; i++) { 765 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) { 766 can_apply_seamless_boot = true; 767 break; 768 } 769 } 770 771 return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT; 772 } 773 774 static bool is_hdmi_frl_in_use(struct dc_link *link) 775 { 776 int i; 777 unsigned int hdmi_conn_count = 0; 778 unsigned int hdmi_stream_count = 0; 779 bool hdmi_frl_in_use = false; 780 bool incoming_link_identical = false; 781 782 /*Enumerate HDMI connector from all present links */ 783 for (i = 0; i < link->dc->link_count; i++) { 784 if (link->dc->links[i] != NULL && 785 dc_is_hdmi_signal(link->dc->links[i]->connector_signal)) 786 hdmi_conn_count++; 787 } 788 /* If less than 2 HDMI Connector, assume HPO is always available*/ 789 if (hdmi_conn_count < 2) 790 return false; 791 792 /*Enumerate existing HDMI stream count*/ 793 for (i = 0; i < link->dc->current_state->stream_count; i++) { 794 if (dc_is_hdmi_signal(link->dc->current_state->streams[i]->signal)) 795 hdmi_stream_count++; 796 if (link == link->dc->current_state->streams[i]->link && 797 (dc_is_hdmi_frl_signal(link->dc->current_state->streams[i]->signal))) 798 incoming_link_identical = true; 799 } 800 801 if (hdmi_stream_count > 1 || (hdmi_stream_count == 1 && !incoming_link_identical)) { 802 for (i = 0; i < link->dc->current_state->stream_count; i++) { 803 if (dc_is_hdmi_frl_signal( 804 link->dc->current_state->streams[i]->signal)) { 805 hdmi_frl_in_use = true; 806 break; 807 } 808 } 809 } 810 811 /* Check if previous link already has been assigned with FRL*/ 812 if (!hdmi_frl_in_use && !incoming_link_identical) { 813 for (i = 0; i < link->dc->link_count; i++) { 814 if (link->dc->links[i] != NULL && 815 link->dc->links[i]->local_sink != NULL && 816 link != link->dc->links[i] && 817 dc_is_hdmi_frl_signal( 818 link->dc->links[i]->local_sink->sink_signal)) { 819 hdmi_frl_in_use = true; 820 break; 821 } 822 } 823 } 824 825 return hdmi_frl_in_use; 826 } 827 828 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc) 829 { 830 dc_z10_restore(dc); 831 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 832 } 833 834 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc) 835 { 836 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 837 } 838 839 static void verify_link_capability_destructive(struct dc_link *link, 840 enum dc_detect_reason reason) 841 { 842 bool should_prepare_phy_clocks = 843 should_prepare_phy_clocks_for_link_verification(link->dc, reason); 844 845 if (should_prepare_phy_clocks) 846 prepare_phy_clocks_for_destructive_link_verification(link->dc); 847 848 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 849 struct dc_link_settings known_limit_link_setting = 850 dp_get_max_link_cap(link); 851 link_set_all_streams_dpms_off_for_link(link); 852 dp_verify_link_cap_with_retries( 853 link, &known_limit_link_setting, 854 LINK_TRAINING_MAX_VERIFY_RETRY); 855 } else if (dc_is_hdmi_signal(link->local_sink->sink_signal)) { 856 if (!is_hdmi_frl_in_use(link)) { 857 link_set_all_streams_dpms_off_for_link(link); 858 hdmi_frl_verify_link_cap(link, &link->frl_reported_link_cap); 859 link->local_sink->sink_signal = (link->frl_verified_link_cap.frl_link_rate != HDMI_FRL_LINK_RATE_DISABLE) 860 ? SIGNAL_TYPE_HDMI_FRL : SIGNAL_TYPE_HDMI_TYPE_A; 861 } else { 862 link->local_sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 863 link->frl_verified_link_cap.frl_link_rate = HDMI_FRL_LINK_RATE_DISABLE; 864 } 865 } else { 866 ASSERT(0); 867 } 868 869 if (should_prepare_phy_clocks) 870 restore_phy_clocks_for_destructive_link_verification(link->dc); 871 } 872 873 static void verify_link_capability_non_destructive(struct dc_link *link) 874 { 875 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 876 if (dc_is_embedded_signal(link->local_sink->sink_signal) || 877 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) 878 /* TODO - should we check link encoder's max link caps here? 879 * How do we know which link encoder to check from? 880 */ 881 link->verified_link_cap = link->reported_link_cap; 882 else 883 link->verified_link_cap = dp_get_max_link_cap(link); 884 } else if (dc_is_hdmi_signal(link->local_sink->sink_signal)) { 885 link->verified_link_cap = link->reported_link_cap; 886 887 if (is_hdmi_frl_in_use(link)) { 888 link->local_sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 889 link->frl_verified_link_cap.frl_link_rate = HDMI_FRL_LINK_RATE_DISABLE; 890 } 891 } 892 } 893 894 static bool should_verify_link_capability_destructively(struct dc_link *link, 895 enum dc_detect_reason reason) 896 { 897 (void)reason; 898 bool destrictive = false; 899 struct dc_link_settings max_link_cap; 900 bool is_link_enc_unavailable = false; 901 902 if (!link->dc->config.unify_link_enc_assignment) 903 is_link_enc_unavailable = link->link_enc && 904 link->dc->res_pool->funcs->link_encs_assign && 905 !link_enc_cfg_is_link_enc_avail( 906 link->ctx->dc, 907 link->link_enc->preferred_engine, 908 link); 909 910 if (dc_is_dp_signal(link->local_sink->sink_signal)) { 911 max_link_cap = dp_get_max_link_cap(link); 912 destrictive = true; 913 914 if (link->dc->debug.skip_detection_link_training || 915 dc_is_embedded_signal(link->local_sink->sink_signal) || 916 (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 917 !link->dc->config.enable_dpia_pre_training)) { 918 destrictive = false; 919 } else if (link_dp_get_encoding_format(&max_link_cap) == 920 DP_8b_10b_ENCODING) { 921 if (link->dpcd_caps.is_mst_capable || 922 is_link_enc_unavailable) { 923 destrictive = false; 924 } 925 } 926 } else if (dc_is_hdmi_signal(link->local_sink->sink_signal) && link->link_enc && 927 link->link_enc->features.flags.bits.IS_HDMI_FRL_CAPABLE && 928 link->local_sink->edid_caps.max_frl_rate != 0) { 929 int i = 0; 930 struct pipe_ctx *pipes = 931 link->dc->current_state->res_ctx.pipe_ctx; 932 933 destrictive = true; 934 if (is_hdmi_frl_in_use(link)) { 935 destrictive = false; 936 } else if (link->dc->config.skip_frl_pretraining) { 937 for (i = 0; i < MAX_PIPES; i++) { 938 if (pipes[i].stream != NULL && 939 pipes[i].stream->link == link) { 940 /*If link is already active, skip PHY programming*/ 941 if (link->link_status.link_active) { 942 destrictive = false; 943 } 944 } 945 } 946 } 947 } 948 949 return destrictive; 950 } 951 952 static void verify_link_capability(struct dc_link *link, 953 enum dc_detect_reason reason) 954 { 955 if (should_verify_link_capability_destructively(link, reason)) 956 verify_link_capability_destructive(link, reason); 957 else 958 verify_link_capability_non_destructive(link); 959 } 960 961 /** 962 * link_detect_evaluate_edid_header() - Evaluate if an EDID header is acceptable. 963 * 964 * Evaluates an 8-byte EDID header to check if it's good enough 965 * for the purpose of determining whether a display is connected 966 * without reading the full EDID. 967 * 968 * @edid_header: The first 8 bytes of the EDID read from DDC. 969 * 970 * Return: true if the header looks valid (>= 6 of 8 bytes match the 971 * expected 00/FF pattern), false otherwise. 972 */ 973 static bool link_detect_evaluate_edid_header(uint8_t edid_header[8]) 974 { 975 int edid_header_score = 0; 976 int i; 977 978 for (i = 0; i < 8; ++i) 979 edid_header_score += edid_header[i] == ((i == 0 || i == 7) ? 0x00 : 0xff); 980 981 return edid_header_score >= 6; 982 } 983 984 /** 985 * link_detect_ddc_probe() - Probe the DDC to see if a display is connected. 986 * 987 * Detect whether a display is connected to DDC without reading full EDID. 988 * Reads only the EDID header (the first 8 bytes of EDID) from DDC and 989 * evaluates whether that matches. 990 * 991 * @link: DC link whose DDC/I2C is probed for the EDID header. 992 * 993 * Return: true if the EDID header was read and passes validation, 994 * false otherwise. 995 */ 996 static bool link_detect_ddc_probe(struct dc_link *link) 997 { 998 enum signal_type signal = link_detect_sink_signal_type(link, DETECT_REASON_HPD); 999 enum ddc_transaction_type transaction_type = get_ddc_transaction_type(signal); 1000 uint8_t edid_header[8] = {0}; 1001 uint8_t zero = 0; 1002 bool ddc_probed; 1003 1004 if (!link->ddc) 1005 return false; 1006 1007 if (link->dc->hwss.prepare_ddc) 1008 link->dc->hwss.prepare_ddc(link); 1009 1010 set_ddc_transaction_type(link->ddc, transaction_type); 1011 1012 ddc_probed = link_query_ddc_data(link->ddc, 0x50, &zero, 1, edid_header, sizeof(edid_header)); 1013 1014 if (!ddc_probed) 1015 return false; 1016 1017 if (!link_detect_evaluate_edid_header(edid_header)) 1018 return false; 1019 1020 return true; 1021 } 1022 1023 /** 1024 * link_detect_dac_load_detect() - Performs DAC load detection. 1025 * 1026 * Load detection can be used to detect the presence of an 1027 * analog display when we can't read DDC. This causes a visible 1028 * visual glitch so it should be used sparingly. 1029 * 1030 * @link: DC link to test using the DAC load-detect path. 1031 * 1032 * Return: true if the VBIOS load-detect call reports OK, false 1033 * otherwise. 1034 */ 1035 static bool link_detect_dac_load_detect(struct dc_link *link) 1036 { 1037 if (!link->dc->hwss.dac_load_detect) 1038 return false; 1039 1040 return link->dc->hwss.dac_load_detect(link); 1041 } 1042 1043 /* 1044 * detect_link_and_local_sink() - Detect if a sink is attached to a given link 1045 * 1046 * link->local_sink is created or destroyed as needed. 1047 * 1048 * This does not create remote sinks. 1049 */ 1050 static bool detect_link_and_local_sink(struct dc_link *link, 1051 enum dc_detect_reason reason) 1052 { 1053 struct dc_sink_init_data sink_init_data = { 0 }; 1054 struct display_sink_capability sink_caps = { 0 }; 1055 uint32_t i; 1056 bool converter_disable_audio = false; 1057 struct audio_support *aud_support = &link->dc->res_pool->audio_support; 1058 bool same_edid = false; 1059 enum dc_edid_status edid_status; 1060 struct dc_context *dc_ctx = link->ctx; 1061 struct dc *dc = dc_ctx->dc; 1062 struct dc_sink *sink = NULL; 1063 struct dc_sink *prev_sink = NULL; 1064 struct dpcd_caps prev_dpcd_caps; 1065 enum dc_connection_type new_connection_type = dc_connection_none; 1066 const uint32_t post_oui_delay = 30; // 30ms 1067 1068 if (dc_is_virtual_signal(link->connector_signal)) 1069 return false; 1070 1071 if (((link->connector_signal == SIGNAL_TYPE_LVDS || 1072 link->connector_signal == SIGNAL_TYPE_EDP) && 1073 (!link->dc->config.allow_edp_hotplug_detection)) && 1074 link->local_sink) { 1075 // need to re-write OUI and brightness in resume case 1076 if (link->connector_signal == SIGNAL_TYPE_EDP && 1077 (link->dpcd_sink_ext_caps.bits.oled == 1)) { 1078 dpcd_set_source_specific_data(link); 1079 msleep(post_oui_delay); 1080 set_default_brightness_aux(link); 1081 } 1082 1083 return true; 1084 } 1085 1086 if (!link_detect_connection_type(link, &new_connection_type)) { 1087 BREAK_TO_DEBUGGER(); 1088 return false; 1089 } 1090 1091 prev_sink = link->local_sink; 1092 if (prev_sink) { 1093 dc_sink_retain(prev_sink); 1094 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps)); 1095 } 1096 1097 link_disconnect_sink(link); 1098 if (new_connection_type != dc_connection_none) { 1099 link->type = new_connection_type; 1100 link->link_state_valid = false; 1101 1102 /* From Disconnected-to-Connected. */ 1103 switch (link->connector_signal) { 1104 case SIGNAL_TYPE_HDMI_FRL: 1105 case SIGNAL_TYPE_HDMI_TYPE_A: { 1106 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1107 if (aud_support->hdmi_audio_native) 1108 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 1109 else 1110 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1111 break; 1112 } 1113 1114 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 1115 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1116 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1117 break; 1118 } 1119 1120 case SIGNAL_TYPE_DVI_DUAL_LINK: { 1121 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1122 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1123 break; 1124 } 1125 1126 case SIGNAL_TYPE_RGB: { 1127 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1128 sink_caps.signal = SIGNAL_TYPE_RGB; 1129 break; 1130 } 1131 1132 case SIGNAL_TYPE_LVDS: { 1133 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 1134 sink_caps.signal = SIGNAL_TYPE_LVDS; 1135 break; 1136 } 1137 1138 case SIGNAL_TYPE_EDP: { 1139 detect_edp_sink_caps(link); 1140 read_current_link_settings_on_detect(link); 1141 1142 /* Disable power sequence on MIPI panel + converter 1143 */ 1144 if (dc->config.enable_mipi_converter_optimization && 1145 dc_ctx->dce_version == DCN_VERSION_3_01 && 1146 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 && 1147 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580, 1148 sizeof(link->dpcd_caps.branch_dev_name)) == 0) { 1149 dc->config.edp_no_power_sequencing = true; 1150 1151 if (!link->dpcd_caps.set_power_state_capable_edp) 1152 link->wa_flags.dp_keep_receiver_powered = true; 1153 } 1154 1155 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 1156 sink_caps.signal = SIGNAL_TYPE_EDP; 1157 break; 1158 } 1159 1160 case SIGNAL_TYPE_DISPLAY_PORT: { 1161 1162 /* wa HPD high coming too early*/ 1163 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 1164 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { 1165 1166 /* if alt mode times out, return false */ 1167 if (!wait_for_entering_dp_alt_mode(link)) 1168 return false; 1169 } 1170 1171 if (!detect_dp(link, &sink_caps, reason)) { 1172 1173 if (prev_sink) 1174 dc_sink_release(prev_sink); 1175 return false; 1176 } 1177 1178 /* Active SST downstream branch device unplug*/ 1179 if (link->type == dc_connection_sst_branch && 1180 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) { 1181 if (prev_sink) 1182 /* Downstream unplug */ 1183 dc_sink_release(prev_sink); 1184 return true; 1185 } 1186 1187 /* disable audio for non DP to HDMI active sst converter */ 1188 if (link->type == dc_connection_sst_branch && 1189 is_dp_active_dongle(link) && 1190 (link->dpcd_caps.dongle_type != 1191 DISPLAY_DONGLE_DP_HDMI_CONVERTER)) 1192 converter_disable_audio = true; 1193 1194 /* limited link rate to HBR3 for DPIA until we implement USB4 V2 */ 1195 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && 1196 link->reported_link_cap.link_rate > LINK_RATE_HIGH3) 1197 link->reported_link_cap.link_rate = LINK_RATE_HIGH3; 1198 1199 if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling 1200 && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc 1201 && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support) { 1202 if (link_dpia_enable_usb4_dp_bw_alloc_mode(link) == false) 1203 link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc = false; 1204 } 1205 break; 1206 } 1207 1208 default: 1209 DC_ERROR("Invalid connector type! signal:%d\n", 1210 link->connector_signal); 1211 if (prev_sink) 1212 dc_sink_release(prev_sink); 1213 return false; 1214 } /* switch() */ 1215 1216 if (link->dpcd_caps.sink_count.bits.SINK_COUNT) 1217 link->dpcd_sink_count = 1218 link->dpcd_caps.sink_count.bits.SINK_COUNT; 1219 else 1220 link->dpcd_sink_count = 1; 1221 1222 set_ddc_transaction_type(link->ddc, 1223 sink_caps.transaction_type); 1224 1225 link->aux_mode = 1226 link_is_in_aux_transaction_mode(link->ddc); 1227 1228 sink_init_data.link = link; 1229 sink_init_data.sink_signal = sink_caps.signal; 1230 1231 sink = dc_sink_create(&sink_init_data); 1232 if (!sink) { 1233 DC_ERROR("Failed to create sink!\n"); 1234 if (prev_sink) 1235 dc_sink_release(prev_sink); 1236 return false; 1237 } 1238 1239 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; 1240 sink->converter_disable_audio = converter_disable_audio; 1241 1242 /* dc_sink_create returns a new reference */ 1243 link->local_sink = sink; 1244 1245 edid_status = dm_helpers_read_local_edid(link->ctx, 1246 link, sink); 1247 1248 switch (edid_status) { 1249 case EDID_BAD_CHECKSUM: 1250 DC_LOG_ERROR("EDID checksum invalid.\n"); 1251 break; 1252 case EDID_PARTIAL_VALID: 1253 DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n"); 1254 break; 1255 case EDID_NO_RESPONSE: 1256 /* Analog connectors without EDID: 1257 * - old monitor that actually doesn't have EDID 1258 * - cheap DVI-A cable or adapter that doesn't connect DDC 1259 */ 1260 if (dc_connector_supports_analog(link->link_id.id)) { 1261 /* If we didn't already detect a display using 1262 * DAC load detection, we know it isn't connected. 1263 */ 1264 if (link->type != dc_connection_analog_load) { 1265 if (prev_sink) 1266 dc_sink_release(prev_sink); 1267 link_disconnect_sink(link); 1268 return false; 1269 } 1270 1271 LINK_INFO("link=%d, analog display detected without EDID\n", 1272 link->link_index); 1273 1274 link->type = dc_connection_analog_load; 1275 sink->edid_caps.analog = true; 1276 break; 1277 } 1278 1279 DC_LOG_ERROR("No EDID read.\n"); 1280 1281 /* 1282 * Abort detection for non-DP connectors if we have 1283 * no EDID 1284 * 1285 * DP needs to report as connected if HDP is high 1286 * even if we have no EDID in order to go to 1287 * fail-safe mode 1288 */ 1289 if (dc_is_hdmi_signal(link->connector_signal) || 1290 dc_is_dvi_signal(link->connector_signal)) { 1291 if (prev_sink) 1292 dc_sink_release(prev_sink); 1293 1294 return false; 1295 } 1296 1297 if (link->type == dc_connection_sst_branch && 1298 link->dpcd_caps.dongle_type == 1299 DISPLAY_DONGLE_DP_VGA_CONVERTER && 1300 reason == DETECT_REASON_HPDRX) { 1301 /* Abort detection for DP-VGA adapters when EDID 1302 * can't be read and detection reason is VGA-side 1303 * hotplug 1304 */ 1305 if (prev_sink) 1306 dc_sink_release(prev_sink); 1307 link_disconnect_sink(link); 1308 1309 return true; 1310 } 1311 1312 break; 1313 default: 1314 break; 1315 } 1316 1317 // Check if edid is the same 1318 if ((prev_sink) && 1319 (edid_status == EDID_THE_SAME || edid_status == EDID_OK)) 1320 same_edid = is_same_edid(&prev_sink->dc_edid, 1321 &sink->dc_edid); 1322 1323 if (sink->edid_caps.panel_patch.skip_scdc_overwrite) 1324 link->ctx->dc->debug.hdmi20_disable = true; 1325 1326 if (sink->edid_caps.panel_patch.remove_sink_ext_caps) 1327 link->dpcd_sink_ext_caps.raw = 0; 1328 1329 if (dc_is_hdmi_signal(link->connector_signal)) 1330 read_scdc_caps(link->ddc, link->local_sink); 1331 1332 if (dc_is_hdmi_signal(link->connector_signal) && dc->debug.enable_hdmi_idcc) { 1333 memset(&link->hdmi_cable_id, 0, sizeof(union hdmi_idcc_cable_id)); 1334 read_idcc_data(link->ddc, HDMI_IDCC_SCOPE_RW_CA, 1335 link->hdmi_cable_id.raw, 0, 4); 1336 } 1337 if (sink->edid_caps.rr_capable) 1338 hdmi_frl_write_read_request_enable(link->ddc); 1339 /* When FreeSync is toggled through OSD, 1340 * we see same EDID no matter what. Check MCCS caps 1341 * to see if we should update FreeSync caps now. 1342 */ 1343 dm_helpers_read_mccs_caps( 1344 link->ctx, 1345 link, 1346 sink); 1347 1348 if (prev_sink != NULL) { 1349 if (memcmp(&sink->mccs_caps, &prev_sink->mccs_caps, sizeof(struct mccs_caps))) 1350 same_edid = false; 1351 } 1352 1353 if (reason != DETECT_REASON_FALLBACK && dc_is_hdmi_signal(link->connector_signal) && 1354 link->link_enc->features.flags.bits.IS_HDMI_FRL_CAPABLE && sink->edid_caps.max_frl_rate != 0) { 1355 hdmi_frl_retrieve_link_cap(link, link->local_sink); 1356 } 1357 if (reason == DETECT_REASON_FALLBACK && sink->sink_signal == SIGNAL_TYPE_HDMI_FRL) 1358 same_edid = false; 1359 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 1360 sink_caps.transaction_type == 1361 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 1362 /* 1363 * TODO debug why certain monitors don't like 1364 * two link trainings 1365 */ 1366 query_hdcp_capability(sink->sink_signal, link); 1367 } else { 1368 // If edid is the same, then discard new sink and revert back to original sink 1369 if (same_edid) { 1370 link_disconnect_remap(prev_sink, link); 1371 sink = prev_sink; 1372 prev_sink = NULL; 1373 if (reason == DETECT_REASON_FALLBACK && sink->sink_signal == SIGNAL_TYPE_HDMI_FRL) 1374 sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 1375 } 1376 1377 if (!sink->edid_caps.analog) 1378 query_hdcp_capability(sink->sink_signal, link); 1379 } 1380 1381 /* DVI-I connector connected to analog display. */ 1382 if ((link->link_id.id == CONNECTOR_ID_DUAL_LINK_DVII || 1383 link->link_id.id == CONNECTOR_ID_SINGLE_LINK_DVII) && 1384 sink->edid_caps.analog) 1385 sink->sink_signal = SIGNAL_TYPE_RGB; 1386 1387 /* HDMI-DVI Dongle */ 1388 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && 1389 !sink->edid_caps.edid_hdmi) 1390 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1391 else if (dc_is_dvi_signal(sink->sink_signal) && 1392 dc_is_dvi_signal(link->connector_signal) && 1393 aud_support->hdmi_audio_native && 1394 sink->edid_caps.edid_hdmi) 1395 sink->sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; 1396 1397 if (link->local_sink && dc_is_dp_signal(sink_caps.signal)) 1398 dp_trace_init(link); 1399 1400 /* Connectivity log: detection */ 1401 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) { 1402 CONN_DATA_DETECT(link, 1403 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE], 1404 DC_EDID_BLOCK_SIZE, 1405 "%s: [Block %d] ", sink->edid_caps.display_name, i); 1406 } 1407 1408 DC_LOG_DETECTION_EDID_PARSER("%s: " 1409 "manufacturer_id = %X, " 1410 "product_id = %X, " 1411 "serial_number = %X, " 1412 "manufacture_week = %d, " 1413 "manufacture_year = %d, " 1414 "display_name = %s, " 1415 "speaker_flag = %d, " 1416 "audio_mode_count = %d\n", 1417 __func__, 1418 sink->edid_caps.manufacturer_id, 1419 sink->edid_caps.product_id, 1420 sink->edid_caps.serial_number, 1421 sink->edid_caps.manufacture_week, 1422 sink->edid_caps.manufacture_year, 1423 sink->edid_caps.display_name, 1424 sink->edid_caps.speaker_flags, 1425 sink->edid_caps.audio_mode_count); 1426 1427 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) { 1428 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, " 1429 "format_code = %d, " 1430 "channel_count = %d, " 1431 "sample_rate = %d, " 1432 "sample_size = %d\n", 1433 __func__, 1434 i, 1435 sink->edid_caps.audio_modes[i].format_code, 1436 sink->edid_caps.audio_modes[i].channel_count, 1437 sink->edid_caps.audio_modes[i].sample_rate, 1438 sink->edid_caps.audio_modes[i].sample_size); 1439 } 1440 1441 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1442 // Init dc_panel_config by HW config 1443 if (dc_ctx->dc->res_pool->funcs->get_panel_config_defaults) 1444 dc_ctx->dc->res_pool->funcs->get_panel_config_defaults(&link->panel_config); 1445 // Pickup base DM settings 1446 dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink); 1447 // Override dc_panel_config if system has specific settings 1448 dm_helpers_override_panel_settings(dc_ctx, link); 1449 1450 //sink only can use supported link rate table, we are foreced to enable it 1451 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN) 1452 link->panel_config.ilr.optimize_edp_link_rate = true; 1453 link->reported_link_cap.link_rate = get_max_edp_link_rate(link); 1454 } 1455 1456 } else { 1457 /* From Connected-to-Disconnected. */ 1458 link->type = dc_connection_none; 1459 sink_caps.signal = SIGNAL_TYPE_NONE; 1460 memset(&link->hdcp_caps, 0, sizeof(struct hdcp_caps)); 1461 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk 1462 * is not cleared. If we emulate a DP signal on this connection, it thinks 1463 * the dongle is still there and limits the number of modes we can emulate. 1464 * Clear dongle_max_pix_clk on disconnect to fix this 1465 */ 1466 link->dongle_max_pix_clk = 0; 1467 1468 dc_link_clear_dprx_states(link); 1469 dp_trace_reset(link); 1470 } 1471 1472 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n", 1473 link->link_index, sink, 1474 (sink_caps.signal == 1475 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"), 1476 prev_sink, same_edid); 1477 1478 if (prev_sink) 1479 dc_sink_release(prev_sink); 1480 1481 return true; 1482 } 1483 1484 /** 1485 * link_detect_connection_type_analog() - Determines if an analog sink is connected. 1486 * 1487 * @link: DC link to evaluate (must support analog signalling). 1488 * @type: Updated with the detected connection type: 1489 * dc_connection_single (analog via DDC), 1490 * dc_connection_analog_load (via load-detect), 1491 * or dc_connection_none. 1492 * 1493 * Return: true if detection completed. 1494 */ 1495 static bool link_detect_connection_type_analog(struct dc_link *link, enum dc_connection_type *type) 1496 { 1497 /* Don't care about connectors that don't support an analog signal. */ 1498 ASSERT(dc_connector_supports_analog(link->link_id.id)); 1499 1500 if (link_detect_ddc_probe(link)) { 1501 *type = dc_connection_single; 1502 return true; 1503 } 1504 1505 if (link_detect_dac_load_detect(link)) { 1506 *type = dc_connection_analog_load; 1507 return true; 1508 } 1509 1510 *type = dc_connection_none; 1511 return true; 1512 } 1513 1514 /* 1515 * link_detect_connection_type() - Determine if there is a sink connected 1516 * 1517 * @type: Returned connection type 1518 * Does not detect downstream devices, such as MST sinks 1519 * or display connected through active dongles 1520 */ 1521 bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type) 1522 { 1523 if (link->connector_signal == SIGNAL_TYPE_LVDS) { 1524 *type = dc_connection_single; 1525 return true; 1526 } 1527 1528 /* Ignore the HPD pin (if any) for analog connectors. 1529 * Instead rely on DDC and DAC. 1530 * 1531 * - VGA connectors don't have any HPD at all. 1532 * - Some DVI-A cables don't connect the HPD pin. 1533 * - Some DVI-A cables pull up the HPD pin. 1534 * (So it's high even when no display is connected.) 1535 */ 1536 if (dc_connector_supports_analog(link->link_id.id)) 1537 return link_detect_connection_type_analog(link, type); 1538 1539 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1540 /*in case it is not on*/ 1541 if (!link->dc->config.edp_no_power_sequencing) 1542 link->dc->hwss.edp_power_control(link, true); 1543 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 1544 } 1545 1546 /* Link may not have physical HPD pin. */ 1547 if (link->ep_type != DISPLAY_ENDPOINT_PHY) { 1548 if (link->is_hpd_pending || !dpia_query_hpd_status(link)) 1549 *type = dc_connection_none; 1550 else 1551 *type = dc_connection_single; 1552 1553 return true; 1554 } 1555 1556 1557 if (link_get_hpd_state(link)) { 1558 *type = dc_connection_single; 1559 /* TODO: need to do the actual detection */ 1560 } else { 1561 *type = dc_connection_none; 1562 if (link->connector_signal == SIGNAL_TYPE_EDP) { 1563 /* eDP is not connected, power down it */ 1564 if (!link->dc->config.edp_no_power_sequencing) 1565 link->dc->hwss.edp_power_control(link, false); 1566 } 1567 } 1568 1569 return true; 1570 } 1571 1572 bool link_detect(struct dc_link *link, enum dc_detect_reason reason) 1573 { 1574 bool is_local_sink_detect_success; 1575 bool is_delegated_to_mst_top_mgr = false; 1576 enum dc_connection_type pre_link_type = link->type; 1577 1578 is_local_sink_detect_success = detect_link_and_local_sink(link, reason); 1579 1580 if (is_local_sink_detect_success && link->local_sink) { 1581 verify_link_capability(link, reason); 1582 } 1583 1584 DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__, 1585 link->link_index, is_local_sink_detect_success, pre_link_type, link->type); 1586 1587 if (is_local_sink_detect_success && link->local_sink && 1588 dc_is_dp_signal(link->local_sink->sink_signal) && 1589 link->dpcd_caps.is_mst_capable) 1590 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason); 1591 1592 if (pre_link_type == dc_connection_mst_branch && 1593 link->type != dc_connection_mst_branch) 1594 is_delegated_to_mst_top_mgr = link_reset_cur_dp_mst_topology(link); 1595 1596 return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr; 1597 } 1598 1599 void link_clear_dprx_states(struct dc_link *link) 1600 { 1601 memset(&link->dprx_states, 0, sizeof(link->dprx_states)); 1602 } 1603 1604 bool link_is_hdcp14(struct dc_link *link, enum signal_type signal) 1605 { 1606 bool ret = false; 1607 1608 switch (signal) { 1609 case SIGNAL_TYPE_DISPLAY_PORT: 1610 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1611 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE; 1612 break; 1613 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1614 case SIGNAL_TYPE_DVI_DUAL_LINK: 1615 case SIGNAL_TYPE_HDMI_TYPE_A: 1616 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable, 1617 * we can poll for bksv but some displays have an issue with this. Since its so rare 1618 * for a display to not be 1.4 capable, this assumtion is ok 1619 */ 1620 ret = true; 1621 break; 1622 default: 1623 break; 1624 } 1625 return ret; 1626 } 1627 1628 bool link_is_hdcp22(struct dc_link *link, enum signal_type signal) 1629 { 1630 bool ret = false; 1631 1632 switch (signal) { 1633 case SIGNAL_TYPE_DISPLAY_PORT: 1634 case SIGNAL_TYPE_DISPLAY_PORT_MST: 1635 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE && 1636 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable && 1637 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0; 1638 break; 1639 case SIGNAL_TYPE_DVI_SINGLE_LINK: 1640 case SIGNAL_TYPE_DVI_DUAL_LINK: 1641 case SIGNAL_TYPE_HDMI_TYPE_A: 1642 case SIGNAL_TYPE_HDMI_FRL: 1643 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0; 1644 break; 1645 default: 1646 break; 1647 } 1648 1649 return ret; 1650 } 1651 1652 const struct dc_link_status *link_get_status(const struct dc_link *link) 1653 { 1654 return &link->link_status; 1655 } 1656 1657 1658 static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink *sink) 1659 { 1660 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) { 1661 BREAK_TO_DEBUGGER(); 1662 return false; 1663 } 1664 1665 dc_sink_retain(sink); 1666 1667 dc_link->remote_sinks[dc_link->sink_count] = sink; 1668 dc_link->sink_count++; 1669 1670 return true; 1671 } 1672 1673 struct dc_sink *link_add_remote_sink( 1674 struct dc_link *link, 1675 const uint8_t *edid, 1676 unsigned int len, 1677 struct dc_sink_init_data *init_data) 1678 { 1679 struct dc_sink *dc_sink; 1680 enum dc_edid_status edid_status; 1681 1682 if (len > DC_MAX_EDID_BUFFER_SIZE) { 1683 dm_error("Max EDID buffer size breached!\n"); 1684 return NULL; 1685 } 1686 1687 if (!init_data) { 1688 BREAK_TO_DEBUGGER(); 1689 return NULL; 1690 } 1691 1692 if (!init_data->link) { 1693 BREAK_TO_DEBUGGER(); 1694 return NULL; 1695 } 1696 1697 dc_sink = dc_sink_create(init_data); 1698 1699 if (!dc_sink) 1700 return NULL; 1701 1702 memmove(dc_sink->dc_edid.raw_edid, edid, len); 1703 dc_sink->dc_edid.length = len; 1704 1705 if (!link_add_remote_sink_helper( 1706 link, 1707 dc_sink)) 1708 goto fail_add_sink; 1709 1710 edid_status = dm_helpers_parse_edid_caps( 1711 link, 1712 &dc_sink->dc_edid, 1713 &dc_sink->edid_caps); 1714 1715 /* 1716 * Treat device as no EDID device if EDID 1717 * parsing fails 1718 */ 1719 if (edid_status != EDID_OK && edid_status != EDID_PARTIAL_VALID) { 1720 dc_sink->dc_edid.length = 0; 1721 dm_error("Bad EDID, status%d!\n", edid_status); 1722 } 1723 1724 return dc_sink; 1725 1726 fail_add_sink: 1727 dc_sink_release(dc_sink); 1728 return NULL; 1729 } 1730 1731 void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) 1732 { 1733 unsigned int i; 1734 1735 if (!link->sink_count) { 1736 BREAK_TO_DEBUGGER(); 1737 return; 1738 } 1739 1740 for (i = 0; i < link->sink_count; i++) { 1741 if (link->remote_sinks[i] == sink) { 1742 dc_sink_release(sink); 1743 link->remote_sinks[i] = NULL; 1744 1745 /* shrink array to remove empty place */ 1746 while (i < link->sink_count - 1) { 1747 link->remote_sinks[i] = link->remote_sinks[i+1]; 1748 i++; 1749 } 1750 link->remote_sinks[i] = NULL; 1751 link->sink_count--; 1752 return; 1753 } 1754 } 1755 } 1756