1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_HW_H
8 #define ATH12K_HW_H
9
10 #include <linux/mhi.h>
11 #include <linux/uuid.h>
12
13 #include "wmi.h"
14 #include "hal.h"
15
16 /* Target configuration defines */
17
18 /* Num VDEVS per radio */
19 #define TARGET_NUM_VDEVS (16 + 1)
20
21 #define TARGET_NUM_PEERS_PDEV_SINGLE (TARGET_NUM_STATIONS_SINGLE + \
22 TARGET_NUM_VDEVS)
23 #define TARGET_NUM_PEERS_PDEV_DBS (TARGET_NUM_STATIONS_DBS + \
24 TARGET_NUM_VDEVS)
25 #define TARGET_NUM_PEERS_PDEV_DBS_SBS (TARGET_NUM_STATIONS_DBS_SBS + \
26 TARGET_NUM_VDEVS)
27
28 /* Num of peers for Single Radio mode */
29 #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV_SINGLE)
30
31 /* Num of peers for DBS */
32 #define TARGET_NUM_PEERS_DBS (2 * TARGET_NUM_PEERS_PDEV_DBS)
33
34 /* Num of peers for DBS_SBS */
35 #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV_DBS_SBS)
36
37 /* Max num of stations for Single Radio mode */
38 #define TARGET_NUM_STATIONS_SINGLE 512
39
40 /* Max num of stations for DBS */
41 #define TARGET_NUM_STATIONS_DBS 128
42
43 /* Max num of stations for DBS_SBS */
44 #define TARGET_NUM_STATIONS_DBS_SBS 128
45
46 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x
47 #define TARGET_NUM_PEER_KEYS 2
48 #define TARGET_NUM_TIDS(x) (2 * TARGET_NUM_PEERS(x) + \
49 4 * TARGET_NUM_VDEVS + 8)
50
51 #define TARGET_AST_SKID_LIMIT 16
52 #define TARGET_NUM_OFFLD_PEERS 4
53 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
54
55 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
56 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
57 #define TARGET_RX_TIMEOUT_LO_PRI 100
58 #define TARGET_RX_TIMEOUT_HI_PRI 40
59
60 #define TARGET_DECAP_MODE_RAW 0
61 #define TARGET_DECAP_MODE_NATIVE_WIFI 1
62 #define TARGET_DECAP_MODE_ETH 2
63
64 #define TARGET_SCAN_MAX_PENDING_REQS 4
65 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
66 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
67 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
68 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
69 #define TARGET_NUM_MCAST_GROUPS 12
70 #define TARGET_NUM_MCAST_TABLE_ELEMS 64
71 #define TARGET_MCAST2UCAST_MODE 2
72 #define TARGET_TX_DBG_LOG_SIZE 1024
73 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
74 #define TARGET_VOW_CONFIG 0
75 #define TARGET_NUM_MSDU_DESC (2500)
76 #define TARGET_MAX_FRAG_ENTRIES 6
77 #define TARGET_MAX_BCN_OFFLD 16
78 #define TARGET_NUM_WDS_ENTRIES 32
79 #define TARGET_DMA_BURST_SIZE 1
80 #define TARGET_RX_BATCHMODE 1
81 #define TARGET_EMA_MAX_PROFILE_PERIOD 8
82
83 #define ATH12K_HW_DEFAULT_QUEUE 0
84 #define ATH12K_HW_MAX_QUEUES 4
85 #define ATH12K_QUEUE_LEN 4096
86
87 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4
88
89 #define ATH12K_FW_DIR "ath12k"
90
91 #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD"
92 #define ATH12K_BOARD_API2_FILE "board-2.bin"
93 #define ATH12K_DEFAULT_BOARD_FILE "board.bin"
94 #define ATH12K_DEFAULT_CAL_FILE "caldata.bin"
95 #define ATH12K_AMSS_FILE "amss.bin"
96 #define ATH12K_M3_FILE "m3.bin"
97 #define ATH12K_REGDB_FILE_NAME "regdb.bin"
98
99 #define ATH12K_PCIE_MAX_PAYLOAD_SIZE 128
100 #define ATH12K_IPQ5332_USERPD_ID 1
101
102 enum ath12k_hw_rate_cck {
103 ATH12K_HW_RATE_CCK_LP_11M = 0,
104 ATH12K_HW_RATE_CCK_LP_5_5M,
105 ATH12K_HW_RATE_CCK_LP_2M,
106 ATH12K_HW_RATE_CCK_LP_1M,
107 ATH12K_HW_RATE_CCK_SP_11M,
108 ATH12K_HW_RATE_CCK_SP_5_5M,
109 ATH12K_HW_RATE_CCK_SP_2M,
110 };
111
112 enum ath12k_hw_rate_ofdm {
113 ATH12K_HW_RATE_OFDM_48M = 0,
114 ATH12K_HW_RATE_OFDM_24M,
115 ATH12K_HW_RATE_OFDM_12M,
116 ATH12K_HW_RATE_OFDM_6M,
117 ATH12K_HW_RATE_OFDM_54M,
118 ATH12K_HW_RATE_OFDM_36M,
119 ATH12K_HW_RATE_OFDM_18M,
120 ATH12K_HW_RATE_OFDM_9M,
121 };
122
123 enum ath12k_bus {
124 ATH12K_BUS_PCI,
125 ATH12K_BUS_AHB,
126 };
127
128 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11
129
130 struct hal_rx_desc;
131 struct hal_tcl_data_cmd;
132 struct htt_rx_ring_tlv_filter;
133 enum hal_encrypt_type;
134
135 struct ath12k_hw_ring_mask {
136 u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX];
137 u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
138 u8 rx_mon_status[ATH12K_EXT_IRQ_GRP_NUM_MAX];
139 u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX];
140 u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX];
141 u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX];
142 u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX];
143 u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX];
144 u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
145 };
146
147 struct ath12k_hw_hal_params {
148 enum hal_rx_buf_return_buf_manager rx_buf_rbm;
149 u32 wbm2sw_cc_enable;
150 };
151
152 enum ath12k_m3_fw_loaders {
153 ath12k_m3_fw_loader_driver,
154 ath12k_m3_fw_loader_remoteproc,
155 };
156
157 struct ath12k_hw_params {
158 const char *name;
159 u16 hw_rev;
160
161 struct {
162 const char *dir;
163 size_t board_size;
164 size_t cal_offset;
165 enum ath12k_m3_fw_loaders m3_loader;
166 } fw;
167
168 u8 max_radios;
169 bool single_pdev_only:1;
170 u32 qmi_service_ins_id;
171 bool internal_sleep_clock:1;
172
173 const struct ath12k_hw_ops *hw_ops;
174 const struct ath12k_hw_ring_mask *ring_mask;
175 const struct ath12k_hw_regs *regs;
176
177 const struct ce_attr *host_ce_config;
178 u32 ce_count;
179 const struct ce_pipe_config *target_ce_config;
180 u32 target_ce_count;
181 const struct service_to_pipe *svc_to_ce_map;
182 u32 svc_to_ce_map_len;
183
184 const struct ath12k_hw_hal_params *hal_params;
185
186 bool rxdma1_enable:1;
187 int num_rxdma_per_pdev;
188 int num_rxdma_dst_ring;
189 bool rx_mac_buf_ring:1;
190 bool vdev_start_delay:1;
191
192 u16 interface_modes;
193 bool supports_monitor:1;
194
195 bool idle_ps:1;
196 bool download_calib:1;
197 bool supports_suspend:1;
198 bool tcl_ring_retry:1;
199 bool reoq_lut_support:1;
200 bool supports_shadow_regs:1;
201 bool supports_aspm:1;
202 bool current_cc_support:1;
203
204 u32 num_tcl_banks;
205 u32 max_tx_ring;
206
207 const struct mhi_controller_config *mhi_config;
208
209 void (*wmi_init)(struct ath12k_base *ab,
210 struct ath12k_wmi_resource_config_arg *config);
211
212 const struct hal_ops *hal_ops;
213
214 u64 qmi_cnss_feature_bitmap;
215
216 u32 rfkill_pin;
217 u32 rfkill_cfg;
218 u32 rfkill_on_level;
219
220 u32 rddm_size;
221
222 u8 def_num_link;
223 u16 max_mlo_peer;
224
225 u32 otp_board_id_register;
226
227 bool supports_sta_ps;
228
229 const guid_t *acpi_guid;
230 bool supports_dynamic_smps_6ghz;
231
232 u32 iova_mask;
233
234 const struct ce_ie_addr *ce_ie_addr;
235 const struct ce_remap *ce_remap;
236 u32 bdf_addr_offset;
237
238 /* setup REO queue, frag etc only for primary link peer */
239 bool dp_primary_link_only:1;
240 };
241
242 struct ath12k_hw_ops {
243 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
244 int (*mac_id_to_pdev_id)(const struct ath12k_hw_params *hw, int mac_id);
245 int (*mac_id_to_srng_id)(const struct ath12k_hw_params *hw, int mac_id);
246 int (*rxdma_ring_sel_config)(struct ath12k_base *ab);
247 u8 (*get_ring_selector)(struct sk_buff *skb);
248 bool (*dp_srng_is_tx_comp_ring)(int ring_num);
249 };
250
251 static inline
ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params * hw,int pdev_idx)252 int ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params *hw,
253 int pdev_idx)
254 {
255 if (hw->hw_ops->get_hw_mac_from_pdev_id)
256 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
257
258 return 0;
259 }
260
ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params * hw,int mac_id)261 static inline int ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params *hw,
262 int mac_id)
263 {
264 if (hw->hw_ops->mac_id_to_pdev_id)
265 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
266
267 return 0;
268 }
269
ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params * hw,int mac_id)270 static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw,
271 int mac_id)
272 {
273 if (hw->hw_ops->mac_id_to_srng_id)
274 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
275
276 return 0;
277 }
278
279 struct ath12k_fw_ie {
280 __le32 id;
281 __le32 len;
282 u8 data[];
283 };
284
285 enum ath12k_bd_ie_board_type {
286 ATH12K_BD_IE_BOARD_NAME = 0,
287 ATH12K_BD_IE_BOARD_DATA = 1,
288 };
289
290 enum ath12k_bd_ie_regdb_type {
291 ATH12K_BD_IE_REGDB_NAME = 0,
292 ATH12K_BD_IE_REGDB_DATA = 1,
293 };
294
295 enum ath12k_bd_ie_type {
296 /* contains sub IEs of enum ath12k_bd_ie_board_type */
297 ATH12K_BD_IE_BOARD = 0,
298 /* contains sub IEs of enum ath12k_bd_ie_regdb_type */
299 ATH12K_BD_IE_REGDB = 1,
300 };
301
302 struct ath12k_hw_regs {
303 u32 hal_tcl1_ring_id;
304 u32 hal_tcl1_ring_misc;
305 u32 hal_tcl1_ring_tp_addr_lsb;
306 u32 hal_tcl1_ring_tp_addr_msb;
307 u32 hal_tcl1_ring_consumer_int_setup_ix0;
308 u32 hal_tcl1_ring_consumer_int_setup_ix1;
309 u32 hal_tcl1_ring_msi1_base_lsb;
310 u32 hal_tcl1_ring_msi1_base_msb;
311 u32 hal_tcl1_ring_msi1_data;
312 u32 hal_tcl_ring_base_lsb;
313 u32 hal_tcl1_ring_base_lsb;
314 u32 hal_tcl1_ring_base_msb;
315 u32 hal_tcl2_ring_base_lsb;
316
317 u32 hal_tcl_status_ring_base_lsb;
318
319 u32 hal_reo1_qdesc_addr;
320 u32 hal_reo1_qdesc_max_peerid;
321
322 u32 hal_wbm_idle_ring_base_lsb;
323 u32 hal_wbm_idle_ring_misc_addr;
324 u32 hal_wbm_r0_idle_list_cntl_addr;
325 u32 hal_wbm_r0_idle_list_size_addr;
326 u32 hal_wbm_scattered_ring_base_lsb;
327 u32 hal_wbm_scattered_ring_base_msb;
328 u32 hal_wbm_scattered_desc_head_info_ix0;
329 u32 hal_wbm_scattered_desc_head_info_ix1;
330 u32 hal_wbm_scattered_desc_tail_info_ix0;
331 u32 hal_wbm_scattered_desc_tail_info_ix1;
332 u32 hal_wbm_scattered_desc_ptr_hp_addr;
333
334 u32 hal_wbm_sw_release_ring_base_lsb;
335 u32 hal_wbm_sw1_release_ring_base_lsb;
336 u32 hal_wbm0_release_ring_base_lsb;
337 u32 hal_wbm1_release_ring_base_lsb;
338
339 u32 pcie_qserdes_sysclk_en_sel;
340 u32 pcie_pcs_osc_dtct_config_base;
341
342 u32 hal_umac_ce0_src_reg_base;
343 u32 hal_umac_ce0_dest_reg_base;
344 u32 hal_umac_ce1_src_reg_base;
345 u32 hal_umac_ce1_dest_reg_base;
346
347 u32 hal_ppe_rel_ring_base;
348
349 u32 hal_reo2_ring_base;
350 u32 hal_reo1_misc_ctrl_addr;
351 u32 hal_reo1_sw_cookie_cfg0;
352 u32 hal_reo1_sw_cookie_cfg1;
353 u32 hal_reo1_qdesc_lut_base0;
354 u32 hal_reo1_qdesc_lut_base1;
355 u32 hal_reo1_ring_base_lsb;
356 u32 hal_reo1_ring_base_msb;
357 u32 hal_reo1_ring_id;
358 u32 hal_reo1_ring_misc;
359 u32 hal_reo1_ring_hp_addr_lsb;
360 u32 hal_reo1_ring_hp_addr_msb;
361 u32 hal_reo1_ring_producer_int_setup;
362 u32 hal_reo1_ring_msi1_base_lsb;
363 u32 hal_reo1_ring_msi1_base_msb;
364 u32 hal_reo1_ring_msi1_data;
365 u32 hal_reo1_aging_thres_ix0;
366 u32 hal_reo1_aging_thres_ix1;
367 u32 hal_reo1_aging_thres_ix2;
368 u32 hal_reo1_aging_thres_ix3;
369
370 u32 hal_reo2_sw0_ring_base;
371
372 u32 hal_sw2reo_ring_base;
373 u32 hal_sw2reo1_ring_base;
374
375 u32 hal_reo_cmd_ring_base;
376
377 u32 hal_reo_status_ring_base;
378
379 u32 gcc_gcc_pcie_hot_rst;
380 };
381
ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type)382 static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type)
383 {
384 switch (type) {
385 case ATH12K_BD_IE_BOARD:
386 return "board data";
387 case ATH12K_BD_IE_REGDB:
388 return "regdb data";
389 }
390
391 return "unknown";
392 }
393
394 int ath12k_hw_init(struct ath12k_base *ab);
395
396 #endif
397