1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6
7 #include <linux/ptp_clock_kernel.h>
8 #include <linux/timecounter.h>
9 #include <linux/bitfield.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/phylink.h>
13 #include <linux/dim.h>
14 #include <net/ip.h>
15
16 #define WX_NCSI_SUP 0x8000
17 #define WX_NCSI_MASK 0x8000
18 #define WX_WOL_SUP 0x4000
19 #define WX_WOL_MASK 0x4000
20
21 /* MSI-X capability fields masks */
22 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
23 #define WX_PCI_LINK_STATUS 0xB2
24 #define WX_MAX_PF_MACVLANS 15
25 #define WX_MAX_VF_MC_ENTRIES 30
26
27 /**************** Global Registers ****************************/
28 #define WX_VF_REG_OFFSET(_v) FIELD_GET(GENMASK(15, 5), (_v))
29 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))
30
31 /* chip control Registers */
32 #define WX_MIS_PWR 0x10000
33 #define WX_MIS_RST 0x1000C
34 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
35 #define WX_MIS_RST_SW_RST BIT(0)
36 #define WX_MIS_ST 0x10028
37 #define WX_MIS_ST_MNG_INIT_DN BIT(0)
38 #define WX_MIS_SWSM 0x1002C
39 #define WX_MIS_SWSM_SMBI BIT(0)
40 #define WX_MIS_RST_ST 0x10030
41 #define WX_MIS_RST_ST_RST_INI_SHIFT 8
42 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
43
44 /* FMGR Registers */
45 #define WX_SPI_CMD 0x10104
46 #define WX_SPI_CMD_READ_DWORD 0x1
47 #define WX_SPI_CLK_DIV 0x3
48 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
49 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
50 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
51 #define WX_SPI_DATA 0x10108
52 #define WX_SPI_DATA_BYPASS BIT(31)
53 #define WX_SPI_DATA_OP_DONE BIT(0)
54 #define WX_SPI_STATUS 0x1010C
55 #define WX_SPI_STATUS_OPDONE BIT(0)
56 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
57 #define WX_SPI_ILDR_STATUS 0x10120
58
59 /* Sensors for PVT(Process Voltage Temperature) */
60 #define WX_TS_EN 0x10304
61 #define WX_TS_EN_ENA BIT(0)
62 #define WX_TS_ALARM_THRE 0x1030C
63 #define WX_TS_DALARM_THRE 0x10310
64 #define WX_TS_INT_EN 0x10314
65 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
66 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
67 #define WX_TS_ALARM_ST 0x10318
68 #define WX_TS_ALARM_ST_DALARM BIT(1)
69 #define WX_TS_ALARM_ST_ALARM BIT(0)
70
71 /* statistic */
72 #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C
73 #define WX_TX_BC_FRAMES_GOOD_L 0x11824
74 #define WX_TX_MC_FRAMES_GOOD_L 0x1182C
75 #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900
76 #define WX_RX_BC_FRAMES_GOOD_L 0x11918
77 #define WX_RX_MC_FRAMES_GOOD_L 0x11920
78 #define WX_RX_CRC_ERROR_FRAMES_L 0x11928
79 #define WX_RX_LEN_ERROR_FRAMES_L 0x11978
80 #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938
81 #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C
82 #define WX_MAC_LXONOFFRXC 0x11E0C
83
84 /*********************** Receive DMA registers **************************/
85 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4))
86 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4))
87 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4))
88 #define WX_RDM_DRP_PKT 0x12500
89 #define WX_RDM_PKT_CNT 0x12504
90 #define WX_RDM_BYTE_CNT_LSB 0x12508
91 #define WX_RDM_BMC2OS_CNT 0x12510
92
93 /************************* Port Registers ************************************/
94 /* port cfg Registers */
95 #define WX_CFG_PORT_CTL 0x14400
96 #define WX_CFG_PORT_CTL_PFRSTD BIT(14)
97 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
98 #define WX_CFG_PORT_CTL_QINQ BIT(2)
99 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
100 #define WX_CFG_PORT_ST 0x14404
101 #define WX_CFG_PORT_ST_LANID GENMASK(9, 8)
102 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
103 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
104
105 #define WX_CFG_PORT_CTL_NUM_VT_NONE 0
106 #define WX_CFG_PORT_CTL_NUM_VT_8 FIELD_PREP(GENMASK(13, 12), 1)
107 #define WX_CFG_PORT_CTL_NUM_VT_32 FIELD_PREP(GENMASK(13, 12), 2)
108 #define WX_CFG_PORT_CTL_NUM_VT_64 FIELD_PREP(GENMASK(13, 12), 3)
109
110 /* GPIO Registers */
111 #define WX_GPIO_DR 0x14800
112 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
113 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
114 #define WX_GPIO_DDR 0x14804
115 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
116 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
117 #define WX_GPIO_CTL 0x14808
118 #define WX_GPIO_INTEN 0x14830
119 #define WX_GPIO_INTEN_0 BIT(0)
120 #define WX_GPIO_INTEN_1 BIT(1)
121 #define WX_GPIO_INTMASK 0x14834
122 #define WX_GPIO_INTTYPE_LEVEL 0x14838
123 #define WX_GPIO_POLARITY 0x1483C
124 #define WX_GPIO_INTSTATUS 0x14844
125 #define WX_GPIO_EOI 0x1484C
126 #define WX_GPIO_EXT 0x14850
127
128 /*********************** Transmit DMA registers **************************/
129 /* transmit global control */
130 #define WX_TDM_CTL 0x18000
131 #define WX_TDM_VF_TE(_i) (0x18004 + ((_i) * 4))
132 #define WX_TDM_MAC_AS(_i) (0x18060 + ((_i) * 4))
133 #define WX_TDM_VLAN_AS(_i) (0x18070 + ((_i) * 4))
134 #define WX_TDM_VFTE_CLR(_i) (0x180A0 + ((_i) * 4))
135
136 /* TDM CTL BIT */
137 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
138 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
139 #define WX_TDM_RP_IDX 0x1820C
140 #define WX_TDM_PKT_CNT 0x18308
141 #define WX_TDM_BYTE_CNT_LSB 0x1830C
142 #define WX_TDM_OS2BMC_CNT 0x18314
143 #define WX_TDM_RP_RATE 0x18404
144
145 /***************************** RDB registers *********************************/
146 /* receive packet buffer */
147 #define WX_RDB_PB_CTL 0x19000
148 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
149 #define WX_RDB_PB_CTL_DISABLED BIT(0)
150 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
151 #define WX_RDB_PB_SZ_SHIFT 10
152 /* statistic */
153 #define WX_RDB_PFCMACDAL 0x19210
154 #define WX_RDB_PFCMACDAH 0x19214
155 #define WX_RDB_LXOFFTXC 0x19218
156 #define WX_RDB_LXONTXC 0x1921C
157 /* Flow Control Registers */
158 #define WX_RDB_RFCV 0x19200
159 #define WX_RDB_RFCL 0x19220
160 #define WX_RDB_RFCL_XONE BIT(31)
161 #define WX_RDB_RFCH 0x19260
162 #define WX_RDB_RFCH_XOFFE BIT(31)
163 #define WX_RDB_RFCRT 0x192A0
164 #define WX_RDB_RFCC 0x192A4
165 #define WX_RDB_RFCC_RFCE_802_3X BIT(3)
166 /* ring assignment */
167 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
168 #define WX_RDB_PL_CFG_L4HDR BIT(1)
169 #define WX_RDB_PL_CFG_L3HDR BIT(2)
170 #define WX_RDB_PL_CFG_L2HDR BIT(3)
171 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
172 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
173 #define WX_RDB_PL_CFG_RSS_EN BIT(24)
174 #define WX_RDB_PL_CFG_RSS_MASK GENMASK(23, 16)
175 #define WX_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4))
176 #define WX_RDB_RSSRK(_i) (0x19480 + ((_i) * 4))
177 #define WX_RDB_RA_CTL 0x194F4
178 #define WX_RDB_RA_CTL_MULTI_RSS BIT(0)
179 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
180 #define WX_RDB_RA_CTL_RSS_IPV4_TCP BIT(16)
181 #define WX_RDB_RA_CTL_RSS_IPV4 BIT(17)
182 #define WX_RDB_RA_CTL_RSS_IPV6 BIT(20)
183 #define WX_RDB_RA_CTL_RSS_IPV6_TCP BIT(21)
184 #define WX_RDB_RA_CTL_RSS_IPV4_UDP BIT(22)
185 #define WX_RDB_RA_CTL_RSS_IPV6_UDP BIT(23)
186 #define WX_RDB_RA_CTL_RSS_MASK GENMASK(23, 16)
187 #define WX_RDB_FDIR_MATCH 0x19558
188 #define WX_RDB_FDIR_MISS 0x1955C
189 /* VM RSS */
190 #define WX_RDB_VMRSSRK(_i, _p) (0x1A000 + ((_i) * 4) + ((_p) * 0x40))
191 #define WX_RDB_VMRSSTBL(_i, _p) (0x1B000 + ((_i) * 4) + ((_p) * 0x40))
192
193 /******************************* PSR Registers *******************************/
194 /* psr control */
195 #define WX_PSR_CTL 0x15000
196 #define WX_PSR_VM_CTL 0x151B0
197 /* Header split receive */
198 #define WX_PSR_CTL_SW_EN BIT(18)
199 #define WX_PSR_CTL_RSC_ACK BIT(17)
200 #define WX_PSR_CTL_RSC_DIS BIT(16)
201 #define WX_PSR_CTL_PCSD BIT(13)
202 #define WX_PSR_CTL_IPPCSE BIT(12)
203 #define WX_PSR_CTL_BAM BIT(10)
204 #define WX_PSR_CTL_UPE BIT(9)
205 #define WX_PSR_CTL_MPE BIT(8)
206 #define WX_PSR_CTL_MFE BIT(7)
207 #define WX_PSR_CTL_MO_SHIFT 5
208 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
209 #define WX_PSR_CTL_TPE BIT(4)
210 #define WX_PSR_MAX_SZ 0x15020
211 #define WX_PSR_VLAN_CTL 0x15088
212 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
213 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
214 /* EType Queue Filter */
215 #define WX_PSR_ETYPE_SWC(_i) (0x15128 + ((_i) * 4))
216 #define WX_PSR_ETYPE_SWC_FILTER_1588 3
217 #define WX_PSR_ETYPE_SWC_FILTER_EN BIT(31)
218 #define WX_PSR_ETYPE_SWC_1588 BIT(30)
219 /* 1588 */
220 #define WX_PSR_1588_MSG 0x15120
221 #define WX_PSR_1588_MSG_V1_SYNC FIELD_PREP(GENMASK(7, 0), 0)
222 #define WX_PSR_1588_MSG_V1_DELAY_REQ FIELD_PREP(GENMASK(7, 0), 1)
223 #define WX_PSR_1588_STMPL 0x151E8
224 #define WX_PSR_1588_STMPH 0x151A4
225 #define WX_PSR_1588_CTL 0x15188
226 #define WX_PSR_1588_CTL_ENABLED BIT(4)
227 #define WX_PSR_1588_CTL_TYPE_MASK GENMASK(3, 1)
228 #define WX_PSR_1588_CTL_TYPE_L4_V1 FIELD_PREP(GENMASK(3, 1), 1)
229 #define WX_PSR_1588_CTL_TYPE_EVENT_V2 FIELD_PREP(GENMASK(3, 1), 5)
230 #define WX_PSR_1588_CTL_VALID BIT(0)
231 /* mcasst/ucast overflow tbl */
232 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
233 #define WX_PSR_MC_TBL_REG(_i) FIELD_GET(GENMASK(11, 5), (_i))
234 #define WX_PSR_MC_TBL_BIT(_i) FIELD_GET(GENMASK(4, 0), (_i))
235 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
236 #define WX_PSR_VM_CTL_REPLEN BIT(30) /* replication enabled */
237 #define WX_PSR_VM_CTL_POOL_MASK GENMASK(12, 7)
238
239 /* VM L2 contorl */
240 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
241 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
242 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
243 #define WX_PSR_VM_L2CTL_VPE BIT(7) /* vlan promiscuous mode */
244 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
245 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
246 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
247 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
248 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
249
250 /* Management */
251 #define WX_PSR_MNG_FLEX_SEL 0x1582C
252 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
253 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
254 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
255 #define WX_PSR_LAN_FLEX_SEL 0x15B8C
256 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
257 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
258 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
259
260 #define WX_PSR_WKUP_CTL 0x15B80
261 /* Wake Up Filter Control Bit */
262 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
263
264 /* vlan tbl */
265 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
266
267 /* mac switcher */
268 #define WX_PSR_MAC_SWC_AD_L 0x16200
269 #define WX_PSR_MAC_SWC_AD_H 0x16204
270 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
271 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
272 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
273 #define WX_PSR_MAC_SWC_VM_L 0x16208
274 #define WX_PSR_MAC_SWC_VM_H 0x1620C
275 #define WX_PSR_MAC_SWC_IDX 0x16210
276 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
277
278 /* vlan switch */
279 #define WX_PSR_VLAN_SWC 0x16220
280 #define WX_PSR_VLAN_SWC_VM_L 0x16224
281 #define WX_PSR_VLAN_SWC_VM_H 0x16228
282 #define WX_PSR_VLAN_SWC_VM(_i) (0x16224 + ((_i) * 4))
283 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
284 /* VLAN pool filtering masks */
285 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
286 #define WX_PSR_VLAN_SWC_ENTRIES 64
287 #define WX_PSR_VLAN_SWC_VLANID_MASK GENMASK(11, 0)
288
289 /********************************* RSEC **************************************/
290 /* general rsec */
291 #define WX_RSC_CTL 0x17000
292 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
293 #define WX_RSC_CTL_CRC_STRIP BIT(2)
294 #define WX_RSC_CTL_RX_DIS BIT(1)
295 #define WX_RSC_ST 0x17004
296 #define WX_RSC_ST_RSEC_RDY BIT(0)
297
298 /*********************** Transmit DMA registers **************************/
299 /* transmit global control */
300 #define WX_TDM_ETYPE_AS(_i) (0x18058 + ((_i) * 4))
301 #define WX_TDM_VLAN_INS(_i) (0x18100 + ((_i) * 4))
302 /* Per VF Port VLAN insertion rules */
303 #define WX_TDM_VLAN_INS_VLANA_DEFAULT BIT(30) /* Always use default VLAN*/
304
305 /****************************** TDB ******************************************/
306 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
307 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
308
309 /****************************** TSEC *****************************************/
310 /* Security Control Registers */
311 #define WX_TSC_CTL 0x1D000
312 #define WX_TSC_CTL_TX_DIS BIT(1)
313 #define WX_TSC_CTL_TSEC_DIS BIT(0)
314 #define WX_TSC_ST 0x1D004
315 #define WX_TSC_ST_SECTX_RDY BIT(0)
316 #define WX_TSC_BUF_AE 0x1D00C
317 #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
318 /* 1588 */
319 #define WX_TSC_1588_CTL 0x11F00
320 #define WX_TSC_1588_CTL_ENABLED BIT(4)
321 #define WX_TSC_1588_CTL_VALID BIT(0)
322 #define WX_TSC_1588_STMPL 0x11F04
323 #define WX_TSC_1588_STMPH 0x11F08
324 #define WX_TSC_1588_SYSTIML 0x11F0C
325 #define WX_TSC_1588_SYSTIMH 0x11F10
326 #define WX_TSC_1588_INC 0x11F14
327 #define WX_TSC_1588_INT_ST 0x11F20
328 #define WX_TSC_1588_INT_ST_TT1 BIT(5)
329 #define WX_TSC_1588_INT_EN 0x11F24
330 #define WX_TSC_1588_INT_EN_TT1 BIT(5)
331 #define WX_TSC_1588_AUX_CTL 0x11F28
332 #define WX_TSC_1588_AUX_CTL_EN_TS0 BIT(8)
333 #define WX_TSC_1588_AUX_CTL_EN_TT1 BIT(2)
334 #define WX_TSC_1588_AUX_CTL_PLSG BIT(1)
335 #define WX_TSC_1588_AUX_CTL_EN_TT0 BIT(0)
336 #define WX_TSC_1588_TRGT_L(i) (0x11F2C + ((i) * 8)) /* [0,1] */
337 #define WX_TSC_1588_TRGT_H(i) (0x11F30 + ((i) * 8)) /* [0,1] */
338 #define WX_TSC_1588_SDP(i) (0x11F5C + ((i) * 4)) /* [0,3] */
339 #define WX_TSC_1588_SDP_OUT_LEVEL_H FIELD_PREP(BIT(4), 0)
340 #define WX_TSC_1588_SDP_OUT_LEVEL_L FIELD_PREP(BIT(4), 1)
341 #define WX_TSC_1588_SDP_FUN_SEL_MASK GENMASK(2, 0)
342 #define WX_TSC_1588_SDP_FUN_SEL_TT0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 1)
343 #define WX_TSC_1588_SDP_FUN_SEL_TS0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 5)
344
345 /************************************** MNG ********************************/
346 #define WX_MNG_SWFW_SYNC 0x1E008
347 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
348 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
349 #define WX_MNG_MBOX 0x1E100
350 #define WX_MNG_MBOX_CTL 0x1E044
351 #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
352 #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
353 #define WX_MNG_BMC2OS_CNT 0x1E090
354 #define WX_MNG_OS2BMC_CNT 0x1E094
355 #define WX_SW2FW_MBOX_CMD 0x1E0A0
356 #define WX_SW2FW_MBOX_CMD_VLD BIT(31)
357 #define WX_SW2FW_MBOX 0x1E200
358 #define WX_FW2SW_MBOX 0x1E300
359
360 /************************************* ETH MAC *****************************/
361 #define WX_MAC_TX_CFG 0x11000
362 #define WX_MAC_TX_CFG_TE BIT(0)
363 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
364 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
365 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
366 #define WX_MAC_RX_CFG 0x11004
367 #define WX_MAC_RX_CFG_RE BIT(0)
368 #define WX_MAC_RX_CFG_JE BIT(8)
369 #define WX_MAC_PKT_FLT 0x11008
370 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
371 #define WX_MAC_WDG_TIMEOUT 0x1100C
372 #define WX_MAC_RX_FLOW_CTRL 0x11090
373 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
374
375 #define WX_MAC_WDG_TIMEOUT_WTO_MASK GENMASK(3, 0)
376 #define WX_MAC_WDG_TIMEOUT_WTO_DELTA 2
377 /* MDIO Registers */
378 #define WX_MSCA 0x11200
379 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
380 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
381 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
382 #define WX_MSCC 0x11204
383 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
384
385 enum WX_MSCA_CMD_value {
386 WX_MSCA_CMD_RSV = 0,
387 WX_MSCA_CMD_WRITE,
388 WX_MSCA_CMD_POST_READ,
389 WX_MSCA_CMD_READ,
390 };
391
392 #define WX_MSCC_SADDR BIT(18)
393 #define WX_MSCC_BUSY BIT(22)
394 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
395 #define WX_MDIO_CLAUSE_SELECT 0x11220
396 #define WX_MMC_CONTROL 0x11800
397 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
398
399 /********************************* BAR registers ***************************/
400 /* Interrupt Registers */
401 #define WX_BME_CTL 0x12020
402 #define WX_PX_MISC_IC 0x100
403 #define WX_PX_MISC_ICS 0x104
404 #define WX_PX_MISC_IEN 0x108
405 #define WX_PX_INTA 0x110
406 #define WX_PX_GPIE 0x118
407 #define WX_PX_GPIE_MODEL BIT(0)
408 #define WX_PX_IC(_i) (0x120 + (_i) * 4)
409 #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
410 #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
411 #define WX_PX_ISB_ADDR_L 0x160
412 #define WX_PX_ISB_ADDR_H 0x164
413 #define WX_PX_TRANSACTION_PENDING 0x168
414 #define WX_PX_ITRSEL 0x180
415 #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
416 #define WX_PX_ITR_CNT_WDIS BIT(31)
417 #define WX_PX_MISC_IVAR 0x4FC
418 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
419
420 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
421 #define WX_7K_ITR 595
422 #define WX_12K_ITR 336
423 #define WX_20K_ITR 200
424 #define WX_SP_MAX_EITR 0x00000FF8U
425 #define WX_AML_MAX_EITR 0x00000FFFU
426 #define WX_EM_MAX_EITR 0x00007FFCU
427
428 /* transmit DMA Registers */
429 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
430 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
431 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
432 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
433 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
434 /* Transmit Config masks */
435 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
436 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
437 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
438 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
439 #define WX_PX_TR_CFG_THRE_SHIFT 8
440
441 /* Receive DMA Registers */
442 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
443 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
444 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
445 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
446 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
447 #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40))
448 /* PX_RR_CFG bit definitions */
449 #define WX_PX_RR_CFG_VLAN BIT(31)
450 #define WX_PX_RR_CFG_DROP_EN BIT(30)
451 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
452 #define WX_PX_RR_CFG_RR_THER_SHIFT 16
453 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
454 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
455 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
456 * + at bit 8 offset (<< 12)
457 * = (<< 6)
458 */
459 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
460 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
461 #define WX_PX_RR_CFG_RR_EN BIT(0)
462
463 /* Number of 80 microseconds we wait for PCI Express master disable */
464 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
465
466 #define WX_RSS_64Q_MASK 0x3F
467 #define WX_RSS_8Q_MASK 0x7
468 #define WX_RSS_4Q_MASK 0x3
469 #define WX_RSS_2Q_MASK 0x1
470 #define WX_RSS_DISABLED_MASK 0x0
471
472 #define WX_VMDQ_4Q_MASK 0x7C
473 #define WX_VMDQ_2Q_MASK 0x7E
474
475 /****************** Manageablility Host Interface defines ********************/
476 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
477 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
478 #define WX_HIC_HDR_INDEX_MAX 255
479
480 #define FW_READ_SHADOW_RAM_CMD 0x31
481 #define FW_READ_SHADOW_RAM_LEN 0x6
482 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
483 #define FW_NVM_DATA_OFFSET 3
484 #define FW_MAX_READ_BUFFER_SIZE 244
485 #define FW_RESET_CMD 0xDF
486 #define FW_RESET_LEN 0x2
487 #define FW_CEM_HDR_LEN 0x4
488 #define FW_CEM_CMD_RESERVED 0X0
489 #define FW_CEM_MAX_RETRIES 3
490 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
491 #define FW_PPS_SET_CMD 0xF6
492 #define FW_PPS_SET_LEN 0x14
493
494 #define WX_SW_REGION_PTR 0x1C
495
496 #define WX_MAC_STATE_DEFAULT 0x1
497 #define WX_MAC_STATE_MODIFIED 0x2
498 #define WX_MAC_STATE_IN_USE 0x4
499
500 /* BitTimes (BT) conversion */
501 #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
502 #define WX_B2BT(BT) ((BT) * 8)
503
504 /* Calculate Delay to respond to PFC */
505 #define WX_PFC_D 672
506 /* Calculate Cable Delay */
507 #define WX_CABLE_DC 5556 /* Delay Copper */
508 /* Calculate Delay incurred from higher layer */
509 #define WX_HD 6144
510
511 /* Calculate Interface Delay */
512 #define WX_PHY_D 12800
513 #define WX_MAC_D 4096
514 #define WX_XAUI_D (2 * 1024)
515 #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D)
516 /* Calculate PCI Bus delay for low thresholds */
517 #define WX_PCI_DELAY 10000
518
519 /* Calculate delay value in bit times */
520 #define WX_DV(_max_frame_link, _max_frame_tc) \
521 ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \
522 (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \
523 2 * WX_B2BT(_max_frame_tc))
524
525 /* Calculate low threshold delay values */
526 #define WX_LOW_DV(_max_frame_tc) \
527 (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))
528
529 /* flow control */
530 #define WX_DEFAULT_FCPAUSE 0xFFFF
531
532 #define WX_MAX_RXD 8192
533 #define WX_MAX_TXD 8192
534 #define WX_MIN_RXD 128
535 #define WX_MIN_TXD 128
536
537 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */
538 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
539 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
540
541 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
542 #define VMDQ_P(p) ((p) + wx->ring_feature[RING_F_VMDQ].offset)
543
544 /* Supported Rx Buffer Sizes */
545 #define WX_RXBUFFER_256 256 /* Used for skb receive header */
546 #define WX_RXBUFFER_2K 2048
547 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
548
549 #if MAX_SKB_FRAGS < 8
550 #define WX_RX_BUFSZ ALIGN(WX_MAX_RXBUFFER / MAX_SKB_FRAGS, 1024)
551 #else
552 #define WX_RX_BUFSZ WX_RXBUFFER_2K
553 #endif
554
555 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
556
557 #define WX_MAX_DATA_PER_TXD BIT(14)
558 /* Tx Descriptors needed, worst case */
559 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
560 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
561
562 /******************* Receive Descriptor bit definitions **********************/
563 #define WX_RXD_STAT_DD BIT(0) /* Done */
564 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
565 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
566 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
567 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
568 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
569 #define WX_RXD_STAT_IPV6EX BIT(12) /* IPv6 Dest Header */
570 #define WX_RXD_STAT_TS BIT(14) /* IEEE1588 Time Stamp */
571
572 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
573 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
574 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
575 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
576
577 /* RSS Hash results */
578 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
579 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
580 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
581 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
582 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
583 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
584 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
585
586 #define WX_RSS_L4_TYPES_MASK \
587 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
588 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
589 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
590 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
591 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
592 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
593 /* TUN */
594 #define WX_PTYPE_TUN_IPV4 0x80
595 #define WX_PTYPE_TUN_IPV6 0xC0
596
597 /* PKT for TUN */
598 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
599 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
600 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
601 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
602 /* PKT for !TUN */
603 #define WX_PTYPE_PKT_MAC 0x10
604 #define WX_PTYPE_PKT_IP 0x20
605
606 /* TYP for PKT=mac */
607 #define WX_PTYPE_TYP_MAC 0x01
608 /* TYP for PKT=ip */
609 #define WX_PTYPE_PKT_IPV6 0x08
610 #define WX_PTYPE_TYP_IPFRAG 0x01
611 #define WX_PTYPE_TYP_IP 0x02
612 #define WX_PTYPE_TYP_UDP 0x03
613 #define WX_PTYPE_TYP_TCP 0x04
614 #define WX_PTYPE_TYP_SCTP 0x05
615
616 /* Packet type non-ip values */
617 enum wx_l2_ptypes {
618 WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC),
619 WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC),
620
621 WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG),
622 WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP),
623 WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP),
624 WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP),
625 WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP),
626 WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
627 WX_PTYPE_TYP_IPFRAG),
628 WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
629 WX_PTYPE_TYP_IP),
630 WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
631 WX_PTYPE_TYP_UDP),
632 WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
633 WX_PTYPE_TYP_TCP),
634 WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
635 WX_PTYPE_TYP_SCTP),
636
637 WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM),
638 WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM),
639 };
640
641 #define WX_PTYPE_PKT(_pt) ((_pt) & 0x30)
642 #define WX_PTYPE_TYPL4(_pt) ((_pt) & 0x07)
643
644 #define WX_RXD_PKTTYPE(_rxd) \
645 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
646 /*********************** Transmit Descriptor Config Masks ****************/
647 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
648 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
649 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
650 #define WX_TXD_EOP BIT(24) /* End of Packet */
651 #define WX_TXD_IFCS BIT(25) /* Insert FCS */
652 #define WX_TXD_RS BIT(27) /* Report Status */
653
654 /*********************** Adv Transmit Descriptor Config Masks ****************/
655 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
656 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
657 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
658 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
659 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
660 #define WX_TXD_CC BIT(7) /* Check Context */
661 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
662 #define WX_TXD_L4CS BIT(9)
663 #define WX_TXD_IIPCS BIT(10)
664 #define WX_TXD_EIPCS BIT(11)
665 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
666 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
667 #define WX_TXD_TAG_TPID_SEL_SHIFT 11
668
669 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
670 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
671
672 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
673 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
674 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
675 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
676 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
677
678 enum wx_tx_flags {
679 /* cmd_type flags */
680 WX_TX_FLAGS_HW_VLAN = 0x01,
681 WX_TX_FLAGS_TSO = 0x02,
682 WX_TX_FLAGS_TSTAMP = 0x04,
683
684 /* olinfo flags */
685 WX_TX_FLAGS_CC = 0x08,
686 WX_TX_FLAGS_IPV4 = 0x10,
687 WX_TX_FLAGS_CSUM = 0x20,
688 WX_TX_FLAGS_OUTER_IPV4 = 0x100,
689 WX_TX_FLAGS_LINKSEC = 0x200,
690 WX_TX_FLAGS_IPSEC = 0x400,
691
692 /* software defined flags */
693 WX_TX_FLAGS_SW_VLAN = 0x40,
694 };
695
696 /* VLAN info */
697 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
698 #define WX_TX_FLAGS_VLAN_SHIFT 16
699
700 /* wx_dec_ptype.mac: outer mac */
701 enum wx_dec_ptype_mac {
702 WX_DEC_PTYPE_MAC_IP = 0,
703 WX_DEC_PTYPE_MAC_L2 = 2,
704 WX_DEC_PTYPE_MAC_FCOE = 3,
705 };
706
707 /* wx_dec_ptype.[e]ip: outer&encaped ip */
708 #define WX_DEC_PTYPE_IP_FRAG 0x4
709 enum wx_dec_ptype_ip {
710 WX_DEC_PTYPE_IP_NONE = 0,
711 WX_DEC_PTYPE_IP_IPV4 = 1,
712 WX_DEC_PTYPE_IP_IPV6 = 2,
713 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
714 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
715 };
716
717 /* wx_dec_ptype.etype: encaped type */
718 enum wx_dec_ptype_etype {
719 WX_DEC_PTYPE_ETYPE_NONE = 0,
720 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
721 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
722 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
723 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
724 };
725
726 /* wx_dec_ptype.proto: payload proto */
727 enum wx_dec_ptype_prot {
728 WX_DEC_PTYPE_PROT_NONE = 0,
729 WX_DEC_PTYPE_PROT_UDP = 1,
730 WX_DEC_PTYPE_PROT_TCP = 2,
731 WX_DEC_PTYPE_PROT_SCTP = 3,
732 WX_DEC_PTYPE_PROT_ICMP = 4,
733 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
734 };
735
736 /* wx_dec_ptype.layer: payload layer */
737 enum wx_dec_ptype_layer {
738 WX_DEC_PTYPE_LAYER_NONE = 0,
739 WX_DEC_PTYPE_LAYER_PAY2 = 1,
740 WX_DEC_PTYPE_LAYER_PAY3 = 2,
741 WX_DEC_PTYPE_LAYER_PAY4 = 3,
742 };
743
744 struct wx_dec_ptype {
745 u32 known:1;
746 u32 mac:2; /* outer mac */
747 u32 ip:3; /* outer ip*/
748 u32 etype:3; /* encaped type */
749 u32 eip:3; /* encaped ip */
750 u32 prot:4; /* payload proto */
751 u32 layer:3; /* payload layer */
752 };
753
754 /* macro to make the table lines short */
755 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
756 {1, \
757 WX_DEC_PTYPE_MAC_##mac, /* mac */\
758 WX_DEC_PTYPE_IP_##ip, /* ip */ \
759 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
760 WX_DEC_PTYPE_IP_##eip, /* eip */\
761 WX_DEC_PTYPE_PROT_##proto, /* proto */\
762 WX_DEC_PTYPE_LAYER_##layer /* layer */}
763
764 /* Host Interface Command Structures */
765 struct wx_hic_hdr {
766 u8 cmd;
767 u8 buf_len;
768 union {
769 u8 cmd_resv;
770 u8 ret_status;
771 } cmd_or_resp;
772 union {
773 u8 checksum;
774 u8 index;
775 };
776 };
777
778 struct wx_hic_hdr2_req {
779 u8 cmd;
780 u8 buf_lenh;
781 u8 buf_lenl;
782 union {
783 u8 checksum;
784 u8 index;
785 };
786 };
787
788 struct wx_hic_hdr2_rsp {
789 u8 cmd;
790 u8 buf_lenl;
791 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
792 union {
793 u8 checksum;
794 u8 index;
795 };
796 };
797
798 union wx_hic_hdr2 {
799 struct wx_hic_hdr2_req req;
800 struct wx_hic_hdr2_rsp rsp;
801 };
802
803 /* These need to be dword aligned */
804 struct wx_hic_read_shadow_ram {
805 union wx_hic_hdr2 hdr;
806 u32 address;
807 u16 length;
808 u16 pad2;
809 u16 data;
810 u16 pad3;
811 };
812
813 struct wx_hic_reset {
814 struct wx_hic_hdr hdr;
815 u16 lan_id;
816 u16 reset_type;
817 };
818
819 struct wx_hic_set_pps {
820 struct wx_hic_hdr hdr;
821 u8 lan_id;
822 u8 enable;
823 u16 pad2;
824 u64 nsec;
825 u64 cycles;
826 };
827
828 /* Bus parameters */
829 struct wx_bus_info {
830 u8 func;
831 u16 device;
832 };
833
834 struct wx_mbx_info {
835 u16 size;
836 u32 mailbox;
837 u32 udelay;
838 u32 timeout;
839 /* lock mbx access */
840 spinlock_t mbx_lock;
841 };
842
843 struct wx_thermal_sensor_data {
844 s16 temp;
845 s16 alarm_thresh;
846 s16 dalarm_thresh;
847 };
848
849 enum wx_mac_type {
850 wx_mac_unknown = 0,
851 wx_mac_sp,
852 wx_mac_em,
853 wx_mac_aml,
854 wx_mac_aml40,
855 };
856
857 enum wx_media_type {
858 wx_media_unknown = 0,
859 wx_media_fiber,
860 wx_media_copper,
861 wx_media_backplane
862 };
863
864 enum em_mac_type {
865 em_mac_type_unknown = 0,
866 em_mac_type_mdi,
867 em_mac_type_rgmii
868 };
869
870 struct wx_mac_info {
871 enum wx_mac_type type;
872 bool set_lben;
873 u8 addr[ETH_ALEN];
874 u8 perm_addr[ETH_ALEN];
875 u32 mta_shadow[128];
876 s32 mc_filter_type;
877 u32 mcft_size;
878 u32 vft_shadow[128];
879 u32 vft_size;
880 u32 num_rar_entries;
881 u32 rx_pb_size;
882 u32 tx_pb_size;
883 u32 max_tx_queues;
884 u32 max_rx_queues;
885
886 u16 max_msix_vectors;
887 struct wx_thermal_sensor_data sensor;
888 };
889
890 enum wx_eeprom_type {
891 wx_eeprom_uninitialized = 0,
892 wx_eeprom_spi,
893 wx_flash,
894 wx_eeprom_none /* No NVM support */
895 };
896
897 struct wx_eeprom_info {
898 enum wx_eeprom_type type;
899 u32 semaphore_delay;
900 u16 word_size;
901 u16 sw_region_offset;
902 };
903
904 struct wx_addr_filter_info {
905 u32 num_mc_addrs;
906 u32 mta_in_use;
907 bool user_set_promisc;
908 };
909
910 struct wx_mac_addr {
911 u8 addr[ETH_ALEN];
912 u16 state; /* bitmask */
913 u64 pools;
914 };
915
916 enum wx_reset_type {
917 WX_LAN_RESET = 0,
918 WX_SW_RESET,
919 WX_GLOBAL_RESET
920 };
921
922 struct wx_cb {
923 dma_addr_t dma;
924 u16 append_cnt; /* number of skb's appended */
925 bool dma_released;
926 };
927
928 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
929
930 /* Transmit Descriptor */
931 union wx_tx_desc {
932 struct {
933 __le64 buffer_addr; /* Address of descriptor's data buf */
934 __le32 cmd_type_len;
935 __le32 olinfo_status;
936 } read;
937 struct {
938 __le64 rsvd; /* Reserved */
939 __le32 nxtseq_seed;
940 __le32 status;
941 } wb;
942 };
943
944 /* Receive Descriptor */
945 union wx_rx_desc {
946 struct {
947 __le64 pkt_addr; /* Packet buffer address */
948 __le64 hdr_addr; /* Header buffer address */
949 } read;
950 struct {
951 struct {
952 union {
953 __le32 data;
954 struct {
955 __le16 pkt_info; /* RSS, Pkt type */
956 __le16 hdr_info; /* Splithdr, hdrlen */
957 } hs_rss;
958 } lo_dword;
959 union {
960 __le32 rss; /* RSS Hash */
961 struct {
962 __le16 ip_id; /* IP id */
963 __le16 csum; /* Packet Checksum */
964 } csum_ip;
965 } hi_dword;
966 } lower;
967 struct {
968 __le32 status_error; /* ext status/error */
969 __le16 length; /* Packet length */
970 __le16 vlan; /* VLAN tag */
971 } upper;
972 } wb; /* writeback */
973 };
974
975 struct wx_tx_context_desc {
976 __le32 vlan_macip_lens;
977 __le32 seqnum_seed;
978 __le32 type_tucmd_mlhl;
979 __le32 mss_l4len_idx;
980 };
981
982 /* if _flag is in _input, return _result */
983 #define WX_SET_FLAG(_input, _flag, _result) \
984 (((_flag) <= (_result)) ? \
985 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
986 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
987
988 #define WX_RX_DESC(R, i) \
989 (&(((union wx_rx_desc *)((R)->desc))[i]))
990 #define WX_TX_DESC(R, i) \
991 (&(((union wx_tx_desc *)((R)->desc))[i]))
992 #define WX_TX_CTXTDESC(R, i) \
993 (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
994
995 /* wrapper around a pointer to a socket buffer,
996 * so a DMA handle can be stored along with the buffer
997 */
998 struct wx_tx_buffer {
999 union wx_tx_desc *next_to_watch;
1000 unsigned long time_stamp;
1001 struct sk_buff *skb;
1002 unsigned int bytecount;
1003 unsigned short gso_segs;
1004 DEFINE_DMA_UNMAP_ADDR(dma);
1005 DEFINE_DMA_UNMAP_LEN(len);
1006 __be16 protocol;
1007 u32 tx_flags;
1008 };
1009
1010 struct wx_rx_buffer {
1011 struct sk_buff *skb;
1012 dma_addr_t dma;
1013 struct page *page;
1014 unsigned int page_offset;
1015 };
1016
1017 struct wx_queue_stats {
1018 u64 packets;
1019 u64 bytes;
1020 };
1021
1022 struct wx_tx_queue_stats {
1023 u64 restart_queue;
1024 u64 tx_busy;
1025 };
1026
1027 struct wx_rx_queue_stats {
1028 u64 non_eop_descs;
1029 u64 csum_good_cnt;
1030 u64 csum_err;
1031 u64 alloc_rx_buff_failed;
1032 };
1033
1034 /* iterator for handling rings in ring container */
1035 #define wx_for_each_ring(posm, headm) \
1036 for (posm = (headm).ring; posm; posm = posm->next)
1037
1038 struct wx_ring_container {
1039 struct wx_ring *ring; /* pointer to linked list of rings */
1040 unsigned int total_bytes; /* total bytes processed this int */
1041 unsigned int total_packets; /* total packets processed this int */
1042 u8 count; /* total number of rings in vector */
1043 u8 itr; /* current ITR setting for ring */
1044 struct dim dim; /* data for net_dim algorithm */
1045 };
1046 struct wx_ring {
1047 struct wx_ring *next; /* pointer to next ring in q_vector */
1048 struct wx_q_vector *q_vector; /* backpointer to host q_vector */
1049 struct net_device *netdev; /* netdev ring belongs to */
1050 struct device *dev; /* device for DMA mapping */
1051 struct page_pool *page_pool;
1052 void *desc; /* descriptor ring memory */
1053 union {
1054 struct wx_tx_buffer *tx_buffer_info;
1055 struct wx_rx_buffer *rx_buffer_info;
1056 };
1057 u8 __iomem *tail;
1058 dma_addr_t dma; /* phys. address of descriptor ring */
1059 unsigned int size; /* length in bytes */
1060
1061 u16 count; /* amount of descriptors */
1062 unsigned long last_rx_timestamp;
1063
1064 u8 queue_index; /* needed for multiqueue queue management */
1065 u8 reg_idx; /* holds the special value that gets
1066 * the hardware register offset
1067 * associated with this ring, which is
1068 * different for DCB and RSS modes
1069 */
1070 u16 next_to_use;
1071 u16 next_to_clean;
1072 union {
1073 u16 next_to_alloc;
1074 struct {
1075 u8 atr_sample_rate;
1076 u8 atr_count;
1077 };
1078 };
1079
1080 struct wx_queue_stats stats;
1081 struct u64_stats_sync syncp;
1082 union {
1083 struct wx_tx_queue_stats tx_stats;
1084 struct wx_rx_queue_stats rx_stats;
1085 };
1086 } ____cacheline_internodealigned_in_smp;
1087
1088 struct wx_q_vector {
1089 struct wx *wx;
1090 int cpu; /* CPU for DCA */
1091 int numa_node;
1092 u16 v_idx; /* index of q_vector within array, also used for
1093 * finding the bit in EICR and friends that
1094 * represents the vector for this ring
1095 */
1096 u16 itr; /* Interrupt throttle rate written to EITR */
1097 struct wx_ring_container rx, tx;
1098 struct napi_struct napi;
1099 struct rcu_head rcu; /* to avoid race with update stats on free */
1100
1101 u16 total_events; /* number of interrupts processed */
1102
1103 char name[IFNAMSIZ + 17];
1104
1105 /* for dynamic allocation of rings associated with this q_vector */
1106 struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
1107 };
1108
1109 struct wx_ring_feature {
1110 u16 limit; /* upper limit on feature indices */
1111 u16 indices; /* current value of indices */
1112 u16 mask; /* Mask used for feature to ring mapping */
1113 u16 offset; /* offset to start of feature */
1114 };
1115
1116 enum wx_ring_f_enum {
1117 RING_F_NONE = 0,
1118 RING_F_VMDQ,
1119 RING_F_RSS,
1120 RING_F_FDIR,
1121 RING_F_ARRAY_SIZE /* must be last in enum set */
1122 };
1123
1124 enum wx_isb_idx {
1125 WX_ISB_HEADER,
1126 WX_ISB_MISC,
1127 WX_ISB_VEC0,
1128 WX_ISB_VEC1,
1129 WX_ISB_MAX
1130 };
1131
1132 struct wx_fc_info {
1133 u32 high_water; /* Flow Ctrl High-water */
1134 u32 low_water; /* Flow Ctrl Low-water */
1135 };
1136
1137 /* Statistics counters collected by the MAC */
1138 struct wx_hw_stats {
1139 u64 gprc;
1140 u64 gptc;
1141 u64 gorc;
1142 u64 gotc;
1143 u64 tpr;
1144 u64 tpt;
1145 u64 bprc;
1146 u64 bptc;
1147 u64 mprc;
1148 u64 mptc;
1149 u64 roc;
1150 u64 ruc;
1151 u64 lxonoffrxc;
1152 u64 lxontxc;
1153 u64 lxofftxc;
1154 u64 o2bgptc;
1155 u64 b2ospc;
1156 u64 o2bspc;
1157 u64 b2ogprc;
1158 u64 rdmdrop;
1159 u64 crcerrs;
1160 u64 rlec;
1161 u64 qmprc;
1162 u64 fdirmatch;
1163 u64 fdirmiss;
1164 };
1165
1166 enum wx_state {
1167 WX_STATE_RESETTING,
1168 WX_STATE_SWFW_BUSY,
1169 WX_STATE_PTP_RUNNING,
1170 WX_STATE_PTP_TX_IN_PROGRESS,
1171 WX_STATE_SERVICE_SCHED,
1172 WX_STATE_NBITS /* must be last */
1173 };
1174
1175 struct vf_data_storage {
1176 struct pci_dev *vfdev;
1177 unsigned char vf_mac_addr[ETH_ALEN];
1178 bool spoofchk_enabled;
1179 bool link_enable;
1180 bool trusted;
1181 int xcast_mode;
1182 unsigned int vf_api;
1183 bool clear_to_send;
1184 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
1185 u16 pf_qos;
1186 bool pf_set_mac;
1187
1188 u16 vf_mc_hashes[WX_MAX_VF_MC_ENTRIES];
1189 u16 num_vf_mc_hashes;
1190 u16 vlan_count;
1191 int link_state;
1192 };
1193
1194 struct vf_macvlans {
1195 struct list_head mvlist;
1196 int vf;
1197 bool free;
1198 bool is_macvlan;
1199 u8 vf_macvlan[ETH_ALEN];
1200 };
1201
1202 #define WX_RSS_FIELD_IPV4_TCP BIT(0)
1203 #define WX_RSS_FIELD_IPV4 BIT(1)
1204 #define WX_RSS_FIELD_IPV4_SCTP BIT(2)
1205 #define WX_RSS_FIELD_IPV6_SCTP BIT(3)
1206 #define WX_RSS_FIELD_IPV6_TCP BIT(4)
1207 #define WX_RSS_FIELD_IPV6 BIT(5)
1208 #define WX_RSS_FIELD_IPV4_UDP BIT(6)
1209 #define WX_RSS_FIELD_IPV6_UDP BIT(7)
1210
1211 struct wx_rss_flow_map {
1212 u8 flow_type;
1213 u32 data;
1214 u8 flag;
1215 };
1216
1217 enum wx_pf_flags {
1218 WX_FLAG_MULTI_64_FUNC,
1219 WX_FLAG_SWFW_RING,
1220 WX_FLAG_VMDQ_ENABLED,
1221 WX_FLAG_VLAN_PROMISC,
1222 WX_FLAG_SRIOV_ENABLED,
1223 WX_FLAG_IRQ_VECTOR_SHARED,
1224 WX_FLAG_FDIR_CAPABLE,
1225 WX_FLAG_FDIR_HASH,
1226 WX_FLAG_FDIR_PERFECT,
1227 WX_FLAG_RSC_CAPABLE,
1228 WX_FLAG_RX_HWTSTAMP_ENABLED,
1229 WX_FLAG_RX_HWTSTAMP_IN_REGISTER,
1230 WX_FLAG_PTP_PPS_ENABLED,
1231 WX_FLAG_NEED_LINK_CONFIG,
1232 WX_FLAG_NEED_SFP_RESET,
1233 WX_FLAG_NEED_UPDATE_LINK,
1234 WX_FLAG_NEED_DO_RESET,
1235 WX_PF_FLAGS_NBITS /* must be last */
1236 };
1237
1238 struct wx {
1239 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1240 DECLARE_BITMAP(state, WX_STATE_NBITS);
1241 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS);
1242
1243 void *priv;
1244 u8 __iomem *hw_addr;
1245 u8 __iomem *b4_addr; /* vf only */
1246 struct pci_dev *pdev;
1247 struct net_device *netdev;
1248 struct wx_bus_info bus;
1249 struct wx_mbx_info mbx;
1250 struct wx_mac_info mac;
1251 enum em_mac_type mac_type;
1252 enum wx_media_type media_type;
1253 struct wx_eeprom_info eeprom;
1254 struct wx_addr_filter_info addr_ctrl;
1255 struct wx_fc_info fc;
1256 struct wx_mac_addr *mac_table;
1257 u16 device_id;
1258 u16 vendor_id;
1259 u16 subsystem_device_id;
1260 u16 subsystem_vendor_id;
1261 u8 revision_id;
1262 u16 oem_ssid;
1263 u16 oem_svid;
1264 u16 msg_enable;
1265 bool adapter_stopped;
1266 u16 tpid[8];
1267 char eeprom_id[32];
1268 char *driver_name;
1269 enum wx_reset_type reset_type;
1270 u8 swfw_index;
1271
1272 /* PHY stuff */
1273 bool notify_down;
1274 int adv_speed;
1275 int adv_duplex;
1276 unsigned int link;
1277 int speed;
1278 int duplex;
1279 struct phy_device *phydev;
1280 struct phylink *phylink;
1281 struct phylink_config phylink_config;
1282
1283 bool wol_hw_supported;
1284 bool ncsi_enabled;
1285 bool gpio_ctrl;
1286 raw_spinlock_t gpio_lock;
1287
1288 /* Tx fast path data */
1289 int num_tx_queues;
1290 u16 tx_itr_setting;
1291 u16 tx_work_limit;
1292
1293 /* Rx fast path data */
1294 int num_rx_queues;
1295 u16 rx_itr_setting;
1296 u16 rx_work_limit;
1297 bool adaptive_itr;
1298
1299 int num_q_vectors; /* current number of q_vectors for device */
1300 int max_q_vectors; /* upper limit of q_vectors for device */
1301
1302 u32 tx_ring_count;
1303 u32 rx_ring_count;
1304
1305 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
1306 struct wx_ring *rx_ring[64];
1307 struct wx_q_vector *q_vector[64];
1308 int num_rx_pools;
1309 int num_rx_queues_per_pool;
1310
1311 unsigned int queues_per_pool;
1312 struct msix_entry *msix_q_entries;
1313 struct msix_entry *msix_entry;
1314 struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];
1315
1316 /* misc interrupt status block */
1317 dma_addr_t isb_dma;
1318 u32 *isb_mem;
1319 u32 isb_tag[WX_ISB_MAX];
1320 bool misc_irq_domain;
1321 u32 eims_other;
1322 u32 eims_enable_mask;
1323
1324 #define WX_MAX_RETA_ENTRIES 128
1325 #define WX_RSS_INDIR_TBL_MAX 64
1326 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
1327 u8 rss_flags;
1328 bool rss_enabled;
1329 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
1330 u32 *rss_key;
1331 u32 wol;
1332
1333 u16 bd_number;
1334 bool default_up;
1335
1336 struct wx_hw_stats stats;
1337 u64 tx_busy;
1338 u64 non_eop_descs;
1339 u64 restart_queue;
1340 u64 hw_csum_rx_good;
1341 u64 hw_csum_rx_error;
1342 u64 alloc_rx_buff_failed;
1343 unsigned int num_vfs;
1344 struct vf_data_storage *vfinfo;
1345 struct vf_macvlans vf_mvs;
1346 struct vf_macvlans *mv_list;
1347 unsigned long fwd_bitmask;
1348
1349 u32 atr_sample_rate;
1350 void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype);
1351 void (*configure_fdir)(struct wx *wx);
1352 int (*setup_tc)(struct net_device *netdev, u8 tc);
1353 void (*do_reset)(struct net_device *netdev);
1354 int (*ptp_setup_sdp)(struct wx *wx);
1355 void (*set_num_queues)(struct wx *wx);
1356
1357 bool pps_enabled;
1358 u64 pps_width;
1359 u64 pps_edge_start;
1360 u64 pps_edge_end;
1361 u64 sec_to_cc;
1362 u32 base_incval;
1363 u32 tx_hwtstamp_pkts;
1364 u32 tx_hwtstamp_timeouts;
1365 u32 tx_hwtstamp_skipped;
1366 u32 tx_hwtstamp_errors;
1367 u32 rx_hwtstamp_cleared;
1368 unsigned long last_overflow_check;
1369 unsigned long last_rx_ptp_check;
1370 unsigned long ptp_tx_start;
1371 seqlock_t hw_tc_lock; /* seqlock for ptp */
1372 struct cyclecounter hw_cc;
1373 struct timecounter hw_tc;
1374 struct ptp_clock *ptp_clock;
1375 struct ptp_clock_info ptp_caps;
1376 struct kernel_hwtstamp_config tstamp_config;
1377 struct sk_buff *ptp_tx_skb;
1378
1379 struct timer_list service_timer;
1380 struct work_struct service_task;
1381 };
1382
1383 #define WX_INTR_ALL (~0ULL)
1384 #define WX_INTR_Q(i) BIT((i))
1385
1386 /* register operations */
1387 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
1388 #define rd32(a, reg) readl((a)->hw_addr + (reg))
1389 #define rd32a(a, reg, offset) ( \
1390 rd32((a), (reg) + ((offset) << 2)))
1391 #define wr32a(a, reg, off, val) \
1392 wr32((a), (reg) + ((off) << 2), (val))
1393
1394 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)1395 rd32m(struct wx *wx, u32 reg, u32 mask)
1396 {
1397 u32 val;
1398
1399 val = rd32(wx, reg);
1400 return val & mask;
1401 }
1402
1403 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)1404 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
1405 {
1406 u32 val;
1407
1408 val = rd32(wx, reg);
1409 val = ((val & ~mask) | (field & mask));
1410
1411 wr32(wx, reg, val);
1412 }
1413
1414 static inline u64
rd64(struct wx * wx,u32 reg)1415 rd64(struct wx *wx, u32 reg)
1416 {
1417 u64 lsb, msb;
1418
1419 lsb = rd32(wx, reg);
1420 msb = rd32(wx, reg + 4);
1421
1422 return (lsb | msb << 32);
1423 }
1424
1425 static inline u32
rd32ptp(struct wx * wx,u32 reg)1426 rd32ptp(struct wx *wx, u32 reg)
1427 {
1428 if (wx->mac.type == wx_mac_em)
1429 return rd32(wx, reg);
1430
1431 return rd32(wx, reg + 0xB500);
1432 }
1433
1434 static inline void
wr32ptp(struct wx * wx,u32 reg,u32 value)1435 wr32ptp(struct wx *wx, u32 reg, u32 value)
1436 {
1437 if (wx->mac.type == wx_mac_em)
1438 return wr32(wx, reg, value);
1439
1440 return wr32(wx, reg + 0xB500, value);
1441 }
1442
1443 /* On some domestic CPU platforms, sometimes IO is not synchronized with
1444 * flushing memory, here use readl() to flush PCI read and write.
1445 */
1446 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
1447
1448 #define wx_err(wx, fmt, arg...) \
1449 dev_err(&(wx)->pdev->dev, fmt, ##arg)
1450
1451 #define wx_dbg(wx, fmt, arg...) \
1452 dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
1453
phylink_to_wx(struct phylink_config * config)1454 static inline struct wx *phylink_to_wx(struct phylink_config *config)
1455 {
1456 return container_of(config, struct wx, phylink_config);
1457 }
1458
wx_set_state_reset(struct wx * wx)1459 static inline int wx_set_state_reset(struct wx *wx)
1460 {
1461 u8 timeout = 50;
1462
1463 while (test_and_set_bit(WX_STATE_RESETTING, wx->state)) {
1464 timeout--;
1465 if (!timeout)
1466 return -EBUSY;
1467
1468 usleep_range(1000, 2000);
1469 }
1470
1471 return 0;
1472 }
1473
1474 #endif /* _WX_TYPE_H_ */
1475