1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/devfreq.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interconnect.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset-controller.h>
17 #include <linux/time.h>
18
19 #include <soc/qcom/ice.h>
20
21 #include <ufs/ufshcd.h>
22 #include <ufs/ufshci.h>
23 #include <ufs/ufs_quirks.h>
24 #include <ufs/unipro.h>
25 #include "ufshcd-pltfrm.h"
26 #include "ufs-qcom.h"
27
28 #define MCQ_QCFGPTR_MASK GENMASK(7, 0)
29 #define MCQ_QCFGPTR_UNIT 0x200
30 #define MCQ_SQATTR_OFFSET(c) \
31 ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT)
32 #define MCQ_QCFG_SIZE 0x40
33
34 enum {
35 TSTBUS_UAWM,
36 TSTBUS_UARM,
37 TSTBUS_TXUC,
38 TSTBUS_RXUC,
39 TSTBUS_DFC,
40 TSTBUS_TRLUT,
41 TSTBUS_TMRLUT,
42 TSTBUS_OCSC,
43 TSTBUS_UTP_HCI,
44 TSTBUS_COMBINED,
45 TSTBUS_WRAPPER,
46 TSTBUS_UNIPRO,
47 TSTBUS_MAX,
48 };
49
50 #define QCOM_UFS_MAX_GEAR 5
51 #define QCOM_UFS_MAX_LANE 2
52
53 enum {
54 MODE_MIN,
55 MODE_PWM,
56 MODE_HS_RA,
57 MODE_HS_RB,
58 MODE_MAX,
59 };
60
61 static const struct __ufs_qcom_bw_table {
62 u32 mem_bw;
63 u32 cfg_bw;
64 } ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
65 [MODE_MIN][0][0] = { 0, 0 }, /* Bandwidth values in KB/s */
66 [MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922, 1000 },
67 [MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844, 1000 },
68 [MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688, 1000 },
69 [MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376, 1000 },
70 [MODE_PWM][UFS_PWM_G5][UFS_LANE_1] = { 14752, 1000 },
71 [MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844, 1000 },
72 [MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688, 1000 },
73 [MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376, 1000 },
74 [MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752, 1000 },
75 [MODE_PWM][UFS_PWM_G5][UFS_LANE_2] = { 29504, 1000 },
76 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796, 1000 },
77 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591, 1000 },
78 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
79 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
80 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
81 [MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591, 1000 },
82 [MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181, 1000 },
83 [MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
84 [MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
85 [MODE_HS_RA][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
86 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422, 1000 },
87 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189, 1000 },
88 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582, 102400 },
89 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200, 204800 },
90 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_1] = { 5836800, 409600 },
91 [MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189, 1000 },
92 [MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378, 1000 },
93 [MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582, 204800 },
94 [MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200, 409600 },
95 [MODE_HS_RB][UFS_HS_G5][UFS_LANE_2] = { 5836800, 819200 },
96 [MODE_MAX][0][0] = { 7643136, 819200 },
97 };
98
99 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
100 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up);
101
rcdev_to_ufs_host(struct reset_controller_dev * rcd)102 static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd)
103 {
104 return container_of(rcd, struct ufs_qcom_host, rcdev);
105 }
106
107 #ifdef CONFIG_SCSI_UFS_CRYPTO
108
ufs_qcom_ice_enable(struct ufs_qcom_host * host)109 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
110 {
111 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
112 qcom_ice_enable(host->ice);
113 }
114
ufs_qcom_ice_init(struct ufs_qcom_host * host)115 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
116 {
117 struct ufs_hba *hba = host->hba;
118 struct device *dev = hba->dev;
119 struct qcom_ice *ice;
120
121 ice = of_qcom_ice_get(dev);
122 if (ice == ERR_PTR(-EOPNOTSUPP)) {
123 dev_warn(dev, "Disabling inline encryption support\n");
124 ice = NULL;
125 }
126
127 if (IS_ERR_OR_NULL(ice))
128 return PTR_ERR_OR_ZERO(ice);
129
130 host->ice = ice;
131 hba->caps |= UFSHCD_CAP_CRYPTO;
132
133 return 0;
134 }
135
ufs_qcom_ice_resume(struct ufs_qcom_host * host)136 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
137 {
138 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
139 return qcom_ice_resume(host->ice);
140
141 return 0;
142 }
143
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)144 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
145 {
146 if (host->hba->caps & UFSHCD_CAP_CRYPTO)
147 return qcom_ice_suspend(host->ice);
148
149 return 0;
150 }
151
ufs_qcom_ice_program_key(struct ufs_hba * hba,const union ufs_crypto_cfg_entry * cfg,int slot)152 static int ufs_qcom_ice_program_key(struct ufs_hba *hba,
153 const union ufs_crypto_cfg_entry *cfg,
154 int slot)
155 {
156 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
157 union ufs_crypto_cap_entry cap;
158 bool config_enable =
159 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE;
160
161 /* Only AES-256-XTS has been tested so far. */
162 cap = hba->crypto_cap_array[cfg->crypto_cap_idx];
163 if (cap.algorithm_id != UFS_CRYPTO_ALG_AES_XTS ||
164 cap.key_size != UFS_CRYPTO_KEY_SIZE_256)
165 return -EOPNOTSUPP;
166
167 if (config_enable)
168 return qcom_ice_program_key(host->ice,
169 QCOM_ICE_CRYPTO_ALG_AES_XTS,
170 QCOM_ICE_CRYPTO_KEY_SIZE_256,
171 cfg->crypto_key,
172 cfg->data_unit_size, slot);
173 else
174 return qcom_ice_evict_key(host->ice, slot);
175 }
176
177 #else
178
179 #define ufs_qcom_ice_program_key NULL
180
ufs_qcom_ice_enable(struct ufs_qcom_host * host)181 static inline void ufs_qcom_ice_enable(struct ufs_qcom_host *host)
182 {
183 }
184
ufs_qcom_ice_init(struct ufs_qcom_host * host)185 static int ufs_qcom_ice_init(struct ufs_qcom_host *host)
186 {
187 return 0;
188 }
189
ufs_qcom_ice_resume(struct ufs_qcom_host * host)190 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
191 {
192 return 0;
193 }
194
ufs_qcom_ice_suspend(struct ufs_qcom_host * host)195 static inline int ufs_qcom_ice_suspend(struct ufs_qcom_host *host)
196 {
197 return 0;
198 }
199 #endif
200
ufs_qcom_disable_lane_clks(struct ufs_qcom_host * host)201 static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
202 {
203 if (!host->is_lane_clks_enabled)
204 return;
205
206 clk_bulk_disable_unprepare(host->num_clks, host->clks);
207
208 host->is_lane_clks_enabled = false;
209 }
210
ufs_qcom_enable_lane_clks(struct ufs_qcom_host * host)211 static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
212 {
213 int err;
214
215 err = clk_bulk_prepare_enable(host->num_clks, host->clks);
216 if (err)
217 return err;
218
219 host->is_lane_clks_enabled = true;
220
221 return 0;
222 }
223
ufs_qcom_init_lane_clks(struct ufs_qcom_host * host)224 static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
225 {
226 int err;
227 struct device *dev = host->hba->dev;
228
229 if (has_acpi_companion(dev))
230 return 0;
231
232 err = devm_clk_bulk_get_all(dev, &host->clks);
233 if (err <= 0)
234 return err;
235
236 host->num_clks = err;
237
238 return 0;
239 }
240
ufs_qcom_check_hibern8(struct ufs_hba * hba)241 static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
242 {
243 int err;
244 u32 tx_fsm_val;
245 unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS);
246
247 do {
248 err = ufshcd_dme_get(hba,
249 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
250 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
251 &tx_fsm_val);
252 if (err || tx_fsm_val == TX_FSM_HIBERN8)
253 break;
254
255 /* sleep for max. 200us */
256 usleep_range(100, 200);
257 } while (time_before(jiffies, timeout));
258
259 /*
260 * we might have scheduled out for long during polling so
261 * check the state again.
262 */
263 if (time_after(jiffies, timeout))
264 err = ufshcd_dme_get(hba,
265 UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE,
266 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
267 &tx_fsm_val);
268
269 if (err) {
270 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n",
271 __func__, err);
272 } else if (tx_fsm_val != TX_FSM_HIBERN8) {
273 err = tx_fsm_val;
274 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n",
275 __func__, err);
276 }
277
278 return err;
279 }
280
ufs_qcom_select_unipro_mode(struct ufs_qcom_host * host)281 static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host)
282 {
283 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1);
284
285 if (host->hw_ver.major >= 0x05)
286 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0);
287 }
288
289 /*
290 * ufs_qcom_host_reset - reset host controller and PHY
291 */
ufs_qcom_host_reset(struct ufs_hba * hba)292 static int ufs_qcom_host_reset(struct ufs_hba *hba)
293 {
294 int ret;
295 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
296 bool reenable_intr;
297
298 if (!host->core_reset)
299 return 0;
300
301 reenable_intr = hba->is_irq_enabled;
302 ufshcd_disable_irq(hba);
303
304 ret = reset_control_assert(host->core_reset);
305 if (ret) {
306 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
307 __func__, ret);
308 return ret;
309 }
310
311 /*
312 * The hardware requirement for delay between assert/deassert
313 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
314 * ~125us (4/32768). To be on the safe side add 200us delay.
315 */
316 usleep_range(200, 210);
317
318 ret = reset_control_deassert(host->core_reset);
319 if (ret) {
320 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",
321 __func__, ret);
322 return ret;
323 }
324
325 usleep_range(1000, 1100);
326
327 if (reenable_intr)
328 ufshcd_enable_irq(hba);
329
330 return 0;
331 }
332
ufs_qcom_get_hs_gear(struct ufs_hba * hba)333 static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
334 {
335 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
336
337 if (host->hw_ver.major >= 0x4)
338 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
339
340 /* Default is HS-G3 */
341 return UFS_HS_G3;
342 }
343
ufs_qcom_power_up_sequence(struct ufs_hba * hba)344 static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
345 {
346 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
347 struct ufs_host_params *host_params = &host->host_params;
348 struct phy *phy = host->generic_phy;
349 enum phy_mode mode;
350 int ret;
351
352 /*
353 * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
354 * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
355 * so that the subsequent power mode change shall stick to Rate-A.
356 */
357 if (host->hw_ver.major == 0x5) {
358 if (host->phy_gear == UFS_HS_G5)
359 host_params->hs_rate = PA_HS_MODE_A;
360 else
361 host_params->hs_rate = PA_HS_MODE_B;
362 }
363
364 mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
365
366 /* Reset UFS Host Controller and PHY */
367 ret = ufs_qcom_host_reset(hba);
368 if (ret)
369 return ret;
370
371 if (phy->power_count) {
372 phy_power_off(phy);
373 phy_exit(phy);
374 }
375
376 /* phy initialization - calibrate the phy */
377 ret = phy_init(phy);
378 if (ret) {
379 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
380 __func__, ret);
381 return ret;
382 }
383
384 ret = phy_set_mode_ext(phy, mode, host->phy_gear);
385 if (ret)
386 goto out_disable_phy;
387
388 /* power on phy - start serdes and phy's power and clocks */
389 ret = phy_power_on(phy);
390 if (ret) {
391 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
392 __func__, ret);
393 goto out_disable_phy;
394 }
395
396 ufs_qcom_select_unipro_mode(host);
397
398 return 0;
399
400 out_disable_phy:
401 phy_exit(phy);
402
403 return ret;
404 }
405
406 /*
407 * The UTP controller has a number of internal clock gating cells (CGCs).
408 * Internal hardware sub-modules within the UTP controller control the CGCs.
409 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
410 * in a specific operation, UTP controller CGCs are by default disabled and
411 * this function enables them (after every UFS link startup) to save some power
412 * leakage.
413 */
ufs_qcom_enable_hw_clk_gating(struct ufs_hba * hba)414 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
415 {
416 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
417 REG_UFS_CFG2);
418
419 /* Ensure that HW clock gating is enabled before next operations */
420 ufshcd_readl(hba, REG_UFS_CFG2);
421 }
422
ufs_qcom_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)423 static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
424 enum ufs_notify_change_status status)
425 {
426 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
427 int err;
428
429 switch (status) {
430 case PRE_CHANGE:
431 err = ufs_qcom_power_up_sequence(hba);
432 if (err)
433 return err;
434
435 /*
436 * The PHY PLL output is the source of tx/rx lane symbol
437 * clocks, hence, enable the lane clocks only after PHY
438 * is initialized.
439 */
440 err = ufs_qcom_enable_lane_clks(host);
441 break;
442 case POST_CHANGE:
443 /* check if UFS PHY moved from DISABLED to HIBERN8 */
444 err = ufs_qcom_check_hibern8(hba);
445 ufs_qcom_enable_hw_clk_gating(hba);
446 ufs_qcom_ice_enable(host);
447 break;
448 default:
449 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status);
450 err = -EINVAL;
451 break;
452 }
453 return err;
454 }
455
456 /**
457 * ufs_qcom_cfg_timers - Configure ufs qcom cfg timers
458 *
459 * @hba: host controller instance
460 * @gear: Current operating gear
461 * @hs: current power mode
462 * @rate: current operating rate (A or B)
463 * @update_link_startup_timer: indicate if link_start ongoing
464 * @is_pre_scale_up: flag to check if pre scale up condition.
465 * Return: zero for success and non-zero in case of a failure.
466 */
ufs_qcom_cfg_timers(struct ufs_hba * hba,u32 gear,u32 hs,u32 rate,bool update_link_startup_timer,bool is_pre_scale_up)467 static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
468 u32 hs, u32 rate, bool update_link_startup_timer,
469 bool is_pre_scale_up)
470 {
471 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
472 struct ufs_clk_info *clki;
473 unsigned long core_clk_rate = 0;
474 u32 core_clk_cycles_per_us;
475
476 /*
477 * UTP controller uses SYS1CLK_1US_REG register for Interrupt
478 * Aggregation logic.
479 * It is mandatory to write SYS1CLK_1US_REG register on UFS host
480 * controller V4.0.0 onwards.
481 */
482 if (host->hw_ver.major < 4 && !ufshcd_is_intr_aggr_allowed(hba))
483 return 0;
484
485 if (gear == 0) {
486 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
487 return -EINVAL;
488 }
489
490 list_for_each_entry(clki, &hba->clk_list_head, list) {
491 if (!strcmp(clki->name, "core_clk")) {
492 if (is_pre_scale_up)
493 core_clk_rate = clki->max_freq;
494 else
495 core_clk_rate = clk_get_rate(clki->clk);
496 break;
497 }
498
499 }
500
501 /* If frequency is smaller than 1MHz, set to 1MHz */
502 if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
503 core_clk_rate = DEFAULT_CLK_RATE_HZ;
504
505 core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
506 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
507 ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
508 /*
509 * make sure above write gets applied before we return from
510 * this function.
511 */
512 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
513 }
514
515 return 0;
516 }
517
ufs_qcom_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)518 static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
519 enum ufs_notify_change_status status)
520 {
521 int err = 0;
522
523 switch (status) {
524 case PRE_CHANGE:
525 if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
526 0, true, false)) {
527 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
528 __func__);
529 return -EINVAL;
530 }
531
532 err = ufs_qcom_set_core_clk_ctrl(hba, true);
533 if (err)
534 dev_err(hba->dev, "cfg core clk ctrl failed\n");
535 /*
536 * Some UFS devices (and may be host) have issues if LCC is
537 * enabled. So we are setting PA_Local_TX_LCC_Enable to 0
538 * before link startup which will make sure that both host
539 * and device TX LCC are disabled once link startup is
540 * completed.
541 */
542 err = ufshcd_disable_host_tx_lcc(hba);
543
544 break;
545 default:
546 break;
547 }
548
549 return err;
550 }
551
ufs_qcom_device_reset_ctrl(struct ufs_hba * hba,bool asserted)552 static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted)
553 {
554 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
555
556 /* reset gpio is optional */
557 if (!host->device_reset)
558 return;
559
560 gpiod_set_value_cansleep(host->device_reset, asserted);
561 }
562
ufs_qcom_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)563 static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
564 enum ufs_notify_change_status status)
565 {
566 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
567 struct phy *phy = host->generic_phy;
568
569 if (status == PRE_CHANGE)
570 return 0;
571
572 if (ufs_qcom_is_link_off(hba)) {
573 /*
574 * Disable the tx/rx lane symbol clocks before PHY is
575 * powered down as the PLL source should be disabled
576 * after downstream clocks are disabled.
577 */
578 ufs_qcom_disable_lane_clks(host);
579 phy_power_off(phy);
580
581 /* reset the connected UFS device during power down */
582 ufs_qcom_device_reset_ctrl(hba, true);
583
584 } else if (!ufs_qcom_is_link_active(hba)) {
585 ufs_qcom_disable_lane_clks(host);
586 }
587
588 return ufs_qcom_ice_suspend(host);
589 }
590
ufs_qcom_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)591 static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
592 {
593 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
594 struct phy *phy = host->generic_phy;
595 int err;
596
597 if (ufs_qcom_is_link_off(hba)) {
598 err = phy_power_on(phy);
599 if (err) {
600 dev_err(hba->dev, "%s: failed PHY power on: %d\n",
601 __func__, err);
602 return err;
603 }
604
605 err = ufs_qcom_enable_lane_clks(host);
606 if (err)
607 return err;
608
609 } else if (!ufs_qcom_is_link_active(hba)) {
610 err = ufs_qcom_enable_lane_clks(host);
611 if (err)
612 return err;
613 }
614
615 return ufs_qcom_ice_resume(host);
616 }
617
ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host * host,bool enable)618 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
619 {
620 if (host->dev_ref_clk_ctrl_mmio &&
621 (enable ^ host->is_dev_ref_clk_enabled)) {
622 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
623
624 if (enable)
625 temp |= host->dev_ref_clk_en_mask;
626 else
627 temp &= ~host->dev_ref_clk_en_mask;
628
629 /*
630 * If we are here to disable this clock it might be immediately
631 * after entering into hibern8 in which case we need to make
632 * sure that device ref_clk is active for specific time after
633 * hibern8 enter.
634 */
635 if (!enable) {
636 unsigned long gating_wait;
637
638 gating_wait = host->hba->dev_info.clk_gating_wait_us;
639 if (!gating_wait) {
640 udelay(1);
641 } else {
642 /*
643 * bRefClkGatingWaitTime defines the minimum
644 * time for which the reference clock is
645 * required by device during transition from
646 * HS-MODE to LS-MODE or HIBERN8 state. Give it
647 * more delay to be on the safe side.
648 */
649 gating_wait += 10;
650 usleep_range(gating_wait, gating_wait + 10);
651 }
652 }
653
654 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
655
656 /*
657 * Make sure the write to ref_clk reaches the destination and
658 * not stored in a Write Buffer (WB).
659 */
660 readl(host->dev_ref_clk_ctrl_mmio);
661
662 /*
663 * If we call hibern8 exit after this, we need to make sure that
664 * device ref_clk is stable for at least 1us before the hibern8
665 * exit command.
666 */
667 if (enable)
668 udelay(1);
669
670 host->is_dev_ref_clk_enabled = enable;
671 }
672 }
673
ufs_qcom_icc_set_bw(struct ufs_qcom_host * host,u32 mem_bw,u32 cfg_bw)674 static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
675 {
676 struct device *dev = host->hba->dev;
677 int ret;
678
679 ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
680 if (ret < 0) {
681 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
682 return ret;
683 }
684
685 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
686 if (ret < 0) {
687 dev_err(dev, "failed to set bandwidth request: %d\n", ret);
688 return ret;
689 }
690
691 return 0;
692 }
693
ufs_qcom_get_bw_table(struct ufs_qcom_host * host)694 static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
695 {
696 struct ufs_pa_layer_attr *p = &host->dev_req_params;
697 int gear = max_t(u32, p->gear_rx, p->gear_tx);
698 int lane = max_t(u32, p->lane_rx, p->lane_tx);
699
700 if (WARN_ONCE(gear > QCOM_UFS_MAX_GEAR,
701 "ICC scaling for UFS Gear (%d) not supported. Using Gear (%d) bandwidth\n",
702 gear, QCOM_UFS_MAX_GEAR))
703 gear = QCOM_UFS_MAX_GEAR;
704
705 if (WARN_ONCE(lane > QCOM_UFS_MAX_LANE,
706 "ICC scaling for UFS Lane (%d) not supported. Using Lane (%d) bandwidth\n",
707 lane, QCOM_UFS_MAX_LANE))
708 lane = QCOM_UFS_MAX_LANE;
709
710 if (ufshcd_is_hs_mode(p)) {
711 if (p->hs_rate == PA_HS_MODE_B)
712 return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
713 else
714 return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
715 } else {
716 return ufs_qcom_bw_table[MODE_PWM][gear][lane];
717 }
718 }
719
ufs_qcom_icc_update_bw(struct ufs_qcom_host * host)720 static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
721 {
722 struct __ufs_qcom_bw_table bw_table;
723
724 bw_table = ufs_qcom_get_bw_table(host);
725
726 return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
727 }
728
ufs_qcom_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)729 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
730 enum ufs_notify_change_status status,
731 struct ufs_pa_layer_attr *dev_max_params,
732 struct ufs_pa_layer_attr *dev_req_params)
733 {
734 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
735 struct ufs_host_params *host_params = &host->host_params;
736 int ret = 0;
737
738 if (!dev_req_params) {
739 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
740 return -EINVAL;
741 }
742
743 switch (status) {
744 case PRE_CHANGE:
745 ret = ufshcd_negotiate_pwr_params(host_params, dev_max_params, dev_req_params);
746 if (ret) {
747 dev_err(hba->dev, "%s: failed to determine capabilities\n",
748 __func__);
749 return ret;
750 }
751
752 /*
753 * During UFS driver probe, always update the PHY gear to match the negotiated
754 * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
755 * the second init can program the optimal PHY settings. This allows one to start
756 * the first init with either the minimum or the maximum support gear.
757 */
758 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
759 /*
760 * Skip REINIT if the negotiated gear matches with the
761 * initial phy_gear. Otherwise, update the phy_gear to
762 * program the optimal gear setting during REINIT.
763 */
764 if (host->phy_gear == dev_req_params->gear_tx)
765 hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
766 else
767 host->phy_gear = dev_req_params->gear_tx;
768 }
769
770 /* enable the device ref clock before changing to HS mode */
771 if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
772 ufshcd_is_hs_mode(dev_req_params))
773 ufs_qcom_dev_ref_clk_ctrl(host, true);
774
775 if (host->hw_ver.major >= 0x4) {
776 ufshcd_dme_configure_adapt(hba,
777 dev_req_params->gear_tx,
778 PA_INITIAL_ADAPT);
779 }
780 break;
781 case POST_CHANGE:
782 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
783 dev_req_params->pwr_rx,
784 dev_req_params->hs_rate, false, false)) {
785 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
786 __func__);
787 /*
788 * we return error code at the end of the routine,
789 * but continue to configure UFS_PHY_TX_LANE_ENABLE
790 * and bus voting as usual
791 */
792 ret = -EINVAL;
793 }
794
795 /* cache the power mode parameters to use internally */
796 memcpy(&host->dev_req_params,
797 dev_req_params, sizeof(*dev_req_params));
798
799 ufs_qcom_icc_update_bw(host);
800
801 /* disable the device ref clock if entered PWM mode */
802 if (ufshcd_is_hs_mode(&hba->pwr_info) &&
803 !ufshcd_is_hs_mode(dev_req_params))
804 ufs_qcom_dev_ref_clk_ctrl(host, false);
805 break;
806 default:
807 ret = -EINVAL;
808 break;
809 }
810
811 return ret;
812 }
813
ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba * hba)814 static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
815 {
816 int err;
817 u32 pa_vs_config_reg1;
818
819 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
820 &pa_vs_config_reg1);
821 if (err)
822 return err;
823
824 /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
825 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
826 (pa_vs_config_reg1 | (1 << 12)));
827 }
828
ufs_qcom_apply_dev_quirks(struct ufs_hba * hba)829 static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
830 {
831 int err = 0;
832
833 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME)
834 err = ufs_qcom_quirk_host_pa_saveconfigtime(hba);
835
836 return err;
837 }
838
839 /* UFS device-specific quirks */
840 static struct ufs_dev_quirk ufs_qcom_dev_fixups[] = {
841 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
842 .model = UFS_ANY_MODEL,
843 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
844 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
845 .model = UFS_ANY_MODEL,
846 .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM },
847 { .wmanufacturerid = UFS_VENDOR_WDC,
848 .model = UFS_ANY_MODEL,
849 .quirk = UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE },
850 {}
851 };
852
ufs_qcom_fixup_dev_quirks(struct ufs_hba * hba)853 static void ufs_qcom_fixup_dev_quirks(struct ufs_hba *hba)
854 {
855 ufshcd_fixup_dev_quirks(hba, ufs_qcom_dev_fixups);
856 }
857
ufs_qcom_get_ufs_hci_version(struct ufs_hba * hba)858 static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba)
859 {
860 return ufshci_version(2, 0);
861 }
862
863 /**
864 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
865 * @hba: host controller instance
866 *
867 * QCOM UFS host controller might have some non standard behaviours (quirks)
868 * than what is specified by UFSHCI specification. Advertise all such
869 * quirks to standard UFS host controller driver so standard takes them into
870 * account.
871 */
ufs_qcom_advertise_quirks(struct ufs_hba * hba)872 static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
873 {
874 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev);
875 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
876
877 if (host->hw_ver.major == 0x2)
878 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION;
879
880 if (host->hw_ver.major > 0x3)
881 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
882
883 if (drvdata && drvdata->quirks)
884 hba->quirks |= drvdata->quirks;
885 }
886
ufs_qcom_set_phy_gear(struct ufs_qcom_host * host)887 static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
888 {
889 struct ufs_host_params *host_params = &host->host_params;
890 u32 val, dev_major;
891
892 /*
893 * Default to powering up the PHY to the max gear possible, which is
894 * backwards compatible with lower gears but not optimal from
895 * a power usage point of view. After device negotiation, if the
896 * gear is lower a reinit will be performed to program the PHY
897 * to the ideal gear for this combo of controller and device.
898 */
899 host->phy_gear = host_params->hs_tx_gear;
900
901 if (host->hw_ver.major < 0x4) {
902 /*
903 * These controllers only have one PHY init sequence,
904 * let's power up the PHY using that (the minimum supported
905 * gear, UFS_HS_G2).
906 */
907 host->phy_gear = UFS_HS_G2;
908 } else if (host->hw_ver.major >= 0x5) {
909 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
910 dev_major = FIELD_GET(UFS_DEV_VER_MAJOR_MASK, val);
911
912 /*
913 * Since the UFS device version is populated, let's remove the
914 * REINIT quirk as the negotiated gear won't change during boot.
915 * So there is no need to do reinit.
916 */
917 if (dev_major != 0x0)
918 host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
919
920 /*
921 * For UFS 3.1 device and older, power up the PHY using HS-G4
922 * PHY gear to save power.
923 */
924 if (dev_major > 0x0 && dev_major < 0x4)
925 host->phy_gear = UFS_HS_G4;
926 }
927 }
928
ufs_qcom_set_host_params(struct ufs_hba * hba)929 static void ufs_qcom_set_host_params(struct ufs_hba *hba)
930 {
931 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
932 struct ufs_host_params *host_params = &host->host_params;
933
934 ufshcd_init_host_params(host_params);
935
936 /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
937 host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
938 }
939
ufs_qcom_set_caps(struct ufs_hba * hba)940 static void ufs_qcom_set_caps(struct ufs_hba *hba)
941 {
942 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
943 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING;
944 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
945 hba->caps |= UFSHCD_CAP_WB_EN;
946 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE;
947 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
948 }
949
950 /**
951 * ufs_qcom_setup_clocks - enables/disable clocks
952 * @hba: host controller instance
953 * @on: If true, enable clocks else disable them.
954 * @status: PRE_CHANGE or POST_CHANGE notify
955 *
956 * Return: 0 on success, non-zero on failure.
957 */
ufs_qcom_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)958 static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
959 enum ufs_notify_change_status status)
960 {
961 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
962
963 /*
964 * In case ufs_qcom_init() is not yet done, simply ignore.
965 * This ufs_qcom_setup_clocks() shall be called from
966 * ufs_qcom_init() after init is done.
967 */
968 if (!host)
969 return 0;
970
971 switch (status) {
972 case PRE_CHANGE:
973 if (on) {
974 ufs_qcom_icc_update_bw(host);
975 } else {
976 if (!ufs_qcom_is_link_active(hba)) {
977 /* disable device ref_clk */
978 ufs_qcom_dev_ref_clk_ctrl(host, false);
979 }
980 }
981 break;
982 case POST_CHANGE:
983 if (on) {
984 /* enable the device ref clock for HS mode*/
985 if (ufshcd_is_hs_mode(&hba->pwr_info))
986 ufs_qcom_dev_ref_clk_ctrl(host, true);
987 } else {
988 ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
989 ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
990 }
991 break;
992 }
993
994 return 0;
995 }
996
997 static int
ufs_qcom_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)998 ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
999 {
1000 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1001
1002 ufs_qcom_assert_reset(host->hba);
1003 /* provide 1ms delay to let the reset pulse propagate. */
1004 usleep_range(1000, 1100);
1005 return 0;
1006 }
1007
1008 static int
ufs_qcom_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)1009 ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
1010 {
1011 struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
1012
1013 ufs_qcom_deassert_reset(host->hba);
1014
1015 /*
1016 * after reset deassertion, phy will need all ref clocks,
1017 * voltage, current to settle down before starting serdes.
1018 */
1019 usleep_range(1000, 1100);
1020 return 0;
1021 }
1022
1023 static const struct reset_control_ops ufs_qcom_reset_ops = {
1024 .assert = ufs_qcom_reset_assert,
1025 .deassert = ufs_qcom_reset_deassert,
1026 };
1027
ufs_qcom_icc_init(struct ufs_qcom_host * host)1028 static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
1029 {
1030 struct device *dev = host->hba->dev;
1031 int ret;
1032
1033 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
1034 if (IS_ERR(host->icc_ddr))
1035 return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
1036 "failed to acquire interconnect path\n");
1037
1038 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
1039 if (IS_ERR(host->icc_cpu))
1040 return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
1041 "failed to acquire interconnect path\n");
1042
1043 /*
1044 * Set Maximum bandwidth vote before initializing the UFS controller and
1045 * device. Ideally, a minimal interconnect vote would suffice for the
1046 * initialization, but a max vote would allow faster initialization.
1047 */
1048 ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
1049 ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
1050 if (ret < 0)
1051 return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
1052
1053 return 0;
1054 }
1055
1056 /**
1057 * ufs_qcom_init - bind phy with controller
1058 * @hba: host controller instance
1059 *
1060 * Binds PHY with controller and powers up PHY enabling clocks
1061 * and regulators.
1062 *
1063 * Return: -EPROBE_DEFER if binding fails, returns negative error
1064 * on phy power up failure and returns zero on success.
1065 */
ufs_qcom_init(struct ufs_hba * hba)1066 static int ufs_qcom_init(struct ufs_hba *hba)
1067 {
1068 int err;
1069 struct device *dev = hba->dev;
1070 struct ufs_qcom_host *host;
1071 struct ufs_clk_info *clki;
1072 const struct ufs_qcom_drvdata *drvdata = of_device_get_match_data(hba->dev);
1073
1074 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
1075 if (!host)
1076 return -ENOMEM;
1077
1078 /* Make a two way bind between the qcom host and the hba */
1079 host->hba = hba;
1080 ufshcd_set_variant(hba, host);
1081
1082 /* Setup the optional reset control of HCI */
1083 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst");
1084 if (IS_ERR(host->core_reset)) {
1085 err = dev_err_probe(dev, PTR_ERR(host->core_reset),
1086 "Failed to get reset control\n");
1087 goto out_variant_clear;
1088 }
1089
1090 /* Fire up the reset controller. Failure here is non-fatal. */
1091 host->rcdev.of_node = dev->of_node;
1092 host->rcdev.ops = &ufs_qcom_reset_ops;
1093 host->rcdev.owner = dev->driver->owner;
1094 host->rcdev.nr_resets = 1;
1095 err = devm_reset_controller_register(dev, &host->rcdev);
1096 if (err)
1097 dev_warn(dev, "Failed to register reset controller\n");
1098
1099 if (!has_acpi_companion(dev)) {
1100 host->generic_phy = devm_phy_get(dev, "ufsphy");
1101 if (IS_ERR(host->generic_phy)) {
1102 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n");
1103 goto out_variant_clear;
1104 }
1105 }
1106
1107 err = ufs_qcom_icc_init(host);
1108 if (err)
1109 goto out_variant_clear;
1110
1111 host->device_reset = devm_gpiod_get_optional(dev, "reset",
1112 GPIOD_OUT_HIGH);
1113 if (IS_ERR(host->device_reset)) {
1114 err = dev_err_probe(dev, PTR_ERR(host->device_reset),
1115 "Failed to acquire device reset gpio\n");
1116 goto out_variant_clear;
1117 }
1118
1119 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
1120 &host->hw_ver.minor, &host->hw_ver.step);
1121
1122 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1;
1123 host->dev_ref_clk_en_mask = BIT(26);
1124
1125 list_for_each_entry(clki, &hba->clk_list_head, list) {
1126 if (!strcmp(clki->name, "core_clk_unipro"))
1127 clki->keep_link_active = true;
1128 }
1129
1130 err = ufs_qcom_init_lane_clks(host);
1131 if (err)
1132 goto out_variant_clear;
1133
1134 ufs_qcom_set_caps(hba);
1135 ufs_qcom_advertise_quirks(hba);
1136 ufs_qcom_set_host_params(hba);
1137 ufs_qcom_set_phy_gear(host);
1138
1139 err = ufs_qcom_ice_init(host);
1140 if (err)
1141 goto out_variant_clear;
1142
1143 ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
1144
1145 ufs_qcom_get_default_testbus_cfg(host);
1146 err = ufs_qcom_testbus_config(host);
1147 if (err)
1148 /* Failure is non-fatal */
1149 dev_warn(dev, "%s: failed to configure the testbus %d\n",
1150 __func__, err);
1151
1152 if (drvdata && drvdata->no_phy_retention)
1153 hba->spm_lvl = UFS_PM_LVL_5;
1154
1155 return 0;
1156
1157 out_variant_clear:
1158 ufshcd_set_variant(hba, NULL);
1159
1160 return err;
1161 }
1162
ufs_qcom_exit(struct ufs_hba * hba)1163 static void ufs_qcom_exit(struct ufs_hba *hba)
1164 {
1165 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1166
1167 ufs_qcom_disable_lane_clks(host);
1168 phy_power_off(host->generic_phy);
1169 phy_exit(host->generic_phy);
1170 }
1171
1172 /**
1173 * ufs_qcom_set_clk_40ns_cycles - Configure 40ns clk cycles
1174 *
1175 * @hba: host controller instance
1176 * @cycles_in_1us: No of cycles in 1us to be configured
1177 *
1178 * Returns error if dme get/set configuration for 40ns fails
1179 * and returns zero on success.
1180 */
ufs_qcom_set_clk_40ns_cycles(struct ufs_hba * hba,u32 cycles_in_1us)1181 static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba,
1182 u32 cycles_in_1us)
1183 {
1184 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1185 u32 cycles_in_40ns;
1186 u32 reg;
1187 int err;
1188
1189 /*
1190 * UFS host controller V4.0.0 onwards needs to program
1191 * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed
1192 * frequency of unipro core clk of UFS host controller.
1193 */
1194 if (host->hw_ver.major < 4)
1195 return 0;
1196
1197 /*
1198 * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not
1199 * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will
1200 * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware
1201 * specification expect to be 16. Hence use exact hardware spec
1202 * mandated value for cycles_in_40ns instead of calculating using
1203 * generic formulae.
1204 */
1205 switch (cycles_in_1us) {
1206 case UNIPRO_CORE_CLK_FREQ_403_MHZ:
1207 cycles_in_40ns = 16;
1208 break;
1209 case UNIPRO_CORE_CLK_FREQ_300_MHZ:
1210 cycles_in_40ns = 12;
1211 break;
1212 case UNIPRO_CORE_CLK_FREQ_201_5_MHZ:
1213 cycles_in_40ns = 8;
1214 break;
1215 case UNIPRO_CORE_CLK_FREQ_150_MHZ:
1216 cycles_in_40ns = 6;
1217 break;
1218 case UNIPRO_CORE_CLK_FREQ_100_MHZ:
1219 cycles_in_40ns = 4;
1220 break;
1221 case UNIPRO_CORE_CLK_FREQ_75_MHZ:
1222 cycles_in_40ns = 3;
1223 break;
1224 case UNIPRO_CORE_CLK_FREQ_37_5_MHZ:
1225 cycles_in_40ns = 2;
1226 break;
1227 default:
1228 dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n",
1229 cycles_in_1us);
1230 return -EINVAL;
1231 }
1232
1233 err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®);
1234 if (err)
1235 return err;
1236
1237 reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK;
1238 reg |= cycles_in_40ns;
1239
1240 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg);
1241 }
1242
ufs_qcom_set_core_clk_ctrl(struct ufs_hba * hba,bool is_scale_up)1243 static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up)
1244 {
1245 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1246 struct list_head *head = &hba->clk_list_head;
1247 struct ufs_clk_info *clki;
1248 u32 cycles_in_1us = 0;
1249 u32 core_clk_ctrl_reg;
1250 int err;
1251
1252 list_for_each_entry(clki, head, list) {
1253 if (!IS_ERR_OR_NULL(clki->clk) &&
1254 !strcmp(clki->name, "core_clk_unipro")) {
1255 if (!clki->max_freq)
1256 cycles_in_1us = 150; /* default for backwards compatibility */
1257 else if (is_scale_up)
1258 cycles_in_1us = ceil(clki->max_freq, (1000 * 1000));
1259 else
1260 cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000));
1261 break;
1262 }
1263 }
1264
1265 err = ufshcd_dme_get(hba,
1266 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1267 &core_clk_ctrl_reg);
1268 if (err)
1269 return err;
1270
1271 /* Bit mask is different for UFS host controller V4.0.0 onwards */
1272 if (host->hw_ver.major >= 4) {
1273 if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us))
1274 return -ERANGE;
1275 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4;
1276 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us);
1277 } else {
1278 if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us))
1279 return -ERANGE;
1280 core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK;
1281 core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us);
1282 }
1283
1284 /* Clear CORE_CLK_DIV_EN */
1285 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1286
1287 err = ufshcd_dme_set(hba,
1288 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1289 core_clk_ctrl_reg);
1290 if (err)
1291 return err;
1292
1293 /* Configure unipro core clk 40ns attribute */
1294 return ufs_qcom_set_clk_40ns_cycles(hba, cycles_in_1us);
1295 }
1296
ufs_qcom_clk_scale_up_pre_change(struct ufs_hba * hba)1297 static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
1298 {
1299 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1300 struct ufs_pa_layer_attr *attr = &host->dev_req_params;
1301 int ret;
1302
1303 ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx,
1304 attr->hs_rate, false, true);
1305 if (ret) {
1306 dev_err(hba->dev, "%s ufs cfg timer failed\n", __func__);
1307 return ret;
1308 }
1309 /* set unipro core clock attributes and clear clock divider */
1310 return ufs_qcom_set_core_clk_ctrl(hba, true);
1311 }
1312
ufs_qcom_clk_scale_up_post_change(struct ufs_hba * hba)1313 static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba)
1314 {
1315 return 0;
1316 }
1317
ufs_qcom_clk_scale_down_pre_change(struct ufs_hba * hba)1318 static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba)
1319 {
1320 int err;
1321 u32 core_clk_ctrl_reg;
1322
1323 err = ufshcd_dme_get(hba,
1324 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1325 &core_clk_ctrl_reg);
1326
1327 /* make sure CORE_CLK_DIV_EN is cleared */
1328 if (!err &&
1329 (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) {
1330 core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
1331 err = ufshcd_dme_set(hba,
1332 UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
1333 core_clk_ctrl_reg);
1334 }
1335
1336 return err;
1337 }
1338
ufs_qcom_clk_scale_down_post_change(struct ufs_hba * hba)1339 static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba)
1340 {
1341 /* set unipro core clock attributes and clear clock divider */
1342 return ufs_qcom_set_core_clk_ctrl(hba, false);
1343 }
1344
ufs_qcom_clk_scale_notify(struct ufs_hba * hba,bool scale_up,enum ufs_notify_change_status status)1345 static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
1346 bool scale_up, enum ufs_notify_change_status status)
1347 {
1348 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1349 int err;
1350
1351 /* check the host controller state before sending hibern8 cmd */
1352 if (!ufshcd_is_hba_active(hba))
1353 return 0;
1354
1355 if (status == PRE_CHANGE) {
1356 err = ufshcd_uic_hibern8_enter(hba);
1357 if (err)
1358 return err;
1359 if (scale_up)
1360 err = ufs_qcom_clk_scale_up_pre_change(hba);
1361 else
1362 err = ufs_qcom_clk_scale_down_pre_change(hba);
1363
1364 if (err) {
1365 ufshcd_uic_hibern8_exit(hba);
1366 return err;
1367 }
1368 } else {
1369 if (scale_up)
1370 err = ufs_qcom_clk_scale_up_post_change(hba);
1371 else
1372 err = ufs_qcom_clk_scale_down_post_change(hba);
1373
1374
1375 if (err) {
1376 ufshcd_uic_hibern8_exit(hba);
1377 return err;
1378 }
1379
1380 ufs_qcom_icc_update_bw(host);
1381 ufshcd_uic_hibern8_exit(hba);
1382 }
1383
1384 return 0;
1385 }
1386
ufs_qcom_enable_test_bus(struct ufs_qcom_host * host)1387 static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
1388 {
1389 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,
1390 UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);
1391 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
1392 }
1393
ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host * host)1394 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
1395 {
1396 /* provide a legal default configuration */
1397 host->testbus.select_major = TSTBUS_UNIPRO;
1398 host->testbus.select_minor = 37;
1399 }
1400
ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host * host)1401 static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host)
1402 {
1403 if (host->testbus.select_major >= TSTBUS_MAX) {
1404 dev_err(host->hba->dev,
1405 "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n",
1406 __func__, host->testbus.select_major);
1407 return false;
1408 }
1409
1410 return true;
1411 }
1412
ufs_qcom_testbus_config(struct ufs_qcom_host * host)1413 int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
1414 {
1415 int reg;
1416 int offset;
1417 u32 mask = TEST_BUS_SUB_SEL_MASK;
1418
1419 if (!host)
1420 return -EINVAL;
1421
1422 if (!ufs_qcom_testbus_cfg_is_ok(host))
1423 return -EPERM;
1424
1425 switch (host->testbus.select_major) {
1426 case TSTBUS_UAWM:
1427 reg = UFS_TEST_BUS_CTRL_0;
1428 offset = 24;
1429 break;
1430 case TSTBUS_UARM:
1431 reg = UFS_TEST_BUS_CTRL_0;
1432 offset = 16;
1433 break;
1434 case TSTBUS_TXUC:
1435 reg = UFS_TEST_BUS_CTRL_0;
1436 offset = 8;
1437 break;
1438 case TSTBUS_RXUC:
1439 reg = UFS_TEST_BUS_CTRL_0;
1440 offset = 0;
1441 break;
1442 case TSTBUS_DFC:
1443 reg = UFS_TEST_BUS_CTRL_1;
1444 offset = 24;
1445 break;
1446 case TSTBUS_TRLUT:
1447 reg = UFS_TEST_BUS_CTRL_1;
1448 offset = 16;
1449 break;
1450 case TSTBUS_TMRLUT:
1451 reg = UFS_TEST_BUS_CTRL_1;
1452 offset = 8;
1453 break;
1454 case TSTBUS_OCSC:
1455 reg = UFS_TEST_BUS_CTRL_1;
1456 offset = 0;
1457 break;
1458 case TSTBUS_WRAPPER:
1459 reg = UFS_TEST_BUS_CTRL_2;
1460 offset = 16;
1461 break;
1462 case TSTBUS_COMBINED:
1463 reg = UFS_TEST_BUS_CTRL_2;
1464 offset = 8;
1465 break;
1466 case TSTBUS_UTP_HCI:
1467 reg = UFS_TEST_BUS_CTRL_2;
1468 offset = 0;
1469 break;
1470 case TSTBUS_UNIPRO:
1471 reg = UFS_UNIPRO_CFG;
1472 offset = 20;
1473 mask = 0xFFF;
1474 break;
1475 /*
1476 * No need for a default case, since
1477 * ufs_qcom_testbus_cfg_is_ok() checks that the configuration
1478 * is legal
1479 */
1480 }
1481 mask <<= offset;
1482 ufshcd_rmwl(host->hba, TEST_BUS_SEL,
1483 (u32)host->testbus.select_major << 19,
1484 REG_UFS_CFG1);
1485 ufshcd_rmwl(host->hba, mask,
1486 (u32)host->testbus.select_minor << offset,
1487 reg);
1488 ufs_qcom_enable_test_bus(host);
1489
1490 return 0;
1491 }
1492
ufs_qcom_dump_dbg_regs(struct ufs_hba * hba)1493 static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
1494 {
1495 u32 reg;
1496 struct ufs_qcom_host *host;
1497
1498 host = ufshcd_get_variant(hba);
1499
1500 ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,
1501 "HCI Vendor Specific Registers ");
1502
1503 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
1504 ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");
1505
1506 reg = ufshcd_readl(hba, REG_UFS_CFG1);
1507 reg |= UTP_DBG_RAMS_EN;
1508 ufshcd_writel(hba, reg, REG_UFS_CFG1);
1509
1510 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
1511 ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");
1512
1513 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
1514 ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");
1515
1516 reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
1517 ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");
1518
1519 /* clear bit 17 - UTP_DBG_RAMS_EN */
1520 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);
1521
1522 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
1523 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");
1524
1525 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
1526 ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");
1527
1528 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
1529 ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");
1530
1531 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
1532 ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");
1533
1534 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
1535 ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");
1536
1537 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
1538 ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");
1539
1540 reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
1541 ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");
1542 }
1543
1544 /**
1545 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1546 * @hba: per-adapter instance
1547 *
1548 * Toggles the (optional) reset line to reset the attached device.
1549 */
ufs_qcom_device_reset(struct ufs_hba * hba)1550 static int ufs_qcom_device_reset(struct ufs_hba *hba)
1551 {
1552 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1553
1554 /* reset gpio is optional */
1555 if (!host->device_reset)
1556 return -EOPNOTSUPP;
1557
1558 /*
1559 * The UFS device shall detect reset pulses of 1us, sleep for 10us to
1560 * be on the safe side.
1561 */
1562 ufs_qcom_device_reset_ctrl(hba, true);
1563 usleep_range(10, 15);
1564
1565 ufs_qcom_device_reset_ctrl(hba, false);
1566 usleep_range(10, 15);
1567
1568 return 0;
1569 }
1570
1571 #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND)
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * d)1572 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1573 struct devfreq_dev_profile *p,
1574 struct devfreq_simple_ondemand_data *d)
1575 {
1576 p->polling_ms = 60;
1577 p->timer = DEVFREQ_TIMER_DELAYED;
1578 d->upthreshold = 70;
1579 d->downdifferential = 5;
1580
1581 hba->clk_scaling.suspend_on_no_request = true;
1582 }
1583 #else
ufs_qcom_config_scaling_param(struct ufs_hba * hba,struct devfreq_dev_profile * p,struct devfreq_simple_ondemand_data * data)1584 static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
1585 struct devfreq_dev_profile *p,
1586 struct devfreq_simple_ondemand_data *data)
1587 {
1588 }
1589 #endif
1590
1591 /* Resources */
1592 static const struct ufshcd_res_info ufs_res_info[RES_MAX] = {
1593 {.name = "ufs_mem",},
1594 {.name = "mcq",},
1595 /* Submission Queue DAO */
1596 {.name = "mcq_sqd",},
1597 /* Submission Queue Interrupt Status */
1598 {.name = "mcq_sqis",},
1599 /* Completion Queue DAO */
1600 {.name = "mcq_cqd",},
1601 /* Completion Queue Interrupt Status */
1602 {.name = "mcq_cqis",},
1603 /* MCQ vendor specific */
1604 {.name = "mcq_vs",},
1605 };
1606
ufs_qcom_mcq_config_resource(struct ufs_hba * hba)1607 static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba)
1608 {
1609 struct platform_device *pdev = to_platform_device(hba->dev);
1610 struct ufshcd_res_info *res;
1611 struct resource *res_mem, *res_mcq;
1612 int i, ret;
1613
1614 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info));
1615
1616 for (i = 0; i < RES_MAX; i++) {
1617 res = &hba->res[i];
1618 res->resource = platform_get_resource_byname(pdev,
1619 IORESOURCE_MEM,
1620 res->name);
1621 if (!res->resource) {
1622 dev_info(hba->dev, "Resource %s not provided\n", res->name);
1623 if (i == RES_UFS)
1624 return -ENODEV;
1625 continue;
1626 } else if (i == RES_UFS) {
1627 res_mem = res->resource;
1628 res->base = hba->mmio_base;
1629 continue;
1630 }
1631
1632 res->base = devm_ioremap_resource(hba->dev, res->resource);
1633 if (IS_ERR(res->base)) {
1634 dev_err(hba->dev, "Failed to map res %s, err=%d\n",
1635 res->name, (int)PTR_ERR(res->base));
1636 ret = PTR_ERR(res->base);
1637 res->base = NULL;
1638 return ret;
1639 }
1640 }
1641
1642 /* MCQ resource provided in DT */
1643 res = &hba->res[RES_MCQ];
1644 /* Bail if MCQ resource is provided */
1645 if (res->base)
1646 goto out;
1647
1648 /* Explicitly allocate MCQ resource from ufs_mem */
1649 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL);
1650 if (!res_mcq)
1651 return -ENOMEM;
1652
1653 res_mcq->start = res_mem->start +
1654 MCQ_SQATTR_OFFSET(hba->mcq_capabilities);
1655 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1;
1656 res_mcq->flags = res_mem->flags;
1657 res_mcq->name = "mcq";
1658
1659 ret = insert_resource(&iomem_resource, res_mcq);
1660 if (ret) {
1661 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n",
1662 ret);
1663 return ret;
1664 }
1665
1666 res->base = devm_ioremap_resource(hba->dev, res_mcq);
1667 if (IS_ERR(res->base)) {
1668 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n",
1669 (int)PTR_ERR(res->base));
1670 ret = PTR_ERR(res->base);
1671 goto ioremap_err;
1672 }
1673
1674 out:
1675 hba->mcq_base = res->base;
1676 return 0;
1677 ioremap_err:
1678 res->base = NULL;
1679 remove_resource(res_mcq);
1680 return ret;
1681 }
1682
ufs_qcom_op_runtime_config(struct ufs_hba * hba)1683 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba)
1684 {
1685 struct ufshcd_res_info *mem_res, *sqdao_res;
1686 struct ufshcd_mcq_opr_info_t *opr;
1687 int i;
1688
1689 mem_res = &hba->res[RES_UFS];
1690 sqdao_res = &hba->res[RES_MCQ_SQD];
1691
1692 if (!mem_res->base || !sqdao_res->base)
1693 return -EINVAL;
1694
1695 for (i = 0; i < OPR_MAX; i++) {
1696 opr = &hba->mcq_opr[i];
1697 opr->offset = sqdao_res->resource->start -
1698 mem_res->resource->start + 0x40 * i;
1699 opr->stride = 0x100;
1700 opr->base = sqdao_res->base + 0x40 * i;
1701 }
1702
1703 return 0;
1704 }
1705
ufs_qcom_get_hba_mac(struct ufs_hba * hba)1706 static int ufs_qcom_get_hba_mac(struct ufs_hba *hba)
1707 {
1708 /* Qualcomm HC supports up to 64 */
1709 return MAX_SUPP_MAC;
1710 }
1711
ufs_qcom_get_outstanding_cqs(struct ufs_hba * hba,unsigned long * ocqs)1712 static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba,
1713 unsigned long *ocqs)
1714 {
1715 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS];
1716
1717 if (!mcq_vs_res->base)
1718 return -EINVAL;
1719
1720 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS);
1721
1722 return 0;
1723 }
1724
ufs_qcom_write_msi_msg(struct msi_desc * desc,struct msi_msg * msg)1725 static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1726 {
1727 struct device *dev = msi_desc_to_dev(desc);
1728 struct ufs_hba *hba = dev_get_drvdata(dev);
1729
1730 ufshcd_mcq_config_esi(hba, msg);
1731 }
1732
ufs_qcom_mcq_esi_handler(int irq,void * data)1733 static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *data)
1734 {
1735 struct msi_desc *desc = data;
1736 struct device *dev = msi_desc_to_dev(desc);
1737 struct ufs_hba *hba = dev_get_drvdata(dev);
1738 u32 id = desc->msi_index;
1739 struct ufs_hw_queue *hwq = &hba->uhq[id];
1740
1741 ufshcd_mcq_write_cqis(hba, 0x1, id);
1742 ufshcd_mcq_poll_cqe_lock(hba, hwq);
1743
1744 return IRQ_HANDLED;
1745 }
1746
ufs_qcom_config_esi(struct ufs_hba * hba)1747 static int ufs_qcom_config_esi(struct ufs_hba *hba)
1748 {
1749 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1750 struct msi_desc *desc;
1751 struct msi_desc *failed_desc = NULL;
1752 int nr_irqs, ret;
1753
1754 if (host->esi_enabled)
1755 return 0;
1756
1757 /*
1758 * 1. We only handle CQs as of now.
1759 * 2. Poll queues do not need ESI.
1760 */
1761 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
1762 ret = platform_device_msi_init_and_alloc_irqs(hba->dev, nr_irqs,
1763 ufs_qcom_write_msi_msg);
1764 if (ret) {
1765 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret);
1766 return ret;
1767 }
1768
1769 msi_lock_descs(hba->dev);
1770 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1771 ret = devm_request_irq(hba->dev, desc->irq,
1772 ufs_qcom_mcq_esi_handler,
1773 IRQF_SHARED, "qcom-mcq-esi", desc);
1774 if (ret) {
1775 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n",
1776 __func__, desc->irq, ret);
1777 failed_desc = desc;
1778 break;
1779 }
1780 }
1781 msi_unlock_descs(hba->dev);
1782
1783 if (ret) {
1784 /* Rewind */
1785 msi_lock_descs(hba->dev);
1786 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) {
1787 if (desc == failed_desc)
1788 break;
1789 devm_free_irq(hba->dev, desc->irq, hba);
1790 }
1791 msi_unlock_descs(hba->dev);
1792 platform_device_msi_free_irqs_all(hba->dev);
1793 } else {
1794 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
1795 host->hw_ver.step == 0)
1796 ufshcd_rmwl(hba, ESI_VEC_MASK,
1797 FIELD_PREP(ESI_VEC_MASK, MAX_ESI_VEC - 1),
1798 REG_UFS_CFG3);
1799 ufshcd_mcq_enable_esi(hba);
1800 host->esi_enabled = true;
1801 }
1802
1803 return ret;
1804 }
1805
1806 /*
1807 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1808 *
1809 * The variant operations configure the necessary controller and PHY
1810 * handshake during initialization.
1811 */
1812 static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
1813 .name = "qcom",
1814 .init = ufs_qcom_init,
1815 .exit = ufs_qcom_exit,
1816 .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version,
1817 .clk_scale_notify = ufs_qcom_clk_scale_notify,
1818 .setup_clocks = ufs_qcom_setup_clocks,
1819 .hce_enable_notify = ufs_qcom_hce_enable_notify,
1820 .link_startup_notify = ufs_qcom_link_startup_notify,
1821 .pwr_change_notify = ufs_qcom_pwr_change_notify,
1822 .apply_dev_quirks = ufs_qcom_apply_dev_quirks,
1823 .fixup_dev_quirks = ufs_qcom_fixup_dev_quirks,
1824 .suspend = ufs_qcom_suspend,
1825 .resume = ufs_qcom_resume,
1826 .dbg_register_dump = ufs_qcom_dump_dbg_regs,
1827 .device_reset = ufs_qcom_device_reset,
1828 .config_scaling_param = ufs_qcom_config_scaling_param,
1829 .program_key = ufs_qcom_ice_program_key,
1830 .mcq_config_resource = ufs_qcom_mcq_config_resource,
1831 .get_hba_mac = ufs_qcom_get_hba_mac,
1832 .op_runtime_config = ufs_qcom_op_runtime_config,
1833 .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs,
1834 .config_esi = ufs_qcom_config_esi,
1835 };
1836
1837 /**
1838 * ufs_qcom_probe - probe routine of the driver
1839 * @pdev: pointer to Platform device handle
1840 *
1841 * Return: zero for success and non-zero for failure.
1842 */
ufs_qcom_probe(struct platform_device * pdev)1843 static int ufs_qcom_probe(struct platform_device *pdev)
1844 {
1845 int err;
1846 struct device *dev = &pdev->dev;
1847
1848 /* Perform generic probe */
1849 err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
1850 if (err)
1851 return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
1852
1853 return 0;
1854 }
1855
1856 /**
1857 * ufs_qcom_remove - set driver_data of the device to NULL
1858 * @pdev: pointer to platform device handle
1859 *
1860 * Always returns 0
1861 */
ufs_qcom_remove(struct platform_device * pdev)1862 static void ufs_qcom_remove(struct platform_device *pdev)
1863 {
1864 struct ufs_hba *hba = platform_get_drvdata(pdev);
1865 struct ufs_qcom_host *host = ufshcd_get_variant(hba);
1866
1867 ufshcd_pltfrm_remove(pdev);
1868 if (host->esi_enabled)
1869 platform_device_msi_free_irqs_all(hba->dev);
1870 }
1871
1872 static const struct ufs_qcom_drvdata ufs_qcom_sm8550_drvdata = {
1873 .quirks = UFSHCD_QUIRK_BROKEN_LSDBS_CAP,
1874 .no_phy_retention = true,
1875 };
1876
1877 static const struct of_device_id ufs_qcom_of_match[] __maybe_unused = {
1878 { .compatible = "qcom,ufshc" },
1879 { .compatible = "qcom,sm8550-ufshc", .data = &ufs_qcom_sm8550_drvdata },
1880 { .compatible = "qcom,sm8650-ufshc", .data = &ufs_qcom_sm8550_drvdata },
1881 {},
1882 };
1883 MODULE_DEVICE_TABLE(of, ufs_qcom_of_match);
1884
1885 #ifdef CONFIG_ACPI
1886 static const struct acpi_device_id ufs_qcom_acpi_match[] = {
1887 { "QCOM24A5" },
1888 { },
1889 };
1890 MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match);
1891 #endif
1892
1893 static const struct dev_pm_ops ufs_qcom_pm_ops = {
1894 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1895 .prepare = ufshcd_suspend_prepare,
1896 .complete = ufshcd_resume_complete,
1897 #ifdef CONFIG_PM_SLEEP
1898 .suspend = ufshcd_system_suspend,
1899 .resume = ufshcd_system_resume,
1900 .freeze = ufshcd_system_freeze,
1901 .restore = ufshcd_system_restore,
1902 .thaw = ufshcd_system_thaw,
1903 #endif
1904 };
1905
1906 static struct platform_driver ufs_qcom_pltform = {
1907 .probe = ufs_qcom_probe,
1908 .remove = ufs_qcom_remove,
1909 .driver = {
1910 .name = "ufshcd-qcom",
1911 .pm = &ufs_qcom_pm_ops,
1912 .of_match_table = of_match_ptr(ufs_qcom_of_match),
1913 .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match),
1914 },
1915 };
1916 module_platform_driver(ufs_qcom_pltform);
1917
1918 MODULE_DESCRIPTION("Qualcomm UFS host controller driver");
1919 MODULE_LICENSE("GPL v2");
1920